diff --git a/common/lsp/BUILD b/common/lsp/BUILD index 062ebc52d..87d7969fe 100644 --- a/common/lsp/BUILD +++ b/common/lsp/BUILD @@ -12,7 +12,7 @@ load("//common/tools:jcxxgen.bzl", "jcxxgen") package( default_applicable_licenses = ["//:license"], default_visibility = [ - "//:__subpackages__", + "//verilog/tools/ls:__subpackages__", ], ) diff --git a/third_party/portable_endian/BUILD b/third_party/portable_endian/BUILD index 6e6785ab2..a4b7c7c64 100644 --- a/third_party/portable_endian/BUILD +++ b/third_party/portable_endian/BUILD @@ -3,5 +3,5 @@ licenses(["unencumbered"]) cc_library( name = "portable_endian", hdrs = ["portable_endian.h"], - visibility = ["//visibility:public"], + visibility = ["//common/util:__pkg__"], ) diff --git a/verilog/analysis/checkers/BUILD b/verilog/analysis/checkers/BUILD index 27b425f36..1b06db65a 100644 --- a/verilog/analysis/checkers/BUILD +++ b/verilog/analysis/checkers/BUILD @@ -29,11 +29,11 @@ cc_library( ":explicit-task-lifetime-rule", ":forbid-consecutive-null-statements-rule", ":forbid-defparam-rule", + ":forbid-negative-array-dim", ":forbidden-anonymous-enums-rule", ":forbidden-anonymous-structs-unions-rule", ":forbidden-macro-rule", ":forbidden-symbol-rule", - ":forbid-negative-array-dim", ":generate-label-prefix-rule", ":generate-label-rule", ":interface-name-style-rule", @@ -1067,8 +1067,8 @@ cc_library( "//common/analysis/matcher:bound-symbol-manager", "//common/text:symbol", "//common/text:syntax-tree-context", - "//verilog/CST:verilog-matchers", "//verilog/CST:statement", + "//verilog/CST:verilog-matchers", "//verilog/analysis:descriptions", "//verilog/analysis:lint-rule-registry", "@com_google_absl//absl/strings", diff --git a/verilog/tools/diff/BUILD b/verilog/tools/diff/BUILD index e217c6ee5..abecc3f57 100644 --- a/verilog/tools/diff/BUILD +++ b/verilog/tools/diff/BUILD @@ -4,6 +4,11 @@ load("//bazel:sh_test_with_runfiles_lib.bzl", "sh_test_with_runfiles_lib") load("//bazel:variables.bzl", "STATIC_EXECUTABLES_FEATURE") +package( + default_applicable_licenses = ["//:license"], + default_visibility = ["//visibility:private"], +) + cc_binary( name = "verible-verilog-diff", srcs = ["verilog_diff.cc"], diff --git a/verilog/tools/formatter/BUILD b/verilog/tools/formatter/BUILD index 04817845f..d1467b389 100644 --- a/verilog/tools/formatter/BUILD +++ b/verilog/tools/formatter/BUILD @@ -4,6 +4,11 @@ load("//bazel:sh_test_with_runfiles_lib.bzl", "sh_test_with_runfiles_lib") load("//bazel:variables.bzl", "STATIC_EXECUTABLES_FEATURE") +package( + default_applicable_licenses = ["//:license"], + default_visibility = ["//visibility:private"], +) + cc_binary( name = "verible-verilog-format", srcs = ["verilog_format.cc"], diff --git a/verilog/tools/lint/BUILD b/verilog/tools/lint/BUILD index b6f3d8b26..dd21e5822 100644 --- a/verilog/tools/lint/BUILD +++ b/verilog/tools/lint/BUILD @@ -1,4 +1,4 @@ -# This package only contains end-to-end tests for the style linter. +# This package contains style linter binary and end-to-end tests it load( ":verilog_style_lint.bzl", @@ -8,6 +8,11 @@ load( load("//bazel:sh_test_with_runfiles_lib.bzl", "sh_test_with_runfiles_lib") load("//bazel:variables.bzl", "STATIC_EXECUTABLES_FEATURE") +package( + default_applicable_licenses = ["//:license"], + default_visibility = ["//visibility:private"], +) + # Integration tests for different flags and configurations # These tests help confirm that rules' cc_libraries are properly alwayslink-ed. # TODO(fangism): re-organize this into structs instead of tuples, diff --git a/verilog/tools/obfuscator/BUILD b/verilog/tools/obfuscator/BUILD index 9d436de10..8a833409e 100644 --- a/verilog/tools/obfuscator/BUILD +++ b/verilog/tools/obfuscator/BUILD @@ -4,6 +4,11 @@ load("//bazel:sh_test_with_runfiles_lib.bzl", "sh_test_with_runfiles_lib") load("//bazel:variables.bzl", "STATIC_EXECUTABLES_FEATURE") +package( + default_applicable_licenses = ["//:license"], + default_visibility = ["//visibility:private"], +) + cc_binary( name = "verible-verilog-obfuscate", srcs = ["verilog_obfuscate.cc"], diff --git a/verilog/tools/preprocessor/BUILD b/verilog/tools/preprocessor/BUILD index 9cb5095dc..89677e331 100644 --- a/verilog/tools/preprocessor/BUILD +++ b/verilog/tools/preprocessor/BUILD @@ -4,6 +4,11 @@ load("//bazel:sh_test_with_runfiles_lib.bzl", "sh_test_with_runfiles_lib") load("//bazel:variables.bzl", "STATIC_EXECUTABLES_FEATURE") +package( + default_applicable_licenses = ["//:license"], + default_visibility = ["//visibility:private"], +) + cc_binary( name = "verible-verilog-preprocessor", srcs = ["verilog_preprocessor.cc"], diff --git a/verilog/tools/project/BUILD b/verilog/tools/project/BUILD index ba31c0ba9..162d6be56 100644 --- a/verilog/tools/project/BUILD +++ b/verilog/tools/project/BUILD @@ -4,6 +4,11 @@ load("//bazel:sh_test_with_runfiles_lib.bzl", "sh_test_with_runfiles_lib") load("//bazel:variables.bzl", "STATIC_EXECUTABLES_FEATURE") +package( + default_applicable_licenses = ["//:license"], + default_visibility = ["//visibility:private"], +) + cc_binary( name = "verible-verilog-project", srcs = ["project_tool.cc"], diff --git a/verilog/tools/syntax/BUILD b/verilog/tools/syntax/BUILD index 213a249e8..fdfcf2075 100644 --- a/verilog/tools/syntax/BUILD +++ b/verilog/tools/syntax/BUILD @@ -3,6 +3,11 @@ load("//bazel:sh_test_with_runfiles_lib.bzl", "sh_test_with_runfiles_lib") load("//bazel:variables.bzl", "STATIC_EXECUTABLES_FEATURE") +package( + default_applicable_licenses = ["//:license"], + default_visibility = ["//visibility:private"], +) + cc_binary( name = "verible-verilog-syntax", srcs = ["verilog_syntax.cc"], diff --git a/verilog/tools/syntax/export_json_examples/BUILD b/verilog/tools/syntax/export_json_examples/BUILD index c3e038297..9ec970aff 100644 --- a/verilog/tools/syntax/export_json_examples/BUILD +++ b/verilog/tools/syntax/export_json_examples/BUILD @@ -1,5 +1,10 @@ load("@rules_python//python:defs.bzl", "py_binary", "py_library", "py_test") +package( + default_applicable_licenses = ["//:license"], + default_visibility = ["//visibility:public"], # public examples +) + py_library( name = "verible-verilog-syntax-py", srcs = ["verible_verilog_syntax.py"],