From 8f33d2d195af23b3969f0f3824f4da1e46495e2d Mon Sep 17 00:00:00 2001 From: Jan Bylicki Date: Tue, 27 Jun 2023 12:24:37 +0200 Subject: [PATCH] formatter_test: Changed test styling to break newlines in strings Signed-off-by: Jan Bylicki --- verilog/formatting/formatter_test.cc | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/verilog/formatting/formatter_test.cc b/verilog/formatting/formatter_test.cc index 83b636fa6..c40d44f5b 100644 --- a/verilog/formatting/formatter_test.cc +++ b/verilog/formatting/formatter_test.cc @@ -15452,11 +15452,17 @@ TEST(FormatterEndToEndTest, AlwaysWrapModuleInstantiation) { {"module foo; bar #(.N(N)) bq (.bus(bus));endmodule\n", // instance parameter and port fits on line "module foo;\n" - " bar #(\n .N(N)\n ) bq (\n .bus(bus)\n );\n" + " bar #(\n" + " .N(N)\n" + " ) bq (\n" + " .bus(bus)\n" + " );\n" "endmodule\n"}, {"module foo; bar bq (.bus(bus));endmodule\n", "module foo;\n" - " bar bq (\n .bus(bus)\n );\n" + " bar bq (\n" + " .bus(bus)\n" + " );\n" "endmodule\n"}, }; FormatStyle style;