From c70fc60c2e17056716f7102e7f7f53a19021ef96 Mon Sep 17 00:00:00 2001
From: Shupei Fan <dymarkfan@outlook.com>
Date: Sun, 3 Nov 2024 14:26:37 +0000
Subject: [PATCH] [nix] add vsrc build support

---
 nix/t1/conversion/sv-to-vcs-simulator.nix      | 18 +++++++++++++++---
 nix/t1/conversion/sv-to-verilator-emulator.nix | 17 +++++++++++++----
 nix/t1/t1.nix                                  |  8 ++++++++
 3 files changed, 36 insertions(+), 7 deletions(-)

diff --git a/nix/t1/conversion/sv-to-vcs-simulator.nix b/nix/t1/conversion/sv-to-vcs-simulator.nix
index edede9231..8c82a9fbb 100644
--- a/nix/t1/conversion/sv-to-vcs-simulator.nix
+++ b/nix/t1/conversion/sv-to-vcs-simulator.nix
@@ -6,8 +6,10 @@
 
 { mainProgram
 , rtl
+, vsrc ? [ ]
 , enableTrace ? false
 , vcsLinkLibs ? [ ]
+, topModule ? null
 }:
 
 assert lib.assertMsg (builtins.typeOf vcsLinkLibs == "list") "vcsLinkLibs should be list of strings";
@@ -22,7 +24,12 @@ stdenv.mkDerivation rec {
   dontPatchELF = true;
   enableCover = true;
 
-  src = rtl;
+  srcs = [
+    rtl
+    vsrc
+  ];
+
+  dontUnpack = true;
 
   vcsArgs = [
     "-sverilog"
@@ -31,8 +38,13 @@ stdenv.mkDerivation rec {
     "-y"
     "$DWBB_DIR/sim_ver"
     "+libext+.v"
-    "-file"
-    "filelist.f"
+    "-F"
+    "${rtl}/filelist.f"
+  ]
+  ++ vsrc
+  ++ lib.optionals (topModule != null) [
+    "-top"
+    topModule
   ]
   ++ lib.optionals enableCover [
     "-cm"
diff --git a/nix/t1/conversion/sv-to-verilator-emulator.nix b/nix/t1/conversion/sv-to-verilator-emulator.nix
index bc719d8a1..751ef9dd1 100644
--- a/nix/t1/conversion/sv-to-verilator-emulator.nix
+++ b/nix/t1/conversion/sv-to-verilator-emulator.nix
@@ -7,8 +7,10 @@
 
 { mainProgram
 , rtl
+, vsrc ? [ ]
 , enableTrace ? false
 , extraVerilatorArgs ? [ ]
+, topModule ? null
 , ...
 }@overrides:
 
@@ -19,15 +21,19 @@ rec {
 
   __noChroot = true;
 
-  src = rtl;
+  srcs = [
+    rtl
+    vsrc
+  ];
+
+  dontUnpack = true;
 
   nativeBuildInputs = [ verilator ];
 
   # zlib is required for Rust to link against
   propagatedBuildInputs = [ zlib ];
 
-  verilatorFilelist = "filelist.f";
-  verilatorTop = "TestBench";
+  verilatorFilelist = "${rtl}/filelist.f";
   verilatorThreads = 8;
   verilatorArgs = [
     "--cc"
@@ -44,8 +50,11 @@ rec {
     "-Wno-lint"
     "-F"
     verilatorFilelist
+  ]
+  ++ vsrc
+  ++ lib.optionals (topModule != null) [
     "--top"
-    verilatorTop
+    topModule
   ]
   ++ extraVerilatorArgs
   ++ lib.optionals enableTrace [
diff --git a/nix/t1/t1.nix b/nix/t1/t1.nix
index 788c43aa3..6cfc08b6e 100644
--- a/nix/t1/t1.nix
+++ b/nix/t1/t1.nix
@@ -115,12 +115,16 @@ forEachTop (topName: generator: innerMostScope: {
 
   verilator-emu = t1Scope.sv-to-verilator-emulator {
     mainProgram = "${topName}-verilated-simulator";
+    topModule = "TestBench";
     rtl = innerMostScope.rtl;
+    vsrc = [ ../../${topName}/vsrc/ClockGen.sv ];
     extraVerilatorArgs = [ "${innerMostScope.verilator-dpi-lib}/lib/libdpi_${topName}.a" ];
   };
   verilator-emu-trace = t1Scope.sv-to-verilator-emulator {
     mainProgram = "${topName}-verilated-trace-simulator";
+    topModule = "TestBench";
     rtl = innerMostScope.rtl;
+    vsrc = [ ../../${topName}/vsrc/ClockGen.sv ];
     enableTrace = true;
     extraVerilatorArgs = [ "${innerMostScope.verilator-dpi-lib-trace}/lib/libdpi_${topName}.a" ];
   };
@@ -147,12 +151,16 @@ forEachTop (topName: generator: innerMostScope: {
 
   vcs-emu = t1Scope.sv-to-vcs-simulator {
     mainProgram = "${topName}-vcs-simulator";
+    topModule = "TestBench";
     rtl = innerMostScope.rtl;
+    vsrc = [ ../../${topName}/vsrc/ClockGen.sv ];
     vcsLinkLibs = [ "${innerMostScope.vcs-dpi-lib}/lib/libdpi_${topName}.a" ];
   };
   vcs-emu-trace = t1Scope.sv-to-vcs-simulator {
     mainProgram = "${topName}-vcs-trace-simulator";
+    topModule = "TestBench";
     rtl = innerMostScope.rtl;
+    vsrc = [ ../../${topName}/vsrc/ClockGen.sv ];
     enableTrace = true;
     vcsLinkLibs = [ "${innerMostScope.vcs-dpi-lib-trace}/lib/libdpi_${topName}.a" ];
   };