From b5f5a8e16d71d28716ef2a155135310f9938888a Mon Sep 17 00:00:00 2001 From: ngc7331 Date: Thu, 31 Oct 2024 11:28:21 +0800 Subject: [PATCH] fix(RVCDecoder): c.addi4spn with imm=0 should be reserved --- src/main/scala/rocket/RVC.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/rocket/RVC.scala b/src/main/scala/rocket/RVC.scala index c9252c086cf..0874a9405fc 100644 --- a/src/main/scala/rocket/RVC.scala +++ b/src/main/scala/rocket/RVC.scala @@ -155,12 +155,12 @@ class RVCDecoder(x: UInt, xLen: Int, fLen: Int, useAddiForMv: Boolean = false) { } def q0_ill = { - def allz = !(x(12, 2).orR) + def immz = !(x(12, 5).orR) def fld = if (fLen >= 64) false.B else true.B def flw32 = if (xLen == 64 || fLen >= 32) false.B else true.B def fsd = if (fLen >= 64) false.B else true.B def fsw32 = if (xLen == 64 || fLen >= 32) false.B else true.B - Seq(allz, fld, false.B, flw32, true.B, fsd, false.B, fsw32) + Seq(immz, fld, false.B, flw32, true.B, fsd, false.B, fsw32) } def q1_ill = {