From 91a6257ca3d6dff1cb83047eff34af2fb8c35995 Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Thu, 28 Mar 2024 20:03:59 -0700 Subject: [PATCH 01/10] Add LMS enable bit, regenerate RDL --- src/integration/rtl/caliptra_reg.h | 2 ++ src/integration/rtl/caliptra_reg_defines.svh | 2 ++ src/soc_ifc/rtl/caliptra_top_reg.h | 2 ++ src/soc_ifc/rtl/caliptra_top_reg_defines.svh | 2 ++ src/soc_ifc/rtl/soc_ifc_external_reg.rdl | 1 + src/soc_ifc/rtl/soc_ifc_reg.sv | 3 ++- src/soc_ifc/rtl/soc_ifc_reg_covergroups.svh | 4 +++- src/soc_ifc/rtl/soc_ifc_reg_pkg.sv | 5 +++++ src/soc_ifc/rtl/soc_ifc_reg_sample.svh | 6 ++++-- src/soc_ifc/rtl/soc_ifc_reg_uvm.sv | 5 +++++ src/soc_ifc/rtl/soc_ifc_top.sv | 2 ++ 11 files changed, 30 insertions(+), 4 deletions(-) diff --git a/src/integration/rtl/caliptra_reg.h b/src/integration/rtl/caliptra_reg.h index b9e942264..a5117e8c8 100644 --- a/src/integration/rtl/caliptra_reg.h +++ b/src/integration/rtl/caliptra_reg.h @@ -5552,6 +5552,8 @@ #define SOC_IFC_REG_CPTRA_HW_CONFIG_I3C_EN_MASK (0x4) #define SOC_IFC_REG_CPTRA_HW_CONFIG_UART_EN_LOW (3) #define SOC_IFC_REG_CPTRA_HW_CONFIG_UART_EN_MASK (0x8) +#define SOC_IFC_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_LOW (4) +#define SOC_IFC_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_MASK (0x10) #define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_EN (0x300300e4) #define SOC_IFC_REG_CPTRA_WDT_TIMER1_EN (0xe4) #define SOC_IFC_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_LOW (0) diff --git a/src/integration/rtl/caliptra_reg_defines.svh b/src/integration/rtl/caliptra_reg_defines.svh index fa35a7f13..ca517ddab 100644 --- a/src/integration/rtl/caliptra_reg_defines.svh +++ b/src/integration/rtl/caliptra_reg_defines.svh @@ -5552,6 +5552,8 @@ `define SOC_IFC_REG_CPTRA_HW_CONFIG_I3C_EN_MASK (32'h4) `define SOC_IFC_REG_CPTRA_HW_CONFIG_UART_EN_LOW (3) `define SOC_IFC_REG_CPTRA_HW_CONFIG_UART_EN_MASK (32'h8) +`define SOC_IFC_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_LOW (4) +`define SOC_IFC_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_MASK (32'h10) `define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_EN (32'h300300e4) `define SOC_IFC_REG_CPTRA_WDT_TIMER1_EN (32'he4) `define SOC_IFC_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_LOW (0) diff --git a/src/soc_ifc/rtl/caliptra_top_reg.h b/src/soc_ifc/rtl/caliptra_top_reg.h index 790b71cb8..89a1738ba 100644 --- a/src/soc_ifc/rtl/caliptra_top_reg.h +++ b/src/soc_ifc/rtl/caliptra_top_reg.h @@ -308,6 +308,8 @@ #define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_I3C_EN_MASK (0x4) #define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_UART_EN_LOW (3) #define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_UART_EN_MASK (0x8) +#define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_LOW (4) +#define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_MASK (0x10) #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN (0x300300e4) #define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN (0xe4) #define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_LOW (0) diff --git a/src/soc_ifc/rtl/caliptra_top_reg_defines.svh b/src/soc_ifc/rtl/caliptra_top_reg_defines.svh index 344d910ea..8d537dd1a 100644 --- a/src/soc_ifc/rtl/caliptra_top_reg_defines.svh +++ b/src/soc_ifc/rtl/caliptra_top_reg_defines.svh @@ -308,6 +308,8 @@ `define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_I3C_EN_MASK (32'h4) `define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_UART_EN_LOW (3) `define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_UART_EN_MASK (32'h8) +`define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_LOW (4) +`define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_MASK (32'h10) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN (32'h300300e4) `define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN (32'he4) `define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_LOW (0) diff --git a/src/soc_ifc/rtl/soc_ifc_external_reg.rdl b/src/soc_ifc/rtl/soc_ifc_external_reg.rdl index c578f11c1..36d1c2a79 100644 --- a/src/soc_ifc/rtl/soc_ifc_external_reg.rdl +++ b/src/soc_ifc/rtl/soc_ifc_external_reg.rdl @@ -327,6 +327,7 @@ reg { field {sw=r; hw=w;} QSPI_en; field {sw=r; hw=w;} I3C_en; field {sw=r; hw=w;} UART_en; + field {sw=r; hw=w;} LMS_acc_en; } CPTRA_HW_CONFIG; //Timer1 diff --git a/src/soc_ifc/rtl/soc_ifc_reg.sv b/src/soc_ifc/rtl/soc_ifc_reg.sv index ddf5a3d80..3789f1e35 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg.sv +++ b/src/soc_ifc/rtl/soc_ifc_reg.sv @@ -5813,7 +5813,8 @@ module soc_ifc_reg ( assign readback_array[56][1:1] = (decoded_reg_strb.CPTRA_HW_CONFIG && !decoded_req_is_wr) ? hwif_in.CPTRA_HW_CONFIG.QSPI_en.next : '0; assign readback_array[56][2:2] = (decoded_reg_strb.CPTRA_HW_CONFIG && !decoded_req_is_wr) ? hwif_in.CPTRA_HW_CONFIG.I3C_en.next : '0; assign readback_array[56][3:3] = (decoded_reg_strb.CPTRA_HW_CONFIG && !decoded_req_is_wr) ? hwif_in.CPTRA_HW_CONFIG.UART_en.next : '0; - assign readback_array[56][31:4] = '0; + assign readback_array[56][4:4] = (decoded_reg_strb.CPTRA_HW_CONFIG && !decoded_req_is_wr) ? hwif_in.CPTRA_HW_CONFIG.LMS_acc_en.next : '0; + assign readback_array[56][31:5] = '0; assign readback_array[57][0:0] = (decoded_reg_strb.CPTRA_WDT_TIMER1_EN && !decoded_req_is_wr) ? field_storage.CPTRA_WDT_TIMER1_EN.timer1_en.value : '0; assign readback_array[57][31:1] = '0; assign readback_array[58][0:0] = (decoded_reg_strb.CPTRA_WDT_TIMER1_CTRL && !decoded_req_is_wr) ? field_storage.CPTRA_WDT_TIMER1_CTRL.timer1_restart.value : '0; diff --git a/src/soc_ifc/rtl/soc_ifc_reg_covergroups.svh b/src/soc_ifc/rtl/soc_ifc_reg_covergroups.svh index 0b835415e..6fc4600d8 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg_covergroups.svh +++ b/src/soc_ifc/rtl/soc_ifc_reg_covergroups.svh @@ -633,13 +633,15 @@ input bit [1-1:0] iTRNG_en, input bit [1-1:0] QSPI_en, input bit [1-1:0] I3C_en, - input bit [1-1:0] UART_en + input bit [1-1:0] UART_en, + input bit [1-1:0] LMS_acc_en ); option.per_instance = 1; iTRNG_en_cp : coverpoint iTRNG_en; QSPI_en_cp : coverpoint QSPI_en; I3C_en_cp : coverpoint I3C_en; UART_en_cp : coverpoint UART_en; + LMS_acc_en_cp : coverpoint LMS_acc_en; endgroup diff --git a/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv b/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv index 5ed0446ca..c5e8a9188 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv +++ b/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv @@ -189,11 +189,16 @@ package soc_ifc_reg_pkg; logic next; } soc_ifc_reg__CPTRA_HW_CONFIG__UART_en__in_t; + typedef struct packed{ + logic next; + } soc_ifc_reg__CPTRA_HW_CONFIG__LMS_acc_en__in_t; + typedef struct packed{ soc_ifc_reg__CPTRA_HW_CONFIG__iTRNG_en__in_t iTRNG_en; soc_ifc_reg__CPTRA_HW_CONFIG__QSPI_en__in_t QSPI_en; soc_ifc_reg__CPTRA_HW_CONFIG__I3C_en__in_t I3C_en; soc_ifc_reg__CPTRA_HW_CONFIG__UART_en__in_t UART_en; + soc_ifc_reg__CPTRA_HW_CONFIG__LMS_acc_en__in_t LMS_acc_en; } soc_ifc_reg__CPTRA_HW_CONFIG__in_t; typedef struct packed{ diff --git a/src/soc_ifc/rtl/soc_ifc_reg_sample.svh b/src/soc_ifc/rtl/soc_ifc_reg_sample.svh index e677131de..7dd9fc4b9 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg_sample.svh +++ b/src/soc_ifc/rtl/soc_ifc_reg_sample.svh @@ -735,9 +735,10 @@ foreach(QSPI_en_bit_cg[bt]) this.QSPI_en_bit_cg[bt].sample(data[1 + bt]); foreach(I3C_en_bit_cg[bt]) this.I3C_en_bit_cg[bt].sample(data[2 + bt]); foreach(UART_en_bit_cg[bt]) this.UART_en_bit_cg[bt].sample(data[3 + bt]); + foreach(LMS_acc_en_bit_cg[bt]) this.LMS_acc_en_bit_cg[bt].sample(data[4 + bt]); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( data[0:0]/*iTRNG_en*/ , data[1:1]/*QSPI_en*/ , data[2:2]/*I3C_en*/ , data[3:3]/*UART_en*/ ); + this.fld_cg.sample( data[0:0]/*iTRNG_en*/ , data[1:1]/*QSPI_en*/ , data[2:2]/*I3C_en*/ , data[3:3]/*UART_en*/ , data[4:4]/*LMS_acc_en*/ ); end endfunction @@ -747,9 +748,10 @@ foreach(QSPI_en_bit_cg[bt]) this.QSPI_en_bit_cg[bt].sample(QSPI_en.get_mirrored_value() >> bt); foreach(I3C_en_bit_cg[bt]) this.I3C_en_bit_cg[bt].sample(I3C_en.get_mirrored_value() >> bt); foreach(UART_en_bit_cg[bt]) this.UART_en_bit_cg[bt].sample(UART_en.get_mirrored_value() >> bt); + foreach(LMS_acc_en_bit_cg[bt]) this.LMS_acc_en_bit_cg[bt].sample(LMS_acc_en.get_mirrored_value() >> bt); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( iTRNG_en.get_mirrored_value() , QSPI_en.get_mirrored_value() , I3C_en.get_mirrored_value() , UART_en.get_mirrored_value() ); + this.fld_cg.sample( iTRNG_en.get_mirrored_value() , QSPI_en.get_mirrored_value() , I3C_en.get_mirrored_value() , UART_en.get_mirrored_value() , LMS_acc_en.get_mirrored_value() ); end endfunction diff --git a/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv b/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv index 249f71bb5..eb8b4ddd8 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv +++ b/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv @@ -904,11 +904,13 @@ package soc_ifc_reg_uvm; soc_ifc_reg__CPTRA_HW_CONFIG_bit_cg QSPI_en_bit_cg[1]; soc_ifc_reg__CPTRA_HW_CONFIG_bit_cg I3C_en_bit_cg[1]; soc_ifc_reg__CPTRA_HW_CONFIG_bit_cg UART_en_bit_cg[1]; + soc_ifc_reg__CPTRA_HW_CONFIG_bit_cg LMS_acc_en_bit_cg[1]; soc_ifc_reg__CPTRA_HW_CONFIG_fld_cg fld_cg; rand uvm_reg_field iTRNG_en; rand uvm_reg_field QSPI_en; rand uvm_reg_field I3C_en; rand uvm_reg_field UART_en; + rand uvm_reg_field LMS_acc_en; function new(string name = "soc_ifc_reg__CPTRA_HW_CONFIG"); super.new(name, 32, build_coverage(UVM_CVR_ALL)); @@ -928,11 +930,14 @@ package soc_ifc_reg_uvm; this.I3C_en.configure(this, 1, 2, "RO", 1, 'h0, 0, 1, 0); this.UART_en = new("UART_en"); this.UART_en.configure(this, 1, 3, "RO", 1, 'h0, 0, 1, 0); + this.LMS_acc_en = new("LMS_acc_en"); + this.LMS_acc_en.configure(this, 1, 4, "RO", 1, 'h0, 0, 1, 0); if (has_coverage(UVM_CVR_REG_BITS)) begin foreach(iTRNG_en_bit_cg[bt]) iTRNG_en_bit_cg[bt] = new(); foreach(QSPI_en_bit_cg[bt]) QSPI_en_bit_cg[bt] = new(); foreach(I3C_en_bit_cg[bt]) I3C_en_bit_cg[bt] = new(); foreach(UART_en_bit_cg[bt]) UART_en_bit_cg[bt] = new(); + foreach(LMS_acc_en_bit_cg[bt]) LMS_acc_en_bit_cg[bt] = new(); end if (has_coverage(UVM_CVR_FIELD_VALS)) fld_cg = new(); diff --git a/src/soc_ifc/rtl/soc_ifc_top.sv b/src/soc_ifc/rtl/soc_ifc_top.sv index 28350fad0..df9f8a223 100644 --- a/src/soc_ifc/rtl/soc_ifc_top.sv +++ b/src/soc_ifc/rtl/soc_ifc_top.sv @@ -412,6 +412,8 @@ always_comb soc_ifc_reg_hwif_in.CPTRA_HW_CONFIG.UART_en.next = 1'b1; `else always_comb soc_ifc_reg_hwif_in.CPTRA_HW_CONFIG.UART_en.next = 1'b0; `endif +// Hardcoded because all future revs will have LMS accelerator available +always_comb soc_ifc_reg_hwif_in.CPTRA_HW_CONFIG.LMS_acc_en.next = 1'b1; //SOC Stepping ID update always_comb begin From 835335ec0032ee13fd3295454cb04707653b1c17 Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Tue, 2 Apr 2024 13:10:01 -0700 Subject: [PATCH 02/10] Update rev id for 1.1, updated bit-map description --- src/soc_ifc/rtl/soc_ifc_external_reg.rdl | 6 +++++- src/soc_ifc/rtl/soc_ifc_reg.sv | 2 +- src/soc_ifc/rtl/soc_ifc_reg_uvm.sv | 2 +- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/src/soc_ifc/rtl/soc_ifc_external_reg.rdl b/src/soc_ifc/rtl/soc_ifc_external_reg.rdl index 36d1c2a79..cb4df8fb1 100644 --- a/src/soc_ifc/rtl/soc_ifc_external_reg.rdl +++ b/src/soc_ifc/rtl/soc_ifc_external_reg.rdl @@ -307,7 +307,11 @@ reg { SoC stepping ID is repopulated with the value in the fuse register on every warm reset [br]Caliptra Access: RO [br]SOC Access: RO"; - field {sw=r; resetsignal = cptra_rst_b;} CPTRA_GENERATION[16]=1; + field {desc = "Caliptra official release version. Bit field encoding is: + [br][lb]15:8[rb] Patch version + [br][lb] 7:4[rb] Minor version + [br][lb] 3:0[rb] Major version"; + sw=r; resetsignal = cptra_rst_b;} CPTRA_GENERATION[16]=0x0011; field {sw=r; hw=w; resetsignal = cptra_rst_b;} SOC_STEPPING_ID[16]=0; } CPTRA_HW_REV_ID; reg { diff --git a/src/soc_ifc/rtl/soc_ifc_reg.sv b/src/soc_ifc/rtl/soc_ifc_reg.sv index 3789f1e35..cd90345bf 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg.sv +++ b/src/soc_ifc/rtl/soc_ifc_reg.sv @@ -5804,7 +5804,7 @@ module soc_ifc_reg ( for(genvar i0=0; i0<2; i0++) begin assign readback_array[i0*1 + 51][31:0] = (decoded_reg_strb.CPTRA_GENERIC_OUTPUT_WIRES[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_GENERIC_OUTPUT_WIRES[i0].generic_wires.value : '0; end - assign readback_array[53][15:0] = (decoded_reg_strb.CPTRA_HW_REV_ID && !decoded_req_is_wr) ? 16'h1 : '0; + assign readback_array[53][15:0] = (decoded_reg_strb.CPTRA_HW_REV_ID && !decoded_req_is_wr) ? 16'h11 : '0; assign readback_array[53][31:16] = (decoded_reg_strb.CPTRA_HW_REV_ID && !decoded_req_is_wr) ? hwif_in.CPTRA_HW_REV_ID.SOC_STEPPING_ID.next : '0; for(genvar i0=0; i0<2; i0++) begin assign readback_array[i0*1 + 54][31:0] = (decoded_reg_strb.CPTRA_FW_REV_ID[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_FW_REV_ID[i0].REV_ID.value : '0; diff --git a/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv b/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv index eb8b4ddd8..fcd827b09 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv +++ b/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv @@ -852,7 +852,7 @@ package soc_ifc_reg_uvm; virtual function void build(); this.CPTRA_GENERATION = new("CPTRA_GENERATION"); - this.CPTRA_GENERATION.configure(this, 16, 0, "RO", 0, 'h1, 1, 1, 0); + this.CPTRA_GENERATION.configure(this, 16, 0, "RO", 0, 'h11, 1, 1, 0); this.SOC_STEPPING_ID = new("SOC_STEPPING_ID"); this.SOC_STEPPING_ID.configure(this, 16, 16, "RO", 1, 'h0, 1, 1, 0); if (has_coverage(UVM_CVR_REG_BITS)) begin From f1033e1201d9fceb2e178d822fc9050a0f5f4b2d Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Wed, 3 Apr 2024 09:56:05 -0700 Subject: [PATCH 03/10] Add smoke test to validate hw config regs, plus Makefile build options --- .../smoke_test_hw_config/caliptra_isr.h | 193 ++++++++++++++++++ .../smoke_test_hw_config.c | 147 +++++++++++++ .../smoke_test_hw_config.yml | 17 ++ tools/scripts/Makefile | 30 ++- 4 files changed, 385 insertions(+), 2 deletions(-) create mode 100644 src/integration/test_suites/smoke_test_hw_config/caliptra_isr.h create mode 100644 src/integration/test_suites/smoke_test_hw_config/smoke_test_hw_config.c create mode 100755 src/integration/test_suites/smoke_test_hw_config/smoke_test_hw_config.yml diff --git a/src/integration/test_suites/smoke_test_hw_config/caliptra_isr.h b/src/integration/test_suites/smoke_test_hw_config/caliptra_isr.h new file mode 100644 index 000000000..7bf456414 --- /dev/null +++ b/src/integration/test_suites/smoke_test_hw_config/caliptra_isr.h @@ -0,0 +1,193 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// --------------------------------------------------------------------- +// File: caliptra_isr.h +// Description: +// Provides function declarations for use by external test files, so +// that the ISR functionality may behave like a library. +// TODO: +// This header file includes inline function definitions for event and +// test specific interrupt service behavior, so it should be copied and +// modified for each test. +// --------------------------------------------------------------------- + +#ifndef CALIPTRA_ISR_H + #define CALIPTRA_ISR_H + +#include "caliptra_reg.h" +#include +#include "printf.h" +#include "riscv_hw_if.h" + +/* --------------- symbols/typedefs --------------- */ +typedef struct { + uint32_t doe_error; + uint32_t doe_notif; + uint32_t ecc_error; + uint32_t ecc_notif; + uint32_t hmac_error; + uint32_t hmac_notif; + uint32_t kv_error; + uint32_t kv_notif; + uint32_t sha512_error; + uint32_t sha512_notif; + uint32_t sha256_error; + uint32_t sha256_notif; + uint32_t qspi_error; + uint32_t qspi_notif; + uint32_t uart_error; + uint32_t uart_notif; + uint32_t i3c_error; + uint32_t i3c_notif; + uint32_t soc_ifc_error; + uint32_t soc_ifc_notif; + uint32_t sha512_acc_error; + uint32_t sha512_acc_notif; +} caliptra_intr_received_s; +extern volatile caliptra_intr_received_s cptra_intr_rcv; + +/* --------------- Function Declarations --------------- */ + +// Performs all the CSR setup to configure and enable vectored external interrupts +void init_interrupts(void); + +// These inline functions are used to insert event-specific functionality into the +// otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr" +inline void service_doe_error_intr() {return;} +inline void service_doe_notif_intr() {return;} + +inline void service_ecc_error_intr() {return;} +inline void service_ecc_notif_intr() {return;} + +inline void service_hmac_error_intr() {return;} +inline void service_hmac_notif_intr() {return;} + +inline void service_kv_error_intr() {return;} +inline void service_kv_notif_intr() {return;} +inline void service_sha512_error_intr() {return;} +inline void service_sha512_notif_intr() {return;} + +inline void service_sha256_error_intr() {return;} +inline void service_sha256_notif_intr() {return;} + +inline void service_qspi_error_intr() {return;} +inline void service_qspi_notif_intr() {return;} +inline void service_uart_error_intr() {return;} +inline void service_uart_notif_intr() {return;} +inline void service_i3c_error_intr() {return;} +inline void service_i3c_notif_intr() {return;} + +inline void service_soc_ifc_error_intr() { + uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R); + uint32_t sts = *reg; + /* Write 1 to Clear the pending interrupt */ + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK; + cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK; + cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK; + cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK; + cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK; + cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK; + cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK; + cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK) { + *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK; + cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK; + } + if (sts == 0) { + VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts); + SEND_STDOUT_CTRL(0x1); + while(1); + } +} + +inline void service_soc_ifc_notif_intr () { + uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R); + uint32_t sts = *reg; + /* Write 1 to Clear the pending interrupt */ + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) { + VPRINTF(HIGH, "cmd_avail\n"); + *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK; + cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) { + VPRINTF(HIGH, "mbox_ecc_cor\n"); + *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK; + cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) { + VPRINTF(HIGH, "debug_locked\n"); + *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK; + cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) { + VPRINTF(HIGH, "SCAN_MODE\n"); + *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK; + cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) { + VPRINTF(HIGH, "soc_req_lock\n"); + *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK; + cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK; + } + if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) { + VPRINTF(HIGH, "gen_in_toggle\n"); + *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK; + cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK; + } + if (sts == 0) { + VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts); + SEND_STDOUT_CTRL(0x1); + while(1); + } +} + +inline void service_sha512_acc_error_intr() {return;} +inline void service_sha512_acc_notif_intr() { + uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R); + uint32_t sts = *reg; + /* Write 1 to Clear the pending interrupt */ + if (sts & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) { + *reg = SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK; + cptra_intr_rcv.sha512_acc_notif |= SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK; + } + if (sts == 0) { + VPRINTF(ERROR,"bad sha512_acc_notif_intr sts:%x\n", sts); + SEND_STDOUT_CTRL(0x1); + while(1); + } +} + + +#endif //CALIPTRA_ISR_H diff --git a/src/integration/test_suites/smoke_test_hw_config/smoke_test_hw_config.c b/src/integration/test_suites/smoke_test_hw_config/smoke_test_hw_config.c new file mode 100644 index 000000000..78647dcc9 --- /dev/null +++ b/src/integration/test_suites/smoke_test_hw_config/smoke_test_hw_config.c @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +#include "caliptra_defines.h" +#include "caliptra_isr.h" +#include "riscv-csr.h" +#include "veer-csr.h" +#include "riscv_hw_if.h" +#include +#include +#include "printf.h" + + +//int whisperPrintf(const char* format, ...); +//#define ee_printf whisperPrintf + + +volatile char* stdout = (char *)STDOUT; +volatile uint32_t intr_count; +#ifdef CPT_VERBOSITY + enum printf_verbosity verbosity_g = CPT_VERBOSITY; +#else + enum printf_verbosity verbosity_g = LOW; +#endif + +volatile caliptra_intr_received_s cptra_intr_rcv = { + .doe_error = 0, + .doe_notif = 0, + .ecc_error = 0, + .ecc_notif = 0, + .hmac_error = 0, + .hmac_notif = 0, + .kv_error = 0, + .kv_notif = 0, + .sha512_error = 0, + .sha512_notif = 0, + .sha256_error = 0, + .sha256_notif = 0, + .qspi_error = 0, + .qspi_notif = 0, + .uart_error = 0, + .uart_notif = 0, + .i3c_error = 0, + .i3c_notif = 0, + .soc_ifc_error = 0, + .soc_ifc_notif = 0, + .sha512_acc_error = 0, + .sha512_acc_notif = 0, +}; + +void main(void) { + int argc=0; + char *argv[1]; + uint32_t data; + uint32_t data_exp; + uint8_t fail = 0; + + VPRINTF(LOW, "----------------------------------\nHardware Config Test from VeeR EL2 !!\n----------------------------------\n"); + + // Setup the interrupt CSR configuration + init_interrupts(); + + // Test HW REV ID + data = (lsu_read_32(CLP_SOC_IFC_REG_CPTRA_HW_REV_ID) & SOC_IFC_REG_CPTRA_HW_REV_ID_CPTRA_GENERATION_MASK) >> SOC_IFC_REG_CPTRA_HW_REV_ID_CPTRA_GENERATION_LOW; + #ifdef CALIPTRA_HW_REV_ID + if (data != CALIPTRA_HW_REV_ID) { + VPRINTF(FATAL, "HW REV ID register reports a version of major [%u], minor [%u], patch [%u] which does not match the expected value %u.%u.%u\n", + (data & 0xf), + (data & 0xf0) >> 4, + (data & 0xff00) >> 16, + (CALIPTRA_HW_REV_ID & 0xf), + (CALIPTRA_HW_REV_ID & 0xf0) >> 4, + (CALIPTRA_HW_REV_ID & 0xff00) >> 16); + fail = 1; + } + #else + VPRINTF(FATAL, "CALIPTRA_HW_REV_ID is not defined!\n"); + fail = 1; + #endif + + // Test HW CONFIG + data = lsu_read_32(CLP_SOC_IFC_REG_CPTRA_HW_CONFIG); + #ifdef CALIPTRA_HWCONFIG_TRNG_EN + data_exp = SOC_IFC_REG_CPTRA_HW_CONFIG_ITRNG_EN_MASK; + #else + data_exp = 0; + #endif + if ((data & SOC_IFC_REG_CPTRA_HW_CONFIG_ITRNG_EN_MASK) != data_exp) { + VPRINTF(FATAL, "HW Config register reports [%d] for ITRNG EN, expected [%d]!\n", (data & SOC_IFC_REG_CPTRA_HW_CONFIG_ITRNG_EN_MASK), data_exp); + fail = 1; + } + #ifdef CALIPTRA_HWCONFIG_QSPI_EN + data_exp = SOC_IFC_REG_CPTRA_HW_CONFIG_QSPI_EN_MASK; + #else + data_exp = 0; + #endif + if ((data & SOC_IFC_REG_CPTRA_HW_CONFIG_QSPI_EN_MASK) != data_exp) { + VPRINTF(FATAL, "HW Config register reports [%d] for QSPI EN, expected [%d]!\n", (data & SOC_IFC_REG_CPTRA_HW_CONFIG_QSPI_EN_MASK), data_exp); + fail = 1; + } + #ifdef CALIPTRA_HWCONFIG_I3C_EN + data_exp = SOC_IFC_REG_CPTRA_HW_CONFIG_I3C_EN_MASK; + #else + data_exp = 0; + #endif + if ((data & SOC_IFC_REG_CPTRA_HW_CONFIG_I3C_EN_MASK) != data_exp) { + VPRINTF(FATAL, "HW Config register reports [%d] for I3C EN, expected [%d]!\n", (data & SOC_IFC_REG_CPTRA_HW_CONFIG_I3C_EN_MASK), data_exp); + fail = 1; + } + #ifdef CALIPTRA_HWCONFIG_UART_EN + data_exp = SOC_IFC_REG_CPTRA_HW_CONFIG_UART_EN_MASK; + #else + data_exp = 0; + #endif + if ((data & SOC_IFC_REG_CPTRA_HW_CONFIG_UART_EN_MASK) != data_exp) { + VPRINTF(FATAL, "HW Config register reports [%d] for UART EN, expected [%d]!\n", (data & SOC_IFC_REG_CPTRA_HW_CONFIG_UART_EN_MASK), data_exp); + fail = 1; + } + #ifdef CALIPTRA_HWCONFIG_LMS_EN + data_exp = SOC_IFC_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_MASK; + #else + data_exp = 0; + #endif + if ((data & SOC_IFC_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_MASK) != data_exp) { + VPRINTF(FATAL, "HW Config register reports [%d] for LMS Acc EN, expected [%d]!\n", (data & SOC_IFC_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_MASK), data_exp); + fail = 1; + } + + // Ending status + if (fail) { + SEND_STDOUT_CTRL(0x1); + while(1); + } + + return; +} diff --git a/src/integration/test_suites/smoke_test_hw_config/smoke_test_hw_config.yml b/src/integration/test_suites/smoke_test_hw_config/smoke_test_hw_config.yml new file mode 100755 index 000000000..ce834e9ee --- /dev/null +++ b/src/integration/test_suites/smoke_test_hw_config/smoke_test_hw_config.yml @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +--- +seed: 1 +testname: smoke_test_hw_config diff --git a/tools/scripts/Makefile b/tools/scripts/Makefile index e4f61e119..b2a419a57 100644 --- a/tools/scripts/Makefile +++ b/tools/scripts/Makefile @@ -15,7 +15,17 @@ PLAYBOOK_RANDOM_SEED ?= $(shell date +%s) BUILD_CFLAGS ?= +# Cflags to give fw visibility to expected hw configuration +# Current release version is 1.1 - smoke test uses this value to check HW_REV_ID register +# Update the value here after 1.1 +CALIPTRA_HW_REV_ID=0x0011 +# After 1.1, LMS accelerator is always available +HWCFG_CFLAGS ?= -DCALIPTRA_HWCONFIG_LMS_EN -DCALIPTRA_HW_REV_ID=$(CALIPTRA_HW_REV_ID) TEST_CFLAGS = -g -O3 -DMY_RANDOM_SEED=$(PLAYBOOK_RANDOM_SEED) $(BUILD_CFLAGS) +CALIPTRA_INTERNAL_QSPI ?= 1 +CALIPTRA_INTERNAL_TRNG ?= 1 +CALIPTRA_INTERNAL_UART ?= 1 +CALIPTRA_INTERNAL_I3C ?= 0 VERILATOR = verilator GCC_PREFIX = riscv64-unknown-elf BUILD_DIR = $(CURDIR) @@ -183,7 +193,23 @@ TB_DPI_SRCS := $(addprefix $(CALIPTRA_ROOT)/src/integration/test_suites/libs/,$( TB_VERILATOR_SRCS = $(TBDIR)/test_caliptra_top_tb.cpp $(TB_DPI_SRCS) # Testbench defs -TB_DEFS = +define+CALIPTRA_INTERNAL_QSPI+CALIPTRA_INTERNAL_TRNG+CALIPTRA_INTERNAL_UART +TB_DEFS = +ifeq (CALIPTRA_INTERNAL_QSPI, 1) +TB_DEFS += +define+CALIPTRA_INTERNAL_QSPI +HWCFG_CFLAGS += -DCALIPTRA_HWCONFIG_QSPI_EN +endif +ifeq (CALIPTRA_INTERNAL_TRNG, 1) +TB_DEFS += +define+CALIPTRA_INTERNAL_TRNG +HWCFG_CFLAGS += -DCALIPTRA_HWCONFIG_TRNG_EN +endif +ifeq (CALIPTRA_INTERNAL_UART, 1) +TB_DEFS += +define+CALIPTRA_INTERNAL_UART +HWCFG_CFLAGS += -DCALIPTRA_HWCONFIG_UART_EN +endif +ifeq (CALIPTRA_INTERNAL_I3C , 1) +TB_DEFS += +define+CALIPTRA_INTERNAL_I3C +HWCFG_CFLAGS += -DCALIPTRA_HWCONFIG_I3C_EN +endif # By default debugging (JTAG) is locked in Caliptra. Add "DEBUG_UNLOCKED=1" to # enable it. @@ -312,7 +338,7 @@ program.hex: $(OFILE_CRT) $(OFILES) $(LINK) %.o : %.c $(HEADER_FILES) cp $(HEADER_FILES) $(BUILD_DIR) - $(GCC_PREFIX)-gcc $(includes) $(TEST_CFLAGS) -DCOMPILER_FLAGS="\"$(TEST_CFLAGS)\"" $(ABI) -nostdlib -c $< -o $@ + $(GCC_PREFIX)-gcc $(includes) $(TEST_CFLAGS) $(HWCFG_CFLAGS) -DCOMPILER_FLAGS="\"$(TEST_CFLAGS)\"" $(ABI) -nostdlib -c $< -o $@ endif From 35a11c7162c81b248f9f4ac19d89d6dbefe7f481 Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Wed, 3 Apr 2024 10:19:55 -0700 Subject: [PATCH 04/10] Add new hw_config smoke test to regressions --- src/integration/stimulus/L0_regression.yml | 1 + src/integration/stimulus/L0_trng_regression.yml | 1 + .../testsuites/caliptra_top_nightly_directed_regression.yml | 1 + 3 files changed, 3 insertions(+) diff --git a/src/integration/stimulus/L0_regression.yml b/src/integration/stimulus/L0_regression.yml index c26634827..5e19d3ac7 100644 --- a/src/integration/stimulus/L0_regression.yml +++ b/src/integration/stimulus/L0_regression.yml @@ -33,6 +33,7 @@ contents: - ../test_suites/smoke_test_trng/smoke_test_trng.yml - ../test_suites/smoke_test_qspi/smoke_test_qspi.yml - ../test_suites/smoke_test_uart/smoke_test_uart.yml + - ../test_suites/smoke_test_hw_config/smoke_test_hw_config.yml - ../test_suites/smoke_test_kv_uds_reset/smoke_test_kv_uds_reset.yml - ../test_suites/smoke_test_kv_securitystate/smoke_test_kv_securitystate.yml - ../test_suites/smoke_test_kv_ecc_flow/smoke_test_kv_ecc_flow.yml diff --git a/src/integration/stimulus/L0_trng_regression.yml b/src/integration/stimulus/L0_trng_regression.yml index 9bf496444..e55a5adbb 100644 --- a/src/integration/stimulus/L0_trng_regression.yml +++ b/src/integration/stimulus/L0_trng_regression.yml @@ -14,6 +14,7 @@ contents: - ../test_suites/c_intr_handler/c_intr_handler.yml - ../test_suites/smoke_test_sram_ecc/smoke_test_sram_ecc.yml - ../test_suites/smoke_test_trng/smoke_test_trng.yml + - ../test_suites/smoke_test_hw_config/smoke_test_hw_config.yml - ../test_suites/smoke_test_kv_uds_reset/smoke_test_kv_uds_reset.yml - ../test_suites/smoke_test_wdt/smoke_test_wdt.yml - ../test_suites/smoke_test_cg_wdt/smoke_test_cg_wdt.yml diff --git a/src/integration/stimulus/testsuites/caliptra_top_nightly_directed_regression.yml b/src/integration/stimulus/testsuites/caliptra_top_nightly_directed_regression.yml index 43946d5a4..2e354e7ae 100644 --- a/src/integration/stimulus/testsuites/caliptra_top_nightly_directed_regression.yml +++ b/src/integration/stimulus/testsuites/caliptra_top_nightly_directed_regression.yml @@ -31,6 +31,7 @@ contents: - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_trng/smoke_test_trng.yml - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_qspi/smoke_test_qspi.yml - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_uart/smoke_test_uart.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_hw_config/smoke_test_hw_config.yml - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_kv_uds_reset/smoke_test_kv_uds_reset.yml - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_kv_securitystate/smoke_test_kv_securitystate.yml - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_kv_ecc_flow/smoke_test_kv_ecc_flow.yml From eb07d280bc8cfc130a6d28e847adf2da106c683c Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Thu, 11 Apr 2024 10:44:06 -0700 Subject: [PATCH 05/10] Update predicted values for HW_CONFIG/HW_REV_ID regs --- src/soc_ifc/tb/soc_ifc_tb_pkg.sv | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/soc_ifc/tb/soc_ifc_tb_pkg.sv b/src/soc_ifc/tb/soc_ifc_tb_pkg.sv index 4115bdd98..2d89c494b 100644 --- a/src/soc_ifc/tb/soc_ifc_tb_pkg.sv +++ b/src/soc_ifc/tb/soc_ifc_tb_pkg.sv @@ -276,7 +276,7 @@ package soc_ifc_tb_pkg; "CPTRA_MBOX_VALID_PAUSER" : 32'hffff_ffff, "CPTRA_TRNG_VALID_PAUSER" : 32'hffff_ffff, "INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES" : 32'h5, - "CPTRA_HW_REV_ID" : 32'h1, + "CPTRA_HW_REV_ID" : 32'h11, "CPTRA_WDT_TIMER1_TIMEOUT_PERIOD" : 32'hffff_ffff, "CPTRA_WDT_TIMER2_TIMEOUT_PERIOD" : 32'hffff_ffff, "CPTRA_FUSE_VALID_PAUSER" : 32'hffff_ffff @@ -327,7 +327,9 @@ package soc_ifc_tb_pkg; dword_t _soc_register_mask_dict [string] = { "CPTRA_HW_CONFIG" : (`SOC_IFC_REG_CPTRA_HW_CONFIG_ITRNG_EN_MASK | `SOC_IFC_REG_CPTRA_HW_CONFIG_QSPI_EN_MASK | - `SOC_IFC_REG_CPTRA_HW_CONFIG_I3C_EN_MASK), + `SOC_IFC_REG_CPTRA_HW_CONFIG_I3C_EN_MASK | + `SOC_IFC_REG_CPTRA_HW_CONFIG_UART_EN_MASK | + `SOC_IFC_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_MASK), "CPTRA_FLOW_STATUS" : (`SOC_IFC_REG_CPTRA_FLOW_STATUS_STATUS_MASK | `SOC_IFC_REG_CPTRA_FLOW_STATUS_IDEVID_CSR_READY_MASK | //`SOC_IFC_REG_CPTRA_FLOW_STATUS_BOOT_FSM_PS_MASK | From b9c4223c98da9665a05bb6f47ce80cb875ff3acb Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Thu, 11 Apr 2024 11:28:12 -0700 Subject: [PATCH 06/10] Update initialization values in soc_ifc tb --- src/soc_ifc/tb/soc_ifc_tb_pkg.sv | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc_ifc/tb/soc_ifc_tb_pkg.sv b/src/soc_ifc/tb/soc_ifc_tb_pkg.sv index 2d89c494b..2fcf9119f 100644 --- a/src/soc_ifc/tb/soc_ifc_tb_pkg.sv +++ b/src/soc_ifc/tb/soc_ifc_tb_pkg.sv @@ -277,6 +277,7 @@ package soc_ifc_tb_pkg; "CPTRA_TRNG_VALID_PAUSER" : 32'hffff_ffff, "INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES" : 32'h5, "CPTRA_HW_REV_ID" : 32'h11, + "CPTRA_HW_CONFIG" : 32'h0000_0010, // LMS Acc Cap bit is set "CPTRA_WDT_TIMER1_TIMEOUT_PERIOD" : 32'hffff_ffff, "CPTRA_WDT_TIMER2_TIMEOUT_PERIOD" : 32'hffff_ffff, "CPTRA_FUSE_VALID_PAUSER" : 32'hffff_ffff @@ -306,6 +307,7 @@ package soc_ifc_tb_pkg; "CPTRA_RESET_REASON" : 32'h2, // field WARM_RESET "CPTRA_FUSE_WR_DONE" : 32'h1, // field 0 "CPTRA_HW_REV_ID" : 32'hffff_ffff, // field SOC_STEPPING_ID, CPTRA_GENERATION + "CPTRA_HW_CONFIG" : 32'h0000_001F, // All existing bits are sticky "CPTRA_FUSE_VALID_PAUSER" : 32'hffff_ffff, "CPTRA_FUSE_PAUSER_LOCK" : 32'h1, "CPTRA_TIMER_CONFIG" : 32'hffff_ffff, From cb87ac302d26b98a1bb31fd93fc87f31d7b4dc32 Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Fri, 22 Mar 2024 18:26:53 -0700 Subject: [PATCH 07/10] Updated reg descs with access privileges --- src/soc_ifc/rtl/soc_ifc_external_reg.rdl | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/src/soc_ifc/rtl/soc_ifc_external_reg.rdl b/src/soc_ifc/rtl/soc_ifc_external_reg.rdl index cb4df8fb1..92651e8e4 100644 --- a/src/soc_ifc/rtl/soc_ifc_external_reg.rdl +++ b/src/soc_ifc/rtl/soc_ifc_external_reg.rdl @@ -418,26 +418,34 @@ reg { reg { name = "Caliptra WDT1 Config"; - desc = "SOC provided count in cycles for WDT1 timeout."; + desc = "SOC provided count in cycles for WDT1 timeout. + [br]Caliptra Access: RW + [br]SOC Access: RW"; field {sw=rw; hw=na; resetsignal = cptra_pwrgood;} TIMEOUT[32]=0; } CPTRA_WDT_CFG[2]; reg { name = "Caliptra iTRNG Entropy Configuration 0"; - desc = "Adaptive threshold values for entropy source health tests."; + desc = "Adaptive threshold values for entropy source health tests. + [br]Caliptra Access: RW + [br]SOC Access: RW"; field {sw=rw; resetsignal=cptra_rst_b;} low_threshold[16]=0; field {sw=rw; resetsignal=cptra_rst_b;} high_threshold[16]=0; } CPTRA_iTRNG_ENTROPY_CONFIG_0; reg { name = "Caliptra iTRNG Entropy Configuration 1"; - desc = "Repetition count value for entropy source health tests."; + desc = "Repetition count value for entropy source health tests. + [br]Caliptra Access: RW + [br]SOC Access: RW"; field {sw=rw; resetsignal=cptra_rst_b;} repetition_count[16]=0; field {sw=rw; resetsignal=cptra_rst_b;} RSVD[16]=0; } CPTRA_iTRNG_ENTROPY_CONFIG_1; reg { name = "Caliptra Reserved Registers"; - desc = "Set of reserved registers for survivability"; + desc = "Set of reserved registers for survivability + [br]Caliptra Access: RW + [br]SOC Access: RW"; field {sw=rw; resetsignal=cptra_rst_b;} RSVD[32]=0; } CPTRA_RSVD_REG[2]; From fbdf0ba8bdb79556033965ea9e6af3d20e8ec4c0 Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Thu, 18 Apr 2024 18:24:32 -0700 Subject: [PATCH 08/10] Fix RDL checker so some grep arguments aren't ignored --- .github/scripts/pr_rdl_check.sh | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/.github/scripts/pr_rdl_check.sh b/.github/scripts/pr_rdl_check.sh index f5cb8d7a0..4398a0a39 100755 --- a/.github/scripts/pr_rdl_check.sh +++ b/.github/scripts/pr_rdl_check.sh @@ -26,6 +26,8 @@ fi if ! git show-ref --quiet "${merge_dest}"; then echo "Could not find ref named [${merge_dest}]" exit 1 +else + echo "Evaluating RDL modifications for merge into [${merge_dest}] with ref [$(git show-ref "${merge_dest}")]" fi if [[ -z "${CALIPTRA_ROOT:+"empty"}" ]]; then @@ -44,10 +46,10 @@ for rdl_file in $(find "${CALIPTRA_ROOT}/src" -name "*.rdl"); do echo "Did not find any file named [$rtl_file] that would be generated from [$rdl_file]"; fi; done -args=$(for fname in "${gen_rtl_list[@]}"; do echo -n " -e '$fname'"; done) +patn=$(echo "${gen_rtl_list[@]}" | sed 's, ,\\\|,g') # Find file modifications -rdl_mod_count=$(git diff --merge-base "${merge_dest}" --name-only | eval grep -c -e '\.rdl$\|tools\/templates\/rdl\|reg_gen.sh\|reg_gen.py\|reg_doc_gen.sh\|reg_doc_gen.py' $args || exit 0) +rdl_mod_count=$(git diff --merge-base "${merge_dest}" --name-only | grep -c -e '\.rdl$\|tools\/templates\/rdl\|reg_gen.sh\|reg_gen.py\|reg_doc_gen.sh\|reg_doc_gen.py' -e "${patn}" || exit 0) if [[ "${rdl_mod_count}" -gt 0 ]]; then # Run the HTML Doc generator script (to update the REG macro header files) # and the individual reg generator script but then remove the docs directories From 22085deedd800566b6af20d33da7437a43b94025 Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Fri, 26 Apr 2024 15:57:32 -0700 Subject: [PATCH 09/10] Typo fix for makefile --- tools/scripts/Makefile | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tools/scripts/Makefile b/tools/scripts/Makefile index b2a419a57..3beb5328c 100644 --- a/tools/scripts/Makefile +++ b/tools/scripts/Makefile @@ -194,19 +194,19 @@ TB_VERILATOR_SRCS = $(TBDIR)/test_caliptra_top_tb.cpp $(TB_DPI_SRCS) # Testbench defs TB_DEFS = -ifeq (CALIPTRA_INTERNAL_QSPI, 1) +ifeq ($(CALIPTRA_INTERNAL_QSPI), 1) TB_DEFS += +define+CALIPTRA_INTERNAL_QSPI HWCFG_CFLAGS += -DCALIPTRA_HWCONFIG_QSPI_EN endif -ifeq (CALIPTRA_INTERNAL_TRNG, 1) +ifeq ($(CALIPTRA_INTERNAL_TRNG), 1) TB_DEFS += +define+CALIPTRA_INTERNAL_TRNG HWCFG_CFLAGS += -DCALIPTRA_HWCONFIG_TRNG_EN endif -ifeq (CALIPTRA_INTERNAL_UART, 1) +ifeq ($(CALIPTRA_INTERNAL_UART), 1) TB_DEFS += +define+CALIPTRA_INTERNAL_UART HWCFG_CFLAGS += -DCALIPTRA_HWCONFIG_UART_EN endif -ifeq (CALIPTRA_INTERNAL_I3C , 1) +ifeq ($(CALIPTRA_INTERNAL_I3C) , 1) TB_DEFS += +define+CALIPTRA_INTERNAL_I3C HWCFG_CFLAGS += -DCALIPTRA_HWCONFIG_I3C_EN endif From 497f25992fc2fba8dfacfa96f11096a029760bc1 Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Tue, 30 Apr 2024 02:13:53 +0000 Subject: [PATCH 10/10] MICROSOFT AUTOMATED PIPELINE: Stamp 'cwhitehead-msft-LMS-cap-bit' with updated timestamp and hash after successful run --- .github/workflow_metadata/pr_hash | 2 +- .github/workflow_metadata/pr_timestamp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflow_metadata/pr_hash b/.github/workflow_metadata/pr_hash index 44b56164e..d96267be8 100644 --- a/.github/workflow_metadata/pr_hash +++ b/.github/workflow_metadata/pr_hash @@ -1 +1 @@ -a1c6b4e9634eda1208a2bdc365434561792dbe62102bcb254a470c3f9216bc45a755aadd6334294ab3116b82593f1eb6 \ No newline at end of file +b6a76c62fb59087fd27c838bf609afbad5b318521c2f9f16d27599ca166e71a67227e054bbfad47824c3c7f09bb4cce7 \ No newline at end of file diff --git a/.github/workflow_metadata/pr_timestamp b/.github/workflow_metadata/pr_timestamp index cc9863c4f..b6556295a 100644 --- a/.github/workflow_metadata/pr_timestamp +++ b/.github/workflow_metadata/pr_timestamp @@ -1 +1 @@ -1714426957 \ No newline at end of file +1714443225 \ No newline at end of file