From 4ae54c336a60ac2abc3a4b0ca4de98aa421eef17 Mon Sep 17 00:00:00 2001 From: Caleb <11879229+calebofearth@users.noreply.github.com> Date: Tue, 19 Nov 2024 12:25:54 -0800 Subject: [PATCH] [RTL] Convert AXI_ID to AXI_USER (#642) * Convert AXI_ID to AXI_USER * MICROSOFT AUTOMATED PIPELINE: Stamp 'cwhitehead-msft-axi-user' with updated timestamp and hash after successful run * Revert default user value of 1 - this is driven in TB when needed * MICROSOFT AUTOMATED PIPELINE: Stamp 'cwhitehead-msft-axi-user' with updated timestamp and hash after successful run --- .github/workflow_metadata/pr_hash | 2 +- .github/workflow_metadata/pr_timestamp | 2 +- src/integration/rtl/caliptra_reg.h | 88 ++++---- src/integration/rtl/caliptra_reg_defines.svh | 88 ++++---- src/integration/tb/caliptra_top_tb_soc_bfm.sv | 68 +++--- src/soc_ifc/coverage/soc_ifc_cov_if.sv | 210 +++++++++--------- src/soc_ifc/rtl/caliptra_top_reg.h | 88 ++++---- src/soc_ifc/rtl/caliptra_top_reg_defines.svh | 88 ++++---- src/soc_ifc/rtl/mbox.sv | 14 +- src/soc_ifc/rtl/mbox_csr.rdl | 12 +- src/soc_ifc/rtl/mbox_csr.sv | 32 +-- src/soc_ifc/rtl/mbox_csr_pkg.sv | 16 +- src/soc_ifc/rtl/mbox_csr_uvm.sv | 30 +-- src/soc_ifc/rtl/soc_ifc_arb.sv | 20 +- src/soc_ifc/rtl/soc_ifc_external_reg.rdl | 58 ++--- src/soc_ifc/rtl/soc_ifc_pkg.sv | 16 +- src/soc_ifc/rtl/soc_ifc_reg.sv | 192 ++++++++-------- src/soc_ifc/rtl/soc_ifc_reg_covergroups.svh | 48 ++-- src/soc_ifc/rtl/soc_ifc_reg_pkg.sv | 96 ++++---- src/soc_ifc/rtl/soc_ifc_reg_sample.svh | 60 ++--- src/soc_ifc/rtl/soc_ifc_reg_uvm.sv | 160 ++++++------- src/soc_ifc/rtl/soc_ifc_top.sv | 70 +++--- 22 files changed, 729 insertions(+), 729 deletions(-) diff --git a/.github/workflow_metadata/pr_hash b/.github/workflow_metadata/pr_hash index 7c2f41599..069318d80 100644 --- a/.github/workflow_metadata/pr_hash +++ b/.github/workflow_metadata/pr_hash @@ -1 +1 @@ -fa1eb0583cba1d002083811627ac6aa3cc5abec5b97928888a2b12b4cd8b15e8437d996c3bc459941be6c28c4b5ab5c3 \ No newline at end of file +6104519ceefcd79a47c8c890b053f79f50e15d8213ab0685984df75f95b1273d5eff69ea0dc07cd2d53536d9ed52f88a \ No newline at end of file diff --git a/.github/workflow_metadata/pr_timestamp b/.github/workflow_metadata/pr_timestamp index a320c309a..6a7b5c155 100644 --- a/.github/workflow_metadata/pr_timestamp +++ b/.github/workflow_metadata/pr_timestamp @@ -1 +1 @@ -1731724731 \ No newline at end of file +1732036724 \ No newline at end of file diff --git a/src/integration/rtl/caliptra_reg.h b/src/integration/rtl/caliptra_reg.h index 238fb403c..a7d0303db 100644 --- a/src/integration/rtl/caliptra_reg.h +++ b/src/integration/rtl/caliptra_reg.h @@ -5043,8 +5043,8 @@ #define MBOX_CSR_MBOX_LOCK (0x0) #define MBOX_CSR_MBOX_LOCK_LOCK_LOW (0) #define MBOX_CSR_MBOX_LOCK_LOCK_MASK (0x1) -#define CLP_MBOX_CSR_MBOX_ID (0x30020004) -#define MBOX_CSR_MBOX_ID (0x4) +#define CLP_MBOX_CSR_MBOX_USER (0x30020004) +#define MBOX_CSR_MBOX_USER (0x4) #define CLP_MBOX_CSR_MBOX_CMD (0x30020008) #define MBOX_CSR_MBOX_CMD (0x8) #define CLP_MBOX_CSR_MBOX_DLEN (0x3002000c) @@ -5544,42 +5544,42 @@ #define SOC_IFC_REG_CPTRA_SECURITY_STATE_SCAN_MODE_MASK (0x8) #define SOC_IFC_REG_CPTRA_SECURITY_STATE_RSVD_LOW (4) #define SOC_IFC_REG_CPTRA_SECURITY_STATE_RSVD_MASK (0xfffffff0) -#define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_0 (0x30030048) -#define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_0 (0x48) -#define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_1 (0x3003004c) -#define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_1 (0x4c) -#define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_2 (0x30030050) -#define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_2 (0x50) -#define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_3 (0x30030054) -#define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_3 (0x54) -#define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_4 (0x30030058) -#define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_4 (0x58) -#define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_0 (0x3003005c) -#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_0 (0x5c) -#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_0_LOCK_LOW (0) -#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_0_LOCK_MASK (0x1) -#define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_1 (0x30030060) -#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_1 (0x60) -#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_1_LOCK_LOW (0) -#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_1_LOCK_MASK (0x1) -#define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_2 (0x30030064) -#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_2 (0x64) -#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_2_LOCK_LOW (0) -#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_2_LOCK_MASK (0x1) -#define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_3 (0x30030068) -#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_3 (0x68) -#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_3_LOCK_LOW (0) -#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_3_LOCK_MASK (0x1) -#define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_4 (0x3003006c) -#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_4 (0x6c) -#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_4_LOCK_LOW (0) -#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_4_LOCK_MASK (0x1) -#define CLP_SOC_IFC_REG_CPTRA_TRNG_VALID_AXI_ID (0x30030070) -#define SOC_IFC_REG_CPTRA_TRNG_VALID_AXI_ID (0x70) -#define CLP_SOC_IFC_REG_CPTRA_TRNG_AXI_ID_LOCK (0x30030074) -#define SOC_IFC_REG_CPTRA_TRNG_AXI_ID_LOCK (0x74) -#define SOC_IFC_REG_CPTRA_TRNG_AXI_ID_LOCK_LOCK_LOW (0) -#define SOC_IFC_REG_CPTRA_TRNG_AXI_ID_LOCK_LOCK_MASK (0x1) +#define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_0 (0x30030048) +#define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_0 (0x48) +#define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_1 (0x3003004c) +#define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_1 (0x4c) +#define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_2 (0x30030050) +#define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_2 (0x50) +#define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_3 (0x30030054) +#define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_3 (0x54) +#define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_4 (0x30030058) +#define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_4 (0x58) +#define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_0 (0x3003005c) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_0 (0x5c) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_0_LOCK_LOW (0) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_0_LOCK_MASK (0x1) +#define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_1 (0x30030060) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_1 (0x60) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_1_LOCK_LOW (0) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_1_LOCK_MASK (0x1) +#define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_2 (0x30030064) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_2 (0x64) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_2_LOCK_LOW (0) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_2_LOCK_MASK (0x1) +#define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_3 (0x30030068) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_3 (0x68) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_3_LOCK_LOW (0) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_3_LOCK_MASK (0x1) +#define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_4 (0x3003006c) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_4 (0x6c) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_4_LOCK_LOW (0) +#define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_4_LOCK_MASK (0x1) +#define CLP_SOC_IFC_REG_CPTRA_TRNG_VALID_AXI_USER (0x30030070) +#define SOC_IFC_REG_CPTRA_TRNG_VALID_AXI_USER (0x70) +#define CLP_SOC_IFC_REG_CPTRA_TRNG_AXI_USER_LOCK (0x30030074) +#define SOC_IFC_REG_CPTRA_TRNG_AXI_USER_LOCK (0x74) +#define SOC_IFC_REG_CPTRA_TRNG_AXI_USER_LOCK_LOCK_LOW (0) +#define SOC_IFC_REG_CPTRA_TRNG_AXI_USER_LOCK_LOCK_MASK (0x1) #define CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_0 (0x30030078) #define SOC_IFC_REG_CPTRA_TRNG_DATA_0 (0x78) #define CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_1 (0x3003007c) @@ -5690,12 +5690,12 @@ #define SOC_IFC_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_MASK (0x1) #define SOC_IFC_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_LOW (1) #define SOC_IFC_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_MASK (0x2) -#define CLP_SOC_IFC_REG_CPTRA_FUSE_VALID_AXI_ID (0x30030108) -#define SOC_IFC_REG_CPTRA_FUSE_VALID_AXI_ID (0x108) -#define CLP_SOC_IFC_REG_CPTRA_FUSE_AXI_ID_LOCK (0x3003010c) -#define SOC_IFC_REG_CPTRA_FUSE_AXI_ID_LOCK (0x10c) -#define SOC_IFC_REG_CPTRA_FUSE_AXI_ID_LOCK_LOCK_LOW (0) -#define SOC_IFC_REG_CPTRA_FUSE_AXI_ID_LOCK_LOCK_MASK (0x1) +#define CLP_SOC_IFC_REG_CPTRA_FUSE_VALID_AXI_USER (0x30030108) +#define SOC_IFC_REG_CPTRA_FUSE_VALID_AXI_USER (0x108) +#define CLP_SOC_IFC_REG_CPTRA_FUSE_AXI_USER_LOCK (0x3003010c) +#define SOC_IFC_REG_CPTRA_FUSE_AXI_USER_LOCK (0x10c) +#define SOC_IFC_REG_CPTRA_FUSE_AXI_USER_LOCK_LOCK_LOW (0) +#define SOC_IFC_REG_CPTRA_FUSE_AXI_USER_LOCK_LOCK_MASK (0x1) #define CLP_SOC_IFC_REG_CPTRA_WDT_CFG_0 (0x30030110) #define SOC_IFC_REG_CPTRA_WDT_CFG_0 (0x110) #define CLP_SOC_IFC_REG_CPTRA_WDT_CFG_1 (0x30030114) diff --git a/src/integration/rtl/caliptra_reg_defines.svh b/src/integration/rtl/caliptra_reg_defines.svh index ba0339373..cc1dfc47b 100644 --- a/src/integration/rtl/caliptra_reg_defines.svh +++ b/src/integration/rtl/caliptra_reg_defines.svh @@ -5043,8 +5043,8 @@ `define MBOX_CSR_MBOX_LOCK (32'h0) `define MBOX_CSR_MBOX_LOCK_LOCK_LOW (0) `define MBOX_CSR_MBOX_LOCK_LOCK_MASK (32'h1) -`define CLP_MBOX_CSR_MBOX_ID (32'h30020004) -`define MBOX_CSR_MBOX_ID (32'h4) +`define CLP_MBOX_CSR_MBOX_USER (32'h30020004) +`define MBOX_CSR_MBOX_USER (32'h4) `define CLP_MBOX_CSR_MBOX_CMD (32'h30020008) `define MBOX_CSR_MBOX_CMD (32'h8) `define CLP_MBOX_CSR_MBOX_DLEN (32'h3002000c) @@ -5544,42 +5544,42 @@ `define SOC_IFC_REG_CPTRA_SECURITY_STATE_SCAN_MODE_MASK (32'h8) `define SOC_IFC_REG_CPTRA_SECURITY_STATE_RSVD_LOW (4) `define SOC_IFC_REG_CPTRA_SECURITY_STATE_RSVD_MASK (32'hfffffff0) -`define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_0 (32'h30030048) -`define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_0 (32'h48) -`define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_1 (32'h3003004c) -`define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_1 (32'h4c) -`define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_2 (32'h30030050) -`define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_2 (32'h50) -`define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_3 (32'h30030054) -`define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_3 (32'h54) -`define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_4 (32'h30030058) -`define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_4 (32'h58) -`define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_0 (32'h3003005c) -`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_0 (32'h5c) -`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_0_LOCK_LOW (0) -`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_0_LOCK_MASK (32'h1) -`define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_1 (32'h30030060) -`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_1 (32'h60) -`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_1_LOCK_LOW (0) -`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_1_LOCK_MASK (32'h1) -`define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_2 (32'h30030064) -`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_2 (32'h64) -`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_2_LOCK_LOW (0) -`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_2_LOCK_MASK (32'h1) -`define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_3 (32'h30030068) -`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_3 (32'h68) -`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_3_LOCK_LOW (0) -`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_3_LOCK_MASK (32'h1) -`define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_4 (32'h3003006c) -`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_4 (32'h6c) -`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_4_LOCK_LOW (0) -`define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_4_LOCK_MASK (32'h1) -`define CLP_SOC_IFC_REG_CPTRA_TRNG_VALID_AXI_ID (32'h30030070) -`define SOC_IFC_REG_CPTRA_TRNG_VALID_AXI_ID (32'h70) -`define CLP_SOC_IFC_REG_CPTRA_TRNG_AXI_ID_LOCK (32'h30030074) -`define SOC_IFC_REG_CPTRA_TRNG_AXI_ID_LOCK (32'h74) -`define SOC_IFC_REG_CPTRA_TRNG_AXI_ID_LOCK_LOCK_LOW (0) -`define SOC_IFC_REG_CPTRA_TRNG_AXI_ID_LOCK_LOCK_MASK (32'h1) +`define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_0 (32'h30030048) +`define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_0 (32'h48) +`define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_1 (32'h3003004c) +`define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_1 (32'h4c) +`define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_2 (32'h30030050) +`define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_2 (32'h50) +`define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_3 (32'h30030054) +`define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_3 (32'h54) +`define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_4 (32'h30030058) +`define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_4 (32'h58) +`define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_0 (32'h3003005c) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_0 (32'h5c) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_0_LOCK_LOW (0) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_0_LOCK_MASK (32'h1) +`define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_1 (32'h30030060) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_1 (32'h60) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_1_LOCK_LOW (0) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_1_LOCK_MASK (32'h1) +`define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_2 (32'h30030064) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_2 (32'h64) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_2_LOCK_LOW (0) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_2_LOCK_MASK (32'h1) +`define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_3 (32'h30030068) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_3 (32'h68) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_3_LOCK_LOW (0) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_3_LOCK_MASK (32'h1) +`define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_4 (32'h3003006c) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_4 (32'h6c) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_4_LOCK_LOW (0) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_4_LOCK_MASK (32'h1) +`define CLP_SOC_IFC_REG_CPTRA_TRNG_VALID_AXI_USER (32'h30030070) +`define SOC_IFC_REG_CPTRA_TRNG_VALID_AXI_USER (32'h70) +`define CLP_SOC_IFC_REG_CPTRA_TRNG_AXI_USER_LOCK (32'h30030074) +`define SOC_IFC_REG_CPTRA_TRNG_AXI_USER_LOCK (32'h74) +`define SOC_IFC_REG_CPTRA_TRNG_AXI_USER_LOCK_LOCK_LOW (0) +`define SOC_IFC_REG_CPTRA_TRNG_AXI_USER_LOCK_LOCK_MASK (32'h1) `define CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_0 (32'h30030078) `define SOC_IFC_REG_CPTRA_TRNG_DATA_0 (32'h78) `define CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_1 (32'h3003007c) @@ -5690,12 +5690,12 @@ `define SOC_IFC_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_MASK (32'h1) `define SOC_IFC_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_LOW (1) `define SOC_IFC_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_MASK (32'h2) -`define CLP_SOC_IFC_REG_CPTRA_FUSE_VALID_AXI_ID (32'h30030108) -`define SOC_IFC_REG_CPTRA_FUSE_VALID_AXI_ID (32'h108) -`define CLP_SOC_IFC_REG_CPTRA_FUSE_AXI_ID_LOCK (32'h3003010c) -`define SOC_IFC_REG_CPTRA_FUSE_AXI_ID_LOCK (32'h10c) -`define SOC_IFC_REG_CPTRA_FUSE_AXI_ID_LOCK_LOCK_LOW (0) -`define SOC_IFC_REG_CPTRA_FUSE_AXI_ID_LOCK_LOCK_MASK (32'h1) +`define CLP_SOC_IFC_REG_CPTRA_FUSE_VALID_AXI_USER (32'h30030108) +`define SOC_IFC_REG_CPTRA_FUSE_VALID_AXI_USER (32'h108) +`define CLP_SOC_IFC_REG_CPTRA_FUSE_AXI_USER_LOCK (32'h3003010c) +`define SOC_IFC_REG_CPTRA_FUSE_AXI_USER_LOCK (32'h10c) +`define SOC_IFC_REG_CPTRA_FUSE_AXI_USER_LOCK_LOCK_LOW (0) +`define SOC_IFC_REG_CPTRA_FUSE_AXI_USER_LOCK_LOCK_MASK (32'h1) `define CLP_SOC_IFC_REG_CPTRA_WDT_CFG_0 (32'h30030110) `define SOC_IFC_REG_CPTRA_WDT_CFG_0 (32'h110) `define CLP_SOC_IFC_REG_CPTRA_WDT_CFG_1 (32'h30030114) diff --git a/src/integration/tb/caliptra_top_tb_soc_bfm.sv b/src/integration/tb/caliptra_top_tb_soc_bfm.sv index a7d9ea750..ac6320927 100644 --- a/src/integration/tb/caliptra_top_tb_soc_bfm.sv +++ b/src/integration/tb/caliptra_top_tb_soc_bfm.sv @@ -250,16 +250,16 @@ import caliptra_top_tb_pkg::*; #( $write ("SoC: Requesting mailbox lock..."); poll_count = 0; do begin - m_axi_bfm_if.axi_read_single(.addr(`CLP_MBOX_CSR_MBOX_LOCK), .id(32'hFFFF_FFFF), .data(rdata), .resp(rresp)); + m_axi_bfm_if.axi_read_single(.addr(`CLP_MBOX_CSR_MBOX_LOCK), .user(32'hFFFF_FFFF), .data(rdata), .resp(rresp)); poll_count++; end while (rdata[`MBOX_CSR_MBOX_LOCK_LOCK_LOW] == 1); $display ("\n >>> SoC: Lock granted after polling %d times\n", poll_count); $display ("SoC: Writing the Command Register\n"); - m_axi_bfm_if.axi_write_single(.addr(`CLP_MBOX_CSR_MBOX_CMD), .id(32'hFFFF_FFFF), .data(32'hBA5EBA11), .resp(wresp)); + m_axi_bfm_if.axi_write_single(.addr(`CLP_MBOX_CSR_MBOX_CMD), .user(32'hFFFF_FFFF), .data(32'hBA5EBA11), .resp(wresp)); $display ("SoC: Writing the Data Length Register\n"); - m_axi_bfm_if.axi_write_single(.addr(`CLP_MBOX_CSR_MBOX_DLEN), .id(32'hFFFF_FFFF), .data(FW_NUM_DWORDS*4), .resp(wresp)); + m_axi_bfm_if.axi_write_single(.addr(`CLP_MBOX_CSR_MBOX_DLEN), .user(32'hFFFF_FFFF), .data(FW_NUM_DWORDS*4), .resp(wresp)); $display ("SoC: Writing the Firmware into Data-in Register\n"); fw_blob = new[FW_NUM_DWORDS]; @@ -269,23 +269,23 @@ import caliptra_top_tb_pkg::*; #( m_axi_bfm_if.axi_write(.addr(`CLP_MBOX_CSR_MBOX_DATAIN), .burst(AXI_BURST_FIXED), .len (FW_NUM_DWORDS-1), - .id (32'hFFFF_FFFF), + .user (32'hFFFF_FFFF), .data (fw_blob), .strb (wstrb_array), .resp (wresp)); $display ("SoC: Setting the Execute Register\n"); - m_axi_bfm_if.axi_write_single(.addr(`CLP_MBOX_CSR_MBOX_EXECUTE), .id(32'hFFFF_FFFF), .data(32'h00000001), .resp(wresp)); + m_axi_bfm_if.axi_write_single(.addr(`CLP_MBOX_CSR_MBOX_EXECUTE), .user(32'hFFFF_FFFF), .data(32'h00000001), .resp(wresp)); $display("SoC: Waiting for Response Data availability\n"); wait(mailbox_data_avail); $display("SoC: Reading the Status Register...\n"); - m_axi_bfm_if.axi_read_single(.addr(`CLP_MBOX_CSR_MBOX_STATUS), .id(32'hFFFF_FFFF), .data(rdata), .resp(rresp)); + m_axi_bfm_if.axi_read_single(.addr(`CLP_MBOX_CSR_MBOX_STATUS), .user(32'hFFFF_FFFF), .data(rdata), .resp(rresp)); if (((rdata & `MBOX_CSR_MBOX_STATUS_STATUS_MASK) >> `MBOX_CSR_MBOX_STATUS_STATUS_LOW) == DATA_READY) begin: READ_RESP_DATA $display("SoC: Reading the Data Length Register...\n"); - m_axi_bfm_if.axi_read_single(.addr(`CLP_MBOX_CSR_MBOX_DLEN), .id(32'hFFFF_FFFF), .data(rdata), .resp(rresp)); + m_axi_bfm_if.axi_read_single(.addr(`CLP_MBOX_CSR_MBOX_DLEN), .user(32'hFFFF_FFFF), .data(rdata), .resp(rresp)); $display("SoC: Reading the Data Out Register\n"); for (int xfer4k = 0; xfer4k < rdata; xfer4k += 4096) begin @@ -293,17 +293,17 @@ import caliptra_top_tb_pkg::*; #( dw_count = byte_count/(`CALIPTRA_AXI_DATA_WIDTH/8) + |byte_count[$clog2(`CALIPTRA_AXI_DATA_WIDTH/8)-1:0]; rdata_array = new[dw_count]; rresp_array = new[dw_count]; - m_axi_bfm_if.axi_read(.addr(`CLP_MBOX_CSR_MBOX_DATAOUT), - .burst(AXI_BURST_FIXED), - .len(dw_count-1), - .id (32'hFFFF_FFFF), - .data(rdata_array), - .resp(rresp_array)); + m_axi_bfm_if.axi_read(.addr (`CLP_MBOX_CSR_MBOX_DATAOUT), + .burst(AXI_BURST_FIXED), + .len (dw_count-1 ), + .user (32'hFFFF_FFFF ), + .data (rdata_array ), + .resp (rresp_array) ); end end: READ_RESP_DATA $display("SoC: Resetting the Execute Register\n"); - m_axi_bfm_if.axi_write_single(.addr(`CLP_MBOX_CSR_MBOX_EXECUTE), .id(32'hFFFF_FFFF), .data(32'h0), .resp(wresp)); + m_axi_bfm_if.axi_write_single(.addr(`CLP_MBOX_CSR_MBOX_EXECUTE), .user(32'hFFFF_FFFF), .data(32'h0), .resp(wresp)); //Wait for Mailbox flow to be done before toggling generic_input_wires @(negedge core_clk); @@ -319,7 +319,7 @@ import caliptra_top_tb_pkg::*; #( forever begin if (cptra_error_fatal_dly_p) begin $display("SoC: Observed cptra_error_fatal; reading Caliptra register\n"); - m_axi_bfm_if.axi_read_single(.addr(`CLP_SOC_IFC_REG_CPTRA_HW_ERROR_FATAL), .id(32'hFFFF_FFFF), .data(rdata), .resp(rresp)); + m_axi_bfm_if.axi_read_single(.addr(`CLP_SOC_IFC_REG_CPTRA_HW_ERROR_FATAL), .data(rdata), .resp(rresp)); if (rdata[`SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_ICCM_ECC_UNC_LOW]) begin generic_input_wires = {32'h0, ICCM_FATAL_OBSERVED}; end @@ -343,7 +343,7 @@ import caliptra_top_tb_pkg::*; #( end else if (cptra_error_non_fatal_dly_p) begin $display("SoC: Observed cptra_error_non_fatal; reading Caliptra register\n"); - m_axi_bfm_if.axi_read_single(.addr(`CLP_SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL), .id(32'hFFFF_FFFF), .data(rdata), .resp(rresp)); + m_axi_bfm_if.axi_read_single(.addr(`CLP_SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL), .data(rdata), .resp(rresp)); if (rdata[`SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_NO_LOCK_LOW]) begin generic_input_wires = {32'h0, PROT_NO_LOCK_NON_FATAL_OBSERVED}; end @@ -357,11 +357,11 @@ import caliptra_top_tb_pkg::*; #( generic_input_wires = {32'h0, ERROR_NONE_SET}; end $display("SoC: Observed cptra_error_non_fatal; writing to clear Caliptra register\n"); - m_axi_bfm_if.axi_write_single(.addr(`CLP_SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL), .id(32'hFFFF_FFFF), .data(rdata), .resp(wresp)); + m_axi_bfm_if.axi_write_single(.addr(`CLP_SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL), .data(rdata), .resp(wresp)); end else if (soc_ifc_hw_error_wdata) begin $display("SoC: Observed cptra_error_fatal; writing to clear Caliptra register\n"); - m_axi_bfm_if.axi_write_single(.addr(`CLP_SOC_IFC_REG_CPTRA_HW_ERROR_FATAL), .id(32'hFFFF_FFFF), .data(soc_ifc_hw_error_wdata), .resp(wresp)); + m_axi_bfm_if.axi_write_single(.addr(`CLP_SOC_IFC_REG_CPTRA_HW_ERROR_FATAL), .data(soc_ifc_hw_error_wdata), .resp(wresp)); soc_ifc_hw_error_wdata = '0; end else if (ras_test_ctrl.do_no_lock_access) begin @@ -373,10 +373,10 @@ import caliptra_top_tb_pkg::*; #( rresp_array = new[dw_count]; m_axi_bfm_if.axi_read(.addr(`CLP_MBOX_CSR_MBOX_DATAOUT), .burst(AXI_BURST_FIXED), - .len(dw_count-1), - .id (32'hFFFF_FFFF), - .data(rdata_array), - .resp(rresp_array)); + .len (dw_count-1 ), + .user (32'hFFFF_FFFF ), + .data (rdata_array ), + .resp (rresp_array) ); end join end @@ -386,13 +386,13 @@ import caliptra_top_tb_pkg::*; #( $write ("SoC: Requesting mailbox lock..."); poll_count = 0; do begin - m_axi_bfm_if.axi_read_single(.addr(`CLP_MBOX_CSR_MBOX_LOCK), .id(32'hFFFF_FFFF), .data(rdata), .resp(rresp)); + m_axi_bfm_if.axi_read_single(.addr(`CLP_MBOX_CSR_MBOX_LOCK), .user(32'hFFFF_FFFF), .data(rdata), .resp(rresp)); poll_count++; end while (rdata[`MBOX_CSR_MBOX_LOCK_LOCK_LOW] == 1); $display ("\n >>> SoC: Lock granted after polling %d times\n", poll_count); $display("SoC: Reading the Data Length Register...\n"); - m_axi_bfm_if.axi_read_single(.addr(`CLP_MBOX_CSR_MBOX_DLEN), .id(32'hFFFF_FFFF), .data(rdata), .resp(rresp)); + m_axi_bfm_if.axi_read_single(.addr(`CLP_MBOX_CSR_MBOX_DLEN), .user(32'hFFFF_FFFF), .data(rdata), .resp(rresp)); $display("SoC: Reading the Data Out Register\n"); dw_count = 1; @@ -400,10 +400,10 @@ import caliptra_top_tb_pkg::*; #( rresp_array = new[dw_count]; m_axi_bfm_if.axi_read(.addr(`CLP_MBOX_CSR_MBOX_DATAOUT), .burst(AXI_BURST_FIXED), - .len(dw_count-1), - .id (32'hFFFF_FFFF), - .data(rdata_array), - .resp(rresp_array)); + .len (dw_count-1 ), + .user (32'hFFFF_FFFF ), + .data (rdata_array ), + .resp (rresp_array) ); end join end @@ -420,7 +420,7 @@ import caliptra_top_tb_pkg::*; #( end else if (mailbox_data_avail) begin $display("SoC: Reading the Data Length Register\n"); - m_axi_bfm_if.axi_read_single(.addr(`CLP_MBOX_CSR_MBOX_DLEN), .id(32'hFFFF_FFFF), .data(rdata), .resp(rresp)); + m_axi_bfm_if.axi_read_single(.addr(`CLP_MBOX_CSR_MBOX_DLEN), .user(32'hFFFF_FFFF), .data(rdata), .resp(rresp)); $display("SoC: Reading the Data Out Register\n"); for (int xfer4k = 0; xfer4k < rdata; xfer4k += 4096) begin @@ -430,14 +430,14 @@ import caliptra_top_tb_pkg::*; #( rresp_array = new[dw_count]; m_axi_bfm_if.axi_read(.addr(`CLP_MBOX_CSR_MBOX_DATAOUT), .burst(AXI_BURST_FIXED), - .len(dw_count-1), - .id (32'hFFFF_FFFF), - .data(rdata_array), - .resp(rresp_array)); + .len (dw_count-1 ), + .user (32'hFFFF_FFFF ), + .data (rdata_array ), + .resp (rresp_array )); end $display ("SoC: Writing the Mbox Status Register\n"); - m_axi_bfm_if.axi_write_single(.addr(`CLP_MBOX_CSR_MBOX_STATUS), .id(32'hFFFF_FFFF), .data(32'h1), .resp(wresp)); + m_axi_bfm_if.axi_write_single(.addr(`CLP_MBOX_CSR_MBOX_STATUS), .user(32'hFFFF_FFFF), .data(32'h1), .resp(wresp)); end @(posedge core_clk); end diff --git a/src/soc_ifc/coverage/soc_ifc_cov_if.sv b/src/soc_ifc/coverage/soc_ifc_cov_if.sv index e31c77fea..fec38befd 100644 --- a/src/soc_ifc/coverage/soc_ifc_cov_if.sv +++ b/src/soc_ifc/coverage/soc_ifc_cov_if.sv @@ -425,31 +425,31 @@ interface soc_ifc_cov_if // logic [3:0] bus_CPTRA_SECURITY_STATE; // logic [31:0] full_addr_CPTRA_SECURITY_STATE = `CLP_SOC_IFC_REG_CPTRA_SECURITY_STATE; - logic hit_CPTRA_MBOX_VALID_AXI_ID[0:4]; - logic [3:0] bus_CPTRA_MBOX_VALID_AXI_ID[0:4]; - logic [31:0] full_addr_CPTRA_MBOX_VALID_AXI_ID[0:4]; - assign full_addr_CPTRA_MBOX_VALID_AXI_ID[0] = `CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_0; - assign full_addr_CPTRA_MBOX_VALID_AXI_ID[1] = `CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_1; - assign full_addr_CPTRA_MBOX_VALID_AXI_ID[2] = `CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_2; - assign full_addr_CPTRA_MBOX_VALID_AXI_ID[3] = `CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_3; - assign full_addr_CPTRA_MBOX_VALID_AXI_ID[4] = `CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_4; - - logic hit_CPTRA_MBOX_AXI_ID_LOCK[0:4]; - logic [3:0] bus_CPTRA_MBOX_AXI_ID_LOCK[0:4]; - logic [31:0] full_addr_CPTRA_MBOX_AXI_ID_LOCK[0:4]; - assign full_addr_CPTRA_MBOX_AXI_ID_LOCK[0] = `CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_0; - assign full_addr_CPTRA_MBOX_AXI_ID_LOCK[1] = `CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_1; - assign full_addr_CPTRA_MBOX_AXI_ID_LOCK[2] = `CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_2; - assign full_addr_CPTRA_MBOX_AXI_ID_LOCK[3] = `CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_3; - assign full_addr_CPTRA_MBOX_AXI_ID_LOCK[4] = `CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_4; - - logic hit_CPTRA_TRNG_VALID_AXI_ID; - logic [3:0] bus_CPTRA_TRNG_VALID_AXI_ID; - logic [31:0] full_addr_CPTRA_TRNG_VALID_AXI_ID = `CLP_SOC_IFC_REG_CPTRA_TRNG_VALID_AXI_ID; - - logic hit_CPTRA_TRNG_AXI_ID_LOCK; - logic [3:0] bus_CPTRA_TRNG_AXI_ID_LOCK; - logic [31:0] full_addr_CPTRA_TRNG_AXI_ID_LOCK = `CLP_SOC_IFC_REG_CPTRA_TRNG_AXI_ID_LOCK; + logic hit_CPTRA_MBOX_VALID_AXI_USER[0:4]; + logic [3:0] bus_CPTRA_MBOX_VALID_AXI_USER[0:4]; + logic [31:0] full_addr_CPTRA_MBOX_VALID_AXI_USER[0:4]; + assign full_addr_CPTRA_MBOX_VALID_AXI_USER[0] = `CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_0; + assign full_addr_CPTRA_MBOX_VALID_AXI_USER[1] = `CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_1; + assign full_addr_CPTRA_MBOX_VALID_AXI_USER[2] = `CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_2; + assign full_addr_CPTRA_MBOX_VALID_AXI_USER[3] = `CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_3; + assign full_addr_CPTRA_MBOX_VALID_AXI_USER[4] = `CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_4; + + logic hit_CPTRA_MBOX_AXI_USER_LOCK[0:4]; + logic [3:0] bus_CPTRA_MBOX_AXI_USER_LOCK[0:4]; + logic [31:0] full_addr_CPTRA_MBOX_AXI_USER_LOCK[0:4]; + assign full_addr_CPTRA_MBOX_AXI_USER_LOCK[0] = `CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_0; + assign full_addr_CPTRA_MBOX_AXI_USER_LOCK[1] = `CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_1; + assign full_addr_CPTRA_MBOX_AXI_USER_LOCK[2] = `CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_2; + assign full_addr_CPTRA_MBOX_AXI_USER_LOCK[3] = `CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_3; + assign full_addr_CPTRA_MBOX_AXI_USER_LOCK[4] = `CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_4; + + logic hit_CPTRA_TRNG_VALID_AXI_USER; + logic [3:0] bus_CPTRA_TRNG_VALID_AXI_USER; + logic [31:0] full_addr_CPTRA_TRNG_VALID_AXI_USER = `CLP_SOC_IFC_REG_CPTRA_TRNG_VALID_AXI_USER; + + logic hit_CPTRA_TRNG_AXI_USER_LOCK; + logic [3:0] bus_CPTRA_TRNG_AXI_USER_LOCK; + logic [31:0] full_addr_CPTRA_TRNG_AXI_USER_LOCK = `CLP_SOC_IFC_REG_CPTRA_TRNG_AXI_USER_LOCK; logic hit_CPTRA_TRNG_DATA[0:11]; logic [3:0] bus_CPTRA_TRNG_DATA[0:11]; @@ -553,13 +553,13 @@ interface soc_ifc_cov_if logic [3:0] bus_CPTRA_WDT_STATUS; logic [31:0] full_addr_CPTRA_WDT_STATUS = `CLP_SOC_IFC_REG_CPTRA_WDT_STATUS; - logic hit_CPTRA_FUSE_VALID_AXI_ID; - logic [3:0] bus_CPTRA_FUSE_VALID_AXI_ID; - logic [31:0] full_addr_CPTRA_FUSE_VALID_AXI_ID = `CLP_SOC_IFC_REG_CPTRA_FUSE_VALID_AXI_ID; + logic hit_CPTRA_FUSE_VALID_AXI_USER; + logic [3:0] bus_CPTRA_FUSE_VALID_AXI_USER; + logic [31:0] full_addr_CPTRA_FUSE_VALID_AXI_USER = `CLP_SOC_IFC_REG_CPTRA_FUSE_VALID_AXI_USER; - logic hit_CPTRA_FUSE_AXI_ID_LOCK; - logic [3:0] bus_CPTRA_FUSE_AXI_ID_LOCK; - logic [31:0] full_addr_CPTRA_FUSE_AXI_ID_LOCK = `CLP_SOC_IFC_REG_CPTRA_FUSE_AXI_ID_LOCK; + logic hit_CPTRA_FUSE_AXI_USER_LOCK; + logic [3:0] bus_CPTRA_FUSE_AXI_USER_LOCK; + logic [31:0] full_addr_CPTRA_FUSE_AXI_USER_LOCK = `CLP_SOC_IFC_REG_CPTRA_FUSE_AXI_USER_LOCK; logic hit_CPTRA_WDT_CFG[0:1]; logic [3:0] bus_CPTRA_WDT_CFG[0:1]; @@ -968,41 +968,41 @@ interface soc_ifc_cov_if // assign hit_CPTRA_SECURITY_STATE = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_SECURITY_STATE[AXI_ADDR_WIDTH-1:0]); // assign bus_CPTRA_SECURITY_STATE = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_SECURITY_STATE}}; - assign hit_CPTRA_MBOX_VALID_AXI_ID[0] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_VALID_AXI_ID[0][18-1:0]); - assign bus_CPTRA_MBOX_VALID_AXI_ID[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_VALID_AXI_ID[0]}}; + assign hit_CPTRA_MBOX_VALID_AXI_USER[0] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_VALID_AXI_USER[0][18-1:0]); + assign bus_CPTRA_MBOX_VALID_AXI_USER[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_VALID_AXI_USER[0]}}; - assign hit_CPTRA_MBOX_VALID_AXI_ID[1] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_VALID_AXI_ID[1][18-1:0]); - assign bus_CPTRA_MBOX_VALID_AXI_ID[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_VALID_AXI_ID[1]}}; + assign hit_CPTRA_MBOX_VALID_AXI_USER[1] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_VALID_AXI_USER[1][18-1:0]); + assign bus_CPTRA_MBOX_VALID_AXI_USER[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_VALID_AXI_USER[1]}}; - assign hit_CPTRA_MBOX_VALID_AXI_ID[2] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_VALID_AXI_ID[2][18-1:0]); - assign bus_CPTRA_MBOX_VALID_AXI_ID[2] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_VALID_AXI_ID[2]}}; + assign hit_CPTRA_MBOX_VALID_AXI_USER[2] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_VALID_AXI_USER[2][18-1:0]); + assign bus_CPTRA_MBOX_VALID_AXI_USER[2] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_VALID_AXI_USER[2]}}; - assign hit_CPTRA_MBOX_VALID_AXI_ID[3] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_VALID_AXI_ID[3][18-1:0]); - assign bus_CPTRA_MBOX_VALID_AXI_ID[3] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_VALID_AXI_ID[3]}}; + assign hit_CPTRA_MBOX_VALID_AXI_USER[3] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_VALID_AXI_USER[3][18-1:0]); + assign bus_CPTRA_MBOX_VALID_AXI_USER[3] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_VALID_AXI_USER[3]}}; - assign hit_CPTRA_MBOX_VALID_AXI_ID[4] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_VALID_AXI_ID[4][18-1:0]); - assign bus_CPTRA_MBOX_VALID_AXI_ID[4] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_VALID_AXI_ID[4]}}; + assign hit_CPTRA_MBOX_VALID_AXI_USER[4] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_VALID_AXI_USER[4][18-1:0]); + assign bus_CPTRA_MBOX_VALID_AXI_USER[4] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_VALID_AXI_USER[4]}}; - assign hit_CPTRA_MBOX_AXI_ID_LOCK[0] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_AXI_ID_LOCK[0][18-1:0]); - assign bus_CPTRA_MBOX_AXI_ID_LOCK[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_AXI_ID_LOCK[0]}}; + assign hit_CPTRA_MBOX_AXI_USER_LOCK[0] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_AXI_USER_LOCK[0][18-1:0]); + assign bus_CPTRA_MBOX_AXI_USER_LOCK[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_AXI_USER_LOCK[0]}}; - assign hit_CPTRA_MBOX_AXI_ID_LOCK[1] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_AXI_ID_LOCK[1][18-1:0]); - assign bus_CPTRA_MBOX_AXI_ID_LOCK[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_AXI_ID_LOCK[1]}}; + assign hit_CPTRA_MBOX_AXI_USER_LOCK[1] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_AXI_USER_LOCK[1][18-1:0]); + assign bus_CPTRA_MBOX_AXI_USER_LOCK[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_AXI_USER_LOCK[1]}}; - assign hit_CPTRA_MBOX_AXI_ID_LOCK[2] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_AXI_ID_LOCK[2][18-1:0]); - assign bus_CPTRA_MBOX_AXI_ID_LOCK[2] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_AXI_ID_LOCK[2]}}; + assign hit_CPTRA_MBOX_AXI_USER_LOCK[2] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_AXI_USER_LOCK[2][18-1:0]); + assign bus_CPTRA_MBOX_AXI_USER_LOCK[2] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_AXI_USER_LOCK[2]}}; - assign hit_CPTRA_MBOX_AXI_ID_LOCK[3] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_AXI_ID_LOCK[3][18-1:0]); - assign bus_CPTRA_MBOX_AXI_ID_LOCK[3] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_AXI_ID_LOCK[3]}}; + assign hit_CPTRA_MBOX_AXI_USER_LOCK[3] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_AXI_USER_LOCK[3][18-1:0]); + assign bus_CPTRA_MBOX_AXI_USER_LOCK[3] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_AXI_USER_LOCK[3]}}; - assign hit_CPTRA_MBOX_AXI_ID_LOCK[4] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_AXI_ID_LOCK[4][18-1:0]); - assign bus_CPTRA_MBOX_AXI_ID_LOCK[4] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_AXI_ID_LOCK[4]}}; + assign hit_CPTRA_MBOX_AXI_USER_LOCK[4] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_AXI_USER_LOCK[4][18-1:0]); + assign bus_CPTRA_MBOX_AXI_USER_LOCK[4] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_AXI_USER_LOCK[4]}}; - assign hit_CPTRA_TRNG_VALID_AXI_ID = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_TRNG_VALID_AXI_ID[AXI_ADDR_WIDTH-1:0]); - assign bus_CPTRA_TRNG_VALID_AXI_ID = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_TRNG_VALID_AXI_ID}}; + assign hit_CPTRA_TRNG_VALID_AXI_USER = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_TRNG_VALID_AXI_USER[AXI_ADDR_WIDTH-1:0]); + assign bus_CPTRA_TRNG_VALID_AXI_USER = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_TRNG_VALID_AXI_USER}}; - assign hit_CPTRA_TRNG_AXI_ID_LOCK = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_TRNG_AXI_ID_LOCK[AXI_ADDR_WIDTH-1:0]); - assign bus_CPTRA_TRNG_AXI_ID_LOCK = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_TRNG_AXI_ID_LOCK}}; + assign hit_CPTRA_TRNG_AXI_USER_LOCK = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_TRNG_AXI_USER_LOCK[AXI_ADDR_WIDTH-1:0]); + assign bus_CPTRA_TRNG_AXI_USER_LOCK = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_TRNG_AXI_USER_LOCK}}; assign hit_CPTRA_TRNG_DATA[0] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_TRNG_DATA[0][18-1:0]); assign bus_CPTRA_TRNG_DATA[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_TRNG_DATA[0]}}; @@ -1112,11 +1112,11 @@ interface soc_ifc_cov_if assign hit_CPTRA_WDT_STATUS = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_WDT_STATUS[AXI_ADDR_WIDTH-1:0]); assign bus_CPTRA_WDT_STATUS = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_WDT_STATUS}}; - assign hit_CPTRA_FUSE_VALID_AXI_ID = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FUSE_VALID_AXI_ID[AXI_ADDR_WIDTH-1:0]); - assign bus_CPTRA_FUSE_VALID_AXI_ID = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_FUSE_VALID_AXI_ID}}; + assign hit_CPTRA_FUSE_VALID_AXI_USER = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FUSE_VALID_AXI_USER[AXI_ADDR_WIDTH-1:0]); + assign bus_CPTRA_FUSE_VALID_AXI_USER = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_FUSE_VALID_AXI_USER}}; - assign hit_CPTRA_FUSE_AXI_ID_LOCK = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FUSE_AXI_ID_LOCK[AXI_ADDR_WIDTH-1:0]); - assign bus_CPTRA_FUSE_AXI_ID_LOCK = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_FUSE_AXI_ID_LOCK}}; + assign hit_CPTRA_FUSE_AXI_USER_LOCK = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FUSE_AXI_USER_LOCK[AXI_ADDR_WIDTH-1:0]); + assign bus_CPTRA_FUSE_AXI_USER_LOCK = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_FUSE_AXI_USER_LOCK}}; assign hit_CPTRA_WDT_CFG[0] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_WDT_CFG[0][18-1:0]); assign bus_CPTRA_WDT_CFG[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_WDT_CFG[0]}}; @@ -1684,77 +1684,77 @@ interface soc_ifc_cov_if // } // endgroup - // ----------------------- COVERGROUP CPTRA_MBOX_VALID_AXI_ID [0:4] ----------------------- - covergroup soc_ifc_CPTRA_MBOX_VALID_AXI_ID_cg (ref logic [3:0] bus_event[0:4]) @(posedge clk); - CPTRA_MBOX_VALID_AXI_ID0_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_VALID_AXI_ID[0]; - bus_CPTRA_MBOX_VALID_AXI_ID0_cp : coverpoint bus_event[0] { + // ----------------------- COVERGROUP CPTRA_MBOX_VALID_AXI_USER [0:4] ----------------------- + covergroup soc_ifc_CPTRA_MBOX_VALID_AXI_USER_cg (ref logic [3:0] bus_event[0:4]) @(posedge clk); + CPTRA_MBOX_VALID_AXI_USER0_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_VALID_AXI_USER[0]; + bus_CPTRA_MBOX_VALID_AXI_USER0_cp : coverpoint bus_event[0] { bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } - CPTRA_MBOX_VALID_AXI_ID1_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_VALID_AXI_ID[1]; - bus_CPTRA_MBOX_VALID_AXI_ID1_cp : coverpoint bus_event[1] { + CPTRA_MBOX_VALID_AXI_USER1_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_VALID_AXI_USER[1]; + bus_CPTRA_MBOX_VALID_AXI_USER1_cp : coverpoint bus_event[1] { bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } - CPTRA_MBOX_VALID_AXI_ID2_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_VALID_AXI_ID[2]; - bus_CPTRA_MBOX_VALID_AXI_ID2_cp : coverpoint bus_event[2] { + CPTRA_MBOX_VALID_AXI_USER2_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_VALID_AXI_USER[2]; + bus_CPTRA_MBOX_VALID_AXI_USER2_cp : coverpoint bus_event[2] { bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } - CPTRA_MBOX_VALID_AXI_ID3_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_VALID_AXI_ID[3]; - bus_CPTRA_MBOX_VALID_AXI_ID3_cp : coverpoint bus_event[3] { + CPTRA_MBOX_VALID_AXI_USER3_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_VALID_AXI_USER[3]; + bus_CPTRA_MBOX_VALID_AXI_USER3_cp : coverpoint bus_event[3] { bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } - CPTRA_MBOX_VALID_AXI_ID4_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_VALID_AXI_ID[4]; - bus_CPTRA_MBOX_VALID_AXI_ID4_cp : coverpoint bus_event[4] { + CPTRA_MBOX_VALID_AXI_USER4_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_VALID_AXI_USER[4]; + bus_CPTRA_MBOX_VALID_AXI_USER4_cp : coverpoint bus_event[4] { bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup - // ----------------------- COVERGROUP CPTRA_MBOX_AXI_ID_LOCK [0:4] ----------------------- - covergroup soc_ifc_CPTRA_MBOX_AXI_ID_LOCK_cg (ref logic [3:0] bus_event[0:4]) @(posedge clk); - CPTRA_MBOX_AXI_ID_LOCK0_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_AXI_ID_LOCK[0]; - bus_CPTRA_MBOX_AXI_ID_LOCK0_cp : coverpoint bus_event[0] { + // ----------------------- COVERGROUP CPTRA_MBOX_AXI_USER_LOCK [0:4] ----------------------- + covergroup soc_ifc_CPTRA_MBOX_AXI_USER_LOCK_cg (ref logic [3:0] bus_event[0:4]) @(posedge clk); + CPTRA_MBOX_AXI_USER_LOCK0_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_AXI_USER_LOCK[0]; + bus_CPTRA_MBOX_AXI_USER_LOCK0_cp : coverpoint bus_event[0] { bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } - CPTRA_MBOX_AXI_ID_LOCK1_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_AXI_ID_LOCK[1]; - bus_CPTRA_MBOX_AXI_ID_LOCK1_cp : coverpoint bus_event[1] { + CPTRA_MBOX_AXI_USER_LOCK1_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_AXI_USER_LOCK[1]; + bus_CPTRA_MBOX_AXI_USER_LOCK1_cp : coverpoint bus_event[1] { bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } - CPTRA_MBOX_AXI_ID_LOCK2_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_AXI_ID_LOCK[2]; - bus_CPTRA_MBOX_AXI_ID_LOCK2_cp : coverpoint bus_event[2] { + CPTRA_MBOX_AXI_USER_LOCK2_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_AXI_USER_LOCK[2]; + bus_CPTRA_MBOX_AXI_USER_LOCK2_cp : coverpoint bus_event[2] { bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } - CPTRA_MBOX_AXI_ID_LOCK3_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_AXI_ID_LOCK[3]; - bus_CPTRA_MBOX_AXI_ID_LOCK3_cp : coverpoint bus_event[3] { + CPTRA_MBOX_AXI_USER_LOCK3_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_AXI_USER_LOCK[3]; + bus_CPTRA_MBOX_AXI_USER_LOCK3_cp : coverpoint bus_event[3] { bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } - CPTRA_MBOX_AXI_ID_LOCK4_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_AXI_ID_LOCK[4]; - bus_CPTRA_MBOX_AXI_ID_LOCK4_cp : coverpoint bus_event[4] { + CPTRA_MBOX_AXI_USER_LOCK4_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_AXI_USER_LOCK[4]; + bus_CPTRA_MBOX_AXI_USER_LOCK4_cp : coverpoint bus_event[4] { bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup - // ----------------------- COVERGROUP CPTRA_TRNG_VALID_AXI_ID ----------------------- - covergroup soc_ifc_CPTRA_TRNG_VALID_AXI_ID_cg (ref logic [3:0] bus_event) @(posedge clk); - CPTRA_TRNG_VALID_AXI_ID_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TRNG_VALID_AXI_ID; - bus_CPTRA_TRNG_VALID_AXI_ID_cp : coverpoint bus_event { + // ----------------------- COVERGROUP CPTRA_TRNG_VALID_AXI_USER ----------------------- + covergroup soc_ifc_CPTRA_TRNG_VALID_AXI_USER_cg (ref logic [3:0] bus_event) @(posedge clk); + CPTRA_TRNG_VALID_AXI_USER_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TRNG_VALID_AXI_USER; + bus_CPTRA_TRNG_VALID_AXI_USER_cp : coverpoint bus_event { bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup - // ----------------------- COVERGROUP CPTRA_TRNG_AXI_ID_LOCK ----------------------- - covergroup soc_ifc_CPTRA_TRNG_AXI_ID_LOCK_cg (ref logic [3:0] bus_event) @(posedge clk); - CPTRA_TRNG_AXI_ID_LOCK_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TRNG_AXI_ID_LOCK; - bus_CPTRA_TRNG_AXI_ID_LOCK_cp : coverpoint bus_event { + // ----------------------- COVERGROUP CPTRA_TRNG_AXI_USER_LOCK ----------------------- + covergroup soc_ifc_CPTRA_TRNG_AXI_USER_LOCK_cg (ref logic [3:0] bus_event) @(posedge clk); + CPTRA_TRNG_AXI_USER_LOCK_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TRNG_AXI_USER_LOCK; + bus_CPTRA_TRNG_AXI_USER_LOCK_cp : coverpoint bus_event { bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } @@ -2020,19 +2020,19 @@ interface soc_ifc_cov_if } endgroup - // ----------------------- COVERGROUP CPTRA_FUSE_VALID_AXI_ID ----------------------- - covergroup soc_ifc_CPTRA_FUSE_VALID_AXI_ID_cg (ref logic [3:0] bus_event) @(posedge clk); - CPTRA_FUSE_VALID_AXI_ID_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FUSE_VALID_AXI_ID; - bus_CPTRA_FUSE_VALID_AXI_ID_cp : coverpoint bus_event { + // ----------------------- COVERGROUP CPTRA_FUSE_VALID_AXI_USER ----------------------- + covergroup soc_ifc_CPTRA_FUSE_VALID_AXI_USER_cg (ref logic [3:0] bus_event) @(posedge clk); + CPTRA_FUSE_VALID_AXI_USER_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FUSE_VALID_AXI_USER; + bus_CPTRA_FUSE_VALID_AXI_USER_cp : coverpoint bus_event { bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup - // ----------------------- COVERGROUP CPTRA_FUSE_AXI_ID_LOCK ----------------------- - covergroup soc_ifc_CPTRA_FUSE_AXI_ID_LOCK_cg (ref logic [3:0] bus_event) @(posedge clk); - CPTRA_FUSE_AXI_ID_LOCK_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FUSE_AXI_ID_LOCK; - bus_CPTRA_FUSE_AXI_ID_LOCK_cp : coverpoint bus_event { + // ----------------------- COVERGROUP CPTRA_FUSE_AXI_USER_LOCK ----------------------- + covergroup soc_ifc_CPTRA_FUSE_AXI_USER_LOCK_cg (ref logic [3:0] bus_event) @(posedge clk); + CPTRA_FUSE_AXI_USER_LOCK_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FUSE_AXI_USER_LOCK; + bus_CPTRA_FUSE_AXI_USER_LOCK_cp : coverpoint bus_event { bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } @@ -3036,10 +3036,10 @@ interface soc_ifc_cov_if soc_ifc_CPTRA_FLOW_STATUS_cg CPTRA_FLOW_STATUS_cg = new(bus_CPTRA_FLOW_STATUS); soc_ifc_CPTRA_RESET_REASON_cg CPTRA_RESET_REASON_cg = new(bus_CPTRA_RESET_REASON); // soc_ifc_CPTRA_SECURITY_STATE_cg CPTRA_SECURITY_STATE_cg = new(bus_CPTRA_SECURITY_STATE); - soc_ifc_CPTRA_MBOX_VALID_AXI_ID_cg CPTRA_MBOX_VALID_AXI_ID_cg = new(bus_CPTRA_MBOX_VALID_AXI_ID); - soc_ifc_CPTRA_MBOX_AXI_ID_LOCK_cg CPTRA_MBOX_AXI_ID_LOCK_cg = new(bus_CPTRA_MBOX_AXI_ID_LOCK); - soc_ifc_CPTRA_TRNG_VALID_AXI_ID_cg CPTRA_TRNG_VALID_AXI_ID_cg = new(bus_CPTRA_TRNG_VALID_AXI_ID); - soc_ifc_CPTRA_TRNG_AXI_ID_LOCK_cg CPTRA_TRNG_AXI_ID_LOCK_cg = new(bus_CPTRA_TRNG_AXI_ID_LOCK); + soc_ifc_CPTRA_MBOX_VALID_AXI_USER_cg CPTRA_MBOX_VALID_AXI_USER_cg = new(bus_CPTRA_MBOX_VALID_AXI_USER); + soc_ifc_CPTRA_MBOX_AXI_USER_LOCK_cg CPTRA_MBOX_AXI_USER_LOCK_cg = new(bus_CPTRA_MBOX_AXI_USER_LOCK); + soc_ifc_CPTRA_TRNG_VALID_AXI_USER_cg CPTRA_TRNG_VALID_AXI_USER_cg = new(bus_CPTRA_TRNG_VALID_AXI_USER); + soc_ifc_CPTRA_TRNG_AXI_USER_LOCK_cg CPTRA_TRNG_AXI_USER_LOCK_cg = new(bus_CPTRA_TRNG_AXI_USER_LOCK); soc_ifc_CPTRA_TRNG_DATA_cg CPTRA_TRNG_DATA_cg = new(bus_CPTRA_TRNG_DATA); soc_ifc_CPTRA_TRNG_CTRL_cg CPTRA_TRNG_CTRL_cg = new(bus_CPTRA_TRNG_CTRL); soc_ifc_CPTRA_TRNG_STATUS_cg CPTRA_TRNG_STATUS_cg = new(bus_CPTRA_TRNG_STATUS); @@ -3060,8 +3060,8 @@ interface soc_ifc_cov_if soc_ifc_CPTRA_WDT_TIMER2_CTRL_cg CPTRA_WDT_TIMER2_CTRL_cg = new(bus_CPTRA_WDT_TIMER2_CTRL); soc_ifc_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_cg CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_cg = new(bus_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD); soc_ifc_CPTRA_WDT_STATUS_cg CPTRA_WDT_STATUS_cg = new(bus_CPTRA_WDT_STATUS); - soc_ifc_CPTRA_FUSE_VALID_AXI_ID_cg CPTRA_FUSE_VALID_AXI_ID_cg = new(bus_CPTRA_FUSE_VALID_AXI_ID); - soc_ifc_CPTRA_FUSE_AXI_ID_LOCK_cg CPTRA_FUSE_AXI_ID_LOCK_cg = new(bus_CPTRA_FUSE_AXI_ID_LOCK); + soc_ifc_CPTRA_FUSE_VALID_AXI_USER_cg CPTRA_FUSE_VALID_AXI_USER_cg = new(bus_CPTRA_FUSE_VALID_AXI_USER); + soc_ifc_CPTRA_FUSE_AXI_USER_LOCK_cg CPTRA_FUSE_AXI_USER_LOCK_cg = new(bus_CPTRA_FUSE_AXI_USER_LOCK); soc_ifc_CPTRA_WDT_CFG_cg CPTRA_WDT_CFG_cg = new(bus_CPTRA_WDT_CFG); soc_ifc_CPTRA_iTRNG_ENTROPY_CONFIG_0_cg CPTRA_iTRNG_ENTROPY_CONFIG_0_cg = new(bus_CPTRA_iTRNG_ENTROPY_CONFIG_0); soc_ifc_CPTRA_iTRNG_ENTROPY_CONFIG_1_cg CPTRA_iTRNG_ENTROPY_CONFIG_1_cg = new(bus_CPTRA_iTRNG_ENTROPY_CONFIG_1); diff --git a/src/soc_ifc/rtl/caliptra_top_reg.h b/src/soc_ifc/rtl/caliptra_top_reg.h index 7ba3d4d55..758457eb6 100644 --- a/src/soc_ifc/rtl/caliptra_top_reg.h +++ b/src/soc_ifc/rtl/caliptra_top_reg.h @@ -22,8 +22,8 @@ #define MBOX_CSR_MBOX_LOCK (0x0) #define MBOX_CSR_MBOX_LOCK_LOCK_LOW (0) #define MBOX_CSR_MBOX_LOCK_LOCK_MASK (0x1) -#define CALIPTRA_TOP_REG_MBOX_CSR_MBOX_ID (0x30020004) -#define MBOX_CSR_MBOX_ID (0x4) +#define CALIPTRA_TOP_REG_MBOX_CSR_MBOX_USER (0x30020004) +#define MBOX_CSR_MBOX_USER (0x4) #define CALIPTRA_TOP_REG_MBOX_CSR_MBOX_CMD (0x30020008) #define MBOX_CSR_MBOX_CMD (0x8) #define CALIPTRA_TOP_REG_MBOX_CSR_MBOX_DLEN (0x3002000c) @@ -196,42 +196,42 @@ #define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE_SCAN_MODE_MASK (0x8) #define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE_RSVD_LOW (4) #define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE_RSVD_MASK (0xfffffff0) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_ID_0 (0x30030048) -#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_ID_0 (0x48) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_ID_1 (0x3003004c) -#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_ID_1 (0x4c) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_ID_2 (0x30030050) -#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_ID_2 (0x50) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_ID_3 (0x30030054) -#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_ID_3 (0x54) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_ID_4 (0x30030058) -#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_ID_4 (0x58) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_0 (0x3003005c) -#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_0 (0x5c) -#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_0_LOCK_LOW (0) -#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_0_LOCK_MASK (0x1) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_1 (0x30030060) -#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_1 (0x60) -#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_1_LOCK_LOW (0) -#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_1_LOCK_MASK (0x1) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_2 (0x30030064) -#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_2 (0x64) -#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_2_LOCK_LOW (0) -#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_2_LOCK_MASK (0x1) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_3 (0x30030068) -#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_3 (0x68) -#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_3_LOCK_LOW (0) -#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_3_LOCK_MASK (0x1) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_4 (0x3003006c) -#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_4 (0x6c) -#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_4_LOCK_LOW (0) -#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_4_LOCK_MASK (0x1) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_VALID_AXI_ID (0x30030070) -#define GENERIC_AND_FUSE_REG_CPTRA_TRNG_VALID_AXI_ID (0x70) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_AXI_ID_LOCK (0x30030074) -#define GENERIC_AND_FUSE_REG_CPTRA_TRNG_AXI_ID_LOCK (0x74) -#define GENERIC_AND_FUSE_REG_CPTRA_TRNG_AXI_ID_LOCK_LOCK_LOW (0) -#define GENERIC_AND_FUSE_REG_CPTRA_TRNG_AXI_ID_LOCK_LOCK_MASK (0x1) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_0 (0x30030048) +#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_0 (0x48) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_1 (0x3003004c) +#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_1 (0x4c) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_2 (0x30030050) +#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_2 (0x50) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_3 (0x30030054) +#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_3 (0x54) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_4 (0x30030058) +#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_4 (0x58) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_0 (0x3003005c) +#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_0 (0x5c) +#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_0_LOCK_LOW (0) +#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_0_LOCK_MASK (0x1) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_1 (0x30030060) +#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_1 (0x60) +#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_1_LOCK_LOW (0) +#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_1_LOCK_MASK (0x1) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_2 (0x30030064) +#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_2 (0x64) +#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_2_LOCK_LOW (0) +#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_2_LOCK_MASK (0x1) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_3 (0x30030068) +#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_3 (0x68) +#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_3_LOCK_LOW (0) +#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_3_LOCK_MASK (0x1) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_4 (0x3003006c) +#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_4 (0x6c) +#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_4_LOCK_LOW (0) +#define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_4_LOCK_MASK (0x1) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_VALID_AXI_USER (0x30030070) +#define GENERIC_AND_FUSE_REG_CPTRA_TRNG_VALID_AXI_USER (0x70) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_AXI_USER_LOCK (0x30030074) +#define GENERIC_AND_FUSE_REG_CPTRA_TRNG_AXI_USER_LOCK (0x74) +#define GENERIC_AND_FUSE_REG_CPTRA_TRNG_AXI_USER_LOCK_LOCK_LOW (0) +#define GENERIC_AND_FUSE_REG_CPTRA_TRNG_AXI_USER_LOCK_LOCK_MASK (0x1) #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_0 (0x30030078) #define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_0 (0x78) #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_1 (0x3003007c) @@ -342,12 +342,12 @@ #define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_MASK (0x1) #define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_LOW (1) #define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_MASK (0x2) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FUSE_VALID_AXI_ID (0x30030108) -#define GENERIC_AND_FUSE_REG_CPTRA_FUSE_VALID_AXI_ID (0x108) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FUSE_AXI_ID_LOCK (0x3003010c) -#define GENERIC_AND_FUSE_REG_CPTRA_FUSE_AXI_ID_LOCK (0x10c) -#define GENERIC_AND_FUSE_REG_CPTRA_FUSE_AXI_ID_LOCK_LOCK_LOW (0) -#define GENERIC_AND_FUSE_REG_CPTRA_FUSE_AXI_ID_LOCK_LOCK_MASK (0x1) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FUSE_VALID_AXI_USER (0x30030108) +#define GENERIC_AND_FUSE_REG_CPTRA_FUSE_VALID_AXI_USER (0x108) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FUSE_AXI_USER_LOCK (0x3003010c) +#define GENERIC_AND_FUSE_REG_CPTRA_FUSE_AXI_USER_LOCK (0x10c) +#define GENERIC_AND_FUSE_REG_CPTRA_FUSE_AXI_USER_LOCK_LOCK_LOW (0) +#define GENERIC_AND_FUSE_REG_CPTRA_FUSE_AXI_USER_LOCK_LOCK_MASK (0x1) #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_CFG_0 (0x30030110) #define GENERIC_AND_FUSE_REG_CPTRA_WDT_CFG_0 (0x110) #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_CFG_1 (0x30030114) diff --git a/src/soc_ifc/rtl/caliptra_top_reg_defines.svh b/src/soc_ifc/rtl/caliptra_top_reg_defines.svh index c29538396..399cc4237 100644 --- a/src/soc_ifc/rtl/caliptra_top_reg_defines.svh +++ b/src/soc_ifc/rtl/caliptra_top_reg_defines.svh @@ -22,8 +22,8 @@ `define MBOX_CSR_MBOX_LOCK (32'h0) `define MBOX_CSR_MBOX_LOCK_LOCK_LOW (0) `define MBOX_CSR_MBOX_LOCK_LOCK_MASK (32'h1) -`define CALIPTRA_TOP_REG_MBOX_CSR_MBOX_ID (32'h30020004) -`define MBOX_CSR_MBOX_ID (32'h4) +`define CALIPTRA_TOP_REG_MBOX_CSR_MBOX_USER (32'h30020004) +`define MBOX_CSR_MBOX_USER (32'h4) `define CALIPTRA_TOP_REG_MBOX_CSR_MBOX_CMD (32'h30020008) `define MBOX_CSR_MBOX_CMD (32'h8) `define CALIPTRA_TOP_REG_MBOX_CSR_MBOX_DLEN (32'h3002000c) @@ -196,42 +196,42 @@ `define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE_SCAN_MODE_MASK (32'h8) `define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE_RSVD_LOW (4) `define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE_RSVD_MASK (32'hfffffff0) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_ID_0 (32'h30030048) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_ID_0 (32'h48) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_ID_1 (32'h3003004c) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_ID_1 (32'h4c) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_ID_2 (32'h30030050) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_ID_2 (32'h50) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_ID_3 (32'h30030054) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_ID_3 (32'h54) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_ID_4 (32'h30030058) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_ID_4 (32'h58) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_0 (32'h3003005c) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_0 (32'h5c) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_0_LOCK_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_0_LOCK_MASK (32'h1) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_1 (32'h30030060) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_1 (32'h60) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_1_LOCK_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_1_LOCK_MASK (32'h1) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_2 (32'h30030064) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_2 (32'h64) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_2_LOCK_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_2_LOCK_MASK (32'h1) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_3 (32'h30030068) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_3 (32'h68) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_3_LOCK_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_3_LOCK_MASK (32'h1) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_4 (32'h3003006c) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_4 (32'h6c) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_4_LOCK_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_ID_LOCK_4_LOCK_MASK (32'h1) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_VALID_AXI_ID (32'h30030070) -`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_VALID_AXI_ID (32'h70) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_AXI_ID_LOCK (32'h30030074) -`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_AXI_ID_LOCK (32'h74) -`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_AXI_ID_LOCK_LOCK_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_AXI_ID_LOCK_LOCK_MASK (32'h1) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_0 (32'h30030048) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_0 (32'h48) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_1 (32'h3003004c) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_1 (32'h4c) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_2 (32'h30030050) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_2 (32'h50) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_3 (32'h30030054) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_3 (32'h54) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_4 (32'h30030058) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_4 (32'h58) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_0 (32'h3003005c) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_0 (32'h5c) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_0_LOCK_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_0_LOCK_MASK (32'h1) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_1 (32'h30030060) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_1 (32'h60) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_1_LOCK_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_1_LOCK_MASK (32'h1) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_2 (32'h30030064) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_2 (32'h64) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_2_LOCK_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_2_LOCK_MASK (32'h1) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_3 (32'h30030068) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_3 (32'h68) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_3_LOCK_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_3_LOCK_MASK (32'h1) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_4 (32'h3003006c) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_4 (32'h6c) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_4_LOCK_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_4_LOCK_MASK (32'h1) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_VALID_AXI_USER (32'h30030070) +`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_VALID_AXI_USER (32'h70) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_AXI_USER_LOCK (32'h30030074) +`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_AXI_USER_LOCK (32'h74) +`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_AXI_USER_LOCK_LOCK_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_AXI_USER_LOCK_LOCK_MASK (32'h1) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_0 (32'h30030078) `define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_0 (32'h78) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_1 (32'h3003007c) @@ -342,12 +342,12 @@ `define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_MASK (32'h1) `define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_LOW (1) `define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_MASK (32'h2) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FUSE_VALID_AXI_ID (32'h30030108) -`define GENERIC_AND_FUSE_REG_CPTRA_FUSE_VALID_AXI_ID (32'h108) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FUSE_AXI_ID_LOCK (32'h3003010c) -`define GENERIC_AND_FUSE_REG_CPTRA_FUSE_AXI_ID_LOCK (32'h10c) -`define GENERIC_AND_FUSE_REG_CPTRA_FUSE_AXI_ID_LOCK_LOCK_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_FUSE_AXI_ID_LOCK_LOCK_MASK (32'h1) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FUSE_VALID_AXI_USER (32'h30030108) +`define GENERIC_AND_FUSE_REG_CPTRA_FUSE_VALID_AXI_USER (32'h108) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FUSE_AXI_USER_LOCK (32'h3003010c) +`define GENERIC_AND_FUSE_REG_CPTRA_FUSE_AXI_USER_LOCK (32'h10c) +`define GENERIC_AND_FUSE_REG_CPTRA_FUSE_AXI_USER_LOCK_LOCK_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_FUSE_AXI_USER_LOCK_LOCK_MASK (32'h1) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_CFG_0 (32'h30030110) `define GENERIC_AND_FUSE_REG_CPTRA_WDT_CFG_0 (32'h110) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_CFG_1 (32'h30030114) diff --git a/src/soc_ifc/rtl/mbox.sv b/src/soc_ifc/rtl/mbox.sv index a2e65c25e..db77658f3 100644 --- a/src/soc_ifc/rtl/mbox.sv +++ b/src/soc_ifc/rtl/mbox.sv @@ -62,7 +62,7 @@ module mbox output logic soc_mbox_data_avail, output logic soc_req_mbox_lock, output mbox_protocol_error_t mbox_protocol_error, - output logic mbox_inv_axi_id_axs, + output logic mbox_inv_axi_user_axs, //DMI reg access input logic dmi_inc_rdptr, @@ -159,7 +159,7 @@ assign mbox_error = read_error | write_error; //2) SoC requests are valid if soc has lock and it's the AXI ID that locked it always_comb valid_requester = hwif_out.mbox_lock.lock.value & ((~req_data.soc_req & (~soc_has_lock || (mbox_fsm_ps == MBOX_EXECUTE_UC))) | - ( req_data.soc_req & soc_has_lock & (req_data.id == hwif_out.mbox_id.id.value[SOC_IFC_ID_W-1:0]))); + ( req_data.soc_req & soc_has_lock & (req_data.user == hwif_out.mbox_user.user.value[SOC_IFC_USER_W-1:0]))); //Determine if this is a valid request from the receiver side always_comb valid_receiver = hwif_out.mbox_lock.lock.value & @@ -389,12 +389,12 @@ always_comb begin : mbox_fsm_combo endcase end -// Any ol' AXI_ID is fine for reg-reads (except dataout) +// Any ol' AXI_USER is fine for reg-reads (except dataout) // NOTE: This only captures accesses by AXI agents that are valid, but do not // have lock. Invalid agent accesses are blocked by arbiter. -assign mbox_inv_axi_id_axs = req_dv && req_data.soc_req && !req_hold && - !valid_requester && !valid_receiver && - (req_data.write || hwif_out.mbox_dataout.dataout.swacc); +assign mbox_inv_axi_user_axs = req_dv && req_data.soc_req && !req_hold && + !valid_requester && !valid_receiver && + (req_data.write || hwif_out.mbox_dataout.dataout.swacc); //increment read ptr only if its allowed @@ -547,7 +547,7 @@ always_comb mbox_rd_full_nxt = rst_mbox_rdptr ? '0 : inc_rdptr & (mbox_rdptr == always_comb soc_req_mbox_lock = hwif_out.mbox_lock.lock.value & ~soc_has_lock & hwif_out.mbox_lock.lock.swmod & req_data.soc_req; always_comb hwif_in.cptra_rst_b = rst_b; -always_comb hwif_in.mbox_id.id.next = 32'(req_data.id); +always_comb hwif_in.mbox_user.user.next = 32'(req_data.user); always_comb hwif_in.mbox_status.mbox_fsm_ps.next = mbox_fsm_ps; always_comb hwif_in.soc_req = req_data.soc_req; diff --git a/src/soc_ifc/rtl/mbox_csr.rdl b/src/soc_ifc/rtl/mbox_csr.rdl index b6a710714..20db8a635 100644 --- a/src/soc_ifc/rtl/mbox_csr.rdl +++ b/src/soc_ifc/rtl/mbox_csr.rdl @@ -39,15 +39,15 @@ addrmap mbox_csr { field {rset; sw=r; hw=r; hwclr=true; precedence=hw; swmod=true;} lock=0; } mbox_lock; - // ID register - // store AXI ID from interface when setting lock + // USER register + // store AXI USER from interface when setting lock reg { - name="Mailbox ID"; - desc="Stores the AXI ID that locked the mailbox + name="Mailbox USER"; + desc="Stores the AXI USER that locked the mailbox [br]Caliptra Access: RO [br]SOC Access: RO"; - field {sw=r; hw=rw; we=lock_set;} id[32]=0; - } mbox_id; + field {sw=r; hw=rw; we=lock_set;} user[32]=0; + } mbox_user; reg { name="Mailbox Command"; diff --git a/src/soc_ifc/rtl/mbox_csr.sv b/src/soc_ifc/rtl/mbox_csr.sv index d99ba04d7..c58f79ea2 100644 --- a/src/soc_ifc/rtl/mbox_csr.sv +++ b/src/soc_ifc/rtl/mbox_csr.sv @@ -67,7 +67,7 @@ module mbox_csr ( //-------------------------------------------------------------------------- typedef struct packed{ logic mbox_lock; - logic mbox_id; + logic mbox_user; logic mbox_cmd; logic mbox_dlen; logic mbox_datain; @@ -84,7 +84,7 @@ module mbox_csr ( always_comb begin decoded_reg_strb.mbox_lock = cpuif_req_masked & (cpuif_addr == 6'h0); - decoded_reg_strb.mbox_id = cpuif_req_masked & (cpuif_addr == 6'h4); + decoded_reg_strb.mbox_user = cpuif_req_masked & (cpuif_addr == 6'h4); decoded_reg_strb.mbox_cmd = cpuif_req_masked & (cpuif_addr == 6'h8); decoded_reg_strb.mbox_dlen = cpuif_req_masked & (cpuif_addr == 6'hc); decoded_reg_strb.mbox_datain = cpuif_req_masked & (cpuif_addr == 6'h10); @@ -114,8 +114,8 @@ module mbox_csr ( struct packed{ logic [31:0] next; logic load_next; - } id; - } mbox_id; + } user; + } mbox_user; struct packed{ struct packed{ logic [31:0] next; @@ -190,8 +190,8 @@ module mbox_csr ( struct packed{ struct packed{ logic [31:0] value; - } id; - } mbox_id; + } user; + } mbox_user; struct packed{ struct packed{ logic [31:0] value; @@ -270,27 +270,27 @@ module mbox_csr ( end assign hwif_out.mbox_lock.lock.value = field_storage.mbox_lock.lock.value; assign hwif_out.mbox_lock.lock.swmod = decoded_reg_strb.mbox_lock && !decoded_req_is_wr; - // Field: mbox_csr.mbox_id.id + // Field: mbox_csr.mbox_user.user always_comb begin automatic logic [31:0] next_c; automatic logic load_next_c; - next_c = field_storage.mbox_id.id.value; + next_c = field_storage.mbox_user.user.value; load_next_c = '0; if(hwif_in.lock_set) begin // HW Write - we - next_c = hwif_in.mbox_id.id.next; + next_c = hwif_in.mbox_user.user.next; load_next_c = '1; end - field_combo.mbox_id.id.next = next_c; - field_combo.mbox_id.id.load_next = load_next_c; + field_combo.mbox_user.user.next = next_c; + field_combo.mbox_user.user.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.mbox_id.id.value <= 32'h0; - end else if(field_combo.mbox_id.id.load_next) begin - field_storage.mbox_id.id.value <= field_combo.mbox_id.id.next; + field_storage.mbox_user.user.value <= 32'h0; + end else if(field_combo.mbox_user.user.load_next) begin + field_storage.mbox_user.user.value <= field_combo.mbox_user.user.next; end end - assign hwif_out.mbox_id.id.value = field_storage.mbox_id.id.value; + assign hwif_out.mbox_user.user.value = field_storage.mbox_user.user.value; // Field: mbox_csr.mbox_cmd.command always_comb begin automatic logic [31:0] next_c; @@ -585,7 +585,7 @@ module mbox_csr ( logic [9-1:0][31:0] readback_array; assign readback_array[0][0:0] = (decoded_reg_strb.mbox_lock && !decoded_req_is_wr) ? field_storage.mbox_lock.lock.value : '0; assign readback_array[0][31:1] = '0; - assign readback_array[1][31:0] = (decoded_reg_strb.mbox_id && !decoded_req_is_wr) ? field_storage.mbox_id.id.value : '0; + assign readback_array[1][31:0] = (decoded_reg_strb.mbox_user && !decoded_req_is_wr) ? field_storage.mbox_user.user.value : '0; assign readback_array[2][31:0] = (decoded_reg_strb.mbox_cmd && !decoded_req_is_wr) ? field_storage.mbox_cmd.command.value : '0; assign readback_array[3][31:0] = (decoded_reg_strb.mbox_dlen && !decoded_req_is_wr) ? field_storage.mbox_dlen.length.value : '0; assign readback_array[4][31:0] = (decoded_reg_strb.mbox_datain && !decoded_req_is_wr) ? field_storage.mbox_datain.datain.value : '0; diff --git a/src/soc_ifc/rtl/mbox_csr_pkg.sv b/src/soc_ifc/rtl/mbox_csr_pkg.sv index 13341ef52..39f775c03 100644 --- a/src/soc_ifc/rtl/mbox_csr_pkg.sv +++ b/src/soc_ifc/rtl/mbox_csr_pkg.sv @@ -16,11 +16,11 @@ package mbox_csr_pkg; typedef struct packed{ logic [31:0] next; - } mbox_csr__mbox_id__id__in_t; + } mbox_csr__mbox_user__user__in_t; typedef struct packed{ - mbox_csr__mbox_id__id__in_t id; - } mbox_csr__mbox_id__in_t; + mbox_csr__mbox_user__user__in_t user; + } mbox_csr__mbox_user__in_t; typedef struct packed{ logic [31:0] next; @@ -80,7 +80,7 @@ package mbox_csr_pkg; logic valid_requester; logic valid_receiver; mbox_csr__mbox_lock__in_t mbox_lock; - mbox_csr__mbox_id__in_t mbox_id; + mbox_csr__mbox_user__in_t mbox_user; mbox_csr__mbox_dataout__in_t mbox_dataout; mbox_csr__mbox_execute__in_t mbox_execute; mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__in_t mbox_status; @@ -97,11 +97,11 @@ package mbox_csr_pkg; typedef struct packed{ logic [31:0] value; - } mbox_csr__mbox_id__id__out_t; + } mbox_csr__mbox_user__user__out_t; typedef struct packed{ - mbox_csr__mbox_id__id__out_t id; - } mbox_csr__mbox_id__out_t; + mbox_csr__mbox_user__user__out_t user; + } mbox_csr__mbox_user__out_t; typedef struct packed{ logic swmod; @@ -190,7 +190,7 @@ package mbox_csr_pkg; typedef struct packed{ mbox_csr__mbox_lock__out_t mbox_lock; - mbox_csr__mbox_id__out_t mbox_id; + mbox_csr__mbox_user__out_t mbox_user; mbox_csr__mbox_cmd__out_t mbox_cmd; mbox_csr__mbox_dlen__out_t mbox_dlen; mbox_csr__mbox_datain__out_t mbox_datain; diff --git a/src/soc_ifc/rtl/mbox_csr_uvm.sv b/src/soc_ifc/rtl/mbox_csr_uvm.sv index ee50564b5..760853a1a 100644 --- a/src/soc_ifc/rtl/mbox_csr_uvm.sv +++ b/src/soc_ifc/rtl/mbox_csr_uvm.sv @@ -34,17 +34,17 @@ package mbox_csr_uvm; endfunction : build endclass : mbox_csr__mbox_lock - // Reg - mbox_csr::mbox_id - class mbox_csr__mbox_id extends uvm_reg; + // Reg - mbox_csr::mbox_user + class mbox_csr__mbox_user extends uvm_reg; protected uvm_reg_data_t m_current; protected uvm_reg_data_t m_data; protected bit m_is_read; - mbox_csr__mbox_id_bit_cg id_bit_cg[32]; - mbox_csr__mbox_id_fld_cg fld_cg; - rand uvm_reg_field id; + mbox_csr__mbox_user_bit_cg user_bit_cg[32]; + mbox_csr__mbox_user_fld_cg fld_cg; + rand uvm_reg_field user; - function new(string name = "mbox_csr__mbox_id"); + function new(string name = "mbox_csr__mbox_user"); super.new(name, 32, build_coverage(UVM_CVR_ALL)); endfunction : new extern virtual function void sample_values(); @@ -54,15 +54,15 @@ package mbox_csr_uvm; uvm_reg_map map); virtual function void build(); - this.id = new("id"); - this.id.configure(this, 32, 0, "RO", 1, 'h0, 1, 1, 0); + this.user = new("user"); + this.user.configure(this, 32, 0, "RO", 1, 'h0, 1, 1, 0); if (has_coverage(UVM_CVR_REG_BITS)) begin - foreach(id_bit_cg[bt]) id_bit_cg[bt] = new(); + foreach(user_bit_cg[bt]) user_bit_cg[bt] = new(); end if (has_coverage(UVM_CVR_FIELD_VALS)) fld_cg = new(); endfunction : build - endclass : mbox_csr__mbox_id + endclass : mbox_csr__mbox_user // Reg - mbox_csr::mbox_cmd class mbox_csr__mbox_cmd extends uvm_reg; @@ -302,7 +302,7 @@ package mbox_csr_uvm; // Addrmap - mbox_csr class mbox_csr extends uvm_reg_block; rand mbox_csr__mbox_lock mbox_lock; - rand mbox_csr__mbox_id mbox_id; + rand mbox_csr__mbox_user mbox_user; rand mbox_csr__mbox_cmd mbox_cmd; rand mbox_csr__mbox_dlen mbox_dlen; rand mbox_csr__mbox_datain mbox_datain; @@ -322,11 +322,11 @@ package mbox_csr_uvm; this.mbox_lock.build(); this.default_map.add_reg(this.mbox_lock, 'h0); - this.mbox_id = new("mbox_id"); - this.mbox_id.configure(this); + this.mbox_user = new("mbox_user"); + this.mbox_user.configure(this); - this.mbox_id.build(); - this.default_map.add_reg(this.mbox_id, 'h4); + this.mbox_user.build(); + this.default_map.add_reg(this.mbox_user, 'h4); this.mbox_cmd = new("mbox_cmd"); this.mbox_cmd.configure(this); diff --git a/src/soc_ifc/rtl/soc_ifc_arb.sv b/src/soc_ifc/rtl/soc_ifc_arb.sv index 36913a531..7451ca887 100644 --- a/src/soc_ifc/rtl/soc_ifc_arb.sv +++ b/src/soc_ifc/rtl/soc_ifc_arb.sv @@ -15,13 +15,13 @@ module soc_ifc_arb import soc_ifc_pkg::*; #( - parameter AXI_ID_WIDTH = 32 + parameter AXI_USER_WIDTH = 32 )( input logic clk, input logic rst_b, - input logic [4:0][AXI_ID_WIDTH-1:0] valid_mbox_ids, - input logic valid_fuse_id, + input logic [4:0][AXI_USER_WIDTH-1:0] valid_mbox_users, + input logic valid_fuse_user, //UC inf input logic uc_req_dv, output logic uc_req_hold, @@ -104,7 +104,7 @@ logic uc_reg_req_ip; logic uc_sha_req_ip; logic uc_dma_req_ip; -//filter mailbox requests by id +//filter mailbox requests by user logic valid_mbox_req; @@ -157,7 +157,7 @@ always_comb soc_mbox_req = (valid_mbox_req & (soc_req_data.addr inside {[MBOX_RE //Ensure that requests to fuse block match the appropriate id value always_comb uc_reg_req = (uc_req_dv & (uc_req_data.addr inside {[SOC_IFC_REG_START_ADDR:SOC_IFC_REG_END_ADDR]})); always_comb soc_reg_req = (soc_req_dv & (soc_req_data.addr inside {[SOC_IFC_REG_START_ADDR:SOC_IFC_REG_END_ADDR]}) & - (~(soc_req_data.addr inside {[SOC_IFC_FUSE_START_ADDR:SOC_IFC_FUSE_END_ADDR]}) | valid_fuse_id)); + (~(soc_req_data.addr inside {[SOC_IFC_FUSE_START_ADDR:SOC_IFC_FUSE_END_ADDR]}) | valid_fuse_user)); //Requests to SHA always_comb uc_sha_req = (uc_req_dv & (uc_req_data.addr inside {[SHA_REG_START_ADDR:SHA_REG_END_ADDR]})); @@ -167,15 +167,15 @@ always_comb soc_sha_req = (soc_req_dv & (soc_req_data.addr inside {[SHA_REG_STAR always_comb uc_dma_req = (uc_req_dv & (uc_req_data.addr inside {[DMA_REG_START_ADDR:DMA_REG_END_ADDR]})); always_comb soc_dma_req = (soc_req_dv & (soc_req_data.addr inside {[DMA_REG_START_ADDR:DMA_REG_END_ADDR]})); -//Check if SoC request is coming from a valid id -//There are 5 valid id registers, check if id attribute matches any of them -//Check if id matches Default Valid id parameter - this id value is always valid +//Check if SoC request is coming from a valid user +//There are 5 valid user registers, check if user attribute matches any of them +//Check if user matches Default Valid user parameter - this user value is always valid always_comb begin valid_mbox_req = '0; for (int i=0; i < 5; i++) begin - valid_mbox_req |= soc_req_dv & (soc_req_data.id == valid_mbox_ids[i]); + valid_mbox_req |= soc_req_dv & (soc_req_data.user == valid_mbox_users[i]); end - valid_mbox_req |= soc_req_dv & (soc_req_data.id == CPTRA_DEF_MBOX_VALID_AXI_ID[SOC_IFC_ID_W-1:0]); + valid_mbox_req |= soc_req_dv & (soc_req_data.user == CPTRA_DEF_MBOX_VALID_AXI_USER[SOC_IFC_USER_W-1:0]); end //check for collisions diff --git a/src/soc_ifc/rtl/soc_ifc_external_reg.rdl b/src/soc_ifc/rtl/soc_ifc_external_reg.rdl index 7bcbb7dad..8c8de8d95 100644 --- a/src/soc_ifc/rtl/soc_ifc_external_reg.rdl +++ b/src/soc_ifc/rtl/soc_ifc_external_reg.rdl @@ -165,46 +165,46 @@ reg { } CPTRA_SECURITY_STATE; reg { - name = "Valid ID Registers"; - desc = "Valid AXI ID attributes for requests from SoC AXI Interface. Only valid once LOCK is set. + name = "Valid USER Registers"; + desc = "Valid AXI USER attributes for requests from SoC AXI Interface. Only valid once LOCK is set. [br]Caliptra Access: RW [br]SOC Access: RW - Read-Only once locked by AXI_ID_LOCK."; - field {sw=rw; hw=r; swwel;resetsignal = cptra_rst_b;} AXI_ID[32]=0xFFFF_FFFF; - } CPTRA_MBOX_VALID_AXI_ID[5]; + Read-Only once locked by AXI_USER_LOCK."; + field {sw=rw; hw=r; swwel;resetsignal = cptra_rst_b;} AXI_USER[32]=0xFFFF_FFFF; + } CPTRA_MBOX_VALID_AXI_USER[5]; //FIXME: Should LOCK be W1 here? reg { name = "Valid ID Register Lock"; - desc = "Valid AXI_ID attributes for requests from SoC AXI Interface. - [br]Each bit corresponds to locking the associated MBOX_VALID_AXI_ID register. - [br]Associated MBOX_VALID_AXI_ID register is only valid once locked by this bit. + desc = "Valid AXI_USER attributes for requests from SoC AXI Interface. + [br]Each bit corresponds to locking the associated MBOX_VALID_AXI_USER register. + [br]Associated MBOX_VALID_AXI_USER register is only valid once locked by this bit. [br]Caliptra Access: RW [br]SOC Access: RW [br]Read-Only once locked."; field {sw=rw; hw=r; swwel; resetsignal = cptra_rst_b;} LOCK=0; - } CPTRA_MBOX_AXI_ID_LOCK[5]; + } CPTRA_MBOX_AXI_USER_LOCK[5]; reg { - name = "Valid ID for TRNG"; - desc = "Valid AXI ID attributes for TRNG on SoC AXI Interface. Only valid once LOCK is set. + name = "Valid USER for TRNG"; + desc = "Valid AXI USER attributes for TRNG on SoC AXI Interface. Only valid once LOCK is set. [br]Caliptra Access: RW [br]SOC Access: RW - [br]Read-Only once locked by TRNG_AXI_ID_LOCK."; - field {sw=rw; hw=r; swwel; resetsignal = cptra_rst_b;} AXI_ID[32]=0xFFFF_FFFF; - } CPTRA_TRNG_VALID_AXI_ID; + [br]Read-Only once locked by TRNG_AXI_USER_LOCK."; + field {sw=rw; hw=r; swwel; resetsignal = cptra_rst_b;} AXI_USER[32]=0xFFFF_FFFF; + } CPTRA_TRNG_VALID_AXI_USER; reg { - name = "Valid ID for TRNG AXI_ID Lock"; - desc = "Valid AXI ID attributes for requests from SoC AXI Interface. - [br]Each bit corresponds to locking the associated TRNG_VALID_AXI_ID register. - [br]Associated TRNG_VALID_AXI_ID register is only valid once locked by this bit. + name = "Valid ID for TRNG AXI_USER Lock"; + desc = "Valid AXI USER attributes for requests from SoC AXI Interface. + [br]Each bit corresponds to locking the associated TRNG_VALID_AXI_USER register. + [br]Associated TRNG_VALID_AXI_USER register is only valid once locked by this bit. [br]Caliptra FW RW access for survivability but cannot unlock once locked [br]Caliptra Access: RW [br]SOC Access: RW [br]Read-Only once locked."; field {sw=rw; hw=r; swwel; resetsignal=cptra_rst_b;} LOCK=0; - } CPTRA_TRNG_AXI_ID_LOCK; + } CPTRA_TRNG_AXI_USER_LOCK; reg { name = "TRNG Data"; @@ -397,25 +397,25 @@ reg { } CPTRA_WDT_STATUS; reg { - name = "Valid ID for FUSE"; - desc = "Valid AXI ID attributes for FUSE on SoC AXI Interface. Only valid once LOCK is set. + name = "Valid USER for FUSE"; + desc = "Valid AXI USER attributes for FUSE on SoC AXI Interface. Only valid once LOCK is set. [br]Caliptra Access: RW [br]SOC Access: RW - [br]Read-Only once locked by FUSE_AXI_ID_LOCK."; - field {sw=rw; hw=r; swwel; resetsignal = cptra_pwrgood;} AXI_ID[32]=0xFFFF_FFFF; - } CPTRA_FUSE_VALID_AXI_ID; + [br]Read-Only once locked by FUSE_AXI_USER_LOCK."; + field {sw=rw; hw=r; swwel; resetsignal = cptra_pwrgood;} AXI_USER[32]=0xFFFF_FFFF; + } CPTRA_FUSE_VALID_AXI_USER; reg { - name = "Valid ID for FUSE AXI_ID Lock"; - desc = "Valid AXI_ID attributes for requests from SoC AXI Interface. - [br]Each bit corresponds to locking the associated FUSE_VALID_AXI_ID register. - [br]Associated FUSE_VALID_AXI_ID register is only valid once locked by this bit. + name = "Valid USER for FUSE AXI_USER Lock"; + desc = "Valid AXI_USER attributes for requests from SoC AXI Interface. + [br]Each bit corresponds to locking the associated FUSE_VALID_AXI_USER register. + [br]Associated FUSE_VALID_AXI_USER register is only valid once locked by this bit. [br]Caliptra FW RW access for survivability but cannot unlock once locked [br]Caliptra Access: RW [br]SOC Access: RW [br]Read-Only once locked."; field {sw=rw; hw=r; swwel; resetsignal=cptra_pwrgood;} LOCK=0; - } CPTRA_FUSE_AXI_ID_LOCK; + } CPTRA_FUSE_AXI_USER_LOCK; reg { name = "Caliptra WDT1 Config"; diff --git a/src/soc_ifc/rtl/soc_ifc_pkg.sv b/src/soc_ifc/rtl/soc_ifc_pkg.sv index 96bafb17c..11a548638 100644 --- a/src/soc_ifc/rtl/soc_ifc_pkg.sv +++ b/src/soc_ifc/rtl/soc_ifc_pkg.sv @@ -57,14 +57,14 @@ package soc_ifc_pkg; parameter SOC_IFC_FUSE_START_ADDR = SOC_IFC_REG_START_ADDR + 32'h0000_0200; parameter SOC_IFC_FUSE_END_ADDR = SOC_IFC_REG_START_ADDR + 32'h0000_05FF; - //Valid AXI_ID - //Lock the AXI_ID values from integration time - parameter [4:0] CPTRA_SET_MBOX_AXI_ID_INTEG = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}; - parameter [4:0][31:0] CPTRA_MBOX_VALID_AXI_ID = {32'h4444_4444, 32'h3333_3333, 32'h2222_2222, 32'h1111_1111, 32'h0000_0000}; - parameter [31:0] CPTRA_DEF_MBOX_VALID_AXI_ID = 32'hFFFF_FFFF; + //Valid AXI_USER + //Lock the AXI_USER values from integration time + parameter [4:0] CPTRA_SET_MBOX_AXI_USER_INTEG = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}; + parameter [4:0][31:0] CPTRA_MBOX_VALID_AXI_USER = {32'h4444_4444, 32'h3333_3333, 32'h2222_2222, 32'h1111_1111, 32'h0000_0000}; + parameter [31:0] CPTRA_DEF_MBOX_VALID_AXI_USER = 32'hFFFF_FFFF; - parameter CPTRA_SET_FUSE_AXI_ID_INTEG = 1'b0; - parameter [31:0] CPTRA_FUSE_VALID_AXI_ID = 32'h0000_0000; + parameter CPTRA_SET_FUSE_AXI_USER_INTEG = 1'b0; + parameter [31:0] CPTRA_FUSE_VALID_AXI_USER = 32'h0000_0000; //DMI Register encodings //Read only registers @@ -129,7 +129,7 @@ package soc_ifc_pkg; logic [SOC_IFC_ADDR_W-1:0] addr; logic [SOC_IFC_DATA_W-1:0] wdata; logic [SOC_IFC_DATA_W/8-1:0] wstrb; -// logic [SOC_IFC_USER_W-1:0] user; + logic [SOC_IFC_USER_W-1:0] user; logic [SOC_IFC_ID_W -1:0] id; logic write; logic soc_req; diff --git a/src/soc_ifc/rtl/soc_ifc_reg.sv b/src/soc_ifc/rtl/soc_ifc_reg.sv index d179af23c..c8abb9e7c 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg.sv +++ b/src/soc_ifc/rtl/soc_ifc_reg.sv @@ -77,10 +77,10 @@ module soc_ifc_reg ( logic CPTRA_FLOW_STATUS; logic CPTRA_RESET_REASON; logic CPTRA_SECURITY_STATE; - logic [5-1:0]CPTRA_MBOX_VALID_AXI_ID; - logic [5-1:0]CPTRA_MBOX_AXI_ID_LOCK; - logic CPTRA_TRNG_VALID_AXI_ID; - logic CPTRA_TRNG_AXI_ID_LOCK; + logic [5-1:0]CPTRA_MBOX_VALID_AXI_USER; + logic [5-1:0]CPTRA_MBOX_AXI_USER_LOCK; + logic CPTRA_TRNG_VALID_AXI_USER; + logic CPTRA_TRNG_AXI_USER_LOCK; logic [12-1:0]CPTRA_TRNG_DATA; logic CPTRA_TRNG_CTRL; logic CPTRA_TRNG_STATUS; @@ -101,8 +101,8 @@ module soc_ifc_reg ( logic CPTRA_WDT_TIMER2_CTRL; logic [2-1:0]CPTRA_WDT_TIMER2_TIMEOUT_PERIOD; logic CPTRA_WDT_STATUS; - logic CPTRA_FUSE_VALID_AXI_ID; - logic CPTRA_FUSE_AXI_ID_LOCK; + logic CPTRA_FUSE_VALID_AXI_USER; + logic CPTRA_FUSE_AXI_USER_LOCK; logic [2-1:0]CPTRA_WDT_CFG; logic CPTRA_iTRNG_ENTROPY_CONFIG_0; logic CPTRA_iTRNG_ENTROPY_CONFIG_1; @@ -195,13 +195,13 @@ module soc_ifc_reg ( decoded_reg_strb.CPTRA_RESET_REASON = cpuif_req_masked & (cpuif_addr == 12'h40); decoded_reg_strb.CPTRA_SECURITY_STATE = cpuif_req_masked & (cpuif_addr == 12'h44); for(int i0=0; i0<5; i0++) begin - decoded_reg_strb.CPTRA_MBOX_VALID_AXI_ID[i0] = cpuif_req_masked & (cpuif_addr == 12'h48 + i0*12'h4); + decoded_reg_strb.CPTRA_MBOX_VALID_AXI_USER[i0] = cpuif_req_masked & (cpuif_addr == 12'h48 + i0*12'h4); end for(int i0=0; i0<5; i0++) begin - decoded_reg_strb.CPTRA_MBOX_AXI_ID_LOCK[i0] = cpuif_req_masked & (cpuif_addr == 12'h5c + i0*12'h4); + decoded_reg_strb.CPTRA_MBOX_AXI_USER_LOCK[i0] = cpuif_req_masked & (cpuif_addr == 12'h5c + i0*12'h4); end - decoded_reg_strb.CPTRA_TRNG_VALID_AXI_ID = cpuif_req_masked & (cpuif_addr == 12'h70); - decoded_reg_strb.CPTRA_TRNG_AXI_ID_LOCK = cpuif_req_masked & (cpuif_addr == 12'h74); + decoded_reg_strb.CPTRA_TRNG_VALID_AXI_USER = cpuif_req_masked & (cpuif_addr == 12'h70); + decoded_reg_strb.CPTRA_TRNG_AXI_USER_LOCK = cpuif_req_masked & (cpuif_addr == 12'h74); for(int i0=0; i0<12; i0++) begin decoded_reg_strb.CPTRA_TRNG_DATA[i0] = cpuif_req_masked & (cpuif_addr == 12'h78 + i0*12'h4); end @@ -234,8 +234,8 @@ module soc_ifc_reg ( decoded_reg_strb.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i0] = cpuif_req_masked & (cpuif_addr == 12'hfc + i0*12'h4); end decoded_reg_strb.CPTRA_WDT_STATUS = cpuif_req_masked & (cpuif_addr == 12'h104); - decoded_reg_strb.CPTRA_FUSE_VALID_AXI_ID = cpuif_req_masked & (cpuif_addr == 12'h108); - decoded_reg_strb.CPTRA_FUSE_AXI_ID_LOCK = cpuif_req_masked & (cpuif_addr == 12'h10c); + decoded_reg_strb.CPTRA_FUSE_VALID_AXI_USER = cpuif_req_masked & (cpuif_addr == 12'h108); + decoded_reg_strb.CPTRA_FUSE_AXI_USER_LOCK = cpuif_req_masked & (cpuif_addr == 12'h10c); for(int i0=0; i0<2; i0++) begin decoded_reg_strb.CPTRA_WDT_CFG[i0] = cpuif_req_masked & (cpuif_addr == 12'h110 + i0*12'h4); end @@ -440,26 +440,26 @@ module soc_ifc_reg ( struct packed{ logic [31:0] next; logic load_next; - } AXI_ID; - } [5-1:0]CPTRA_MBOX_VALID_AXI_ID; + } AXI_USER; + } [5-1:0]CPTRA_MBOX_VALID_AXI_USER; struct packed{ struct packed{ logic next; logic load_next; } LOCK; - } [5-1:0]CPTRA_MBOX_AXI_ID_LOCK; + } [5-1:0]CPTRA_MBOX_AXI_USER_LOCK; struct packed{ struct packed{ logic [31:0] next; logic load_next; - } AXI_ID; - } CPTRA_TRNG_VALID_AXI_ID; + } AXI_USER; + } CPTRA_TRNG_VALID_AXI_USER; struct packed{ struct packed{ logic next; logic load_next; } LOCK; - } CPTRA_TRNG_AXI_ID_LOCK; + } CPTRA_TRNG_AXI_USER_LOCK; struct packed{ struct packed{ logic [31:0] next; @@ -580,14 +580,14 @@ module soc_ifc_reg ( struct packed{ logic [31:0] next; logic load_next; - } AXI_ID; - } CPTRA_FUSE_VALID_AXI_ID; + } AXI_USER; + } CPTRA_FUSE_VALID_AXI_USER; struct packed{ struct packed{ logic next; logic load_next; } LOCK; - } CPTRA_FUSE_AXI_ID_LOCK; + } CPTRA_FUSE_AXI_USER_LOCK; struct packed{ struct packed{ logic [31:0] next; @@ -1317,23 +1317,23 @@ module soc_ifc_reg ( struct packed{ struct packed{ logic [31:0] value; - } AXI_ID; - } [5-1:0]CPTRA_MBOX_VALID_AXI_ID; + } AXI_USER; + } [5-1:0]CPTRA_MBOX_VALID_AXI_USER; struct packed{ struct packed{ logic value; } LOCK; - } [5-1:0]CPTRA_MBOX_AXI_ID_LOCK; + } [5-1:0]CPTRA_MBOX_AXI_USER_LOCK; struct packed{ struct packed{ logic [31:0] value; - } AXI_ID; - } CPTRA_TRNG_VALID_AXI_ID; + } AXI_USER; + } CPTRA_TRNG_VALID_AXI_USER; struct packed{ struct packed{ logic value; } LOCK; - } CPTRA_TRNG_AXI_ID_LOCK; + } CPTRA_TRNG_AXI_USER_LOCK; struct packed{ struct packed{ logic [31:0] value; @@ -1433,13 +1433,13 @@ module soc_ifc_reg ( struct packed{ struct packed{ logic [31:0] value; - } AXI_ID; - } CPTRA_FUSE_VALID_AXI_ID; + } AXI_USER; + } CPTRA_FUSE_VALID_AXI_USER; struct packed{ struct packed{ logic value; } LOCK; - } CPTRA_FUSE_AXI_ID_LOCK; + } CPTRA_FUSE_AXI_USER_LOCK; struct packed{ struct packed{ logic [31:0] value; @@ -2365,93 +2365,93 @@ module soc_ifc_reg ( end assign hwif_out.CPTRA_RESET_REASON.WARM_RESET.value = field_storage.CPTRA_RESET_REASON.WARM_RESET.value; for(genvar i0=0; i0<5; i0++) begin - // Field: soc_ifc_reg.CPTRA_MBOX_VALID_AXI_ID[].AXI_ID + // Field: soc_ifc_reg.CPTRA_MBOX_VALID_AXI_USER[].AXI_USER always_comb begin automatic logic [31:0] next_c; automatic logic load_next_c; - next_c = field_storage.CPTRA_MBOX_VALID_AXI_ID[i0].AXI_ID.value; + next_c = field_storage.CPTRA_MBOX_VALID_AXI_USER[i0].AXI_USER.value; load_next_c = '0; - if(decoded_reg_strb.CPTRA_MBOX_VALID_AXI_ID[i0] && decoded_req_is_wr && !(hwif_in.CPTRA_MBOX_VALID_AXI_ID[i0].AXI_ID.swwel)) begin // SW write - next_c = (field_storage.CPTRA_MBOX_VALID_AXI_ID[i0].AXI_ID.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); + if(decoded_reg_strb.CPTRA_MBOX_VALID_AXI_USER[i0] && decoded_req_is_wr && !(hwif_in.CPTRA_MBOX_VALID_AXI_USER[i0].AXI_USER.swwel)) begin // SW write + next_c = (field_storage.CPTRA_MBOX_VALID_AXI_USER[i0].AXI_USER.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end - field_combo.CPTRA_MBOX_VALID_AXI_ID[i0].AXI_ID.next = next_c; - field_combo.CPTRA_MBOX_VALID_AXI_ID[i0].AXI_ID.load_next = load_next_c; + field_combo.CPTRA_MBOX_VALID_AXI_USER[i0].AXI_USER.next = next_c; + field_combo.CPTRA_MBOX_VALID_AXI_USER[i0].AXI_USER.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_MBOX_VALID_AXI_ID[i0].AXI_ID.value <= 32'hffffffff; - end else if(field_combo.CPTRA_MBOX_VALID_AXI_ID[i0].AXI_ID.load_next) begin - field_storage.CPTRA_MBOX_VALID_AXI_ID[i0].AXI_ID.value <= field_combo.CPTRA_MBOX_VALID_AXI_ID[i0].AXI_ID.next; + field_storage.CPTRA_MBOX_VALID_AXI_USER[i0].AXI_USER.value <= 32'hffffffff; + end else if(field_combo.CPTRA_MBOX_VALID_AXI_USER[i0].AXI_USER.load_next) begin + field_storage.CPTRA_MBOX_VALID_AXI_USER[i0].AXI_USER.value <= field_combo.CPTRA_MBOX_VALID_AXI_USER[i0].AXI_USER.next; end end - assign hwif_out.CPTRA_MBOX_VALID_AXI_ID[i0].AXI_ID.value = field_storage.CPTRA_MBOX_VALID_AXI_ID[i0].AXI_ID.value; + assign hwif_out.CPTRA_MBOX_VALID_AXI_USER[i0].AXI_USER.value = field_storage.CPTRA_MBOX_VALID_AXI_USER[i0].AXI_USER.value; end for(genvar i0=0; i0<5; i0++) begin - // Field: soc_ifc_reg.CPTRA_MBOX_AXI_ID_LOCK[].LOCK + // Field: soc_ifc_reg.CPTRA_MBOX_AXI_USER_LOCK[].LOCK always_comb begin automatic logic [0:0] next_c; automatic logic load_next_c; - next_c = field_storage.CPTRA_MBOX_AXI_ID_LOCK[i0].LOCK.value; + next_c = field_storage.CPTRA_MBOX_AXI_USER_LOCK[i0].LOCK.value; load_next_c = '0; - if(decoded_reg_strb.CPTRA_MBOX_AXI_ID_LOCK[i0] && decoded_req_is_wr && !(hwif_in.CPTRA_MBOX_AXI_ID_LOCK[i0].LOCK.swwel)) begin // SW write - next_c = (field_storage.CPTRA_MBOX_AXI_ID_LOCK[i0].LOCK.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); + if(decoded_reg_strb.CPTRA_MBOX_AXI_USER_LOCK[i0] && decoded_req_is_wr && !(hwif_in.CPTRA_MBOX_AXI_USER_LOCK[i0].LOCK.swwel)) begin // SW write + next_c = (field_storage.CPTRA_MBOX_AXI_USER_LOCK[i0].LOCK.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; end - field_combo.CPTRA_MBOX_AXI_ID_LOCK[i0].LOCK.next = next_c; - field_combo.CPTRA_MBOX_AXI_ID_LOCK[i0].LOCK.load_next = load_next_c; + field_combo.CPTRA_MBOX_AXI_USER_LOCK[i0].LOCK.next = next_c; + field_combo.CPTRA_MBOX_AXI_USER_LOCK[i0].LOCK.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_MBOX_AXI_ID_LOCK[i0].LOCK.value <= 1'h0; - end else if(field_combo.CPTRA_MBOX_AXI_ID_LOCK[i0].LOCK.load_next) begin - field_storage.CPTRA_MBOX_AXI_ID_LOCK[i0].LOCK.value <= field_combo.CPTRA_MBOX_AXI_ID_LOCK[i0].LOCK.next; + field_storage.CPTRA_MBOX_AXI_USER_LOCK[i0].LOCK.value <= 1'h0; + end else if(field_combo.CPTRA_MBOX_AXI_USER_LOCK[i0].LOCK.load_next) begin + field_storage.CPTRA_MBOX_AXI_USER_LOCK[i0].LOCK.value <= field_combo.CPTRA_MBOX_AXI_USER_LOCK[i0].LOCK.next; end end - assign hwif_out.CPTRA_MBOX_AXI_ID_LOCK[i0].LOCK.value = field_storage.CPTRA_MBOX_AXI_ID_LOCK[i0].LOCK.value; + assign hwif_out.CPTRA_MBOX_AXI_USER_LOCK[i0].LOCK.value = field_storage.CPTRA_MBOX_AXI_USER_LOCK[i0].LOCK.value; end - // Field: soc_ifc_reg.CPTRA_TRNG_VALID_AXI_ID.AXI_ID + // Field: soc_ifc_reg.CPTRA_TRNG_VALID_AXI_USER.AXI_USER always_comb begin automatic logic [31:0] next_c; automatic logic load_next_c; - next_c = field_storage.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.value; + next_c = field_storage.CPTRA_TRNG_VALID_AXI_USER.AXI_USER.value; load_next_c = '0; - if(decoded_reg_strb.CPTRA_TRNG_VALID_AXI_ID && decoded_req_is_wr && !(hwif_in.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.swwel)) begin // SW write - next_c = (field_storage.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); + if(decoded_reg_strb.CPTRA_TRNG_VALID_AXI_USER && decoded_req_is_wr && !(hwif_in.CPTRA_TRNG_VALID_AXI_USER.AXI_USER.swwel)) begin // SW write + next_c = (field_storage.CPTRA_TRNG_VALID_AXI_USER.AXI_USER.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end - field_combo.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.next = next_c; - field_combo.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.load_next = load_next_c; + field_combo.CPTRA_TRNG_VALID_AXI_USER.AXI_USER.next = next_c; + field_combo.CPTRA_TRNG_VALID_AXI_USER.AXI_USER.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.value <= 32'hffffffff; - end else if(field_combo.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.load_next) begin - field_storage.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.value <= field_combo.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.next; + field_storage.CPTRA_TRNG_VALID_AXI_USER.AXI_USER.value <= 32'hffffffff; + end else if(field_combo.CPTRA_TRNG_VALID_AXI_USER.AXI_USER.load_next) begin + field_storage.CPTRA_TRNG_VALID_AXI_USER.AXI_USER.value <= field_combo.CPTRA_TRNG_VALID_AXI_USER.AXI_USER.next; end end - assign hwif_out.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.value = field_storage.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.value; - // Field: soc_ifc_reg.CPTRA_TRNG_AXI_ID_LOCK.LOCK + assign hwif_out.CPTRA_TRNG_VALID_AXI_USER.AXI_USER.value = field_storage.CPTRA_TRNG_VALID_AXI_USER.AXI_USER.value; + // Field: soc_ifc_reg.CPTRA_TRNG_AXI_USER_LOCK.LOCK always_comb begin automatic logic [0:0] next_c; automatic logic load_next_c; - next_c = field_storage.CPTRA_TRNG_AXI_ID_LOCK.LOCK.value; + next_c = field_storage.CPTRA_TRNG_AXI_USER_LOCK.LOCK.value; load_next_c = '0; - if(decoded_reg_strb.CPTRA_TRNG_AXI_ID_LOCK && decoded_req_is_wr && !(hwif_in.CPTRA_TRNG_AXI_ID_LOCK.LOCK.swwel)) begin // SW write - next_c = (field_storage.CPTRA_TRNG_AXI_ID_LOCK.LOCK.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); + if(decoded_reg_strb.CPTRA_TRNG_AXI_USER_LOCK && decoded_req_is_wr && !(hwif_in.CPTRA_TRNG_AXI_USER_LOCK.LOCK.swwel)) begin // SW write + next_c = (field_storage.CPTRA_TRNG_AXI_USER_LOCK.LOCK.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; end - field_combo.CPTRA_TRNG_AXI_ID_LOCK.LOCK.next = next_c; - field_combo.CPTRA_TRNG_AXI_ID_LOCK.LOCK.load_next = load_next_c; + field_combo.CPTRA_TRNG_AXI_USER_LOCK.LOCK.next = next_c; + field_combo.CPTRA_TRNG_AXI_USER_LOCK.LOCK.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_TRNG_AXI_ID_LOCK.LOCK.value <= 1'h0; - end else if(field_combo.CPTRA_TRNG_AXI_ID_LOCK.LOCK.load_next) begin - field_storage.CPTRA_TRNG_AXI_ID_LOCK.LOCK.value <= field_combo.CPTRA_TRNG_AXI_ID_LOCK.LOCK.next; + field_storage.CPTRA_TRNG_AXI_USER_LOCK.LOCK.value <= 1'h0; + end else if(field_combo.CPTRA_TRNG_AXI_USER_LOCK.LOCK.load_next) begin + field_storage.CPTRA_TRNG_AXI_USER_LOCK.LOCK.value <= field_combo.CPTRA_TRNG_AXI_USER_LOCK.LOCK.next; end end - assign hwif_out.CPTRA_TRNG_AXI_ID_LOCK.LOCK.value = field_storage.CPTRA_TRNG_AXI_ID_LOCK.LOCK.value; + assign hwif_out.CPTRA_TRNG_AXI_USER_LOCK.LOCK.value = field_storage.CPTRA_TRNG_AXI_USER_LOCK.LOCK.value; for(genvar i0=0; i0<12; i0++) begin // Field: soc_ifc_reg.CPTRA_TRNG_DATA[].DATA always_comb begin @@ -2910,48 +2910,48 @@ module soc_ifc_reg ( end end assign hwif_out.CPTRA_WDT_STATUS.t2_timeout.value = field_storage.CPTRA_WDT_STATUS.t2_timeout.value; - // Field: soc_ifc_reg.CPTRA_FUSE_VALID_AXI_ID.AXI_ID + // Field: soc_ifc_reg.CPTRA_FUSE_VALID_AXI_USER.AXI_USER always_comb begin automatic logic [31:0] next_c; automatic logic load_next_c; - next_c = field_storage.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.value; + next_c = field_storage.CPTRA_FUSE_VALID_AXI_USER.AXI_USER.value; load_next_c = '0; - if(decoded_reg_strb.CPTRA_FUSE_VALID_AXI_ID && decoded_req_is_wr && !(hwif_in.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.swwel)) begin // SW write - next_c = (field_storage.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); + if(decoded_reg_strb.CPTRA_FUSE_VALID_AXI_USER && decoded_req_is_wr && !(hwif_in.CPTRA_FUSE_VALID_AXI_USER.AXI_USER.swwel)) begin // SW write + next_c = (field_storage.CPTRA_FUSE_VALID_AXI_USER.AXI_USER.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end - field_combo.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.next = next_c; - field_combo.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.load_next = load_next_c; + field_combo.CPTRA_FUSE_VALID_AXI_USER.AXI_USER.next = next_c; + field_combo.CPTRA_FUSE_VALID_AXI_USER.AXI_USER.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.value <= 32'hffffffff; - end else if(field_combo.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.load_next) begin - field_storage.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.value <= field_combo.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.next; + field_storage.CPTRA_FUSE_VALID_AXI_USER.AXI_USER.value <= 32'hffffffff; + end else if(field_combo.CPTRA_FUSE_VALID_AXI_USER.AXI_USER.load_next) begin + field_storage.CPTRA_FUSE_VALID_AXI_USER.AXI_USER.value <= field_combo.CPTRA_FUSE_VALID_AXI_USER.AXI_USER.next; end end - assign hwif_out.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.value = field_storage.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.value; - // Field: soc_ifc_reg.CPTRA_FUSE_AXI_ID_LOCK.LOCK + assign hwif_out.CPTRA_FUSE_VALID_AXI_USER.AXI_USER.value = field_storage.CPTRA_FUSE_VALID_AXI_USER.AXI_USER.value; + // Field: soc_ifc_reg.CPTRA_FUSE_AXI_USER_LOCK.LOCK always_comb begin automatic logic [0:0] next_c; automatic logic load_next_c; - next_c = field_storage.CPTRA_FUSE_AXI_ID_LOCK.LOCK.value; + next_c = field_storage.CPTRA_FUSE_AXI_USER_LOCK.LOCK.value; load_next_c = '0; - if(decoded_reg_strb.CPTRA_FUSE_AXI_ID_LOCK && decoded_req_is_wr && !(hwif_in.CPTRA_FUSE_AXI_ID_LOCK.LOCK.swwel)) begin // SW write - next_c = (field_storage.CPTRA_FUSE_AXI_ID_LOCK.LOCK.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); + if(decoded_reg_strb.CPTRA_FUSE_AXI_USER_LOCK && decoded_req_is_wr && !(hwif_in.CPTRA_FUSE_AXI_USER_LOCK.LOCK.swwel)) begin // SW write + next_c = (field_storage.CPTRA_FUSE_AXI_USER_LOCK.LOCK.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; end - field_combo.CPTRA_FUSE_AXI_ID_LOCK.LOCK.next = next_c; - field_combo.CPTRA_FUSE_AXI_ID_LOCK.LOCK.load_next = load_next_c; + field_combo.CPTRA_FUSE_AXI_USER_LOCK.LOCK.next = next_c; + field_combo.CPTRA_FUSE_AXI_USER_LOCK.LOCK.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.CPTRA_FUSE_AXI_ID_LOCK.LOCK.value <= 1'h0; - end else if(field_combo.CPTRA_FUSE_AXI_ID_LOCK.LOCK.load_next) begin - field_storage.CPTRA_FUSE_AXI_ID_LOCK.LOCK.value <= field_combo.CPTRA_FUSE_AXI_ID_LOCK.LOCK.next; + field_storage.CPTRA_FUSE_AXI_USER_LOCK.LOCK.value <= 1'h0; + end else if(field_combo.CPTRA_FUSE_AXI_USER_LOCK.LOCK.load_next) begin + field_storage.CPTRA_FUSE_AXI_USER_LOCK.LOCK.value <= field_combo.CPTRA_FUSE_AXI_USER_LOCK.LOCK.next; end end - assign hwif_out.CPTRA_FUSE_AXI_ID_LOCK.LOCK.value = field_storage.CPTRA_FUSE_AXI_ID_LOCK.LOCK.value; + assign hwif_out.CPTRA_FUSE_AXI_USER_LOCK.LOCK.value = field_storage.CPTRA_FUSE_AXI_USER_LOCK.LOCK.value; for(genvar i0=0; i0<2; i0++) begin // Field: soc_ifc_reg.CPTRA_WDT_CFG[].TIMEOUT always_comb begin @@ -5805,14 +5805,14 @@ module soc_ifc_reg ( assign readback_array[17][3:3] = (decoded_reg_strb.CPTRA_SECURITY_STATE && !decoded_req_is_wr) ? hwif_in.CPTRA_SECURITY_STATE.scan_mode.next : '0; assign readback_array[17][31:4] = (decoded_reg_strb.CPTRA_SECURITY_STATE && !decoded_req_is_wr) ? 28'h0 : '0; for(genvar i0=0; i0<5; i0++) begin - assign readback_array[i0*1 + 18][31:0] = (decoded_reg_strb.CPTRA_MBOX_VALID_AXI_ID[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_MBOX_VALID_AXI_ID[i0].AXI_ID.value : '0; + assign readback_array[i0*1 + 18][31:0] = (decoded_reg_strb.CPTRA_MBOX_VALID_AXI_USER[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_MBOX_VALID_AXI_USER[i0].AXI_USER.value : '0; end for(genvar i0=0; i0<5; i0++) begin - assign readback_array[i0*1 + 23][0:0] = (decoded_reg_strb.CPTRA_MBOX_AXI_ID_LOCK[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_MBOX_AXI_ID_LOCK[i0].LOCK.value : '0; + assign readback_array[i0*1 + 23][0:0] = (decoded_reg_strb.CPTRA_MBOX_AXI_USER_LOCK[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_MBOX_AXI_USER_LOCK[i0].LOCK.value : '0; assign readback_array[i0*1 + 23][31:1] = '0; end - assign readback_array[28][31:0] = (decoded_reg_strb.CPTRA_TRNG_VALID_AXI_ID && !decoded_req_is_wr) ? field_storage.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.value : '0; - assign readback_array[29][0:0] = (decoded_reg_strb.CPTRA_TRNG_AXI_ID_LOCK && !decoded_req_is_wr) ? field_storage.CPTRA_TRNG_AXI_ID_LOCK.LOCK.value : '0; + assign readback_array[28][31:0] = (decoded_reg_strb.CPTRA_TRNG_VALID_AXI_USER && !decoded_req_is_wr) ? field_storage.CPTRA_TRNG_VALID_AXI_USER.AXI_USER.value : '0; + assign readback_array[29][0:0] = (decoded_reg_strb.CPTRA_TRNG_AXI_USER_LOCK && !decoded_req_is_wr) ? field_storage.CPTRA_TRNG_AXI_USER_LOCK.LOCK.value : '0; assign readback_array[29][31:1] = '0; for(genvar i0=0; i0<12; i0++) begin assign readback_array[i0*1 + 30][31:0] = (decoded_reg_strb.CPTRA_TRNG_DATA[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_TRNG_DATA[i0].DATA.value : '0; @@ -5864,8 +5864,8 @@ module soc_ifc_reg ( assign readback_array[65][0:0] = (decoded_reg_strb.CPTRA_WDT_STATUS && !decoded_req_is_wr) ? field_storage.CPTRA_WDT_STATUS.t1_timeout.value : '0; assign readback_array[65][1:1] = (decoded_reg_strb.CPTRA_WDT_STATUS && !decoded_req_is_wr) ? field_storage.CPTRA_WDT_STATUS.t2_timeout.value : '0; assign readback_array[65][31:2] = '0; - assign readback_array[66][31:0] = (decoded_reg_strb.CPTRA_FUSE_VALID_AXI_ID && !decoded_req_is_wr) ? field_storage.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.value : '0; - assign readback_array[67][0:0] = (decoded_reg_strb.CPTRA_FUSE_AXI_ID_LOCK && !decoded_req_is_wr) ? field_storage.CPTRA_FUSE_AXI_ID_LOCK.LOCK.value : '0; + assign readback_array[66][31:0] = (decoded_reg_strb.CPTRA_FUSE_VALID_AXI_USER && !decoded_req_is_wr) ? field_storage.CPTRA_FUSE_VALID_AXI_USER.AXI_USER.value : '0; + assign readback_array[67][0:0] = (decoded_reg_strb.CPTRA_FUSE_AXI_USER_LOCK && !decoded_req_is_wr) ? field_storage.CPTRA_FUSE_AXI_USER_LOCK.LOCK.value : '0; assign readback_array[67][31:1] = '0; for(genvar i0=0; i0<2; i0++) begin assign readback_array[i0*1 + 68][31:0] = (decoded_reg_strb.CPTRA_WDT_CFG[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_WDT_CFG[i0].TIMEOUT.value : '0; diff --git a/src/soc_ifc/rtl/soc_ifc_reg_covergroups.svh b/src/soc_ifc/rtl/soc_ifc_reg_covergroups.svh index ebd06c48a..b65dbeacc 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg_covergroups.svh +++ b/src/soc_ifc/rtl/soc_ifc_reg_covergroups.svh @@ -265,8 +265,8 @@ endgroup - /*----------------------- SOC_IFC_REG__CPTRA_MBOX_VALID_AXI_ID COVERGROUPS -----------------------*/ - covergroup soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID_bit_cg with function sample(input bit reg_bit); + /*----------------------- SOC_IFC_REG__CPTRA_MBOX_VALID_AXI_USER COVERGROUPS -----------------------*/ + covergroup soc_ifc_reg__CPTRA_MBOX_VALID_AXI_USER_bit_cg with function sample(input bit reg_bit); option.per_instance = 1; reg_bit_cp : coverpoint reg_bit { bins value[2] = {0,1}; @@ -277,16 +277,16 @@ } endgroup - covergroup soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID_fld_cg with function sample( - input bit [32-1:0] AXI_ID + covergroup soc_ifc_reg__CPTRA_MBOX_VALID_AXI_USER_fld_cg with function sample( + input bit [32-1:0] AXI_USER ); option.per_instance = 1; - AXI_ID_cp : coverpoint AXI_ID; + AXI_USER_cp : coverpoint AXI_USER; endgroup - /*----------------------- SOC_IFC_REG__CPTRA_MBOX_AXI_ID_LOCK COVERGROUPS -----------------------*/ - covergroup soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK_bit_cg with function sample(input bit reg_bit); + /*----------------------- SOC_IFC_REG__CPTRA_MBOX_AXI_USER_LOCK COVERGROUPS -----------------------*/ + covergroup soc_ifc_reg__CPTRA_MBOX_AXI_USER_LOCK_bit_cg with function sample(input bit reg_bit); option.per_instance = 1; reg_bit_cp : coverpoint reg_bit { bins value[2] = {0,1}; @@ -297,7 +297,7 @@ } endgroup - covergroup soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK_fld_cg with function sample( + covergroup soc_ifc_reg__CPTRA_MBOX_AXI_USER_LOCK_fld_cg with function sample( input bit [1-1:0] LOCK ); option.per_instance = 1; @@ -305,8 +305,8 @@ endgroup - /*----------------------- SOC_IFC_REG__CPTRA_TRNG_VALID_AXI_ID COVERGROUPS -----------------------*/ - covergroup soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID_bit_cg with function sample(input bit reg_bit); + /*----------------------- SOC_IFC_REG__CPTRA_TRNG_VALID_AXI_USER COVERGROUPS -----------------------*/ + covergroup soc_ifc_reg__CPTRA_TRNG_VALID_AXI_USER_bit_cg with function sample(input bit reg_bit); option.per_instance = 1; reg_bit_cp : coverpoint reg_bit { bins value[2] = {0,1}; @@ -317,11 +317,11 @@ } endgroup - covergroup soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID_fld_cg with function sample( - input bit [32-1:0] AXI_ID + covergroup soc_ifc_reg__CPTRA_TRNG_VALID_AXI_USER_fld_cg with function sample( + input bit [32-1:0] AXI_USER ); option.per_instance = 1; - AXI_ID_cp : coverpoint AXI_ID { + AXI_USER_cp : coverpoint AXI_USER { bins zero_val = {32'h0}; bins rand_val[64] = {[1:32'hFFFF_FFFE]}; bins ones_val = {{32{1'b1}}}; @@ -331,8 +331,8 @@ endgroup - /*----------------------- SOC_IFC_REG__CPTRA_TRNG_AXI_ID_LOCK COVERGROUPS -----------------------*/ - covergroup soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK_bit_cg with function sample(input bit reg_bit); + /*----------------------- SOC_IFC_REG__CPTRA_TRNG_AXI_USER_LOCK COVERGROUPS -----------------------*/ + covergroup soc_ifc_reg__CPTRA_TRNG_AXI_USER_LOCK_bit_cg with function sample(input bit reg_bit); option.per_instance = 1; reg_bit_cp : coverpoint reg_bit { bins value[2] = {0,1}; @@ -343,7 +343,7 @@ } endgroup - covergroup soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK_fld_cg with function sample( + covergroup soc_ifc_reg__CPTRA_TRNG_AXI_USER_LOCK_fld_cg with function sample( input bit [1-1:0] LOCK ); option.per_instance = 1; @@ -789,8 +789,8 @@ endgroup - /*----------------------- SOC_IFC_REG__CPTRA_FUSE_VALID_AXI_ID COVERGROUPS -----------------------*/ - covergroup soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID_bit_cg with function sample(input bit reg_bit); + /*----------------------- SOC_IFC_REG__CPTRA_FUSE_VALID_AXI_USER COVERGROUPS -----------------------*/ + covergroup soc_ifc_reg__CPTRA_FUSE_VALID_AXI_USER_bit_cg with function sample(input bit reg_bit); option.per_instance = 1; reg_bit_cp : coverpoint reg_bit { bins value[2] = {0,1}; @@ -801,11 +801,11 @@ } endgroup - covergroup soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID_fld_cg with function sample( - input bit [32-1:0] AXI_ID + covergroup soc_ifc_reg__CPTRA_FUSE_VALID_AXI_USER_fld_cg with function sample( + input bit [32-1:0] AXI_USER ); option.per_instance = 1; - AXI_ID_cp : coverpoint AXI_ID { + AXI_USER_cp : coverpoint AXI_USER { bins zero_val = {32'h0}; bins rand_val[64] = {[1:32'hFFFF_FFFE]}; bins ones_val = {{32{1'b1}}}; @@ -815,8 +815,8 @@ endgroup - /*----------------------- SOC_IFC_REG__CPTRA_FUSE_AXI_ID_LOCK COVERGROUPS -----------------------*/ - covergroup soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK_bit_cg with function sample(input bit reg_bit); + /*----------------------- SOC_IFC_REG__CPTRA_FUSE_AXI_USER_LOCK COVERGROUPS -----------------------*/ + covergroup soc_ifc_reg__CPTRA_FUSE_AXI_USER_LOCK_bit_cg with function sample(input bit reg_bit); option.per_instance = 1; reg_bit_cp : coverpoint reg_bit { bins value[2] = {0,1}; @@ -827,7 +827,7 @@ } endgroup - covergroup soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK_fld_cg with function sample( + covergroup soc_ifc_reg__CPTRA_FUSE_AXI_USER_LOCK_fld_cg with function sample( input bit [1-1:0] LOCK ); option.per_instance = 1; diff --git a/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv b/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv index 30f4eb8d3..dbbea2814 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv +++ b/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv @@ -84,35 +84,35 @@ package soc_ifc_reg_pkg; typedef struct packed{ logic swwel; - } soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID__AXI_ID__in_t; + } soc_ifc_reg__CPTRA_MBOX_VALID_AXI_USER__AXI_USER__in_t; typedef struct packed{ - soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID__AXI_ID__in_t AXI_ID; - } soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID__in_t; + soc_ifc_reg__CPTRA_MBOX_VALID_AXI_USER__AXI_USER__in_t AXI_USER; + } soc_ifc_reg__CPTRA_MBOX_VALID_AXI_USER__in_t; typedef struct packed{ logic swwel; - } soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK__LOCK__in_t; + } soc_ifc_reg__CPTRA_MBOX_AXI_USER_LOCK__LOCK__in_t; typedef struct packed{ - soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK__LOCK__in_t LOCK; - } soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK__in_t; + soc_ifc_reg__CPTRA_MBOX_AXI_USER_LOCK__LOCK__in_t LOCK; + } soc_ifc_reg__CPTRA_MBOX_AXI_USER_LOCK__in_t; typedef struct packed{ logic swwel; - } soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID__AXI_ID__in_t; + } soc_ifc_reg__CPTRA_TRNG_VALID_AXI_USER__AXI_USER__in_t; typedef struct packed{ - soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID__AXI_ID__in_t AXI_ID; - } soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID__in_t; + soc_ifc_reg__CPTRA_TRNG_VALID_AXI_USER__AXI_USER__in_t AXI_USER; + } soc_ifc_reg__CPTRA_TRNG_VALID_AXI_USER__in_t; typedef struct packed{ logic swwel; - } soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK__LOCK__in_t; + } soc_ifc_reg__CPTRA_TRNG_AXI_USER_LOCK__LOCK__in_t; typedef struct packed{ - soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK__LOCK__in_t LOCK; - } soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK__in_t; + soc_ifc_reg__CPTRA_TRNG_AXI_USER_LOCK__LOCK__in_t LOCK; + } soc_ifc_reg__CPTRA_TRNG_AXI_USER_LOCK__in_t; typedef struct packed{ logic swwe; @@ -217,19 +217,19 @@ package soc_ifc_reg_pkg; typedef struct packed{ logic swwel; - } soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID__AXI_ID__in_t; + } soc_ifc_reg__CPTRA_FUSE_VALID_AXI_USER__AXI_USER__in_t; typedef struct packed{ - soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID__AXI_ID__in_t AXI_ID; - } soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID__in_t; + soc_ifc_reg__CPTRA_FUSE_VALID_AXI_USER__AXI_USER__in_t AXI_USER; + } soc_ifc_reg__CPTRA_FUSE_VALID_AXI_USER__in_t; typedef struct packed{ logic swwel; - } soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK__LOCK__in_t; + } soc_ifc_reg__CPTRA_FUSE_AXI_USER_LOCK__LOCK__in_t; typedef struct packed{ - soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK__LOCK__in_t LOCK; - } soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK__in_t; + soc_ifc_reg__CPTRA_FUSE_AXI_USER_LOCK__LOCK__in_t LOCK; + } soc_ifc_reg__CPTRA_FUSE_AXI_USER_LOCK__in_t; typedef struct packed{ logic swwel; @@ -439,10 +439,10 @@ package soc_ifc_reg_pkg; soc_ifc_reg__CPTRA_FLOW_STATUS__in_t CPTRA_FLOW_STATUS; soc_ifc_reg__CPTRA_RESET_REASON__in_t CPTRA_RESET_REASON; soc_ifc_reg__CPTRA_SECURITY_STATE__in_t CPTRA_SECURITY_STATE; - soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID__in_t [5-1:0]CPTRA_MBOX_VALID_AXI_ID; - soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK__in_t [5-1:0]CPTRA_MBOX_AXI_ID_LOCK; - soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID__in_t CPTRA_TRNG_VALID_AXI_ID; - soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK__in_t CPTRA_TRNG_AXI_ID_LOCK; + soc_ifc_reg__CPTRA_MBOX_VALID_AXI_USER__in_t [5-1:0]CPTRA_MBOX_VALID_AXI_USER; + soc_ifc_reg__CPTRA_MBOX_AXI_USER_LOCK__in_t [5-1:0]CPTRA_MBOX_AXI_USER_LOCK; + soc_ifc_reg__CPTRA_TRNG_VALID_AXI_USER__in_t CPTRA_TRNG_VALID_AXI_USER; + soc_ifc_reg__CPTRA_TRNG_AXI_USER_LOCK__in_t CPTRA_TRNG_AXI_USER_LOCK; soc_ifc_reg__CPTRA_TRNG_DATA__in_t [12-1:0]CPTRA_TRNG_DATA; soc_ifc_reg__CPTRA_TRNG_STATUS__in_t CPTRA_TRNG_STATUS; soc_ifc_reg__CPTRA_FUSE_WR_DONE__in_t CPTRA_FUSE_WR_DONE; @@ -452,8 +452,8 @@ package soc_ifc_reg_pkg; soc_ifc_reg__CPTRA_HW_REV_ID__in_t CPTRA_HW_REV_ID; soc_ifc_reg__CPTRA_HW_CONFIG__in_t CPTRA_HW_CONFIG; soc_ifc_reg__CPTRA_WDT_STATUS__in_t CPTRA_WDT_STATUS; - soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID__in_t CPTRA_FUSE_VALID_AXI_ID; - soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK__in_t CPTRA_FUSE_AXI_ID_LOCK; + soc_ifc_reg__CPTRA_FUSE_VALID_AXI_USER__in_t CPTRA_FUSE_VALID_AXI_USER; + soc_ifc_reg__CPTRA_FUSE_AXI_USER_LOCK__in_t CPTRA_FUSE_AXI_USER_LOCK; soc_ifc_reg__fuse_uds_seed__in_t [16-1:0]fuse_uds_seed; soc_ifc_reg__fuse_field_entropy__in_t [8-1:0]fuse_field_entropy; soc_ifc_reg__fuse_key_manifest_pk_hash__in_t [12-1:0]fuse_key_manifest_pk_hash; @@ -575,35 +575,35 @@ package soc_ifc_reg_pkg; typedef struct packed{ logic [31:0] value; - } soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID__AXI_ID__out_t; + } soc_ifc_reg__CPTRA_MBOX_VALID_AXI_USER__AXI_USER__out_t; typedef struct packed{ - soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID__AXI_ID__out_t AXI_ID; - } soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID__out_t; + soc_ifc_reg__CPTRA_MBOX_VALID_AXI_USER__AXI_USER__out_t AXI_USER; + } soc_ifc_reg__CPTRA_MBOX_VALID_AXI_USER__out_t; typedef struct packed{ logic value; - } soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK__LOCK__out_t; + } soc_ifc_reg__CPTRA_MBOX_AXI_USER_LOCK__LOCK__out_t; typedef struct packed{ - soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK__LOCK__out_t LOCK; - } soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK__out_t; + soc_ifc_reg__CPTRA_MBOX_AXI_USER_LOCK__LOCK__out_t LOCK; + } soc_ifc_reg__CPTRA_MBOX_AXI_USER_LOCK__out_t; typedef struct packed{ logic [31:0] value; - } soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID__AXI_ID__out_t; + } soc_ifc_reg__CPTRA_TRNG_VALID_AXI_USER__AXI_USER__out_t; typedef struct packed{ - soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID__AXI_ID__out_t AXI_ID; - } soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID__out_t; + soc_ifc_reg__CPTRA_TRNG_VALID_AXI_USER__AXI_USER__out_t AXI_USER; + } soc_ifc_reg__CPTRA_TRNG_VALID_AXI_USER__out_t; typedef struct packed{ logic value; - } soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK__LOCK__out_t; + } soc_ifc_reg__CPTRA_TRNG_AXI_USER_LOCK__LOCK__out_t; typedef struct packed{ - soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK__LOCK__out_t LOCK; - } soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK__out_t; + soc_ifc_reg__CPTRA_TRNG_AXI_USER_LOCK__LOCK__out_t LOCK; + } soc_ifc_reg__CPTRA_TRNG_AXI_USER_LOCK__out_t; typedef struct packed{ logic swacc; @@ -749,19 +749,19 @@ package soc_ifc_reg_pkg; typedef struct packed{ logic [31:0] value; - } soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID__AXI_ID__out_t; + } soc_ifc_reg__CPTRA_FUSE_VALID_AXI_USER__AXI_USER__out_t; typedef struct packed{ - soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID__AXI_ID__out_t AXI_ID; - } soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID__out_t; + soc_ifc_reg__CPTRA_FUSE_VALID_AXI_USER__AXI_USER__out_t AXI_USER; + } soc_ifc_reg__CPTRA_FUSE_VALID_AXI_USER__out_t; typedef struct packed{ logic value; - } soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK__LOCK__out_t; + } soc_ifc_reg__CPTRA_FUSE_AXI_USER_LOCK__LOCK__out_t; typedef struct packed{ - soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK__LOCK__out_t LOCK; - } soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK__out_t; + soc_ifc_reg__CPTRA_FUSE_AXI_USER_LOCK__LOCK__out_t LOCK; + } soc_ifc_reg__CPTRA_FUSE_AXI_USER_LOCK__out_t; typedef struct packed{ logic [31:0] value; @@ -980,10 +980,10 @@ package soc_ifc_reg_pkg; soc_ifc_reg__CPTRA_BOOT_STATUS__out_t CPTRA_BOOT_STATUS; soc_ifc_reg__CPTRA_FLOW_STATUS__out_t CPTRA_FLOW_STATUS; soc_ifc_reg__CPTRA_RESET_REASON__out_t CPTRA_RESET_REASON; - soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID__out_t [5-1:0]CPTRA_MBOX_VALID_AXI_ID; - soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK__out_t [5-1:0]CPTRA_MBOX_AXI_ID_LOCK; - soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID__out_t CPTRA_TRNG_VALID_AXI_ID; - soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK__out_t CPTRA_TRNG_AXI_ID_LOCK; + soc_ifc_reg__CPTRA_MBOX_VALID_AXI_USER__out_t [5-1:0]CPTRA_MBOX_VALID_AXI_USER; + soc_ifc_reg__CPTRA_MBOX_AXI_USER_LOCK__out_t [5-1:0]CPTRA_MBOX_AXI_USER_LOCK; + soc_ifc_reg__CPTRA_TRNG_VALID_AXI_USER__out_t CPTRA_TRNG_VALID_AXI_USER; + soc_ifc_reg__CPTRA_TRNG_AXI_USER_LOCK__out_t CPTRA_TRNG_AXI_USER_LOCK; soc_ifc_reg__CPTRA_TRNG_DATA__out_t [12-1:0]CPTRA_TRNG_DATA; soc_ifc_reg__CPTRA_TRNG_CTRL__out_t CPTRA_TRNG_CTRL; soc_ifc_reg__CPTRA_TRNG_STATUS__out_t CPTRA_TRNG_STATUS; @@ -1001,8 +1001,8 @@ package soc_ifc_reg_pkg; soc_ifc_reg__CPTRA_WDT_TIMER2_CTRL__out_t CPTRA_WDT_TIMER2_CTRL; soc_ifc_reg__CPTRA_WDT_TIMER2_TIMEOUT_PERIOD__out_t [2-1:0]CPTRA_WDT_TIMER2_TIMEOUT_PERIOD; soc_ifc_reg__CPTRA_WDT_STATUS__out_t CPTRA_WDT_STATUS; - soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID__out_t CPTRA_FUSE_VALID_AXI_ID; - soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK__out_t CPTRA_FUSE_AXI_ID_LOCK; + soc_ifc_reg__CPTRA_FUSE_VALID_AXI_USER__out_t CPTRA_FUSE_VALID_AXI_USER; + soc_ifc_reg__CPTRA_FUSE_AXI_USER_LOCK__out_t CPTRA_FUSE_AXI_USER_LOCK; soc_ifc_reg__fuse_uds_seed__out_t [16-1:0]fuse_uds_seed; soc_ifc_reg__fuse_field_entropy__out_t [8-1:0]fuse_field_entropy; soc_ifc_reg__fuse_key_manifest_pk_hash__out_t [12-1:0]fuse_key_manifest_pk_hash; diff --git a/src/soc_ifc/rtl/soc_ifc_reg_sample.svh b/src/soc_ifc/rtl/soc_ifc_reg_sample.svh index ff26ec47f..e46e5a92b 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg_sample.svh +++ b/src/soc_ifc/rtl/soc_ifc_reg_sample.svh @@ -320,8 +320,8 @@ end endfunction - /*----------------------- SOC_IFC_REG__CPTRA_MBOX_VALID_AXI_ID SAMPLE FUNCTIONS -----------------------*/ - function void soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID::sample(uvm_reg_data_t data, + /*----------------------- SOC_IFC_REG__CPTRA_MBOX_VALID_AXI_USER SAMPLE FUNCTIONS -----------------------*/ + function void soc_ifc_reg__CPTRA_MBOX_VALID_AXI_USER::sample(uvm_reg_data_t data, uvm_reg_data_t byte_en, bit is_read, uvm_reg_map map); @@ -329,24 +329,24 @@ m_data = data; m_is_read = is_read; if (get_coverage(UVM_CVR_REG_BITS)) begin - foreach(AXI_ID_bit_cg[bt]) this.AXI_ID_bit_cg[bt].sample(data[0 + bt]); + foreach(AXI_USER_bit_cg[bt]) this.AXI_USER_bit_cg[bt].sample(data[0 + bt]); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( data[31:0]/*AXI_ID*/ ); + this.fld_cg.sample( data[31:0]/*AXI_USER*/ ); end endfunction - function void soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID::sample_values(); + function void soc_ifc_reg__CPTRA_MBOX_VALID_AXI_USER::sample_values(); if (get_coverage(UVM_CVR_REG_BITS)) begin - foreach(AXI_ID_bit_cg[bt]) this.AXI_ID_bit_cg[bt].sample(AXI_ID.get_mirrored_value() >> bt); + foreach(AXI_USER_bit_cg[bt]) this.AXI_USER_bit_cg[bt].sample(AXI_USER.get_mirrored_value() >> bt); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( AXI_ID.get_mirrored_value() ); + this.fld_cg.sample( AXI_USER.get_mirrored_value() ); end endfunction - /*----------------------- SOC_IFC_REG__CPTRA_MBOX_AXI_ID_LOCK SAMPLE FUNCTIONS -----------------------*/ - function void soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK::sample(uvm_reg_data_t data, + /*----------------------- SOC_IFC_REG__CPTRA_MBOX_AXI_USER_LOCK SAMPLE FUNCTIONS -----------------------*/ + function void soc_ifc_reg__CPTRA_MBOX_AXI_USER_LOCK::sample(uvm_reg_data_t data, uvm_reg_data_t byte_en, bit is_read, uvm_reg_map map); @@ -361,7 +361,7 @@ end endfunction - function void soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK::sample_values(); + function void soc_ifc_reg__CPTRA_MBOX_AXI_USER_LOCK::sample_values(); if (get_coverage(UVM_CVR_REG_BITS)) begin foreach(LOCK_bit_cg[bt]) this.LOCK_bit_cg[bt].sample(LOCK.get_mirrored_value() >> bt); end @@ -370,8 +370,8 @@ end endfunction - /*----------------------- SOC_IFC_REG__CPTRA_TRNG_VALID_AXI_ID SAMPLE FUNCTIONS -----------------------*/ - function void soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID::sample(uvm_reg_data_t data, + /*----------------------- SOC_IFC_REG__CPTRA_TRNG_VALID_AXI_USER SAMPLE FUNCTIONS -----------------------*/ + function void soc_ifc_reg__CPTRA_TRNG_VALID_AXI_USER::sample(uvm_reg_data_t data, uvm_reg_data_t byte_en, bit is_read, uvm_reg_map map); @@ -379,24 +379,24 @@ m_data = data; m_is_read = is_read; if (get_coverage(UVM_CVR_REG_BITS)) begin - foreach(AXI_ID_bit_cg[bt]) this.AXI_ID_bit_cg[bt].sample(data[0 + bt]); + foreach(AXI_USER_bit_cg[bt]) this.AXI_USER_bit_cg[bt].sample(data[0 + bt]); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( data[31:0]/*AXI_ID*/ ); + this.fld_cg.sample( data[31:0]/*AXI_USER*/ ); end endfunction - function void soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID::sample_values(); + function void soc_ifc_reg__CPTRA_TRNG_VALID_AXI_USER::sample_values(); if (get_coverage(UVM_CVR_REG_BITS)) begin - foreach(AXI_ID_bit_cg[bt]) this.AXI_ID_bit_cg[bt].sample(AXI_ID.get_mirrored_value() >> bt); + foreach(AXI_USER_bit_cg[bt]) this.AXI_USER_bit_cg[bt].sample(AXI_USER.get_mirrored_value() >> bt); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( AXI_ID.get_mirrored_value() ); + this.fld_cg.sample( AXI_USER.get_mirrored_value() ); end endfunction - /*----------------------- SOC_IFC_REG__CPTRA_TRNG_AXI_ID_LOCK SAMPLE FUNCTIONS -----------------------*/ - function void soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK::sample(uvm_reg_data_t data, + /*----------------------- SOC_IFC_REG__CPTRA_TRNG_AXI_USER_LOCK SAMPLE FUNCTIONS -----------------------*/ + function void soc_ifc_reg__CPTRA_TRNG_AXI_USER_LOCK::sample(uvm_reg_data_t data, uvm_reg_data_t byte_en, bit is_read, uvm_reg_map map); @@ -411,7 +411,7 @@ end endfunction - function void soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK::sample_values(); + function void soc_ifc_reg__CPTRA_TRNG_AXI_USER_LOCK::sample_values(); if (get_coverage(UVM_CVR_REG_BITS)) begin foreach(LOCK_bit_cg[bt]) this.LOCK_bit_cg[bt].sample(LOCK.get_mirrored_value() >> bt); end @@ -934,8 +934,8 @@ end endfunction - /*----------------------- SOC_IFC_REG__CPTRA_FUSE_VALID_AXI_ID SAMPLE FUNCTIONS -----------------------*/ - function void soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID::sample(uvm_reg_data_t data, + /*----------------------- SOC_IFC_REG__CPTRA_FUSE_VALID_AXI_USER SAMPLE FUNCTIONS -----------------------*/ + function void soc_ifc_reg__CPTRA_FUSE_VALID_AXI_USER::sample(uvm_reg_data_t data, uvm_reg_data_t byte_en, bit is_read, uvm_reg_map map); @@ -943,24 +943,24 @@ m_data = data; m_is_read = is_read; if (get_coverage(UVM_CVR_REG_BITS)) begin - foreach(AXI_ID_bit_cg[bt]) this.AXI_ID_bit_cg[bt].sample(data[0 + bt]); + foreach(AXI_USER_bit_cg[bt]) this.AXI_USER_bit_cg[bt].sample(data[0 + bt]); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( data[31:0]/*AXI_ID*/ ); + this.fld_cg.sample( data[31:0]/*AXI_USER*/ ); end endfunction - function void soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID::sample_values(); + function void soc_ifc_reg__CPTRA_FUSE_VALID_AXI_USER::sample_values(); if (get_coverage(UVM_CVR_REG_BITS)) begin - foreach(AXI_ID_bit_cg[bt]) this.AXI_ID_bit_cg[bt].sample(AXI_ID.get_mirrored_value() >> bt); + foreach(AXI_USER_bit_cg[bt]) this.AXI_USER_bit_cg[bt].sample(AXI_USER.get_mirrored_value() >> bt); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( AXI_ID.get_mirrored_value() ); + this.fld_cg.sample( AXI_USER.get_mirrored_value() ); end endfunction - /*----------------------- SOC_IFC_REG__CPTRA_FUSE_AXI_ID_LOCK SAMPLE FUNCTIONS -----------------------*/ - function void soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK::sample(uvm_reg_data_t data, + /*----------------------- SOC_IFC_REG__CPTRA_FUSE_AXI_USER_LOCK SAMPLE FUNCTIONS -----------------------*/ + function void soc_ifc_reg__CPTRA_FUSE_AXI_USER_LOCK::sample(uvm_reg_data_t data, uvm_reg_data_t byte_en, bit is_read, uvm_reg_map map); @@ -975,7 +975,7 @@ end endfunction - function void soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK::sample_values(); + function void soc_ifc_reg__CPTRA_FUSE_AXI_USER_LOCK::sample_values(); if (get_coverage(UVM_CVR_REG_BITS)) begin foreach(LOCK_bit_cg[bt]) this.LOCK_bit_cg[bt].sample(LOCK.get_mirrored_value() >> bt); end diff --git a/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv b/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv index aab915dd3..b6df335a9 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv +++ b/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv @@ -409,17 +409,17 @@ package soc_ifc_reg_uvm; endfunction : build endclass : soc_ifc_reg__CPTRA_SECURITY_STATE - // Reg - soc_ifc_reg::CPTRA_MBOX_VALID_AXI_ID - class soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID extends uvm_reg; + // Reg - soc_ifc_reg::CPTRA_MBOX_VALID_AXI_USER + class soc_ifc_reg__CPTRA_MBOX_VALID_AXI_USER extends uvm_reg; protected uvm_reg_data_t m_current; protected uvm_reg_data_t m_data; protected bit m_is_read; - soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID_bit_cg AXI_ID_bit_cg[32]; - soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID_fld_cg fld_cg; - rand uvm_reg_field AXI_ID; + soc_ifc_reg__CPTRA_MBOX_VALID_AXI_USER_bit_cg AXI_USER_bit_cg[32]; + soc_ifc_reg__CPTRA_MBOX_VALID_AXI_USER_fld_cg fld_cg; + rand uvm_reg_field AXI_USER; - function new(string name = "soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID"); + function new(string name = "soc_ifc_reg__CPTRA_MBOX_VALID_AXI_USER"); super.new(name, 32, build_coverage(UVM_CVR_ALL)); endfunction : new extern virtual function void sample_values(); @@ -429,27 +429,27 @@ package soc_ifc_reg_uvm; uvm_reg_map map); virtual function void build(); - this.AXI_ID = new("AXI_ID"); - this.AXI_ID.configure(this, 32, 0, "RW", 0, 'hffffffff, 1, 1, 0); + this.AXI_USER = new("AXI_USER"); + this.AXI_USER.configure(this, 32, 0, "RW", 0, 'hffffffff, 1, 1, 0); if (has_coverage(UVM_CVR_REG_BITS)) begin - foreach(AXI_ID_bit_cg[bt]) AXI_ID_bit_cg[bt] = new(); + foreach(AXI_USER_bit_cg[bt]) AXI_USER_bit_cg[bt] = new(); end if (has_coverage(UVM_CVR_FIELD_VALS)) fld_cg = new(); endfunction : build - endclass : soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID + endclass : soc_ifc_reg__CPTRA_MBOX_VALID_AXI_USER - // Reg - soc_ifc_reg::CPTRA_MBOX_AXI_ID_LOCK - class soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK extends uvm_reg; + // Reg - soc_ifc_reg::CPTRA_MBOX_AXI_USER_LOCK + class soc_ifc_reg__CPTRA_MBOX_AXI_USER_LOCK extends uvm_reg; protected uvm_reg_data_t m_current; protected uvm_reg_data_t m_data; protected bit m_is_read; - soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK_bit_cg LOCK_bit_cg[1]; - soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK_fld_cg fld_cg; + soc_ifc_reg__CPTRA_MBOX_AXI_USER_LOCK_bit_cg LOCK_bit_cg[1]; + soc_ifc_reg__CPTRA_MBOX_AXI_USER_LOCK_fld_cg fld_cg; rand uvm_reg_field LOCK; - function new(string name = "soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK"); + function new(string name = "soc_ifc_reg__CPTRA_MBOX_AXI_USER_LOCK"); super.new(name, 32, build_coverage(UVM_CVR_ALL)); endfunction : new extern virtual function void sample_values(); @@ -467,19 +467,19 @@ package soc_ifc_reg_uvm; if (has_coverage(UVM_CVR_FIELD_VALS)) fld_cg = new(); endfunction : build - endclass : soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK + endclass : soc_ifc_reg__CPTRA_MBOX_AXI_USER_LOCK - // Reg - soc_ifc_reg::CPTRA_TRNG_VALID_AXI_ID - class soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID extends uvm_reg; + // Reg - soc_ifc_reg::CPTRA_TRNG_VALID_AXI_USER + class soc_ifc_reg__CPTRA_TRNG_VALID_AXI_USER extends uvm_reg; protected uvm_reg_data_t m_current; protected uvm_reg_data_t m_data; protected bit m_is_read; - soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID_bit_cg AXI_ID_bit_cg[32]; - soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID_fld_cg fld_cg; - rand uvm_reg_field AXI_ID; + soc_ifc_reg__CPTRA_TRNG_VALID_AXI_USER_bit_cg AXI_USER_bit_cg[32]; + soc_ifc_reg__CPTRA_TRNG_VALID_AXI_USER_fld_cg fld_cg; + rand uvm_reg_field AXI_USER; - function new(string name = "soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID"); + function new(string name = "soc_ifc_reg__CPTRA_TRNG_VALID_AXI_USER"); super.new(name, 32, build_coverage(UVM_CVR_ALL)); endfunction : new extern virtual function void sample_values(); @@ -489,27 +489,27 @@ package soc_ifc_reg_uvm; uvm_reg_map map); virtual function void build(); - this.AXI_ID = new("AXI_ID"); - this.AXI_ID.configure(this, 32, 0, "RW", 0, 'hffffffff, 1, 1, 0); + this.AXI_USER = new("AXI_USER"); + this.AXI_USER.configure(this, 32, 0, "RW", 0, 'hffffffff, 1, 1, 0); if (has_coverage(UVM_CVR_REG_BITS)) begin - foreach(AXI_ID_bit_cg[bt]) AXI_ID_bit_cg[bt] = new(); + foreach(AXI_USER_bit_cg[bt]) AXI_USER_bit_cg[bt] = new(); end if (has_coverage(UVM_CVR_FIELD_VALS)) fld_cg = new(); endfunction : build - endclass : soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID + endclass : soc_ifc_reg__CPTRA_TRNG_VALID_AXI_USER - // Reg - soc_ifc_reg::CPTRA_TRNG_AXI_ID_LOCK - class soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK extends uvm_reg; + // Reg - soc_ifc_reg::CPTRA_TRNG_AXI_USER_LOCK + class soc_ifc_reg__CPTRA_TRNG_AXI_USER_LOCK extends uvm_reg; protected uvm_reg_data_t m_current; protected uvm_reg_data_t m_data; protected bit m_is_read; - soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK_bit_cg LOCK_bit_cg[1]; - soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK_fld_cg fld_cg; + soc_ifc_reg__CPTRA_TRNG_AXI_USER_LOCK_bit_cg LOCK_bit_cg[1]; + soc_ifc_reg__CPTRA_TRNG_AXI_USER_LOCK_fld_cg fld_cg; rand uvm_reg_field LOCK; - function new(string name = "soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK"); + function new(string name = "soc_ifc_reg__CPTRA_TRNG_AXI_USER_LOCK"); super.new(name, 32, build_coverage(UVM_CVR_ALL)); endfunction : new extern virtual function void sample_values(); @@ -527,7 +527,7 @@ package soc_ifc_reg_uvm; if (has_coverage(UVM_CVR_FIELD_VALS)) fld_cg = new(); endfunction : build - endclass : soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK + endclass : soc_ifc_reg__CPTRA_TRNG_AXI_USER_LOCK // Reg - soc_ifc_reg::CPTRA_TRNG_DATA class soc_ifc_reg__CPTRA_TRNG_DATA extends uvm_reg; @@ -1164,17 +1164,17 @@ package soc_ifc_reg_uvm; endfunction : build endclass : soc_ifc_reg__CPTRA_WDT_STATUS - // Reg - soc_ifc_reg::CPTRA_FUSE_VALID_AXI_ID - class soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID extends uvm_reg; + // Reg - soc_ifc_reg::CPTRA_FUSE_VALID_AXI_USER + class soc_ifc_reg__CPTRA_FUSE_VALID_AXI_USER extends uvm_reg; protected uvm_reg_data_t m_current; protected uvm_reg_data_t m_data; protected bit m_is_read; - soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID_bit_cg AXI_ID_bit_cg[32]; - soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID_fld_cg fld_cg; - rand uvm_reg_field AXI_ID; + soc_ifc_reg__CPTRA_FUSE_VALID_AXI_USER_bit_cg AXI_USER_bit_cg[32]; + soc_ifc_reg__CPTRA_FUSE_VALID_AXI_USER_fld_cg fld_cg; + rand uvm_reg_field AXI_USER; - function new(string name = "soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID"); + function new(string name = "soc_ifc_reg__CPTRA_FUSE_VALID_AXI_USER"); super.new(name, 32, build_coverage(UVM_CVR_ALL)); endfunction : new extern virtual function void sample_values(); @@ -1184,27 +1184,27 @@ package soc_ifc_reg_uvm; uvm_reg_map map); virtual function void build(); - this.AXI_ID = new("AXI_ID"); - this.AXI_ID.configure(this, 32, 0, "RW", 0, 'hffffffff, 1, 1, 0); + this.AXI_USER = new("AXI_USER"); + this.AXI_USER.configure(this, 32, 0, "RW", 0, 'hffffffff, 1, 1, 0); if (has_coverage(UVM_CVR_REG_BITS)) begin - foreach(AXI_ID_bit_cg[bt]) AXI_ID_bit_cg[bt] = new(); + foreach(AXI_USER_bit_cg[bt]) AXI_USER_bit_cg[bt] = new(); end if (has_coverage(UVM_CVR_FIELD_VALS)) fld_cg = new(); endfunction : build - endclass : soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID + endclass : soc_ifc_reg__CPTRA_FUSE_VALID_AXI_USER - // Reg - soc_ifc_reg::CPTRA_FUSE_AXI_ID_LOCK - class soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK extends uvm_reg; + // Reg - soc_ifc_reg::CPTRA_FUSE_AXI_USER_LOCK + class soc_ifc_reg__CPTRA_FUSE_AXI_USER_LOCK extends uvm_reg; protected uvm_reg_data_t m_current; protected uvm_reg_data_t m_data; protected bit m_is_read; - soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK_bit_cg LOCK_bit_cg[1]; - soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK_fld_cg fld_cg; + soc_ifc_reg__CPTRA_FUSE_AXI_USER_LOCK_bit_cg LOCK_bit_cg[1]; + soc_ifc_reg__CPTRA_FUSE_AXI_USER_LOCK_fld_cg fld_cg; rand uvm_reg_field LOCK; - function new(string name = "soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK"); + function new(string name = "soc_ifc_reg__CPTRA_FUSE_AXI_USER_LOCK"); super.new(name, 32, build_coverage(UVM_CVR_ALL)); endfunction : new extern virtual function void sample_values(); @@ -1222,7 +1222,7 @@ package soc_ifc_reg_uvm; if (has_coverage(UVM_CVR_FIELD_VALS)) fld_cg = new(); endfunction : build - endclass : soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK + endclass : soc_ifc_reg__CPTRA_FUSE_AXI_USER_LOCK // Reg - soc_ifc_reg::CPTRA_WDT_CFG class soc_ifc_reg__CPTRA_WDT_CFG extends uvm_reg; @@ -3731,10 +3731,10 @@ package soc_ifc_reg_uvm; rand soc_ifc_reg__CPTRA_FLOW_STATUS CPTRA_FLOW_STATUS; rand soc_ifc_reg__CPTRA_RESET_REASON CPTRA_RESET_REASON; rand soc_ifc_reg__CPTRA_SECURITY_STATE CPTRA_SECURITY_STATE; - rand soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID CPTRA_MBOX_VALID_AXI_ID[5]; - rand soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK CPTRA_MBOX_AXI_ID_LOCK[5]; - rand soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID CPTRA_TRNG_VALID_AXI_ID; - rand soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK CPTRA_TRNG_AXI_ID_LOCK; + rand soc_ifc_reg__CPTRA_MBOX_VALID_AXI_USER CPTRA_MBOX_VALID_AXI_USER[5]; + rand soc_ifc_reg__CPTRA_MBOX_AXI_USER_LOCK CPTRA_MBOX_AXI_USER_LOCK[5]; + rand soc_ifc_reg__CPTRA_TRNG_VALID_AXI_USER CPTRA_TRNG_VALID_AXI_USER; + rand soc_ifc_reg__CPTRA_TRNG_AXI_USER_LOCK CPTRA_TRNG_AXI_USER_LOCK; rand soc_ifc_reg__CPTRA_TRNG_DATA CPTRA_TRNG_DATA[12]; rand soc_ifc_reg__CPTRA_TRNG_CTRL CPTRA_TRNG_CTRL; rand soc_ifc_reg__CPTRA_TRNG_STATUS CPTRA_TRNG_STATUS; @@ -3755,8 +3755,8 @@ package soc_ifc_reg_uvm; rand soc_ifc_reg__CPTRA_WDT_TIMER2_CTRL CPTRA_WDT_TIMER2_CTRL; rand soc_ifc_reg__CPTRA_WDT_TIMER2_TIMEOUT_PERIOD CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[2]; rand soc_ifc_reg__CPTRA_WDT_STATUS CPTRA_WDT_STATUS; - rand soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID CPTRA_FUSE_VALID_AXI_ID; - rand soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK CPTRA_FUSE_AXI_ID_LOCK; + rand soc_ifc_reg__CPTRA_FUSE_VALID_AXI_USER CPTRA_FUSE_VALID_AXI_USER; + rand soc_ifc_reg__CPTRA_FUSE_AXI_USER_LOCK CPTRA_FUSE_AXI_USER_LOCK; rand soc_ifc_reg__CPTRA_WDT_CFG CPTRA_WDT_CFG[2]; rand soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_0 CPTRA_iTRNG_ENTROPY_CONFIG_0; rand soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_1 CPTRA_iTRNG_ENTROPY_CONFIG_1; @@ -3853,30 +3853,30 @@ package soc_ifc_reg_uvm; this.CPTRA_SECURITY_STATE.build(); this.default_map.add_reg(this.CPTRA_SECURITY_STATE, 'h44); - foreach(this.CPTRA_MBOX_VALID_AXI_ID[i0]) begin - this.CPTRA_MBOX_VALID_AXI_ID[i0] = new($sformatf("CPTRA_MBOX_VALID_AXI_ID[%0d]", i0)); - this.CPTRA_MBOX_VALID_AXI_ID[i0].configure(this); + foreach(this.CPTRA_MBOX_VALID_AXI_USER[i0]) begin + this.CPTRA_MBOX_VALID_AXI_USER[i0] = new($sformatf("CPTRA_MBOX_VALID_AXI_USER[%0d]", i0)); + this.CPTRA_MBOX_VALID_AXI_USER[i0].configure(this); - this.CPTRA_MBOX_VALID_AXI_ID[i0].build(); - this.default_map.add_reg(this.CPTRA_MBOX_VALID_AXI_ID[i0], 'h48 + i0*'h4); + this.CPTRA_MBOX_VALID_AXI_USER[i0].build(); + this.default_map.add_reg(this.CPTRA_MBOX_VALID_AXI_USER[i0], 'h48 + i0*'h4); end - foreach(this.CPTRA_MBOX_AXI_ID_LOCK[i0]) begin - this.CPTRA_MBOX_AXI_ID_LOCK[i0] = new($sformatf("CPTRA_MBOX_AXI_ID_LOCK[%0d]", i0)); - this.CPTRA_MBOX_AXI_ID_LOCK[i0].configure(this); + foreach(this.CPTRA_MBOX_AXI_USER_LOCK[i0]) begin + this.CPTRA_MBOX_AXI_USER_LOCK[i0] = new($sformatf("CPTRA_MBOX_AXI_USER_LOCK[%0d]", i0)); + this.CPTRA_MBOX_AXI_USER_LOCK[i0].configure(this); - this.CPTRA_MBOX_AXI_ID_LOCK[i0].build(); - this.default_map.add_reg(this.CPTRA_MBOX_AXI_ID_LOCK[i0], 'h5c + i0*'h4); + this.CPTRA_MBOX_AXI_USER_LOCK[i0].build(); + this.default_map.add_reg(this.CPTRA_MBOX_AXI_USER_LOCK[i0], 'h5c + i0*'h4); end - this.CPTRA_TRNG_VALID_AXI_ID = new("CPTRA_TRNG_VALID_AXI_ID"); - this.CPTRA_TRNG_VALID_AXI_ID.configure(this); + this.CPTRA_TRNG_VALID_AXI_USER = new("CPTRA_TRNG_VALID_AXI_USER"); + this.CPTRA_TRNG_VALID_AXI_USER.configure(this); - this.CPTRA_TRNG_VALID_AXI_ID.build(); - this.default_map.add_reg(this.CPTRA_TRNG_VALID_AXI_ID, 'h70); - this.CPTRA_TRNG_AXI_ID_LOCK = new("CPTRA_TRNG_AXI_ID_LOCK"); - this.CPTRA_TRNG_AXI_ID_LOCK.configure(this); + this.CPTRA_TRNG_VALID_AXI_USER.build(); + this.default_map.add_reg(this.CPTRA_TRNG_VALID_AXI_USER, 'h70); + this.CPTRA_TRNG_AXI_USER_LOCK = new("CPTRA_TRNG_AXI_USER_LOCK"); + this.CPTRA_TRNG_AXI_USER_LOCK.configure(this); - this.CPTRA_TRNG_AXI_ID_LOCK.build(); - this.default_map.add_reg(this.CPTRA_TRNG_AXI_ID_LOCK, 'h74); + this.CPTRA_TRNG_AXI_USER_LOCK.build(); + this.default_map.add_reg(this.CPTRA_TRNG_AXI_USER_LOCK, 'h74); foreach(this.CPTRA_TRNG_DATA[i0]) begin this.CPTRA_TRNG_DATA[i0] = new($sformatf("CPTRA_TRNG_DATA[%0d]", i0)); this.CPTRA_TRNG_DATA[i0].configure(this); @@ -3989,16 +3989,16 @@ package soc_ifc_reg_uvm; this.CPTRA_WDT_STATUS.build(); this.default_map.add_reg(this.CPTRA_WDT_STATUS, 'h104); - this.CPTRA_FUSE_VALID_AXI_ID = new("CPTRA_FUSE_VALID_AXI_ID"); - this.CPTRA_FUSE_VALID_AXI_ID.configure(this); + this.CPTRA_FUSE_VALID_AXI_USER = new("CPTRA_FUSE_VALID_AXI_USER"); + this.CPTRA_FUSE_VALID_AXI_USER.configure(this); - this.CPTRA_FUSE_VALID_AXI_ID.build(); - this.default_map.add_reg(this.CPTRA_FUSE_VALID_AXI_ID, 'h108); - this.CPTRA_FUSE_AXI_ID_LOCK = new("CPTRA_FUSE_AXI_ID_LOCK"); - this.CPTRA_FUSE_AXI_ID_LOCK.configure(this); + this.CPTRA_FUSE_VALID_AXI_USER.build(); + this.default_map.add_reg(this.CPTRA_FUSE_VALID_AXI_USER, 'h108); + this.CPTRA_FUSE_AXI_USER_LOCK = new("CPTRA_FUSE_AXI_USER_LOCK"); + this.CPTRA_FUSE_AXI_USER_LOCK.configure(this); - this.CPTRA_FUSE_AXI_ID_LOCK.build(); - this.default_map.add_reg(this.CPTRA_FUSE_AXI_ID_LOCK, 'h10c); + this.CPTRA_FUSE_AXI_USER_LOCK.build(); + this.default_map.add_reg(this.CPTRA_FUSE_AXI_USER_LOCK, 'h10c); foreach(this.CPTRA_WDT_CFG[i0]) begin this.CPTRA_WDT_CFG[i0] = new($sformatf("CPTRA_WDT_CFG[%0d]", i0)); this.CPTRA_WDT_CFG[i0].configure(this); diff --git a/src/soc_ifc/rtl/soc_ifc_top.sv b/src/soc_ifc/rtl/soc_ifc_top.sv index 33811e707..fb37b05ae 100644 --- a/src/soc_ifc/rtl/soc_ifc_top.sv +++ b/src/soc_ifc/rtl/soc_ifc_top.sv @@ -188,7 +188,7 @@ soc_ifc_req_t dma_sram_req_data; logic [SOC_IFC_DATA_W-1:0] dma_sram_rdata; logic dma_sram_error; -logic [4:0][AXI_ID_WIDTH-1:0] valid_mbox_ids; +logic [4:0][AXI_USER_WIDTH-1:0] valid_mbox_users; // Pulse signals to trigger interrupts logic uc_mbox_data_avail; @@ -203,7 +203,7 @@ logic sram_double_ecc_error; logic soc_req_mbox_lock; logic [1:0] generic_input_toggle; mbox_protocol_error_t mbox_protocol_error; -logic mbox_inv_id_p; +logic mbox_inv_user_p; logic uc_mbox_lock; logic iccm_unlock; @@ -245,8 +245,8 @@ logic t2_timeout_p; logic wdt_error_t1_intr_serviced; logic wdt_error_t2_intr_serviced; -logic valid_trng_id; -logic valid_fuse_id; +logic valid_trng_user; +logic valid_fuse_user; boot_fsm_state_e boot_fsm_ps; @@ -305,7 +305,7 @@ axi_sub #( .dv (soc_req_dv ), .addr (soc_req.addr ), // Byte address .write (soc_req.write ), - .user (/*soc_req.user*/), + .user (soc_req.user ), .id (soc_req.id ), .wdata (soc_req.wdata ), // Requires: Component dwidth == AXI dwidth .wstrb (soc_req.wstrb ), // Requires: Component dwidth == AXI dwidth @@ -356,7 +356,7 @@ i_ahb_slv_sif_soc_ifc ( .rdata(uc_req_rdata) ); -//always_comb uc_req.user = '1; +always_comb uc_req.user = '1; always_comb uc_req.id = '1; always_comb uc_req.soc_req = 1'b0; always_comb uc_req.wstrb = {AHB_DATA_WIDTH/8{1'b1}}; @@ -366,13 +366,13 @@ always_comb uc_req.wstrb = {AHB_DATA_WIDTH/8{1'b1}}; //Requests are serviced using round robin arbitration soc_ifc_arb #( - .AXI_ID_WIDTH(AXI_ID_WIDTH) + .AXI_USER_WIDTH(AXI_USER_WIDTH) ) i_soc_ifc_arb ( .clk(soc_ifc_clk_cg), .rst_b(cptra_noncore_rst_b), - .valid_mbox_ids(valid_mbox_ids), - .valid_fuse_id(valid_fuse_id), + .valid_mbox_users(valid_mbox_users), + .valid_fuse_user(valid_fuse_user), //UC inf .uc_req_dv(uc_req_dv), .uc_req_hold(uc_req_hold), @@ -580,23 +580,23 @@ always_comb scan_mode_p = scan_mode & ~scan_mode_f; always_comb begin for (int i=0; i<5; i++) begin //once locked, can't be cleared until reset - soc_ifc_reg_hwif_in.CPTRA_MBOX_AXI_ID_LOCK[i].LOCK.swwel = soc_ifc_reg_hwif_out.CPTRA_MBOX_AXI_ID_LOCK[i].LOCK.value; + soc_ifc_reg_hwif_in.CPTRA_MBOX_AXI_USER_LOCK[i].LOCK.swwel = soc_ifc_reg_hwif_out.CPTRA_MBOX_AXI_USER_LOCK[i].LOCK.value; //lock the writes to valid id field once lock is set - soc_ifc_reg_hwif_in.CPTRA_MBOX_VALID_AXI_ID[i].AXI_ID.swwel = soc_ifc_reg_hwif_out.CPTRA_MBOX_AXI_ID_LOCK[i].LOCK.value; - //If integrator set AXI_ID values at integration time, pick it up from the define - valid_mbox_ids[i] = CPTRA_SET_MBOX_AXI_ID_INTEG[i] ? CPTRA_MBOX_VALID_AXI_ID[i][AXI_ID_WIDTH-1:0] : - soc_ifc_reg_hwif_out.CPTRA_MBOX_AXI_ID_LOCK[i].LOCK.value ? - soc_ifc_reg_hwif_out.CPTRA_MBOX_VALID_AXI_ID[i].AXI_ID.value[AXI_ID_WIDTH-1:0] : CPTRA_DEF_MBOX_VALID_AXI_ID; + soc_ifc_reg_hwif_in.CPTRA_MBOX_VALID_AXI_USER[i].AXI_USER.swwel = soc_ifc_reg_hwif_out.CPTRA_MBOX_AXI_USER_LOCK[i].LOCK.value; + //If integrator set AXI_USER values at integration time, pick it up from the define + valid_mbox_users[i] = CPTRA_SET_MBOX_AXI_USER_INTEG[i] ? CPTRA_MBOX_VALID_AXI_USER[i][AXI_USER_WIDTH-1:0] : + soc_ifc_reg_hwif_out.CPTRA_MBOX_AXI_USER_LOCK[i].LOCK.value ? + soc_ifc_reg_hwif_out.CPTRA_MBOX_VALID_AXI_USER[i].AXI_USER.value[AXI_USER_WIDTH-1:0] : CPTRA_DEF_MBOX_VALID_AXI_USER; end end //can't write to trng valid id after it is locked -always_comb soc_ifc_reg_hwif_in.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.swwel = soc_ifc_reg_hwif_out.CPTRA_TRNG_AXI_ID_LOCK.LOCK.value; -always_comb soc_ifc_reg_hwif_in.CPTRA_TRNG_AXI_ID_LOCK.LOCK.swwel = soc_ifc_reg_hwif_out.CPTRA_TRNG_AXI_ID_LOCK.LOCK.value; +always_comb soc_ifc_reg_hwif_in.CPTRA_TRNG_VALID_AXI_USER.AXI_USER.swwel = soc_ifc_reg_hwif_out.CPTRA_TRNG_AXI_USER_LOCK.LOCK.value; +always_comb soc_ifc_reg_hwif_in.CPTRA_TRNG_AXI_USER_LOCK.LOCK.swwel = soc_ifc_reg_hwif_out.CPTRA_TRNG_AXI_USER_LOCK.LOCK.value; -//fuse register AXI ID fields -always_comb soc_ifc_reg_hwif_in.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_AXI_ID_LOCK.LOCK.value; -always_comb soc_ifc_reg_hwif_in.CPTRA_FUSE_AXI_ID_LOCK.LOCK.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_AXI_ID_LOCK.LOCK.value; +//fuse register AXI USER fields +always_comb soc_ifc_reg_hwif_in.CPTRA_FUSE_VALID_AXI_USER.AXI_USER.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_AXI_USER_LOCK.LOCK.value; +always_comb soc_ifc_reg_hwif_in.CPTRA_FUSE_AXI_USER_LOCK.LOCK.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_AXI_USER_LOCK.LOCK.value; ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// // Can't write to RW-able fuses once fuse_done is set (implies the register is being locked using the fuse_wr_done) @@ -654,16 +654,16 @@ always_comb soc_ifc_reg_hwif_in.fuse_soc_stepping_id.soc_stepping_id.swwel = soc always_comb soc_ifc_reg_hwif_in.CPTRA_FUSE_WR_DONE.done.swwe = soc_ifc_reg_req_data.soc_req & ~soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value; ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -//When TRNG_AXI_ID_LOCK is one only allow valid ids to write to TRNG -//If TRNG_AXI_ID_LOCK is zero allow any id to write to TRNG -always_comb valid_trng_id = soc_ifc_reg_req_data.soc_req & (~soc_ifc_reg_hwif_out.CPTRA_TRNG_AXI_ID_LOCK.LOCK.value | - (soc_ifc_reg_req_data.id == soc_ifc_reg_hwif_out.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.value[AXI_ID_WIDTH-1:0])); +//When TRNG_AXI_USER_LOCK is one only allow valid users to write to TRNG +//If TRNG_AXI_USER_LOCK is zero allow any id to write to TRNG +always_comb valid_trng_user = soc_ifc_reg_req_data.soc_req & (~soc_ifc_reg_hwif_out.CPTRA_TRNG_AXI_USER_LOCK.LOCK.value | + (soc_ifc_reg_req_data.user == soc_ifc_reg_hwif_out.CPTRA_TRNG_VALID_AXI_USER.AXI_USER.value[AXI_USER_WIDTH-1:0])); -always_comb soc_ifc_reg_hwif_in.CPTRA_TRNG_STATUS.DATA_WR_DONE.swwe = valid_trng_id; +always_comb soc_ifc_reg_hwif_in.CPTRA_TRNG_STATUS.DATA_WR_DONE.swwe = valid_trng_user; always_comb begin for (int i = 0; i < 12; i++) begin - soc_ifc_reg_hwif_in.CPTRA_TRNG_DATA[i].DATA.swwe = valid_trng_id; + soc_ifc_reg_hwif_in.CPTRA_TRNG_DATA[i].DATA.swwe = valid_trng_user; soc_ifc_reg_hwif_in.CPTRA_TRNG_DATA[i].DATA.hwclr = soc_ifc_reg_hwif_out.CPTRA_TRNG_CTRL.clear.value; end end @@ -672,11 +672,11 @@ end always_comb soc_ifc_reg_hwif_in.CPTRA_TRNG_STATUS.DATA_WR_DONE.hwclr = ~soc_ifc_reg_hwif_out.CPTRA_TRNG_STATUS.DATA_REQ.value; generate - if (CPTRA_SET_FUSE_AXI_ID_INTEG) begin - always_comb valid_fuse_id = soc_req_dv & (soc_req.id == CPTRA_FUSE_VALID_AXI_ID); + if (CPTRA_SET_FUSE_AXI_USER_INTEG) begin + always_comb valid_fuse_user = soc_req_dv & (soc_req.user == CPTRA_FUSE_VALID_AXI_USER); end else begin - always_comb valid_fuse_id = soc_req_dv & (~soc_ifc_reg_hwif_out.CPTRA_FUSE_AXI_ID_LOCK.LOCK.value | - (soc_req.id == soc_ifc_reg_hwif_out.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.value[AXI_ID_WIDTH-1:0])); + always_comb valid_fuse_user = soc_req_dv & (~soc_ifc_reg_hwif_out.CPTRA_FUSE_AXI_USER_LOCK.LOCK.value | + (soc_req.user == soc_ifc_reg_hwif_out.CPTRA_FUSE_VALID_AXI_USER.AXI_USER.value[AXI_USER_WIDTH-1:0])); end endgenerate // Generate a pulse to set the interrupt bit @@ -692,7 +692,7 @@ end always_comb uc_cmd_avail_p = uc_mbox_data_avail & !uc_mbox_data_avail_d; // Pulse input to soc_ifc_reg to set the interrupt status bit and generate interrupt output (if enabled) always_comb soc_ifc_reg_hwif_in.intr_block_rf.error_internal_intr_r.error_internal_sts.hwset = 1'b0; // TODO -always_comb soc_ifc_reg_hwif_in.intr_block_rf.error_internal_intr_r.error_inv_dev_sts.hwset = mbox_inv_id_p; // All invalid ids, or only 'valid id but != mbox_id.id'? +always_comb soc_ifc_reg_hwif_in.intr_block_rf.error_internal_intr_r.error_inv_dev_sts.hwset = mbox_inv_user_p; // All invalid user, or only 'valid user but != mbox_user.user'? always_comb soc_ifc_reg_hwif_in.intr_block_rf.error_internal_intr_r.error_cmd_fail_sts.hwset = |mbox_protocol_error; // Set by any protocol error violation (mirrors the bits in CPTRA_HW_ERROR_NON_FATAL) always_comb soc_ifc_reg_hwif_in.intr_block_rf.error_internal_intr_r.error_bad_fuse_sts.hwset = 1'b0; // TODO always_comb soc_ifc_reg_hwif_in.intr_block_rf.error_internal_intr_r.error_iccm_blocked_sts.hwset = iccm_axs_blocked; @@ -737,13 +737,13 @@ soc_ifc_reg i_soc_ifc_reg ( .hwif_out(soc_ifc_reg_hwif_out) ); -//Mask read data to TRNG DATA when TRNG AXI_ID is locked and the requester isn't the correct AXI_ID +//Mask read data to TRNG DATA when TRNG AXI_USER is locked and the requester isn't the correct AXI_USER always_comb begin soc_ifc_reg_rdata_mask = 0; for (int i = 0; i < 12; i++) begin soc_ifc_reg_rdata_mask |= soc_ifc_reg_req_data.soc_req & soc_ifc_reg_hwif_out.CPTRA_TRNG_DATA[i].DATA.swacc & - soc_ifc_reg_hwif_out.CPTRA_TRNG_AXI_ID_LOCK.LOCK.value & - (soc_ifc_reg_req_data.id != soc_ifc_reg_hwif_out.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.value[AXI_ID_WIDTH-1:0]); + soc_ifc_reg_hwif_out.CPTRA_TRNG_AXI_USER_LOCK.LOCK.value & + (soc_ifc_reg_req_data.user != soc_ifc_reg_hwif_out.CPTRA_TRNG_VALID_AXI_USER.AXI_USER.value[AXI_USER_WIDTH-1:0]); end end @@ -877,7 +877,7 @@ i_mbox ( .uc_mbox_data_avail(uc_mbox_data_avail), .soc_req_mbox_lock(soc_req_mbox_lock), .mbox_protocol_error(mbox_protocol_error), - .mbox_inv_axi_id_axs(mbox_inv_id_p), + .mbox_inv_axi_user_axs(mbox_inv_user_p), .dmi_inc_rdptr(dmi_inc_rdptr), .dmi_reg(mbox_dmi_reg) );