diff --git a/src/ecc/rtl/ecc_reg.rdl b/src/ecc/rtl/ecc_reg.rdl index 12239e82f..57ea07c4c 100644 --- a/src/ecc/rtl/ecc_reg.rdl +++ b/src/ecc/rtl/ecc_reg.rdl @@ -38,8 +38,7 @@ addrmap ecc_reg { reg { name = "ECC component name register type definition"; desc = "Two 32-bit read-only registers repereseting of the name - of ECC component. These registers are located at - ECC_base_address + 0x0000_0000 and 0x0000_0004 addresses."; + of ECC component."; default sw = r; default hw = w; @@ -53,8 +52,7 @@ addrmap ecc_reg { reg { name = "ECC component version register type definition"; desc = "Two 32-bit read-only registers repereseting of the version - of ECC component. These registers are located at - ECC_base_address + 0x0000_0008 and 0x0000_000C addresses."; + of ECC component."; default sw = r; default hw = w; @@ -66,23 +64,19 @@ addrmap ecc_reg { /* ---- ECC Component Control ---- */ reg { - name = "ECC component control register type definition"; - desc = "One 4-bit register to set the type of ECC operations. - [br] bit #[1:0]: This can be: - [br] 00 for NONE - [br] 01 for KEYGEN - [br] 10 for SIGNING - [br] 11 for VERIFYING - [br] bit #2: Zeroize all internal registers after ECC process, to avoid SCA leakage. - [br] bit #3: Run ECC Signing flow to sign PCRs. - [br] This register is located at ECC_base_address + 0x0000_0010."; + name = "ECC CTRL"; + desc = "ECC component control register type definition"; default sw = w; default hw = r; default resetsignal = reset_b; - field {desc = "Control command field"; swwe = ecc_ready; hwclr;} CTRL[2] = 2'b0; - field {desc = "Zeroize all internal registers"; singlepulse;} ZEROIZE = 1'b0; - field {desc = "Run PCR Signing flow"; swwe = ecc_ready; hwclr;} PCR_SIGN = 1'b0; + field {desc = "Control command field: This can be: + [br] 00 for NONE + [br] 01 for KEYGEN + [br] 10 for SIGNING + [br] 11 for VERIFYING"; swwe = ecc_ready; hwclr;} CTRL[2] = 2'b0; + field {desc = "Zeroize all internal registers: Zeroize all internal registers after ECC process, to avoid SCA leakage."; singlepulse;} ZEROIZE = 1'b0; + field {desc = "Run PCR Signing flow: Run ECC Signing flow to sign PCRs."; swwe = ecc_ready; hwclr;} PCR_SIGN = 1'b0; } ECC_CTRL @0x00000010; @@ -90,30 +84,26 @@ addrmap ecc_reg { /* ---- ECC Component Status ---- */ reg { - name = "ECC component status register type definition"; - desc = "One 2-bit register including the following flags: - bit #0: READY : ​Indicates if the core is ready to take - a control command and process the block. - bit #1: VALID : ​Indicates if the process is done and the - hash value stored in DIGEST registers is valid. - This register is located at ECC_base_address + 0x0000_0018."; + name = "ECC STATUS"; + desc = "ECC component status register type definition"; default sw = r; default hw = w; default resetsignal = reset_b; - field {desc = "Status ready bit";} READY = 1'b0; - field {desc = "Status valid bit";} VALID = 1'b0; + field {desc = "Status ready bit: ​Indicates if the core is ready to take + a control command and process the block.";} READY = 1'b0; + field {desc = "Status valid bit: ​Indicates if the process is done and the + hash value stored in DIGEST registers is valid.";} VALID = 1'b0; } ECC_STATUS @0x00000018; /* ---- ECC Component Input SEED ---- */ reg { - name = "ECC component seed register type definition"; - desc = "12 32-bit registers storing the 384-bit seed for keygen. - The seed can be any 384-bit value in [0 : 2^384-1]. - These registers are located at ECC_base_address + - 0x0000_0080 to 0x0000_00AC in big-endian representation."; + name = "ECC SEED"; + desc = "ECC component seed register type definition + 12 32-bit registers storing the 384-bit seed for keygen. + The seed can be any 384-bit value in [0 : 2^384-1]."; default sw = w; default hw = rw; @@ -126,11 +116,10 @@ addrmap ecc_reg { /* ---- ECC Component Input NONCE ---- */ reg { - name = "ECC component nonce register type definition"; - desc = "12 32-bit registers storing the 384-bit nonce for keygen. - The nonce can be any 384-bit value in [0 : 2^384-1]. - These registers are located at ECC_base_address + - 0x0000_0500 to 0x0000_052C in big-endian representation."; + name = "ECC NONCE"; + desc = "ECC component nonce register type definition + 12 32-bit registers storing the 384-bit nonce for keygen. + The nonce can be any 384-bit value in [0 : 2^384-1]."; default sw = w; default hw = r; @@ -143,12 +132,11 @@ addrmap ecc_reg { /* ---- ECC Component Input Message ---- */ reg { - name = "ECC component hashed message register type definition"; - desc = "12 32-bit registers storing the hash of the message respect + name = "ECC_MSG"; + desc = "ECC component hashed message register type definition + 12 32-bit registers storing the hash of the message respect to SHA384 algorithm. - The hashed message can be any 384-bit value in [0 : 2^384-1]. - These registers are located at ECC_base_address + - 0x0000_0100 to 0x0000_012C in big-endian representation."; + The hashed message can be any 384-bit value in [0 : 2^384-1]."; default sw = w; default hw = rw; @@ -162,13 +150,12 @@ addrmap ecc_reg { /* ---- ECC Component Private Key OUT---- */ reg { - name = "ECC component private key output register type definition"; - desc = "12 32-bit registers storing the private key for keygen. + name = "ECC PRIVKEY OUT"; + desc = "ECC component private key output register type definition + 12 32-bit registers storing the private key for keygen. These registers is read by ECC user after keygen operation. The private key is in [1 : q-1] while q is the group - order of the Secp384r1 curve. - These registers are located at ECC_base_address + - 0x0000_0180 to 0x0000_01AC in big-endian representation."; + order of the Secp384r1 curve."; default sw = r; default hw = w; @@ -180,13 +167,12 @@ addrmap ecc_reg { /* ---- ECC Component Private Key IN---- */ reg { - name = "ECC component private key input register type definition"; - desc = "12 32-bit registers storing the private key for signing. + name = "ECC PRIVKEY IN"; + desc = "ECC component private key input register type definition + 12 32-bit registers storing the private key for signing. These registers is set before signing operation. The private key should be in [1 : q-1] while q is the group - order of the Secp384r1 curve. - These registers are located at ECC_base_address + - 0x0000_0580 to 0x0000_05AC in big-endian representation."; + order of the Secp384r1 curve."; default sw = w; default hw = rw; @@ -199,14 +185,13 @@ addrmap ecc_reg { /* ---- ECC Component Public Key x ---- */ reg { - name = "ECC component public key (x) register type definition"; - desc = "12 32-bit registers storing the x coordinate of public key. + name = "ECC PUBKEY X"; + desc = "ECC component public key (x) register type definition + 12 32-bit registers storing the x coordinate of public key. These registers is read by ECC user after keygen operation, or be set before verifying operation. The public key x should be in [1 : p-1] while p is the prime - number of the Secp384r1 curve. - These registers are located at ECC_base_address + - 0x0000_0200 to 0x0000_022C in big-endian representation."; + number of the Secp384r1 curve."; default sw = rw; default hw = rw; @@ -219,14 +204,13 @@ addrmap ecc_reg { /* ---- ECC Component Public Key y ---- */ reg { - name = "ECC component public key (y) register type definition"; - desc = "12 32-bit registers storing the y coordinate of public key. + name = "ECC PUBKEY Y"; + desc = "ECC component public key (y) register type definition + 12 32-bit registers storing the y coordinate of public key. These registers is read by ECC user after keygen operation, or be set before verifying operation. The public key y should be in [1 : p-1] while p is the prime - number of the Secp384r1 curve. - These registers are located at ECC_base_address + - 0x0000_0280 to 0x0000_02AC in big-endian representation."; + number of the Secp384r1 curve."; default sw = rw; default hw = rw; @@ -240,17 +224,16 @@ addrmap ecc_reg { /* ---- ECC Component Signature R ---- */ reg { - name = "ECC component signature R register type definition"; - desc = "12 32-bit registers storing the signature R of the message. + name = "ECC SIGN R"; + desc = "ECC component signature R register type definition + 12 32-bit registers storing the signature R of the message. These registers is read by ECC user after signing operation, or be set before verifying operation. The signature R should be in [1 : q-1] while q is the group order of the Secp384r1 curve. Based on RFC6979, If R turns out to be zero, a new nonce (by changing the private key or the message) should be selected and R computed - again (this is an utterly improbable occurrence). - These registers are located at ECC_base_address + - 0x0000_0300 to 0x0000_032C in big-endian representation."; + again (this is an utterly improbable occurrence)."; default sw = rw; default hw = rw; @@ -264,14 +247,13 @@ addrmap ecc_reg { /* ---- ECC Component Signature S ---- */ reg { - name = "ECC component signature S register type definition"; - desc = "12 32-bit registers storing the signature S of the message. + name = "ECC SIGN S"; + desc = "ECC component signature S register type definition + 12 32-bit registers storing the signature S of the message. These registers is read by ECC user after signing operation, or be set before verifying operation. The signature S should be in [1 : q-1] while q is the group - order of the Secp384r1 curve. - These registers are located at ECC_base_address + - 0x0000_0380 to 0x0000_03AC in big-endian representation."; + order of the Secp384r1 curve."; default sw = rw; default hw = rw; @@ -286,14 +268,13 @@ addrmap ecc_reg { /* ---- ECC Component Verify R Result ---- */ reg { - name = "ECC component verify R result register type definition"; - desc = "12 32-bit registers storing the result of verifying operation. + name = "ECC VERIFY R"; + desc = "ECC component verify R result register type definition + 12 32-bit registers storing the result of verifying operation. Firmware is responsible for comparing the computed result with the signature R, and if they are equal the signature is valid. The verify R result should be in [1 : q-1] while q is the group - order of the Secp384r1 curve. - These registers are located at ECC_base_address + - 0x0000_0400 to 0x0000_042C in big-endian representation."; + order of the Secp384r1 curve."; default sw = r; default hw = rw; @@ -307,13 +288,12 @@ addrmap ecc_reg { /* ---- ECC Component Input IV ---- */ reg { - name = "ECC component IV register type definition"; - desc = "12 32-bit registers storing the 384-bit IV required + name = "ECC IV"; + desc = "ECC component IV register type definition + 12 32-bit registers storing the 384-bit IV required for SCA countermeasures to randomize the inputs with no change on the ECC outputs. - The IV can be any 384-bit value in [0 : 2^384-1]. - These registers are located at ECC_base_address + - 0x0000_0480 to 0x0000_04AC in big-endian representation."; + The IV can be any 384-bit value in [0 : 2^384-1]."; default sw = w; default hw = r; diff --git a/src/hmac/rtl/hmac_reg.rdl b/src/hmac/rtl/hmac_reg.rdl index d800877ad..4dcc6947f 100644 --- a/src/hmac/rtl/hmac_reg.rdl +++ b/src/hmac/rtl/hmac_reg.rdl @@ -36,8 +36,7 @@ addrmap hmac_reg { reg { name = "HMAC384 component name register type definition"; desc = "Two 32-bit read-only registers repereseting of the name - of HMAC384 component. These registers are located at - HMAC384_base_address + 0x0000_0000 and 0x0000_0004 addresses."; + of HMAC384 component."; default sw = r; default hw = w; @@ -51,8 +50,7 @@ addrmap hmac_reg { reg { name = "HMAC384 component version register type definition"; desc = "Two 32-bit read-only registers repereseting of the version - of HMAC384 component. These registers are located at - HMAC384_base_address + 0x0000_0008 and 0x0000_000C addresses."; + of HMAC384 component."; default sw = r; default hw = w; @@ -64,23 +62,18 @@ addrmap hmac_reg { /* ---- HMAC384 Component Control ---- */ reg { - name = "HMAC384 component control register type definition"; - desc = "One 3-bit register including the following flags: - bit #0: INIT : Trigs the HMAC384 core to start the - processing for the key and the first padded - message block. - bit #1: NEXT: ​Trigs the HMAC384 core to start the - processing for the remining padded message block. - bit #3: Zeroize all internal registers after HMAC process, to avoid SCA leakage. - This register is located at HMAC384_base_address + 0x0000_0010 - After each software write, hardware will erase the register."; + name = "HMAC384 CTRL"; + desc = "HMAC384 component control register type definition"; default sw = w; default hw = r; default resetsignal = reset_b; - field {desc = "Control init command bit"; singlepulse;} INIT = 1'b0; - field {desc = "Control next command bit"; singlepulse;} NEXT = 1'b0; - field {desc = "Zeroize all internal registers"; singlepulse;} ZEROIZE = 1'b0; + field {desc = "Control init command bit: Trigs the HMAC384 core to start the + processing for the key and the first padded + message block."; singlepulse;} INIT = 1'b0; + field {desc = "Control next command bit: ​Trigs the HMAC384 core to start the + processing for the remining padded message block. "; singlepulse;} NEXT = 1'b0; + field {desc = "Zeroize all internal registers: Zeroize all internal registers after HMAC process, to avoid SCA leakage."; singlepulse;} ZEROIZE = 1'b0; } HMAC384_CTRL @0x00000010; @@ -88,19 +81,16 @@ addrmap hmac_reg { /* ---- HMAC384 Component Status ---- */ reg { - name = "HMAC384 component status register type definition"; - desc = "One 2-bit register including the following flags: - bit #0: READY : ​Indicates if the core is ready to take - a control command and process the block. - bit #1: Valid: ​Indicates if the process is done and the - results stored in TAG registers are valid. - This register is located at HMAC384_base_address + 0x0000_0018."; + name = "HMAC384 STATUS"; + desc = "HMAC384 component status register type definition"; default sw = r; default hw = w; default resetsignal = reset_b; - field {desc = "Status ready bit";} READY = 1'b0; - field {desc = "Status valid bit";} VALID = 1'b0; + field {desc = "Status ready bit: ​Indicates if the core is ready to take + a control command and process the block.";} READY = 1'b0; + field {desc = "Status valid bit: ​Indicates if the process is done and the + results stored in TAG registers are valid.";} VALID = 1'b0; } HMAC384_STATUS @0x00000018; @@ -108,10 +98,9 @@ addrmap hmac_reg { /* ---- HMAC384 Component Input Key ---- */ reg { - name = "HMAC384 component key register type definition"; - desc = "12 32-bit registers storing the 384-bit key. - These registers are located at HMAC384_base_address + - 0x0000_0040 to 0x0000_006C in big-endian representation."; + name = "HMAC384 KEY"; + desc = "HMAC384 component key register type definition + 12 32-bit registers storing the 384-bit key."; default sw = w; default hw = rw; @@ -125,10 +114,9 @@ addrmap hmac_reg { /* ---- HMAC384 Component Input Message Block ---- */ reg { - name = "HMAC384 component block register type definition"; - desc = "32 32-bit registers storing the 1024-bit padded input. - These registers are located at HMAC384_base_address + - 0x0000_0080 to 0x0000_00FC in big-endian representation."; + name = "HMAC384 BLOCK"; + desc = "HMAC384 component block register type definition + 32 32-bit registers storing the 1024-bit padded input."; default sw = w; default hw = rw; @@ -142,10 +130,9 @@ addrmap hmac_reg { /* ---- HMAC384 Component Output Tag ---- */ reg { - name = "HMAC384 component tag register type definition"; - desc = "12 32-bit registers storing the 384-bit digest output. - These registers are located at HMAC384_base_address + - 0x0000_0100 to 0x0000_012C in big-endian representation."; + name = "HMAC384 TAG"; + desc = "HMAC384 component tag register type definition + 12 32-bit registers storing the 384-bit digest output."; default sw = r; default hw = w; @@ -157,10 +144,9 @@ addrmap hmac_reg { /* ---- HMAC384 Component Input LFSR Seed ---- */ reg { - name = "HMAC384 component lfsr seed register type definition"; - desc = "12 32-bit registers storing the 384-bit lfsr seed input. - These registers are located at HMAC384_base_address + - 0x0000_0130 to 0x0000_015C in big-endian representation."; + name = "HMAC384 LFSR SEED"; + desc = "HMAC384 component lfsr seed register type definition + 12 32-bit registers storing the 384-bit lfsr seed input."; default sw = w; default hw = r; diff --git a/src/sha256/rtl/sha256_reg.rdl b/src/sha256/rtl/sha256_reg.rdl index ce707fdb8..b930e0755 100644 --- a/src/sha256/rtl/sha256_reg.rdl +++ b/src/sha256/rtl/sha256_reg.rdl @@ -38,8 +38,7 @@ addrmap sha256_reg { reg { name = "SHA256 component name register type definition"; desc = "Two 32-bit read-only registers repereseting of the name - of SHA256 component. These registers are located at - SHA256_base_address + 0x0000_0000 and 0x0000_0004 addresses."; + of SHA256 component."; default sw = r; default hw = w; @@ -53,8 +52,7 @@ addrmap sha256_reg { reg { name = "SHA256 component version register type definition"; desc = "Two 32-bit read-only registers repereseting of the version - of SHA256 component. These registers are located at - SHA256_base_address + 0x0000_0008 and 0x0000_000C addresses."; + of SHA256 component."; default sw = r; default hw = w; @@ -66,27 +64,22 @@ addrmap sha256_reg { /* ---- SHA256 Component Control ---- */ reg { - name = "SHA256 component control register type definition"; - desc = "One 4-bit register including the following flags: - bit #0: INIT : Trigs the SHA256 core to start the - processing for the first padded message block. - bit #1: NEXT: ​Trigs the SHA256 core to start the - processing for the remining padded message block. - bit #2: MODE : Indicates the SHA256 core to set dynamically - the type of hashing algorithm. This can be: - 0 for SHA256/224 - 1 for SHA256 - bit #3: Zeroize all internal registers after SHA process, to avoid SCA leakage. - This register is located at SHA256_base_address + 0x0000_0010 + name = "SHA256 CTRL"; + desc = "SHA256 component control register type definition. After each software write, hardware will erase the register."; default sw = w; default hw = r; default resetsignal = reset_b; - field {desc = "Control init command bit"; singlepulse;} INIT = 1'b0; - field {desc = "Control next command bit"; singlepulse;} NEXT = 1'b0; - field {desc = "Control mode command bits"; swwe = sha256_ready;} MODE = 1'b1; - field {desc = "Zeroize all internal registers"; singlepulse;} ZEROIZE = 1'b0; + field {desc = "Control init command bit: Trigs the SHA256 core to start the + processing for the first padded message block."; singlepulse;} INIT = 1'b0; + field {desc = "Control next command bit: ​Trigs the SHA256 core to start the + processing for the remining padded message block."; singlepulse;} NEXT = 1'b0; + field {desc = "Control mode command bits: Indicates the SHA256 core to set dynamically + the type of hashing algorithm. This can be: + 0 for SHA256/224 + 1 for SHA256"; swwe = sha256_ready;} MODE = 1'b1; + field {desc = "Zeroize all internal registers: Zeroize all internal registers after SHA process, to avoid SCA leakage."; singlepulse;} ZEROIZE = 1'b0; field {desc = "Control Winternitz verification mode command bits"; singlepulse; swwe = sha256_ready;} WNTZ_MODE = 1'b0; field {desc = "Control Winternitz W value"; swwe = sha256_ready;} WNTZ_W[4] = 4'h4; field {desc = "Control Winternitz n value(SHA192/SHA256 --> n = 24/32)"; swwe = sha256_ready;} WNTZ_N_MODE = 1'b0; @@ -95,29 +88,25 @@ addrmap sha256_reg { /* ---- SHA256 Component Status ---- */ reg { - name = "SHA256 component status register type definition"; - desc = "One 2-bit register including the following flags: - bit #0: READY : ​Indicates if the core is ready to take - a control command and process the block. - bit #1: Valid: ​Indicates if the process is done and the - hash value stored in DIGEST registers is valid. - This register is located at SHA256_base_address + 0x0000_0018."; + name = "SHA256_STATUS"; + desc = "SHA256 component status register type definition"; default sw = r; default hw = w; default resetsignal = reset_b; - field {desc = "Status ready bit";} READY = 1'b0; - field {desc = "Status valid bit";} VALID = 1'b0; + field {desc = "Status ready bit: ​Indicates if the core is ready to take + a control command and process the block.";} READY = 1'b0; + field {desc = "Status valid bit: ​Indicates if the process is done and the + hash value stored in DIGEST registers is valid.";} VALID = 1'b0; field {desc = "Winternitz busy status bit";} WNTZ_BUSY = 1'b0; } SHA256_STATUS @0x00000018; /* ---- SHA256 Component Input Message Block ---- */ reg { - name = "SHA256 component block register type definition"; - desc = "16 32-bit registers storing the 512-bit padded input. - These registers are located at SHA256_base_address + - 0x0000_0080 to 0x0000_00BC in big-endian representation."; + name = "SHA256 BLOCK"; + desc = "SHA256 component block register type definition. + 16 32-bit registers storing the 512-bit padded input."; default sw = w; default hw = r; @@ -128,10 +117,9 @@ addrmap sha256_reg { /* ---- SHA256 Component Output Digest ---- */ reg { - name = "SHA256 component digest register type definition"; - desc = "8 32-bit registers storing the 256-bit digest output. - These registers are located at SHA256_base_address + - 0x0000_0100 to 0x0000_011C in big-endian representation."; + name = "SHA256 DIGEST"; + desc = "SHA256 component digest register type definition + 8 32-bit registers storing the 256-bit digest output."; default sw = r; default hw = w; diff --git a/src/sha512/rtl/sha512_reg.rdl b/src/sha512/rtl/sha512_reg.rdl index ae222e04c..3dcfbf946 100644 --- a/src/sha512/rtl/sha512_reg.rdl +++ b/src/sha512/rtl/sha512_reg.rdl @@ -35,8 +35,7 @@ addrmap sha512_reg { reg { name = "SHA512 component name register type definition"; desc = "Two 32-bit read-only registers repereseting of the name - of SHA512 component. These registers are located at - SHA512_base_address + 0x0000_0000 and 0x0000_0004 addresses."; + of SHA512 component."; default sw = r; default hw = w; @@ -50,8 +49,7 @@ addrmap sha512_reg { reg { name = "SHA512 component version register type definition"; desc = "Two 32-bit read-only registers repereseting of the version - of SHA512 component. These registers are located at - SHA512_base_address + 0x0000_0008 and 0x0000_000C addresses."; + of SHA512 component."; default sw = r; default hw = w; @@ -61,29 +59,23 @@ addrmap sha512_reg { /* ---- SHA512 Component Control ---- */ reg { - name = "SHA512 component control register type definition"; - desc = "One 5-bit register including the following flags: - bit #0: INIT : Trigs the SHA512 core to start the - processing for the first padded message block. - bit #1: NEXT: ​Trigs the SHA512 core to start the - processing for the remining padded message block. - bit #3-2: MODE : Indicates the SHA512 core to set dynamically - the type of hashing algorithm. This can be: - 00 for SHA512/224 - 01 for SHA512/256 - 10 for SHA384 - 11 for SHA512 - bit #4: Zeroize all internal registers after SHA process, to avoid SCA leakage. - This register is located at SHA512_base_address + 0x0000_0010 - After each software write, hardware will erase the register."; + name = "SHA512 CTRL"; + desc = "SHA512 component control register type definition"; default sw = w; default hw = r; default resetsignal = reset_b; - field {desc = "Control init command bit"; singlepulse;} INIT = 1'b0; - field {desc = "Control next command bit"; singlepulse;} NEXT = 1'b0; - field {desc = "Control mode command bits";} MODE[2] = 2'b10; - field {desc = "Zeroize all internal registers"; singlepulse;} ZEROIZE = 1'b0; + field {desc = "Control init command bit: Trigs the SHA512 core to start the + processing for the first padded message block."; singlepulse;} INIT = 1'b0; + field {desc = "Control next command bit: Trigs the SHA512 core to start the + processing for the remining padded message block."; singlepulse;} NEXT = 1'b0; + field {desc = "Control mode command bits: Indicates the SHA512 core to set dynamically + the type of hashing algorithm. This can be: + 00 for SHA512/224 + 01 for SHA512/256 + 10 for SHA384 + 11 for SHA512";} MODE[2] = 2'b10; + field {desc = "Zeroize all internal registers: Zeroize all internal registers after SHA process, to avoid SCA leakage."; singlepulse;} ZEROIZE = 1'b0; field {desc = "Indicates last iteration for keyvault or hash extend function. Result of this INIT or NEXT cycle will be written back to the appropriate vault"; hwclr;} LAST = 1'b0; @@ -91,28 +83,24 @@ addrmap sha512_reg { /* ---- SHA512 Component Status ---- */ reg { - name = "SHA512 component status register type definition"; - desc = "One 2-bit register including the following flags: - bit #0: READY : ​Indicates if the core is ready to take - a control command and process the block. - bit #1: Valid: ​Indicates if the process is done and the - hash value stored in DIGEST registers is valid. - This register is located at SHA512_base_address + 0x0000_0018."; + name = "SHA512 STATUS"; + desc = "SHA512 component status register type definition"; default sw = r; default hw = w; default resetsignal = reset_b; - field {desc = "Status ready bit";} READY = 1'b0; - field {desc = "Status valid bit";} VALID = 1'b0; + field {desc = "Status ready bit: ​Indicates if the core is ready to take + a control command and process the block.";} READY = 1'b0; + field {desc = "Status valid bit: Indicates if the process is done and the + hash value stored in DIGEST registers is valid.";} VALID = 1'b0; } SHA512_STATUS @0x00000018; /* ---- SHA512 Component Input Message Block ---- */ reg { - name = "SHA512 component block register type definition"; - desc = "32 32-bit registers storing the 1024-bit padded input. - These registers are located at SHA512_base_address + - 0x0000_0080 to 0x0000_00FC in big-endian representation."; + name = "SHA512 BLOCK"; + desc = "SHA512 component block register type definition + 32 32-bit registers storing the 1024-bit padded input."; default sw = w; default hw = rw; @@ -124,10 +112,9 @@ addrmap sha512_reg { /* ---- SHA512 Component Output Digest ---- */ reg { - name = "SHA512 component digest register type definition"; - desc = "16 32-bit registers storing the 512-bit digest output. - These registers are located at SHA512_base_address + - 0x0000_0100 to 0x0000_013C in big-endian representation."; + name = "SHA512 DIGEST"; + desc = "SHA512 component digest register type definition + 16 32-bit registers storing the 512-bit digest output."; default sw = r; default hw = w;