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webtalk_pn.xml
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webtalk_pn.xml
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<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Sun Dec 10 11:26:53 2017">
<section name="Project Information" visible="false">
<property name="ProjectID" value="91E51C176C894EC9A93076BD8E1D5D78" type="project"/>
<property name="ProjectIteration" value="196" type="project"/>
<property name="ProjectFile" value="D:/workspace/xilinx/cat_pad/cat_pad.xise" type="project"/>
<property name="ProjectCreationTimestamp" value="2017-11-17T14:22:53" type="project"/>
</section>
<section name="Project Statistics" visible="true">
<property name="PROPEXT_xilxSynthMaxFanout_virtex2" value="100000" type="process"/>
<property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
<property name="PROP_LastAppliedGoal" value="Timing Performance" type="design"/>
<property name="PROP_LastAppliedStrategy" value="Performance with IOB Packing;C:/Xilinx/14.7/ISE_DS/ISE/spartan3e/data/spartan3e_performance_with_iobpacking.xds" type="design"/>
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
<property name="PROP_SelectedInstanceHierarchicalPath" value="/test_basic_frame" type="process"/>
<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
<property name="PROP_SynthOptEffort" value="High" type="process"/>
<property name="PROP_SynthTopFile" value="changed" type="process"/>
<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
<property name="PROP_UseSmartGuide" value="false" type="design"/>
<property name="PROP_UserBrowsedStrategyFiles" value="C:/Xilinx/14.7/ISE_DS/ISE/data/default.xds" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="2017-11-17T14:22:53" type="design"/>
<property name="PROP_intWbtProjectID" value="91E51C176C894EC9A93076BD8E1D5D78" type="design"/>
<property name="PROP_intWbtProjectIteration" value="196" type="process"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_lockPinsUcfFile" value="changed" type="process"/>
<property name="PROP_selectedSimRootSourceNode_behav" value="work.test_basic_frame" type="process"/>
<property name="PROP_xilxBitgStart_IntDone" value="true" type="process"/>
<property name="PROP_xilxMapPackRegInto" value="For Inputs and Outputs" type="process"/>
<property name="PROP_xilxMapTimingDrivenPacking" value="true" type="process"/>
<property name="PROP_xilxPARplacerEffortLevel" value="High" type="process"/>
<property name="PROP_xilxPARrouterEffortLevel" value="High" type="process"/>
<property name="PROP_xilxSynthRegBalancing" value="Yes" type="process"/>
<property name="PROP_xstPackIORegister" value="Yes" type="process"/>
<property name="PROP_AutoTop" value="true" type="design"/>
<property name="PROP_DevFamily" value="Spartan3E" type="design"/>
<property name="PROP_DevDevice" value="xc3s1200e" type="design"/>
<property name="PROP_DevFamilyPMName" value="spartan3e" type="design"/>
<property name="PROP_MapExtraEffort" value="Normal" type="process"/>
<property name="PROP_xilxPARextraEffortLevel" value="Normal" type="process"/>
<property name="PROP_DevPackage" value="fg320" type="design"/>
<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
<property name="PROP_DevSpeed" value="-4" type="design"/>
<property name="PROP_PreferredLanguage" value="VHDL" type="design"/>
<property name="FILE_UCF" value="1" type="source"/>
<property name="FILE_VHDL" value="36" type="source"/>
</section>
</application>
</document>