From c3146a20b183c6634b57fc3aa7a085dab6ec924a Mon Sep 17 00:00:00 2001 From: Rusiru Induwara <150885221+induwara23630@users.noreply.github.com> Date: Wed, 1 Jan 2025 12:52:30 +0530 Subject: [PATCH 1/2] corrected ins mem --- ALUunit/ALU.v | 2 +- InstructionMemory/instructionmem.v | 17 +- RegisterFile/regtest.vvp | 308 +++++++++++++++++++++-------- RegisterFile/wave.vcd | 11 +- 4 files changed, 235 insertions(+), 103 deletions(-) diff --git a/ALUunit/ALU.v b/ALUunit/ALU.v index 081ff3f..c0955dd 100644 --- a/ALUunit/ALU.v +++ b/ALUunit/ALU.v @@ -21,7 +21,7 @@ module alu (data1,data2,ALU_OPCODE,Output); always @(*) begin - case (opcode) + case (ALU_OPCODE) 5'b00000:#2 Output = data1+data2; //ADD instruction 5'b00001:#2 Output = data1-data2; //SUB instruction 5'b00010:#1 Output = data1|data2; //OR instruction diff --git a/InstructionMemory/instructionmem.v b/InstructionMemory/instructionmem.v index 5f4226d..21adf4f 100644 --- a/InstructionMemory/instructionmem.v +++ b/InstructionMemory/instructionmem.v @@ -1,8 +1,8 @@ module instruction_memory(CLK,READ,ADDRESS,READINST,BUSYWAIT); input CLK; input READ; -input[5:0] ADDRESS; -output reg [127:0] READINST; +input[31:0] ADDRESS; +output reg [31:0] READINST; output reg BUSYWAIT; @@ -15,6 +15,7 @@ initial begin BUSYWAIT = 0; + //Hardcoded instructions {memory_array[10'd3], memory_array[10'd2], memory_array[10'd1], memory_array[10'd0]} = 32'b00000000000001000000000000011001; // loadi 4 #25 @@ -40,18 +41,6 @@ begin READINST[15:8] = #40 memory_array[{ADDRESS,4'b0001}]; READINST[23:16] = #40 memory_array[{ADDRESS,4'b0010}]; READINST[31:24] = #40 memory_array[{ADDRESS,4'b0011}]; - READINST[39:32] = #40 memory_array[{ADDRESS,4'b0100}]; - READINST[47:40] = #40 memory_array[{ADDRESS,4'b0101}]; - READINST[55:48] = #40 memory_array[{ADDRESS,4'b0110}]; - READINST[63:56] = #40 memory_array[{ADDRESS,4'b0111}]; - READINST[71:64] = #40 memory_array[{ADDRESS,4'b1000}]; - READINST[79:72] = #40 memory_array[{ADDRESS,4'b1001}]; - READINST[87:80] = #40 memory_array[{ADDRESS,4'b1010}]; - READINST[95:88] = #40 memory_array[{ADDRESS,4'b1011}]; - READINST[103:96] = #40 memory_array[{ADDRESS,4'b1100}]; - READINST[111:104] = #40 memory_array[{ADDRESS,4'b1101}]; - READINST[119:112] = #40 memory_array[{ADDRESS,4'b1110}]; - READINST[127:120] = #40 memory_array[{ADDRESS,4'b1111}]; BUSYWAIT = 0; end end diff --git a/RegisterFile/regtest.vvp b/RegisterFile/regtest.vvp index c6b8ae6..1fa7ccc 100644 --- a/RegisterFile/regtest.vvp +++ b/RegisterFile/regtest.vvp @@ -7,18 +7,18 @@ :vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi"; :vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi"; :vpi_module "C:\iverilog\lib\ivl\va_math.vpi"; -S_000001ce2548e580 .scope module, "RegisterFile_tb" "RegisterFile_tb" 2 1; +S_0000015c7e0be550 .scope module, "RegisterFile_tb" "RegisterFile_tb" 2 2; .timescale 0 0; -v000001ce253346c0_0 .var "CLK", 0 0; -v000001ce253348a0_0 .net "DATA1", 31 0, v000001ce254869f0_0; 1 drivers -v000001ce25333d60_0 .net "DATA2", 31 0, v000001ce2548e940_0; 1 drivers -v000001ce253341c0_0 .var "RESET", 0 0; -v000001ce25334580_0 .var "RS1", 4 0; -v000001ce25334120_0 .var "RS2", 4 0; -v000001ce25333cc0_0 .var "WRITEADDRESS", 4 0; -v000001ce25334620_0 .var "WRITEDATA", 31 0; -v000001ce25334760_0 .var "WRITEENABLE", 0 0; -S_000001ce2548e710 .scope module, "uut" "RegisterFile" 2 8, 2 57 0, S_000001ce2548e580; +v0000015c7e161490_0 .var "CLK", 0 0; +v0000015c7e1023f0_0 .net "DATA1", 31 0, v0000015c7e0d3120_0; 1 drivers +v0000015c7e101f90_0 .net "DATA2", 31 0, v0000015c7e0be910_0; 1 drivers +v0000015c7e1025d0_0 .var "RESET", 0 0; +v0000015c7e102990_0 .var "RS1", 4 0; +v0000015c7e102170_0 .var "RS2", 4 0; +v0000015c7e102030_0 .var "WRITEADDRESS", 4 0; +v0000015c7e102c10_0 .var "WRITEDATA", 31 0; +v0000015c7e1020d0_0 .var "WRITEENABLE", 0 0; +S_0000015c7e0be6e0 .scope module, "uut" "RegisterFile" 2 9, 2 56 0, S_0000015c7e0be550; .timescale 0 0; .port_info 0 /INPUT 5 "RS1"; .port_info 1 /INPUT 5 "RS2"; @@ -29,129 +29,275 @@ S_000001ce2548e710 .scope module, "uut" "RegisterFile" 2 8, 2 57 0, S_000001ce25 .port_info 6 /INPUT 1 "CLK"; .port_info 7 /OUTPUT 32 "DATA1"; .port_info 8 /OUTPUT 32 "DATA2"; -v000001ce2548e8a0_0 .net "CLK", 0 0, v000001ce253346c0_0; 1 drivers -v000001ce254869f0_0 .var "DATA1", 31 0; -v000001ce2548e940_0 .var "DATA2", 31 0; -v000001ce253336d0_0 .net "RESET", 0 0, v000001ce253341c0_0; 1 drivers -v000001ce25333770_0 .net "RS1", 4 0, v000001ce25334580_0; 1 drivers -v000001ce25333810_0 .net "RS2", 4 0, v000001ce25334120_0; 1 drivers -v000001ce253338b0_0 .net "WRITEADDRESS", 4 0, v000001ce25333cc0_0; 1 drivers -v000001ce25333950_0 .net "WRITEDATA", 31 0, v000001ce25334620_0; 1 drivers -v000001ce253339f0_0 .net "WRITEENABLE", 0 0, v000001ce25334760_0; 1 drivers -v000001ce25333a90_0 .var/i "i", 31 0; -v000001ce25333b30 .array "registers", 31 0, 31 0; -E_000001ce2532b040 .event anyedge, v000001ce25333810_0, v000001ce25333770_0; -E_000001ce2532b8c0 .event posedge, v000001ce2548e8a0_0; - .scope S_000001ce2548e710; +v0000015c7e0be870_0 .net "CLK", 0 0, v0000015c7e161490_0; 1 drivers +v0000015c7e0d3120_0 .var "DATA1", 31 0; +v0000015c7e0be910_0 .var "DATA2", 31 0; +v0000015c7e161030_0 .net "RESET", 0 0, v0000015c7e1025d0_0; 1 drivers +v0000015c7e1610d0_0 .net "RS1", 4 0, v0000015c7e102990_0; 1 drivers +v0000015c7e161170_0 .net "RS2", 4 0, v0000015c7e102170_0; 1 drivers +v0000015c7e161210_0 .net "WRITEADDRESS", 4 0, v0000015c7e102030_0; 1 drivers +v0000015c7e1612b0_0 .net "WRITEDATA", 31 0, v0000015c7e102c10_0; 1 drivers +v0000015c7e161350_0 .net "WRITEENABLE", 0 0, v0000015c7e1020d0_0; 1 drivers +v0000015c7e1613f0 .array "registers", 31 0, 31 0; +E_0000015c7e0f8aa0 .event anyedge, v0000015c7e161170_0, v0000015c7e1610d0_0; +E_0000015c7e0f8de0 .event posedge, v0000015c7e0be870_0; + .scope S_0000015c7e0be6e0; T_0 ; - %wait E_000001ce2532b8c0; - %load/vec4 v000001ce253336d0_0; + %wait E_0000015c7e0f8de0; + %load/vec4 v0000015c7e161030_0; %flag_set/vec4 8; %jmp/0xz T_0.0, 8; %delay 1, 0; %pushi/vec4 0, 0, 32; - %store/vec4 v000001ce25333a90_0, 0, 32; -T_0.2 ; - %load/vec4 v000001ce25333a90_0; - %cmpi/s 32, 0, 32; - %jmp/0xz T_0.3, 5; - %pushi/vec4 0, 0, 32; - %ix/getv/s 3, v000001ce25333a90_0; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v000001ce25333b30, 0, 4; - ; show_stmt_assign_vector: Get l-value for compressed += operand - %load/vec4 v000001ce25333a90_0; - %pushi/vec4 1, 0, 32; - %add; - %store/vec4 v000001ce25333a90_0, 0, 32; - %jmp T_0.2; -T_0.3 ; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0000015c7e1613f0, 0, 4; + %pushi/vec4 0, 0, 32; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0000015c7e1613f0, 0, 4; + %pushi/vec4 0, 0, 32; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0000015c7e1613f0, 0, 4; + %pushi/vec4 0, 0, 32; + %ix/load 3, 4, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0000015c7e1613f0, 0, 4; + %pushi/vec4 0, 0, 32; + %ix/load 3, 5, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0000015c7e1613f0, 0, 4; + %pushi/vec4 0, 0, 32; + %ix/load 3, 6, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0000015c7e1613f0, 0, 4; + %pushi/vec4 0, 0, 32; + %ix/load 3, 7, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0000015c7e1613f0, 0, 4; + %pushi/vec4 0, 0, 32; + %ix/load 3, 8, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0000015c7e1613f0, 0, 4; + %pushi/vec4 0, 0, 32; + %ix/load 3, 9, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0000015c7e1613f0, 0, 4; + %pushi/vec4 0, 0, 32; + %ix/load 3, 10, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0000015c7e1613f0, 0, 4; + %pushi/vec4 0, 0, 32; + %ix/load 3, 11, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0000015c7e1613f0, 0, 4; + %pushi/vec4 0, 0, 32; + %ix/load 3, 12, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0000015c7e1613f0, 0, 4; + %pushi/vec4 0, 0, 32; + %ix/load 3, 13, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0000015c7e1613f0, 0, 4; + %pushi/vec4 0, 0, 32; + %ix/load 3, 14, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0000015c7e1613f0, 0, 4; + %pushi/vec4 0, 0, 32; + %ix/load 3, 15, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0000015c7e1613f0, 0, 4; + %pushi/vec4 0, 0, 32; + %ix/load 3, 16, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0000015c7e1613f0, 0, 4; + %pushi/vec4 0, 0, 32; + %ix/load 3, 17, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0000015c7e1613f0, 0, 4; + %pushi/vec4 0, 0, 32; + %ix/load 3, 18, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0000015c7e1613f0, 0, 4; + %pushi/vec4 0, 0, 32; + %ix/load 3, 19, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0000015c7e1613f0, 0, 4; + %pushi/vec4 0, 0, 32; + %ix/load 3, 20, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0000015c7e1613f0, 0, 4; + %pushi/vec4 0, 0, 32; + %ix/load 3, 21, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0000015c7e1613f0, 0, 4; + %pushi/vec4 0, 0, 32; + %ix/load 3, 22, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0000015c7e1613f0, 0, 4; + %pushi/vec4 0, 0, 32; + %ix/load 3, 23, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0000015c7e1613f0, 0, 4; + %pushi/vec4 0, 0, 32; + %ix/load 3, 24, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0000015c7e1613f0, 0, 4; + %pushi/vec4 0, 0, 32; + %ix/load 3, 25, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0000015c7e1613f0, 0, 4; + %pushi/vec4 0, 0, 32; + %ix/load 3, 26, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0000015c7e1613f0, 0, 4; + %pushi/vec4 0, 0, 32; + %ix/load 3, 27, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0000015c7e1613f0, 0, 4; + %pushi/vec4 0, 0, 32; + %ix/load 3, 28, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0000015c7e1613f0, 0, 4; + %pushi/vec4 0, 0, 32; + %ix/load 3, 29, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0000015c7e1613f0, 0, 4; + %pushi/vec4 0, 0, 32; + %ix/load 3, 30, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0000015c7e1613f0, 0, 4; + %pushi/vec4 0, 0, 32; + %ix/load 3, 31, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0000015c7e1613f0, 0, 4; %jmp T_0.1; T_0.0 ; - %load/vec4 v000001ce253339f0_0; + %load/vec4 v0000015c7e161350_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_0.4, 9; + %load/vec4 v0000015c7e161210_0; + %pushi/vec4 0, 0, 5; + %cmp/ne; + %flag_get/vec4 4; + %and; +T_0.4; %flag_set/vec4 8; - %jmp/0xz T_0.4, 8; + %jmp/0xz T_0.2, 8; %delay 1, 0; - %load/vec4 v000001ce25333950_0; - %load/vec4 v000001ce253338b0_0; + %load/vec4 v0000015c7e1612b0_0; + %load/vec4 v0000015c7e161210_0; %pad/u 7; %ix/vec4 3; %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v000001ce25333b30, 0, 4; -T_0.4 ; + %assign/vec4/a/d v0000015c7e1613f0, 0, 4; +T_0.2 ; T_0.1 ; %jmp T_0; .thread T_0; - .scope S_000001ce2548e710; + .scope S_0000015c7e0be6e0; T_1 ; - %wait E_000001ce2532b040; + %wait E_0000015c7e0f8aa0; %delay 2, 0; - %load/vec4 v000001ce25333770_0; + %load/vec4 v0000015c7e1610d0_0; %pad/u 7; %ix/vec4 4; - %load/vec4a v000001ce25333b30, 4; - %assign/vec4 v000001ce254869f0_0, 0; - %load/vec4 v000001ce25333810_0; + %load/vec4a v0000015c7e1613f0, 4; + %assign/vec4 v0000015c7e0d3120_0, 0; + %load/vec4 v0000015c7e161170_0; %pad/u 7; %ix/vec4 4; - %load/vec4a v000001ce25333b30, 4; - %assign/vec4 v000001ce2548e940_0, 0; + %load/vec4a v0000015c7e1613f0, 4; + %assign/vec4 v0000015c7e0be910_0, 0; %jmp T_1; .thread T_1, $push; - .scope S_000001ce2548e580; + .scope S_0000015c7e0be550; T_2 ; %pushi/vec4 0, 0, 1; - %store/vec4 v000001ce253346c0_0, 0, 1; + %store/vec4 v0000015c7e161490_0, 0, 1; %end; .thread T_2; - .scope S_000001ce2548e580; + .scope S_0000015c7e0be550; T_3 ; %delay 5, 0; - %load/vec4 v000001ce253346c0_0; + %load/vec4 v0000015c7e161490_0; %inv; - %store/vec4 v000001ce253346c0_0, 0, 1; + %store/vec4 v0000015c7e161490_0, 0, 1; %jmp T_3; .thread T_3; - .scope S_000001ce2548e580; + .scope S_0000015c7e0be550; T_4 ; - %vpi_call 2 20 "$dumpfile", "wave.vcd" {0 0 0}; - %vpi_call 2 21 "$dumpvars", 32'sb00000000000000000000000000000000, S_000001ce2548e580 {0 0 0}; + %vpi_call 2 21 "$dumpfile", "wave.vcd" {0 0 0}; + %vpi_call 2 22 "$dumpvars", 32'sb00000000000000000000000000000000, S_0000015c7e0be550 {0 0 0}; %pushi/vec4 1, 0, 1; - %store/vec4 v000001ce253341c0_0, 0, 1; + %store/vec4 v0000015c7e1025d0_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001ce25334760_0, 0, 1; + %store/vec4 v0000015c7e1020d0_0, 0, 1; %delay 10, 0; %pushi/vec4 0, 0, 1; - %store/vec4 v000001ce253341c0_0, 0, 1; + %store/vec4 v0000015c7e1025d0_0, 0, 1; %pushi/vec4 1, 0, 5; - %store/vec4 v000001ce25333cc0_0, 0, 5; + %store/vec4 v0000015c7e102030_0, 0, 5; %pushi/vec4 2779096485, 0, 32; - %store/vec4 v000001ce25334620_0, 0, 32; + %store/vec4 v0000015c7e102c10_0, 0, 32; %pushi/vec4 1, 0, 1; - %store/vec4 v000001ce25334760_0, 0, 1; + %store/vec4 v0000015c7e1020d0_0, 0, 1; %delay 10, 0; %pushi/vec4 0, 0, 1; - %store/vec4 v000001ce25334760_0, 0, 1; + %store/vec4 v0000015c7e1020d0_0, 0, 1; %pushi/vec4 1, 0, 5; - %store/vec4 v000001ce25334580_0, 0, 5; + %store/vec4 v0000015c7e102990_0, 0, 5; %pushi/vec4 0, 0, 5; - %store/vec4 v000001ce25334120_0, 0, 5; + %store/vec4 v0000015c7e102170_0, 0, 5; %delay 10, 0; %pushi/vec4 2, 0, 5; - %store/vec4 v000001ce25333cc0_0, 0, 5; + %store/vec4 v0000015c7e102030_0, 0, 5; %pushi/vec4 1515870810, 0, 32; - %store/vec4 v000001ce25334620_0, 0, 32; + %store/vec4 v0000015c7e102c10_0, 0, 32; %pushi/vec4 1, 0, 1; - %store/vec4 v000001ce25334760_0, 0, 1; + %store/vec4 v0000015c7e1020d0_0, 0, 1; %delay 10, 0; %pushi/vec4 0, 0, 1; - %store/vec4 v000001ce25334760_0, 0, 1; + %store/vec4 v0000015c7e1020d0_0, 0, 1; %pushi/vec4 1, 0, 5; - %store/vec4 v000001ce25334580_0, 0, 5; + %store/vec4 v0000015c7e102990_0, 0, 5; %pushi/vec4 2, 0, 5; - %store/vec4 v000001ce25334120_0, 0, 5; + %store/vec4 v0000015c7e102170_0, 0, 5; %delay 10, 0; - %vpi_call 2 50 "$finish" {0 0 0}; + %vpi_call 2 51 "$finish" {0 0 0}; %end; .thread T_4; # The file index is used to find the file name in the following table. diff --git a/RegisterFile/wave.vcd b/RegisterFile/wave.vcd index 3047ab8..4da31a1 100644 --- a/RegisterFile/wave.vcd +++ b/RegisterFile/wave.vcd @@ -1,5 +1,5 @@ $date - Thu Dec 12 22:12:44 2024 + Mon Dec 30 14:31:27 2024 $end $version Icarus Verilog @@ -27,13 +27,14 @@ $var wire 32 - WRITEDATA [31:0] $end $var wire 1 ) WRITEENABLE $end $var reg 32 . DATA1 [31:0] $end $var reg 32 / DATA2 [31:0] $end -$var integer 32 0 i [31:0] $end $upscope $end $upscope $end $enddefinitions $end +$comment Show the parameter values. $end +$dumpall +$end #0 $dumpvars -bx 0 bx / bx . bx - @@ -52,8 +53,6 @@ bx ! $end #5 1# -#6 -b100000 0 #10 0# 1) @@ -72,8 +71,6 @@ b1 % b1 * 0) #22 -b0 ! -b0 / b10100101101001011010010110100101 " b10100101101001011010010110100101 . #25 From 01afa58b5c1c9aacb05fb41f287c276c9843fe4b Mon Sep 17 00:00:00 2001 From: Rusiru Induwara <150885221+induwara23630@users.noreply.github.com> Date: Thu, 2 Jan 2025 09:01:31 +0530 Subject: [PATCH 2/2] corrected dmem --- Data Memory/datamem.v | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/Data Memory/datamem.v b/Data Memory/datamem.v index ad16c10..a845896 100644 --- a/Data Memory/datamem.v +++ b/Data Memory/datamem.v @@ -1,7 +1,8 @@ -module data_memory(CLK,RESET,READ,WRITE,ADDRESS,WRITEDATA,READDATA,BUSYWAIT); +module data_memory(CLK,RESET,READ,FUNCT3,WRITE,ADDRESS,WRITEDATA,READDATA,BUSYWAIT); input CLK; input RESET; input READ; +input [2:0] FUNCT3; input WRITE; input[31:0] ADDRESS; input[31:0] WRITEDATA; @@ -29,10 +30,24 @@ begin end if(WRITE) begin - memory_array[ADDRESS] <=#40 WRITEDATA[7:0]; - memory_array[ADDRESS+1] <=#40 WRITEDATA[15:8]; - memory_array[ADDRESS+2] <=#40 WRITEDATA[23:16]; - memory_array[ADDRESS+3] <=#40 WRITEDATA[31:24]; + case(FUNCT3) + 3'b000: //SB + begin + memory_array[ADDRESS] <=#40 WRITEDATA[7:0]; + end + 3'b001: //SH + begin + memory_array[ADDRESS] <=#40 WRITEDATA[7:0]; + memory_array[ADDRESS+1] <=#40 WRITEDATA[15:8]; + end + 3'b010: //SW + begin + memory_array[ADDRESS] <=#40 WRITEDATA[7:0]; + memory_array[ADDRESS+1] <=#40 WRITEDATA[15:8]; + memory_array[ADDRESS+2] <=#40 WRITEDATA[23:16]; + memory_array[ADDRESS+3] <=#40 WRITEDATA[31:24]; + end + endcase end end