diff --git a/Data Memory/datamem.v b/Data Memory/datamem.v
index ad16c10..a845896 100644
--- a/Data Memory/datamem.v	
+++ b/Data Memory/datamem.v	
@@ -1,7 +1,8 @@
-module data_memory(CLK,RESET,READ,WRITE,ADDRESS,WRITEDATA,READDATA,BUSYWAIT);
+module data_memory(CLK,RESET,READ,FUNCT3,WRITE,ADDRESS,WRITEDATA,READDATA,BUSYWAIT);
 input           CLK;
 input           RESET;
 input           READ;
+input [2:0]     FUNCT3;
 input           WRITE;
 input[31:0]      ADDRESS;
 input[31:0]      WRITEDATA;
@@ -29,10 +30,24 @@ begin
     end
     if(WRITE)
 	begin
-        memory_array[ADDRESS]   <=#40 WRITEDATA[7:0];    
-        memory_array[ADDRESS+1] <=#40 WRITEDATA[15:8];   
-        memory_array[ADDRESS+2] <=#40 WRITEDATA[23:16]; 
-        memory_array[ADDRESS+3] <=#40 WRITEDATA[31:24];  
+        case(FUNCT3)
+        3'b000: //SB
+        begin
+            memory_array[ADDRESS] <=#40 WRITEDATA[7:0];
+        end
+        3'b001: //SH
+        begin
+            memory_array[ADDRESS]   <=#40 WRITEDATA[7:0];    
+            memory_array[ADDRESS+1] <=#40 WRITEDATA[15:8];   
+        end
+        3'b010: //SW
+        begin
+            memory_array[ADDRESS]   <=#40 WRITEDATA[7:0];    
+            memory_array[ADDRESS+1] <=#40 WRITEDATA[15:8];   
+            memory_array[ADDRESS+2] <=#40 WRITEDATA[23:16]; 
+            memory_array[ADDRESS+3] <=#40 WRITEDATA[31:24];  
+        end
+        endcase
     end
 end
 
diff --git a/InstructionMemory/instructionmem.v b/InstructionMemory/instructionmem.v
index 6e48358..59db29e 100644
--- a/InstructionMemory/instructionmem.v
+++ b/InstructionMemory/instructionmem.v
@@ -1,4 +1,5 @@
 
+
 // module instruction_memory(CLK,READ,ADDRESS,READINST,BUSYWAIT);
 // input				CLK;
 // input				READ;
@@ -8,6 +9,7 @@
 
 
 
+
 // //Declare memory array 1024x8-bits 
 // reg [7:0] memory_array [1023:0];
 
@@ -16,7 +18,9 @@
 // begin
 // 	BUSYWAIT = 0;
 	
-//   //Hardcoded instructions
+
+  //Hardcoded instructions
+
   
 //    {memory_array[10'd3],  memory_array[10'd2],  memory_array[10'd1],  memory_array[10'd0]}  = 32'b00000000000001000000000000011001; // loadi 4 #25
 //    {memory_array[10'd7],  memory_array[10'd6],  memory_array[10'd5],  memory_array[10'd4]}  = 32'b00000000000001010000000000100011; // loadi 5 #35
@@ -79,6 +83,7 @@ initial begin
     // Add more instructions as needed
 end
 
+
 // Fetch instruction based on PC
 always @(posedge CLK or posedge RESET) begin
     #1
@@ -87,6 +92,7 @@ always @(posedge CLK or posedge RESET) begin
     end else begin
         INSTRUCTION <= memory_array[PC[9:2]]; // Fetch instruction (PC[9:2] to align with 32-bit words)
     end
+
 end
 
 endmodule
diff --git a/RegisterFile/regtest.vvp b/RegisterFile/regtest.vvp
index 07f192a..e69de29 100644
--- a/RegisterFile/regtest.vvp
+++ b/RegisterFile/regtest.vvp
@@ -1,307 +0,0 @@
-#! /c/Source/iverilog-install/bin/vvp
-:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
-:ivl_delay_selection "TYPICAL";
-:vpi_time_precision + 0;
-:vpi_module "C:\iverilog\lib\ivl\system.vpi";
-:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
-:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
-:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
-:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
-S_00000226ad58ab20 .scope module, "RegisterFile_tb" "RegisterFile_tb" 2 62;
- .timescale 0 0;
-v00000226ad5e0440_0 .var "CLK", 0 0;
-v00000226ad5827b0_0 .net "DATA1", 31 0, v00000226ad6c67c0_0;  1 drivers
-v00000226ad582670_0 .net "DATA2", 31 0, v00000226ad58aee0_0;  1 drivers
-v00000226ad582710_0 .var "RESET", 0 0;
-v00000226ad581d10_0 .var "RS1", 4 0;
-v00000226ad582990_0 .var "RS2", 4 0;
-v00000226ad582030_0 .var "WRITEADDRESS", 4 0;
-v00000226ad582350_0 .var "WRITEDATA", 31 0;
-v00000226ad582530_0 .var "WRITEENABLE", 0 0;
-S_00000226ad58acb0 .scope module, "uut" "RegisterFile" 2 69, 2 1 0, S_00000226ad58ab20;
- .timescale 0 0;
-    .port_info 0 /INPUT 5 "RS1";
-    .port_info 1 /INPUT 5 "RS2";
-    .port_info 2 /INPUT 32 "WRITEDATA";
-    .port_info 3 /INPUT 5 "WRITEADDRESS";
-    .port_info 4 /INPUT 1 "WRITEENABLE";
-    .port_info 5 /INPUT 1 "RESET";
-    .port_info 6 /INPUT 1 "CLK";
-    .port_info 7 /OUTPUT 32 "DATA1";
-    .port_info 8 /OUTPUT 32 "DATA2";
-v00000226ad58ae40_0 .net "CLK", 0 0, v00000226ad5e0440_0;  1 drivers
-v00000226ad6c67c0_0 .var "DATA1", 31 0;
-v00000226ad58aee0_0 .var "DATA2", 31 0;
-v00000226ad5dffe0_0 .net "RESET", 0 0, v00000226ad582710_0;  1 drivers
-v00000226ad5e0080_0 .net "RS1", 4 0, v00000226ad581d10_0;  1 drivers
-v00000226ad5e0120_0 .net "RS2", 4 0, v00000226ad582990_0;  1 drivers
-v00000226ad5e01c0_0 .net "WRITEADDRESS", 4 0, v00000226ad582030_0;  1 drivers
-v00000226ad5e0260_0 .net "WRITEDATA", 31 0, v00000226ad582350_0;  1 drivers
-v00000226ad5e0300_0 .net "WRITEENABLE", 0 0, v00000226ad582530_0;  1 drivers
-v00000226ad5e03a0 .array "registers", 31 0, 31 0;
-E_00000226ad579e00 .event anyedge, v00000226ad5e0120_0, v00000226ad5e0080_0;
-E_00000226ad579b00 .event posedge, v00000226ad58ae40_0;
-    .scope S_00000226ad58acb0;
-T_0 ;
-    %wait E_00000226ad579b00;
-    %load/vec4 v00000226ad5dffe0_0;
-    %flag_set/vec4 8;
-    %jmp/0xz  T_0.0, 8;
-    %delay 1, 0;
-    %pushi/vec4 0, 0, 32;
-    %ix/load 3, 1, 0;
-    %flag_set/imm 4, 0;
-    %ix/load 4, 0, 0; Constant delay
-    %assign/vec4/a/d v00000226ad5e03a0, 0, 4;
-    %pushi/vec4 0, 0, 32;
-    %ix/load 3, 2, 0;
-    %flag_set/imm 4, 0;
-    %ix/load 4, 0, 0; Constant delay
-    %assign/vec4/a/d v00000226ad5e03a0, 0, 4;
-    %pushi/vec4 0, 0, 32;
-    %ix/load 3, 3, 0;
-    %flag_set/imm 4, 0;
-    %ix/load 4, 0, 0; Constant delay
-    %assign/vec4/a/d v00000226ad5e03a0, 0, 4;
-    %pushi/vec4 0, 0, 32;
-    %ix/load 3, 4, 0;
-    %flag_set/imm 4, 0;
-    %ix/load 4, 0, 0; Constant delay
-    %assign/vec4/a/d v00000226ad5e03a0, 0, 4;
-    %pushi/vec4 0, 0, 32;
-    %ix/load 3, 5, 0;
-    %flag_set/imm 4, 0;
-    %ix/load 4, 0, 0; Constant delay
-    %assign/vec4/a/d v00000226ad5e03a0, 0, 4;
-    %pushi/vec4 0, 0, 32;
-    %ix/load 3, 6, 0;
-    %flag_set/imm 4, 0;
-    %ix/load 4, 0, 0; Constant delay
-    %assign/vec4/a/d v00000226ad5e03a0, 0, 4;
-    %pushi/vec4 0, 0, 32;
-    %ix/load 3, 7, 0;
-    %flag_set/imm 4, 0;
-    %ix/load 4, 0, 0; Constant delay
-    %assign/vec4/a/d v00000226ad5e03a0, 0, 4;
-    %pushi/vec4 0, 0, 32;
-    %ix/load 3, 8, 0;
-    %flag_set/imm 4, 0;
-    %ix/load 4, 0, 0; Constant delay
-    %assign/vec4/a/d v00000226ad5e03a0, 0, 4;
-    %pushi/vec4 0, 0, 32;
-    %ix/load 3, 9, 0;
-    %flag_set/imm 4, 0;
-    %ix/load 4, 0, 0; Constant delay
-    %assign/vec4/a/d v00000226ad5e03a0, 0, 4;
-    %pushi/vec4 0, 0, 32;
-    %ix/load 3, 10, 0;
-    %flag_set/imm 4, 0;
-    %ix/load 4, 0, 0; Constant delay
-    %assign/vec4/a/d v00000226ad5e03a0, 0, 4;
-    %pushi/vec4 0, 0, 32;
-    %ix/load 3, 11, 0;
-    %flag_set/imm 4, 0;
-    %ix/load 4, 0, 0; Constant delay
-    %assign/vec4/a/d v00000226ad5e03a0, 0, 4;
-    %pushi/vec4 0, 0, 32;
-    %ix/load 3, 12, 0;
-    %flag_set/imm 4, 0;
-    %ix/load 4, 0, 0; Constant delay
-    %assign/vec4/a/d v00000226ad5e03a0, 0, 4;
-    %pushi/vec4 0, 0, 32;
-    %ix/load 3, 13, 0;
-    %flag_set/imm 4, 0;
-    %ix/load 4, 0, 0; Constant delay
-    %assign/vec4/a/d v00000226ad5e03a0, 0, 4;
-    %pushi/vec4 0, 0, 32;
-    %ix/load 3, 14, 0;
-    %flag_set/imm 4, 0;
-    %ix/load 4, 0, 0; Constant delay
-    %assign/vec4/a/d v00000226ad5e03a0, 0, 4;
-    %pushi/vec4 0, 0, 32;
-    %ix/load 3, 15, 0;
-    %flag_set/imm 4, 0;
-    %ix/load 4, 0, 0; Constant delay
-    %assign/vec4/a/d v00000226ad5e03a0, 0, 4;
-    %pushi/vec4 0, 0, 32;
-    %ix/load 3, 16, 0;
-    %flag_set/imm 4, 0;
-    %ix/load 4, 0, 0; Constant delay
-    %assign/vec4/a/d v00000226ad5e03a0, 0, 4;
-    %pushi/vec4 0, 0, 32;
-    %ix/load 3, 17, 0;
-    %flag_set/imm 4, 0;
-    %ix/load 4, 0, 0; Constant delay
-    %assign/vec4/a/d v00000226ad5e03a0, 0, 4;
-    %pushi/vec4 0, 0, 32;
-    %ix/load 3, 18, 0;
-    %flag_set/imm 4, 0;
-    %ix/load 4, 0, 0; Constant delay
-    %assign/vec4/a/d v00000226ad5e03a0, 0, 4;
-    %pushi/vec4 0, 0, 32;
-    %ix/load 3, 19, 0;
-    %flag_set/imm 4, 0;
-    %ix/load 4, 0, 0; Constant delay
-    %assign/vec4/a/d v00000226ad5e03a0, 0, 4;
-    %pushi/vec4 0, 0, 32;
-    %ix/load 3, 20, 0;
-    %flag_set/imm 4, 0;
-    %ix/load 4, 0, 0; Constant delay
-    %assign/vec4/a/d v00000226ad5e03a0, 0, 4;
-    %pushi/vec4 0, 0, 32;
-    %ix/load 3, 21, 0;
-    %flag_set/imm 4, 0;
-    %ix/load 4, 0, 0; Constant delay
-    %assign/vec4/a/d v00000226ad5e03a0, 0, 4;
-    %pushi/vec4 0, 0, 32;
-    %ix/load 3, 22, 0;
-    %flag_set/imm 4, 0;
-    %ix/load 4, 0, 0; Constant delay
-    %assign/vec4/a/d v00000226ad5e03a0, 0, 4;
-    %pushi/vec4 0, 0, 32;
-    %ix/load 3, 23, 0;
-    %flag_set/imm 4, 0;
-    %ix/load 4, 0, 0; Constant delay
-    %assign/vec4/a/d v00000226ad5e03a0, 0, 4;
-    %pushi/vec4 0, 0, 32;
-    %ix/load 3, 24, 0;
-    %flag_set/imm 4, 0;
-    %ix/load 4, 0, 0; Constant delay
-    %assign/vec4/a/d v00000226ad5e03a0, 0, 4;
-    %pushi/vec4 0, 0, 32;
-    %ix/load 3, 25, 0;
-    %flag_set/imm 4, 0;
-    %ix/load 4, 0, 0; Constant delay
-    %assign/vec4/a/d v00000226ad5e03a0, 0, 4;
-    %pushi/vec4 0, 0, 32;
-    %ix/load 3, 26, 0;
-    %flag_set/imm 4, 0;
-    %ix/load 4, 0, 0; Constant delay
-    %assign/vec4/a/d v00000226ad5e03a0, 0, 4;
-    %pushi/vec4 0, 0, 32;
-    %ix/load 3, 27, 0;
-    %flag_set/imm 4, 0;
-    %ix/load 4, 0, 0; Constant delay
-    %assign/vec4/a/d v00000226ad5e03a0, 0, 4;
-    %pushi/vec4 0, 0, 32;
-    %ix/load 3, 28, 0;
-    %flag_set/imm 4, 0;
-    %ix/load 4, 0, 0; Constant delay
-    %assign/vec4/a/d v00000226ad5e03a0, 0, 4;
-    %pushi/vec4 0, 0, 32;
-    %ix/load 3, 29, 0;
-    %flag_set/imm 4, 0;
-    %ix/load 4, 0, 0; Constant delay
-    %assign/vec4/a/d v00000226ad5e03a0, 0, 4;
-    %pushi/vec4 0, 0, 32;
-    %ix/load 3, 30, 0;
-    %flag_set/imm 4, 0;
-    %ix/load 4, 0, 0; Constant delay
-    %assign/vec4/a/d v00000226ad5e03a0, 0, 4;
-    %pushi/vec4 0, 0, 32;
-    %ix/load 3, 31, 0;
-    %flag_set/imm 4, 0;
-    %ix/load 4, 0, 0; Constant delay
-    %assign/vec4/a/d v00000226ad5e03a0, 0, 4;
-    %jmp T_0.1;
-T_0.0 ;
-    %load/vec4 v00000226ad5e0300_0;
-    %flag_set/vec4 9;
-    %flag_get/vec4 9;
-    %jmp/0 T_0.4, 9;
-    %load/vec4 v00000226ad5e01c0_0;
-    %pushi/vec4 0, 0, 5;
-    %cmp/ne;
-    %flag_get/vec4 4;
-    %and;
-T_0.4;
-    %flag_set/vec4 8;
-    %jmp/0xz  T_0.2, 8;
-    %delay 1, 0;
-    %load/vec4 v00000226ad5e0260_0;
-    %load/vec4 v00000226ad5e01c0_0;
-    %pad/u 7;
-    %ix/vec4 3;
-    %ix/load 4, 0, 0; Constant delay
-    %assign/vec4/a/d v00000226ad5e03a0, 0, 4;
-T_0.2 ;
-T_0.1 ;
-    %jmp T_0;
-    .thread T_0;
-    .scope S_00000226ad58acb0;
-T_1 ;
-    %wait E_00000226ad579e00;
-    %delay 2, 0;
-    %load/vec4 v00000226ad5e0080_0;
-    %pad/u 7;
-    %ix/vec4 4;
-    %load/vec4a v00000226ad5e03a0, 4;
-    %assign/vec4 v00000226ad6c67c0_0, 0;
-    %load/vec4 v00000226ad5e0120_0;
-    %pad/u 7;
-    %ix/vec4 4;
-    %load/vec4a v00000226ad5e03a0, 4;
-    %assign/vec4 v00000226ad58aee0_0, 0;
-    %jmp T_1;
-    .thread T_1, $push;
-    .scope S_00000226ad58ab20;
-T_2 ;
-    %pushi/vec4 0, 0, 1;
-    %store/vec4 v00000226ad5e0440_0, 0, 1;
-    %end;
-    .thread T_2;
-    .scope S_00000226ad58ab20;
-T_3 ;
-    %delay 5, 0;
-    %load/vec4 v00000226ad5e0440_0;
-    %inv;
-    %store/vec4 v00000226ad5e0440_0, 0, 1;
-    %jmp T_3;
-    .thread T_3;
-    .scope S_00000226ad58ab20;
-T_4 ;
-    %vpi_call 2 81 "$dumpfile", "wave.vcd" {0 0 0};
-    %vpi_call 2 82 "$dumpvars", 32'sb00000000000000000000000000000000, S_00000226ad58ab20 {0 0 0};
-    %pushi/vec4 1, 0, 1;
-    %store/vec4 v00000226ad582710_0, 0, 1;
-    %pushi/vec4 0, 0, 1;
-    %store/vec4 v00000226ad582530_0, 0, 1;
-    %delay 10, 0;
-    %pushi/vec4 0, 0, 1;
-    %store/vec4 v00000226ad582710_0, 0, 1;
-    %pushi/vec4 1, 0, 5;
-    %store/vec4 v00000226ad582030_0, 0, 5;
-    %pushi/vec4 2779096485, 0, 32;
-    %store/vec4 v00000226ad582350_0, 0, 32;
-    %pushi/vec4 1, 0, 1;
-    %store/vec4 v00000226ad582530_0, 0, 1;
-    %delay 10, 0;
-    %pushi/vec4 0, 0, 1;
-    %store/vec4 v00000226ad582530_0, 0, 1;
-    %pushi/vec4 1, 0, 5;
-    %store/vec4 v00000226ad581d10_0, 0, 5;
-    %pushi/vec4 0, 0, 5;
-    %store/vec4 v00000226ad582990_0, 0, 5;
-    %delay 10, 0;
-    %pushi/vec4 2, 0, 5;
-    %store/vec4 v00000226ad582030_0, 0, 5;
-    %pushi/vec4 1515870810, 0, 32;
-    %store/vec4 v00000226ad582350_0, 0, 32;
-    %pushi/vec4 1, 0, 1;
-    %store/vec4 v00000226ad582530_0, 0, 1;
-    %delay 10, 0;
-    %pushi/vec4 0, 0, 1;
-    %store/vec4 v00000226ad582530_0, 0, 1;
-    %pushi/vec4 1, 0, 5;
-    %store/vec4 v00000226ad581d10_0, 0, 5;
-    %pushi/vec4 2, 0, 5;
-    %store/vec4 v00000226ad582990_0, 0, 5;
-    %delay 10, 0;
-    %vpi_call 2 111 "$finish" {0 0 0};
-    %end;
-    .thread T_4;
-# The file index is used to find the file name in the following table.
-:file_names 3;
-    "N/A";
-    "<interactive>";
-    "registerfile.v";
diff --git a/RegisterFile/wave.vcd b/RegisterFile/wave.vcd
index 3047ab8..4da31a1 100644
--- a/RegisterFile/wave.vcd
+++ b/RegisterFile/wave.vcd
@@ -1,5 +1,5 @@
 $date
-	Thu Dec 12 22:12:44 2024
+	Mon Dec 30 14:31:27 2024
 $end
 $version
 	Icarus Verilog
@@ -27,13 +27,14 @@ $var wire 32 - WRITEDATA [31:0] $end
 $var wire 1 ) WRITEENABLE $end
 $var reg 32 . DATA1 [31:0] $end
 $var reg 32 / DATA2 [31:0] $end
-$var integer 32 0 i [31:0] $end
 $upscope $end
 $upscope $end
 $enddefinitions $end
+$comment Show the parameter values. $end
+$dumpall
+$end
 #0
 $dumpvars
-bx 0
 bx /
 bx .
 bx -
@@ -52,8 +53,6 @@ bx !
 $end
 #5
 1#
-#6
-b100000 0
 #10
 0#
 1)
@@ -72,8 +71,6 @@ b1 %
 b1 *
 0)
 #22
-b0 !
-b0 /
 b10100101101001011010010110100101 "
 b10100101101001011010010110100101 .
 #25