diff --git a/CPU/CPU.v b/CPU/CPU.v index 629aa00..b8240fc 100644 --- a/CPU/CPU.v +++ b/CPU/CPU.v @@ -72,7 +72,7 @@ module CPU (CLK, RESET); // instruction decode stage controlUnit controlunit1(INSTRUCTION_OUT, WRITEENABLE, MEMORYACCESS, MEMWRITE, MEMREAD, JUMPANDLINK, ALU_OPCODE, IMMEDIATESELECT, OFFSETGENARATOR, BRANCH, JUMP, IMMEDIATE_TYPE); - RegisterFile registerfile1(RS1,RS2,WRITEDATA,WRITEADDRESS_IDOUT,WRITEENABLE_MEMOUT,RESET,CLK,DATA1,DATA2); + RegisterFile registerfile1(RS1,RS2,WRITEDATA,WRITEADDRESS_MEMOUT,WRITEENABLE_MEMOUT,RESET,CLK,DATA1,DATA2); imidiateGenarator imidiateGenarator1(INSTRUCTION_OUT,IMMEDIATE_TYPE,IMMEDIATE_VALUE); ID_ExPipeline ID_EXPipeline1(CLK,RESET,WRITEENABLE,MEMORYACCESS,MEMWRITE,MEMREAD,JUMPANDLINK,ALU_OPCODE,IMMEDIATESELECT,OFFSETGENARATOR,BRANCH,JUMP,PC_OUT,PC_PLUS_4_OUT,DATA1,DATA2,INSTRUCTION_OUT,IMMEDIATE_VALUE,WRITEENABLE_IDOUT,MEMORYACCESS_IDOUT,MEMWRITE_IDOUT,MEMREAD_IDOUT,JAL_IDOUT,ALU_OPCODE_IDOUT,IMMEDIATESELECT_IDOUT,OFFSETGENARATOR_IDOUT,BRANCH_IDOUT,JUMP_IDOUT,PC_IDOUT,PC_PLUS_4_IDOUT,DATA1_IDOUT,DATA2_IDOUT,WRITEADDRESS_IDOUT,FUNCT3_IDOUT,IMMEDIATE_VALUE_IDOUT); diff --git a/CPU/CPU_tb.vvp b/CPU/CPU_tb.vvp index 6e5754e..98e5156 100644 --- a/CPU/CPU_tb.vvp +++ b/CPU/CPU_tb.vvp @@ -7,126 +7,126 @@ :vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi"; :vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi"; :vpi_module "C:\iverilog\lib\ivl\va_math.vpi"; -S_000001d3464be730 .scope module, "cpu_testbench" "cpu_testbench" 2 3; +S_0000017b113de790 .scope module, "cpu_testbench" "cpu_testbench" 2 3; .timescale 0 0; -v000001d34652a6c0_0 .var "CLK", 0 0; -v000001d34652a260_0 .var "RESET", 0 0; -S_000001d34640fee0 .scope module, "cpu_inst" "CPU" 2 8, 3 16 0, S_000001d3464be730; +v0000017b11449860_0 .var "CLK", 0 0; +v0000017b1144a3a0_0 .var "RESET", 0 0; +S_0000017b113debb0 .scope module, "cpu_inst" "CPU" 2 8, 3 16 0, S_0000017b113de790; .timescale 0 0; .port_info 0 /INPUT 1 "CLK"; .port_info 1 /INPUT 1 "RESET"; -v000001d346521ae0_0 .net "ALURESULT", 31 0, v000001d3464c08f0_0; 1 drivers -v000001d346520d20_0 .net "ALURESULT_EXOUT", 31 0, v000001d34651b6b0_0; 1 drivers -v000001d346521b80_0 .net "ALURESULT_MEMOUT", 31 0, v000001d34651f670_0; 1 drivers -v000001d346521e00_0 .net "ALU_OPCODE", 4 0, v000001d34651ef90_0; 1 drivers -v000001d346521680_0 .net "ALU_OPCODE_IDOUT", 4 0, v000001d34651c470_0; 1 drivers -v000001d346520f00_0 .net "BRANCH", 0 0, v000001d34651fc10_0; 1 drivers -v000001d346521860_0 .net "BRANCH_IDOUT", 0 0, v000001d34651bbb0_0; 1 drivers -v000001d346520280_0 .net "BUSYWAIT", 0 0, v000001d346520e60_0; 1 drivers -v000001d346520320_0 .net "CLK", 0 0, v000001d34652a6c0_0; 1 drivers -v000001d346520640_0 .net "DATA1", 31 0, v000001d346520b40_0; 1 drivers -v000001d346520fa0_0 .net "DATA1_IDOUT", 31 0, v000001d34651bc50_0; 1 drivers -v000001d346523b60_0 .net "DATA2", 31 0, v000001d346521c20_0; 1 drivers -v000001d3465232a0_0 .net "DATA2_EXOUT", 31 0, v000001d34651d050_0; 1 drivers -v000001d346524c40_0 .net "DATA2_IDOUT", 31 0, v000001d34651b610_0; 1 drivers -v000001d3465244c0_0 .net "DATA_OUT", 31 0, v000001d3465206e0_0; 1 drivers -v000001d346524380_0 .net "Data1_MUX_OUT", 31 0, v000001d3464c0670_0; 1 drivers -v000001d346523fc0_0 .net "Data2_MUX_OUT", 31 0, v000001d34649f120_0; 1 drivers -v000001d346523d40_0 .net "FUNCT3_EXOUT", 2 0, v000001d34651c0b0_0; 1 drivers -v000001d346523340_0 .net "FUNCT3_IDOUT", 2 0, v000001d34651c790_0; 1 drivers -v000001d346524060_0 .net "IMMEDIATESELECT", 0 0, v000001d34651ec70_0; 1 drivers -v000001d346524ce0_0 .net "IMMEDIATESELECT_IDOUT", 0 0, v000001d34651c1f0_0; 1 drivers -v000001d3465246a0_0 .net "IMMEDIATE_TYPE", 2 0, v000001d34651fcb0_0; 1 drivers -v000001d346524920_0 .net "IMMEDIATE_VALUE", 31 0, v000001d3465217c0_0; 1 drivers -v000001d346523c00_0 .net "IMMEDIATE_VALUE_IDOUT", 31 0, v000001d34651b750_0; 1 drivers -v000001d346524100_0 .net "INSTRUCTION", 31 0, v000001d3465214a0_0; 1 drivers -v000001d346523f20_0 .net "INSTRUCTION_OUT", 31 0, v000001d34651ed10_0; 1 drivers -v000001d346524ba0_0 .net "JAL_IDOUT", 0 0, v000001d34651c510_0; 1 drivers -v000001d3465241a0_0 .net "JAL_MUX_OUT", 31 0, v000001d34651f5d0_0; 1 drivers -v000001d346523200_0 .net "JUMP", 0 0, v000001d34651e310_0; 1 drivers -v000001d346524240_0 .net "JUMPANDLINK", 0 0, v000001d34651fe90_0; 1 drivers -v000001d3465242e0_0 .net "JUMP_IDOUT", 0 0, v000001d34651c3d0_0; 1 drivers -v000001d346523de0_0 .net "MEMORYACCESS", 0 0, v000001d34651ff30_0; 1 drivers -v000001d346524420_0 .net "MEMORYACCESS_EXOUT", 0 0, v000001d34651c5b0_0; 1 drivers -v000001d346524560_0 .net "MEMORYACCESS_IDOUT", 0 0, v000001d34651b9d0_0; 1 drivers -v000001d346524e20_0 .net "MEMORYACCESS_MEMOUT", 0 0, v000001d34651edb0_0; 1 drivers -v000001d346524740_0 .net "MEMREAD", 0 0, v000001d34651ffd0_0; 1 drivers -v000001d346523e80_0 .net "MEMREAD_EXOUT", 0 0, v000001d34651b7f0_0; 1 drivers -v000001d346523a20_0 .net "MEMREAD_IDOUT", 0 0, v000001d34651b890_0; 1 drivers -v000001d3465249c0_0 .net "MEMWRITE", 0 0, v000001d34651e450_0; 1 drivers -v000001d346524600_0 .net "MEMWRITE_EXOUT", 0 0, v000001d34651b250_0; 1 drivers -v000001d346524d80_0 .net "MEMWRITE_IDOUT", 0 0, v000001d34651b930_0; 1 drivers -v000001d346523ca0_0 .net "OFFSETGENARATOR", 0 0, v000001d34651e8b0_0; 1 drivers -v000001d346524880_0 .net "OFFSETGENARATOR_IDOUT", 0 0, v000001d34651bd90_0; 1 drivers -v000001d3465233e0_0 .net "PCADDRESSCONTROLLER", 0 0, v000001d3464c1a70_0; 1 drivers -v000001d346525000_0 .net "PCOUT", 31 0, v000001d346520500_0; 1 drivers -v000001d3465247e0_0 .net "PC_IDOUT", 31 0, v000001d34651be30_0; 1 drivers -v000001d346524a60_0 .net "PC_MUX_OUT", 31 0, v000001d34651ee50_0; 1 drivers -v000001d346524b00_0 .net "PC_OUT", 31 0, v000001d34651f0d0_0; 1 drivers -v000001d3465250a0_0 .net "PC_PLUS_4", 31 0, L_000001d346529c20; 1 drivers -v000001d346523700_0 .net "PC_PLUS_4_IDOUT", 31 0, v000001d34651c650_0; 1 drivers -v000001d346524ec0_0 .net "PC_PLUS_4_OUT", 31 0, v000001d34651f490_0; 1 drivers -v000001d346524f60_0 .net "READDATA_MEMOUT", 31 0, v000001d34651f7b0_0; 1 drivers -v000001d346523480_0 .net "RESET", 0 0, v000001d34652a260_0; 1 drivers -v000001d346523520_0 .net "RS1", 4 0, L_000001d346529b80; 1 drivers -v000001d3465235c0_0 .net "RS2", 4 0, L_000001d34652aee0; 1 drivers -v000001d346523660_0 .net "TARGETEDADDRESS", 31 0, v000001d3464c0170_0; 1 drivers -v000001d3465237a0_0 .net "WRITEADDRESS_EXOUT", 4 0, v000001d34651ba70_0; 1 drivers -v000001d346523840_0 .net "WRITEADDRESS_IDOUT", 4 0, v000001d34651c970_0; 1 drivers -v000001d3465238e0_0 .net "WRITEADDRESS_MEMOUT", 4 0, v000001d34651f850_0; 1 drivers -v000001d346523980_0 .net "WRITEDATA", 31 0, v000001d34651f990_0; 1 drivers -v000001d346523ac0_0 .net "WRITEENABLE", 0 0, v000001d346520820_0; 1 drivers -v000001d346529ae0_0 .net "WRITEENABLE_EXOUT", 0 0, v000001d34651b2f0_0; 1 drivers -v000001d346529860_0 .net "WRITEENABLE_IDOUT", 0 0, v000001d34651c6f0_0; 1 drivers -v000001d34652b0c0_0 .net "WRITEENABLE_MEMOUT", 0 0, v000001d34651f8f0_0; 1 drivers -L_000001d346529b80 .part v000001d34651ed10_0, 15, 5; -L_000001d34652aee0 .part v000001d34651ed10_0, 20, 5; -S_000001d346410070 .scope module, "ALU" "alu" 3 82, 4 3 0, S_000001d34640fee0; +v0000017b11440640_0 .net "ALURESULT", 31 0, v0000017b113e1750_0; 1 drivers +v0000017b114406e0_0 .net "ALURESULT_EXOUT", 31 0, v0000017b1143b570_0; 1 drivers +v0000017b11441860_0 .net "ALURESULT_MEMOUT", 31 0, v0000017b1143f5d0_0; 1 drivers +v0000017b114408c0_0 .net "ALU_OPCODE", 4 0, v0000017b1143f850_0; 1 drivers +v0000017b11440dc0_0 .net "ALU_OPCODE_IDOUT", 4 0, v0000017b1143b9d0_0; 1 drivers +v0000017b11441a40_0 .net "BRANCH", 0 0, v0000017b1143f8f0_0; 1 drivers +v0000017b114412c0_0 .net "BRANCH_IDOUT", 0 0, v0000017b1143ba70_0; 1 drivers +v0000017b11441f40_0 .net "BUSYWAIT", 0 0, v0000017b11441180_0; 1 drivers +v0000017b114410e0_0 .net "CLK", 0 0, v0000017b11449860_0; 1 drivers +v0000017b11441360_0 .net "DATA1", 31 0, v0000017b11440aa0_0; 1 drivers +v0000017b11441400_0 .net "DATA1_IDOUT", 31 0, v0000017b1143cc90_0; 1 drivers +v0000017b11444240_0 .net "DATA2", 31 0, v0000017b11441540_0; 1 drivers +v0000017b11444b00_0 .net "DATA2_EXOUT", 31 0, v0000017b1143cab0_0; 1 drivers +v0000017b11444ba0_0 .net "DATA2_IDOUT", 31 0, v0000017b1143bc50_0; 1 drivers +v0000017b11443700_0 .net "DATA_OUT", 31 0, v0000017b11442080_0; 1 drivers +v0000017b11445000_0 .net "Data1_MUX_OUT", 31 0, v0000017b113e0d50_0; 1 drivers +v0000017b11444c40_0 .net "Data2_MUX_OUT", 31 0, v0000017b113bf400_0; 1 drivers +v0000017b11444600_0 .net "FUNCT3_EXOUT", 2 0, v0000017b1143cfb0_0; 1 drivers +v0000017b11444100_0 .net "FUNCT3_IDOUT", 2 0, v0000017b1143c8d0_0; 1 drivers +v0000017b114442e0_0 .net "IMMEDIATESELECT", 0 0, v0000017b1143ea90_0; 1 drivers +v0000017b11444380_0 .net "IMMEDIATESELECT_IDOUT", 0 0, v0000017b1143c290_0; 1 drivers +v0000017b11443980_0 .net "IMMEDIATE_TYPE", 2 0, v0000017b1143f030_0; 1 drivers +v0000017b11444420_0 .net "IMMEDIATE_VALUE", 31 0, v0000017b11440820_0; 1 drivers +v0000017b114446a0_0 .net "IMMEDIATE_VALUE_IDOUT", 31 0, v0000017b1143c790_0; 1 drivers +v0000017b11444a60_0 .net "INSTRUCTION", 31 0, v0000017b114401e0_0; 1 drivers +v0000017b11444880_0 .net "INSTRUCTION_OUT", 31 0, v0000017b1143ed10_0; 1 drivers +v0000017b114432a0_0 .net "JAL_IDOUT", 0 0, v0000017b1143cf10_0; 1 drivers +v0000017b11443d40_0 .net "JAL_MUX_OUT", 31 0, v0000017b1143e630_0; 1 drivers +v0000017b11443f20_0 .net "JUMP", 0 0, v0000017b1143e1d0_0; 1 drivers +v0000017b11443ca0_0 .net "JUMPANDLINK", 0 0, v0000017b1143edb0_0; 1 drivers +v0000017b11444ce0_0 .net "JUMP_IDOUT", 0 0, v0000017b1143ce70_0; 1 drivers +v0000017b114444c0_0 .net "MEMORYACCESS", 0 0, v0000017b1143e590_0; 1 drivers +v0000017b114441a0_0 .net "MEMORYACCESS_EXOUT", 0 0, v0000017b1143bb10_0; 1 drivers +v0000017b11443660_0 .net "MEMORYACCESS_IDOUT", 0 0, v0000017b1143ca10_0; 1 drivers +v0000017b11443840_0 .net "MEMORYACCESS_MEMOUT", 0 0, v0000017b1143fc10_0; 1 drivers +v0000017b114450a0_0 .net "MEMREAD", 0 0, v0000017b1143e310_0; 1 drivers +v0000017b11444d80_0 .net "MEMREAD_EXOUT", 0 0, v0000017b1143d050_0; 1 drivers +v0000017b11444e20_0 .net "MEMREAD_IDOUT", 0 0, v0000017b1143bcf0_0; 1 drivers +v0000017b11443200_0 .net "MEMWRITE", 0 0, v0000017b1143e450_0; 1 drivers +v0000017b11444ec0_0 .net "MEMWRITE_EXOUT", 0 0, v0000017b1143c0b0_0; 1 drivers +v0000017b11443480_0 .net "MEMWRITE_IDOUT", 0 0, v0000017b1143bd90_0; 1 drivers +v0000017b114435c0_0 .net "OFFSETGENARATOR", 0 0, v0000017b1143e4f0_0; 1 drivers +v0000017b11444f60_0 .net "OFFSETGENARATOR_IDOUT", 0 0, v0000017b1143bf70_0; 1 drivers +v0000017b11443a20_0 .net "PCADDRESSCONTROLLER", 0 0, v0000017b113e1ed0_0; 1 drivers +v0000017b11444560_0 .net "PCOUT", 31 0, v0000017b11440460_0; 1 drivers +v0000017b114438e0_0 .net "PC_IDOUT", 31 0, v0000017b1143c1f0_0; 1 drivers +v0000017b11444060_0 .net "PC_MUX_OUT", 31 0, v0000017b1143f710_0; 1 drivers +v0000017b11444740_0 .net "PC_OUT", 31 0, v0000017b1143fcb0_0; 1 drivers +v0000017b11443340_0 .net "PC_PLUS_4", 31 0, L_0000017b1144ab20; 1 drivers +v0000017b114447e0_0 .net "PC_PLUS_4_IDOUT", 31 0, v0000017b1143c6f0_0; 1 drivers +v0000017b114433e0_0 .net "PC_PLUS_4_OUT", 31 0, v0000017b1143fb70_0; 1 drivers +v0000017b11443520_0 .net "READDATA_MEMOUT", 31 0, v0000017b1143f170_0; 1 drivers +v0000017b11444920_0 .net "RESET", 0 0, v0000017b1144a3a0_0; 1 drivers +v0000017b114437a0_0 .net "RS1", 4 0, L_0000017b11449b80; 1 drivers +v0000017b11443fc0_0 .net "RS2", 4 0, L_0000017b1144b020; 1 drivers +v0000017b114449c0_0 .net "TARGETEDADDRESS", 31 0, v0000017b113e1f70_0; 1 drivers +v0000017b11443ac0_0 .net "WRITEADDRESS_EXOUT", 4 0, v0000017b1143be30_0; 1 drivers +v0000017b11443b60_0 .net "WRITEADDRESS_IDOUT", 4 0, v0000017b1143c3d0_0; 1 drivers +v0000017b11443de0_0 .net "WRITEADDRESS_MEMOUT", 4 0, v0000017b1143fd50_0; 1 drivers +v0000017b11443c00_0 .net "WRITEDATA", 31 0, v0000017b1143e950_0; 1 drivers +v0000017b11443e80_0 .net "WRITEENABLE", 0 0, v0000017b11440f00_0; 1 drivers +v0000017b1144b0c0_0 .net "WRITEENABLE_EXOUT", 0 0, v0000017b1143b6b0_0; 1 drivers +v0000017b1144a760_0 .net "WRITEENABLE_IDOUT", 0 0, v0000017b1143c830_0; 1 drivers +v0000017b1144a6c0_0 .net "WRITEENABLE_MEMOUT", 0 0, v0000017b1143f0d0_0; 1 drivers +L_0000017b11449b80 .part v0000017b1143ed10_0, 15, 5; +L_0000017b1144b020 .part v0000017b1143ed10_0, 20, 5; +S_0000017b113ded40 .scope module, "ALU" "alu" 3 82, 4 3 0, S_0000017b113debb0; .timescale 0 0; .port_info 0 /INPUT 32 "data1"; .port_info 1 /INPUT 32 "data2"; .port_info 2 /INPUT 5 "ALU_OPCODE"; .port_info 3 /OUTPUT 32 "Output"; -v000001d3464c0850_0 .net "ALU_OPCODE", 4 0, v000001d34651c470_0; alias, 1 drivers -v000001d3464c1390_0 .net "MULHSU_result", 31 0, L_000001d3465295e0; 1 drivers -v000001d3464c11b0_0 .net "MULHU_result", 31 0, L_000001d346529680; 1 drivers -v000001d3464c1430_0 .net "MULH_result", 31 0, L_000001d34652a300; 1 drivers -v000001d3464c08f0_0 .var "Output", 31 0; -v000001d3464c0df0_0 .net/s *"_ivl_0", 63 0, L_000001d346529220; 1 drivers -L_000001d34652b230 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v000001d3464c00d0_0 .net *"_ivl_11", 31 0, L_000001d34652b230; 1 drivers -v000001d3464c0530_0 .net *"_ivl_12", 63 0, L_000001d34652ad00; 1 drivers -L_000001d34652b278 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v000001d3464c14d0_0 .net *"_ivl_15", 31 0, L_000001d34652b278; 1 drivers -v000001d3464c19d0_0 .net/s *"_ivl_2", 63 0, L_000001d34652a760; 1 drivers -v000001d3464c1f70_0 .net *"_ivl_20", 63 0, L_000001d346529ea0; 1 drivers -L_000001d34652b2c0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v000001d3464c1bb0_0 .net *"_ivl_23", 31 0, L_000001d34652b2c0; 1 drivers -v000001d3464c1570_0 .net *"_ivl_24", 63 0, L_000001d34652a080; 1 drivers -L_000001d34652b308 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v000001d3464c1610_0 .net *"_ivl_27", 31 0, L_000001d34652b308; 1 drivers -v000001d3464c1b10_0 .net *"_ivl_8", 63 0, L_000001d346529e00; 1 drivers -v000001d3464c17f0_0 .net "data1", 31 0, v000001d3464c0670_0; alias, 1 drivers -v000001d3464c0cb0_0 .net "data2", 31 0, v000001d34649f120_0; alias, 1 drivers -v000001d3464c07b0_0 .net "mulh_result", 63 0, L_000001d346529f40; 1 drivers -v000001d3464c1e30_0 .net "mulhsu_result", 63 0, L_000001d34652a800; 1 drivers -v000001d3464c02b0_0 .net "mulhu_result", 63 0, L_000001d34652a440; 1 drivers -E_000001d3464b1000/0 .event anyedge, v000001d3464c0850_0, v000001d3464c17f0_0, v000001d3464c0cb0_0, v000001d3464c1430_0; -E_000001d3464b1000/1 .event anyedge, v000001d3464c11b0_0, v000001d3464c1390_0; -E_000001d3464b1000 .event/or E_000001d3464b1000/0, E_000001d3464b1000/1; -L_000001d346529220 .extend/s 64, v000001d3464c0670_0; -L_000001d34652a760 .extend/s 64, v000001d34649f120_0; -L_000001d346529f40 .arith/mult 64, L_000001d346529220, L_000001d34652a760; -L_000001d34652a300 .part L_000001d346529f40, 32, 32; -L_000001d346529e00 .concat [ 32 32 0 0], v000001d3464c0670_0, L_000001d34652b230; -L_000001d34652ad00 .concat [ 32 32 0 0], v000001d34649f120_0, L_000001d34652b278; -L_000001d34652a440 .arith/mult 64, L_000001d346529e00, L_000001d34652ad00; -L_000001d346529680 .part L_000001d34652a440, 32, 32; -L_000001d346529ea0 .concat [ 32 32 0 0], v000001d3464c0670_0, L_000001d34652b2c0; -L_000001d34652a080 .concat [ 32 32 0 0], v000001d34649f120_0, L_000001d34652b308; -L_000001d34652a800 .arith/mult 64, L_000001d346529ea0, L_000001d34652a080; -L_000001d3465295e0 .part L_000001d34652a800, 32, 32; -S_000001d346452080 .scope module, "BranchController1" "BranchController" 3 84, 5 1 0, S_000001d34640fee0; +v0000017b113e1d90_0 .net "ALU_OPCODE", 4 0, v0000017b1143b9d0_0; alias, 1 drivers +v0000017b113e1250_0 .net "MULHSU_result", 31 0, L_0000017b114499a0; 1 drivers +v0000017b113e0490_0 .net "MULHU_result", 31 0, L_0000017b1144abc0; 1 drivers +v0000017b113e1b10_0 .net "MULH_result", 31 0, L_0000017b1144a9e0; 1 drivers +v0000017b113e1750_0 .var "Output", 31 0; +v0000017b113e12f0_0 .net/s *"_ivl_0", 63 0, L_0000017b1144a800; 1 drivers +L_0000017b1144b230 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0000017b113e1bb0_0 .net *"_ivl_11", 31 0, L_0000017b1144b230; 1 drivers +v0000017b113e1390_0 .net *"_ivl_12", 63 0, L_0000017b1144a300; 1 drivers +L_0000017b1144b278 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0000017b113e1430_0 .net *"_ivl_15", 31 0, L_0000017b1144b278; 1 drivers +v0000017b113e1070_0 .net/s *"_ivl_2", 63 0, L_0000017b1144a4e0; 1 drivers +v0000017b113e0a30_0 .net *"_ivl_20", 63 0, L_0000017b11449680; 1 drivers +L_0000017b1144b2c0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0000017b113e1c50_0 .net *"_ivl_23", 31 0, L_0000017b1144b2c0; 1 drivers +v0000017b113e16b0_0 .net *"_ivl_24", 63 0, L_0000017b11449900; 1 drivers +L_0000017b1144b308 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0000017b113e0670_0 .net *"_ivl_27", 31 0, L_0000017b1144b308; 1 drivers +v0000017b113e0850_0 .net *"_ivl_8", 63 0, L_0000017b1144a440; 1 drivers +v0000017b113e1cf0_0 .net "data1", 31 0, v0000017b113e0d50_0; alias, 1 drivers +v0000017b113e0b70_0 .net "data2", 31 0, v0000017b113bf400_0; alias, 1 drivers +v0000017b113e0c10_0 .net "mulh_result", 63 0, L_0000017b1144af80; 1 drivers +v0000017b113e0cb0_0 .net "mulhsu_result", 63 0, L_0000017b114494a0; 1 drivers +v0000017b113e0710_0 .net "mulhu_result", 63 0, L_0000017b11449e00; 1 drivers +E_0000017b113d12e0/0 .event anyedge, v0000017b113e1d90_0, v0000017b113e1cf0_0, v0000017b113e0b70_0, v0000017b113e1b10_0; +E_0000017b113d12e0/1 .event anyedge, v0000017b113e0490_0, v0000017b113e1250_0; +E_0000017b113d12e0 .event/or E_0000017b113d12e0/0, E_0000017b113d12e0/1; +L_0000017b1144a800 .extend/s 64, v0000017b113e0d50_0; +L_0000017b1144a4e0 .extend/s 64, v0000017b113bf400_0; +L_0000017b1144af80 .arith/mult 64, L_0000017b1144a800, L_0000017b1144a4e0; +L_0000017b1144a9e0 .part L_0000017b1144af80, 32, 32; +L_0000017b1144a440 .concat [ 32 32 0 0], v0000017b113e0d50_0, L_0000017b1144b230; +L_0000017b1144a300 .concat [ 32 32 0 0], v0000017b113bf400_0, L_0000017b1144b278; +L_0000017b11449e00 .arith/mult 64, L_0000017b1144a440, L_0000017b1144a300; +L_0000017b1144abc0 .part L_0000017b11449e00, 32, 32; +L_0000017b11449680 .concat [ 32 32 0 0], v0000017b113e0d50_0, L_0000017b1144b2c0; +L_0000017b11449900 .concat [ 32 32 0 0], v0000017b113bf400_0, L_0000017b1144b308; +L_0000017b114494a0 .arith/mult 64, L_0000017b11449680, L_0000017b11449900; +L_0000017b114499a0 .part L_0000017b114494a0, 32, 32; +S_0000017b1132fee0 .scope module, "BranchController1" "BranchController" 3 84, 5 1 0, S_0000017b113debb0; .timescale 0 0; .port_info 0 /INPUT 32 "data1"; .port_info 1 /INPUT 32 "data2"; @@ -136,40 +136,40 @@ S_000001d346452080 .scope module, "BranchController1" "BranchController" 3 84, 5 .port_info 5 /INPUT 1 "Jump"; .port_info 6 /OUTPUT 32 "TargetedAddress"; .port_info 7 /OUTPUT 1 "PCAddressController"; -v000001d3464c1ed0_0 .net/s "ALUresult", 31 0, v000001d3464c08f0_0; alias, 1 drivers -v000001d3464c0990_0 .net "Branch", 0 0, v000001d34651bbb0_0; alias, 1 drivers -v000001d3464c16b0_0 .net "Jump", 0 0, v000001d34651c3d0_0; alias, 1 drivers -v000001d3464c1a70_0 .var "PCAddressController", 0 0; -v000001d3464c0170_0 .var "TargetedAddress", 31 0; -v000001d3464c1c50_0 .net/s "data1", 31 0, v000001d3464c0670_0; alias, 1 drivers -v000001d3464c0d50_0 .net/s "data2", 31 0, v000001d34649f120_0; alias, 1 drivers -v000001d3464c1cf0_0 .net "func3", 2 0, v000001d34651c790_0; alias, 1 drivers -E_000001d3464b1580/0 .event anyedge, v000001d3464c08f0_0, v000001d3464c16b0_0, v000001d3464c0990_0, v000001d3464c1cf0_0; -E_000001d3464b1580/1 .event anyedge, v000001d3464c0cb0_0, v000001d3464c17f0_0; -E_000001d3464b1580 .event/or E_000001d3464b1580/0, E_000001d3464b1580/1; -S_000001d346452210 .scope module, "Data1_MUX" "MUX_32bit" 3 80, 6 1 0, S_000001d34640fee0; +v0000017b113e1e30_0 .net/s "ALUresult", 31 0, v0000017b113e1750_0; alias, 1 drivers +v0000017b113e17f0_0 .net "Branch", 0 0, v0000017b1143ba70_0; alias, 1 drivers +v0000017b113e08f0_0 .net "Jump", 0 0, v0000017b1143ce70_0; alias, 1 drivers +v0000017b113e1ed0_0 .var "PCAddressController", 0 0; +v0000017b113e1f70_0 .var "TargetedAddress", 31 0; +v0000017b113e0170_0 .net/s "data1", 31 0, v0000017b113e0d50_0; alias, 1 drivers +v0000017b113e03f0_0 .net/s "data2", 31 0, v0000017b113bf400_0; alias, 1 drivers +v0000017b113e07b0_0 .net "func3", 2 0, v0000017b1143c8d0_0; alias, 1 drivers +E_0000017b113d33e0/0 .event anyedge, v0000017b113e1750_0, v0000017b113e08f0_0, v0000017b113e17f0_0, v0000017b113e07b0_0; +E_0000017b113d33e0/1 .event anyedge, v0000017b113e0b70_0, v0000017b113e1cf0_0; +E_0000017b113d33e0 .event/or E_0000017b113d33e0/0, E_0000017b113d33e0/1; +S_0000017b11330070 .scope module, "Data1_MUX" "MUX_32bit" 3 80, 6 1 0, S_0000017b113debb0; .timescale 0 0; .port_info 0 /INPUT 32 "INPUT_0"; .port_info 1 /INPUT 32 "INPUT_1"; .port_info 2 /INPUT 1 "SELECT"; .port_info 3 /OUTPUT 32 "OUTPUT"; -v000001d3464c0210_0 .net "INPUT_0", 31 0, v000001d34651bc50_0; alias, 1 drivers -v000001d3464c0350_0 .net "INPUT_1", 31 0, v000001d34651be30_0; alias, 1 drivers -v000001d3464c0670_0 .var "OUTPUT", 31 0; -v000001d3464c0710_0 .net "SELECT", 0 0, v000001d34651bd90_0; alias, 1 drivers -E_000001d3464b2d40 .event anyedge, v000001d3464c0710_0, v000001d3464c0350_0, v000001d3464c0210_0; -S_000001d346434980 .scope module, "Data2_MUX" "MUX_32bit" 3 81, 6 1 0, S_000001d34640fee0; +v0000017b113e0530_0 .net "INPUT_0", 31 0, v0000017b1143cc90_0; alias, 1 drivers +v0000017b113e0990_0 .net "INPUT_1", 31 0, v0000017b1143c1f0_0; alias, 1 drivers +v0000017b113e0d50_0 .var "OUTPUT", 31 0; +v0000017b113e0e90_0 .net "SELECT", 0 0, v0000017b1143bf70_0; alias, 1 drivers +E_0000017b113d3220 .event anyedge, v0000017b113e0e90_0, v0000017b113e0990_0, v0000017b113e0530_0; +S_0000017b11372080 .scope module, "Data2_MUX" "MUX_32bit" 3 81, 6 1 0, S_0000017b113debb0; .timescale 0 0; .port_info 0 /INPUT 32 "INPUT_0"; .port_info 1 /INPUT 32 "INPUT_1"; .port_info 2 /INPUT 1 "SELECT"; .port_info 3 /OUTPUT 32 "OUTPUT"; -v000001d3464c0b70_0 .net "INPUT_0", 31 0, v000001d34651b610_0; alias, 1 drivers -v000001d34649f6c0_0 .net "INPUT_1", 31 0, v000001d34651b750_0; alias, 1 drivers -v000001d34649f120_0 .var "OUTPUT", 31 0; -v000001d34651c8d0_0 .net "SELECT", 0 0, v000001d34651c1f0_0; alias, 1 drivers -E_000001d3464b3600 .event anyedge, v000001d34651c8d0_0, v000001d34649f6c0_0, v000001d3464c0b70_0; -S_000001d346434b10 .scope module, "EX_MEM_pipeline1" "EX_MEM_pipeline" 3 85, 7 1 0, S_000001d34640fee0; +v0000017b113e0fd0_0 .net "INPUT_0", 31 0, v0000017b1143bc50_0; alias, 1 drivers +v0000017b113bef00_0 .net "INPUT_1", 31 0, v0000017b1143c790_0; alias, 1 drivers +v0000017b113bf400_0 .var "OUTPUT", 31 0; +v0000017b1143b7f0_0 .net "SELECT", 0 0, v0000017b1143c290_0; alias, 1 drivers +E_0000017b113d35e0 .event anyedge, v0000017b1143b7f0_0, v0000017b113bef00_0, v0000017b113e0fd0_0; +S_0000017b11372210 .scope module, "EX_MEM_pipeline1" "EX_MEM_pipeline" 3 85, 7 1 0, S_0000017b113debb0; .timescale 0 0; .port_info 0 /INPUT 1 "CLK"; .port_info 1 /INPUT 1 "RESET"; @@ -189,26 +189,26 @@ S_000001d346434b10 .scope module, "EX_MEM_pipeline1" "EX_MEM_pipeline" 3 85, 7 1 .port_info 15 /OUTPUT 5 "WRITE_ADDRESS_OUT"; .port_info 16 /OUTPUT 3 "FUNCT3_OUT"; .port_info 17 /OUTPUT 32 "DATA2_OUT"; -v000001d34651bed0_0 .net "ALU_OUTPUT", 31 0, v000001d34651f5d0_0; alias, 1 drivers -v000001d34651b6b0_0 .var "ALU_OUTPUT_OUT", 31 0; -v000001d34651cfb0_0 .net "CLK", 0 0, v000001d34652a6c0_0; alias, 1 drivers -v000001d34651c330_0 .net "DATA2", 31 0, v000001d34651b610_0; alias, 1 drivers -v000001d34651d050_0 .var "DATA2_OUT", 31 0; -v000001d34651cc90_0 .net "FUNCT3", 2 0, v000001d34651c790_0; alias, 1 drivers -v000001d34651c0b0_0 .var "FUNCT3_OUT", 2 0; -v000001d34651b1b0_0 .net "MEM_ACCESS", 0 0, v000001d34651b9d0_0; alias, 1 drivers -v000001d34651c5b0_0 .var "MEM_ACCESS_OUT", 0 0; -v000001d34651c010_0 .net "MEM_READ", 0 0, v000001d34651b890_0; alias, 1 drivers -v000001d34651b7f0_0 .var "MEM_READ_OUT", 0 0; -v000001d34651c830_0 .net "MEM_WRITE", 0 0, v000001d34651b930_0; alias, 1 drivers -v000001d34651b250_0 .var "MEM_WRITE_OUT", 0 0; -v000001d34651cdd0_0 .net "RESET", 0 0, v000001d34652a260_0; alias, 1 drivers -v000001d34651cab0_0 .net "WRITE_ADDRESS", 4 0, v000001d34651c970_0; alias, 1 drivers -v000001d34651ba70_0 .var "WRITE_ADDRESS_OUT", 4 0; -v000001d34651ca10_0 .net "WRITE_ENABLE", 0 0, v000001d34651c6f0_0; alias, 1 drivers -v000001d34651b2f0_0 .var "WRITE_ENABLE_OUT", 0 0; -E_000001d3464b3e40 .event posedge, v000001d34651cfb0_0; -S_000001d34647e940 .scope module, "ID_EXPipeline1" "ID_ExPipeline" 3 77, 8 1 0, S_000001d34640fee0; +v0000017b1143c010_0 .net "ALU_OUTPUT", 31 0, v0000017b1143e630_0; alias, 1 drivers +v0000017b1143b570_0 .var "ALU_OUTPUT_OUT", 31 0; +v0000017b1143b390_0 .net "CLK", 0 0, v0000017b11449860_0; alias, 1 drivers +v0000017b1143c470_0 .net "DATA2", 31 0, v0000017b1143bc50_0; alias, 1 drivers +v0000017b1143cab0_0 .var "DATA2_OUT", 31 0; +v0000017b1143b890_0 .net "FUNCT3", 2 0, v0000017b1143c8d0_0; alias, 1 drivers +v0000017b1143cfb0_0 .var "FUNCT3_OUT", 2 0; +v0000017b1143b610_0 .net "MEM_ACCESS", 0 0, v0000017b1143ca10_0; alias, 1 drivers +v0000017b1143bb10_0 .var "MEM_ACCESS_OUT", 0 0; +v0000017b1143b930_0 .net "MEM_READ", 0 0, v0000017b1143bcf0_0; alias, 1 drivers +v0000017b1143d050_0 .var "MEM_READ_OUT", 0 0; +v0000017b1143c510_0 .net "MEM_WRITE", 0 0, v0000017b1143bd90_0; alias, 1 drivers +v0000017b1143c0b0_0 .var "MEM_WRITE_OUT", 0 0; +v0000017b1143b250_0 .net "RESET", 0 0, v0000017b1144a3a0_0; alias, 1 drivers +v0000017b1143c970_0 .net "WRITE_ADDRESS", 4 0, v0000017b1143c3d0_0; alias, 1 drivers +v0000017b1143be30_0 .var "WRITE_ADDRESS_OUT", 4 0; +v0000017b1143b2f0_0 .net "WRITE_ENABLE", 0 0, v0000017b1143c830_0; alias, 1 drivers +v0000017b1143b6b0_0 .var "WRITE_ENABLE_OUT", 0 0; +E_0000017b113d32a0 .event posedge, v0000017b1143b390_0; +S_0000017b11354980 .scope module, "ID_EXPipeline1" "ID_ExPipeline" 3 77, 8 1 0, S_0000017b113debb0; .timescale 0 0; .port_info 0 /INPUT 1 "CLK"; .port_info 1 /INPUT 1 "Reset"; @@ -245,42 +245,42 @@ S_000001d34647e940 .scope module, "ID_EXPipeline1" "ID_ExPipeline" 3 77, 8 1 0, .port_info 32 /OUTPUT 5 "Out_WriteAddress"; .port_info 33 /OUTPUT 3 "Out_func3"; .port_info 34 /OUTPUT 32 "Out_Immediate_value"; -v000001d34651cb50_0 .net "ALU_Opcode", 4 0, v000001d34651ef90_0; alias, 1 drivers -v000001d34651b390_0 .net "Branch", 0 0, v000001d34651fc10_0; alias, 1 drivers -v000001d34651cbf0_0 .net "CLK", 0 0, v000001d34652a6c0_0; alias, 1 drivers -v000001d34651bcf0_0 .net "Data1", 31 0, v000001d346520b40_0; alias, 1 drivers -v000001d34651bb10_0 .net "Data2", 31 0, v000001d346521c20_0; alias, 1 drivers -v000001d34651bf70_0 .net "Immediate_Select", 0 0, v000001d34651ec70_0; alias, 1 drivers -v000001d34651ce70_0 .net "Immediate_value", 31 0, v000001d3465217c0_0; alias, 1 drivers -v000001d34651c290_0 .net "Jump", 0 0, v000001d34651e310_0; alias, 1 drivers -v000001d34651cf10_0 .net "Jump_and_Link", 0 0, v000001d34651fe90_0; alias, 1 drivers -v000001d34651b430_0 .net "Mem_Read", 0 0, v000001d34651ffd0_0; alias, 1 drivers -v000001d34651b4d0_0 .net "Mem_Write", 0 0, v000001d34651e450_0; alias, 1 drivers -v000001d34651b570_0 .net "Memory_Access", 0 0, v000001d34651ff30_0; alias, 1 drivers -v000001d34651c150_0 .net "Offset_Generate", 0 0, v000001d34651e8b0_0; alias, 1 drivers -v000001d34651c470_0 .var "Out_ALU_Opcode", 4 0; -v000001d34651bbb0_0 .var "Out_Branch", 0 0; -v000001d34651bc50_0 .var "Out_Data1", 31 0; -v000001d34651b610_0 .var "Out_Data2", 31 0; -v000001d34651c1f0_0 .var "Out_Immediate_Select", 0 0; -v000001d34651b750_0 .var "Out_Immediate_value", 31 0; -v000001d34651c3d0_0 .var "Out_Jump", 0 0; -v000001d34651c510_0 .var "Out_Jump_and_Link", 0 0; -v000001d34651b890_0 .var "Out_Mem_Read", 0 0; -v000001d34651b930_0 .var "Out_Mem_Write", 0 0; -v000001d34651b9d0_0 .var "Out_Memory_Access", 0 0; -v000001d34651bd90_0 .var "Out_Offset_Generate", 0 0; -v000001d34651be30_0 .var "Out_PC", 31 0; -v000001d34651c650_0 .var "Out_PC_next", 31 0; -v000001d34651c970_0 .var "Out_WriteAddress", 4 0; -v000001d34651c6f0_0 .var "Out_Write_Enable", 0 0; -v000001d34651c790_0 .var "Out_func3", 2 0; -v000001d34651e950_0 .net "PC", 31 0, v000001d34651f0d0_0; alias, 1 drivers -v000001d34651e4f0_0 .net "PC_next", 31 0, v000001d34651f490_0; alias, 1 drivers -v000001d34651f210_0 .net "Reset", 0 0, v000001d34652a260_0; alias, 1 drivers -v000001d34651e590_0 .net "Write_Enable", 0 0, v000001d346520820_0; alias, 1 drivers -v000001d34651e810_0 .net "instruction", 31 0, v000001d34651ed10_0; alias, 1 drivers -S_000001d3464193f0 .scope module, "ID_IF_register1" "ID_IF_register" 3 71, 9 1 0, S_000001d34640fee0; +v0000017b1143c650_0 .net "ALU_Opcode", 4 0, v0000017b1143f850_0; alias, 1 drivers +v0000017b1143bed0_0 .net "Branch", 0 0, v0000017b1143f8f0_0; alias, 1 drivers +v0000017b1143cdd0_0 .net "CLK", 0 0, v0000017b11449860_0; alias, 1 drivers +v0000017b1143bbb0_0 .net "Data1", 31 0, v0000017b11440aa0_0; alias, 1 drivers +v0000017b1143b1b0_0 .net "Data2", 31 0, v0000017b11441540_0; alias, 1 drivers +v0000017b1143c150_0 .net "Immediate_Select", 0 0, v0000017b1143ea90_0; alias, 1 drivers +v0000017b1143cd30_0 .net "Immediate_value", 31 0, v0000017b11440820_0; alias, 1 drivers +v0000017b1143b430_0 .net "Jump", 0 0, v0000017b1143e1d0_0; alias, 1 drivers +v0000017b1143c330_0 .net "Jump_and_Link", 0 0, v0000017b1143edb0_0; alias, 1 drivers +v0000017b1143b750_0 .net "Mem_Read", 0 0, v0000017b1143e310_0; alias, 1 drivers +v0000017b1143c5b0_0 .net "Mem_Write", 0 0, v0000017b1143e450_0; alias, 1 drivers +v0000017b1143b4d0_0 .net "Memory_Access", 0 0, v0000017b1143e590_0; alias, 1 drivers +v0000017b1143cbf0_0 .net "Offset_Generate", 0 0, v0000017b1143e4f0_0; alias, 1 drivers +v0000017b1143b9d0_0 .var "Out_ALU_Opcode", 4 0; +v0000017b1143ba70_0 .var "Out_Branch", 0 0; +v0000017b1143cc90_0 .var "Out_Data1", 31 0; +v0000017b1143bc50_0 .var "Out_Data2", 31 0; +v0000017b1143c290_0 .var "Out_Immediate_Select", 0 0; +v0000017b1143c790_0 .var "Out_Immediate_value", 31 0; +v0000017b1143ce70_0 .var "Out_Jump", 0 0; +v0000017b1143cf10_0 .var "Out_Jump_and_Link", 0 0; +v0000017b1143bcf0_0 .var "Out_Mem_Read", 0 0; +v0000017b1143bd90_0 .var "Out_Mem_Write", 0 0; +v0000017b1143ca10_0 .var "Out_Memory_Access", 0 0; +v0000017b1143bf70_0 .var "Out_Offset_Generate", 0 0; +v0000017b1143c1f0_0 .var "Out_PC", 31 0; +v0000017b1143c6f0_0 .var "Out_PC_next", 31 0; +v0000017b1143c3d0_0 .var "Out_WriteAddress", 4 0; +v0000017b1143c830_0 .var "Out_Write_Enable", 0 0; +v0000017b1143c8d0_0 .var "Out_func3", 2 0; +v0000017b1143e6d0_0 .net "PC", 31 0, v0000017b1143fcb0_0; alias, 1 drivers +v0000017b1143e3b0_0 .net "PC_next", 31 0, v0000017b1143fb70_0; alias, 1 drivers +v0000017b11440070_0 .net "Reset", 0 0, v0000017b1144a3a0_0; alias, 1 drivers +v0000017b1143ee50_0 .net "Write_Enable", 0 0, v0000017b11440f00_0; alias, 1 drivers +v0000017b1143eb30_0 .net "instruction", 31 0, v0000017b1143ed10_0; alias, 1 drivers +S_0000017b1139eb50 .scope module, "ID_IF_register1" "ID_IF_register" 3 71, 9 1 0, S_0000017b113debb0; .timescale 0 0; .port_info 0 /INPUT 1 "CLK"; .port_info 1 /INPUT 32 "INSTRUCTION"; @@ -290,26 +290,26 @@ S_000001d3464193f0 .scope module, "ID_IF_register1" "ID_IF_register" 3 71, 9 1 0 .port_info 5 /OUTPUT 32 "INSTRUCTION_OUT"; .port_info 6 /OUTPUT 32 "PC_OUT"; .port_info 7 /OUTPUT 32 "PC_PLUS_4_OUT"; -v000001d34651f2b0_0 .net "CLK", 0 0, v000001d34652a6c0_0; alias, 1 drivers -v000001d34651f350_0 .net "INSTRUCTION", 31 0, v000001d3465214a0_0; alias, 1 drivers -v000001d34651ed10_0 .var "INSTRUCTION_OUT", 31 0; -v000001d34651f3f0_0 .net "PC", 31 0, v000001d346520500_0; alias, 1 drivers -v000001d34651f0d0_0 .var "PC_OUT", 31 0; -v000001d34651e630_0 .net "PC_PLUS_4", 31 0, L_000001d346529c20; alias, 1 drivers -v000001d34651f490_0 .var "PC_PLUS_4_OUT", 31 0; -v000001d34651e6d0_0 .net "RESET", 0 0, v000001d34652a260_0; alias, 1 drivers -S_000001d346406110 .scope module, "JAL_MUX" "MUX_32bit" 3 83, 6 1 0, S_000001d34640fee0; +v0000017b1143eef0_0 .net "CLK", 0 0, v0000017b11449860_0; alias, 1 drivers +v0000017b1143e770_0 .net "INSTRUCTION", 31 0, v0000017b114401e0_0; alias, 1 drivers +v0000017b1143ed10_0 .var "INSTRUCTION_OUT", 31 0; +v0000017b1143e270_0 .net "PC", 31 0, v0000017b11440460_0; alias, 1 drivers +v0000017b1143fcb0_0 .var "PC_OUT", 31 0; +v0000017b1143fad0_0 .net "PC_PLUS_4", 31 0, L_0000017b1144ab20; alias, 1 drivers +v0000017b1143fb70_0 .var "PC_PLUS_4_OUT", 31 0; +v0000017b1143f670_0 .net "RESET", 0 0, v0000017b1144a3a0_0; alias, 1 drivers +S_0000017b113391e0 .scope module, "JAL_MUX" "MUX_32bit" 3 83, 6 1 0, S_0000017b113debb0; .timescale 0 0; .port_info 0 /INPUT 32 "INPUT_0"; .port_info 1 /INPUT 32 "INPUT_1"; .port_info 2 /INPUT 1 "SELECT"; .port_info 3 /OUTPUT 32 "OUTPUT"; -v000001d34651f530_0 .net "INPUT_0", 31 0, v000001d3464c08f0_0; alias, 1 drivers -v000001d34651f030_0 .net "INPUT_1", 31 0, v000001d34651c650_0; alias, 1 drivers -v000001d34651f5d0_0 .var "OUTPUT", 31 0; -v000001d34651e270_0 .net "SELECT", 0 0, v000001d34651c510_0; alias, 1 drivers -E_000001d3464b3d00 .event anyedge, v000001d34651c510_0, v000001d34651c650_0, v000001d3464c08f0_0; -S_000001d3464062a0 .scope module, "MEM_WBPipeline1" "Mem_WBPipeline" 3 89, 10 1 0, S_000001d34640fee0; +v0000017b1143ef90_0 .net "INPUT_0", 31 0, v0000017b113e1750_0; alias, 1 drivers +v0000017b1143fa30_0 .net "INPUT_1", 31 0, v0000017b1143c6f0_0; alias, 1 drivers +v0000017b1143e630_0 .var "OUTPUT", 31 0; +v0000017b1143f210_0 .net "SELECT", 0 0, v0000017b1143cf10_0; alias, 1 drivers +E_0000017b113d34a0 .event anyedge, v0000017b1143cf10_0, v0000017b1143c6f0_0, v0000017b113e1750_0; +S_0000017b11339370 .scope module, "MEM_WBPipeline1" "Mem_WBPipeline" 3 89, 10 1 0, S_0000017b113debb0; .timescale 0 0; .port_info 0 /INPUT 1 "CLK"; .port_info 1 /INPUT 1 "Reset"; @@ -323,41 +323,41 @@ S_000001d3464062a0 .scope module, "MEM_WBPipeline1" "Mem_WBPipeline" 3 89, 10 1 .port_info 9 /OUTPUT 32 "Memory_Data_Out"; .port_info 10 /OUTPUT 32 "ALU_Output_Out"; .port_info 11 /OUTPUT 5 "Write_Address_out"; -v000001d34651fad0_0 .net "ALU_Output", 31 0, v000001d34651b6b0_0; alias, 1 drivers -v000001d34651f670_0 .var "ALU_Output_Out", 31 0; -v000001d34651f710_0 .net "CLK", 0 0, v000001d34652a6c0_0; alias, 1 drivers -v000001d34651fdf0_0 .net "Memory_Data", 31 0, v000001d3465206e0_0; alias, 1 drivers -v000001d34651f7b0_0 .var "Memory_Data_Out", 31 0; -v000001d346520070_0 .net "Memory_access", 0 0, v000001d34651c5b0_0; alias, 1 drivers -v000001d34651edb0_0 .var "Memory_access_Out", 0 0; -v000001d34651e1d0_0 .net "Reset", 0 0, v000001d34652a260_0; alias, 1 drivers -v000001d34651f170_0 .net "Write_Address", 4 0, v000001d34651ba70_0; alias, 1 drivers -v000001d34651f850_0 .var "Write_Address_out", 4 0; -v000001d34651f8f0_0 .var "Write_Enable_Out", 0 0; -v000001d34651e3b0_0 .net "Write_enable", 0 0, v000001d34651b2f0_0; alias, 1 drivers -S_000001d346412f10 .scope module, "Memory_access_MUX" "MUX_32bit" 3 92, 6 1 0, S_000001d34640fee0; +v0000017b1143f2b0_0 .net "ALU_Output", 31 0, v0000017b1143b570_0; alias, 1 drivers +v0000017b1143f5d0_0 .var "ALU_Output_Out", 31 0; +v0000017b1143e810_0 .net "CLK", 0 0, v0000017b11449860_0; alias, 1 drivers +v0000017b1143ec70_0 .net "Memory_Data", 31 0, v0000017b11442080_0; alias, 1 drivers +v0000017b1143f170_0 .var "Memory_Data_Out", 31 0; +v0000017b1143f990_0 .net "Memory_access", 0 0, v0000017b1143bb10_0; alias, 1 drivers +v0000017b1143fc10_0 .var "Memory_access_Out", 0 0; +v0000017b1143ebd0_0 .net "Reset", 0 0, v0000017b1144a3a0_0; alias, 1 drivers +v0000017b1143f350_0 .net "Write_Address", 4 0, v0000017b1143be30_0; alias, 1 drivers +v0000017b1143fd50_0 .var "Write_Address_out", 4 0; +v0000017b1143f0d0_0 .var "Write_Enable_Out", 0 0; +v0000017b1143fdf0_0 .net "Write_enable", 0 0, v0000017b1143b6b0_0; alias, 1 drivers +S_0000017b11326110 .scope module, "Memory_access_MUX" "MUX_32bit" 3 92, 6 1 0, S_0000017b113debb0; .timescale 0 0; .port_info 0 /INPUT 32 "INPUT_0"; .port_info 1 /INPUT 32 "INPUT_1"; .port_info 2 /INPUT 1 "SELECT"; .port_info 3 /OUTPUT 32 "OUTPUT"; -v000001d34651fa30_0 .net "INPUT_0", 31 0, v000001d34651f670_0; alias, 1 drivers -v000001d34651e770_0 .net "INPUT_1", 31 0, v000001d34651f7b0_0; alias, 1 drivers -v000001d34651f990_0 .var "OUTPUT", 31 0; -v000001d34651eef0_0 .net "SELECT", 0 0, v000001d34651edb0_0; alias, 1 drivers -E_000001d3464b3780 .event anyedge, v000001d34651edb0_0, v000001d34651f7b0_0, v000001d34651f670_0; -S_000001d3464130a0 .scope module, "PC_MUX" "MUX_32bit" 3 68, 6 1 0, S_000001d34640fee0; +v0000017b1143f3f0_0 .net "INPUT_0", 31 0, v0000017b1143f5d0_0; alias, 1 drivers +v0000017b1143e8b0_0 .net "INPUT_1", 31 0, v0000017b1143f170_0; alias, 1 drivers +v0000017b1143e950_0 .var "OUTPUT", 31 0; +v0000017b1143f490_0 .net "SELECT", 0 0, v0000017b1143fc10_0; alias, 1 drivers +E_0000017b113d3260 .event anyedge, v0000017b1143fc10_0, v0000017b1143f170_0, v0000017b1143f5d0_0; +S_0000017b113262a0 .scope module, "PC_MUX" "MUX_32bit" 3 68, 6 1 0, S_0000017b113debb0; .timescale 0 0; .port_info 0 /INPUT 32 "INPUT_0"; .port_info 1 /INPUT 32 "INPUT_1"; .port_info 2 /INPUT 1 "SELECT"; .port_info 3 /OUTPUT 32 "OUTPUT"; -v000001d34651fb70_0 .net "INPUT_0", 31 0, L_000001d346529c20; alias, 1 drivers -v000001d34651e9f0_0 .net "INPUT_1", 31 0, v000001d3464c0170_0; alias, 1 drivers -v000001d34651ee50_0 .var "OUTPUT", 31 0; -v000001d34651ea90_0 .net "SELECT", 0 0, v000001d3464c1a70_0; alias, 1 drivers -E_000001d3464b3cc0 .event anyedge, v000001d3464c1a70_0, v000001d3464c0170_0, v000001d34651e630_0; -S_000001d34645f780 .scope module, "controlunit1" "controlUnit" 3 74, 11 1 0, S_000001d34640fee0; +v0000017b1143e9f0_0 .net "INPUT_0", 31 0, L_0000017b1144ab20; alias, 1 drivers +v0000017b1143f530_0 .net "INPUT_1", 31 0, v0000017b113e1f70_0; alias, 1 drivers +v0000017b1143f710_0 .var "OUTPUT", 31 0; +v0000017b1143f7b0_0 .net "SELECT", 0 0, v0000017b113e1ed0_0; alias, 1 drivers +E_0000017b113d2fe0 .event anyedge, v0000017b113e1ed0_0, v0000017b113e1f70_0, v0000017b1143fad0_0; +S_0000017b11332f10 .scope module, "controlunit1" "controlUnit" 3 74, 11 1 0, S_0000017b113debb0; .timescale 0 0; .port_info 0 /INPUT 32 "INSTRUCTION"; .port_info 1 /OUTPUT 1 "WRITE_ENABLE"; @@ -371,26 +371,26 @@ S_000001d34645f780 .scope module, "controlunit1" "controlUnit" 3 74, 11 1 0, S_0 .port_info 9 /OUTPUT 1 "BRANCH"; .port_info 10 /OUTPUT 1 "JUMP"; .port_info 11 /OUTPUT 3 "IMMEDIATE_TYPE"; -v000001d34651ef90_0 .var "ALU_OPCODE", 4 0; -v000001d34651fc10_0 .var "BRANCH", 0 0; -v000001d34651eb30_0 .net "FUNCT3", 2 0, L_000001d34652a620; 1 drivers -v000001d34651ebd0_0 .net "FUNCT7", 6 0, L_000001d346529400; 1 drivers -v000001d34651ec70_0 .var "IMMEDIATE_SELECT", 0 0; -v000001d34651fcb0_0 .var "IMMEDIATE_TYPE", 2 0; -v000001d34651fd50_0 .net "INSTRUCTION", 31 0, v000001d34651ed10_0; alias, 1 drivers -v000001d34651e310_0 .var "JUMP", 0 0; -v000001d34651fe90_0 .var "JUMP_AND_LINK", 0 0; -v000001d34651ff30_0 .var "MEMORY_ACCESS", 0 0; -v000001d34651ffd0_0 .var "MEM_READ", 0 0; -v000001d34651e450_0 .var "MEM_WRITE", 0 0; -v000001d34651e8b0_0 .var "OFFSET_GENARATOR", 0 0; -v000001d346520dc0_0 .net "OPCODE", 6 0, L_000001d34652a3a0; 1 drivers -v000001d346520820_0 .var "WRITE_ENABLE", 0 0; -E_000001d3464b37c0 .event anyedge, v000001d34651ebd0_0, v000001d34651eb30_0, v000001d346520dc0_0; -L_000001d34652a3a0 .part v000001d34651ed10_0, 0, 7; -L_000001d34652a620 .part v000001d34651ed10_0, 12, 3; -L_000001d346529400 .part v000001d34651ed10_0, 25, 7; -S_000001d34645f910 .scope module, "datamemory1" "data_memory" 3 88, 12 1 0, S_000001d34640fee0; +v0000017b1143f850_0 .var "ALU_OPCODE", 4 0; +v0000017b1143f8f0_0 .var "BRANCH", 0 0; +v0000017b1143fe90_0 .net "FUNCT3", 2 0, L_0000017b1144a940; 1 drivers +v0000017b1143ff30_0 .net "FUNCT7", 6 0, L_0000017b1144ae40; 1 drivers +v0000017b1143ea90_0 .var "IMMEDIATE_SELECT", 0 0; +v0000017b1143f030_0 .var "IMMEDIATE_TYPE", 2 0; +v0000017b1143ffd0_0 .net "INSTRUCTION", 31 0, v0000017b1143ed10_0; alias, 1 drivers +v0000017b1143e1d0_0 .var "JUMP", 0 0; +v0000017b1143edb0_0 .var "JUMP_AND_LINK", 0 0; +v0000017b1143e590_0 .var "MEMORY_ACCESS", 0 0; +v0000017b1143e310_0 .var "MEM_READ", 0 0; +v0000017b1143e450_0 .var "MEM_WRITE", 0 0; +v0000017b1143e4f0_0 .var "OFFSET_GENARATOR", 0 0; +v0000017b11440780_0 .net "OPCODE", 6 0, L_0000017b11449400; 1 drivers +v0000017b11440f00_0 .var "WRITE_ENABLE", 0 0; +E_0000017b113d30a0 .event anyedge, v0000017b1143ff30_0, v0000017b1143fe90_0, v0000017b11440780_0; +L_0000017b11449400 .part v0000017b1143ed10_0, 0, 7; +L_0000017b1144a940 .part v0000017b1143ed10_0, 12, 3; +L_0000017b1144ae40 .part v0000017b1143ed10_0, 25, 7; +S_0000017b113330a0 .scope module, "datamemory1" "data_memory" 3 88, 12 1 0, S_0000017b113debb0; .timescale 0 0; .port_info 0 /INPUT 1 "CLK"; .port_info 1 /INPUT 1 "RESET"; @@ -400,61 +400,61 @@ S_000001d34645f910 .scope module, "datamemory1" "data_memory" 3 88, 12 1 0, S_00 .port_info 5 /INPUT 32 "WRITEDATA"; .port_info 6 /OUTPUT 32 "READDATA"; .port_info 7 /OUTPUT 1 "BUSYWAIT"; -v000001d346520780_0 .net "ADDRESS", 31 0, v000001d34651b6b0_0; alias, 1 drivers -v000001d346520e60_0 .var "BUSYWAIT", 0 0; -v000001d346521720_0 .net "CLK", 0 0, v000001d34652a6c0_0; alias, 1 drivers -v000001d346521540_0 .net "READ", 0 0, v000001d34651b7f0_0; alias, 1 drivers -v000001d3465206e0_0 .var "READDATA", 31 0; -v000001d3465203c0_0 .net "RESET", 0 0, v000001d34652a260_0; alias, 1 drivers -v000001d346521040_0 .net "WRITE", 0 0, v000001d34651b250_0; alias, 1 drivers -v000001d346521cc0_0 .net "WRITEDATA", 31 0, v000001d34651d050_0; alias, 1 drivers -v000001d346520960_0 .var *"_ivl_3", 31 0; Local signal -v000001d346521900_0 .var/i "i", 31 0; -v000001d346521180 .array "memory_array", 1023 0, 7 0; -E_000001d3464b3840 .event posedge, v000001d34651cdd0_0; -E_000001d3464b3800 .event anyedge, v000001d34651b250_0, v000001d34651b7f0_0; -S_000001d34644ebe0 .scope module, "imidiateGenarator1" "imidiateGenarator" 3 76, 13 1 0, S_000001d34640fee0; +v0000017b11441b80_0 .net "ADDRESS", 31 0, v0000017b1143b570_0; alias, 1 drivers +v0000017b11441180_0 .var "BUSYWAIT", 0 0; +v0000017b11440b40_0 .net "CLK", 0 0, v0000017b11449860_0; alias, 1 drivers +v0000017b11440960_0 .net "READ", 0 0, v0000017b1143d050_0; alias, 1 drivers +v0000017b11442080_0 .var "READDATA", 31 0; +v0000017b11441040_0 .net "RESET", 0 0, v0000017b1144a3a0_0; alias, 1 drivers +v0000017b11440280_0 .net "WRITE", 0 0, v0000017b1143c0b0_0; alias, 1 drivers +v0000017b114419a0_0 .net "WRITEDATA", 31 0, v0000017b1143cab0_0; alias, 1 drivers +v0000017b11440e60_0 .var *"_ivl_3", 31 0; Local signal +v0000017b11440a00_0 .var/i "i", 31 0; +v0000017b114414a0 .array "memory_array", 1023 0, 7 0; +E_0000017b113d3ca0 .event posedge, v0000017b1143b250_0; +E_0000017b113d37e0 .event anyedge, v0000017b1143c0b0_0, v0000017b1143d050_0; +S_0000017b1137f780 .scope module, "imidiateGenarator1" "imidiateGenarator" 3 76, 13 1 0, S_0000017b113debb0; .timescale 0 0; .port_info 0 /INPUT 32 "INSTRUCTION"; .port_info 1 /INPUT 3 "IMMEDIATE_TYPE"; .port_info 2 /OUTPUT 32 "IMMEDIATE_VALUE"; -v000001d346521220_0 .net "IMMEDIATE_TYPE", 2 0, v000001d34651fcb0_0; alias, 1 drivers -v000001d3465217c0_0 .var "IMMEDIATE_VALUE", 31 0; -v000001d346520460_0 .net "INSTRUCTION", 31 0, v000001d34651ed10_0; alias, 1 drivers -E_000001d3464b3380 .event anyedge, v000001d34651fcb0_0, v000001d34651e810_0; -S_000001d34644ed70 .scope module, "instructionmem1" "instruction_memory" 3 66, 14 62 0, S_000001d34640fee0; +v0000017b114403c0_0 .net "IMMEDIATE_TYPE", 2 0, v0000017b1143f030_0; alias, 1 drivers +v0000017b11440820_0 .var "IMMEDIATE_VALUE", 31 0; +v0000017b11441c20_0 .net "INSTRUCTION", 31 0, v0000017b1143ed10_0; alias, 1 drivers +E_0000017b113d3120 .event anyedge, v0000017b1143f030_0, v0000017b1143eb30_0; +S_0000017b1137f910 .scope module, "instructionmem1" "instruction_memory" 3 66, 14 62 0, S_0000017b113debb0; .timescale 0 0; .port_info 0 /INPUT 1 "CLK"; .port_info 1 /INPUT 1 "RESET"; .port_info 2 /INPUT 32 "PC"; .port_info 3 /OUTPUT 32 "INSTRUCTION"; -v000001d3465215e0_0 .net "CLK", 0 0, v000001d34652a6c0_0; alias, 1 drivers -v000001d3465214a0_0 .var "INSTRUCTION", 31 0; -v000001d3465212c0_0 .net "PC", 31 0, v000001d346520500_0; alias, 1 drivers -v000001d3465208c0_0 .net "RESET", 0 0, v000001d34652a260_0; alias, 1 drivers -v000001d346520a00 .array "memory_array", 255 0, 31 0; -E_000001d3464b31c0 .event posedge, v000001d34651cdd0_0, v000001d34651cfb0_0; -S_000001d346522e70 .scope module, "pc1" "pc" 3 69, 15 1 0, S_000001d34640fee0; +v0000017b11441cc0_0 .net "CLK", 0 0, v0000017b11449860_0; alias, 1 drivers +v0000017b114401e0_0 .var "INSTRUCTION", 31 0; +v0000017b11441680_0 .net "PC", 31 0, v0000017b11440460_0; alias, 1 drivers +v0000017b114415e0_0 .net "RESET", 0 0, v0000017b1144a3a0_0; alias, 1 drivers +v0000017b11441ae0 .array "memory_array", 255 0, 31 0; +E_0000017b113d3960 .event posedge, v0000017b1143b250_0, v0000017b1143b390_0; +S_0000017b11442ce0 .scope module, "pc1" "pc" 3 69, 15 1 0, S_0000017b113debb0; .timescale 0 0; .port_info 0 /INPUT 32 "PCIN"; .port_info 1 /INPUT 1 "RESET"; .port_info 2 /INPUT 1 "CLK"; .port_info 3 /OUTPUT 32 "PCOUT"; -v000001d346520c80_0 .net "CLK", 0 0, v000001d34652a6c0_0; alias, 1 drivers -v000001d346521360_0 .net "PCIN", 31 0, v000001d34651ee50_0; alias, 1 drivers -v000001d346520500_0 .var "PCOUT", 31 0; -v000001d346521ea0_0 .net "RESET", 0 0, v000001d34652a260_0; alias, 1 drivers -S_000001d3465221f0 .scope module, "pc_4_adder" "adder" 3 70, 16 1 0, S_000001d34640fee0; +v0000017b11440320_0 .net "CLK", 0 0, v0000017b11449860_0; alias, 1 drivers +v0000017b11441d60_0 .net "PCIN", 31 0, v0000017b1143f710_0; alias, 1 drivers +v0000017b11440460_0 .var "PCOUT", 31 0; +v0000017b11440be0_0 .net "RESET", 0 0, v0000017b1144a3a0_0; alias, 1 drivers +S_0000017b11442e70 .scope module, "pc_4_adder" "adder" 3 70, 16 1 0, S_0000017b113debb0; .timescale 0 0; .port_info 0 /INPUT 32 "PC"; .port_info 1 /OUTPUT 32 "PCPLUS4"; -v000001d346521f40_0 .net "PC", 31 0, v000001d346520500_0; alias, 1 drivers -v000001d346520aa0_0 .net "PCPLUS4", 31 0, L_000001d346529c20; alias, 1 drivers -L_000001d34652b1e8 .functor BUFT 1, C4<00000000000000000000000000000100>, C4<0>, C4<0>, C4<0>; -v000001d3465219a0_0 .net/2u *"_ivl_0", 31 0, L_000001d34652b1e8; 1 drivers -L_000001d346529c20 .delay 32 (1,1,1) L_000001d346529c20/d; -L_000001d346529c20/d .arith/sum 32, v000001d346520500_0, L_000001d34652b1e8; -S_000001d346522380 .scope module, "registerfile1" "RegisterFile" 3 75, 17 1 0, S_000001d34640fee0; +v0000017b11440fa0_0 .net "PC", 31 0, v0000017b11440460_0; alias, 1 drivers +v0000017b114405a0_0 .net "PCPLUS4", 31 0, L_0000017b1144ab20; alias, 1 drivers +L_0000017b1144b1e8 .functor BUFT 1, C4<00000000000000000000000000000100>, C4<0>, C4<0>, C4<0>; +v0000017b11441220_0 .net/2u *"_ivl_0", 31 0, L_0000017b1144b1e8; 1 drivers +L_0000017b1144ab20 .delay 32 (1,1,1) L_0000017b1144ab20/d; +L_0000017b1144ab20/d .arith/sum 32, v0000017b11440460_0, L_0000017b1144b1e8; +S_0000017b11442830 .scope module, "registerfile1" "RegisterFile" 3 75, 17 1 0, S_0000017b113debb0; .timescale 0 0; .port_info 0 /INPUT 5 "RS1"; .port_info 1 /INPUT 5 "RS2"; @@ -465,124 +465,120 @@ S_000001d346522380 .scope module, "registerfile1" "RegisterFile" 3 75, 17 1 0, S .port_info 6 /INPUT 1 "CLK"; .port_info 7 /OUTPUT 32 "DATA1"; .port_info 8 /OUTPUT 32 "DATA2"; -v000001d346521a40_0 .net "CLK", 0 0, v000001d34652a6c0_0; alias, 1 drivers -v000001d346520b40_0 .var "DATA1", 31 0; -v000001d346521c20_0 .var "DATA2", 31 0; -v000001d346520be0_0 .net "RESET", 0 0, v000001d34652a260_0; alias, 1 drivers -v000001d346521400_0 .net "RS1", 4 0, L_000001d346529b80; alias, 1 drivers -v000001d346522080_0 .net "RS2", 4 0, L_000001d34652aee0; alias, 1 drivers -v000001d346521d60_0 .net "WRITEADDRESS", 4 0, v000001d34651c970_0; alias, 1 drivers -v000001d3465210e0_0 .net "WRITEDATA", 31 0, v000001d34651f990_0; alias, 1 drivers -v000001d3465201e0_0 .net "WRITEENABLE", 0 0, v000001d34651f8f0_0; alias, 1 drivers -v000001d3465205a0 .array "registers", 31 0, 31 0; -E_000001d3464b3f40 .event anyedge, v000001d346522080_0, v000001d346521400_0; - .scope S_000001d34644ed70; +v0000017b114417c0_0 .net "CLK", 0 0, v0000017b11449860_0; alias, 1 drivers +v0000017b11440aa0_0 .var "DATA1", 31 0; +v0000017b11441540_0 .var "DATA2", 31 0; +v0000017b11441720_0 .net "RESET", 0 0, v0000017b1144a3a0_0; alias, 1 drivers +v0000017b11440500_0 .net "RS1", 4 0, L_0000017b11449b80; alias, 1 drivers +v0000017b11441fe0_0 .net "RS2", 4 0, L_0000017b1144b020; alias, 1 drivers +v0000017b11441900_0 .net "WRITEADDRESS", 4 0, v0000017b1143fd50_0; alias, 1 drivers +v0000017b11440c80_0 .net "WRITEDATA", 31 0, v0000017b1143e950_0; alias, 1 drivers +v0000017b11440d20_0 .net "WRITEENABLE", 0 0, v0000017b1143f0d0_0; alias, 1 drivers +v0000017b11441ea0 .array "registers", 31 0, 31 0; +E_0000017b113d3560 .event anyedge, v0000017b11441fe0_0, v0000017b11440500_0; + .scope S_0000017b1137f910; T_0 ; %pushi/vec4 2400223379, 0, 32; %ix/load 4, 0, 0; %flag_set/imm 4, 0; - %store/vec4a v000001d346520a00, 4, 0; + %store/vec4a v0000017b11441ae0, 4, 0; %pushi/vec4 62995, 0, 32; %ix/load 4, 1, 0; %flag_set/imm 4, 0; - %store/vec4a v000001d346520a00, 4, 0; - %pushi/vec4 1441955, 0, 32; - %ix/load 4, 2, 0; - %flag_set/imm 4, 0; - %store/vec4a v000001d346520a00, 4, 0; + %store/vec4a v0000017b11441ae0, 4, 0; %pushi/vec4 4063625475, 0, 32; - %ix/load 4, 3, 0; + %ix/load 4, 2, 0; %flag_set/imm 4, 0; - %store/vec4a v000001d346520a00, 4, 0; + %store/vec4a v0000017b11441ae0, 4, 0; %pushi/vec4 4072710563, 0, 32; - %ix/load 4, 4, 0; + %ix/load 4, 3, 0; %flag_set/imm 4, 0; - %store/vec4a v000001d346520a00, 4, 0; + %store/vec4a v0000017b11441ae0, 4, 0; %end; .thread T_0; - .scope S_000001d34644ed70; + .scope S_0000017b1137f910; T_1 ; - %wait E_000001d3464b31c0; + %wait E_0000017b113d3960; %delay 1, 0; - %load/vec4 v000001d3465208c0_0; + %load/vec4 v0000017b114415e0_0; %flag_set/vec4 8; %jmp/0xz T_1.0, 8; %pushi/vec4 0, 0, 32; - %assign/vec4 v000001d3465214a0_0, 0; + %assign/vec4 v0000017b114401e0_0, 0; %jmp T_1.1; T_1.0 ; - %load/vec4 v000001d3465212c0_0; - %parti/s 8, 0, 2; + %load/vec4 v0000017b11441680_0; + %parti/s 8, 2, 3; %pad/u 10; %ix/vec4 4; - %load/vec4a v000001d346520a00, 4; - %assign/vec4 v000001d3465214a0_0, 0; + %load/vec4a v0000017b11441ae0, 4; + %assign/vec4 v0000017b114401e0_0, 0; T_1.1 ; %jmp T_1; .thread T_1; - .scope S_000001d3464130a0; + .scope S_0000017b113262a0; T_2 ; - %wait E_000001d3464b3cc0; - %load/vec4 v000001d34651ea90_0; + %wait E_0000017b113d2fe0; + %load/vec4 v0000017b1143f7b0_0; %cmpi/e 0, 0, 1; %jmp/0xz T_2.0, 4; - %load/vec4 v000001d34651fb70_0; - %store/vec4 v000001d34651ee50_0, 0, 32; + %load/vec4 v0000017b1143e9f0_0; + %store/vec4 v0000017b1143f710_0, 0, 32; %jmp T_2.1; T_2.0 ; - %load/vec4 v000001d34651e9f0_0; - %store/vec4 v000001d34651ee50_0, 0, 32; + %load/vec4 v0000017b1143f530_0; + %store/vec4 v0000017b1143f710_0, 0, 32; T_2.1 ; %jmp T_2; .thread T_2, $push; - .scope S_000001d346522e70; + .scope S_0000017b11442ce0; T_3 ; - %wait E_000001d3464b3e40; - %load/vec4 v000001d346521ea0_0; + %wait E_0000017b113d32a0; + %load/vec4 v0000017b11440be0_0; %flag_set/vec4 8; %jmp/0xz T_3.0, 8; %delay 1, 0; %pushi/vec4 0, 0, 32; - %assign/vec4 v000001d346520500_0, 0; + %assign/vec4 v0000017b11440460_0, 0; %jmp T_3.1; T_3.0 ; %delay 1, 0; - %load/vec4 v000001d346521360_0; - %assign/vec4 v000001d346520500_0, 0; + %load/vec4 v0000017b11441d60_0; + %assign/vec4 v0000017b11440460_0, 0; T_3.1 ; %jmp T_3; .thread T_3; - .scope S_000001d3464193f0; + .scope S_0000017b1139eb50; T_4 ; - %wait E_000001d3464b3e40; - %load/vec4 v000001d34651e6d0_0; + %wait E_0000017b113d32a0; + %load/vec4 v0000017b1143f670_0; %pad/u 32; %cmpi/e 1, 0, 32; %jmp/0xz T_4.0, 4; %delay 1, 0; %pushi/vec4 0, 0, 32; - %assign/vec4 v000001d34651ed10_0, 0; + %assign/vec4 v0000017b1143ed10_0, 0; %pushi/vec4 0, 0, 32; - %assign/vec4 v000001d34651f0d0_0, 0; + %assign/vec4 v0000017b1143fcb0_0, 0; %pushi/vec4 0, 0, 32; - %assign/vec4 v000001d34651f490_0, 0; + %assign/vec4 v0000017b1143fb70_0, 0; %jmp T_4.1; T_4.0 ; %delay 2, 0; - %load/vec4 v000001d34651f350_0; - %assign/vec4 v000001d34651ed10_0, 0; - %load/vec4 v000001d34651f3f0_0; - %assign/vec4 v000001d34651f0d0_0, 0; - %load/vec4 v000001d34651e630_0; - %assign/vec4 v000001d34651f490_0, 0; + %load/vec4 v0000017b1143e770_0; + %assign/vec4 v0000017b1143ed10_0, 0; + %load/vec4 v0000017b1143e270_0; + %assign/vec4 v0000017b1143fcb0_0, 0; + %load/vec4 v0000017b1143fad0_0; + %assign/vec4 v0000017b1143fb70_0, 0; T_4.1 ; %jmp T_4; .thread T_4; - .scope S_000001d34645f780; + .scope S_0000017b11332f10; T_5 ; - %wait E_000001d3464b37c0; + %wait E_0000017b113d30a0; %delay 1, 0; - %load/vec4 v000001d346520dc0_0; + %load/vec4 v0000017b11440780_0; %dup/vec4; %pushi/vec4 51, 0, 7; %cmp/u; @@ -622,27 +618,27 @@ T_5 ; %jmp T_5.9; T_5.0 ; %pushi/vec4 7, 7, 3; - %store/vec4 v000001d34651fcb0_0, 0, 3; + %store/vec4 v0000017b1143f030_0, 0, 3; %pushi/vec4 1, 0, 1; - %store/vec4 v000001d346520820_0, 0, 1; + %store/vec4 v0000017b11440f00_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651ff30_0, 0, 1; + %store/vec4 v0000017b1143e590_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651e450_0, 0, 1; + %store/vec4 v0000017b1143e450_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651ffd0_0, 0, 1; + %store/vec4 v0000017b1143e310_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651fe90_0, 0, 1; + %store/vec4 v0000017b1143edb0_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651ec70_0, 0, 1; + %store/vec4 v0000017b1143ea90_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651e8b0_0, 0, 1; + %store/vec4 v0000017b1143e4f0_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651fc10_0, 0, 1; + %store/vec4 v0000017b1143f8f0_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651e310_0, 0, 1; - %load/vec4 v000001d34651ebd0_0; - %load/vec4 v000001d34651eb30_0; + %store/vec4 v0000017b1143e1d0_0, 0, 1; + %load/vec4 v0000017b1143ff30_0; + %load/vec4 v0000017b1143fe90_0; %concat/vec4; draw_concat_vec4 %dup/vec4; %pushi/vec4 0, 0, 10; @@ -715,97 +711,97 @@ T_5.0 ; %jmp T_5.27; T_5.10 ; %pushi/vec4 0, 0, 5; - %store/vec4 v000001d34651ef90_0, 0, 5; + %store/vec4 v0000017b1143f850_0, 0, 5; %jmp T_5.27; T_5.11 ; %pushi/vec4 1, 0, 5; - %store/vec4 v000001d34651ef90_0, 0, 5; + %store/vec4 v0000017b1143f850_0, 0, 5; %jmp T_5.27; T_5.12 ; %pushi/vec4 2, 0, 5; - %store/vec4 v000001d34651ef90_0, 0, 5; + %store/vec4 v0000017b1143f850_0, 0, 5; %jmp T_5.27; T_5.13 ; %pushi/vec4 3, 0, 5; - %store/vec4 v000001d34651ef90_0, 0, 5; + %store/vec4 v0000017b1143f850_0, 0, 5; %jmp T_5.27; T_5.14 ; %pushi/vec4 4, 0, 5; - %store/vec4 v000001d34651ef90_0, 0, 5; + %store/vec4 v0000017b1143f850_0, 0, 5; %jmp T_5.27; T_5.15 ; %pushi/vec4 5, 0, 5; - %store/vec4 v000001d34651ef90_0, 0, 5; + %store/vec4 v0000017b1143f850_0, 0, 5; %jmp T_5.27; T_5.16 ; %pushi/vec4 6, 0, 5; - %store/vec4 v000001d34651ef90_0, 0, 5; + %store/vec4 v0000017b1143f850_0, 0, 5; %jmp T_5.27; T_5.17 ; %pushi/vec4 7, 0, 5; - %store/vec4 v000001d34651ef90_0, 0, 5; + %store/vec4 v0000017b1143f850_0, 0, 5; %jmp T_5.27; T_5.18 ; %pushi/vec4 8, 0, 5; - %store/vec4 v000001d34651ef90_0, 0, 5; + %store/vec4 v0000017b1143f850_0, 0, 5; %jmp T_5.27; T_5.19 ; %pushi/vec4 9, 0, 5; - %store/vec4 v000001d34651ef90_0, 0, 5; + %store/vec4 v0000017b1143f850_0, 0, 5; %jmp T_5.27; T_5.20 ; %pushi/vec4 10, 0, 5; - %store/vec4 v000001d34651ef90_0, 0, 5; + %store/vec4 v0000017b1143f850_0, 0, 5; %jmp T_5.27; T_5.21 ; %pushi/vec4 11, 0, 5; - %store/vec4 v000001d34651ef90_0, 0, 5; + %store/vec4 v0000017b1143f850_0, 0, 5; %jmp T_5.27; T_5.22 ; %pushi/vec4 12, 0, 5; - %store/vec4 v000001d34651ef90_0, 0, 5; + %store/vec4 v0000017b1143f850_0, 0, 5; %jmp T_5.27; T_5.23 ; %pushi/vec4 13, 0, 5; - %store/vec4 v000001d34651ef90_0, 0, 5; + %store/vec4 v0000017b1143f850_0, 0, 5; %jmp T_5.27; T_5.24 ; %pushi/vec4 14, 0, 5; - %store/vec4 v000001d34651ef90_0, 0, 5; + %store/vec4 v0000017b1143f850_0, 0, 5; %jmp T_5.27; T_5.25 ; %pushi/vec4 15, 0, 5; - %store/vec4 v000001d34651ef90_0, 0, 5; + %store/vec4 v0000017b1143f850_0, 0, 5; %jmp T_5.27; T_5.26 ; %pushi/vec4 16, 0, 5; - %store/vec4 v000001d34651ef90_0, 0, 5; + %store/vec4 v0000017b1143f850_0, 0, 5; %jmp T_5.27; T_5.27 ; %pop/vec4 1; %jmp T_5.9; T_5.1 ; %pushi/vec4 0, 0, 3; - %store/vec4 v000001d34651fcb0_0, 0, 3; + %store/vec4 v0000017b1143f030_0, 0, 3; %pushi/vec4 1, 0, 1; - %store/vec4 v000001d346520820_0, 0, 1; + %store/vec4 v0000017b11440f00_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651ff30_0, 0, 1; + %store/vec4 v0000017b1143e590_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651e450_0, 0, 1; + %store/vec4 v0000017b1143e450_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651ffd0_0, 0, 1; + %store/vec4 v0000017b1143e310_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651fe90_0, 0, 1; + %store/vec4 v0000017b1143edb0_0, 0, 1; %pushi/vec4 1, 0, 1; - %store/vec4 v000001d34651ec70_0, 0, 1; + %store/vec4 v0000017b1143ea90_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651e8b0_0, 0, 1; + %store/vec4 v0000017b1143e4f0_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651fc10_0, 0, 1; + %store/vec4 v0000017b1143f8f0_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651e310_0, 0, 1; - %load/vec4 v000001d34651eb30_0; + %store/vec4 v0000017b1143e1d0_0, 0, 1; + %load/vec4 v0000017b1143fe90_0; %dup/vec4; %pushi/vec4 0, 0, 3; %cmp/u; @@ -829,27 +825,27 @@ T_5.1 ; %jmp T_5.33; T_5.28 ; %pushi/vec4 0, 0, 5; - %store/vec4 v000001d34651ef90_0, 0, 5; + %store/vec4 v0000017b1143f850_0, 0, 5; %jmp T_5.33; T_5.29 ; %pushi/vec4 16, 0, 5; - %store/vec4 v000001d34651ef90_0, 0, 5; + %store/vec4 v0000017b1143f850_0, 0, 5; %jmp T_5.33; T_5.30 ; %pushi/vec4 4, 0, 5; - %store/vec4 v000001d34651ef90_0, 0, 5; + %store/vec4 v0000017b1143f850_0, 0, 5; %jmp T_5.33; T_5.31 ; %pushi/vec4 2, 0, 5; - %store/vec4 v000001d34651ef90_0, 0, 5; + %store/vec4 v0000017b1143f850_0, 0, 5; %jmp T_5.33; T_5.32 ; %pushi/vec4 3, 0, 5; - %store/vec4 v000001d34651ef90_0, 0, 5; + %store/vec4 v0000017b1143f850_0, 0, 5; %jmp T_5.33; T_5.33 ; %pop/vec4 1; - %load/vec4 v000001d34651ebd0_0; + %load/vec4 v0000017b1143ff30_0; %dup/vec4; %pushi/vec4 0, 0, 7; %cmp/u; @@ -860,7 +856,7 @@ T_5.33 ; %jmp/1 T_5.35, 6; %jmp T_5.36; T_5.34 ; - %load/vec4 v000001d34651eb30_0; + %load/vec4 v0000017b1143fe90_0; %dup/vec4; %pushi/vec4 1, 0, 3; %cmp/u; @@ -872,17 +868,17 @@ T_5.34 ; %jmp T_5.39; T_5.37 ; %pushi/vec4 6, 0, 5; - %store/vec4 v000001d34651ef90_0, 0, 5; + %store/vec4 v0000017b1143f850_0, 0, 5; %jmp T_5.39; T_5.38 ; %pushi/vec4 5, 0, 5; - %store/vec4 v000001d34651ef90_0, 0, 5; + %store/vec4 v0000017b1143f850_0, 0, 5; %jmp T_5.39; T_5.39 ; %pop/vec4 1; %jmp T_5.36; T_5.35 ; - %load/vec4 v000001d34651eb30_0; + %load/vec4 v0000017b1143fe90_0; %dup/vec4; %pushi/vec4 5, 0, 3; %cmp/u; @@ -890,7 +886,7 @@ T_5.35 ; %jmp T_5.41; T_5.40 ; %pushi/vec4 7, 0, 5; - %store/vec4 v000001d34651ef90_0, 0, 5; + %store/vec4 v0000017b1143f850_0, 0, 5; %jmp T_5.41; T_5.41 ; %pop/vec4 1; @@ -900,180 +896,180 @@ T_5.36 ; %jmp T_5.9; T_5.2 ; %pushi/vec4 0, 0, 3; - %store/vec4 v000001d34651fcb0_0, 0, 3; + %store/vec4 v0000017b1143f030_0, 0, 3; %pushi/vec4 1, 0, 1; - %store/vec4 v000001d346520820_0, 0, 1; + %store/vec4 v0000017b11440f00_0, 0, 1; %pushi/vec4 1, 0, 1; - %store/vec4 v000001d34651ff30_0, 0, 1; + %store/vec4 v0000017b1143e590_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651e450_0, 0, 1; + %store/vec4 v0000017b1143e450_0, 0, 1; %pushi/vec4 1, 0, 1; - %store/vec4 v000001d34651ffd0_0, 0, 1; + %store/vec4 v0000017b1143e310_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651fe90_0, 0, 1; + %store/vec4 v0000017b1143edb0_0, 0, 1; %pushi/vec4 1, 0, 1; - %store/vec4 v000001d34651ec70_0, 0, 1; + %store/vec4 v0000017b1143ea90_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651e8b0_0, 0, 1; + %store/vec4 v0000017b1143e4f0_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651fc10_0, 0, 1; + %store/vec4 v0000017b1143f8f0_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651e310_0, 0, 1; + %store/vec4 v0000017b1143e1d0_0, 0, 1; %pushi/vec4 0, 0, 5; - %store/vec4 v000001d34651ef90_0, 0, 5; + %store/vec4 v0000017b1143f850_0, 0, 5; %jmp T_5.9; T_5.3 ; %pushi/vec4 1, 0, 3; - %store/vec4 v000001d34651fcb0_0, 0, 3; + %store/vec4 v0000017b1143f030_0, 0, 3; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d346520820_0, 0, 1; + %store/vec4 v0000017b11440f00_0, 0, 1; %pushi/vec4 1, 0, 1; - %store/vec4 v000001d34651ff30_0, 0, 1; + %store/vec4 v0000017b1143e590_0, 0, 1; %pushi/vec4 1, 0, 1; - %store/vec4 v000001d34651e450_0, 0, 1; + %store/vec4 v0000017b1143e450_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651ffd0_0, 0, 1; + %store/vec4 v0000017b1143e310_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651fe90_0, 0, 1; + %store/vec4 v0000017b1143edb0_0, 0, 1; %pushi/vec4 1, 0, 1; - %store/vec4 v000001d34651ec70_0, 0, 1; + %store/vec4 v0000017b1143ea90_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651e8b0_0, 0, 1; + %store/vec4 v0000017b1143e4f0_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651fc10_0, 0, 1; + %store/vec4 v0000017b1143f8f0_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651e310_0, 0, 1; + %store/vec4 v0000017b1143e1d0_0, 0, 1; %pushi/vec4 0, 0, 5; - %store/vec4 v000001d34651ef90_0, 0, 5; + %store/vec4 v0000017b1143f850_0, 0, 5; %jmp T_5.9; T_5.4 ; %pushi/vec4 2, 0, 3; - %store/vec4 v000001d34651fcb0_0, 0, 3; + %store/vec4 v0000017b1143f030_0, 0, 3; %pushi/vec4 1, 0, 1; - %store/vec4 v000001d346520820_0, 0, 1; + %store/vec4 v0000017b11440f00_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651ff30_0, 0, 1; + %store/vec4 v0000017b1143e590_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651e450_0, 0, 1; + %store/vec4 v0000017b1143e450_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651ffd0_0, 0, 1; + %store/vec4 v0000017b1143e310_0, 0, 1; %pushi/vec4 1, 0, 1; - %store/vec4 v000001d34651fe90_0, 0, 1; + %store/vec4 v0000017b1143edb0_0, 0, 1; %pushi/vec4 1, 0, 1; - %store/vec4 v000001d34651ec70_0, 0, 1; + %store/vec4 v0000017b1143ea90_0, 0, 1; %pushi/vec4 1, 0, 1; - %store/vec4 v000001d34651e8b0_0, 0, 1; + %store/vec4 v0000017b1143e4f0_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651fc10_0, 0, 1; + %store/vec4 v0000017b1143f8f0_0, 0, 1; %pushi/vec4 1, 0, 1; - %store/vec4 v000001d34651e310_0, 0, 1; + %store/vec4 v0000017b1143e1d0_0, 0, 1; %pushi/vec4 0, 0, 5; - %store/vec4 v000001d34651ef90_0, 0, 5; + %store/vec4 v0000017b1143f850_0, 0, 5; %jmp T_5.9; T_5.5 ; %pushi/vec4 0, 0, 3; - %store/vec4 v000001d34651fcb0_0, 0, 3; + %store/vec4 v0000017b1143f030_0, 0, 3; %pushi/vec4 1, 0, 1; - %store/vec4 v000001d346520820_0, 0, 1; + %store/vec4 v0000017b11440f00_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651ff30_0, 0, 1; + %store/vec4 v0000017b1143e590_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651e450_0, 0, 1; + %store/vec4 v0000017b1143e450_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651ffd0_0, 0, 1; + %store/vec4 v0000017b1143e310_0, 0, 1; %pushi/vec4 1, 0, 1; - %store/vec4 v000001d34651fe90_0, 0, 1; + %store/vec4 v0000017b1143edb0_0, 0, 1; %pushi/vec4 1, 0, 1; - %store/vec4 v000001d34651ec70_0, 0, 1; + %store/vec4 v0000017b1143ea90_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651e8b0_0, 0, 1; + %store/vec4 v0000017b1143e4f0_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651fc10_0, 0, 1; + %store/vec4 v0000017b1143f8f0_0, 0, 1; %pushi/vec4 1, 0, 1; - %store/vec4 v000001d34651e310_0, 0, 1; + %store/vec4 v0000017b1143e1d0_0, 0, 1; %pushi/vec4 0, 0, 5; - %store/vec4 v000001d34651ef90_0, 0, 5; + %store/vec4 v0000017b1143f850_0, 0, 5; %jmp T_5.9; T_5.6 ; %pushi/vec4 3, 0, 3; - %store/vec4 v000001d34651fcb0_0, 0, 3; + %store/vec4 v0000017b1143f030_0, 0, 3; %pushi/vec4 1, 0, 1; - %store/vec4 v000001d346520820_0, 0, 1; + %store/vec4 v0000017b11440f00_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651ff30_0, 0, 1; + %store/vec4 v0000017b1143e590_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651e450_0, 0, 1; + %store/vec4 v0000017b1143e450_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651ffd0_0, 0, 1; + %store/vec4 v0000017b1143e310_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651fe90_0, 0, 1; + %store/vec4 v0000017b1143edb0_0, 0, 1; %pushi/vec4 1, 0, 1; - %store/vec4 v000001d34651ec70_0, 0, 1; + %store/vec4 v0000017b1143ea90_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651e8b0_0, 0, 1; + %store/vec4 v0000017b1143e4f0_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651fc10_0, 0, 1; + %store/vec4 v0000017b1143f8f0_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651e310_0, 0, 1; + %store/vec4 v0000017b1143e1d0_0, 0, 1; %pushi/vec4 17, 0, 5; - %store/vec4 v000001d34651ef90_0, 0, 5; + %store/vec4 v0000017b1143f850_0, 0, 5; %jmp T_5.9; T_5.7 ; %pushi/vec4 3, 0, 3; - %store/vec4 v000001d34651fcb0_0, 0, 3; + %store/vec4 v0000017b1143f030_0, 0, 3; %pushi/vec4 1, 0, 1; - %store/vec4 v000001d346520820_0, 0, 1; + %store/vec4 v0000017b11440f00_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651ff30_0, 0, 1; + %store/vec4 v0000017b1143e590_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651e450_0, 0, 1; + %store/vec4 v0000017b1143e450_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651ffd0_0, 0, 1; + %store/vec4 v0000017b1143e310_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651fe90_0, 0, 1; + %store/vec4 v0000017b1143edb0_0, 0, 1; %pushi/vec4 1, 0, 1; - %store/vec4 v000001d34651ec70_0, 0, 1; + %store/vec4 v0000017b1143ea90_0, 0, 1; %pushi/vec4 1, 0, 1; - %store/vec4 v000001d34651e8b0_0, 0, 1; + %store/vec4 v0000017b1143e4f0_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651fc10_0, 0, 1; + %store/vec4 v0000017b1143f8f0_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651e310_0, 0, 1; + %store/vec4 v0000017b1143e1d0_0, 0, 1; %pushi/vec4 0, 0, 5; - %store/vec4 v000001d34651ef90_0, 0, 5; + %store/vec4 v0000017b1143f850_0, 0, 5; %jmp T_5.9; T_5.8 ; %pushi/vec4 4, 0, 3; - %store/vec4 v000001d34651fcb0_0, 0, 3; + %store/vec4 v0000017b1143f030_0, 0, 3; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d346520820_0, 0, 1; + %store/vec4 v0000017b11440f00_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651ff30_0, 0, 1; + %store/vec4 v0000017b1143e590_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651e450_0, 0, 1; + %store/vec4 v0000017b1143e450_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651ffd0_0, 0, 1; + %store/vec4 v0000017b1143e310_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651fe90_0, 0, 1; + %store/vec4 v0000017b1143edb0_0, 0, 1; %pushi/vec4 1, 0, 1; - %store/vec4 v000001d34651ec70_0, 0, 1; + %store/vec4 v0000017b1143ea90_0, 0, 1; %pushi/vec4 1, 0, 1; - %store/vec4 v000001d34651e8b0_0, 0, 1; + %store/vec4 v0000017b1143e4f0_0, 0, 1; %pushi/vec4 1, 0, 1; - %store/vec4 v000001d34651fc10_0, 0, 1; + %store/vec4 v0000017b1143f8f0_0, 0, 1; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34651e310_0, 0, 1; + %store/vec4 v0000017b1143e1d0_0, 0, 1; %pushi/vec4 0, 0, 5; - %store/vec4 v000001d34651ef90_0, 0, 5; + %store/vec4 v0000017b1143f850_0, 0, 5; %jmp T_5.9; T_5.9 ; %pop/vec4 1; %jmp T_5; .thread T_5, $push; - .scope S_000001d346522380; + .scope S_0000017b11442830; T_6 ; - %wait E_000001d3464b3e40; - %load/vec4 v000001d346520be0_0; + %wait E_0000017b113d32a0; + %load/vec4 v0000017b11441720_0; %flag_set/vec4 8; %jmp/0xz T_6.0, 8; %delay 1, 0; @@ -1081,164 +1077,164 @@ T_6 ; %ix/load 3, 1, 0; %flag_set/imm 4, 0; %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v000001d3465205a0, 0, 4; + %assign/vec4/a/d v0000017b11441ea0, 0, 4; %pushi/vec4 0, 0, 32; %ix/load 3, 2, 0; %flag_set/imm 4, 0; %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v000001d3465205a0, 0, 4; + %assign/vec4/a/d v0000017b11441ea0, 0, 4; %pushi/vec4 0, 0, 32; %ix/load 3, 3, 0; %flag_set/imm 4, 0; %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v000001d3465205a0, 0, 4; + %assign/vec4/a/d v0000017b11441ea0, 0, 4; %pushi/vec4 0, 0, 32; %ix/load 3, 4, 0; %flag_set/imm 4, 0; %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v000001d3465205a0, 0, 4; + %assign/vec4/a/d v0000017b11441ea0, 0, 4; %pushi/vec4 0, 0, 32; %ix/load 3, 5, 0; %flag_set/imm 4, 0; %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v000001d3465205a0, 0, 4; + %assign/vec4/a/d v0000017b11441ea0, 0, 4; %pushi/vec4 0, 0, 32; %ix/load 3, 6, 0; %flag_set/imm 4, 0; %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v000001d3465205a0, 0, 4; + %assign/vec4/a/d v0000017b11441ea0, 0, 4; %pushi/vec4 0, 0, 32; %ix/load 3, 7, 0; %flag_set/imm 4, 0; %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v000001d3465205a0, 0, 4; + %assign/vec4/a/d v0000017b11441ea0, 0, 4; %pushi/vec4 0, 0, 32; %ix/load 3, 8, 0; %flag_set/imm 4, 0; %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v000001d3465205a0, 0, 4; + %assign/vec4/a/d v0000017b11441ea0, 0, 4; %pushi/vec4 0, 0, 32; %ix/load 3, 9, 0; %flag_set/imm 4, 0; %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v000001d3465205a0, 0, 4; + %assign/vec4/a/d v0000017b11441ea0, 0, 4; %pushi/vec4 0, 0, 32; %ix/load 3, 10, 0; %flag_set/imm 4, 0; %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v000001d3465205a0, 0, 4; + %assign/vec4/a/d v0000017b11441ea0, 0, 4; %pushi/vec4 0, 0, 32; %ix/load 3, 11, 0; %flag_set/imm 4, 0; %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v000001d3465205a0, 0, 4; + %assign/vec4/a/d v0000017b11441ea0, 0, 4; %pushi/vec4 0, 0, 32; %ix/load 3, 12, 0; %flag_set/imm 4, 0; %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v000001d3465205a0, 0, 4; + %assign/vec4/a/d v0000017b11441ea0, 0, 4; %pushi/vec4 0, 0, 32; %ix/load 3, 13, 0; %flag_set/imm 4, 0; %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v000001d3465205a0, 0, 4; + %assign/vec4/a/d v0000017b11441ea0, 0, 4; %pushi/vec4 0, 0, 32; %ix/load 3, 14, 0; %flag_set/imm 4, 0; %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v000001d3465205a0, 0, 4; + %assign/vec4/a/d v0000017b11441ea0, 0, 4; %pushi/vec4 0, 0, 32; %ix/load 3, 15, 0; %flag_set/imm 4, 0; %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v000001d3465205a0, 0, 4; + %assign/vec4/a/d v0000017b11441ea0, 0, 4; %pushi/vec4 0, 0, 32; %ix/load 3, 16, 0; %flag_set/imm 4, 0; %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v000001d3465205a0, 0, 4; + %assign/vec4/a/d v0000017b11441ea0, 0, 4; %pushi/vec4 0, 0, 32; %ix/load 3, 17, 0; %flag_set/imm 4, 0; %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v000001d3465205a0, 0, 4; + %assign/vec4/a/d v0000017b11441ea0, 0, 4; %pushi/vec4 0, 0, 32; %ix/load 3, 18, 0; %flag_set/imm 4, 0; %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v000001d3465205a0, 0, 4; + %assign/vec4/a/d v0000017b11441ea0, 0, 4; %pushi/vec4 0, 0, 32; %ix/load 3, 19, 0; %flag_set/imm 4, 0; %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v000001d3465205a0, 0, 4; + %assign/vec4/a/d v0000017b11441ea0, 0, 4; %pushi/vec4 0, 0, 32; %ix/load 3, 20, 0; %flag_set/imm 4, 0; %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v000001d3465205a0, 0, 4; + %assign/vec4/a/d v0000017b11441ea0, 0, 4; %pushi/vec4 0, 0, 32; %ix/load 3, 21, 0; %flag_set/imm 4, 0; %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v000001d3465205a0, 0, 4; + %assign/vec4/a/d v0000017b11441ea0, 0, 4; %pushi/vec4 0, 0, 32; %ix/load 3, 22, 0; %flag_set/imm 4, 0; %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v000001d3465205a0, 0, 4; + %assign/vec4/a/d v0000017b11441ea0, 0, 4; %pushi/vec4 0, 0, 32; %ix/load 3, 23, 0; %flag_set/imm 4, 0; %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v000001d3465205a0, 0, 4; + %assign/vec4/a/d v0000017b11441ea0, 0, 4; %pushi/vec4 0, 0, 32; %ix/load 3, 24, 0; %flag_set/imm 4, 0; %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v000001d3465205a0, 0, 4; + %assign/vec4/a/d v0000017b11441ea0, 0, 4; %pushi/vec4 0, 0, 32; %ix/load 3, 25, 0; %flag_set/imm 4, 0; %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v000001d3465205a0, 0, 4; + %assign/vec4/a/d v0000017b11441ea0, 0, 4; %pushi/vec4 0, 0, 32; %ix/load 3, 26, 0; %flag_set/imm 4, 0; %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v000001d3465205a0, 0, 4; + %assign/vec4/a/d v0000017b11441ea0, 0, 4; %pushi/vec4 0, 0, 32; %ix/load 3, 27, 0; %flag_set/imm 4, 0; %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v000001d3465205a0, 0, 4; + %assign/vec4/a/d v0000017b11441ea0, 0, 4; %pushi/vec4 0, 0, 32; %ix/load 3, 28, 0; %flag_set/imm 4, 0; %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v000001d3465205a0, 0, 4; + %assign/vec4/a/d v0000017b11441ea0, 0, 4; %pushi/vec4 0, 0, 32; %ix/load 3, 29, 0; %flag_set/imm 4, 0; %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v000001d3465205a0, 0, 4; + %assign/vec4/a/d v0000017b11441ea0, 0, 4; %pushi/vec4 0, 0, 32; %ix/load 3, 30, 0; %flag_set/imm 4, 0; %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v000001d3465205a0, 0, 4; + %assign/vec4/a/d v0000017b11441ea0, 0, 4; %pushi/vec4 0, 0, 32; %ix/load 3, 31, 0; %flag_set/imm 4, 0; %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v000001d3465205a0, 0, 4; + %assign/vec4/a/d v0000017b11441ea0, 0, 4; %jmp T_6.1; T_6.0 ; - %load/vec4 v000001d3465201e0_0; + %load/vec4 v0000017b11440d20_0; %flag_set/vec4 9; %flag_get/vec4 9; %jmp/0 T_6.4, 9; - %load/vec4 v000001d346521d60_0; + %load/vec4 v0000017b11441900_0; %pushi/vec4 0, 0, 5; %cmp/ne; %flag_get/vec4 4; @@ -1247,37 +1243,37 @@ T_6.4; %flag_set/vec4 8; %jmp/0xz T_6.2, 8; %delay 1, 0; - %load/vec4 v000001d3465210e0_0; - %load/vec4 v000001d346521d60_0; + %load/vec4 v0000017b11440c80_0; + %load/vec4 v0000017b11441900_0; %pad/u 7; %ix/vec4 3; %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v000001d3465205a0, 0, 4; + %assign/vec4/a/d v0000017b11441ea0, 0, 4; T_6.2 ; T_6.1 ; %jmp T_6; .thread T_6; - .scope S_000001d346522380; + .scope S_0000017b11442830; T_7 ; - %wait E_000001d3464b3f40; + %wait E_0000017b113d3560; %delay 2, 0; - %load/vec4 v000001d346521400_0; + %load/vec4 v0000017b11440500_0; %pad/u 7; %ix/vec4 4; - %load/vec4a v000001d3465205a0, 4; - %assign/vec4 v000001d346520b40_0, 0; - %load/vec4 v000001d346522080_0; + %load/vec4a v0000017b11441ea0, 4; + %assign/vec4 v0000017b11440aa0_0, 0; + %load/vec4 v0000017b11441fe0_0; %pad/u 7; %ix/vec4 4; - %load/vec4a v000001d3465205a0, 4; - %assign/vec4 v000001d346521c20_0, 0; + %load/vec4a v0000017b11441ea0, 4; + %assign/vec4 v0000017b11441540_0, 0; %jmp T_7; .thread T_7, $push; - .scope S_000001d34644ebe0; + .scope S_0000017b1137f780; T_8 ; - %wait E_000001d3464b3380; + %wait E_0000017b113d3120; %delay 2, 0; - %load/vec4 v000001d346521220_0; + %load/vec4 v0000017b114403c0_0; %dup/vec4; %pushi/vec4 0, 0, 3; %cmp/u; @@ -1300,204 +1296,204 @@ T_8 ; %jmp/1 T_8.4, 6; %jmp T_8.5; T_8.0 ; - %load/vec4 v000001d346520460_0; + %load/vec4 v0000017b11441c20_0; %parti/s 1, 31, 6; %replicate 21; - %load/vec4 v000001d346520460_0; + %load/vec4 v0000017b11441c20_0; %parti/s 6, 25, 6; %concat/vec4; draw_concat_vec4 - %load/vec4 v000001d346520460_0; + %load/vec4 v0000017b11441c20_0; %parti/s 4, 21, 6; %concat/vec4; draw_concat_vec4 - %load/vec4 v000001d346520460_0; + %load/vec4 v0000017b11441c20_0; %parti/s 1, 20, 6; %concat/vec4; draw_concat_vec4 - %store/vec4 v000001d3465217c0_0, 0, 32; + %store/vec4 v0000017b11440820_0, 0, 32; %jmp T_8.5; T_8.1 ; - %load/vec4 v000001d346520460_0; + %load/vec4 v0000017b11441c20_0; %parti/s 1, 31, 6; %replicate 21; - %load/vec4 v000001d346520460_0; + %load/vec4 v0000017b11441c20_0; %parti/s 6, 25, 6; %concat/vec4; draw_concat_vec4 - %load/vec4 v000001d346520460_0; + %load/vec4 v0000017b11441c20_0; %parti/s 4, 8, 5; %concat/vec4; draw_concat_vec4 - %load/vec4 v000001d346520460_0; + %load/vec4 v0000017b11441c20_0; %parti/s 1, 7, 4; %concat/vec4; draw_concat_vec4 - %store/vec4 v000001d3465217c0_0, 0, 32; + %store/vec4 v0000017b11440820_0, 0, 32; %jmp T_8.5; T_8.2 ; - %load/vec4 v000001d346520460_0; + %load/vec4 v0000017b11441c20_0; %parti/s 1, 31, 6; %replicate 12; - %load/vec4 v000001d346520460_0; + %load/vec4 v0000017b11441c20_0; %parti/s 8, 12, 5; %concat/vec4; draw_concat_vec4 - %load/vec4 v000001d346520460_0; + %load/vec4 v0000017b11441c20_0; %parti/s 1, 20, 6; %concat/vec4; draw_concat_vec4 - %load/vec4 v000001d346520460_0; + %load/vec4 v0000017b11441c20_0; %parti/s 6, 25, 6; %concat/vec4; draw_concat_vec4 - %load/vec4 v000001d346520460_0; + %load/vec4 v0000017b11441c20_0; %parti/s 4, 21, 6; %concat/vec4; draw_concat_vec4 %concati/vec4 0, 0, 1; - %store/vec4 v000001d3465217c0_0, 0, 32; + %store/vec4 v0000017b11440820_0, 0, 32; %jmp T_8.5; T_8.3 ; - %load/vec4 v000001d346520460_0; + %load/vec4 v0000017b11441c20_0; %parti/s 1, 31, 6; - %load/vec4 v000001d346520460_0; + %load/vec4 v0000017b11441c20_0; %parti/s 11, 20, 6; %concat/vec4; draw_concat_vec4 - %load/vec4 v000001d346520460_0; + %load/vec4 v0000017b11441c20_0; %parti/s 8, 12, 5; %concat/vec4; draw_concat_vec4 %concati/vec4 0, 0, 12; - %store/vec4 v000001d3465217c0_0, 0, 32; + %store/vec4 v0000017b11440820_0, 0, 32; %jmp T_8.5; T_8.4 ; - %load/vec4 v000001d346520460_0; + %load/vec4 v0000017b11441c20_0; %parti/s 1, 31, 6; %replicate 20; - %load/vec4 v000001d346520460_0; + %load/vec4 v0000017b11441c20_0; %parti/s 1, 7, 4; %concat/vec4; draw_concat_vec4 - %load/vec4 v000001d346520460_0; + %load/vec4 v0000017b11441c20_0; %parti/s 6, 25, 6; %concat/vec4; draw_concat_vec4 - %load/vec4 v000001d346520460_0; + %load/vec4 v0000017b11441c20_0; %parti/s 4, 8, 5; %concat/vec4; draw_concat_vec4 %concati/vec4 0, 0, 1; - %store/vec4 v000001d3465217c0_0, 0, 32; + %store/vec4 v0000017b11440820_0, 0, 32; %jmp T_8.5; T_8.5 ; %pop/vec4 1; %jmp T_8; .thread T_8, $push; - .scope S_000001d34647e940; + .scope S_0000017b11354980; T_9 ; - %wait E_000001d3464b3e40; - %load/vec4 v000001d34651f210_0; + %wait E_0000017b113d32a0; + %load/vec4 v0000017b11440070_0; %pad/u 32; %cmpi/e 1, 0, 32; %jmp/0xz T_9.0, 4; %delay 1, 0; %pushi/vec4 1, 1, 1; - %assign/vec4 v000001d34651c6f0_0, 0; + %assign/vec4 v0000017b1143c830_0, 0; %pushi/vec4 1, 1, 1; - %assign/vec4 v000001d34651b9d0_0, 0; + %assign/vec4 v0000017b1143ca10_0, 0; %pushi/vec4 1, 1, 1; - %assign/vec4 v000001d34651b930_0, 0; + %assign/vec4 v0000017b1143bd90_0, 0; %pushi/vec4 1, 1, 1; - %assign/vec4 v000001d34651b890_0, 0; + %assign/vec4 v0000017b1143bcf0_0, 0; %pushi/vec4 1, 1, 1; - %assign/vec4 v000001d34651c510_0, 0; + %assign/vec4 v0000017b1143cf10_0, 0; %pushi/vec4 1, 1, 1; - %assign/vec4 v000001d34651c1f0_0, 0; + %assign/vec4 v0000017b1143c290_0, 0; %pushi/vec4 1, 1, 1; - %assign/vec4 v000001d34651bd90_0, 0; + %assign/vec4 v0000017b1143bf70_0, 0; %pushi/vec4 1, 1, 1; - %assign/vec4 v000001d34651bbb0_0, 0; + %assign/vec4 v0000017b1143ba70_0, 0; %pushi/vec4 1, 1, 1; - %assign/vec4 v000001d34651c3d0_0, 0; + %assign/vec4 v0000017b1143ce70_0, 0; %pushi/vec4 31, 31, 5; - %assign/vec4 v000001d34651c470_0, 0; + %assign/vec4 v0000017b1143b9d0_0, 0; %pushi/vec4 4294967295, 4294967295, 32; - %assign/vec4 v000001d34651be30_0, 0; + %assign/vec4 v0000017b1143c1f0_0, 0; %pushi/vec4 4294967295, 4294967295, 32; - %assign/vec4 v000001d34651c650_0, 0; + %assign/vec4 v0000017b1143c6f0_0, 0; %pushi/vec4 4294967295, 4294967295, 32; - %assign/vec4 v000001d34651bc50_0, 0; + %assign/vec4 v0000017b1143cc90_0, 0; %pushi/vec4 4294967295, 4294967295, 32; - %assign/vec4 v000001d34651b610_0, 0; + %assign/vec4 v0000017b1143bc50_0, 0; %pushi/vec4 31, 31, 5; - %assign/vec4 v000001d34651c970_0, 0; + %assign/vec4 v0000017b1143c3d0_0, 0; %pushi/vec4 7, 7, 3; - %assign/vec4 v000001d34651c790_0, 0; + %assign/vec4 v0000017b1143c8d0_0, 0; %pushi/vec4 4294967295, 4294967295, 32; - %assign/vec4 v000001d34651b750_0, 0; + %assign/vec4 v0000017b1143c790_0, 0; %jmp T_9.1; T_9.0 ; %delay 2, 0; - %load/vec4 v000001d34651e590_0; - %assign/vec4 v000001d34651c6f0_0, 0; - %load/vec4 v000001d34651b570_0; - %assign/vec4 v000001d34651b9d0_0, 0; - %load/vec4 v000001d34651b4d0_0; - %assign/vec4 v000001d34651b930_0, 0; - %load/vec4 v000001d34651b430_0; - %assign/vec4 v000001d34651b890_0, 0; - %load/vec4 v000001d34651cf10_0; - %assign/vec4 v000001d34651c510_0, 0; - %load/vec4 v000001d34651bf70_0; - %assign/vec4 v000001d34651c1f0_0, 0; - %load/vec4 v000001d34651c150_0; - %assign/vec4 v000001d34651bd90_0, 0; - %load/vec4 v000001d34651b390_0; - %assign/vec4 v000001d34651bbb0_0, 0; - %load/vec4 v000001d34651c290_0; - %assign/vec4 v000001d34651c3d0_0, 0; - %load/vec4 v000001d34651cb50_0; - %assign/vec4 v000001d34651c470_0, 0; - %load/vec4 v000001d34651e950_0; - %assign/vec4 v000001d34651be30_0, 0; - %load/vec4 v000001d34651e4f0_0; - %assign/vec4 v000001d34651c650_0, 0; - %load/vec4 v000001d34651bcf0_0; - %assign/vec4 v000001d34651bc50_0, 0; - %load/vec4 v000001d34651bb10_0; - %assign/vec4 v000001d34651b610_0, 0; - %load/vec4 v000001d34651e810_0; + %load/vec4 v0000017b1143ee50_0; + %assign/vec4 v0000017b1143c830_0, 0; + %load/vec4 v0000017b1143b4d0_0; + %assign/vec4 v0000017b1143ca10_0, 0; + %load/vec4 v0000017b1143c5b0_0; + %assign/vec4 v0000017b1143bd90_0, 0; + %load/vec4 v0000017b1143b750_0; + %assign/vec4 v0000017b1143bcf0_0, 0; + %load/vec4 v0000017b1143c330_0; + %assign/vec4 v0000017b1143cf10_0, 0; + %load/vec4 v0000017b1143c150_0; + %assign/vec4 v0000017b1143c290_0, 0; + %load/vec4 v0000017b1143cbf0_0; + %assign/vec4 v0000017b1143bf70_0, 0; + %load/vec4 v0000017b1143bed0_0; + %assign/vec4 v0000017b1143ba70_0, 0; + %load/vec4 v0000017b1143b430_0; + %assign/vec4 v0000017b1143ce70_0, 0; + %load/vec4 v0000017b1143c650_0; + %assign/vec4 v0000017b1143b9d0_0, 0; + %load/vec4 v0000017b1143e6d0_0; + %assign/vec4 v0000017b1143c1f0_0, 0; + %load/vec4 v0000017b1143e3b0_0; + %assign/vec4 v0000017b1143c6f0_0, 0; + %load/vec4 v0000017b1143bbb0_0; + %assign/vec4 v0000017b1143cc90_0, 0; + %load/vec4 v0000017b1143b1b0_0; + %assign/vec4 v0000017b1143bc50_0, 0; + %load/vec4 v0000017b1143eb30_0; %parti/s 5, 7, 4; - %assign/vec4 v000001d34651c970_0, 0; - %load/vec4 v000001d34651e810_0; + %assign/vec4 v0000017b1143c3d0_0, 0; + %load/vec4 v0000017b1143eb30_0; %parti/s 3, 12, 5; - %assign/vec4 v000001d34651c790_0, 0; - %load/vec4 v000001d34651ce70_0; - %assign/vec4 v000001d34651b750_0, 0; + %assign/vec4 v0000017b1143c8d0_0, 0; + %load/vec4 v0000017b1143cd30_0; + %assign/vec4 v0000017b1143c790_0, 0; T_9.1 ; %jmp T_9; .thread T_9; - .scope S_000001d346452210; + .scope S_0000017b11330070; T_10 ; - %wait E_000001d3464b2d40; - %load/vec4 v000001d3464c0710_0; + %wait E_0000017b113d3220; + %load/vec4 v0000017b113e0e90_0; %cmpi/e 0, 0, 1; %jmp/0xz T_10.0, 4; - %load/vec4 v000001d3464c0210_0; - %store/vec4 v000001d3464c0670_0, 0, 32; + %load/vec4 v0000017b113e0530_0; + %store/vec4 v0000017b113e0d50_0, 0, 32; %jmp T_10.1; T_10.0 ; - %load/vec4 v000001d3464c0350_0; - %store/vec4 v000001d3464c0670_0, 0, 32; + %load/vec4 v0000017b113e0990_0; + %store/vec4 v0000017b113e0d50_0, 0, 32; T_10.1 ; %jmp T_10; .thread T_10, $push; - .scope S_000001d346434980; + .scope S_0000017b11372080; T_11 ; - %wait E_000001d3464b3600; - %load/vec4 v000001d34651c8d0_0; + %wait E_0000017b113d35e0; + %load/vec4 v0000017b1143b7f0_0; %cmpi/e 0, 0, 1; %jmp/0xz T_11.0, 4; - %load/vec4 v000001d3464c0b70_0; - %store/vec4 v000001d34649f120_0, 0, 32; + %load/vec4 v0000017b113e0fd0_0; + %store/vec4 v0000017b113bf400_0, 0, 32; %jmp T_11.1; T_11.0 ; - %load/vec4 v000001d34649f6c0_0; - %store/vec4 v000001d34649f120_0, 0, 32; + %load/vec4 v0000017b113bef00_0; + %store/vec4 v0000017b113bf400_0, 0, 32; T_11.1 ; %jmp T_11; .thread T_11, $push; - .scope S_000001d346410070; + .scope S_0000017b113ded40; T_12 ; - %wait E_000001d3464b1000; - %load/vec4 v000001d3464c0850_0; + %wait E_0000017b113d12e0; + %load/vec4 v0000017b113e1d90_0; %dup/vec4; %pushi/vec4 0, 0, 5; %cmp/u; @@ -1572,118 +1568,118 @@ T_12 ; %jmp/1 T_12.17, 6; %delay 1, 0; %pushi/vec4 0, 0, 32; - %store/vec4 v000001d3464c08f0_0, 0, 32; + %store/vec4 v0000017b113e1750_0, 0, 32; %jmp T_12.19; T_12.0 ; %delay 2, 0; - %load/vec4 v000001d3464c17f0_0; - %load/vec4 v000001d3464c0cb0_0; + %load/vec4 v0000017b113e1cf0_0; + %load/vec4 v0000017b113e0b70_0; %add; - %store/vec4 v000001d3464c08f0_0, 0, 32; + %store/vec4 v0000017b113e1750_0, 0, 32; %jmp T_12.19; T_12.1 ; %delay 2, 0; - %load/vec4 v000001d3464c17f0_0; - %load/vec4 v000001d3464c0cb0_0; + %load/vec4 v0000017b113e1cf0_0; + %load/vec4 v0000017b113e0b70_0; %sub; - %store/vec4 v000001d3464c08f0_0, 0, 32; + %store/vec4 v0000017b113e1750_0, 0, 32; %jmp T_12.19; T_12.2 ; %delay 1, 0; - %load/vec4 v000001d3464c17f0_0; - %load/vec4 v000001d3464c0cb0_0; + %load/vec4 v0000017b113e1cf0_0; + %load/vec4 v0000017b113e0b70_0; %or; - %store/vec4 v000001d3464c08f0_0, 0, 32; + %store/vec4 v0000017b113e1750_0, 0, 32; %jmp T_12.19; T_12.3 ; %delay 1, 0; - %load/vec4 v000001d3464c17f0_0; - %load/vec4 v000001d3464c0cb0_0; + %load/vec4 v0000017b113e1cf0_0; + %load/vec4 v0000017b113e0b70_0; %xor; - %store/vec4 v000001d3464c08f0_0, 0, 32; + %store/vec4 v0000017b113e1750_0, 0, 32; %jmp T_12.19; T_12.4 ; %delay 1, 0; - %load/vec4 v000001d3464c17f0_0; - %load/vec4 v000001d3464c0cb0_0; + %load/vec4 v0000017b113e1cf0_0; + %load/vec4 v0000017b113e0b70_0; %and; - %store/vec4 v000001d3464c08f0_0, 0, 32; + %store/vec4 v0000017b113e1750_0, 0, 32; %jmp T_12.19; T_12.5 ; %delay 2, 0; - %load/vec4 v000001d3464c17f0_0; - %ix/getv 4, v000001d3464c0cb0_0; + %load/vec4 v0000017b113e1cf0_0; + %ix/getv 4, v0000017b113e0b70_0; %shiftr 4; - %store/vec4 v000001d3464c08f0_0, 0, 32; + %store/vec4 v0000017b113e1750_0, 0, 32; %jmp T_12.19; T_12.6 ; %delay 2, 0; - %load/vec4 v000001d3464c17f0_0; - %ix/getv 4, v000001d3464c0cb0_0; + %load/vec4 v0000017b113e1cf0_0; + %ix/getv 4, v0000017b113e0b70_0; %shiftl 4; - %store/vec4 v000001d3464c08f0_0, 0, 32; + %store/vec4 v0000017b113e1750_0, 0, 32; %jmp T_12.19; T_12.7 ; %delay 2, 0; - %load/vec4 v000001d3464c17f0_0; - %ix/getv 4, v000001d3464c0cb0_0; + %load/vec4 v0000017b113e1cf0_0; + %ix/getv 4, v0000017b113e0b70_0; %shiftr 4; - %store/vec4 v000001d3464c08f0_0, 0, 32; + %store/vec4 v0000017b113e1750_0, 0, 32; %jmp T_12.19; T_12.8 ; %delay 3, 0; - %load/vec4 v000001d3464c17f0_0; - %load/vec4 v000001d3464c0cb0_0; + %load/vec4 v0000017b113e1cf0_0; + %load/vec4 v0000017b113e0b70_0; %mul; - %store/vec4 v000001d3464c08f0_0, 0, 32; + %store/vec4 v0000017b113e1750_0, 0, 32; %jmp T_12.19; T_12.9 ; %delay 3, 0; - %load/vec4 v000001d3464c1430_0; - %store/vec4 v000001d3464c08f0_0, 0, 32; + %load/vec4 v0000017b113e1b10_0; + %store/vec4 v0000017b113e1750_0, 0, 32; %jmp T_12.19; T_12.10 ; %delay 3, 0; - %load/vec4 v000001d3464c11b0_0; - %store/vec4 v000001d3464c08f0_0, 0, 32; + %load/vec4 v0000017b113e0490_0; + %store/vec4 v0000017b113e1750_0, 0, 32; %jmp T_12.19; T_12.11 ; %delay 3, 0; - %load/vec4 v000001d3464c1390_0; - %store/vec4 v000001d3464c08f0_0, 0, 32; + %load/vec4 v0000017b113e1250_0; + %store/vec4 v0000017b113e1750_0, 0, 32; %jmp T_12.19; T_12.12 ; %delay 3, 0; - %load/vec4 v000001d3464c17f0_0; - %load/vec4 v000001d3464c0cb0_0; + %load/vec4 v0000017b113e1cf0_0; + %load/vec4 v0000017b113e0b70_0; %div/s; - %store/vec4 v000001d3464c08f0_0, 0, 32; + %store/vec4 v0000017b113e1750_0, 0, 32; %jmp T_12.19; T_12.13 ; %delay 3, 0; - %load/vec4 v000001d3464c17f0_0; - %load/vec4 v000001d3464c0cb0_0; + %load/vec4 v0000017b113e1cf0_0; + %load/vec4 v0000017b113e0b70_0; %div; - %store/vec4 v000001d3464c08f0_0, 0, 32; + %store/vec4 v0000017b113e1750_0, 0, 32; %jmp T_12.19; T_12.14 ; %delay 4, 0; - %load/vec4 v000001d3464c17f0_0; - %load/vec4 v000001d3464c0cb0_0; + %load/vec4 v0000017b113e1cf0_0; + %load/vec4 v0000017b113e0b70_0; %mod/s; - %store/vec4 v000001d3464c08f0_0, 0, 32; + %store/vec4 v0000017b113e1750_0, 0, 32; %jmp T_12.19; T_12.15 ; %delay 4, 0; - %load/vec4 v000001d3464c17f0_0; - %load/vec4 v000001d3464c0cb0_0; + %load/vec4 v0000017b113e1cf0_0; + %load/vec4 v0000017b113e0b70_0; %mod; - %store/vec4 v000001d3464c08f0_0, 0, 32; + %store/vec4 v0000017b113e1750_0, 0, 32; %jmp T_12.19; T_12.16 ; %delay 2, 0; - %load/vec4 v000001d3464c17f0_0; - %load/vec4 v000001d3464c0cb0_0; + %load/vec4 v0000017b113e1cf0_0; + %load/vec4 v0000017b113e0b70_0; %cmp/u; %flag_mov 8, 5; %jmp/0 T_12.20, 8; @@ -1695,49 +1691,49 @@ T_12.20 ; End of true expr. ; End of false expr. %blend; T_12.21; - %store/vec4 v000001d3464c08f0_0, 0, 32; + %store/vec4 v0000017b113e1750_0, 0, 32; %jmp T_12.19; T_12.17 ; %delay 1, 0; - %load/vec4 v000001d3464c0cb0_0; - %store/vec4 v000001d3464c08f0_0, 0, 32; + %load/vec4 v0000017b113e0b70_0; + %store/vec4 v0000017b113e1750_0, 0, 32; %jmp T_12.19; T_12.19 ; %pop/vec4 1; %jmp T_12; .thread T_12, $push; - .scope S_000001d346406110; + .scope S_0000017b113391e0; T_13 ; - %wait E_000001d3464b3d00; - %load/vec4 v000001d34651e270_0; + %wait E_0000017b113d34a0; + %load/vec4 v0000017b1143f210_0; %cmpi/e 0, 0, 1; %jmp/0xz T_13.0, 4; - %load/vec4 v000001d34651f530_0; - %store/vec4 v000001d34651f5d0_0, 0, 32; + %load/vec4 v0000017b1143ef90_0; + %store/vec4 v0000017b1143e630_0, 0, 32; %jmp T_13.1; T_13.0 ; - %load/vec4 v000001d34651f030_0; - %store/vec4 v000001d34651f5d0_0, 0, 32; + %load/vec4 v0000017b1143fa30_0; + %store/vec4 v0000017b1143e630_0, 0, 32; T_13.1 ; %jmp T_13; .thread T_13, $push; - .scope S_000001d346452080; + .scope S_0000017b1132fee0; T_14 ; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d3464c1a70_0, 0, 1; + %store/vec4 v0000017b113e1ed0_0, 0, 1; %end; .thread T_14; - .scope S_000001d346452080; + .scope S_0000017b1132fee0; T_15 ; - %wait E_000001d3464b1580; + %wait E_0000017b113d33e0; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d3464c1a70_0, 0, 1; - %load/vec4 v000001d3464c0990_0; + %store/vec4 v0000017b113e1ed0_0, 0, 1; + %load/vec4 v0000017b113e17f0_0; %cmpi/e 1, 0, 1; %jmp/0xz T_15.0, 4; - %load/vec4 v000001d3464c1ed0_0; - %store/vec4 v000001d3464c0170_0, 0, 32; - %load/vec4 v000001d3464c1cf0_0; + %load/vec4 v0000017b113e1e30_0; + %store/vec4 v0000017b113e1f70_0, 0, 32; + %load/vec4 v0000017b113e07b0_0; %dup/vec4; %pushi/vec4 0, 0, 3; %cmp/u; @@ -1764,12 +1760,12 @@ T_15 ; %jmp/1 T_15.7, 6; %delay 1, 0; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d3464c1a70_0, 0, 1; + %store/vec4 v0000017b113e1ed0_0, 0, 1; %jmp T_15.9; T_15.2 ; %delay 1, 0; - %load/vec4 v000001d3464c1c50_0; - %load/vec4 v000001d3464c0d50_0; + %load/vec4 v0000017b113e0170_0; + %load/vec4 v0000017b113e03f0_0; %cmp/e; %flag_mov 8, 4; %jmp/0 T_15.10, 8; @@ -1781,12 +1777,12 @@ T_15.10 ; End of true expr. ; End of false expr. %blend; T_15.11; - %store/vec4 v000001d3464c1a70_0, 0, 1; + %store/vec4 v0000017b113e1ed0_0, 0, 1; %jmp T_15.9; T_15.3 ; %delay 1, 0; - %load/vec4 v000001d3464c1c50_0; - %load/vec4 v000001d3464c0d50_0; + %load/vec4 v0000017b113e0170_0; + %load/vec4 v0000017b113e03f0_0; %cmp/ne; %flag_mov 8, 4; %jmp/0 T_15.12, 8; @@ -1798,12 +1794,12 @@ T_15.12 ; End of true expr. ; End of false expr. %blend; T_15.13; - %store/vec4 v000001d3464c1a70_0, 0, 1; + %store/vec4 v0000017b113e1ed0_0, 0, 1; %jmp T_15.9; T_15.4 ; %delay 1, 0; - %load/vec4 v000001d3464c1c50_0; - %load/vec4 v000001d3464c0d50_0; + %load/vec4 v0000017b113e0170_0; + %load/vec4 v0000017b113e03f0_0; %cmp/s; %flag_mov 8, 5; %jmp/0 T_15.14, 8; @@ -1815,12 +1811,12 @@ T_15.14 ; End of true expr. ; End of false expr. %blend; T_15.15; - %store/vec4 v000001d3464c1a70_0, 0, 1; + %store/vec4 v0000017b113e1ed0_0, 0, 1; %jmp T_15.9; T_15.5 ; %delay 1, 0; - %load/vec4 v000001d3464c0d50_0; - %load/vec4 v000001d3464c1c50_0; + %load/vec4 v0000017b113e03f0_0; + %load/vec4 v0000017b113e0170_0; %cmp/s; %flag_or 5, 4; %flag_mov 8, 5; @@ -1833,12 +1829,12 @@ T_15.16 ; End of true expr. ; End of false expr. %blend; T_15.17; - %store/vec4 v000001d3464c1a70_0, 0, 1; + %store/vec4 v0000017b113e1ed0_0, 0, 1; %jmp T_15.9; T_15.6 ; %delay 1, 0; - %load/vec4 v000001d3464c1c50_0; - %load/vec4 v000001d3464c0d50_0; + %load/vec4 v0000017b113e0170_0; + %load/vec4 v0000017b113e03f0_0; %cmp/u; %flag_mov 8, 5; %jmp/0 T_15.18, 8; @@ -1850,12 +1846,12 @@ T_15.18 ; End of true expr. ; End of false expr. %blend; T_15.19; - %store/vec4 v000001d3464c1a70_0, 0, 1; + %store/vec4 v0000017b113e1ed0_0, 0, 1; %jmp T_15.9; T_15.7 ; %delay 1, 0; - %load/vec4 v000001d3464c0d50_0; - %load/vec4 v000001d3464c1c50_0; + %load/vec4 v0000017b113e03f0_0; + %load/vec4 v0000017b113e0170_0; %cmp/u; %flag_or 5, 4; %flag_mov 8, 5; @@ -1868,249 +1864,249 @@ T_15.20 ; End of true expr. ; End of false expr. %blend; T_15.21; - %store/vec4 v000001d3464c1a70_0, 0, 1; + %store/vec4 v0000017b113e1ed0_0, 0, 1; %jmp T_15.9; T_15.9 ; %pop/vec4 1; T_15.0 ; - %load/vec4 v000001d3464c16b0_0; + %load/vec4 v0000017b113e08f0_0; %cmpi/e 1, 0, 1; %jmp/0xz T_15.22, 4; %delay 1, 0; - %load/vec4 v000001d3464c1ed0_0; - %store/vec4 v000001d3464c0170_0, 0, 32; + %load/vec4 v0000017b113e1e30_0; + %store/vec4 v0000017b113e1f70_0, 0, 32; %pushi/vec4 1, 0, 1; - %store/vec4 v000001d3464c1a70_0, 0, 1; + %store/vec4 v0000017b113e1ed0_0, 0, 1; T_15.22 ; %jmp T_15; .thread T_15, $push; - .scope S_000001d346434b10; + .scope S_0000017b11372210; T_16 ; - %wait E_000001d3464b3e40; - %load/vec4 v000001d34651cdd0_0; + %wait E_0000017b113d32a0; + %load/vec4 v0000017b1143b250_0; %flag_set/vec4 8; %jmp/0xz T_16.0, 8; %delay 1, 0; %pushi/vec4 1, 1, 1; - %assign/vec4 v000001d34651b2f0_0, 0; + %assign/vec4 v0000017b1143b6b0_0, 0; %pushi/vec4 1, 1, 1; - %assign/vec4 v000001d34651c5b0_0, 0; + %assign/vec4 v0000017b1143bb10_0, 0; %pushi/vec4 1, 1, 1; - %assign/vec4 v000001d34651b250_0, 0; + %assign/vec4 v0000017b1143c0b0_0, 0; %pushi/vec4 1, 1, 1; - %assign/vec4 v000001d34651b7f0_0, 0; + %assign/vec4 v0000017b1143d050_0, 0; %pushi/vec4 4294967295, 4294967295, 32; - %assign/vec4 v000001d34651b6b0_0, 0; + %assign/vec4 v0000017b1143b570_0, 0; %pushi/vec4 31, 31, 5; - %assign/vec4 v000001d34651ba70_0, 0; + %assign/vec4 v0000017b1143be30_0, 0; %pushi/vec4 7, 7, 3; - %assign/vec4 v000001d34651c0b0_0, 0; + %assign/vec4 v0000017b1143cfb0_0, 0; %pushi/vec4 4294967295, 4294967295, 32; - %assign/vec4 v000001d34651d050_0, 0; + %assign/vec4 v0000017b1143cab0_0, 0; %jmp T_16.1; T_16.0 ; %delay 2, 0; - %load/vec4 v000001d34651ca10_0; - %assign/vec4 v000001d34651b2f0_0, 0; - %load/vec4 v000001d34651b1b0_0; - %assign/vec4 v000001d34651c5b0_0, 0; - %load/vec4 v000001d34651c830_0; - %assign/vec4 v000001d34651b250_0, 0; - %load/vec4 v000001d34651c010_0; - %assign/vec4 v000001d34651b7f0_0, 0; - %load/vec4 v000001d34651bed0_0; - %assign/vec4 v000001d34651b6b0_0, 0; - %load/vec4 v000001d34651cab0_0; - %assign/vec4 v000001d34651ba70_0, 0; - %load/vec4 v000001d34651cc90_0; - %assign/vec4 v000001d34651c0b0_0, 0; - %load/vec4 v000001d34651c330_0; - %assign/vec4 v000001d34651d050_0, 0; + %load/vec4 v0000017b1143b2f0_0; + %assign/vec4 v0000017b1143b6b0_0, 0; + %load/vec4 v0000017b1143b610_0; + %assign/vec4 v0000017b1143bb10_0, 0; + %load/vec4 v0000017b1143c510_0; + %assign/vec4 v0000017b1143c0b0_0, 0; + %load/vec4 v0000017b1143b930_0; + %assign/vec4 v0000017b1143d050_0, 0; + %load/vec4 v0000017b1143c010_0; + %assign/vec4 v0000017b1143b570_0, 0; + %load/vec4 v0000017b1143c970_0; + %assign/vec4 v0000017b1143be30_0, 0; + %load/vec4 v0000017b1143b890_0; + %assign/vec4 v0000017b1143cfb0_0, 0; + %load/vec4 v0000017b1143c470_0; + %assign/vec4 v0000017b1143cab0_0, 0; T_16.1 ; %jmp T_16; .thread T_16; - .scope S_000001d34645f910; + .scope S_0000017b113330a0; T_17 ; - %wait E_000001d3464b3800; - %load/vec4 v000001d346521540_0; + %wait E_0000017b113d37e0; + %load/vec4 v0000017b11440960_0; %flag_set/vec4 8; %jmp/1 T_17.2, 8; - %load/vec4 v000001d346521040_0; + %load/vec4 v0000017b11440280_0; %flag_set/vec4 9; %flag_or 8, 9; T_17.2; %jmp/0xz T_17.0, 8; %pushi/vec4 1, 0, 1; - %store/vec4 v000001d346520e60_0, 0, 1; + %store/vec4 v0000017b11441180_0, 0, 1; %jmp T_17.1; T_17.0 ; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d346520e60_0, 0, 1; + %store/vec4 v0000017b11441180_0, 0, 1; T_17.1 ; %jmp T_17; .thread T_17, $push; - .scope S_000001d34645f910; + .scope S_0000017b113330a0; T_18 ; - %wait E_000001d3464b3e40; - %load/vec4 v000001d346521540_0; + %wait E_0000017b113d32a0; + %load/vec4 v0000017b11440960_0; %flag_set/vec4 8; %jmp/0xz T_18.0, 8; - %ix/getv 4, v000001d346520780_0; - %load/vec4a v000001d346521180, 4; - %load/vec4 v000001d346520780_0; + %ix/getv 4, v0000017b11441b80_0; + %load/vec4a v0000017b114414a0, 4; + %load/vec4 v0000017b11441b80_0; %addi 1, 0, 32; %ix/vec4 4; - %load/vec4a v000001d346521180, 4; + %load/vec4a v0000017b114414a0, 4; %concat/vec4; draw_concat_vec4 - %load/vec4 v000001d346520780_0; + %load/vec4 v0000017b11441b80_0; %addi 2, 0, 32; %ix/vec4 4; - %load/vec4a v000001d346521180, 4; + %load/vec4a v0000017b114414a0, 4; %concat/vec4; draw_concat_vec4 - %load/vec4 v000001d346520780_0; + %load/vec4 v0000017b11441b80_0; %addi 3, 0, 32; %ix/vec4 4; - %load/vec4a v000001d346521180, 4; + %load/vec4a v0000017b114414a0, 4; %concat/vec4; draw_concat_vec4 - %store/vec4 v000001d346520960_0, 0, 32; + %store/vec4 v0000017b11440e60_0, 0, 32; %pushi/vec4 40, 0, 64; %ix/vec4 4; %delayx 4; - %load/vec4 v000001d346520960_0; - %store/vec4 v000001d3465206e0_0, 0, 32; + %load/vec4 v0000017b11440e60_0; + %store/vec4 v0000017b11442080_0, 0, 32; T_18.0 ; - %load/vec4 v000001d346521040_0; + %load/vec4 v0000017b11440280_0; %flag_set/vec4 8; %jmp/0xz T_18.2, 8; - %load/vec4 v000001d346521cc0_0; + %load/vec4 v0000017b114419a0_0; %parti/s 8, 0, 2; - %ix/getv 3, v000001d346520780_0; + %ix/getv 3, v0000017b11441b80_0; %ix/load 4, 40, 0; Constant delay - %assign/vec4/a/d v000001d346521180, 0, 4; - %load/vec4 v000001d346521cc0_0; + %assign/vec4/a/d v0000017b114414a0, 0, 4; + %load/vec4 v0000017b114419a0_0; %parti/s 8, 8, 5; - %load/vec4 v000001d346520780_0; + %load/vec4 v0000017b11441b80_0; %addi 1, 0, 32; %ix/vec4 3; %ix/load 4, 40, 0; Constant delay - %assign/vec4/a/d v000001d346521180, 0, 4; - %load/vec4 v000001d346521cc0_0; + %assign/vec4/a/d v0000017b114414a0, 0, 4; + %load/vec4 v0000017b114419a0_0; %parti/s 8, 16, 6; - %load/vec4 v000001d346520780_0; + %load/vec4 v0000017b11441b80_0; %addi 2, 0, 32; %ix/vec4 3; %ix/load 4, 40, 0; Constant delay - %assign/vec4/a/d v000001d346521180, 0, 4; - %load/vec4 v000001d346521cc0_0; + %assign/vec4/a/d v0000017b114414a0, 0, 4; + %load/vec4 v0000017b114419a0_0; %parti/s 8, 24, 6; - %load/vec4 v000001d346520780_0; + %load/vec4 v0000017b11441b80_0; %addi 3, 0, 32; %ix/vec4 3; %ix/load 4, 40, 0; Constant delay - %assign/vec4/a/d v000001d346521180, 0, 4; + %assign/vec4/a/d v0000017b114414a0, 0, 4; T_18.2 ; %jmp T_18; .thread T_18; - .scope S_000001d34645f910; + .scope S_0000017b113330a0; T_19 ; - %wait E_000001d3464b3840; - %load/vec4 v000001d3465203c0_0; + %wait E_0000017b113d3ca0; + %load/vec4 v0000017b11441040_0; %flag_set/vec4 8; %jmp/0xz T_19.0, 8; %pushi/vec4 0, 0, 32; - %store/vec4 v000001d346521900_0, 0, 32; + %store/vec4 v0000017b11440a00_0, 0, 32; T_19.2 ; - %load/vec4 v000001d346521900_0; + %load/vec4 v0000017b11440a00_0; %cmpi/s 1024, 0, 32; %jmp/0xz T_19.3, 5; %pushi/vec4 0, 0, 8; - %ix/getv/s 3, v000001d346521900_0; + %ix/getv/s 3, v0000017b11440a00_0; %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v000001d346521180, 0, 4; - %load/vec4 v000001d346521900_0; + %assign/vec4/a/d v0000017b114414a0, 0, 4; + %load/vec4 v0000017b11440a00_0; %addi 1, 0, 32; - %store/vec4 v000001d346521900_0, 0, 32; + %store/vec4 v0000017b11440a00_0, 0, 32; %jmp T_19.2; T_19.3 ; T_19.0 ; %jmp T_19; .thread T_19; - .scope S_000001d3464062a0; + .scope S_0000017b11339370; T_20 ; - %wait E_000001d3464b3e40; - %load/vec4 v000001d34651e1d0_0; + %wait E_0000017b113d32a0; + %load/vec4 v0000017b1143ebd0_0; %pad/u 32; %cmpi/e 1, 0, 32; %jmp/0xz T_20.0, 4; %delay 1, 0; %pushi/vec4 1, 1, 1; - %assign/vec4 v000001d34651f8f0_0, 0; + %assign/vec4 v0000017b1143f0d0_0, 0; %pushi/vec4 1, 1, 1; - %assign/vec4 v000001d34651edb0_0, 0; + %assign/vec4 v0000017b1143fc10_0, 0; %pushi/vec4 4294967295, 4294967295, 32; - %assign/vec4 v000001d34651f7b0_0, 0; + %assign/vec4 v0000017b1143f170_0, 0; %pushi/vec4 4294967295, 4294967295, 32; - %assign/vec4 v000001d34651f670_0, 0; + %assign/vec4 v0000017b1143f5d0_0, 0; %pushi/vec4 31, 31, 5; - %assign/vec4 v000001d34651f850_0, 0; + %assign/vec4 v0000017b1143fd50_0, 0; %jmp T_20.1; T_20.0 ; %delay 2, 0; - %load/vec4 v000001d34651e3b0_0; - %assign/vec4 v000001d34651f8f0_0, 0; - %load/vec4 v000001d346520070_0; - %assign/vec4 v000001d34651edb0_0, 0; - %load/vec4 v000001d34651fdf0_0; - %assign/vec4 v000001d34651f7b0_0, 0; - %load/vec4 v000001d34651fad0_0; - %assign/vec4 v000001d34651f670_0, 0; - %load/vec4 v000001d34651f170_0; - %assign/vec4 v000001d34651f850_0, 0; + %load/vec4 v0000017b1143fdf0_0; + %assign/vec4 v0000017b1143f0d0_0, 0; + %load/vec4 v0000017b1143f990_0; + %assign/vec4 v0000017b1143fc10_0, 0; + %load/vec4 v0000017b1143ec70_0; + %assign/vec4 v0000017b1143f170_0, 0; + %load/vec4 v0000017b1143f2b0_0; + %assign/vec4 v0000017b1143f5d0_0, 0; + %load/vec4 v0000017b1143f350_0; + %assign/vec4 v0000017b1143fd50_0, 0; T_20.1 ; %jmp T_20; .thread T_20; - .scope S_000001d346412f10; + .scope S_0000017b11326110; T_21 ; - %wait E_000001d3464b3780; - %load/vec4 v000001d34651eef0_0; + %wait E_0000017b113d3260; + %load/vec4 v0000017b1143f490_0; %cmpi/e 0, 0, 1; %jmp/0xz T_21.0, 4; - %load/vec4 v000001d34651fa30_0; - %store/vec4 v000001d34651f990_0, 0, 32; + %load/vec4 v0000017b1143f3f0_0; + %store/vec4 v0000017b1143e950_0, 0, 32; %jmp T_21.1; T_21.0 ; - %load/vec4 v000001d34651e770_0; - %store/vec4 v000001d34651f990_0, 0, 32; + %load/vec4 v0000017b1143e8b0_0; + %store/vec4 v0000017b1143e950_0, 0, 32; T_21.1 ; %jmp T_21; .thread T_21, $push; - .scope S_000001d3464be730; + .scope S_0000017b113de790; T_22 ; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34652a6c0_0, 0, 1; + %store/vec4 v0000017b11449860_0, 0, 1; T_22.0 ; %delay 4, 0; - %load/vec4 v000001d34652a6c0_0; + %load/vec4 v0000017b11449860_0; %inv; - %store/vec4 v000001d34652a6c0_0, 0, 1; + %store/vec4 v0000017b11449860_0, 0, 1; %jmp T_22.0; %end; .thread T_22; - .scope S_000001d3464be730; + .scope S_0000017b113de790; T_23 ; %pushi/vec4 1, 0, 1; - %store/vec4 v000001d34652a260_0, 0, 1; + %store/vec4 v0000017b1144a3a0_0, 0, 1; %delay 5, 0; %pushi/vec4 0, 0, 1; - %store/vec4 v000001d34652a260_0, 0, 1; + %store/vec4 v0000017b1144a3a0_0, 0, 1; %delay 1000, 0; %vpi_call 2 29 "$finish" {0 0 0}; %end; .thread T_23; - .scope S_000001d3464be730; + .scope S_0000017b113de790; T_24 ; %vpi_call 2 34 "$dumpfile", "cpu_pipeline.vcd" {0 0 0}; - %vpi_call 2 35 "$dumpvars", 32'sb00000000000000000000000000000000, S_000001d3464be730 {0 0 0}; + %vpi_call 2 35 "$dumpvars", 32'sb00000000000000000000000000000000, S_0000017b113de790 {0 0 0}; %end; .thread T_24; # The file index is used to find the file name in the following table. diff --git a/CPU/cpu_pipeline.vcd b/CPU/cpu_pipeline.vcd index da0ffc7..82f47c4 100644 --- a/CPU/cpu_pipeline.vcd +++ b/CPU/cpu_pipeline.vcd @@ -1,5 +1,5 @@ $date - Thu Jan 02 01:26:00 2025 + Mon Jan 06 11:38:23 2025 $end $version Icarus Verilog @@ -507,7 +507,6 @@ b0 ." b0 ) b0 v b0 -" -b0 Y" b0 0 b0 ," b0 6" @@ -571,18 +570,17 @@ b1000 0" b1000 Q" b1000 T" b1000 U" -b11110010110000001010000110100011 I -b11110010110000001010000110100011 1" -b11110010110000001010000110100011 R" +b1111011000010011 I +b1111011000010011 1" +b1111011000010011 R" #22 b0 h b0 g b0 f -b100011 E" -b10 G" -b1111001 F" -b1100 , -b1100 X" +b111 G" +b0 F" +b0 , +b0 X" b0 b b0 a b0 c @@ -596,18 +594,17 @@ b1000 4" b1000 2 b1000 "" b1000 3" -b11110010110000001010000110100011 H -b11110010110000001010000110100011 ~ -b11110010110000001010000110100011 2" -b11110010110000001010000110100011 D" -b11110010110000001010000110100011 O" +b1111011000010011 H +b1111011000010011 ~ +b1111011000010011 2" +b1111011000010011 D" +b1111011000010011 O" b11111111111111111111100011110001 J b11111111111111111111100011110001 s b11111111111111111111100011110001 *" b1 ) b1 v b1 -" -b1 Y" b0 T b0 t b0 x @@ -650,19 +647,19 @@ b1100 /" b1100 B" b1100 V" #23 -1; -1B -0& -b1 L -b1 I" -b1 N" +b100 ] +b100 &" +b100 H" #24 +bx V +bx $" +bx \" b11111111111111111111100011110001 F b11111111111111111111100011110001 y b11111111111111111111100011110001 7" -b11111111111111111111111100100011 K -b11111111111111111111111100100011 #" -b11111111111111111111111100100011 P" +b0 K +b0 #" +b0 P" b11111111111111111111100011110001 ` b11111111111111111111100011110001 j b11111111111111111111100011110001 k @@ -676,24 +673,25 @@ b1100 0" b1100 Q" b1100 T" b1100 U" -bx I -bx 1" -bx R" +b11110010001101100000000100000011 I +b11110010001101100000000100000011 1" +b11110010001101100000000100000011 R" #30 0Y -b11111111111111111111111100100011 Q -b11111111111111111111111100100011 d -b11111111111111111111111100100011 m -b11111111111111111111111100100011 u -bx E" -bx G" -bx F" -bx , -bx X" -bx - -bx W" +b0 Q +b0 d +b0 m +b0 u +b11 E" +b0 G" +b1111001 F" +b11 , +b11 X" +b1100 - +b1100 W" b0 ( b0 =" +b0 Y" b0 ^ b0 ;" b0 >" @@ -711,37 +709,40 @@ b11111111111111111111100011110001 J" 0: 0A 1% -b11111111111111111111111100100011 J -b11111111111111111111111100100011 s -b11111111111111111111111100100011 *" -b10 O -b10 l -b10 w -b10 ." -b11 ) -b11 v -b11 -" -b11 Y" +b0 J +b0 s +b0 *" +b111 O +b111 l +b111 w +b111 ." +b1100 ) +b1100 v +b1100 -" +bx T +bx t +bx x +bx )" b1000 0 b1000 ," b1000 6" b1000 4 b1000 p b1000 +" -19 -1@ -0$ +b100 \ +b100 i +b100 '" b1100 / b1100 !" b1100 4" b1100 2 b1100 "" b1100 3" -bx H -bx ~ -bx 2" -bx D" -bx O" +b11110010001101100000000100000011 H +b11110010001101100000000100000011 ~ +b11110010001101100000000100000011 2" +b11110010001101100000000100000011 D" +b11110010001101100000000100000011 O" b10000 3 b10000 C" b10000 S" @@ -749,23 +750,26 @@ b10000 1 b10000 /" b10000 B" b10000 V" +#31 +b0 F +b0 y +b0 7" +b0 ] +b0 &" +b0 H" +1> +1B +b0 ` +b0 j +b0 k +b0 5" #32 -bx V -bx $" -bx \" -bx X -bx %" -bx [" -b11111111111111111111111100100011 F -b11111111111111111111111100100011 y -b11111111111111111111111100100011 7" -b11111111111111111111111100100011 ` -b11111111111111111111111100100011 j -b11111111111111111111111100100011 k -b11111111111111111111111100100011 5" -bx K -bx #" -bx P" +b0 V +b0 $" +b0 \" +b11111111111111111111111100100011 K +b11111111111111111111111100100011 #" +b11111111111111111111111100100011 P" 0! #36 1! @@ -775,22 +779,20 @@ b10000 0" b10000 Q" b10000 T" b10000 U" +b11110010110000001010000110100011 I +b11110010110000001010000110100011 1" +b11110010110000001010000110100011 R" #38 -bx h -bx g -bx f -bx Q -bx d -bx m -bx u -bx b -bx a -bx c -bx R -bx e -bx n -bx r -1Y +b100011 E" +b10 G" +b1100 , +b1100 X" +b1 - +b1 W" +b11111111111111111111111100100011 Q +b11111111111111111111111100100011 d +b11111111111111111111111100100011 m +b11111111111111111111111100100011 u b11111111111111111111100011110001 ' b11111111111111111111100011110001 @" b11111111111111111111100011110001 Z" @@ -800,44 +802,51 @@ b10000 4" b10000 2 b10000 "" b10000 3" -bx J -bx s -bx *" -bx O -bx l -bx w -bx ." -bx ) -bx v -bx -" -bx Y" -bx T -bx t -bx x -bx )" -bx W -bx q -bx (" +b11110010110000001010000110100011 H +b11110010110000001010000110100011 ~ +b11110010110000001010000110100011 2" +b11110010110000001010000110100011 D" +b11110010110000001010000110100011 O" +b11111111111111111111111100100011 J +b11111111111111111111111100100011 s +b11111111111111111111111100100011 *" +b0 O +b0 l +b0 w +b0 ." +b10 ) +b10 v +b10 -" +b0 T +b0 t +b0 x +b0 )" b1100 0 b1100 ," b1100 6" b1100 4 b1100 p b1100 +" -b10 P -b10 | -b11 * -b11 } -b11 9" -b11111111111111111111111100100011 _ -b11111111111111111111111100100011 z -b11111111111111111111111100100011 8" -b11111111111111111111111100100011 J" -1: -1A -0% +b0 \ +b0 i +b0 '" +1< +1@ +bx U +bx { +bx K" +b111 P +b111 | +b1100 * +b1100 } +b1100 9" +b0 _ +b0 z +b0 8" +b0 J" b1 ( b1 =" +b1 Y" b11111111111111111111100011110001 ^ b11111111111111111111100011110001 ;" b11111111111111111111100011110001 >" @@ -850,14 +859,21 @@ b10100 1 b10100 /" b10100 B" b10100 V" +#39 +0> +1; +0& +b1 L +b1 I" +b1 N" #40 -bx F -bx y -bx 7" -bx ` -bx j -bx k -bx 5" +b11111111111111111111111100100011 F +b11111111111111111111111100100011 y +b11111111111111111111111100100011 7" +b11111111111111111111111100100011 ` +b11111111111111111111111100100011 j +b11111111111111111111111100100011 k +b11111111111111111111111100100011 5" 0! #44 1! @@ -867,41 +883,68 @@ b10100 0" b10100 Q" b10100 T" b10100 U" +bx I +bx 1" +bx R" #46 -bx ' -bx @" -bx Z" -b11 ( -b11 =" -b11111111111111111111111100100011 ^ -b11111111111111111111111100100011 ;" -b11111111111111111111111100100011 >" -1? -0# -bx U -bx { -bx K" -bx P -bx | -bx * -bx } -bx 9" -bx _ -bx z -bx 8" -bx J" +b0 ' +b0 @" +b0 Z" +1Y +bx E" +bx G" +bx F" +bx , +bx X" +bx - +bx W" +b1100 ( +b1100 =" +b1100 Y" +b0 ^ +b0 ;" +b0 >" +b0 U +b0 { +b0 K" +b0 P +b0 | +b10 * +b10 } +b10 9" +b11111111111111111111111100100011 _ +b11111111111111111111111100100011 z +b11111111111111111111111100100011 8" +b11111111111111111111111100100011 J" +1= +1A +b10 O +b10 l +b10 w +b10 ." +b11 ) +b11 v +b11 -" b10000 0 b10000 ," b10000 6" b10000 4 b10000 p b10000 +" +0< +19 +0$ b10100 / b10100 !" b10100 4" b10100 2 b10100 "" b10100 3" +bx H +bx ~ +bx 2" +bx D" +bx O" b11000 3 b11000 C" b11000 S" @@ -910,6 +953,15 @@ b11000 /" b11000 B" b11000 V" #48 +bx V +bx $" +bx \" +bx X +bx %" +bx [" +bx K +bx #" +bx P" 0! #52 1! @@ -920,23 +972,67 @@ b11000 Q" b11000 T" b11000 U" #54 +bx h +bx g +bx f +bx Q +bx d +bx m +bx u +bx b +bx a +bx c +bx R +bx e +bx n +bx r +bx ' +bx @" +bx Z" b11000 / b11000 !" b11000 4" b11000 2 b11000 "" b11000 3" +bx J +bx s +bx *" +bx O +bx l +bx w +bx ." +bx ) +bx v +bx -" +bx T +bx t +bx x +bx )" +bx W +bx q +bx (" b10100 0 b10100 ," b10100 6" b10100 4 b10100 p b10100 +" -bx ( -bx =" -bx ^ -bx ;" -bx >" +b10 P +b10 | +b11 * +b11 } +b11 9" +0= +1: +0% +b10 ( +b10 =" +b10 Y" +b11111111111111111111111100100011 ^ +b11111111111111111111111100100011 ;" +b11111111111111111111111100100011 >" +1? b11100 3 b11100 C" b11100 S" @@ -945,6 +1041,13 @@ b11100 /" b11100 B" b11100 V" #56 +bx F +bx y +bx 7" +bx ` +bx j +bx k +bx 5" 0! #60 1! @@ -955,6 +1058,22 @@ b11100 Q" b11100 T" b11100 U" #62 +b11 ( +b11 =" +b11 Y" +0# +bx U +bx { +bx K" +bx P +bx | +bx * +bx } +bx 9" +bx _ +bx z +bx 8" +bx J" b11000 0 b11000 ," b11000 6" @@ -997,6 +1116,12 @@ b11100 6" b11100 4 b11100 p b11100 +" +bx ( +bx =" +bx Y" +bx ^ +bx ;" +bx >" b100100 3 b100100 C" b100100 S" @@ -2694,17 +2819,7 @@ b100000100 0" b100000100 Q" b100000100 T" b100000100 U" -b10001111000100001000000010010011 I -b10001111000100001000000010010011 1" -b10001111000100001000000010010011 R" #526 -b10011 E" -b0 G" -b1000111 F" -b10001 , -b10001 X" -b1 - -b1 W" b100000000 0 b100000000 ," b100000000 6" @@ -2717,11 +2832,6 @@ b100000100 4" b100000100 2 b100000100 "" b100000100 3" -b10001111000100001000000010010011 H -b10001111000100001000000010010011 ~ -b10001111000100001000000010010011 2" -b10001111000100001000000010010011 D" -b10001111000100001000000010010011 O" b100001000 3 b100001000 C" b100001000 S" @@ -2729,23 +2839,7 @@ b100001000 1 b100001000 /" b100001000 B" b100001000 V" -#527 -0; -0B -1& -b0 L -b0 I" -b0 N" #528 -b0 V -b0 $" -b0 \" -b0 X -b0 %" -b0 [" -b11111111111111111111100011110001 K -b11111111111111111111100011110001 #" -b11111111111111111111100011110001 P" 0! #532 1! @@ -2755,67 +2849,19 @@ b100001000 0" b100001000 Q" b100001000 T" b100001000 U" -b11110010110000001010000110100011 I -b11110010110000001010000110100011 1" -b11110010110000001010000110100011 R" #534 -b0 h -b0 g -b0 f -b100011 E" -b10 G" -b1111001 F" -b1100 , -b1100 X" -b0 b -b0 a -b0 c -b11111111111111111111100011110001 Q -b11111111111111111111100011110001 d -b11111111111111111111100011110001 m -b11111111111111111111100011110001 u -b0 R -b0 e -b0 n -b0 r b100001000 / b100001000 !" b100001000 4" b100001000 2 b100001000 "" b100001000 3" -b11110010110000001010000110100011 H -b11110010110000001010000110100011 ~ -b11110010110000001010000110100011 2" -b11110010110000001010000110100011 D" -b11110010110000001010000110100011 O" -b11111111111111111111100011110001 J -b11111111111111111111100011110001 s -b11111111111111111111100011110001 *" -b0 O -b0 l -b0 w -b0 ." -b1 ) -b1 v -b1 -" -b1 Y" -b0 T -b0 t -b0 x -b0 )" -b0 W -b0 q -b0 (" b100000100 0 b100000100 ," b100000100 6" b100000100 4 b100000100 p b100000100 +" -09 -0@ -1$ b100001100 3 b100001100 C" b100001100 S" @@ -2823,24 +2869,7 @@ b100001100 1 b100001100 /" b100001100 B" b100001100 V" -#535 -1; -1B -0& -b1 L -b1 I" -b1 N" #536 -b11111111111111111111100011110001 F -b11111111111111111111100011110001 y -b11111111111111111111100011110001 7" -b11111111111111111111100011110001 ` -b11111111111111111111100011110001 j -b11111111111111111111100011110001 k -b11111111111111111111100011110001 5" -b11111111111111111111111100100011 K -b11111111111111111111111100100011 #" -b11111111111111111111111100100011 P" 0! #540 1! @@ -2850,68 +2879,19 @@ b100001100 0" b100001100 Q" b100001100 T" b100001100 U" -bx I -bx 1" -bx R" #542 -0Y -b11111111111111111111111100100011 Q -b11111111111111111111111100100011 d -b11111111111111111111111100100011 m -b11111111111111111111111100100011 u -bx E" -bx G" -bx F" -bx , -bx X" -bx - -bx W" -b0 U -b0 { -b0 K" -b0 P -b0 | -b1 * -b1 } -b1 9" -b11111111111111111111100011110001 _ -b11111111111111111111100011110001 z -b11111111111111111111100011110001 8" -b11111111111111111111100011110001 J" -0: -0A -1% -b11111111111111111111111100100011 J -b11111111111111111111111100100011 s -b11111111111111111111111100100011 *" -b10 O -b10 l -b10 w -b10 ." -b11 ) -b11 v -b11 -" -b11 Y" b100001000 0 b100001000 ," b100001000 6" b100001000 4 b100001000 p b100001000 +" -19 -1@ -0$ b100001100 / b100001100 !" b100001100 4" b100001100 2 b100001100 "" b100001100 3" -bx H -bx ~ -bx 2" -bx D" -bx O" b100010000 3 b100010000 C" b100010000 S" @@ -2920,22 +2900,6 @@ b100010000 /" b100010000 B" b100010000 V" #544 -bx V -bx $" -bx \" -bx X -bx %" -bx [" -b11111111111111111111111100100011 F -b11111111111111111111111100100011 y -b11111111111111111111111100100011 7" -b11111111111111111111111100100011 ` -b11111111111111111111111100100011 j -b11111111111111111111111100100011 k -b11111111111111111111111100100011 5" -bx K -bx #" -bx P" 0! #548 1! @@ -2946,73 +2910,18 @@ b100010000 Q" b100010000 T" b100010000 U" #550 -bx h -bx g -bx f -bx Q -bx d -bx m -bx u -bx b -bx a -bx c -bx R -bx e -bx n -bx r -1Y -b11111111111111111111100011110001 ' -b11111111111111111111100011110001 @" -b11111111111111111111100011110001 Z" b100010000 / b100010000 !" b100010000 4" b100010000 2 b100010000 "" b100010000 3" -bx J -bx s -bx *" -bx O -bx l -bx w -bx ." -bx ) -bx v -bx -" -bx Y" -bx T -bx t -bx x -bx )" -bx W -bx q -bx (" b100001100 0 b100001100 ," b100001100 6" b100001100 4 b100001100 p b100001100 +" -b10 P -b10 | -b11 * -b11 } -b11 9" -b11111111111111111111111100100011 _ -b11111111111111111111111100100011 z -b11111111111111111111111100100011 8" -b11111111111111111111111100100011 J" -1: -1A -0% -b1 ( -b1 =" -b11111111111111111111100011110001 ^ -b11111111111111111111100011110001 ;" -b11111111111111111111100011110001 >" -0? -1# b100010100 3 b100010100 C" b100010100 S" @@ -3021,13 +2930,6 @@ b100010100 /" b100010100 B" b100010100 V" #552 -bx F -bx y -bx 7" -bx ` -bx j -bx k -bx 5" 0! #556 1! @@ -3038,28 +2940,6 @@ b100010100 Q" b100010100 T" b100010100 U" #558 -bx ' -bx @" -bx Z" -b11 ( -b11 =" -b11111111111111111111111100100011 ^ -b11111111111111111111111100100011 ;" -b11111111111111111111111100100011 >" -1? -0# -bx U -bx { -bx K" -bx P -bx | -bx * -bx } -bx 9" -bx _ -bx z -bx 8" -bx J" b100010000 0 b100010000 ," b100010000 6" @@ -3102,11 +2982,6 @@ b100010100 6" b100010100 4 b100010100 p b100010100 +" -bx ( -bx =" -bx ^ -bx ;" -bx >" b100011100 3 b100011100 C" b100011100 S" diff --git a/CPU/file for gtk wave.gtkw b/CPU/file for gtk wave.gtkw new file mode 100644 index 0000000..4a740d8 --- /dev/null +++ b/CPU/file for gtk wave.gtkw @@ -0,0 +1,76 @@ +[*] +[*] GTKWave Analyzer v3.3.100 (w)1999-2019 BSI +[*] Mon Jan 06 06:12:32 2025 +[*] +[dumpfile] "D:\CO502-2024 Advanced Computer Architecture (Nov 2024)\e20-co502-RV32IM-pipeline-implementation-group-2\CPU\cpu_pipeline.vcd" +[dumpfile_mtime] "Mon Jan 06 06:08:23 2025" +[dumpfile_size] 60119 +[savefile] "D:\CO502-2024 Advanced Computer Architecture (Nov 2024)\e20-co502-RV32IM-pipeline-implementation-group-2\CPU\file for gtk wave.gtkw" +[timestart] 0 +[size] 1536 793 +[pos] -1 -1 +*-4.000000 13 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] cpu_testbench. +[treeopen] cpu_testbench.cpu_inst. +[sst_width] 197 +[signals_width] 246 +[sst_expanded] 1 +[sst_vpaned_height] 221 +@28 +cpu_testbench.CLK +cpu_testbench.RESET +@22 +cpu_testbench.cpu_inst.pc1.PCIN[31:0] +cpu_testbench.cpu_inst.pc1.PCOUT[31:0] +cpu_testbench.cpu_inst.instructionmem1.INSTRUCTION[31:0] +cpu_testbench.cpu_inst.ID_IF_register1.INSTRUCTION_OUT[31:0] +@28 +cpu_testbench.cpu_inst.controlunit1.WRITE_ENABLE +cpu_testbench.cpu_inst.controlunit1.IMMEDIATE_SELECT +cpu_testbench.cpu_inst.controlunit1.IMMEDIATE_TYPE[2:0] +@22 +cpu_testbench.cpu_inst.controlunit1.ALU_OPCODE[4:0] +cpu_testbench.cpu_inst.registerfile1.DATA1[31:0] +cpu_testbench.cpu_inst.registerfile1.DATA2[31:0] +cpu_testbench.cpu_inst.imidiateGenarator1.IMMEDIATE_VALUE[31:0] +@200 +-id ex pipeline register out +@22 +cpu_testbench.cpu_inst.ID_EXPipeline1.Out_Immediate_value[31:0] +cpu_testbench.cpu_inst.ID_EXPipeline1.Out_Data1[31:0] +cpu_testbench.cpu_inst.ID_EXPipeline1.Out_Data2[31:0] +@200 +-data 1 data 2 muxes out +@22 +cpu_testbench.cpu_inst.Data1_MUX.OUTPUT[31:0] +cpu_testbench.cpu_inst.Data2_MUX.OUTPUT[31:0] +@200 +-alu output +@22 +cpu_testbench.cpu_inst.ALU.Output[31:0] +@200 +-EX mem pipeline +@22 +cpu_testbench.cpu_inst.EX_MEM_pipeline1.ALU_OUTPUT_OUT[31:0] +cpu_testbench.cpu_inst.EX_MEM_pipeline1.WRITE_ADDRESS_OUT[4:0] +@200 +-mem wb pipeline out +@22 +cpu_testbench.cpu_inst.MEM_WBPipeline1.ALU_Output_Out[31:0] +cpu_testbench.cpu_inst.MEM_WBPipeline1.Write_Address_out[4:0] +@28 +cpu_testbench.cpu_inst.MEM_WBPipeline1.Memory_access_Out +@200 +-mem access mux out +@22 +cpu_testbench.cpu_inst.Memory_access_MUX.OUTPUT[31:0] +@200 +-wb stage +@22 +cpu_testbench.cpu_inst.registerfile1.WRITEADDRESS[4:0] +@28 +cpu_testbench.cpu_inst.registerfile1.WRITEENABLE +@23 +cpu_testbench.cpu_inst.registerfile1.WRITEDATA[31:0] +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/InstructionMemory/instructionmem.v b/InstructionMemory/instructionmem.v index 4d5d1e8..6e48358 100644 --- a/InstructionMemory/instructionmem.v +++ b/InstructionMemory/instructionmem.v @@ -74,9 +74,8 @@ initial begin // Hardcoded instructions memory_array[0] = 32'b100011110001_00001_000_00001_0010011; // ADDI x1, x1, 0x8F1 // ADDI x1, x1, 0x8F1 memory_array[1] = 32'b0000000_00000_00001_111_01100_0010011; // ANDI x1, x12, 0x000 - memory_array[2] = 32'b0000000_00001_01100_000_00001_0100011; // SB x1, 0x001(x12) - memory_array[3] = 32'b111100100011_01100_000_00010_0000011; // LB x2, 0xF23(x12) - memory_array[4] = 32'b1111001_01100_00001_010_00011_0100011; // SW x12, 0xF23(x1) + memory_array[2] = 32'b111100100011_01100_000_00010_0000011; // LB x2, 0xF23(x12) + memory_array[3] = 32'b1111001_01100_00001_010_00011_0100011; // SW x12, 0xF23(x1) // Add more instructions as needed end @@ -86,7 +85,7 @@ always @(posedge CLK or posedge RESET) begin if (RESET) begin INSTRUCTION <= 32'b0; // Output zero on reset end else begin - INSTRUCTION <= memory_array[PC[7:0]]; // Fetch instruction (PC[9:2] to align with 32-bit words) + INSTRUCTION <= memory_array[PC[9:2]]; // Fetch instruction (PC[9:2] to align with 32-bit words) end end