@@ -1122,10 +1122,11 @@ static const char *__doc_fiction_bounding_box_2d_x_size = R"doc(The horizontal s
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static const char *__doc_fiction_bounding_box_2d_y_size = R"doc(The vertical size of the bounding box in layout coordinates.)doc";
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- static const char *__doc_fiction_calculate_energy_and_state_type =
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+ static const char *__doc_fiction_calculate_energy_and_state_type_with_kinks_accepted =
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R"doc(This function takes in an SiDB energy distribution. For each charge
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distribution, the state type is determined (i.e. erroneous,
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- transparent).
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+ transparent) while kinks are accepted, meaning a state with kinks is
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+ considered transparent.
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Template parameter ``Lyt``:
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SiDB cell-level layout type.
@@ -1153,6 +1154,44 @@ Parameter ``input_index``:
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Electrostatic potential energy of all charge distributions with
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state type.)doc";
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+ static const char *__doc_fiction_calculate_energy_and_state_type_with_kinks_rejected =
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+ R"doc(This function takes in an SiDB energy distribution. For each charge
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+ distribution, the state type is determined (i.e. erroneous,
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+ transparent) while kinks are rejected, meaning a state with kinks is
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+ considered erroneous.
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+
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+ Template parameter ``Lyt``:
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+ SiDB cell-level layout type.
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+
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+ Template parameter ``TT``:
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+ The type of the truth table specifying the gate behavior.
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+
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+ Parameter ``energy_distribution``:
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+ Energy distribution.
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+
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+ Parameter ``valid_charge_distributions``:
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+ Physically valid charge distributions.
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+
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+ Parameter ``output_bdl_pairs``:
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+ Output BDL pairs.
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+
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+ Parameter ``spec``:
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+ Expected Boolean function of the layout given as a multi-output
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+ truth table.
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+
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+ Parameter ``input_index``:
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+ The index of the current input configuration.
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+
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+ Parameter ``input_bdl_wires``:
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+ Input BDL wires.
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+
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+ Parameter ``output_bdl_wires``:
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+ Output BDL wires.
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+
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+ Returns:
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+ Electrostatic potential energy of all charge distributions with
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+ state type.)doc";
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+
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static const char *__doc_fiction_can_positive_charges_occur =
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R"doc(This algorithm determines if positively charged SiDBs can occur in a
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given SiDB cell-level layout due to strong electrostatic interaction.
@@ -3428,10 +3467,6 @@ probability of less than the given percentage, is determined to be the
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critical temperature. For gate-based simulation, this is the
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probability of erroneous calculations of the gate.)doc";
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- static const char *__doc_fiction_critical_temperature_params_engine = R"doc(Simulation mode to determine the *Critical Temperature*.)doc";
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-
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- static const char *__doc_fiction_critical_temperature_params_input_iterator_params = R"doc(Parameters for the BDL input iterator.)doc";
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-
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static const char *__doc_fiction_critical_temperature_params_iteration_steps =
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R"doc(Number of iteration steps for the *QuickSim* algorithm (only
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applicable if engine == APPROXIMATE).)doc";
@@ -3440,21 +3475,9 @@ static const char *__doc_fiction_critical_temperature_params_max_temperature =
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R"doc(Maximum simulation temperature beyond which no simulation will be
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conducted (~ 126 °C by default) (unit: K).)doc";
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- static const char *__doc_fiction_critical_temperature_params_simulation_engine =
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- R"doc(An enumeration of simulation modes (exact vs. approximate) to use for
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- the *Critical Temperature* Simulation.)doc";
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-
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- static const char *__doc_fiction_critical_temperature_params_simulation_engine_APPROXIMATE =
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- R"doc(This simulation engine quickly calculates the *Critical Temperature*.
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- However, there may be deviations from the exact *Critical
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- Temperature*. This mode is recommended for larger layouts (> 40
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- SiDBs).)doc";
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-
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- static const char *__doc_fiction_critical_temperature_params_simulation_engine_EXACT =
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- R"doc(This simulation engine computes *Critical Temperature* values with 100
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- % accuracy.)doc";
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-
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- static const char *__doc_fiction_critical_temperature_params_simulation_parameters = R"doc(All parameters for physical SiDB simulations.)doc";
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+ static const char *__doc_fiction_critical_temperature_params_operational_params =
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+ R"doc(The parameters used to determine if a layout is `operational` or `non-
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+ operational`.)doc";
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static const char *__doc_fiction_critical_temperature_stats = R"doc(This struct stores the result of the temperature simulation.)doc";
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@@ -4531,7 +4554,7 @@ given Boolean function.)doc";
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static const char *__doc_fiction_detail_critical_temperature_impl_params = R"doc(Parameters for the critical_temperature algorithm.)doc";
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- static const char *__doc_fiction_detail_critical_temperature_impl_physical_simulation_of_layout =
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+ static const char *__doc_fiction_detail_critical_temperature_impl_physical_simulation_of_bdl_iterator =
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R"doc(This function conducts physical simulation of the given layout (gate
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layout with certain input combination). The simulation results are
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stored in the `sim_result_100` variable.
@@ -6844,21 +6867,18 @@ R"doc(Constructor to initialize the algorithm with a layout and parameters.
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Parameter ``lyt``:
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The SiDB cell-level layout to be checked.
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- Parameter ``spec ``:
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+ Parameter ``tt ``:
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Expected Boolean function of the layout given as a multi-output
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truth table.
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Parameter ``params``:
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Parameters for the `is_operational` algorithm.
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- Parameter ``input_bdl_wire``:
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- Optional BDL input wires of lyt.
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-
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- Parameter ``output_bdl_wire``:
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- Optional BDL output wires of lyt.
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+ Parameter ``input_wires``:
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+ BDL input wires of lyt.
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- Parameter ``input_bdl_wire_direction ``:
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- Optional BDL input wire directions of lyt.)doc";
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+ Parameter ``output_wires ``:
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+ BDL output wires of lyt.)doc";
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static const char *__doc_fiction_detail_is_operational_impl_layout = R"doc(SiDB cell-level layout.)doc";
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@@ -6895,6 +6915,28 @@ static const char *__doc_fiction_detail_is_operational_impl_simulator_invocation
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static const char *__doc_fiction_detail_is_operational_impl_truth_table = R"doc(The specification of the layout.)doc";
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+ static const char *__doc_fiction_detail_is_operational_impl_verifiy_logic_match_of_cds =
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+ R"doc(Checks if the given charge distribution correctly encodes the expected
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+ logic for the given input pattern, based on a provided truth table.
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+
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+ Example: In the ground state charge distribution of an AND gate, kinks
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+ are rejected for the gate to be considered operational. Given an input
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+ pattern of `01`, this function will: - Verify that the left input wire
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+ encodes `0`. - Verify that the right input wire encodes `1`. - Verify
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+ that the output wire encodes `0`. Determines if the given charge
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+ distribution fulfills the correct logic based on the provided charge
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+ index and truth table.
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+
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+ Parameter ``given_cds``:
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+ The charge distribution surface to be checked for operation.
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+
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+ Parameter ``input_pattern``:
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+ Input pattern represented by the position of perturbers.
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+
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+ Returns:
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+ Operational status indicating if the layout is `operational` or
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+ `non-operational`.)doc";
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+
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static const char *__doc_fiction_detail_jump_point_search_impl = R"doc()doc";
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static const char *__doc_fiction_detail_jump_point_search_impl_closed_list = R"doc(Closed list that acts as a set of already visited coordinates.)doc";
@@ -18211,6 +18253,50 @@ Template parameter ``Lyt``:
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Returns:
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USE clocking scheme.)doc";
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+ static const char *__doc_fiction_verify_logic_match =
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+ R"doc(Checks if a given charge distribution correctly encodes the expected
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+ logic for a specified input pattern, based on a provided truth table.
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+
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+ @note Kinks are rejected.
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+
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+ Example: In the ground state charge distribution of an AND gate, kinks
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+ are rejected for the gate to be considered operational. Given an input
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+ pattern of `01`, this function will: - Verify that the left input wire
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+ encodes `0`. - Verify that the right input wire encodes `1`. - Verify
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+ that the output wire encodes `0`.
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+
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+ Template parameter ``Lyt``:
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+ SiDB cell-level layout type.
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+
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+ Template parameter ``TT``:
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+ Truth table type.
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+
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+ Parameter ``cds``:
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+ Charge distribution surface, containing charge state information
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+ for each SiDB.
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+
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+ Parameter ``params``:
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+ The parameters used to determine if a layout is `operational` or
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+ `non-operational`.
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+
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+ Parameter ``spec``:
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+ Expected Boolean function of the layout given as a multi-output
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+ truth table.
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+
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+ Parameter ``input_pattern``:
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+ The specific input pattern of the given charge distribution
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+ surface.
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+
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+ Parameter ``input_wires``:
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+ Input BDL wires.
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+
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+ Parameter ``output_wires``:
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+ Output BDL wires.
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+
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+ Returns:
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+ The operational status indicating if the charge distribution
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+ matches the logic for the given input pattern.)doc";
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+
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static const char *__doc_fiction_vertex_coloring =
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R"doc(A vertex coloring is simply a hash map from vertex IDs to Color types
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where Color should be constructible/convertible from int.
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