Verilog coding guidelines

Coding Guidelines for development of primitives in Verilog HDL

This document consists of some general guidelines followed by a more technical set of rules that must be kept in mind while coding in Verilog HDL.

####General Guidelines:

1. The functionality of the primitive or sub-system should be clear, before starting Verilog coding.
2. Verilog should be written in a manner that helps the synthesis tool infer desired digital logic.
3. To ensure that the synthesis tool has inferred the desired logic, it is necessary to synthesize the code on the target device’s synthesis tool (in our case XST). (Note: Read carefully IEEE Verilog Language Reference Manual for synthesizable and non-synthesizable constructs in Verilog)
4. Every tool has its synthesis guidelines and it necessary to understand them before coding.
5. Do have a look and take appropriate actions for the warnings that the synthesis tool generates (if any) while you compile your design.
6. To be on the safer side, it is suggested to carry out the functional and gate level (netlist) simulation of the primitives and sub-systems.

####Guidelines for coding in Verilog HDL: These guidelines only form a checklist while coding. They are not exhaustive in nature. It is assumed that the reader is aware of the concepts of digital design and to a certain extent, understands Verilog coding. Throughout these guidelines signals having “_i” suffix are input signals and those with “_o” suffix are output signals. Active low signals have “_ni” and “_no” suffix.

1. Latches are harmful in any synchronous design and hence they should be avoided.

The following constructs in Verilog lead to an inference of latch by the synthesis tool:

a. Missing ‘else’ statement in a combinational block b. It is not just the case of the missing else statement. Even if the else statement is present, the same variable will have to be assigned in the else section of the code. A latch will still be inferred if the same variable is not assigned in the ELSE section.

always@(select_i or in1_i)
begin
if(select_i == 1’b1)
begin
op_o = in1_i ;
end
end

Note: For those using Verilog-2001 compliant synthesis tool, it is better to use always@(*) for combinational constructs. Otherwise all the variables in the’ if’ and ‘else-if ‘conditions and those getting assigned (i.e. on the right-hand side of the assignment) within the block have to be added.

c. Missing ‘default’ statement in ‘case’ block:

always@(*) begin case(select_i) 1’b0 : op_i = in1_i ; endcase end

d. Using combinational loops:

always@(*) begin if(en_i ) data_o = in_i ; else data_o = data_o ; end

Such combinational loops would create a latch.