diff --git a/ADL/metrics/alderlake_metrics_goldencove_core.json b/ADL/metrics/alderlake_metrics_goldencove_core.json index d72eec5d..cbe7afe5 100644 --- a/ADL/metrics/alderlake_metrics_goldencove_core.json +++ b/ADL/metrics/alderlake_metrics_goldencove_core.json @@ -2,7 +2,7 @@ "Header": { "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.", "Info": "Performance Monitoring Metrics for 12th and 13th Generation Intel(R) Core(TM) Processor0", - "DatePublished": "11/15/2024", + "DatePublished": "12/02/2024", "Version": "1.0", "Legend": "", "TmaVersion": "5.01", @@ -368,7 +368,7 @@ } ], "Formula": "100 * ( ( a / ( a + b + c + d ) - e / ( f ) ) - ( 1 - ( 10 * ( g / ( f ) ) * ( max( ( h / ( a + b + c + d ) ) * ( 1 - i / ( j - k ) ) , 0.0001 ) ) / ( h / ( a + b + c + d ) ) ) ) * ( ( l / ( a + b + c + d ) - e / ( f ) ) ) * ( ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * m / ( n ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) - ( ( 1 - w / x ) * ( ( ( l / ( a + b + c + d ) - e / ( f ) ) ) * ( ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) * ( ( ( 1 - ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) ) * m / ( n ) ) + ( ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * m / ( n ) ) * ( max( ( h / ( a + b + c + d ) ) * ( 1 - i / ( j - k ) ) , 0.0001 ) ) / ( h / ( a + b + c + d ) ) ) / ( ( ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * m / ( n ) ) + ( ( 1 - ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) ) * m / ( n ) ) + ( q / ( n ) ) ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) + ( max( 0 , ( a / ( a + b + c + d ) - e / ( f ) ) - ( ( l / ( a + b + c + d ) - e / ( f ) ) ) ) ) * ( max( y , x / ( s / t ) ) / ( z if smt_on else ( n ) ) / 2 ) / ( ( ( a_a - a_b ) / ( z if smt_on else ( n ) ) / 2 ) + ( ( a_c - a_d ) / ( z if smt_on else ( n ) ) / 2 ) + ( ( a_e - a_f ) / ( z if smt_on else ( n ) ) / 2 ) + ( max( y , x / ( s / t ) ) / ( z if smt_on else ( n ) ) / 2 ) ) ) ) ) - ( 100 * ( ( l / ( a + b + c + d ) - e / ( f ) ) ) * ( ( p / ( n ) ) + ( o / ( n ) ) + ( q / ( n ) ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) )", - "BaseFormula": " 100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - inst_retired.rep_iteration / uops_retired.ms:c1 ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) ) ) - tma_big_code", + "BaseFormula": " 100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - inst_retired.rep_iteration / uops_retired.ms:c1 ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) ) ) - tma_bottleneck_big_code", "Category": "TMA", "CountDomain": "Scaled_Slots", "Threshold": { @@ -1898,7 +1898,7 @@ } ], "Formula": "100 - ( ( 100 * ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( h / ( i ) ) + ( j / ( i ) ) + ( k / ( i ) ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) ) + ( 100 * ( ( b / ( b + c + d + e ) - f / ( g ) ) - ( 1 - ( 10 * ( r / ( g ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) ) * ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) - ( ( 1 - w / x ) * ( ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) * ( ( ( 1 - ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * l / ( i ) ) + ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) / ( ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) + ( ( 1 - ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * l / ( i ) ) + ( k / ( i ) ) ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) + ( max( 0 , ( b / ( b + c + d + e ) - f / ( g ) ) - ( ( a / ( b + c + d + e ) - f / ( g ) ) ) ) ) * ( max( y , x / ( n / o ) ) / ( z if smt_on else ( i ) ) / 2 ) / ( ( ( a_a - a_b ) / ( z if smt_on else ( i ) ) / 2 ) + ( ( a_c - a_d ) / ( z if smt_on else ( i ) ) / 2 ) + ( ( a_e - a_f ) / ( z if smt_on else ( i ) ) / 2 ) + ( max( y , x / ( n / o ) ) / ( z if smt_on else ( i ) ) / 2 ) ) ) ) ) - ( 100 * ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( h / ( i ) ) + ( j / ( i ) ) + ( k / ( i ) ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) ) ) + ( 100 * ( 1 - ( 10 * ( r / ( g ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) ) * ( ( s / ( b + c + d + e ) ) + ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) ) ) + ( 100 * ( ( ( a_g / ( b + c + d + e ) ) * ( ( ( a_h / ( i ) ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_h ) / ( i ) ) + ( ( a_h / ( i ) ) ) + ( a_l / ( i ) ) ) ) * ( ( ( min( i , a_m ) ) / ( i ) ) / ( ( ( min( i , a_m ) ) / ( i ) ) + ( ( min( i , a_n ) ) / ( i ) - ( ( min( i , a_m ) ) / ( i ) ) ) ) ) ) + ( ( a_g / ( b + c + d + e ) ) * ( ( ( a_k - a_h ) / ( i ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_h ) / ( i ) ) + ( ( a_h / ( i ) ) ) + ( a_l / ( i ) ) ) ) * ( ( ( a_o + a_p ) / ( i ) ) / ( ( ( ( ( 28 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_t * ( a_u / ( a_u + a_v ) ) ) + ( ( 27 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_w ) ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) + ( ( ( 27 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_z + a_t * ( 1 - ( a_u / ( a_u + a_v ) ) ) ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) + ( ( ( 12 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_a * ( 1 + ( a_x / a_y ) / 2 ) ) / ( i ) ) + ( ( a_o + a_p ) / ( i ) ) ) ) ) + ( ( a_g / ( b + c + d + e ) ) * ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_h ) / ( i ) ) + ( ( a_h / ( i ) ) ) + ( a_l / ( i ) ) ) ) * ( ( b_b / ( i ) ) / ( ( min( ( 7 ) * b_c + b_d , max( b_e - b_f , 0 ) ) / ( i ) ) + ( 13 * b_g / ( i ) ) + ( min( 2 * ( b_h - a_x - a_y ) * dependentloadsweight / 100 , max( b_e - b_f , 0 ) ) / ( i ) ) + ( ( 16 * max( 0 , b_j - b_k ) + ( b_j / b_l ) * ( ( 10 ) * b_m + ( min( i , b_n ) ) ) ) / ( i ) ) + ( ( b_o / b_p ) * b_q / ( i ) ) + ( b_b / ( i ) ) ) ) ) ) ) + ( 100 * ( ( ( a_g / ( b + c + d + e ) ) * ( ( ( a_h / ( i ) ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_h ) / ( i ) ) + ( ( a_h / ( i ) ) ) + ( a_l / ( i ) ) ) ) * ( ( ( min( i , a_n ) ) / ( i ) - ( ( min( i , a_m ) ) / ( i ) ) ) / ( ( ( min( i , a_m ) ) / ( i ) ) + ( ( min( i , a_n ) ) / ( i ) - ( ( min( i , a_m ) ) / ( i ) ) ) ) ) ) + ( ( a_g / ( b + c + d + e ) ) * ( ( ( a_k - a_h ) / ( i ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_h ) / ( i ) ) + ( ( a_h / ( i ) ) ) + ( a_l / ( i ) ) ) ) * ( ( ( ( 12 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_a * ( 1 + ( a_x / a_y ) / 2 ) ) / ( i ) ) / ( ( ( ( ( 28 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_t * ( a_u / ( a_u + a_v ) ) ) + ( ( 27 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_w ) ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) + ( ( ( 27 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_z + a_t * ( 1 - ( a_u / ( a_u + a_v ) ) ) ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) + ( ( ( 12 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_a * ( 1 + ( a_x / a_y ) / 2 ) ) / ( i ) ) + ( ( a_o + a_p ) / ( i ) ) ) ) ) + ( ( a_g / ( b + c + d + e ) ) * ( ( a_j - a_k ) / ( i ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_h ) / ( i ) ) + ( ( a_h / ( i ) ) ) + ( a_l / ( i ) ) ) ) + ( ( a_g / ( b + c + d + e ) ) * ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_h ) / ( i ) ) + ( ( a_h / ( i ) ) ) + ( a_l / ( i ) ) ) ) * ( ( min( 2 * ( b_h - a_x - a_y ) * dependentloadsweight / 100 , max( b_e - b_f , 0 ) ) / ( i ) ) / ( ( min( ( 7 ) * b_c + b_d , max( b_e - b_f , 0 ) ) / ( i ) ) + ( 13 * b_g / ( i ) ) + ( min( 2 * ( b_h - a_x - a_y ) * dependentloadsweight / 100 , max( b_e - b_f , 0 ) ) / ( i ) ) + ( ( 16 * max( 0 , b_j - b_k ) + ( b_j / b_l ) * ( ( 10 ) * b_m + ( min( i , b_n ) ) ) ) / ( i ) ) + ( ( b_o / b_p ) * b_q / ( i ) ) + ( b_b / ( i ) ) ) ) ) + ( ( a_g / ( b + c + d + e ) ) * ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_h ) / ( i ) ) + ( ( a_h / ( i ) ) ) + ( a_l / ( i ) ) ) ) * ( ( ( 16 * max( 0 , b_j - b_k ) + ( b_j / b_l ) * ( ( 10 ) * b_m + ( min( i , b_n ) ) ) ) / ( i ) ) / ( ( min( ( 7 ) * b_c + b_d , max( b_e - b_f , 0 ) ) / ( i ) ) + ( 13 * b_g / ( i ) ) + ( min( 2 * ( b_h - a_x - a_y ) * dependentloadsweight / 100 , max( b_e - b_f , 0 ) ) / ( i ) ) + ( ( 16 * max( 0 , b_j - b_k ) + ( b_j / b_l ) * ( ( 10 ) * b_m + ( min( i , b_n ) ) ) ) / ( i ) ) + ( ( b_o / b_p ) * b_q / ( i ) ) + ( b_b / ( i ) ) ) ) ) + ( ( a_g / ( b + c + d + e ) ) * ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_h ) / ( i ) ) + ( ( a_h / ( i ) ) ) + ( a_l / ( i ) ) ) ) * ( ( ( b_o / b_p ) * b_q / ( i ) ) / ( ( min( ( 7 ) * b_c + b_d , max( b_e - b_f , 0 ) ) / ( i ) ) + ( 13 * b_g / ( i ) ) + ( min( 2 * ( b_h - a_x - a_y ) * dependentloadsweight / 100 , max( b_e - b_f , 0 ) ) / ( i ) ) + ( ( 16 * max( 0 , b_j - b_k ) + ( b_j / b_l ) * ( ( 10 ) * b_m + ( min( i , b_n ) ) ) ) / ( i ) ) + ( ( b_o / b_p ) * b_q / ( i ) ) + ( b_b / ( i ) ) ) ) ) + ( ( a_g / ( b + c + d + e ) ) * ( ( a_l / ( i ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_h ) / ( i ) ) + ( ( a_h / ( i ) ) ) + ( a_l / ( i ) ) ) ) * ( ( b_r / ( z if smt_on else ( i ) ) ) / ( ( ( ( b_s * ( 10 ) * ( 1 - ( b_j / b_l ) ) ) + ( 1 - ( b_j / b_l ) ) * ( min( i , b_n ) ) ) / ( i ) ) + ( ( 28 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_t / ( i ) ) + ( b_r / ( z if smt_on else ( i ) ) ) + ( 9 * b_u / ( i ) ) + ( ( ( 7 ) * b_v + b_w ) / ( z if smt_on else ( i ) ) ) ) ) ) + ( ( a_g / ( b + c + d + e ) ) * ( ( a_l / ( i ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_h ) / ( i ) ) + ( ( a_h / ( i ) ) ) + ( a_l / ( i ) ) ) ) * ( ( ( ( b_s * ( 10 ) * ( 1 - ( b_j / b_l ) ) ) + ( 1 - ( b_j / b_l ) ) * ( min( i , b_n ) ) ) / ( i ) ) / ( ( ( ( b_s * ( 10 ) * ( 1 - ( b_j / b_l ) ) ) + ( 1 - ( b_j / b_l ) ) * ( min( i , b_n ) ) ) / ( i ) ) + ( ( 28 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_t / ( i ) ) + ( b_r / ( z if smt_on else ( i ) ) ) + ( 9 * b_u / ( i ) ) + ( ( ( 7 ) * b_v + b_w ) / ( z if smt_on else ( i ) ) ) ) ) ) ) ) + ( 100 * ( ( a_g / ( b + c + d + e ) ) * ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) / max( ( a_g / ( b + c + d + e ) ) , ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_h ) / ( i ) ) + ( ( a_h / ( i ) ) ) + ( a_l / ( i ) ) ) ) ) * ( ( min( ( 7 ) * b_c + b_d , max( b_e - b_f , 0 ) ) / ( i ) ) / max( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) , ( ( min( ( 7 ) * b_c + b_d , max( b_e - b_f , 0 ) ) / ( i ) ) + ( 13 * b_g / ( i ) ) + ( min( 2 * ( b_h - a_x - a_y ) * dependentloadsweight / 100 , max( b_e - b_f , 0 ) ) / ( i ) ) + ( ( 16 * max( 0 , b_j - b_k ) + ( b_j / b_l ) * ( ( 10 ) * b_m + ( min( i , b_n ) ) ) ) / ( i ) ) + ( ( b_o / b_p ) * b_q / ( i ) ) + ( b_b / ( i ) ) ) ) ) + ( ( a_g / ( b + c + d + e ) ) * ( ( a_l / ( i ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_h ) / ( i ) ) + ( ( a_h / ( i ) ) ) + ( a_l / ( i ) ) ) ) * ( ( ( ( 7 ) * b_v + b_w ) / ( z if smt_on else ( i ) ) ) / ( ( ( ( b_s * ( 10 ) * ( 1 - ( b_j / b_l ) ) ) + ( 1 - ( b_j / b_l ) ) * ( min( i , b_n ) ) ) / ( i ) ) + ( ( 28 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_t / ( i ) ) + ( b_r / ( z if smt_on else ( i ) ) ) + ( 9 * b_u / ( i ) ) + ( ( ( 7 ) * b_v + b_w ) / ( z if smt_on else ( i ) ) ) ) ) ) ) ) + ( 100 * ( ( a_g / ( b + c + d + e ) ) * ( ( ( ( a_k - a_h ) / ( i ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_h ) / ( i ) ) + ( ( a_h / ( i ) ) ) + ( a_l / ( i ) ) ) ) * ( ( ( ( ( 28 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_t * ( a_u / ( a_u + a_v ) ) ) + ( ( 27 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_w ) ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) + ( ( ( 27 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_z + a_t * ( 1 - ( a_u / ( a_u + a_v ) ) ) ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) ) / ( ( ( ( ( 28 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_t * ( a_u / ( a_u + a_v ) ) ) + ( ( 27 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_w ) ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) + ( ( ( 27 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_z + a_t * ( 1 - ( a_u / ( a_u + a_v ) ) ) ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) + ( ( ( 12 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_a * ( 1 + ( a_x / a_y ) / 2 ) ) / ( i ) ) + ( ( a_o + a_p ) / ( i ) ) ) + ( ( a_l / ( i ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_h ) / ( i ) ) + ( ( a_h / ( i ) ) ) + ( a_l / ( i ) ) ) ) * ( ( 28 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_t / ( i ) ) / ( ( ( ( ( b_s * ( 10 ) * ( 1 - ( b_j / b_l ) ) ) + ( 1 - ( b_j / b_l ) ) * ( min( i , b_n ) ) ) / ( i ) ) + ( ( 28 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_t / ( i ) ) + ( b_r / ( z if smt_on else ( i ) ) ) + ( 9 * b_u / ( i ) ) + ( ( ( 7 ) * b_v + b_w ) / ( z if smt_on else ( i ) ) ) ) - ( ( ( b_s * ( 10 ) * ( 1 - ( b_j / b_l ) ) ) + ( 1 - ( b_j / b_l ) ) * ( min( i , b_n ) ) ) / ( i ) ) ) ) + ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - b_x / v ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - b_x / v ) , 0.0001 ) ) ) ) ) ) + ( 100 * ( ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_g / ( b + c + d + e ) ) ) ) * ( b_y / ( i ) ) / ( ( b_y / ( i ) ) + ( b_z / ( i ) + ( c_a / ( i ) ) ) + ( ( ( ( c_b + max( c_c - b_z , 0 ) ) / ( i ) * ( c_d - a_i ) / ( i ) ) * ( i ) + ( c_e + ( d / ( b + c + d + e ) ) * c_f ) ) / ( i ) if ( b_y < ( c_d - a_i ) ) else ( c_e + ( d / ( b + c + d + e ) ) * c_f ) / ( i ) ) ) ) + ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_g / ( b + c + d + e ) ) ) ) * ( ( ( ( ( c_b + max( c_c - b_z , 0 ) ) / ( i ) * ( c_d - a_i ) / ( i ) ) * ( i ) + ( c_e + ( d / ( b + c + d + e ) ) * c_f ) ) / ( i ) if ( b_y < ( c_d - a_i ) ) else ( c_e + ( d / ( b + c + d + e ) ) * c_f ) / ( i ) ) / ( ( b_y / ( i ) ) + ( b_z / ( i ) + ( c_a / ( i ) ) ) + ( ( ( ( c_b + max( c_c - b_z , 0 ) ) / ( i ) * ( c_d - a_i ) / ( i ) ) * ( i ) + ( c_e + ( d / ( b + c + d + e ) ) * c_f ) ) / ( i ) if ( b_y < ( c_d - a_i ) ) else ( c_e + ( d / ( b + c + d + e ) ) * c_f ) / ( i ) ) ) ) * ( ( c_g / ( i ) ) / ( ( ( c_b + max( c_c - b_z , 0 ) ) / ( i ) * ( c_d - a_i ) / ( i ) ) + ( c_e / ( i ) ) + ( c_h / ( i ) ) + ( c_g / ( i ) ) ) ) ) ) ) + ( 100 * ( ( ( 1 - w / x ) * ( ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) * ( ( ( 1 - ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * l / ( i ) ) + ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) / ( ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) + ( ( 1 - ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * l / ( i ) ) + ( k / ( i ) ) ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) + ( max( 0 , ( b / ( b + c + d + e ) - f / ( g ) ) - ( ( a / ( b + c + d + e ) - f / ( g ) ) ) ) ) * ( max( y , x / ( n / o ) ) / ( z if smt_on else ( i ) ) / 2 ) / ( ( ( a_a - a_b ) / ( z if smt_on else ( i ) ) / 2 ) + ( ( a_c - a_d ) / ( z if smt_on else ( i ) ) / 2 ) + ( ( a_e - a_f ) / ( z if smt_on else ( i ) ) / 2 ) + ( max( y , x / ( n / o ) ) / ( z if smt_on else ( i ) ) / 2 ) ) ) ) + ( 10 * ( r / ( g ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) * ( s / ( b + c + d + e ) ) + ( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - b_x / v ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - b_x / v ) , 0.0001 ) ) ) ) + ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_g / ( b + c + d + e ) ) ) ) * ( ( b_z / ( i ) + ( c_a / ( i ) ) ) + c_c / ( i ) * ( ( c_b + max( c_c - b_z , 0 ) ) / ( i ) * ( c_d - a_i ) / ( i ) ) ) / ( ( b_y / ( i ) ) + ( b_z / ( i ) + ( c_a / ( i ) ) ) + ( ( ( ( c_b + max( c_c - b_z , 0 ) ) / ( i ) * ( c_d - a_i ) / ( i ) ) * ( i ) + ( c_e + ( d / ( b + c + d + e ) ) * c_f ) ) / ( i ) if ( b_y < ( c_d - a_i ) ) else ( c_e + ( d / ( b + c + d + e ) ) * c_f ) / ( i ) ) ) ) + ( ( ( ( r / ( g ) ) / ( ( max( 0 , ( c_i / ( b + c + d + e ) ) - ( r / ( g ) ) ) ) + ( r / ( g ) ) ) ) * ( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * c_j / ( g ) ) / ( r / ( g ) ) ) ) * ( c_i / ( b + c + d + e ) ) ) ) ) + ( 100 * ( ( c_k + 2 * c_l + c_m ) / ( g ) ) ) + ( 100 * ( ( d / ( b + c + d + e ) ) - ( ( c_k + 2 * c_l + c_m ) / ( g ) ) - ( ( ( ( r / ( g ) ) / ( ( max( 0 , ( c_i / ( b + c + d + e ) ) - ( r / ( g ) ) ) ) + ( r / ( g ) ) ) ) * ( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * c_j / ( g ) ) / ( r / ( g ) ) ) ) * ( c_i / ( b + c + d + e ) ) ) ) ) )", - "BaseFormula": " 100 - ( tma_big_code + tma_instruction_fetch_bw + tma_mispredictions + tma_cache_memory_bandwidth + tma_cache_memory_latency + tma_memory_data_tlbs + tma_memory_synchronization + tma_compute_bound_est + tma_irregular_overhead + tma_branching_overhead + tma_useful_work )", + "BaseFormula": " 100 - ( tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottleneck_mispredictions + tma_bottleneck_cache_memory_bandwidth + tma_bottleneck_cache_memory_latency + tma_bottleneck_memory_data_tlbs + tma_bottleneck_memory_synchronization + tma_bottleneck_compute_bound_est + tma_bottleneck_irregular_overhead + tma_bottleneck_branching_overhead + tma_bottleneck_useful_work )", "Category": "TMA", "CountDomain": "Scaled_Slots", "Threshold": { @@ -8411,11 +8411,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_Core_Bound_Likely" + "Value": "metric_TMA_Info_Botlnk_L0_Core_Bound_Likely" } ], "Formula": "a > 0.5", - "BaseFormula": "metric_TMA_Info_Botlnk_Core_Bound_Likely > 0.5", + "BaseFormula": "metric_TMA_Info_Botlnk_L0_Core_Bound_Likely > 0.5", "ThresholdIssues": "" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -9837,11 +9837,11 @@ }, { "Alias": "b", - "Value": "IPC" + "Value": "metric_TMA_Info_Thread_IPC" } ], "Formula": "a < 0.7 & b / 6 > 0.35", - "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & IPC / 6 > 0.35", + "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & metric_TMA_Info_Thread_IPC / 6 > 0.35", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -10224,11 +10224,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_DSB_Misses" + "Value": "metric_TMA_Info_Botlnk_L2_DSB_Misses" } ], "Formula": "a > 10", - "BaseFormula": "metric_TMA_Info_Botlnk_DSB_Misses > 10", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_DSB_Misses > 10", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -10337,11 +10337,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_DSB_Bandwidth" + "Value": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth" } ], "Formula": "a > 10", - "BaseFormula": "metric_TMA_Info_Botlnk_DSB_Bandwidth > 10", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth > 10", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -10433,11 +10433,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_IC_Misses" + "Value": "metric_TMA_Info_Botlnk_L2_IC_Misses" } ], "Formula": "a > 5", - "BaseFormula": "metric_TMA_Info_Botlnk_IC_Misses > 5", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_IC_Misses > 5", "ThresholdIssues": "$issueFL" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -10722,7 +10722,7 @@ ], "Constants": [], "Formula": "( 100 * ( 1 - ( 10 * ( a / ( b ) ) * ( max( ( c / ( d + e + f + g ) ) * ( 1 - h / ( i - j ) ) , 0.0001 ) ) / ( c / ( d + e + f + g ) ) ) ) * ( ( c / ( d + e + f + g ) ) + ( ( k / ( d + e + f + g ) - l / ( b ) ) ) * ( ( ( c / ( d + e + f + g ) ) / ( max( 1 - ( ( d / ( d + e + f + g ) - l / ( b ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) ) * m / ( n ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) ) ) * ( b ) / ( 6 ) / h / 100", - "BaseFormula": " tma_mispredictions * tma_info_thread_slots / ( 6 ) / br_misp_retired.all_branches / 100", + "BaseFormula": " tma_bottleneck_mispredictions * tma_info_thread_slots / ( 6 ) / br_misp_retired.all_branches / 100", "Category": "TMA", "CountDomain": "Core_Metric", "Threshold": { @@ -11480,11 +11480,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Memory_Page_Walks_Utilization" + "Value": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization" } ], "Formula": "a > 0.5", - "BaseFormula": "metric_TMA_Info_Memory_Page_Walks_Utilization > 0.5", + "BaseFormula": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization > 0.5", "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", @@ -11734,11 +11734,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Memory_Useless_HWPF" + "Value": "metric_TMA_Info_Memory_Prefetches_Useless_HWPF" } ], "Formula": "a > 0.15", - "BaseFormula": "metric_TMA_Info_Memory_Useless_HWPF > 0.15", + "BaseFormula": "metric_TMA_Info_Memory_Prefetches_Useless_HWPF > 0.15", "ThresholdIssues": "" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", diff --git a/ADL/metrics/perf/alderlake_metrics_goldencove_core_perf.json b/ADL/metrics/perf/alderlake_metrics_goldencove_core_perf.json index b2bdf6c4..3418ff89 100644 --- a/ADL/metrics/perf/alderlake_metrics_goldencove_core_perf.json +++ b/ADL/metrics/perf/alderlake_metrics_goldencove_core_perf.json @@ -20,7 +20,7 @@ }, { "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the back-end)", - "MetricExpr": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\\,cmask\\=0x1@ ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) ) ) - tma_big_code", + "MetricExpr": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\\,cmask\\=0x1@ ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) ) ) - tma_bottleneck_big_code", "MetricGroup": "BvFB;Fed;FetchBW;Frontend;TopdownL1;tma_L1_group;Default;Scaled_Slots", "MetricName": "tma_bottleneck_instruction_fetch_bw", "MetricThreshold": "tma_bottleneck_instruction_fetch_bw > 20", @@ -89,7 +89,7 @@ }, { "BriefDescription": "Total pipeline cost of remaining bottlenecks in the back-end", - "MetricExpr": "100 - ( tma_big_code + tma_instruction_fetch_bw + tma_mispredictions + tma_cache_memory_bandwidth + tma_cache_memory_latency + tma_memory_data_tlbs + tma_memory_synchronization + tma_compute_bound_est + tma_irregular_overhead + tma_branching_overhead + tma_useful_work )", + "MetricExpr": "100 - ( tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottleneck_mispredictions + tma_bottleneck_cache_memory_bandwidth + tma_bottleneck_cache_memory_latency + tma_bottleneck_memory_data_tlbs + tma_bottleneck_memory_synchronization + tma_bottleneck_compute_bound_est + tma_bottleneck_irregular_overhead + tma_bottleneck_branching_overhead + tma_bottleneck_useful_work )", "MetricGroup": "BvOB;Cor;Offcore;TopdownL1;tma_L1_group;Default;Scaled_Slots", "MetricName": "tma_bottleneck_other_bottlenecks", "MetricThreshold": "tma_bottleneck_other_bottlenecks > 20", @@ -1099,7 +1099,7 @@ "MetricExpr": "100 * ( 1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1 ) if tma_info_system_smt_2t_utilization > 0.5 else 0", "MetricGroup": "Cor;SMT;Metric", "MetricName": "tma_info_botlnk_l0_core_bound_likely", - "MetricThreshold": "tma_info_botlnk_core_bound_likely > 0.5" + "MetricThreshold": "tma_info_botlnk_l0_core_bound_likely > 0.5" }, { "BriefDescription": "Instructions Per Cycle (per Logical Processor)", @@ -1142,7 +1142,7 @@ }, { "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor", - "MetricExpr": "tma_info_thread_slots / ( TOPDOWN.SLOTS / 2 ) if #SMT_on else 1", + "MetricExpr": "tma_info_thread_slots / ( slots / 2 ) if #SMT_on else 1", "MetricGroup": "SMT;TmaL1;TopdownL1;tma_L1_group;Metric", "MetricName": "tma_info_thread_slots_utilization" }, @@ -1361,7 +1361,7 @@ "MetricExpr": "IDQ.DSB_UOPS / ( UOPS_ISSUED.ANY )", "MetricGroup": "DSB;Fed;FetchBW;Metric;tma_issueFB", "MetricName": "tma_info_frontend_dsb_coverage", - "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & ipc / 6 > 0.35", + "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 6 > 0.35", "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1419,7 +1419,7 @@ "MetricExpr": "100 * ( tma_fetch_latency * tma_dsb_switches / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_mite / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) )", "MetricGroup": "DSBmiss;Fed;Scaled_Slots;tma_issueFB", "MetricName": "tma_info_botlnk_l2_dsb_misses", - "MetricThreshold": "tma_info_botlnk_dsb_misses > 10", + "MetricThreshold": "tma_info_botlnk_l2_dsb_misses > 10", "PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1427,7 +1427,7 @@ "MetricExpr": "100 * ( tma_frontend_bound * ( tma_fetch_bandwidth / ( tma_fetch_latency + tma_fetch_bandwidth ) ) * ( tma_dsb / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) )", "MetricGroup": "DSB;Fed;FetchBW;Scaled_Slots;tma_issueFB", "MetricName": "tma_info_botlnk_l2_dsb_bandwidth", - "MetricThreshold": "tma_info_botlnk_dsb_bandwidth > 10", + "MetricThreshold": "tma_info_botlnk_l2_dsb_bandwidth > 10", "PublicDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1435,7 +1435,7 @@ "MetricExpr": "100 * ( tma_fetch_latency * tma_icache_misses / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) )", "MetricGroup": "Fed;FetchLat;IcMiss;Scaled_Slots;tma_issueFL", "MetricName": "tma_info_botlnk_l2_ic_misses", - "MetricThreshold": "tma_info_botlnk_ic_misses > 5", + "MetricThreshold": "tma_info_botlnk_l2_ic_misses > 5", "PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck." }, { @@ -1475,7 +1475,7 @@ }, { "BriefDescription": "Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricExpr": "tma_mispredictions * tma_info_thread_slots / ( 6 ) / BR_MISP_RETIRED.ALL_BRANCHES / 100", + "MetricExpr": "tma_bottleneck_mispredictions * tma_info_thread_slots / ( 6 ) / BR_MISP_RETIRED.ALL_BRANCHES / 100", "MetricGroup": "Bad;BrMispredicts;Core_Metric;tma_issueBM", "MetricName": "tma_info_bad_spec_branch_misprediction_cost", "PublicDescription": "Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_bottleneck_mispredictions, tma_branch_mispredicts, tma_mispredicts_resteers." @@ -1618,7 +1618,7 @@ "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 4 * tma_info_core_core_clks )", "MetricGroup": "Mem;MemoryTLB;Core_Metric", "MetricName": "tma_info_memory_tlb_page_walks_utilization", - "MetricThreshold": "tma_info_memory_page_walks_utilization > 0.5" + "MetricThreshold": "tma_info_memory_tlb_page_walks_utilization > 0.5" }, { "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", @@ -1667,7 +1667,7 @@ "MetricExpr": "L2_LINES_OUT.USELESS_HWPF / ( L2_LINES_OUT.SILENT + L2_LINES_OUT.NON_SILENT )", "MetricGroup": "Prefetches;Metric", "MetricName": "tma_info_memory_prefetches_useless_hwpf", - "MetricThreshold": "tma_info_memory_useless_hwpf > 0.15" + "MetricThreshold": "tma_info_memory_prefetches_useless_hwpf > 0.15" }, { "BriefDescription": "Average Latency for L2 cache miss demand Loads", diff --git a/ARL/metrics/arrowlake_metrics_lioncove_core.json b/ARL/metrics/arrowlake_metrics_lioncove_core.json index 4edca423..a7823b14 100644 --- a/ARL/metrics/arrowlake_metrics_lioncove_core.json +++ b/ARL/metrics/arrowlake_metrics_lioncove_core.json @@ -2,7 +2,7 @@ "Header": { "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.", "Info": "Performance Monitoring Metrics for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture0", - "DatePublished": "11/15/2024", + "DatePublished": "12/02/2024", "Version": "1.0", "Legend": "", "TmaVersion": "5.01", @@ -319,7 +319,7 @@ ], "Constants": [], "Formula": "100 * ( ( a / ( a + b + c + d ) ) - ( 1 - ( 10 * ( e / ( f ) ) * ( max( ( g / ( a + b + c + d ) ) * ( 1 - h / ( i - j ) ) , 0.0001 ) ) / ( g / ( a + b + c + d ) ) ) ) * ( k / ( a + b + c + d ) ) * ( ( ( g / ( a + b + c + d ) ) / ( b / ( a + b + c + d ) ) ) * l / ( m ) ) / ( ( n / ( m ) ) + ( o / ( m ) ) + ( l / ( m ) + ( p / ( m ) ) ) + ( ( 3 ) * q / ( m ) ) + ( r / ( m ) ) + ( s / ( m ) ) ) - ( ( 1 - t / u ) * ( ( k / ( a + b + c + d ) ) * ( ( ( 3 ) * q / ( m ) ) + ( l / ( m ) + ( p / ( m ) ) ) * ( ( ( 1 - ( ( g / ( a + b + c + d ) ) / ( b / ( a + b + c + d ) ) ) ) * l / ( m ) ) + ( ( ( g / ( a + b + c + d ) ) / ( b / ( a + b + c + d ) ) ) * l / ( m ) ) * ( max( ( g / ( a + b + c + d ) ) * ( 1 - h / ( i - j ) ) , 0.0001 ) ) / ( g / ( a + b + c + d ) ) ) / ( ( ( ( g / ( a + b + c + d ) ) / ( b / ( a + b + c + d ) ) ) * l / ( m ) ) + ( ( 1 - ( ( g / ( a + b + c + d ) ) / ( b / ( a + b + c + d ) ) ) ) * l / ( m ) ) + ( p / ( m ) ) ) ) / ( ( n / ( m ) ) + ( o / ( m ) ) + ( l / ( m ) + ( p / ( m ) ) ) + ( ( 3 ) * q / ( m ) ) + ( r / ( m ) ) + ( s / ( m ) ) ) + ( max( 0 , ( a / ( a + b + c + d ) ) - ( k / ( a + b + c + d ) ) ) ) * ( v / ( m ) ) / ( ( ( w / ( m ) + x / ( y + x ) * ( z - a_a ) ) / ( m ) ) + ( ( a_b + y / ( y + x ) * ( z - a_a ) ) / ( m ) ) + ( a_c / ( m ) ) + ( v / ( m ) ) ) ) ) ) - ( 100 * ( k / ( a + b + c + d ) ) * ( ( o / ( m ) ) + ( n / ( m ) ) + ( p / ( m ) ) ) / ( ( n / ( m ) ) + ( o / ( m ) ) + ( l / ( m ) + ( p / ( m ) ) ) + ( ( 3 ) * q / ( m ) ) + ( r / ( m ) ) + ( s / ( m ) ) ) )", - "BaseFormula": " 100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - inst_retired.rep_iteration / uops_retired.ms:c1 ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) ) ) - tma_big_code", + "BaseFormula": " 100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - inst_retired.rep_iteration / uops_retired.ms:c1 ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) ) ) - tma_bottleneck_big_code", "Category": "TMA", "CountDomain": "Scaled_Slots", "Threshold": { @@ -8234,11 +8234,11 @@ }, { "Alias": "b", - "Value": "IPC" + "Value": "metric_TMA_Info_Thread_IPC" } ], "Formula": "a < 0.7 & b / 8 > 0.35", - "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & IPC / 8 > 0.35", + "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & metric_TMA_Info_Thread_IPC / 8 > 0.35", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -8706,11 +8706,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_DSB_Misses" + "Value": "metric_TMA_Info_Botlnk_L2_DSB_Misses" } ], "Formula": "a > 10", - "BaseFormula": "metric_TMA_Info_Botlnk_DSB_Misses > 10", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_DSB_Misses > 10", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -8790,11 +8790,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_DSB_Bandwidth" + "Value": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth" } ], "Formula": "a > 10", - "BaseFormula": "metric_TMA_Info_Botlnk_DSB_Bandwidth > 10", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth > 10", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -8870,11 +8870,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_IC_Misses" + "Value": "metric_TMA_Info_Botlnk_L2_IC_Misses" } ], "Formula": "a > 5", - "BaseFormula": "metric_TMA_Info_Botlnk_IC_Misses > 5", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_IC_Misses > 5", "ThresholdIssues": "$issueFL" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -9171,7 +9171,7 @@ ], "Constants": [], "Formula": "( 100 * ( 1 - ( 10 * ( a / ( b ) ) * ( max( ( c / ( d + e + f + g ) ) * ( 1 - h / ( i - j ) ) , 0.0001 ) ) / ( c / ( d + e + f + g ) ) ) ) * ( ( c / ( d + e + f + g ) ) + ( k / ( d + e + f + g ) ) * ( ( ( c / ( d + e + f + g ) ) / ( e / ( d + e + f + g ) ) ) * l / ( m ) ) / ( ( n / ( m ) ) + ( o / ( m ) ) + ( l / ( m ) + ( p / ( m ) ) ) + ( ( 3 ) * q / ( m ) ) + ( r / ( m ) ) + ( s / ( m ) ) ) ) ) * ( b ) / ( 8 ) / h / 100", - "BaseFormula": " tma_mispredictions * tma_info_thread_slots / ( 8 ) / br_misp_retired.all_branches / 100", + "BaseFormula": " tma_bottleneck_mispredictions * tma_info_thread_slots / ( 8 ) / br_misp_retired.all_branches / 100", "Category": "TMA", "CountDomain": "Core_Metric", "Threshold": { @@ -9966,11 +9966,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Memory_Page_Walks_Utilization" + "Value": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization" } ], "Formula": "a > 0.5", - "BaseFormula": "metric_TMA_Info_Memory_Page_Walks_Utilization > 0.5", + "BaseFormula": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization > 0.5", "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", @@ -10096,11 +10096,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Memory_Load_STLB_Miss_Ret" + "Value": "metric_TMA_Info_Memory_TLB_Load_STLB_Miss_Ret" } ], "Formula": "a > 0.05", - "BaseFormula": "metric_TMA_Info_Memory_Load_STLB_Miss_Ret > 0.05", + "BaseFormula": "metric_TMA_Info_Memory_TLB_Load_STLB_Miss_Ret > 0.05", "ThresholdIssues": "" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -10136,11 +10136,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Memory_Store_STLB_Miss_Ret" + "Value": "metric_TMA_Info_Memory_TLB_Store_STLB_Miss_Ret" } ], "Formula": "a > 0.05", - "BaseFormula": "metric_TMA_Info_Memory_Store_STLB_Miss_Ret > 0.05", + "BaseFormula": "metric_TMA_Info_Memory_TLB_Store_STLB_Miss_Ret > 0.05", "ThresholdIssues": "" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -10176,11 +10176,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Memory_Useless_HWPF" + "Value": "metric_TMA_Info_Memory_Prefetches_Useless_HWPF" } ], "Formula": "a > 0.15", - "BaseFormula": "metric_TMA_Info_Memory_Useless_HWPF > 0.15", + "BaseFormula": "metric_TMA_Info_Memory_Prefetches_Useless_HWPF > 0.15", "ThresholdIssues": "" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", diff --git a/ARL/metrics/perf/arrowlake_metrics_lioncove_core_perf.json b/ARL/metrics/perf/arrowlake_metrics_lioncove_core_perf.json index b533b805..6a0776da 100644 --- a/ARL/metrics/perf/arrowlake_metrics_lioncove_core_perf.json +++ b/ARL/metrics/perf/arrowlake_metrics_lioncove_core_perf.json @@ -20,7 +20,7 @@ }, { "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the back-end)", - "MetricExpr": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\\,cmask\\=0x1@ ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) ) ) - tma_big_code", + "MetricExpr": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\\,cmask\\=0x1@ ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) ) ) - tma_bottleneck_big_code", "MetricGroup": "BvFB;Fed;FetchBW;Frontend;TopdownL1;tma_L1_group;Default;Scaled_Slots", "MetricName": "tma_bottleneck_instruction_fetch_bw", "MetricThreshold": "tma_bottleneck_instruction_fetch_bw > 20", @@ -1301,7 +1301,7 @@ "MetricExpr": "IDQ.DSB_UOPS / ( UOPS_ISSUED.ANY )", "MetricGroup": "DSB;Fed;FetchBW;Metric;tma_issueFB", "MetricName": "tma_info_frontend_dsb_coverage", - "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & ipc / 8 > 0.35", + "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 8 > 0.35", "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1379,7 +1379,7 @@ "MetricExpr": "100 * ( tma_fetch_latency * tma_dsb_switches / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_mite / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) )", "MetricGroup": "DSBmiss;Fed;Scaled_Slots;tma_issueFB", "MetricName": "tma_info_botlnk_l2_dsb_misses", - "MetricThreshold": "tma_info_botlnk_dsb_misses > 10", + "MetricThreshold": "tma_info_botlnk_l2_dsb_misses > 10", "PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1387,7 +1387,7 @@ "MetricExpr": "100 * ( tma_frontend_bound * ( tma_fetch_bandwidth / ( tma_fetch_latency + tma_fetch_bandwidth ) ) * ( tma_dsb / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) )", "MetricGroup": "DSB;Fed;FetchBW;Scaled_Slots;tma_issueFB", "MetricName": "tma_info_botlnk_l2_dsb_bandwidth", - "MetricThreshold": "tma_info_botlnk_dsb_bandwidth > 10", + "MetricThreshold": "tma_info_botlnk_l2_dsb_bandwidth > 10", "PublicDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1395,7 +1395,7 @@ "MetricExpr": "100 * ( tma_fetch_latency * tma_icache_misses / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) )", "MetricGroup": "Fed;FetchLat;IcMiss;Scaled_Slots;tma_issueFL", "MetricName": "tma_info_botlnk_l2_ic_misses", - "MetricThreshold": "tma_info_botlnk_ic_misses > 5", + "MetricThreshold": "tma_info_botlnk_l2_ic_misses > 5", "PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck." }, { @@ -1440,7 +1440,7 @@ }, { "BriefDescription": "Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricExpr": "tma_mispredictions * tma_info_thread_slots / ( 8 ) / BR_MISP_RETIRED.ALL_BRANCHES / 100", + "MetricExpr": "tma_bottleneck_mispredictions * tma_info_thread_slots / ( 8 ) / BR_MISP_RETIRED.ALL_BRANCHES / 100", "MetricGroup": "Bad;BrMispredicts;Core_Metric;tma_issueBM", "MetricName": "tma_info_bad_spec_branch_misprediction_cost", "PublicDescription": "Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_bottleneck_mispredictions, tma_branch_mispredicts, tma_mispredicts_resteers." @@ -1591,7 +1591,7 @@ "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 4 * tma_info_thread_clks )", "MetricGroup": "Mem;MemoryTLB;Core_Metric", "MetricName": "tma_info_memory_tlb_page_walks_utilization", - "MetricThreshold": "tma_info_memory_page_walks_utilization > 0.5" + "MetricThreshold": "tma_info_memory_tlb_page_walks_utilization > 0.5" }, { "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", @@ -1616,21 +1616,21 @@ "MetricExpr": "( MEM_INST_RETIRED.STLB_MISS_LOADS * cpu_core@MEM_INST_RETIRED.STLB_MISS_LOADS@R ) / tma_info_thread_clks", "MetricGroup": "Mem;MemoryTLB;Clocks_Retired", "MetricName": "tma_info_memory_tlb_load_stlb_miss_ret", - "MetricThreshold": "tma_info_memory_load_stlb_miss_ret > 0.05" + "MetricThreshold": "tma_info_memory_tlb_load_stlb_miss_ret > 0.05" }, { "BriefDescription": "This metric represents fraction of cycles the CPU retirement was stalled likely due to STLB misses by demand stores", "MetricExpr": "( MEM_INST_RETIRED.STLB_MISS_STORES * cpu_core@MEM_INST_RETIRED.STLB_MISS_STORES@R ) / tma_info_thread_clks", "MetricGroup": "Mem;MemoryTLB;Clocks_Retired", "MetricName": "tma_info_memory_tlb_store_stlb_miss_ret", - "MetricThreshold": "tma_info_memory_store_stlb_miss_ret > 0.05" + "MetricThreshold": "tma_info_memory_tlb_store_stlb_miss_ret > 0.05" }, { "BriefDescription": "Rate of L2 HW prefetched lines that were not used by demand accesses", "MetricExpr": "L2_LINES_OUT.USELESS_HWPF / ( L2_LINES_OUT.SILENT + L2_LINES_OUT.NON_SILENT )", "MetricGroup": "Prefetches;Metric", "MetricName": "tma_info_memory_prefetches_useless_hwpf", - "MetricThreshold": "tma_info_memory_useless_hwpf > 0.15" + "MetricThreshold": "tma_info_memory_prefetches_useless_hwpf > 0.15" }, { "BriefDescription": "Average Latency for L2 cache miss demand Loads", diff --git a/BDW/metrics/broadwell_metrics.json b/BDW/metrics/broadwell_metrics.json index bd8d4e1d..2d6da494 100644 --- a/BDW/metrics/broadwell_metrics.json +++ b/BDW/metrics/broadwell_metrics.json @@ -2,7 +2,7 @@ "Header": { "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.", "Info": "Performance Monitoring Metrics for 5th Generation Intel(R) Core(TM) Processor0", - "DatePublished": "11/15/2024", + "DatePublished": "12/02/2024", "Version": "1.0", "Legend": "", "TmaVersion": "5.01", @@ -5090,11 +5090,11 @@ }, { "Alias": "b", - "Value": "IPC" + "Value": "metric_TMA_Info_Thread_IPC" } ], "Formula": "a < 0.7 & b / 4 > 0.35", - "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & IPC / 4 > 0.35", + "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & metric_TMA_Info_Thread_IPC / 4 > 0.35", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", @@ -5700,11 +5700,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Memory_Page_Walks_Utilization" + "Value": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization" } ], "Formula": "a > 0.5", - "BaseFormula": "metric_TMA_Info_Memory_Page_Walks_Utilization > 0.5", + "BaseFormula": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization > 0.5", "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", diff --git a/BDW/metrics/perf/broadwell_metrics_perf.json b/BDW/metrics/perf/broadwell_metrics_perf.json index 1c0dcf51..cd4268fc 100644 --- a/BDW/metrics/perf/broadwell_metrics_perf.json +++ b/BDW/metrics/perf/broadwell_metrics_perf.json @@ -814,7 +814,7 @@ "MetricExpr": "IDQ.DSB_UOPS / ( ( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )", "MetricGroup": "DSB;Fed;FetchBW;Metric;tma_issueFB", "MetricName": "tma_info_frontend_dsb_coverage", - "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & ipc / 4 > 0.35", + "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 4 > 0.35", "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -927,7 +927,7 @@ "MetricExpr": "( cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=0x1@ + cpu@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=0x1@ + cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=0x1@ + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / tma_info_core_core_clks", "MetricGroup": "Mem;MemoryTLB;Core_Metric", "MetricName": "tma_info_memory_tlb_page_walks_utilization", - "MetricThreshold": "tma_info_memory_page_walks_utilization > 0.5" + "MetricThreshold": "tma_info_memory_tlb_page_walks_utilization > 0.5" }, { "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", diff --git a/BDX/metrics/broadwellx_metrics.json b/BDX/metrics/broadwellx_metrics.json index b6cf4348..612b1a78 100644 --- a/BDX/metrics/broadwellx_metrics.json +++ b/BDX/metrics/broadwellx_metrics.json @@ -2,7 +2,7 @@ "Header": { "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.", "Info": "Performance Monitoring Metrics for Intel(R) Xeon(R) Processor E5 v4 Family Based on the Broadwell Microarchitecture0", - "DatePublished": "11/15/2024", + "DatePublished": "12/02/2024", "Version": "1.0", "Legend": "", "TmaVersion": "5.01", @@ -6152,11 +6152,11 @@ }, { "Alias": "b", - "Value": "IPC" + "Value": "metric_TMA_Info_Thread_IPC" } ], "Formula": "a < 0.7 & b / 4 > 0.35", - "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & IPC / 4 > 0.35", + "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & metric_TMA_Info_Thread_IPC / 4 > 0.35", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", @@ -6762,11 +6762,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Memory_Page_Walks_Utilization" + "Value": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization" } ], "Formula": "a > 0.5", - "BaseFormula": "metric_TMA_Info_Memory_Page_Walks_Utilization > 0.5", + "BaseFormula": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization > 0.5", "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", diff --git a/BDX/metrics/perf/broadwellx_metrics_perf.json b/BDX/metrics/perf/broadwellx_metrics_perf.json index c9971d74..14ae11ec 100644 --- a/BDX/metrics/perf/broadwellx_metrics_perf.json +++ b/BDX/metrics/perf/broadwellx_metrics_perf.json @@ -1083,7 +1083,7 @@ "MetricExpr": "IDQ.DSB_UOPS / ( ( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )", "MetricGroup": "DSB;Fed;FetchBW;Metric;tma_issueFB", "MetricName": "tma_info_frontend_dsb_coverage", - "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & ipc / 4 > 0.35", + "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 4 > 0.35", "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1196,7 +1196,7 @@ "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / ( 2 * tma_info_core_core_clks )", "MetricGroup": "Mem;MemoryTLB;Core_Metric", "MetricName": "tma_info_memory_tlb_page_walks_utilization", - "MetricThreshold": "tma_info_memory_page_walks_utilization > 0.5" + "MetricThreshold": "tma_info_memory_tlb_page_walks_utilization > 0.5" }, { "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", diff --git a/CLX/metrics/cascadelakex_metrics.json b/CLX/metrics/cascadelakex_metrics.json index 13de24dc..55f36ae8 100644 --- a/CLX/metrics/cascadelakex_metrics.json +++ b/CLX/metrics/cascadelakex_metrics.json @@ -2,7 +2,7 @@ "Header": { "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.", "Info": "Performance Monitoring Metrics for 2nd Generation Intel(R) Xeon(R) Processor Scalable Family based on Cascade Lake product0", - "DatePublished": "11/15/2024", + "DatePublished": "12/02/2024", "Version": "1.0", "Legend": "", "TmaVersion": "5.01", @@ -1249,7 +1249,7 @@ } ], "Formula": "100 * ( ( a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( 1 - ( 10 * ( ( ( d ) / e ) * f / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( max( ( ( g / ( g + h ) ) * ( ( e - ( d ) + ( 4 ) * ( ( i / 2 ) if smt_on else j ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( 1 - g / ( k - h ) ) , 0.0001 ) ) / ( ( g / ( g + h ) ) * ( ( e - ( d ) + ( 4 ) * ( ( i / 2 ) if smt_on else j ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) ) * ( ( 4 ) * l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( ( g / ( g + h ) ) * m / ( c ) ) / ( ( ( n + 2 * o ) / ( c ) ) + ( p / ( c ) ) + ( m / ( c ) + ( 9 ) * q / ( c ) ) + ( ( 2 ) * r / ( c ) ) + ( s / ( c ) ) + ( t / ( c ) ) ) - ( ( ( ( ( ( d ) / e ) * f / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) / ( ( ( ( ( d ) + u - v ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( d ) / e ) * f / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) + ( ( ( d ) / e ) * f / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( ( ( 34 ) * ( w + x ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) / ( ( ( d ) / e ) * f / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( ( 4 ) * l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( ( ( 2 ) * r / ( c ) ) + ( m / ( c ) + ( 9 ) * q / ( c ) ) * ( ( ( 1 - ( g / ( g + h ) ) ) * m / ( c ) ) + ( ( g / ( g + h ) ) * m / ( c ) ) * ( 10 * ( ( ( d ) / e ) * f / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( max( ( ( g / ( g + h ) ) * ( ( e - ( d ) + ( 4 ) * ( ( i / 2 ) if smt_on else j ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( 1 - g / ( k - h ) ) , 0.0001 ) ) / ( ( g / ( g + h ) ) * ( ( e - ( d ) + ( 4 ) * ( ( i / 2 ) if smt_on else j ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) ) / ( ( ( g / ( g + h ) ) * m / ( c ) ) + ( ( 1 - ( g / ( g + h ) ) ) * m / ( c ) ) + ( ( 9 ) * q / ( c ) ) ) ) / ( ( ( n + 2 * o ) / ( c ) ) + ( p / ( c ) ) + ( m / ( c ) + ( 9 ) * q / ( c ) ) + ( ( 2 ) * r / ( c ) ) + ( s / ( c ) ) + ( t / ( c ) ) ) ) ) - ( 100 * ( ( 4 ) * l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( ( p / ( c ) ) + ( ( n + 2 * o ) / ( c ) ) + ( ( 9 ) * q / ( c ) ) ) / ( ( ( n + 2 * o ) / ( c ) ) + ( p / ( c ) ) + ( m / ( c ) + ( 9 ) * q / ( c ) ) + ( ( 2 ) * r / ( c ) ) + ( s / ( c ) ) + ( t / ( c ) ) ) )", - "BaseFormula": " 100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( ( tma_microcode_sequencer / ( tma_few_uops_instructions + tma_microcode_sequencer ) ) * ( tma_assists / tma_microcode_sequencer ) ) * tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) ) ) - tma_big_code", + "BaseFormula": " 100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( ( tma_microcode_sequencer / ( tma_few_uops_instructions + tma_microcode_sequencer ) ) * ( tma_assists / tma_microcode_sequencer ) ) * tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) ) ) - tma_bottleneck_big_code", "Category": "TMA", "CountDomain": "Scaled_Slots", "Threshold": { @@ -2856,7 +2856,7 @@ } ], "Formula": "100 - ( ( 100 * ( ( 4 ) * a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( ( d / ( c ) ) + ( ( e + 2 * f ) / ( c ) ) + ( ( 9 ) * g / ( c ) ) ) / ( ( ( e + 2 * f ) / ( c ) ) + ( d / ( c ) ) + ( h / ( c ) + ( 9 ) * g / ( c ) ) + ( ( 2 ) * i / ( c ) ) + ( j / ( c ) ) + ( k / ( c ) ) ) ) + ( 100 * ( ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( 1 - ( 10 * ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( max( ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( 1 - p / ( t - q ) ) , 0.0001 ) ) / ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) ) * ( ( 4 ) * a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( ( p / ( p + q ) ) * h / ( c ) ) / ( ( ( e + 2 * f ) / ( c ) ) + ( d / ( c ) ) + ( h / ( c ) + ( 9 ) * g / ( c ) ) + ( ( 2 ) * i / ( c ) ) + ( j / ( c ) ) + ( k / ( c ) ) ) - ( ( ( ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) / ( ( ( ( ( m ) + u - v ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) + ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( ( ( 34 ) * ( w + x ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) / ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( ( 4 ) * a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( ( ( 2 ) * i / ( c ) ) + ( h / ( c ) + ( 9 ) * g / ( c ) ) * ( ( ( 1 - ( p / ( p + q ) ) ) * h / ( c ) ) + ( ( p / ( p + q ) ) * h / ( c ) ) * ( 10 * ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( max( ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( 1 - p / ( t - q ) ) , 0.0001 ) ) / ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) ) / ( ( ( p / ( p + q ) ) * h / ( c ) ) + ( ( 1 - ( p / ( p + q ) ) ) * h / ( c ) ) + ( ( 9 ) * g / ( c ) ) ) ) / ( ( ( e + 2 * f ) / ( c ) ) + ( d / ( c ) ) + ( h / ( c ) + ( 9 ) * g / ( c ) ) + ( ( 2 ) * i / ( c ) ) + ( j / ( c ) ) + ( k / ( c ) ) ) ) ) - ( 100 * ( ( 4 ) * a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( ( d / ( c ) ) + ( ( e + 2 * f ) / ( c ) ) + ( ( 9 ) * g / ( c ) ) ) / ( ( ( e + 2 * f ) / ( c ) ) + ( d / ( c ) ) + ( h / ( c ) + ( 9 ) * g / ( c ) ) + ( ( 2 ) * i / ( c ) ) + ( j / ( c ) ) + ( k / ( c ) ) ) ) ) + ( 100 * ( 1 - ( 10 * ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( max( ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( 1 - p / ( t - q ) ) , 0.0001 ) ) / ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) ) * ( ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) + ( ( 4 ) * a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( ( p / ( p + q ) ) * h / ( c ) ) / ( ( ( e + 2 * f ) / ( c ) ) + ( d / ( c ) ) + ( h / ( c ) + ( 9 ) * g / ( c ) ) + ( ( 2 ) * i / ( c ) ) + ( j / ( c ) ) + ( k / ( c ) ) ) ) ) + ( 100 * ( ( ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) / ( ( max( ( y - a_e ) / ( c ) , 0 ) ) + ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) + ( ( a_f - a_d ) / ( c ) ) + ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) + ( z / ( c ) ) ) ) * ( ( ( min( c , a_k ) ) / ( c ) ) / ( ( ( min( c , a_k ) ) / ( c ) ) + ( ( min( c , a_l ) ) / ( c ) - ( ( min( c , a_k ) ) / ( c ) ) ) ) ) ) + ( ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( ( ( a_f - a_d ) / ( c ) ) / ( ( max( ( y - a_e ) / ( c ) , 0 ) ) + ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) + ( ( a_f - a_d ) / ( c ) ) + ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) + ( z / ( c ) ) ) ) * ( ( ( ( a_m / 2 ) if smt_on else a_m ) / ( ( b / 2 ) if smt_on else ( c ) ) ) / ( ( ( ( ( 47.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_q * ( a_r / ( a_r + a_s ) ) ) + ( ( 47.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_t ) ) * ( 1 + ( a_h / a_i ) / 2 ) / ( c ) ) + ( ( ( 47.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_u + a_q * ( 1 - ( a_r / ( a_r + a_s ) ) ) ) * ( 1 + ( a_h / a_i ) / 2 ) / ( c ) ) + ( ( ( 20.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_v * ( 1 + ( a_h / a_i ) / 2 ) ) / ( c ) ) + ( ( ( a_m / 2 ) if smt_on else a_m ) / ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) + ( ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( ( max( ( y - a_e ) / ( c ) , 0 ) ) / ( ( max( ( y - a_e ) / ( c ) , 0 ) ) + ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) + ( ( a_f - a_d ) / ( c ) ) + ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) + ( z / ( c ) ) ) ) * ( ( ( a_w / ( a_x + a_y ) ) * a_j / ( c ) ) / ( ( min( ( 9 ) * a_z + b_a , max( b_b - b_c , 0 ) ) / ( c ) ) + ( 13 * b_d / ( c ) ) + ( min( 2 * ( b_e - a_y - a_x ) * dependentloadsweight / 100 , max( b_b - b_c , 0 ) ) / ( c ) ) + ( ( 12 * max( 0 , b_g - b_h ) + ( b_g / b_i ) * ( ( 11 ) * b_j + ( min( c , b_k ) ) ) ) / ( c ) ) + ( ( a_w / ( a_x + a_y ) ) * b_l / ( c ) ) + ( b_m / ( c ) ) + ( ( a_w / ( a_x + a_y ) ) * a_j / ( c ) ) ) ) ) ) ) + ( 100 * ( ( ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) / ( ( max( ( y - a_e ) / ( c ) , 0 ) ) + ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) + ( ( a_f - a_d ) / ( c ) ) + ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) + ( z / ( c ) ) ) ) * ( ( ( min( c , a_l ) ) / ( c ) - ( ( min( c , a_k ) ) / ( c ) ) ) / ( ( ( min( c , a_k ) ) / ( c ) ) + ( ( min( c , a_l ) ) / ( c ) - ( ( min( c , a_k ) ) / ( c ) ) ) ) ) ) + ( ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( ( ( a_f - a_d ) / ( c ) ) / ( ( max( ( y - a_e ) / ( c ) , 0 ) ) + ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) + ( ( a_f - a_d ) / ( c ) ) + ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) + ( z / ( c ) ) ) ) * ( ( ( ( 20.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_v * ( 1 + ( a_h / a_i ) / 2 ) ) / ( c ) ) / ( ( ( ( ( 47.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_q * ( a_r / ( a_r + a_s ) ) ) + ( ( 47.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_t ) ) * ( 1 + ( a_h / a_i ) / 2 ) / ( c ) ) + ( ( ( 47.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_u + a_q * ( 1 - ( a_r / ( a_r + a_s ) ) ) ) * ( 1 + ( a_h / a_i ) / 2 ) / ( c ) ) + ( ( ( 20.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_v * ( 1 + ( a_h / a_i ) / 2 ) ) / ( c ) ) + ( ( ( a_m / 2 ) if smt_on else a_m ) / ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) + ( ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) / ( ( max( ( y - a_e ) / ( c ) , 0 ) ) + ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) + ( ( a_f - a_d ) / ( c ) ) + ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) + ( z / ( c ) ) ) ) + ( ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( ( max( ( y - a_e ) / ( c ) , 0 ) ) / ( ( max( ( y - a_e ) / ( c ) , 0 ) ) + ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) + ( ( a_f - a_d ) / ( c ) ) + ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) + ( z / ( c ) ) ) ) * ( ( min( 2 * ( b_e - a_y - a_x ) * dependentloadsweight / 100 , max( b_b - b_c , 0 ) ) / ( c ) ) / ( ( min( ( 9 ) * a_z + b_a , max( b_b - b_c , 0 ) ) / ( c ) ) + ( 13 * b_d / ( c ) ) + ( min( 2 * ( b_e - a_y - a_x ) * dependentloadsweight / 100 , max( b_b - b_c , 0 ) ) / ( c ) ) + ( ( 12 * max( 0 , b_g - b_h ) + ( b_g / b_i ) * ( ( 11 ) * b_j + ( min( c , b_k ) ) ) ) / ( c ) ) + ( ( a_w / ( a_x + a_y ) ) * b_l / ( c ) ) + ( b_m / ( c ) ) + ( ( a_w / ( a_x + a_y ) ) * a_j / ( c ) ) ) ) ) + ( ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( ( max( ( y - a_e ) / ( c ) , 0 ) ) / ( ( max( ( y - a_e ) / ( c ) , 0 ) ) + ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) + ( ( a_f - a_d ) / ( c ) ) + ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) + ( z / ( c ) ) ) ) * ( ( ( 12 * max( 0 , b_g - b_h ) + ( b_g / b_i ) * ( ( 11 ) * b_j + ( min( c , b_k ) ) ) ) / ( c ) ) / ( ( min( ( 9 ) * a_z + b_a , max( b_b - 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( ( ( b_j * ( 11 ) * ( 1 - ( b_g / b_i ) ) ) + ( 1 - ( b_g / b_i ) ) * ( min( c , b_k ) ) ) / ( c ) ) ) ) + ( ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( 1 - ( max( ( ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( 1 - b_y / q ) , 0.0001 ) ) / ( ( max( ( ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( 1 - b_y / q ) , 0.0001 ) ) ) ) ) ) + ( 100 * ( ( ( ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( b_z / ( c ) ) / ( ( b_z / ( c ) ) + ( c_a / ( c ) ) + ( ( ( c_b / ( c ) ) * ( c ) + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) ) / ( c ) if ( b_z < ( a_a - y ) ) else ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) / ( c ) ) ) ) + ( ( ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( ( ( ( c_b / ( c ) ) * ( c ) + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) ) / ( c ) if ( b_z < ( a_a - y ) ) else ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) / ( c ) ) / ( ( b_z / ( c ) ) + ( c_a / ( c ) ) + ( ( ( c_b / ( c ) ) * ( c ) + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) ) / ( c ) if ( b_z < ( a_a - y ) ) else ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) / ( c ) ) ) ) * ( ( ( c_c / 2 if smt_on else c_c ) / ( ( b / 2 ) if smt_on else ( c ) ) ) / ( ( c_b / ( c ) ) + ( ( ( c_d - c_e ) / 2 if smt_on else a_b ) / ( ( b / 2 ) if smt_on else ( c ) ) ) + ( ( ( c_e - c_c ) / 2 if smt_on else a_c ) / ( ( b / 2 ) if smt_on else ( c ) ) ) + ( ( c_c / 2 if smt_on else c_c ) / ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) ) ) + ( 100 * ( ( ( ( ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) / ( ( ( ( ( m ) + u - v ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) + ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( ( ( 34 ) * ( w + x ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) / ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( ( 4 ) * a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( ( ( 2 ) * i / ( c ) ) + ( h / ( c ) + ( 9 ) * g / ( c ) ) * ( ( ( 1 - ( p / ( p + q ) ) ) * h / ( c ) ) + ( ( p / ( p + q ) ) * h / ( c ) ) * ( 10 * ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( max( ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( 1 - p / ( t - q ) ) , 0.0001 ) ) / ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) ) / ( ( ( p / ( p + q ) ) * h / ( c ) ) + ( ( 1 - ( p / ( p + q ) ) ) * h / ( c ) ) + ( ( 9 ) * g / ( c ) ) ) ) / ( ( ( e + 2 * f ) / ( c ) ) + ( d / ( c ) ) + ( h / ( c ) + ( 9 ) * g / ( c ) ) + ( ( 2 ) * i / ( c ) ) + ( j / ( c ) ) + ( k / ( c ) ) ) ) + ( 10 * ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( max( ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( 1 - p / ( t - q ) ) , 0.0001 ) ) / ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) + ( ( ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( max( ( ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( 1 - b_y / q ) , 0.0001 ) ) / ( ( max( ( ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( 1 - b_y / q ) , 0.0001 ) ) ) ) + ( ( ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( ( c_a / ( c ) ) + ( ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * c_f / ( c ) * ( c_b / ( c ) ) ) / ( ( b_z / ( c ) ) + ( c_a / ( c ) ) + ( ( ( c_b / ( c ) ) * ( c ) + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) ) / ( c ) if ( b_z < ( a_a - y ) ) else ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) / ( c ) ) ) ) + ( ( ( ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) / ( ( ( ( ( m ) + u - v ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) + ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( ( ( 34 ) * ( w + x ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) / ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( ( ( m ) + u - v ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) ) + ( 100 * ( ( c_g + 2 * c_h + c_i ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) + ( 100 * ( ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( c_g + 2 * c_h + c_i ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) / ( ( ( ( ( m ) + u - v ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) + ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( ( ( 34 ) * ( w + x ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) / ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( ( ( m ) + u - v ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) ) )", - "BaseFormula": " 100 - ( tma_big_code + tma_instruction_fetch_bw + tma_mispredictions + tma_cache_memory_bandwidth + tma_cache_memory_latency + tma_memory_data_tlbs + tma_memory_synchronization + tma_compute_bound_est + tma_irregular_overhead + tma_branching_overhead + tma_useful_work )", + "BaseFormula": " 100 - ( tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottleneck_mispredictions + tma_bottleneck_cache_memory_bandwidth + tma_bottleneck_cache_memory_latency + tma_bottleneck_memory_data_tlbs + tma_bottleneck_memory_synchronization + tma_bottleneck_compute_bound_est + tma_bottleneck_irregular_overhead + tma_bottleneck_branching_overhead + tma_bottleneck_useful_work )", "Category": "TMA", "CountDomain": "Scaled_Slots", "Threshold": { @@ -9358,11 +9358,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_Core_Bound_Likely" + "Value": "metric_TMA_Info_Botlnk_L0_Core_Bound_Likely" } ], "Formula": "a > 0.5", - "BaseFormula": "metric_TMA_Info_Botlnk_Core_Bound_Likely > 0.5", + "BaseFormula": "metric_TMA_Info_Botlnk_L0_Core_Bound_Likely > 0.5", "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", @@ -10666,11 +10666,11 @@ }, { "Alias": "b", - "Value": "IPC" + "Value": "metric_TMA_Info_Thread_IPC" } ], "Formula": "a < 0.7 & b / 4 > 0.35", - "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & IPC / 4 > 0.35", + "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & metric_TMA_Info_Thread_IPC / 4 > 0.35", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", @@ -10983,11 +10983,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_DSB_Misses" + "Value": "metric_TMA_Info_Botlnk_L2_DSB_Misses" } ], "Formula": "a > 10", - "BaseFormula": "metric_TMA_Info_Botlnk_DSB_Misses > 10", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_DSB_Misses > 10", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", @@ -11052,11 +11052,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_DSB_Bandwidth" + "Value": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth" } ], "Formula": "a > 10", - "BaseFormula": "metric_TMA_Info_Botlnk_DSB_Bandwidth > 10", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth > 10", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", @@ -11133,11 +11133,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_IC_Misses" + "Value": "metric_TMA_Info_Botlnk_L2_IC_Misses" } ], "Formula": "a > 5", - "BaseFormula": "metric_TMA_Info_Botlnk_IC_Misses > 5", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_IC_Misses > 5", "ThresholdIssues": "$issueFL" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", @@ -11319,7 +11319,7 @@ } ], "Formula": "( 100 * ( 1 - ( 10 * ( ( ( a ) / b ) * c / ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) ) * ( max( ( ( f / ( f + g ) ) * ( ( b - ( a ) + ( 4 ) * ( ( h / 2 ) if smt_on else i ) ) / ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) ) ) * ( 1 - f / ( j - g ) ) , 0.0001 ) ) / ( ( f / ( f + g ) ) * ( ( b - ( a ) + ( 4 ) * ( ( h / 2 ) if smt_on else i ) ) / ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) ) ) ) ) * ( ( ( f / ( f + g ) ) * ( ( b - ( a ) + ( 4 ) * ( ( h / 2 ) if smt_on else i ) ) / ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) ) ) + ( ( 4 ) * k / ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) ) * ( ( f / ( f + g ) ) * l / ( e ) ) / ( ( ( m + 2 * n ) / ( e ) ) + ( o / ( e ) ) + ( l / ( e ) + ( 9 ) * p / ( e ) ) + ( ( 2 ) * q / ( e ) ) + ( r / ( e ) ) + ( s / ( e ) ) ) ) ) * ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) / ( 4 ) / f / 100", - "BaseFormula": " tma_mispredictions * tma_info_thread_slots / ( 4 ) / br_misp_retired.all_branches / 100", + "BaseFormula": " tma_bottleneck_mispredictions * tma_info_thread_slots / ( 4 ) / br_misp_retired.all_branches / 100", "Category": "TMA", "CountDomain": "Core_Metric", "Threshold": { @@ -12047,11 +12047,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Memory_Page_Walks_Utilization" + "Value": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization" } ], "Formula": "a > 0.5", - "BaseFormula": "metric_TMA_Info_Memory_Page_Walks_Utilization > 0.5", + "BaseFormula": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization > 0.5", "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", diff --git a/CLX/metrics/perf/cascadelakex_metrics_perf.json b/CLX/metrics/perf/cascadelakex_metrics_perf.json index 06d29878..d748efd2 100644 --- a/CLX/metrics/perf/cascadelakex_metrics_perf.json +++ b/CLX/metrics/perf/cascadelakex_metrics_perf.json @@ -315,7 +315,7 @@ }, { "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the back-end)", - "MetricExpr": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( ( tma_microcode_sequencer / ( tma_few_uops_instructions + tma_microcode_sequencer ) ) * ( tma_assists / tma_microcode_sequencer ) ) * tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) ) ) - tma_big_code", + "MetricExpr": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( ( tma_microcode_sequencer / ( tma_few_uops_instructions + tma_microcode_sequencer ) ) * ( tma_assists / tma_microcode_sequencer ) ) * tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) ) ) - tma_bottleneck_big_code", "MetricGroup": "BvFB;Fed;FetchBW;Frontend;TopdownL1;tma_L1_group;Scaled_Slots", "MetricName": "tma_bottleneck_instruction_fetch_bw", "MetricThreshold": "tma_bottleneck_instruction_fetch_bw > 20" @@ -370,7 +370,7 @@ }, { "BriefDescription": "Total pipeline cost of remaining bottlenecks in the back-end", - "MetricExpr": "100 - ( tma_big_code + tma_instruction_fetch_bw + tma_mispredictions + tma_cache_memory_bandwidth + tma_cache_memory_latency + tma_memory_data_tlbs + tma_memory_synchronization + tma_compute_bound_est + tma_irregular_overhead + tma_branching_overhead + tma_useful_work )", + "MetricExpr": "100 - ( tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottleneck_mispredictions + tma_bottleneck_cache_memory_bandwidth + tma_bottleneck_cache_memory_latency + tma_bottleneck_memory_data_tlbs + tma_bottleneck_memory_synchronization + tma_bottleneck_compute_bound_est + tma_bottleneck_irregular_overhead + tma_bottleneck_branching_overhead + tma_bottleneck_useful_work )", "MetricGroup": "BvOB;Cor;Offcore;TopdownL1;tma_L1_group;Scaled_Slots", "MetricName": "tma_bottleneck_other_bottlenecks", "MetricThreshold": "tma_bottleneck_other_bottlenecks > 20", @@ -1302,7 +1302,7 @@ "MetricExpr": "100 * ( 1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1 ) if tma_info_system_smt_2t_utilization > 0.5 else 0", "MetricGroup": "Cor;SMT;Metric", "MetricName": "tma_info_botlnk_l0_core_bound_likely", - "MetricThreshold": "tma_info_botlnk_core_bound_likely > 0.5" + "MetricThreshold": "tma_info_botlnk_l0_core_bound_likely > 0.5" }, { "BriefDescription": "Instructions Per Cycle (per Logical Processor)", @@ -1547,7 +1547,7 @@ "MetricExpr": "IDQ.DSB_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS )", "MetricGroup": "DSB;Fed;FetchBW;Metric;tma_issueFB", "MetricName": "tma_info_frontend_dsb_coverage", - "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & ipc / 4 > 0.35", + "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 4 > 0.35", "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1598,7 +1598,7 @@ "MetricExpr": "100 * ( tma_fetch_latency * tma_dsb_switches / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_mite / ( tma_mite + tma_dsb ) )", "MetricGroup": "DSBmiss;Fed;Scaled_Slots;tma_issueFB", "MetricName": "tma_info_botlnk_l2_dsb_misses", - "MetricThreshold": "tma_info_botlnk_dsb_misses > 10", + "MetricThreshold": "tma_info_botlnk_l2_dsb_misses > 10", "PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1606,7 +1606,7 @@ "MetricExpr": "100 * ( tma_frontend_bound * ( tma_fetch_bandwidth / ( tma_fetch_latency + tma_fetch_bandwidth ) ) * ( tma_dsb / ( tma_mite + tma_dsb ) ) )", "MetricGroup": "DSB;Fed;FetchBW;Scaled_Slots;tma_issueFB", "MetricName": "tma_info_botlnk_l2_dsb_bandwidth", - "MetricThreshold": "tma_info_botlnk_dsb_bandwidth > 10", + "MetricThreshold": "tma_info_botlnk_l2_dsb_bandwidth > 10", "PublicDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1614,7 +1614,7 @@ "MetricExpr": "100 * ( tma_fetch_latency * tma_icache_misses / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) )", "MetricGroup": "Fed;FetchLat;IcMiss;Scaled_Slots;tma_issueFL", "MetricName": "tma_info_botlnk_l2_ic_misses", - "MetricThreshold": "tma_info_botlnk_ic_misses > 5", + "MetricThreshold": "tma_info_botlnk_l2_ic_misses > 5", "PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck." }, { @@ -1633,7 +1633,7 @@ }, { "BriefDescription": "Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricExpr": "tma_mispredictions * tma_info_thread_slots / ( 4 ) / BR_MISP_RETIRED.ALL_BRANCHES / 100", + "MetricExpr": "tma_bottleneck_mispredictions * tma_info_thread_slots / ( 4 ) / BR_MISP_RETIRED.ALL_BRANCHES / 100", "MetricGroup": "Bad;BrMispredicts;Core_Metric;tma_issueBM", "MetricName": "tma_info_bad_spec_branch_misprediction_cost", "PublicDescription": "Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_bottleneck_mispredictions, tma_branch_mispredicts, tma_mispredicts_resteers." @@ -1770,7 +1770,7 @@ "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING ) / ( 2 * tma_info_core_core_clks )", "MetricGroup": "Mem;MemoryTLB;Core_Metric", "MetricName": "tma_info_memory_tlb_page_walks_utilization", - "MetricThreshold": "tma_info_memory_page_walks_utilization > 0.5" + "MetricThreshold": "tma_info_memory_tlb_page_walks_utilization > 0.5" }, { "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", diff --git a/EMR/metrics/emeraldrapids_metrics.json b/EMR/metrics/emeraldrapids_metrics.json index e66196ab..92507de6 100644 --- a/EMR/metrics/emeraldrapids_metrics.json +++ b/EMR/metrics/emeraldrapids_metrics.json @@ -2,7 +2,7 @@ "Header": { "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.", "Info": "Performance Monitoring Metrics for 5th Generation Intel(R) Xeon(R) Processor Scalable Family0", - "DatePublished": "11/15/2024", + "DatePublished": "12/02/2024", "Version": "1.0", "Legend": "", "TmaVersion": "5.01", @@ -1361,7 +1361,7 @@ } ], "Formula": "100 * ( ( a / ( a + b + c + d ) - e / ( f ) ) - ( 1 - ( 10 * ( g / ( f ) ) * ( max( ( h / ( a + b + c + d ) ) * ( 1 - i / ( j - k ) ) , 0.0001 ) ) / ( h / ( a + b + c + d ) ) ) ) * ( ( l / ( a + b + c + d ) - e / ( f ) ) ) * ( ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * m / ( n ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) - ( ( 1 - w / x ) * ( ( ( l / ( a + b + c + d ) - e / ( f ) ) ) * ( ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) * ( ( ( 1 - ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) ) * m / ( n ) ) + ( ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * m / ( n ) ) * ( max( ( h / ( a + b + c + d ) ) * ( 1 - i / ( j - k ) ) , 0.0001 ) ) / ( h / ( a + b + c + d ) ) ) / ( ( ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * m / ( n ) ) + ( ( 1 - ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) ) * m / ( n ) ) + ( q / ( n ) ) ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) + ( max( 0 , ( a / ( a + b + c + d ) - e / ( f ) ) - ( ( l / ( a + b + c + d ) - e / ( f ) ) ) ) ) * ( max( y , x / ( s / t ) ) / ( z if smt_on else ( n ) ) / 2 ) / ( ( ( a_a - a_b ) / ( z if smt_on else ( n ) ) / 2 ) + ( ( a_c - a_d ) / ( z if smt_on else ( n ) ) / 2 ) + ( max( y , x / ( s / t ) ) / ( z if smt_on else ( n ) ) / 2 ) ) ) ) ) - ( 100 * ( ( l / ( a + b + c + d ) - e / ( f ) ) ) * ( ( p / ( n ) ) + ( o / ( n ) ) + ( q / ( n ) ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) )", - "BaseFormula": " 100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - inst_retired.rep_iteration / uops_retired.ms:c1 ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_ms ) ) ) ) - tma_big_code", + "BaseFormula": " 100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - inst_retired.rep_iteration / uops_retired.ms:c1 ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_ms ) ) ) ) - tma_bottleneck_big_code", "Category": "TMA", "CountDomain": "Scaled_Slots", "Threshold": { @@ -2956,7 +2956,7 @@ } ], "Formula": "100 - ( ( 100 * ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( h / ( i ) ) + ( j / ( i ) ) + ( k / ( i ) ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) ) + ( 100 * ( ( b / ( b + c + d + e ) - f / ( g ) ) - ( 1 - ( 10 * ( r / ( g ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) ) * ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) - ( ( 1 - w / x ) * ( ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) * ( ( ( 1 - ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * l / ( i ) ) + ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) / ( ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) + ( ( 1 - ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * l / ( i ) ) + ( k / ( i ) ) ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) + ( max( 0 , ( b / ( b + c + d + e ) - f / ( g ) ) - ( ( a / ( b + c + d + e ) - f / ( g ) ) ) ) ) * ( max( y , x / ( n / o ) ) / ( z if smt_on else ( i ) ) / 2 ) / ( ( ( a_a - a_b ) / ( z if smt_on else ( i ) ) / 2 ) + ( ( a_c - a_d ) / ( z if smt_on else ( i ) ) / 2 ) + ( max( y , x / ( n / o ) ) / ( z if smt_on else ( i ) ) / 2 ) ) ) ) ) - ( 100 * ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( h / ( i ) ) + ( j / ( i ) ) + ( k / ( i ) ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) ) ) + ( 100 * ( 1 - ( 10 * ( r / ( g ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) ) * ( ( s / ( b + c + d + e ) ) + ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) ) ) + ( 100 * ( ( ( a_e / ( b + c + d + e ) ) * ( ( ( a_f / ( i ) ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( min( i , a_k ) ) / ( i ) ) / ( ( ( min( i , a_k ) ) / ( i ) ) + ( ( min( i , a_l ) ) / ( i ) - ( ( min( i , a_k ) ) / ( i ) ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( ( a_i - a_f ) / ( i ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( a_m + a_n ) / ( i ) ) / ( ( ( ( ( 81 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_r * ( a_s / ( a_s + a_t ) ) ) + ( ( 79 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_u ) ) * ( 1 + ( a_v / a_w ) / 2 ) / ( i ) ) + ( ( ( 79 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_x + a_r * ( 1 - ( a_s / ( a_s + a_t ) ) ) ) * ( 1 + ( a_v / a_w ) / 2 ) / ( i ) ) + ( ( ( 37 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_y * ( 1 + ( a_v / a_w ) / 2 ) ) / ( i ) ) + ( ( a_m + a_n ) / ( i ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( a_z / ( i ) ) / ( ( min( ( 7 ) * b_a + b_b , max( b_c - b_d , 0 ) ) / ( i ) ) + ( 13 * b_e / ( i ) ) + ( min( 2 * ( b_f - a_v - a_w ) * dependentloadsweight / 100 , max( b_c - b_d , 0 ) ) / ( i ) ) + ( ( 16 * max( 0 , b_h - b_i ) + ( b_h / b_j ) * ( ( 10 ) * b_k + ( min( i , b_l ) ) ) ) / ( i ) ) + ( ( b_m / b_n ) * b_o / ( i ) ) + ( a_z / ( i ) ) ) ) ) ) ) + ( 100 * ( ( ( a_e / ( b + c + d + e ) ) * ( ( ( a_f / ( i ) ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( min( i , a_l ) ) / ( i ) - ( ( min( i , a_k ) ) / ( i ) ) ) / ( ( ( min( i , a_k ) ) / ( i ) ) + ( ( min( i , a_l ) ) / ( i ) - ( ( min( i , a_k ) ) / ( i ) ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( ( a_i - a_f ) / ( i ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( ( 37 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_y * ( 1 + ( a_v / a_w ) / 2 ) ) / ( i ) ) / ( ( ( ( ( 81 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_r * ( a_s / ( a_s + a_t ) ) ) + ( ( 79 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_u ) ) * ( 1 + ( a_v / a_w ) / 2 ) / ( i ) ) + ( ( ( 79 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_x + a_r * ( 1 - ( a_s / ( a_s + a_t ) ) ) ) * ( 1 + ( a_v / a_w ) / 2 ) / ( i ) ) + ( ( ( 37 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_y * ( 1 + ( a_v / a_w ) / 2 ) ) / ( i ) ) + ( ( a_m + a_n ) / ( i ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( a_h - a_i ) / ( i ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( min( 2 * ( b_f - a_v - a_w ) * dependentloadsweight / 100 , max( b_c - b_d , 0 ) ) / ( i ) ) / ( ( min( ( 7 ) * b_a + b_b , max( b_c - b_d , 0 ) ) / ( i ) ) + ( 13 * b_e / ( i ) ) + ( min( 2 * ( b_f - a_v - a_w ) * dependentloadsweight / 100 , max( b_c - b_d , 0 ) ) / ( i ) ) + ( ( 16 * max( 0 , b_h - b_i ) + ( b_h / b_j ) * ( ( 10 ) * b_k + ( min( i , b_l ) ) ) ) / ( i ) ) + ( ( b_m / b_n ) * b_o / ( i ) ) + ( a_z / ( i ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( 16 * max( 0 , b_h - b_i ) + ( b_h / b_j ) * ( ( 10 ) * b_k + ( min( i , b_l ) ) ) ) / ( i ) ) / ( ( min( ( 7 ) * b_a + b_b , max( b_c - b_d , 0 ) ) / ( i ) ) + ( 13 * b_e / ( i ) ) + ( min( 2 * ( b_f - a_v - a_w ) * dependentloadsweight / 100 , max( b_c - b_d , 0 ) ) / ( i ) ) + ( ( 16 * max( 0 , b_h - b_i ) + ( b_h / b_j ) * ( ( 10 ) * b_k + ( min( i , b_l ) ) ) ) / ( i ) ) + ( ( b_m / b_n ) * b_o / ( i ) ) + ( a_z / ( i ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( b_m / b_n ) * b_o / ( i ) ) / ( ( min( ( 7 ) * b_a + b_b , max( b_c - b_d , 0 ) ) / ( i ) ) + ( 13 * b_e / ( i ) ) + ( min( 2 * ( b_f - a_v - a_w ) * dependentloadsweight / 100 , max( b_c - b_d , 0 ) ) / ( i ) ) + ( ( 16 * max( 0 , b_h - b_i ) + ( b_h / b_j ) * ( ( 10 ) * b_k + ( min( i , b_l ) ) ) ) / ( i ) ) + ( ( b_m / b_n ) * b_o / ( i ) ) + ( a_z / ( i ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( a_j / ( i ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( b_p / ( z if smt_on else ( i ) ) ) / ( ( ( ( b_q * ( 10 ) * ( 1 - ( b_h / b_j ) ) ) + ( 1 - ( b_h / b_j ) ) * ( min( i , b_l ) ) ) / ( i ) ) + ( ( ( 170 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_r + ( 81 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_s ) / ( i ) ) + ( b_p / ( z if smt_on else ( i ) ) ) + ( 9 * b_t / ( i ) ) + ( ( ( 7 ) * b_u + b_v ) / ( z if smt_on else ( i ) ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( a_j / ( i ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( ( b_q * ( 10 ) * ( 1 - ( b_h / b_j ) ) ) + ( 1 - ( b_h / b_j ) ) * ( min( i , b_l ) ) ) / ( i ) ) / ( ( ( ( b_q * ( 10 ) * ( 1 - ( b_h / b_j ) ) ) + ( 1 - ( b_h / b_j ) ) * ( min( i , b_l ) ) ) / ( i ) ) + ( ( ( 170 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_r + ( 81 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_s ) / ( i ) ) + ( b_p / ( z if smt_on else ( i ) ) ) + ( 9 * b_t / ( i ) ) + ( ( ( 7 ) * b_u + b_v ) / ( z if smt_on else ( i ) ) ) ) ) ) ) ) + ( 100 * ( ( a_e / ( b + c + d + e ) ) * ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) / max( ( a_e / ( b + c + d + e ) ) , ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) ) * ( ( min( ( 7 ) * b_a + b_b , max( b_c - b_d , 0 ) ) / ( i ) ) / max( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) , ( ( min( ( 7 ) * b_a + b_b , max( b_c - b_d , 0 ) ) / ( i ) ) + ( 13 * b_e / ( i ) ) + ( min( 2 * ( b_f - a_v - a_w ) * dependentloadsweight / 100 , max( b_c - b_d , 0 ) ) / ( i ) ) + ( ( 16 * max( 0 , b_h - b_i ) + ( b_h / b_j ) * ( ( 10 ) * b_k + ( min( i , b_l ) ) ) ) / ( i ) ) + ( ( b_m / b_n ) * b_o / ( i ) ) + ( a_z / ( i ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( a_j / ( i ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( ( 7 ) * b_u + b_v ) / ( z if smt_on else ( i ) ) ) / ( ( ( ( b_q * ( 10 ) * ( 1 - ( b_h / b_j ) ) ) + ( 1 - ( b_h / b_j ) ) * ( min( i , b_l ) ) ) / ( i ) ) + ( ( ( 170 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_r + ( 81 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_s ) / ( i ) ) + ( b_p / ( z if smt_on else ( i ) ) ) + ( 9 * b_t / ( i ) ) + ( ( ( 7 ) * b_u + b_v ) / ( z if smt_on else ( i ) ) ) ) ) ) ) ) + ( 100 * ( ( a_e / ( b + c + d + e ) ) * ( ( ( ( a_f / ( i ) ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( min( i , a_l ) ) / ( i ) - ( ( min( i , a_k ) ) / ( i ) ) ) / ( ( ( min( i , a_k ) ) / ( i ) ) + ( ( min( i , a_l ) ) / ( i ) - ( ( min( i , a_k ) ) / ( i ) ) ) ) ) * ( ( ( ( 170 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_w + ( ( 170 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_x ) * ( 1 + ( a_v / a_w ) / 2 ) / ( i ) ) / ( ( ( ( 109 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_y * ( 1 + ( a_v / a_w ) / 2 ) / ( i ) ) + ( ( ( 190 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_z * ( 1 + ( a_v / a_w ) / 2 ) / ( i ) ) + ( ( ( ( 170 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_w + ( ( 170 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_x ) * ( 1 + ( a_v / a_w ) / 2 ) / ( i ) ) ) + ( ( ( a_i - a_f ) / ( i ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( ( ( 81 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_r * ( a_s / ( a_s + a_t ) ) ) + ( ( 79 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_u ) ) * ( 1 + ( a_v / a_w ) / 2 ) / ( i ) ) + ( ( ( 79 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_x + a_r * ( 1 - ( a_s / ( a_s + a_t ) ) ) ) * ( 1 + ( a_v / a_w ) / 2 ) / ( i ) ) ) / ( ( ( ( ( 81 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_r * ( a_s / ( a_s + a_t ) ) ) + ( ( 79 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_u ) ) * ( 1 + ( a_v / a_w ) / 2 ) / ( i ) ) + ( ( ( 79 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_x + a_r * ( 1 - ( a_s / ( a_s + a_t ) ) ) ) * ( 1 + ( a_v / a_w ) / 2 ) / ( i ) ) + ( ( ( 37 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_y * ( 1 + ( a_v / a_w ) / 2 ) ) / ( i ) ) + ( ( a_m + a_n ) / ( i ) ) ) + ( ( a_j / ( i ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( 170 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_r + ( 81 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_s ) / ( i ) ) / ( ( ( ( ( b_q * ( 10 ) * ( 1 - ( b_h / b_j ) ) ) + ( 1 - ( b_h / b_j ) ) * ( min( i , b_l ) ) ) / ( i ) ) + ( ( ( 170 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_r + ( 81 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_s ) / ( i ) ) + ( b_p / ( z if smt_on else ( i ) ) ) + ( 9 * b_t / ( i ) ) + ( ( ( 7 ) * b_u + b_v ) / ( z if smt_on else ( i ) ) ) ) - ( ( ( b_q * ( 10 ) * ( 1 - ( b_h / b_j ) ) ) + ( 1 - ( b_h / b_j ) ) * ( min( i , b_l ) ) ) / ( i ) ) ) ) + ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - c_a / v ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - c_a / v ) , 0.0001 ) ) ) ) ) ) + ( 100 * ( ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_e / ( b + c + d + e ) ) ) ) * ( c_b / ( i ) ) / ( ( c_b / ( i ) ) + ( c_c / ( i ) + ( c_d / ( i ) ) ) + ( c_e / ( z if smt_on else ( i ) ) ) + ( ( ( ( c_f + max( c_g - c_c , 0 ) ) / ( i ) * ( c_h - a_g ) / ( i ) ) * ( i ) + ( c_i + ( d / ( b + c + d + e ) ) * c_j ) ) / ( i ) if ( c_b < ( c_h - a_g ) ) else ( c_i + ( d / ( b + c + d + e ) ) * c_j ) / ( i ) ) ) ) + ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_e / ( b + c + d + e ) ) ) ) * ( c_e / ( z if smt_on else ( i ) ) ) / ( ( c_b / ( i ) ) + ( c_c / ( i ) + ( c_d / ( i ) ) ) + ( c_e / ( z if smt_on else ( i ) ) ) + ( ( ( ( c_f + max( c_g - c_c , 0 ) ) / ( i ) * ( c_h - a_g ) / ( i ) ) * ( i ) + ( c_i + ( d / ( b + c + d + e ) ) * c_j ) ) / ( i ) if ( c_b < ( c_h - a_g ) ) else ( c_i + ( d / ( b + c + d + e ) ) * c_j ) / ( i ) ) ) ) + ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_e / ( b + c + d + e ) ) ) ) * ( ( ( ( ( c_f + max( c_g - c_c , 0 ) ) / ( i ) * ( c_h - a_g ) / ( i ) ) * ( i ) + ( c_i + ( d / ( b + c + d + e ) ) * c_j ) ) / ( i ) if ( c_b < ( c_h - a_g ) ) else ( c_i + ( d / ( b + c + d + e ) ) * c_j ) / ( i ) ) / ( ( c_b / ( i ) ) + ( c_c / ( i ) + ( c_d / ( i ) ) ) + ( c_e / ( z if smt_on else ( i ) ) ) + ( ( ( ( c_f + max( c_g - c_c , 0 ) ) / ( i ) * ( c_h - a_g ) / ( i ) ) * ( i ) + ( c_i + ( d / ( b + c + d + e ) ) * c_j ) ) / ( i ) if ( c_b < ( c_h - a_g ) ) else ( c_i + ( d / ( b + c + d + e ) ) * c_j ) / ( i ) ) ) ) * ( ( c_k / ( i ) ) / ( ( ( c_f + max( c_g - c_c , 0 ) ) / ( i ) * ( c_h - a_g ) / ( i ) ) + ( c_i / ( i ) ) + ( c_l / ( i ) ) + ( c_k / ( i ) ) ) ) ) ) ) + ( 100 * ( ( ( 1 - w / x ) * ( ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) * ( ( ( 1 - ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * l / ( i ) ) + ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) / ( ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) + ( ( 1 - ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * l / ( i ) ) + ( k / ( i ) ) ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) + ( max( 0 , ( b / ( b + c + d + e ) - f / ( g ) ) - ( ( a / ( b + c + d + e ) - f / ( g ) ) ) ) ) * ( max( y , x / ( n / o ) ) / ( z if smt_on else ( i ) ) / 2 ) / ( ( ( a_a - a_b ) / ( z if smt_on else ( i ) ) / 2 ) + ( ( a_c - a_d ) / ( z if smt_on else ( i ) ) / 2 ) + ( max( y , x / ( n / o ) ) / ( z if smt_on else ( i ) ) / 2 ) ) ) ) + ( 10 * ( r / ( g ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) * ( s / ( b + c + d + e ) ) + ( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - c_a / v ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - c_a / v ) , 0.0001 ) ) ) ) + ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_e / ( b + c + d + e ) ) ) ) * ( ( c_c / ( i ) + ( c_d / ( i ) ) ) + c_g / ( i ) * ( ( c_f + max( c_g - c_c , 0 ) ) / ( i ) * ( c_h - a_g ) / ( i ) ) ) / ( ( c_b / ( i ) ) + ( c_c / ( i ) + ( c_d / ( i ) ) ) + ( c_e / ( z if smt_on else ( i ) ) ) + ( ( ( ( c_f + max( c_g - c_c , 0 ) ) / ( i ) * ( c_h - a_g ) / ( i ) ) * ( i ) + ( c_i + ( d / ( b + c + d + e ) ) * c_j ) ) / ( i ) if ( c_b < ( c_h - a_g ) ) else ( c_i + ( d / ( b + c + d + e ) ) * c_j ) / ( i ) ) ) ) + ( ( ( ( r / ( g ) ) / ( ( max( 0 , ( c_m / ( b + c + d + e ) ) - ( r / ( g ) ) ) ) + ( r / ( g ) ) ) ) * ( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * c_n / ( g ) ) / ( r / ( g ) ) ) ) * ( c_m / ( b + c + d + e ) ) ) ) ) + ( 100 * ( ( c_o + 2 * c_p + c_q ) / ( g ) ) ) + ( 100 * ( ( d / ( b + c + d + e ) ) - ( ( c_o + 2 * c_p + c_q ) / ( g ) ) - ( ( ( ( r / ( g ) ) / ( ( max( 0 , ( c_m / ( b + c + d + e ) ) - ( r / ( g ) ) ) ) + ( r / ( g ) ) ) ) * ( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * c_n / ( g ) ) / ( r / ( g ) ) ) ) * ( c_m / ( b + c + d + e ) ) ) ) ) )", - "BaseFormula": " 100 - ( tma_big_code + tma_instruction_fetch_bw + tma_mispredictions + tma_cache_memory_bandwidth + tma_cache_memory_latency + tma_memory_data_tlbs + tma_memory_synchronization + tma_compute_bound_est + tma_irregular_overhead + tma_branching_overhead + tma_useful_work )", + "BaseFormula": " 100 - ( tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottleneck_mispredictions + tma_bottleneck_cache_memory_bandwidth + tma_bottleneck_cache_memory_latency + tma_bottleneck_memory_data_tlbs + tma_bottleneck_memory_synchronization + tma_bottleneck_compute_bound_est + tma_bottleneck_irregular_overhead + tma_bottleneck_branching_overhead + tma_bottleneck_useful_work )", "Category": "TMA", "CountDomain": "Scaled_Slots", "Threshold": { @@ -9857,11 +9857,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_Core_Bound_Likely" + "Value": "metric_TMA_Info_Botlnk_L0_Core_Bound_Likely" } ], "Formula": "a > 0.5", - "BaseFormula": "metric_TMA_Info_Botlnk_Core_Bound_Likely > 0.5", + "BaseFormula": "metric_TMA_Info_Botlnk_L0_Core_Bound_Likely > 0.5", "ThresholdIssues": "" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -11367,11 +11367,11 @@ }, { "Alias": "b", - "Value": "IPC" + "Value": "metric_TMA_Info_Thread_IPC" } ], "Formula": "a < 0.7 & b / 6 > 0.35", - "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & IPC / 6 > 0.35", + "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & metric_TMA_Info_Thread_IPC / 6 > 0.35", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -11746,11 +11746,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_DSB_Misses" + "Value": "metric_TMA_Info_Botlnk_L2_DSB_Misses" } ], "Formula": "a > 10", - "BaseFormula": "metric_TMA_Info_Botlnk_DSB_Misses > 10", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_DSB_Misses > 10", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -11851,11 +11851,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_DSB_Bandwidth" + "Value": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth" } ], "Formula": "a > 10", - "BaseFormula": "metric_TMA_Info_Botlnk_DSB_Bandwidth > 10", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth > 10", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -11947,11 +11947,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_IC_Misses" + "Value": "metric_TMA_Info_Botlnk_L2_IC_Misses" } ], "Formula": "a > 5", - "BaseFormula": "metric_TMA_Info_Botlnk_IC_Misses > 5", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_IC_Misses > 5", "ThresholdIssues": "$issueFL" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -12236,7 +12236,7 @@ ], "Constants": [], "Formula": "( 100 * ( 1 - ( 10 * ( a / ( b ) ) * ( max( ( c / ( d + e + f + g ) ) * ( 1 - h / ( i - j ) ) , 0.0001 ) ) / ( c / ( d + e + f + g ) ) ) ) * ( ( c / ( d + e + f + g ) ) + ( ( k / ( d + e + f + g ) - l / ( b ) ) ) * ( ( ( c / ( d + e + f + g ) ) / ( max( 1 - ( ( d / ( d + e + f + g ) - l / ( b ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) ) * m / ( n ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) ) ) * ( b ) / ( 6 ) / h / 100", - "BaseFormula": " tma_mispredictions * tma_info_thread_slots / ( 6 ) / br_misp_retired.all_branches / 100", + "BaseFormula": " tma_bottleneck_mispredictions * tma_info_thread_slots / ( 6 ) / br_misp_retired.all_branches / 100", "Category": "TMA", "CountDomain": "Core_Metric", "Threshold": { @@ -12994,11 +12994,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Memory_Page_Walks_Utilization" + "Value": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization" } ], "Formula": "a > 0.5", - "BaseFormula": "metric_TMA_Info_Memory_Page_Walks_Utilization > 0.5", + "BaseFormula": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization > 0.5", "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", @@ -13308,11 +13308,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Memory_Useless_HWPF" + "Value": "metric_TMA_Info_Memory_Prefetches_Useless_HWPF" } ], "Formula": "a > 0.15", - "BaseFormula": "metric_TMA_Info_Memory_Useless_HWPF > 0.15", + "BaseFormula": "metric_TMA_Info_Memory_Prefetches_Useless_HWPF > 0.15", "ThresholdIssues": "" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", diff --git a/EMR/metrics/perf/emeraldrapids_metrics_perf.json b/EMR/metrics/perf/emeraldrapids_metrics_perf.json index 0c15d57c..04dc0e54 100644 --- a/EMR/metrics/perf/emeraldrapids_metrics_perf.json +++ b/EMR/metrics/perf/emeraldrapids_metrics_perf.json @@ -326,7 +326,7 @@ }, { "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the back-end)", - "MetricExpr": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\\,cmask\\=0x1@ ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_ms ) ) ) ) - tma_big_code", + "MetricExpr": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\\,cmask\\=0x1@ ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_ms ) ) ) ) - tma_bottleneck_big_code", "MetricGroup": "BvFB;Fed;FetchBW;Frontend;TopdownL1;tma_L1_group;Default;Scaled_Slots", "MetricName": "tma_bottleneck_instruction_fetch_bw", "MetricThreshold": "tma_bottleneck_instruction_fetch_bw > 20", @@ -395,7 +395,7 @@ }, { "BriefDescription": "Total pipeline cost of remaining bottlenecks in the back-end", - "MetricExpr": "100 - ( tma_big_code + tma_instruction_fetch_bw + tma_mispredictions + tma_cache_memory_bandwidth + tma_cache_memory_latency + tma_memory_data_tlbs + tma_memory_synchronization + tma_compute_bound_est + tma_irregular_overhead + tma_branching_overhead + tma_useful_work )", + "MetricExpr": "100 - ( tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottleneck_mispredictions + tma_bottleneck_cache_memory_bandwidth + tma_bottleneck_cache_memory_latency + tma_bottleneck_memory_data_tlbs + tma_bottleneck_memory_synchronization + tma_bottleneck_compute_bound_est + tma_bottleneck_irregular_overhead + tma_bottleneck_branching_overhead + tma_bottleneck_useful_work )", "MetricGroup": "BvOB;Cor;Offcore;TopdownL1;tma_L1_group;Default;Scaled_Slots", "MetricName": "tma_bottleneck_other_bottlenecks", "MetricThreshold": "tma_bottleneck_other_bottlenecks > 20", @@ -1448,7 +1448,7 @@ "MetricExpr": "100 * ( 1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1 ) if tma_info_system_smt_2t_utilization > 0.5 else 0", "MetricGroup": "Cor;SMT;Metric", "MetricName": "tma_info_botlnk_l0_core_bound_likely", - "MetricThreshold": "tma_info_botlnk_core_bound_likely > 0.5" + "MetricThreshold": "tma_info_botlnk_l0_core_bound_likely > 0.5" }, { "BriefDescription": "Instructions Per Cycle (per Logical Processor)", @@ -1491,7 +1491,7 @@ }, { "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor", - "MetricExpr": "tma_info_thread_slots / ( TOPDOWN.SLOTS / 2 ) if #SMT_on else 1", + "MetricExpr": "tma_info_thread_slots / ( slots / 2 ) if #SMT_on else 1", "MetricGroup": "SMT;TmaL1;TopdownL1;tma_L1_group;Metric", "MetricName": "tma_info_thread_slots_utilization" }, @@ -1714,7 +1714,7 @@ "MetricExpr": "IDQ.DSB_UOPS / ( UOPS_ISSUED.ANY )", "MetricGroup": "DSB;Fed;FetchBW;Metric;tma_issueFB", "MetricName": "tma_info_frontend_dsb_coverage", - "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & ipc / 6 > 0.35", + "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 6 > 0.35", "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1772,7 +1772,7 @@ "MetricExpr": "100 * ( tma_fetch_latency * tma_dsb_switches / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_mite / ( tma_mite + tma_dsb + tma_ms ) )", "MetricGroup": "DSBmiss;Fed;Scaled_Slots;tma_issueFB", "MetricName": "tma_info_botlnk_l2_dsb_misses", - "MetricThreshold": "tma_info_botlnk_dsb_misses > 10", + "MetricThreshold": "tma_info_botlnk_l2_dsb_misses > 10", "PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1780,7 +1780,7 @@ "MetricExpr": "100 * ( tma_frontend_bound * ( tma_fetch_bandwidth / ( tma_fetch_latency + tma_fetch_bandwidth ) ) * ( tma_dsb / ( tma_mite + tma_dsb + tma_ms ) ) )", "MetricGroup": "DSB;Fed;FetchBW;Scaled_Slots;tma_issueFB", "MetricName": "tma_info_botlnk_l2_dsb_bandwidth", - "MetricThreshold": "tma_info_botlnk_dsb_bandwidth > 10", + "MetricThreshold": "tma_info_botlnk_l2_dsb_bandwidth > 10", "PublicDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1788,7 +1788,7 @@ "MetricExpr": "100 * ( tma_fetch_latency * tma_icache_misses / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) )", "MetricGroup": "Fed;FetchLat;IcMiss;Scaled_Slots;tma_issueFL", "MetricName": "tma_info_botlnk_l2_ic_misses", - "MetricThreshold": "tma_info_botlnk_ic_misses > 5", + "MetricThreshold": "tma_info_botlnk_l2_ic_misses > 5", "PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck." }, { @@ -1828,7 +1828,7 @@ }, { "BriefDescription": "Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricExpr": "tma_mispredictions * tma_info_thread_slots / ( 6 ) / BR_MISP_RETIRED.ALL_BRANCHES / 100", + "MetricExpr": "tma_bottleneck_mispredictions * tma_info_thread_slots / ( 6 ) / BR_MISP_RETIRED.ALL_BRANCHES / 100", "MetricGroup": "Bad;BrMispredicts;Core_Metric;tma_issueBM", "MetricName": "tma_info_bad_spec_branch_misprediction_cost", "PublicDescription": "Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_bottleneck_mispredictions, tma_branch_mispredicts, tma_mispredicts_resteers." @@ -1971,7 +1971,7 @@ "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 4 * tma_info_core_core_clks )", "MetricGroup": "Mem;MemoryTLB;Core_Metric", "MetricName": "tma_info_memory_tlb_page_walks_utilization", - "MetricThreshold": "tma_info_memory_page_walks_utilization > 0.5" + "MetricThreshold": "tma_info_memory_tlb_page_walks_utilization > 0.5" }, { "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", @@ -2032,7 +2032,7 @@ "MetricExpr": "L2_LINES_OUT.USELESS_HWPF / ( L2_LINES_OUT.SILENT + L2_LINES_OUT.NON_SILENT )", "MetricGroup": "Prefetches;Metric", "MetricName": "tma_info_memory_prefetches_useless_hwpf", - "MetricThreshold": "tma_info_memory_useless_hwpf > 0.15" + "MetricThreshold": "tma_info_memory_prefetches_useless_hwpf > 0.15" }, { "BriefDescription": "Average Latency for L2 cache miss demand Loads", @@ -2196,7 +2196,7 @@ }, { "BriefDescription": "Cross-socket Ultra Path Interconnect (UPI) data transmit bandwidth for data only [MB / sec]", - "MetricExpr": "UNC_UPI_TXL_FLITS.ALL_DATA * 64 / 9 / 1000000", + "MetricExpr": "UNC_UPI_TxL_FLITS.ALL_DATA * 64 / 9 / 1000000", "MetricGroup": "SoC;Server;MB/sec", "MetricName": "tma_info_system_upi_data_transmit_bw" }, diff --git a/GNR/metrics/graniterapids_metrics.json b/GNR/metrics/graniterapids_metrics.json index 93d5cefc..6573f1a8 100644 --- a/GNR/metrics/graniterapids_metrics.json +++ b/GNR/metrics/graniterapids_metrics.json @@ -2,7 +2,7 @@ "Header": { "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.", "Info": "Performance Monitoring Metrics for Intel(R) Xeon(R) 6 Processor with P-cores0", - "DatePublished": "11/15/2024", + "DatePublished": "12/02/2024", "Version": "1.0", "Legend": "", "TmaVersion": "5.01", @@ -1418,7 +1418,7 @@ } ], "Formula": "100 * ( ( a / ( a + b + c + d ) - e / ( f ) ) - ( 1 - ( 10 * ( g / ( f ) ) * ( max( ( h / ( a + b + c + d ) ) * ( 1 - i / ( j - k ) ) , 0.0001 ) ) / ( h / ( a + b + c + d ) ) ) ) * ( ( l / ( a + b + c + d ) - e / ( f ) ) ) * ( ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * m / ( n ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) - ( ( 1 - w / x ) * ( ( ( l / ( a + b + c + d ) - e / ( f ) ) ) * ( ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) * ( ( ( 1 - ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) ) * m / ( n ) ) + ( ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * m / ( n ) ) * ( max( ( h / ( a + b + c + d ) ) * ( 1 - i / ( j - k ) ) , 0.0001 ) ) / ( h / ( a + b + c + d ) ) ) / ( ( ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * m / ( n ) ) + ( ( 1 - ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) ) * m / ( n ) ) + ( q / ( n ) ) ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) + ( max( 0 , ( a / ( a + b + c + d ) - e / ( f ) ) - ( ( l / ( a + b + c + d ) - e / ( f ) ) ) ) ) * ( max( y , x / ( s / t ) ) / ( z if smt_on else ( n ) ) / 2 ) / ( ( ( a_a - a_b ) / ( z if smt_on else ( n ) ) / 2 ) + ( ( a_c - a_d ) / ( z if smt_on else ( n ) ) / 2 ) + ( max( y , x / ( s / t ) ) / ( z if smt_on else ( n ) ) / 2 ) ) ) ) ) - ( 100 * ( ( l / ( a + b + c + d ) - e / ( f ) ) ) * ( ( p / ( n ) ) + ( o / ( n ) ) + ( q / ( n ) ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) )", - "BaseFormula": " 100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - inst_retired.rep_iteration / uops_retired.ms:c1 ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_ms ) ) ) ) - tma_big_code", + "BaseFormula": " 100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - inst_retired.rep_iteration / uops_retired.ms:c1 ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_ms ) ) ) ) - tma_bottleneck_big_code", "Category": "TMA", "CountDomain": "Scaled_Slots", "Threshold": { @@ -3145,7 +3145,7 @@ } ], "Formula": "100 - ( ( 100 * ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( h / ( i ) ) + ( j / ( i ) ) + ( k / ( i ) ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) ) + ( 100 * ( ( b / ( b + c + d + e ) - f / ( g ) ) - ( 1 - ( 10 * ( r / ( g ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) ) * ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) - ( ( 1 - w / x ) * ( ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) * ( ( ( 1 - ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * l / ( i ) ) + ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) / ( ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) + ( ( 1 - ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * l / ( i ) ) + ( k / ( i ) ) ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) + ( max( 0 , ( b / ( b + c + d + e ) - f / ( g ) ) - ( ( a / ( b + c + d + e ) - f / ( g ) ) ) ) ) * ( max( y , x / ( n / o ) ) / ( z if smt_on else ( i ) ) / 2 ) / ( ( ( a_a - a_b ) / ( z if smt_on else ( i ) ) / 2 ) + ( ( a_c - a_d ) / ( z if smt_on else ( i ) ) / 2 ) + ( max( y , x / ( n / o ) ) / ( z if smt_on else ( i ) ) / 2 ) ) ) ) ) - ( 100 * ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( h / ( i ) ) + ( j / ( i ) ) + ( k / ( i ) ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) ) ) + ( 100 * ( 1 - ( 10 * ( r / ( g ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) ) * ( ( s / ( b + c + d + e ) ) + ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) ) ) + ( 100 * ( ( ( a_e / ( b + c + d + e ) ) * ( ( ( a_f / ( i ) ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( min( i , a_k ) ) / ( i ) ) / ( ( ( min( i , a_k ) ) / ( i ) ) + ( ( min( i , a_l ) ) / ( i ) - ( ( min( i , a_k ) ) / ( i ) ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( ( a_i - a_f ) / ( i ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( a_m + a_n ) / ( i ) ) / ( ( ( ( min( ( a_o * a_p ) , a_o * ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_p > = 0 ) else ( a_o * ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) + ( min( ( a_t * a_u ) , a_t * ( 81 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_u > = 0 ) else ( a_t * ( 81 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( a_v / ( a_v + a_w ) ) ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) + ( ( ( min( ( a_z * b_a ) , a_z * ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( b_a > = 0 ) else ( a_z * ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) + ( min( ( a_t * a_u ) , a_t * ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_u > = 0 ) else ( a_t * ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( 1 - ( a_v / ( a_v + a_w ) ) ) ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) + ( ( min( ( b_b * b_c ) , b_b * ( 37 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( b_c > = 0 ) else ( b_b * ( 37 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) + ( ( a_m + a_n ) / ( i ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( b_d / ( i ) ) / ( ( ( min( ( b_e * b_f ) , b_e * ( 7 ) ) if ( b_f > = 0 ) else ( b_e * ( 7 ) ) ) / ( i ) + ( b_g / ( i ) ) ) + ( 13 * b_h / ( i ) ) + ( min( 2 * ( b_i - a_x - a_y ) * dependentloadsweight / 100 , max( b_k - b_l , 0 ) ) / ( i ) ) + ( ( b_m * b_n ) / ( i ) ) + ( ( min( ( b_o * b_p ) , b_o * ( b_q / b_r ) ) if ( b_p > = 0 ) else ( b_o * ( b_q / b_r ) ) ) / ( i ) ) + ( b_d / ( i ) ) ) ) ) ) ) + ( 100 * ( ( ( a_e / ( b + c + d + e ) ) * ( ( ( a_f / ( i ) ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( min( i , a_l ) ) / ( i ) - ( ( min( i , a_k ) ) / ( i ) ) ) / ( ( ( min( i , a_k ) ) / ( i ) ) + ( ( min( i , a_l ) ) / ( i ) - ( ( min( i , a_k ) ) / ( i ) ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( ( a_i - a_f ) / ( i ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( min( ( b_b * b_c ) , b_b * ( 37 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( b_c > = 0 ) else ( b_b * ( 37 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) / ( ( ( ( min( ( a_o * a_p ) , a_o * ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_p > = 0 ) else ( a_o * ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) + ( min( ( a_t * a_u ) , a_t * ( 81 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_u > = 0 ) else ( a_t * ( 81 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( a_v / ( a_v + a_w ) ) ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) + ( ( ( min( ( a_z * b_a ) , a_z * ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( b_a > = 0 ) else ( a_z * ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) + ( min( ( a_t * a_u ) , a_t * ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_u > = 0 ) else ( a_t * ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( 1 - ( a_v / ( a_v + a_w ) ) ) ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) + ( ( min( ( b_b * b_c ) , b_b * ( 37 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( b_c > = 0 ) else ( b_b * ( 37 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) + ( ( a_m + a_n ) / ( i ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( a_h - a_i ) / ( i ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( min( 2 * ( b_i - a_x - a_y ) * dependentloadsweight / 100 , max( b_k - b_l , 0 ) ) / ( i ) ) / ( ( ( min( ( b_e * b_f ) , b_e * ( 7 ) ) if ( b_f > = 0 ) else ( b_e * ( 7 ) ) ) / ( i ) + ( b_g / ( i ) ) ) + ( 13 * b_h / ( i ) ) + ( min( 2 * ( b_i - a_x - a_y ) * dependentloadsweight / 100 , max( b_k - b_l , 0 ) ) / ( i ) ) + ( ( b_m * b_n ) / ( i ) ) + ( ( min( ( b_o * b_p ) , b_o * ( b_q / b_r ) ) if ( b_p > = 0 ) else ( b_o * ( b_q / b_r ) ) ) / ( i ) ) + ( b_d / ( i ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( b_m * b_n ) / ( i ) ) / ( ( ( min( ( b_e * b_f ) , b_e * ( 7 ) ) if ( b_f > = 0 ) else ( b_e * ( 7 ) ) ) / ( i ) + ( b_g / ( i ) ) ) + ( 13 * b_h / ( i ) ) + ( min( 2 * ( b_i - a_x - a_y ) * dependentloadsweight / 100 , max( b_k - b_l , 0 ) ) / ( i ) ) + ( ( b_m * b_n ) / ( i ) ) + ( ( min( ( b_o * b_p ) , b_o * ( b_q / b_r ) ) if ( b_p > = 0 ) else ( b_o * ( b_q / b_r ) ) ) / ( i ) ) + ( b_d / ( i ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( min( ( b_o * b_p ) , b_o * ( b_q / b_r ) ) if ( b_p > = 0 ) else ( b_o * ( b_q / b_r ) ) ) / ( i ) ) / ( ( ( min( ( b_e * b_f ) , b_e * ( 7 ) ) if ( b_f > = 0 ) else ( b_e * ( 7 ) ) ) / ( i ) + ( b_g / ( i ) ) ) + ( 13 * b_h / ( i ) ) + ( min( 2 * ( b_i - a_x - a_y ) * dependentloadsweight / 100 , max( b_k - b_l , 0 ) ) / ( i ) ) + ( ( b_m * b_n ) / ( i ) ) + ( ( min( ( b_o * b_p ) , b_o * ( b_q / b_r ) ) if ( b_p > = 0 ) else ( b_o * ( b_q / b_r ) ) ) / ( i ) ) + ( b_d / ( i ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( a_j / ( i ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( min( ( b_s * b_t ) , b_s * 1 ) if ( b_t > = 0 ) else ( b_s * 1 ) ) / ( i ) ) / ( ( ( ( b_u * ( 10 ) * ( 1 - ( b_m / b_v ) ) ) + ( 1 - ( b_m / b_v ) ) * ( min( i , b_w ) ) ) / ( i ) ) + ( ( ( 170 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_x + ( 81 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_y ) / ( i ) ) + ( ( min( ( b_s * b_t ) , b_s * 1 ) if ( b_t > = 0 ) else ( b_s * 1 ) ) / ( i ) ) + ( 9 * b_z / ( i ) ) + ( ( min( ( c_a * c_b ) , c_a * ( 7 ) ) if ( c_b > = 0 ) else ( c_a * ( 7 ) ) ) / ( i ) + ( c_c / ( z if smt_on else ( i ) ) ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( a_j / ( i ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( ( b_u * ( 10 ) * ( 1 - ( b_m / b_v ) ) ) + ( 1 - ( b_m / b_v ) ) * ( min( i , b_w ) ) ) / ( i ) ) / ( ( ( ( b_u * ( 10 ) * ( 1 - ( b_m / b_v ) ) ) + ( 1 - ( b_m / b_v ) ) * ( min( i , b_w ) ) ) / ( i ) ) + ( ( ( 170 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_x + ( 81 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_y ) / ( i ) ) + ( ( min( ( b_s * b_t ) , b_s * 1 ) if ( b_t > = 0 ) else ( b_s * 1 ) ) / ( i ) ) + ( 9 * b_z / ( i ) ) + ( ( min( ( c_a * c_b ) , c_a * ( 7 ) ) if ( c_b > = 0 ) else ( c_a * ( 7 ) ) ) / ( i ) + ( c_c / ( z if smt_on else ( i ) ) ) ) ) ) ) ) ) + ( 100 * ( ( ( a_e / ( b + c + d + e ) ) * ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( min( ( b_e * b_f ) , b_e * ( 7 ) ) if ( b_f > = 0 ) else ( b_e * ( 7 ) ) ) / ( i ) + ( b_g / ( i ) ) ) / ( ( ( min( ( b_e * b_f ) , b_e * ( 7 ) ) if ( b_f > = 0 ) else ( b_e * ( 7 ) ) ) / ( i ) + ( b_g / ( i ) ) ) + ( 13 * b_h / ( i ) ) + ( min( 2 * ( b_i - a_x - a_y ) * dependentloadsweight / 100 , max( b_k - b_l , 0 ) ) / ( i ) ) + ( ( b_m * b_n ) / ( i ) ) + ( ( min( ( b_o * b_p ) , b_o * ( b_q / b_r ) ) if ( b_p > = 0 ) else ( b_o * ( b_q / b_r ) ) ) / ( i ) ) + ( b_d / ( i ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( a_j / ( i ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( min( ( c_a * c_b ) , c_a * ( 7 ) ) if ( c_b > = 0 ) else ( c_a * ( 7 ) ) ) / ( i ) + ( c_c / ( z if smt_on else ( i ) ) ) ) / ( ( ( ( b_u * ( 10 ) * ( 1 - ( b_m / b_v ) ) ) + ( 1 - ( b_m / b_v ) ) * ( min( i , b_w ) ) ) / ( i ) ) + ( ( ( 170 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_x + ( 81 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_y ) / ( i ) ) + ( ( min( ( b_s * b_t ) , b_s * 1 ) if ( b_t > = 0 ) else ( b_s * 1 ) ) / ( i ) ) + ( 9 * b_z / ( i ) ) + ( ( min( ( c_a * c_b ) , c_a * ( 7 ) ) if ( c_b > = 0 ) else ( c_a * ( 7 ) ) ) / ( i ) + ( c_c / ( z if smt_on else ( i ) ) ) ) ) ) ) ) ) + ( 100 * ( ( a_e / ( b + c + d + e ) ) * ( ( ( ( a_f / ( i ) ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( min( i , a_l ) ) / ( i ) - ( ( min( i , a_k ) ) / ( i ) ) ) / ( ( ( min( i , a_k ) ) / ( i ) ) + ( ( min( i , a_l ) ) / ( i ) - ( ( min( i , a_k ) ) / ( i ) ) ) ) ) * ( ( ( c_d * c_e ) + ( c_f * c_g ) ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) / ( ( ( c_h * c_i ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) + ( ( c_j * c_k ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) + ( ( ( c_d * c_e ) + ( c_f * c_g ) ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) ) + ( ( ( a_i - a_f ) / ( i ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( ( min( ( a_o * a_p ) , a_o * ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_p > = 0 ) else ( a_o * ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) + ( min( ( a_t * a_u ) , a_t * ( 81 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_u > = 0 ) else ( a_t * ( 81 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( a_v / ( a_v + a_w ) ) ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) + ( ( ( min( ( a_z * b_a ) , a_z * ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( b_a > = 0 ) else ( a_z * ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) + ( min( ( a_t * a_u ) , a_t * ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_u > = 0 ) else ( a_t * ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( 1 - ( a_v / ( a_v + a_w ) ) ) ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) ) / ( ( ( ( min( ( a_o * a_p ) , a_o * ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_p > = 0 ) else ( a_o * ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) + ( min( ( a_t * a_u ) , a_t * ( 81 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_u > = 0 ) else ( a_t * ( 81 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( a_v / ( a_v + a_w ) ) ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) + ( ( ( min( ( a_z * b_a ) , a_z * ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( b_a > = 0 ) else ( a_z * ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) + ( min( ( a_t * a_u ) , a_t * ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_u > = 0 ) else ( a_t * ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( 1 - ( a_v / ( a_v + a_w ) ) ) ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) + ( ( min( ( b_b * b_c ) , b_b * ( 37 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( b_c > = 0 ) else ( b_b * ( 37 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) + ( ( a_m + a_n ) / ( i ) ) ) + ( ( a_j / ( i ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( 170 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_x + ( 81 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_y ) / ( i ) ) / ( ( ( ( ( b_u * ( 10 ) * ( 1 - ( b_m / b_v ) ) ) + ( 1 - ( b_m / b_v ) ) * ( min( i , b_w ) ) ) / ( i ) ) + ( ( ( 170 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_x + ( 81 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_y ) / ( i ) ) + ( ( min( ( b_s * b_t ) , b_s * 1 ) if ( b_t > = 0 ) else ( b_s * 1 ) ) / ( i ) ) + ( 9 * b_z / ( i ) ) + ( ( min( ( c_a * c_b ) , c_a * ( 7 ) ) if ( c_b > = 0 ) else ( c_a * ( 7 ) ) ) / ( i ) + ( c_c / ( z if smt_on else ( i ) ) ) ) ) - ( ( ( b_u * ( 10 ) * ( 1 - ( b_m / b_v ) ) ) + ( 1 - ( b_m / b_v ) ) * ( min( i , b_w ) ) ) / ( i ) ) ) ) + ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - c_l / v ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - c_l / v ) , 0.0001 ) ) ) ) ) ) + ( 100 * ( ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_e / ( b + c + d + e ) ) ) ) * ( c_m / ( i ) ) / ( ( c_m / ( i ) ) + ( c_n / ( i ) + ( c_o / ( i ) ) ) + ( c_p / ( z if smt_on else ( i ) ) ) + ( ( ( max( c_q - c_n , 0 ) / ( i ) ) * ( i ) + ( c_r + ( d / ( b + c + d + e ) ) * c_s ) ) / ( i ) if ( c_m < ( c_t - a_g ) ) else ( c_r + ( d / ( b + c + d + e ) ) * c_s ) / ( i ) ) ) ) + ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_e / ( b + c + d + e ) ) ) ) * ( c_p / ( z if smt_on else ( i ) ) ) / ( ( c_m / ( i ) ) + ( c_n / ( i ) + ( c_o / ( i ) ) ) + ( c_p / ( z if smt_on else ( i ) ) ) + ( ( ( max( c_q - c_n , 0 ) / ( i ) ) * ( i ) + ( c_r + ( d / ( b + c + d + e ) ) * c_s ) ) / ( i ) if ( c_m < ( c_t - a_g ) ) else ( c_r + ( d / ( b + c + d + e ) ) * c_s ) / ( i ) ) ) ) + ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_e / ( b + c + d + e ) ) ) ) * ( ( ( ( max( c_q - c_n , 0 ) / ( i ) ) * ( i ) + ( c_r + ( d / ( b + c + d + e ) ) * c_s ) ) / ( i ) if ( c_m < ( c_t - a_g ) ) else ( c_r + ( d / ( b + c + d + e ) ) * c_s ) / ( i ) ) / ( ( c_m / ( i ) ) + ( c_n / ( i ) + ( c_o / ( i ) ) ) + ( c_p / ( z if smt_on else ( i ) ) ) + ( ( ( max( c_q - c_n , 0 ) / ( i ) ) * ( i ) + ( c_r + ( d / ( b + c + d + e ) ) * c_s ) ) / ( i ) if ( c_m < ( c_t - a_g ) ) else ( c_r + ( d / ( b + c + d + e ) ) * c_s ) / ( i ) ) ) ) * ( ( c_u / ( i ) ) / ( ( max( c_q - c_n , 0 ) / ( i ) ) + ( c_r / ( i ) ) + ( c_v / ( i ) ) + ( c_u / ( i ) ) ) ) ) ) ) + ( 100 * ( ( ( 1 - w / x ) * ( ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) * ( ( ( 1 - ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * l / ( i ) ) + ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) / ( ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) + ( ( 1 - ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * l / ( i ) ) + ( k / ( i ) ) ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) + ( max( 0 , ( b / ( b + c + d + e ) - f / ( g ) ) - ( ( a / ( b + c + d + e ) - f / ( g ) ) ) ) ) * ( max( y , x / ( n / o ) ) / ( z if smt_on else ( i ) ) / 2 ) / ( ( ( a_a - a_b ) / ( z if smt_on else ( i ) ) / 2 ) + ( ( a_c - a_d ) / ( z if smt_on else ( i ) ) / 2 ) + ( max( y , x / ( n / o ) ) / ( z if smt_on else ( i ) ) / 2 ) ) ) ) + ( 10 * ( r / ( g ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) * ( s / ( b + c + d + e ) ) + ( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - c_l / v ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - c_l / v ) , 0.0001 ) ) ) ) + ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_e / ( b + c + d + e ) ) ) ) * ( ( c_n / ( i ) + ( c_o / ( i ) ) ) + c_w / ( i ) * ( max( c_q - c_n , 0 ) / ( i ) ) ) / ( ( c_m / ( i ) ) + ( c_n / ( i ) + ( c_o / ( i ) ) ) + ( c_p / ( z if smt_on else ( i ) ) ) + ( ( ( max( c_q - c_n , 0 ) / ( i ) ) * ( i ) + ( c_r + ( d / ( b + c + d + e ) ) * c_s ) ) / ( i ) if ( c_m < ( c_t - a_g ) ) else ( c_r + ( d / ( b + c + d + e ) ) * c_s ) / ( i ) ) ) ) + ( ( ( ( r / ( g ) ) / ( ( max( 0 , ( c_x / ( b + c + d + e ) ) - ( r / ( g ) ) ) ) + ( r / ( g ) ) ) ) * ( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * c_y / ( g ) ) / ( r / ( g ) ) ) ) * ( c_x / ( b + c + d + e ) ) ) ) ) + ( 100 * ( ( c_z + 2 * d_a + d_b ) / ( g ) ) ) + ( 100 * ( ( d / ( b + c + d + e ) ) - ( ( c_z + 2 * d_a + d_b ) / ( g ) ) - ( ( ( ( r / ( g ) ) / ( ( max( 0 , ( c_x / ( b + c + d + e ) ) - ( r / ( g ) ) ) ) + ( r / ( g ) ) ) ) * ( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * c_y / ( g ) ) / ( r / ( g ) ) ) ) * ( c_x / ( b + c + d + e ) ) ) ) ) )", - "BaseFormula": " 100 - ( tma_big_code + tma_instruction_fetch_bw + tma_mispredictions + tma_cache_memory_bandwidth + tma_cache_memory_latency + tma_memory_data_tlbs + tma_memory_synchronization + tma_compute_bound_est + tma_irregular_overhead + tma_branching_overhead + tma_useful_work )", + "BaseFormula": " 100 - ( tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottleneck_mispredictions + tma_bottleneck_cache_memory_bandwidth + tma_bottleneck_cache_memory_latency + tma_bottleneck_memory_data_tlbs + tma_bottleneck_memory_synchronization + tma_bottleneck_compute_bound_est + tma_bottleneck_irregular_overhead + tma_bottleneck_branching_overhead + tma_bottleneck_useful_work )", "Category": "TMA", "CountDomain": "Scaled_Slots", "Threshold": { @@ -10287,11 +10287,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_Core_Bound_Likely" + "Value": "metric_TMA_Info_Botlnk_L0_Core_Bound_Likely" } ], "Formula": "a > 0.5", - "BaseFormula": "metric_TMA_Info_Botlnk_Core_Bound_Likely > 0.5", + "BaseFormula": "metric_TMA_Info_Botlnk_L0_Core_Bound_Likely > 0.5", "ThresholdIssues": "" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -11757,11 +11757,11 @@ }, { "Alias": "b", - "Value": "IPC" + "Value": "metric_TMA_Info_Thread_IPC" } ], "Formula": "a < 0.7 & b / 6 > 0.35", - "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & IPC / 6 > 0.35", + "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & metric_TMA_Info_Thread_IPC / 6 > 0.35", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -12250,11 +12250,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_DSB_Misses" + "Value": "metric_TMA_Info_Botlnk_L2_DSB_Misses" } ], "Formula": "a > 10", - "BaseFormula": "metric_TMA_Info_Botlnk_DSB_Misses > 10", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_DSB_Misses > 10", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -12355,11 +12355,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_DSB_Bandwidth" + "Value": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth" } ], "Formula": "a > 10", - "BaseFormula": "metric_TMA_Info_Botlnk_DSB_Bandwidth > 10", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth > 10", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -12451,11 +12451,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_IC_Misses" + "Value": "metric_TMA_Info_Botlnk_L2_IC_Misses" } ], "Formula": "a > 5", - "BaseFormula": "metric_TMA_Info_Botlnk_IC_Misses > 5", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_IC_Misses > 5", "ThresholdIssues": "$issueFL" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -12740,7 +12740,7 @@ ], "Constants": [], "Formula": "( 100 * ( 1 - ( 10 * ( a / ( b ) ) * ( max( ( c / ( d + e + f + g ) ) * ( 1 - h / ( i - j ) ) , 0.0001 ) ) / ( c / ( d + e + f + g ) ) ) ) * ( ( c / ( d + e + f + g ) ) + ( ( k / ( d + e + f + g ) - l / ( b ) ) ) * ( ( ( c / ( d + e + f + g ) ) / ( max( 1 - ( ( d / ( d + e + f + g ) - l / ( b ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) ) * m / ( n ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) ) ) * ( b ) / ( 6 ) / h / 100", - "BaseFormula": " tma_mispredictions * tma_info_thread_slots / ( 6 ) / br_misp_retired.all_branches / 100", + "BaseFormula": " tma_bottleneck_mispredictions * tma_info_thread_slots / ( 6 ) / br_misp_retired.all_branches / 100", "Category": "TMA", "CountDomain": "Core_Metric", "Threshold": { @@ -13498,11 +13498,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Memory_Page_Walks_Utilization" + "Value": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization" } ], "Formula": "a > 0.5", - "BaseFormula": "metric_TMA_Info_Memory_Page_Walks_Utilization > 0.5", + "BaseFormula": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization > 0.5", "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", @@ -13628,11 +13628,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Memory_Load_STLB_Miss_Ret" + "Value": "metric_TMA_Info_Memory_TLB_Load_STLB_Miss_Ret" } ], "Formula": "a > 0.05", - "BaseFormula": "metric_TMA_Info_Memory_Load_STLB_Miss_Ret > 0.05", + "BaseFormula": "metric_TMA_Info_Memory_TLB_Load_STLB_Miss_Ret > 0.05", "ThresholdIssues": "" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -13668,11 +13668,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Memory_Store_STLB_Miss_Ret" + "Value": "metric_TMA_Info_Memory_TLB_Store_STLB_Miss_Ret" } ], "Formula": "a > 0.05", - "BaseFormula": "metric_TMA_Info_Memory_Store_STLB_Miss_Ret > 0.05", + "BaseFormula": "metric_TMA_Info_Memory_TLB_Store_STLB_Miss_Ret > 0.05", "ThresholdIssues": "" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -13892,11 +13892,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Memory_Useless_HWPF" + "Value": "metric_TMA_Info_Memory_Prefetches_Useless_HWPF" } ], "Formula": "a > 0.15", - "BaseFormula": "metric_TMA_Info_Memory_Useless_HWPF > 0.15", + "BaseFormula": "metric_TMA_Info_Memory_Prefetches_Useless_HWPF > 0.15", "ThresholdIssues": "" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", diff --git a/GNR/metrics/perf/graniterapids_metrics_perf.json b/GNR/metrics/perf/graniterapids_metrics_perf.json index 5b020ab1..dc51a815 100644 --- a/GNR/metrics/perf/graniterapids_metrics_perf.json +++ b/GNR/metrics/perf/graniterapids_metrics_perf.json @@ -312,13 +312,13 @@ }, { "BriefDescription": "Percent of time that cores are in cstate C0 as observed by the power control unit (PCU)", - "MetricExpr": "100 * ((UNC_P_POWER_STATE_OCCUPANCY_CORES_C0 / (UNC_P_CLOCKTICKS[0] / #num_packages ) ) / ( #num_cores / #num_packages * #num_packages ) )", + "MetricExpr": "100 * ((UNC_P_POWER_STATE_OCCUPANCY_CORES_C0 / (pcu_0@UNC_P_CLOCKTICKS@ / #num_packages ) ) / ( #num_cores / #num_packages * #num_packages ) )", "MetricGroup": "", "MetricName": "cpu_cstate_c0" }, { "BriefDescription": "Percent of time that cores are in cstate C6 as observed by the power control unit (PCU)", - "MetricExpr": "100 * ((UNC_P_POWER_STATE_OCCUPANCY_CORES_C6 / (UNC_P_CLOCKTICKS[0] / #num_packages ) ) / ( #num_cores / #num_packages * #num_packages ) )", + "MetricExpr": "100 * ((UNC_P_POWER_STATE_OCCUPANCY_CORES_C6 / (pcu_0@UNC_P_CLOCKTICKS@ / #num_packages ) ) / ( #num_cores / #num_packages * #num_packages ) )", "MetricGroup": "", "MetricName": "cpu_cstate_c6" }, @@ -343,7 +343,7 @@ }, { "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the back-end)", - "MetricExpr": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\\,cmask\\=0x1@ ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_ms ) ) ) ) - tma_big_code", + "MetricExpr": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\\,cmask\\=0x1@ ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_ms ) ) ) ) - tma_bottleneck_big_code", "MetricGroup": "BvFB;Fed;FetchBW;Frontend;TopdownL1;tma_L1_group;Default;Scaled_Slots", "MetricName": "tma_bottleneck_instruction_fetch_bw", "MetricThreshold": "tma_bottleneck_instruction_fetch_bw > 20", @@ -412,7 +412,7 @@ }, { "BriefDescription": "Total pipeline cost of remaining bottlenecks in the back-end", - "MetricExpr": "100 - ( tma_big_code + tma_instruction_fetch_bw + tma_mispredictions + tma_cache_memory_bandwidth + tma_cache_memory_latency + tma_memory_data_tlbs + tma_memory_synchronization + tma_compute_bound_est + tma_irregular_overhead + tma_branching_overhead + tma_useful_work )", + "MetricExpr": "100 - ( tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottleneck_mispredictions + tma_bottleneck_cache_memory_bandwidth + tma_bottleneck_cache_memory_latency + tma_bottleneck_memory_data_tlbs + tma_bottleneck_memory_synchronization + tma_bottleneck_compute_bound_est + tma_bottleneck_irregular_overhead + tma_bottleneck_branching_overhead + tma_bottleneck_useful_work )", "MetricGroup": "BvOB;Cor;Offcore;TopdownL1;tma_L1_group;Default;Scaled_Slots", "MetricName": "tma_bottleneck_other_bottlenecks", "MetricThreshold": "tma_bottleneck_other_bottlenecks > 20", @@ -1505,7 +1505,7 @@ "MetricExpr": "100 * ( 1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1 ) if tma_info_system_smt_2t_utilization > 0.5 else 0", "MetricGroup": "Cor;SMT;Metric", "MetricName": "tma_info_botlnk_l0_core_bound_likely", - "MetricThreshold": "tma_info_botlnk_core_bound_likely > 0.5" + "MetricThreshold": "tma_info_botlnk_l0_core_bound_likely > 0.5" }, { "BriefDescription": "Instructions Per Cycle (per Logical Processor)", @@ -1548,7 +1548,7 @@ }, { "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor", - "MetricExpr": "tma_info_thread_slots / ( TOPDOWN.SLOTS / 2 ) if #SMT_on else 1", + "MetricExpr": "tma_info_thread_slots / ( slots / 2 ) if #SMT_on else 1", "MetricGroup": "SMT;TmaL1;TopdownL1;tma_L1_group;Metric", "MetricName": "tma_info_thread_slots_utilization" }, @@ -1771,7 +1771,7 @@ "MetricExpr": "IDQ.DSB_UOPS / ( UOPS_ISSUED.ANY )", "MetricGroup": "DSB;Fed;FetchBW;Metric;tma_issueFB", "MetricName": "tma_info_frontend_dsb_coverage", - "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & ipc / 6 > 0.35", + "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 6 > 0.35", "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1849,7 +1849,7 @@ "MetricExpr": "100 * ( tma_fetch_latency * tma_dsb_switches / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_mite / ( tma_mite + tma_dsb + tma_ms ) )", "MetricGroup": "DSBmiss;Fed;Scaled_Slots;tma_issueFB", "MetricName": "tma_info_botlnk_l2_dsb_misses", - "MetricThreshold": "tma_info_botlnk_dsb_misses > 10", + "MetricThreshold": "tma_info_botlnk_l2_dsb_misses > 10", "PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1857,7 +1857,7 @@ "MetricExpr": "100 * ( tma_frontend_bound * ( tma_fetch_bandwidth / ( tma_fetch_latency + tma_fetch_bandwidth ) ) * ( tma_dsb / ( tma_mite + tma_dsb + tma_ms ) ) )", "MetricGroup": "DSB;Fed;FetchBW;Scaled_Slots;tma_issueFB", "MetricName": "tma_info_botlnk_l2_dsb_bandwidth", - "MetricThreshold": "tma_info_botlnk_dsb_bandwidth > 10", + "MetricThreshold": "tma_info_botlnk_l2_dsb_bandwidth > 10", "PublicDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1865,7 +1865,7 @@ "MetricExpr": "100 * ( tma_fetch_latency * tma_icache_misses / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) )", "MetricGroup": "Fed;FetchLat;IcMiss;Scaled_Slots;tma_issueFL", "MetricName": "tma_info_botlnk_l2_ic_misses", - "MetricThreshold": "tma_info_botlnk_ic_misses > 5", + "MetricThreshold": "tma_info_botlnk_l2_ic_misses > 5", "PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck." }, { @@ -1905,7 +1905,7 @@ }, { "BriefDescription": "Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricExpr": "tma_mispredictions * tma_info_thread_slots / ( 6 ) / BR_MISP_RETIRED.ALL_BRANCHES / 100", + "MetricExpr": "tma_bottleneck_mispredictions * tma_info_thread_slots / ( 6 ) / BR_MISP_RETIRED.ALL_BRANCHES / 100", "MetricGroup": "Bad;BrMispredicts;Core_Metric;tma_issueBM", "MetricName": "tma_info_bad_spec_branch_misprediction_cost", "PublicDescription": "Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_bottleneck_mispredictions, tma_branch_mispredicts, tma_mispredicts_resteers." @@ -2048,7 +2048,7 @@ "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 4 * tma_info_core_core_clks )", "MetricGroup": "Mem;MemoryTLB;Core_Metric", "MetricName": "tma_info_memory_tlb_page_walks_utilization", - "MetricThreshold": "tma_info_memory_page_walks_utilization > 0.5" + "MetricThreshold": "tma_info_memory_tlb_page_walks_utilization > 0.5" }, { "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", @@ -2073,14 +2073,14 @@ "MetricExpr": "( MEM_INST_RETIRED.STLB_MISS_LOADS * MEM_INST_RETIRED.STLB_MISS_LOADS:R ) / tma_info_thread_clks", "MetricGroup": "Mem;MemoryTLB;Clocks_Retired", "MetricName": "tma_info_memory_tlb_load_stlb_miss_ret", - "MetricThreshold": "tma_info_memory_load_stlb_miss_ret > 0.05" + "MetricThreshold": "tma_info_memory_tlb_load_stlb_miss_ret > 0.05" }, { "BriefDescription": "This metric represents fraction of cycles the CPU retirement was stalled likely due to STLB misses by demand stores", "MetricExpr": "( MEM_INST_RETIRED.STLB_MISS_STORES * MEM_INST_RETIRED.STLB_MISS_STORES:R ) / tma_info_thread_clks", "MetricGroup": "Mem;MemoryTLB;Clocks_Retired", "MetricName": "tma_info_memory_tlb_store_stlb_miss_ret", - "MetricThreshold": "tma_info_memory_store_stlb_miss_ret > 0.05" + "MetricThreshold": "tma_info_memory_tlb_store_stlb_miss_ret > 0.05" }, { "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", @@ -2123,7 +2123,7 @@ "MetricExpr": "L2_LINES_OUT.USELESS_HWPF / ( L2_LINES_OUT.SILENT + L2_LINES_OUT.NON_SILENT )", "MetricGroup": "Prefetches;Metric", "MetricName": "tma_info_memory_prefetches_useless_hwpf", - "MetricThreshold": "tma_info_memory_useless_hwpf > 0.15" + "MetricThreshold": "tma_info_memory_prefetches_useless_hwpf > 0.15" }, { "BriefDescription": "Average Latency for L2 cache miss demand Loads", diff --git a/HSW/metrics/haswell_metrics.json b/HSW/metrics/haswell_metrics.json index 98f77bb2..299a8008 100644 --- a/HSW/metrics/haswell_metrics.json +++ b/HSW/metrics/haswell_metrics.json @@ -2,7 +2,7 @@ "Header": { "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.", "Info": "Performance Monitoring Metrics for 4th Generation Intel(R) Core(TM) Processor0", - "DatePublished": "11/12/2024", + "DatePublished": "12/02/2024", "Version": "1.0", "Legend": "", "TmaVersion": "5.01", @@ -44,7 +44,15 @@ "Category": "TMA", "CountDomain": "Slots", "Threshold": { - "Formula": "metric_TMA_Frontend_Bound(%) > 15" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 15", + "BaseFormula": "metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "BvFB;BvIO;TmaL1;PGO", @@ -86,7 +94,19 @@ "Category": "TMA", "CountDomain": "Slots", "Threshold": { - "Formula": "metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 15", + "BaseFormula": "metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Frontend;TmaL2", @@ -115,7 +135,23 @@ "Category": "TMA", "CountDomain": "Clocks", "Threshold": { - "Formula": "metric_TMA_....ICache_Misses(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....ICache_Misses(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....ICache_Misses(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "BigFootprint;BvBC;FetchLat;IcMiss", @@ -148,7 +184,23 @@ "Category": "TMA", "CountDomain": "Clocks", "Threshold": { - "Formula": "metric_TMA_....ITLB_Misses(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....ITLB_Misses(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....ITLB_Misses(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "BigFootprint;BvBC;FetchLat;MemoryTLB", @@ -185,7 +237,23 @@ "Category": "TMA", "CountDomain": "Clocks", "Threshold": { - "Formula": "metric_TMA_....Branch_Resteers(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Branch_Resteers(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....Branch_Resteers(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "~overlap" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "FetchLat", @@ -214,7 +282,23 @@ "Category": "TMA", "CountDomain": "Clocks_Estimated", "Threshold": { - "Formula": "metric_TMA_....MS_Switches(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....MS_Switches(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....MS_Switches(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "$issueMC, $issueMS, $issueMV, $issueSO" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "FetchLat;MicroSeq", @@ -243,7 +327,23 @@ "Category": "TMA", "CountDomain": "Clocks", "Threshold": { - "Formula": "metric_TMA_....LCP(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....LCP(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....LCP(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "FetchLat", @@ -272,7 +372,23 @@ "Category": "TMA", "CountDomain": "Clocks", "Threshold": { - "Formula": "metric_TMA_....DSB_Switches(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....DSB_Switches(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....DSB_Switches(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "DSBmiss;FetchLat", @@ -318,7 +434,15 @@ "Category": "TMA", "CountDomain": "Slots", "Threshold": { - "Formula": "metric_TMA_..Fetch_Bandwidth(%) > 20" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Fetch_Bandwidth(%)" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_..Fetch_Bandwidth(%) > 20", + "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "FetchBW;Frontend;TmaL2", @@ -364,7 +488,19 @@ "Category": "TMA", "CountDomain": "Slots_Estimated", "Threshold": { - "Formula": "metric_TMA_....MITE(%) > 10 & metric_TMA_..Fetch_Bandwidth(%) > 20" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....MITE(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Bandwidth(%)" + } + ], + "Formula": "a > 10 & b > 20", + "BaseFormula": "metric_TMA_....MITE(%) > 10 & metric_TMA_..Fetch_Bandwidth(%) > 20", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "DSBmiss;FetchBW", @@ -410,7 +546,19 @@ "Category": "TMA", "CountDomain": "Slots_Estimated", "Threshold": { - "Formula": "metric_TMA_....DSB(%) > 15 & metric_TMA_..Fetch_Bandwidth(%) > 20" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....DSB(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Bandwidth(%)" + } + ], + "Formula": "a > 15 & b > 20", + "BaseFormula": "metric_TMA_....DSB(%) > 15 & metric_TMA_..Fetch_Bandwidth(%) > 20", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "DSB;FetchBW", @@ -463,7 +611,15 @@ "Category": "TMA", "CountDomain": "Slots", "Threshold": { - "Formula": "metric_TMA_Bad_Speculation(%) > 15" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bad_Speculation(%)" + } + ], + "Formula": "a > 15", + "BaseFormula": "metric_TMA_Bad_Speculation(%) > 15", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "TmaL1", @@ -525,7 +681,19 @@ "Category": "TMA", "CountDomain": "Slots", "Threshold": { - "Formula": "metric_TMA_..Branch_Mispredicts(%) > 10 & metric_TMA_Bad_Speculation(%) > 15" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Branch_Mispredicts(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Bad_Speculation(%)" + } + ], + "Formula": "a > 10 & b > 15", + "BaseFormula": "metric_TMA_..Branch_Mispredicts(%) > 10 & metric_TMA_Bad_Speculation(%) > 15", + "ThresholdIssues": "$issueBM" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "BadSpec;BrMispredicts;BvMP;TmaL2", @@ -587,7 +755,19 @@ "Category": "TMA", "CountDomain": "Slots", "Threshold": { - "Formula": "metric_TMA_..Machine_Clears(%) > 10 & metric_TMA_Bad_Speculation(%) > 15" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Machine_Clears(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Bad_Speculation(%)" + } + ], + "Formula": "a > 10 & b > 15", + "BaseFormula": "metric_TMA_..Machine_Clears(%) > 10 & metric_TMA_Bad_Speculation(%) > 15", + "ThresholdIssues": "$issueMC, $issueSyncxn" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "BadSpec;BvMS;MachineClears;TmaL2", @@ -644,7 +824,15 @@ "Category": "TMA", "CountDomain": "Slots", "Threshold": { - "Formula": "metric_TMA_Backend_Bound(%) > 20" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "BvOB;TmaL1", @@ -738,7 +926,19 @@ "Category": "TMA", "CountDomain": "Slots", "Threshold": { - "Formula": "metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 20", + "BaseFormula": "metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Backend;TmaL2", @@ -771,7 +971,23 @@ "Category": "TMA", "CountDomain": "Stalls", "Threshold": { - "Formula": "metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 20 & c > 20", + "BaseFormula": "metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueL1, $issueMC" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "CacheHits;MemoryBound;TmaL3mem", @@ -804,7 +1020,27 @@ "Category": "TMA", "CountDomain": "Clocks_Estimated", "Threshold": { - "Formula": "metric_TMA_......DTLB_Load(%) > 10 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......DTLB_Load(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......DTLB_Load(%) > 10 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueTLB" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "BvMT;MemoryTLB", @@ -833,7 +1069,27 @@ "Category": "TMA", "CountDomain": "Clocks_Estimated", "Threshold": { - "Formula": "metric_TMA_......Store_Fwd_Blk(%) > 10 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Store_Fwd_Blk(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......Store_Fwd_Blk(%) > 10 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "", @@ -870,7 +1126,27 @@ "Category": "TMA", "CountDomain": "Clocks", "Threshold": { - "Formula": "metric_TMA_......Lock_Latency(%) > 20 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Lock_Latency(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 10 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......Lock_Latency(%) > 20 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueRFO" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "LockCont;Offcore", @@ -911,7 +1187,15 @@ "Category": "TMA", "CountDomain": "Clocks_Calculated", "Threshold": { - "Formula": "metric_TMA_......Split_Loads(%) > 30" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Split_Loads(%)" + } + ], + "Formula": "a > 30", + "BaseFormula": "metric_TMA_......Split_Loads(%) > 30", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "", @@ -940,7 +1224,27 @@ "Category": "TMA", "CountDomain": "Clocks_Estimated", "Threshold": { - "Formula": "metric_TMA_......4K_Aliasing(%) > 20 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......4K_Aliasing(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 10 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......4K_Aliasing(%) > 20 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "", @@ -981,7 +1285,15 @@ "Category": "TMA", "CountDomain": "Clocks_Calculated", "Threshold": { - "Formula": "metric_TMA_......FB_Full(%) > 30" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......FB_Full(%)" + } + ], + "Formula": "a > 30", + "BaseFormula": "metric_TMA_......FB_Full(%) > 30", + "ThresholdIssues": "$issueBW, $issueSL, $issueSmSt" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "BvMB;MemoryBW", @@ -1014,7 +1326,23 @@ "Category": "TMA", "CountDomain": "Stalls", "Threshold": { - "Formula": "metric_TMA_....L2_Bound(%) > 5 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....L2_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 20 & c > 20", + "BaseFormula": "metric_TMA_....L2_Bound(%) > 5 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "BvML;CacheHits;MemoryBound;TmaL3mem", @@ -1051,7 +1379,23 @@ "Category": "TMA", "CountDomain": "Stalls", "Threshold": { - "Formula": "metric_TMA_....L3_Bound(%) > 5 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....L3_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 20 & c > 20", + "BaseFormula": "metric_TMA_....L3_Bound(%) > 5 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "CacheHits;MemoryBound;TmaL3mem", @@ -1104,7 +1448,27 @@ "Category": "TMA", "CountDomain": "Clocks_Estimated", "Threshold": { - "Formula": "metric_TMA_......Contested_Accesses(%) > 5 & metric_TMA_....L3_Bound(%) > 5 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Contested_Accesses(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L3_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......Contested_Accesses(%) > 5 & metric_TMA_....L3_Bound(%) > 5 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueSyncxn" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "BvMS;DataSharing;LockCont;Offcore;Snoop", @@ -1157,7 +1521,27 @@ "Category": "TMA", "CountDomain": "Clocks_Estimated", "Threshold": { - "Formula": "metric_TMA_......Data_Sharing(%) > 5 & metric_TMA_....L3_Bound(%) > 5 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Data_Sharing(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L3_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......Data_Sharing(%) > 5 & metric_TMA_....L3_Bound(%) > 5 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueSyncxn" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "BvMS;Offcore;Snoop", @@ -1210,7 +1594,27 @@ "Category": "TMA", "CountDomain": "Clocks_Estimated", "Threshold": { - "Formula": "metric_TMA_......L3_Hit_Latency(%) > 10 & metric_TMA_....L3_Bound(%) > 5 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......L3_Hit_Latency(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L3_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 5 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......L3_Hit_Latency(%) > 10 & metric_TMA_....L3_Bound(%) > 5 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueLat, ~overlap" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "BvML;MemoryLat", @@ -1252,7 +1656,27 @@ "Category": "TMA", "CountDomain": "Clocks", "Threshold": { - "Formula": "metric_TMA_......SQ_Full(%) > 30 & metric_TMA_....L3_Bound(%) > 5 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......SQ_Full(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L3_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 30 & b > 5 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......SQ_Full(%) > 30 & metric_TMA_....L3_Bound(%) > 5 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueBW" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "BvMB;MemoryBW;Offcore", @@ -1289,7 +1713,23 @@ "Category": "TMA", "CountDomain": "Stalls", "Threshold": { - "Formula": "metric_TMA_....DRAM_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....DRAM_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 20 & c > 20", + "BaseFormula": "metric_TMA_....DRAM_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryBound;TmaL3mem", @@ -1318,7 +1758,27 @@ "Category": "TMA", "CountDomain": "Clocks", "Threshold": { - "Formula": "metric_TMA_......MEM_Bandwidth(%) > 20 & metric_TMA_....DRAM_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......MEM_Bandwidth(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....DRAM_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 10 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......MEM_Bandwidth(%) > 20 & metric_TMA_....DRAM_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueBW" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "BvMB;MemoryBW;Offcore", @@ -1351,7 +1811,27 @@ "Category": "TMA", "CountDomain": "Clocks", "Threshold": { - "Formula": "metric_TMA_......MEM_Latency(%) > 10 & metric_TMA_....DRAM_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......MEM_Latency(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....DRAM_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......MEM_Latency(%) > 10 & metric_TMA_....DRAM_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueLat" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "BvML;MemoryLat;Offcore", @@ -1380,7 +1860,23 @@ "Category": "TMA", "CountDomain": "Stalls", "Threshold": { - "Formula": "metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 20 & c > 20", + "BaseFormula": "metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryBound;TmaL3mem", @@ -1421,7 +1917,27 @@ "Category": "TMA", "CountDomain": "Clocks_Estimated", "Threshold": { - "Formula": "metric_TMA_......Store_Latency(%) > 10 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Store_Latency(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 20 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......Store_Latency(%) > 10 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueRFO, $issueSL, ~overlap" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "BvML;LockCont;MemoryLat;Offcore", @@ -1450,7 +1966,27 @@ "Category": "TMA", "CountDomain": "Clocks_Estimated", "Threshold": { - "Formula": "metric_TMA_......False_Sharing(%) > 5 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......False_Sharing(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 20 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......False_Sharing(%) > 5 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueSyncxn" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "BvMS;DataSharing;LockCont;Offcore;Snoop", @@ -1492,7 +2028,27 @@ "Category": "TMA", "CountDomain": "Core_Utilization", "Threshold": { - "Formula": "metric_TMA_......Split_Stores(%) > 20 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Split_Stores(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 20 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......Split_Stores(%) > 20 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueSpSt" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "", @@ -1525,7 +2081,27 @@ "Category": "TMA", "CountDomain": "Clocks_Estimated", "Threshold": { - "Formula": "metric_TMA_......DTLB_Store(%) > 5 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......DTLB_Store(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 20 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......DTLB_Store(%) > 5 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueTLB" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "BvMT;MemoryTLB", @@ -1619,7 +2195,19 @@ "Category": "TMA", "CountDomain": "Slots", "Threshold": { - "Formula": "metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 20", + "BaseFormula": "metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Backend;TmaL2;Compute", @@ -1661,7 +2249,23 @@ "Category": "TMA", "CountDomain": "Clocks", "Threshold": { - "Formula": "metric_TMA_....Divider(%) > 20 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Divider(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 10 & c > 20", + "BaseFormula": "metric_TMA_....Divider(%) > 20 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "BvCB", @@ -1735,7 +2339,23 @@ "Category": "TMA", "CountDomain": "Clocks", "Threshold": { - "Formula": "metric_TMA_....Ports_Utilization(%) > 15 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Ports_Utilization(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 15 & b > 10 & c > 20", + "BaseFormula": "metric_TMA_....Ports_Utilization(%) > 15 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "PortsUtil", @@ -1789,7 +2409,27 @@ "Category": "TMA", "CountDomain": "Clocks", "Threshold": { - "Formula": "metric_TMA_......Ports_Utilized_0(%) > 20 & metric_TMA_....Ports_Utilization(%) > 15 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Ports_Utilized_0(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Ports_Utilization(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 15 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......Ports_Utilized_0(%) > 20 & metric_TMA_....Ports_Utilization(%) > 15 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "PortsUtil", @@ -1835,7 +2475,27 @@ "Category": "TMA", "CountDomain": "Clocks", "Threshold": { - "Formula": "metric_TMA_......Ports_Utilized_1(%) > 20 & metric_TMA_....Ports_Utilization(%) > 15 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Ports_Utilized_1(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Ports_Utilization(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 15 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......Ports_Utilized_1(%) > 20 & metric_TMA_....Ports_Utilization(%) > 15 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueL1" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "PortsUtil", @@ -1881,7 +2541,27 @@ "Category": "TMA", "CountDomain": "Clocks", "Threshold": { - "Formula": "metric_TMA_......Ports_Utilized_2(%) > 15 & metric_TMA_....Ports_Utilization(%) > 15 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Ports_Utilized_2(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Ports_Utilization(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 15 & b > 15 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......Ports_Utilized_2(%) > 15 & metric_TMA_....Ports_Utilization(%) > 15 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issue2P" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "PortsUtil", @@ -1923,7 +2603,27 @@ "Category": "TMA", "CountDomain": "Clocks", "Threshold": { - "Formula": "metric_TMA_......Ports_Utilized_3m(%) > 40 & metric_TMA_....Ports_Utilization(%) > 15 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Ports_Utilized_3m(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Ports_Utilization(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 40 & b > 15 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......Ports_Utilized_3m(%) > 40 & metric_TMA_....Ports_Utilization(%) > 15 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "BvCB;PortsUtil", @@ -1977,7 +2677,15 @@ "Category": "TMA", "CountDomain": "Core_Execution", "Threshold": { - "Formula": "metric_TMA_........ALU_Op_Utilization(%) > 40" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........ALU_Op_Utilization(%)" + } + ], + "Formula": "a > 40", + "BaseFormula": "metric_TMA_........ALU_Op_Utilization(%) > 40", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "", @@ -2019,7 +2727,15 @@ "Category": "TMA", "CountDomain": "Core_Clocks", "Threshold": { - "Formula": "metric_TMA_..........Port_0(%) > 60" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Port_0(%)" + } + ], + "Formula": "a > 60", + "BaseFormula": "metric_TMA_..........Port_0(%) > 60", + "ThresholdIssues": "$issue2P" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Compute", @@ -2061,7 +2777,15 @@ "Category": "TMA", "CountDomain": "Core_Clocks", "Threshold": { - "Formula": "metric_TMA_..........Port_1(%) > 60" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Port_1(%)" + } + ], + "Formula": "a > 60", + "BaseFormula": "metric_TMA_..........Port_1(%) > 60", + "ThresholdIssues": "$issue2P" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "", @@ -2103,7 +2827,15 @@ "Category": "TMA", "CountDomain": "Core_Clocks", "Threshold": { - "Formula": "metric_TMA_..........Port_5(%) > 60" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Port_5(%)" + } + ], + "Formula": "a > 60", + "BaseFormula": "metric_TMA_..........Port_5(%) > 60", + "ThresholdIssues": "$issue2P" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "", @@ -2145,7 +2877,15 @@ "Category": "TMA", "CountDomain": "Core_Clocks", "Threshold": { - "Formula": "metric_TMA_..........Port_6(%) > 60" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Port_6(%)" + } + ], + "Formula": "a > 60", + "BaseFormula": "metric_TMA_..........Port_6(%) > 60", + "ThresholdIssues": "$issue2P" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "", @@ -2199,7 +2939,15 @@ "Category": "TMA", "CountDomain": "Core_Execution", "Threshold": { - "Formula": "metric_TMA_........Load_Op_Utilization(%) > 60" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Load_Op_Utilization(%)" + } + ], + "Formula": "a > 60", + "BaseFormula": "metric_TMA_........Load_Op_Utilization(%) > 60", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "", @@ -2241,7 +2989,15 @@ "Category": "TMA", "CountDomain": "Core_Clocks", "Threshold": { - "Formula": "metric_TMA_..........Port_2(%) > 60" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Port_2(%)" + } + ], + "Formula": "a > 60", + "BaseFormula": "metric_TMA_..........Port_2(%) > 60", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "", @@ -2283,7 +3039,15 @@ "Category": "TMA", "CountDomain": "Core_Clocks", "Threshold": { - "Formula": "metric_TMA_..........Port_3(%) > 60" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Port_3(%)" + } + ], + "Formula": "a > 60", + "BaseFormula": "metric_TMA_..........Port_3(%) > 60", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "", @@ -2325,7 +3089,15 @@ "Category": "TMA", "CountDomain": "Core_Execution", "Threshold": { - "Formula": "metric_TMA_........Store_Op_Utilization(%) > 60" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Store_Op_Utilization(%)" + } + ], + "Formula": "a > 60", + "BaseFormula": "metric_TMA_........Store_Op_Utilization(%) > 60", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "", @@ -2367,7 +3139,15 @@ "Category": "TMA", "CountDomain": "Core_Clocks", "Threshold": { - "Formula": "metric_TMA_..........Port_4(%) > 60" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Port_4(%)" + } + ], + "Formula": "a > 60", + "BaseFormula": "metric_TMA_..........Port_4(%) > 60", + "ThresholdIssues": "$issueSpSt" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "", @@ -2409,7 +3189,15 @@ "Category": "TMA", "CountDomain": "Core_Clocks", "Threshold": { - "Formula": "metric_TMA_..........Port_7(%) > 60" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Port_7(%)" + } + ], + "Formula": "a > 60", + "BaseFormula": "metric_TMA_..........Port_7(%) > 60", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "", @@ -2450,7 +3238,19 @@ "Category": "TMA", "CountDomain": "Slots", "Threshold": { - "Formula": "metric_TMA_Retiring(%) > 70 | metric_TMA_..Heavy_Operations(%) > 10" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Retiring(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 70 | b > 10", + "BaseFormula": "metric_TMA_Retiring(%) > 70 | metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "BvUW;TmaL1", @@ -2500,7 +3300,15 @@ "Category": "TMA", "CountDomain": "Slots", "Threshold": { - "Formula": "metric_TMA_..Light_Operations(%) > 60" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 60", + "BaseFormula": "metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Retire;TmaL2", @@ -2550,7 +3358,15 @@ "Category": "TMA", "CountDomain": "Slots", "Threshold": { - "Formula": "metric_TMA_..Heavy_Operations(%) > 10" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 10", + "BaseFormula": "metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Retire;TmaL2", @@ -2600,7 +3416,19 @@ "Category": "TMA", "CountDomain": "Slots", "Threshold": { - "Formula": "metric_TMA_....Microcode_Sequencer(%) > 5 & metric_TMA_..Heavy_Operations(%) > 10" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Microcode_Sequencer(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 5 & b > 10", + "BaseFormula": "metric_TMA_....Microcode_Sequencer(%) > 5 & metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "$issueMC, $issueMS" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MicroSeq", @@ -2642,7 +3470,23 @@ "Category": "TMA", "CountDomain": "Slots_Estimated", "Threshold": { - "Formula": "metric_TMA_......Assists(%) > 10 & metric_TMA_....Microcode_Sequencer(%) > 5 & metric_TMA_..Heavy_Operations(%) > 10" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Assists(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Microcode_Sequencer(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 10 & b > 5 & c > 10", + "BaseFormula": "metric_TMA_......Assists(%) > 10 & metric_TMA_....Microcode_Sequencer(%) > 5 & metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "BvIO", @@ -2696,7 +3540,23 @@ "Category": "TMA", "CountDomain": "Slots", "Threshold": { - "Formula": "metric_TMA_......CISC(%) > 10 & metric_TMA_....Microcode_Sequencer(%) > 5 & metric_TMA_..Heavy_Operations(%) > 10" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......CISC(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Microcode_Sequencer(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 10 & b > 5 & c > 10", + "BaseFormula": "metric_TMA_......CISC(%) > 10 & metric_TMA_....Microcode_Sequencer(%) > 5 & metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "", @@ -2723,6 +3583,11 @@ "BaseFormula": " inst_retired.any / tma_info_thread_clks", "Category": "TMA", "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Ret;Summary", "LocateWith": "" @@ -2749,7 +3614,15 @@ "Category": "TMA", "CountDomain": "Metric", "Threshold": { - "Formula": "metric_TMA_Info_Thread_UopPI > 1.05" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Thread_UopPI" + } + ], + "Formula": "a > 1.05", + "BaseFormula": "metric_TMA_Info_Thread_UopPI > 1.05", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Pipeline;Ret;Retire", @@ -2777,7 +3650,15 @@ "Category": "TMA", "CountDomain": "Metric", "Threshold": { - "Formula": "metric_TMA_Info_Thread_UpTB < 4 * 1.5" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Thread_UpTB" + } + ], + "Formula": "a < 4 * 1.5", + "BaseFormula": "metric_TMA_Info_Thread_UpTB < 4 * 1.5", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Branches;Fed;FetchBW", @@ -2804,6 +3685,11 @@ "BaseFormula": " 1 / tma_info_thread_ipc", "Category": "TMA", "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Pipeline;Mem", "LocateWith": "" @@ -2825,6 +3711,11 @@ "BaseFormula": " cpu_clk_unhalted.thread", "Category": "TMA", "CountDomain": "Count", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Pipeline", "LocateWith": "" @@ -2859,6 +3750,11 @@ "BaseFormula": " ( 4 ) * tma_info_core_core_clks", "Category": "TMA", "CountDomain": "Count", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "TmaL1", "LocateWith": "" @@ -2897,6 +3793,11 @@ "BaseFormula": " inst_retired.any / tma_info_core_core_clks", "Category": "TMA", "CountDomain": "Core_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Ret;SMT;TmaL1", "LocateWith": "" @@ -2931,6 +3832,11 @@ "BaseFormula": " ( uops_executed.core / 2 / ( ( uops_executed.core:c1 / 2 ) if smt_on else uops_executed.core:c1 ) ) if smt_on else uops_executed.core / ( ( uops_executed.core:c1 / 2 ) if smt_on else uops_executed.core:c1 )", "Category": "TMA", "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "LocateWith": "" @@ -2965,6 +3871,11 @@ "BaseFormula": " ( cpu_clk_unhalted.thread_any / 2 ) if smt_on else tma_info_thread_clks", "Category": "TMA", "CountDomain": "Count", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "SMT", "LocateWith": "" @@ -2991,7 +3902,15 @@ "Category": "TMA", "CountDomain": "Inst_Metric", "Threshold": { - "Formula": "metric_TMA_Info_Inst_Mix_IpLoad < 3" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpLoad" + } + ], + "Formula": "a < 3", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpLoad < 3", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "InsType", @@ -3019,7 +3938,15 @@ "Category": "TMA", "CountDomain": "Inst_Metric", "Threshold": { - "Formula": "metric_TMA_Info_Inst_Mix_IpStore < 8" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpStore" + } + ], + "Formula": "a < 8", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpStore < 8", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "InsType", @@ -3047,7 +3974,15 @@ "Category": "TMA", "CountDomain": "Inst_Metric", "Threshold": { - "Formula": "metric_TMA_Info_Inst_Mix_IpBranch < 8" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpBranch" + } + ], + "Formula": "a < 8", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpBranch < 8", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Branches;Fed;InsType", @@ -3075,7 +4010,15 @@ "Category": "TMA", "CountDomain": "Inst_Metric", "Threshold": { - "Formula": "metric_TMA_Info_Inst_Mix_IpCall < 200" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpCall" + } + ], + "Formula": "a < 200", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpCall < 200", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Branches;Fed;PGO", @@ -3103,7 +4046,15 @@ "Category": "TMA", "CountDomain": "Inst_Metric", "Threshold": { - "Formula": "metric_TMA_Info_Inst_Mix_IpTB < 4 * 2 + 1" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpTB" + } + ], + "Formula": "a < 4 * 2 + 1", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpTB < 4 * 2 + 1", + "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", @@ -3130,6 +4081,11 @@ "BaseFormula": " br_inst_retired.all_branches / br_inst_retired.near_taken", "Category": "TMA", "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Branches;Fed;PGO", "LocateWith": "" @@ -3151,6 +4107,11 @@ "BaseFormula": " inst_retired.any", "Category": "TMA", "CountDomain": "Count", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Summary;TmaL1", "LocateWith": "INST_RETIRED.PREC_DIST" @@ -3176,6 +4137,11 @@ "BaseFormula": " ( uops_retired.retire_slots ) / uops_retired.retire_slots:c1", "Category": "TMA", "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Pipeline;Ret", "LocateWith": "" @@ -3210,7 +4176,19 @@ "Category": "TMA", "CountDomain": "Metric", "Threshold": { - "Formula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & IPC / 4 > 0.35" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Frontend_DSB_Coverage" + }, + { + "Alias": "b", + "Value": "metric_TMA_Info_Thread_IPC" + } + ], + "Formula": "a < 0.7 & b / 4 > 0.35", + "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & metric_TMA_Info_Thread_IPC / 4 > 0.35", + "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "DSB;Fed;FetchBW", @@ -3237,6 +4215,11 @@ "BaseFormula": " br_inst_retired.near_taken / tma_info_thread_clks", "Category": "TMA", "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Branches;FetchBW", "LocateWith": "" @@ -3262,6 +4245,11 @@ "BaseFormula": " tma_info_inst_mix_instructions / baclears.any", "Category": "TMA", "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Fed", "LocateWith": "" @@ -3288,7 +4276,15 @@ "Category": "TMA", "CountDomain": "Inst_Metric", "Threshold": { - "Formula": "metric_TMA_Info_Bad_Spec_IpMispredict < 200" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Bad_Spec_IpMispredict" + } + ], + "Formula": "a < 200", + "BaseFormula": "metric_TMA_Info_Bad_Spec_IpMispredict < 200", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Bad;BadSpec;BrMispredicts", @@ -3324,7 +4320,15 @@ "Category": "TMA", "CountDomain": "Inst_Metric", "Threshold": { - "Formula": "metric_TMA_Info_Bad_Spec_IpMisp_Indirect < 1000" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Bad_Spec_IpMisp_Indirect" + } + ], + "Formula": "a < 1000", + "BaseFormula": "metric_TMA_Info_Bad_Spec_IpMisp_Indirect < 1000", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Bad;BrMispredicts", @@ -3355,6 +4359,11 @@ "BaseFormula": " l1d_pend_miss.pending / ( mem_load_uops_retired.l1_miss + mem_load_uops_retired.hit_lfb )", "Category": "TMA", "CountDomain": "Clocks_Latency", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Mem;MemoryBound;MemoryLat", "LocateWith": "" @@ -3380,6 +4389,11 @@ "BaseFormula": " l1d_pend_miss.pending / l1d_pend_miss.pending_cycles", "Category": "TMA", "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Mem;MemoryBound;MemoryBW", "LocateWith": "" @@ -3405,6 +4419,11 @@ "BaseFormula": " 1000 * mem_load_uops_retired.l1_miss / inst_retired.any", "Category": "TMA", "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "CacheHits;Mem", "LocateWith": "" @@ -3430,6 +4449,11 @@ "BaseFormula": " 1000 * mem_load_uops_retired.l2_miss / inst_retired.any", "Category": "TMA", "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Mem;Backend;CacheHits", "LocateWith": "" @@ -3455,6 +4479,11 @@ "BaseFormula": " 1000 * offcore_requests.demand_rfo / inst_retired.any", "Category": "TMA", "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "CacheMisses;Offcore", "LocateWith": "" @@ -3480,6 +4509,11 @@ "BaseFormula": " 1000 * mem_load_uops_retired.l3_miss / inst_retired.any", "Category": "TMA", "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Mem", "LocateWith": "" @@ -3506,6 +4540,11 @@ "BaseFormula": " 64 * l1d.replacement / ( 1000000000 ) / tma_info_system_time", "Category": "TMA", "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Mem;MemoryBW", "LocateWith": "" @@ -3532,6 +4571,11 @@ "BaseFormula": " 64 * l2_lines_in.all / ( 1000000000 ) / tma_info_system_time", "Category": "TMA", "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Mem;MemoryBW", "LocateWith": "" @@ -3558,6 +4602,11 @@ "BaseFormula": " 64 * longest_lat_cache.miss / ( 1000000000 ) / tma_info_system_time", "Category": "TMA", "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Mem;MemoryBW", "LocateWith": "" @@ -3605,7 +4654,15 @@ "Category": "TMA", "CountDomain": "Core_Metric", "Threshold": { - "Formula": "metric_TMA_Info_Memory_Page_Walks_Utilization > 0.5" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization" + } + ], + "Formula": "a > 0.5", + "BaseFormula": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization > 0.5", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Mem;MemoryTLB", @@ -3633,6 +4690,11 @@ "BaseFormula": " tma_info_memory_l1d_cache_fill_bw", "Category": "TMA", "CountDomain": "Core_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Mem;MemoryBW", "LocateWith": "" @@ -3659,6 +4721,11 @@ "BaseFormula": " tma_info_memory_l2_cache_fill_bw", "Category": "TMA", "CountDomain": "Core_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Mem;MemoryBW", "LocateWith": "" @@ -3685,6 +4752,11 @@ "BaseFormula": " tma_info_memory_l3_cache_fill_bw", "Category": "TMA", "CountDomain": "Core_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Mem;MemoryBW", "LocateWith": "" @@ -3710,6 +4782,11 @@ "BaseFormula": " offcore_requests_outstanding.demand_data_rd / offcore_requests.demand_data_rd", "Category": "TMA", "CountDomain": "Clocks_Latency", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "LockCont;Memory_Lat;Offcore", "LocateWith": "" @@ -3735,6 +4812,11 @@ "BaseFormula": " offcore_requests_outstanding.demand_data_rd / offcore_requests_outstanding.cycles_with_demand_data_rd", "Category": "TMA", "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Memory_BW;Offcore", "LocateWith": "" @@ -3760,6 +4842,11 @@ "BaseFormula": " offcore_requests_outstanding.all_data_rd / offcore_requests_outstanding.cycles_with_data_rd", "Category": "TMA", "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Memory_BW;Offcore", "LocateWith": "" @@ -3790,6 +4877,11 @@ "BaseFormula": " tma_info_system_cpus_utilized / num_cpus", "Category": "TMA", "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "HPC;Summary", "LocateWith": "" @@ -3816,6 +4908,11 @@ "BaseFormula": " cpu_clk_unhalted.ref_tsc / tsc", "Category": "TMA", "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Summary", "LocateWith": "" @@ -3850,6 +4947,11 @@ "BaseFormula": " tma_info_system_turbo_utilization * tsc / ( 1000000000 ) / tma_info_system_time", "Category": "TMA", "CountDomain": "System_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, "ResolutionLevels": "SYSTEM", "MetricGroup": "Summary;Power", "LocateWith": "" @@ -3875,6 +4977,11 @@ "BaseFormula": " tma_info_thread_clks / cpu_clk_unhalted.ref_tsc", "Category": "TMA", "CountDomain": "Core_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Power", "LocateWith": "" @@ -3909,6 +5016,11 @@ "BaseFormula": " 1 - cpu_clk_unhalted.one_thread_active / ( cpu_clk_unhalted.ref_xclk_any / 2 ) if smt_on else 0", "Category": "TMA", "CountDomain": "Core_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "SMT", "LocateWith": "" @@ -3935,7 +5047,15 @@ "Category": "TMA", "CountDomain": "Metric", "Threshold": { - "Formula": "metric_TMA_Info_System_Kernel_Utilization > 0.05" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_System_Kernel_Utilization" + } + ], + "Formula": "a > 0.05", + "BaseFormula": "metric_TMA_Info_System_Kernel_Utilization > 0.05", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "OS", @@ -3962,6 +5082,11 @@ "BaseFormula": " cpu_clk_unhalted.thread_p:sup / inst_retired.any_p:sup", "Category": "TMA", "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "OS", "LocateWith": "" @@ -3992,6 +5117,11 @@ "BaseFormula": " 64 * ( unc_arb_trk_requests.all + unc_arb_coh_trk_requests.all ) / ( 1000000 ) / tma_info_system_time / 1000", "Category": "TMA", "CountDomain": "GB/sec", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "$issueBW" + }, "ResolutionLevels": "ARB", "MetricGroup": "HPC;MemOffcore;MemoryBW;SoC", "LocateWith": "" @@ -4018,6 +5148,11 @@ "BaseFormula": " unc_pkg_energy_status * ( 61 ) / ( tma_info_system_time * ( 1000000 ) )", "Category": "TMA", "CountDomain": "System_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, "ResolutionLevels": "PKG", "MetricGroup": "Power;SoC", "LocateWith": "" @@ -4040,7 +5175,15 @@ "Category": "TMA", "CountDomain": "Seconds", "Threshold": { - "Formula": "metric_TMA_Info_System_Time < 1" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_System_Time" + } + ], + "Formula": "a < 1", + "BaseFormula": "metric_TMA_Info_System_Time < 1", + "ThresholdIssues": "" }, "ResolutionLevels": "SOCKET, SYSTEM", "MetricGroup": "Summary", @@ -4068,7 +5211,15 @@ "Category": "TMA", "CountDomain": "Clocks", "Threshold": { - "Formula": "metric_TMA_Info_System_MUX > 1.1 | metric_TMA_Info_System_MUX < 0.9" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_System_MUX" + } + ], + "Formula": "a > 1.1 | a < 0.9", + "BaseFormula": "metric_TMA_Info_System_MUX > 1.1 | metric_TMA_Info_System_MUX < 0.9", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Summary", @@ -4091,6 +5242,11 @@ "BaseFormula": " unc_clock.socket", "Category": "TMA", "CountDomain": "Count", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, "ResolutionLevels": "CLOCK", "MetricGroup": "SoC", "LocateWith": "" @@ -4117,7 +5273,15 @@ "Category": "TMA", "CountDomain": "Inst_Metric", "Threshold": { - "Formula": "metric_TMA_Info_System_IpFarBranch < 1000000" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_System_IpFarBranch" + } + ], + "Formula": "a < 1000000", + "BaseFormula": "metric_TMA_Info_System_IpFarBranch < 1000000", + "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Branches;OS", diff --git a/HSW/metrics/perf/haswell_metrics_perf.json b/HSW/metrics/perf/haswell_metrics_perf.json index b1fc8d01..a33796ef 100644 --- a/HSW/metrics/perf/haswell_metrics_perf.json +++ b/HSW/metrics/perf/haswell_metrics_perf.json @@ -5,7 +5,7 @@ "MetricGroup": "BvFB;BvIO;TmaL1;PGO;TopdownL1;tma_L1_group;Slots", "MetricName": "tma_frontend_bound", "ScaleUnit": "100%", - "MetricThreshold": "tma_frontend_bound > 15", + "MetricThreshold": "tma_frontend_bound > 0.15", "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound." }, { @@ -14,7 +14,7 @@ "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;Slots", "MetricName": "tma_fetch_latency", "ScaleUnit": "100%", - "MetricThreshold": "tma_fetch_latency > 10 & tma_frontend_bound > 15", + "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END." }, { @@ -23,7 +23,7 @@ "MetricGroup": "BigFootprint;BvBC;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group;Clocks", "MetricName": "tma_icache_misses", "ScaleUnit": "100%", - "MetricThreshold": "tma_icache_misses > 5 & tma_fetch_latency > 10 & tma_frontend_bound > 15" + "MetricThreshold": "tma_icache_misses > 0.05 & tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15" }, { "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", @@ -31,53 +31,53 @@ "MetricGroup": "BigFootprint;BvBC;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group;Clocks", "MetricName": "tma_itlb_misses", "ScaleUnit": "100%", - "MetricThreshold": "tma_itlb_misses > 5 & tma_fetch_latency > 10 & tma_frontend_bound > 15", + "MetricThreshold": "tma_itlb_misses > 0.05 & tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.WALK_COMPLETED." }, { "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", "MetricExpr": "( 12 ) * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / tma_info_thread_clks", - "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;Clocks", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;Clocks;tma_overlap", "MetricName": "tma_branch_resteers", "ScaleUnit": "100%", - "MetricThreshold": "tma_branch_resteers > 5 & tma_fetch_latency > 10 & tma_frontend_bound > 15", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES." + "MetricThreshold": "tma_branch_resteers > 0.05 & tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_l3_hit_latency, tma_store_latency." }, { "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)", "MetricExpr": "( 2 ) * IDQ.MS_SWITCHES / tma_info_thread_clks", - "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;Clocks_Estimated", + "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;Clocks_Estimated;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO", "MetricName": "tma_ms_switches", "ScaleUnit": "100%", - "MetricThreshold": "tma_ms_switches > 5 & tma_fetch_latency > 10 & tma_frontend_bound > 15", - "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES." + "MetricThreshold": "tma_ms_switches > 0.05 & tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", + "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES. Related metrics: tma_l1_bound, tma_machine_clears, tma_microcode_sequencer." }, { "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)", "MetricExpr": "ILD_STALL.LCP / tma_info_thread_clks", - "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;Clocks", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;Clocks;tma_issueFB", "MetricName": "tma_lcp", "ScaleUnit": "100%", - "MetricThreshold": "tma_lcp > 5 & tma_fetch_latency > 10 & tma_frontend_bound > 15", - "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this." + "MetricThreshold": "tma_lcp > 0.05 & tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", + "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb." }, { "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines", "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / tma_info_thread_clks", - "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;Clocks", + "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;Clocks;tma_issueFB", "MetricName": "tma_dsb_switches", "ScaleUnit": "100%", - "MetricThreshold": "tma_dsb_switches > 5 & tma_fetch_latency > 10 & tma_frontend_bound > 15", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty." + "MetricThreshold": "tma_dsb_switches > 0.05 & tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Related metrics: tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp." }, { "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues", "MetricExpr": "tma_frontend_bound - tma_fetch_latency", - "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;Slots", + "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;Slots;tma_issueFB", "MetricName": "tma_fetch_bandwidth", "ScaleUnit": "100%", - "MetricThreshold": "tma_fetch_bandwidth > 20", - "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend." + "MetricThreshold": "tma_fetch_bandwidth > 0.2", + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Related metrics: tma_dsb_switches, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp." }, { "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)", @@ -85,7 +85,7 @@ "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group;Slots_Estimated", "MetricName": "tma_mite", "ScaleUnit": "100%", - "MetricThreshold": "tma_mite > 10 & tma_fetch_bandwidth > 20", + "MetricThreshold": "tma_mite > 0.1 & tma_fetch_bandwidth > 0.2", "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck." }, { @@ -94,7 +94,7 @@ "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group;Slots_Estimated", "MetricName": "tma_dsb", "ScaleUnit": "100%", - "MetricThreshold": "tma_dsb > 15 & tma_fetch_bandwidth > 20", + "MetricThreshold": "tma_dsb > 0.15 & tma_fetch_bandwidth > 0.2", "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here." }, { @@ -103,26 +103,26 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group;Slots", "MetricName": "tma_bad_speculation", "ScaleUnit": "100%", - "MetricThreshold": "tma_bad_speculation > 15", + "MetricThreshold": "tma_bad_speculation > 0.15", "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example." }, { "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction", "MetricExpr": "( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * tma_bad_speculation", - "MetricGroup": "BadSpec;BrMispredicts;BvMP;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;Slots", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;Slots;tma_issueBM", "MetricName": "tma_branch_mispredicts", "ScaleUnit": "100%", - "MetricThreshold": "tma_branch_mispredicts > 10 & tma_bad_speculation > 15", + "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES." }, { "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears", "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", - "MetricGroup": "BadSpec;BvMS;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;Slots", + "MetricGroup": "BadSpec;BvMS;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;Slots;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "ScaleUnit": "100%", - "MetricThreshold": "tma_machine_clears > 10 & tma_bad_speculation > 15", - "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT." + "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches." }, { "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", @@ -130,7 +130,7 @@ "MetricGroup": "BvOB;TmaL1;TopdownL1;tma_L1_group;Slots", "MetricName": "tma_backend_bound", "ScaleUnit": "100%", - "MetricThreshold": "tma_backend_bound > 20", + "MetricThreshold": "tma_backend_bound > 0.2", "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound." }, { @@ -139,26 +139,26 @@ "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group;Slots", "MetricName": "tma_memory_bound", "ScaleUnit": "100%", - "MetricThreshold": "tma_memory_bound > 20 & tma_backend_bound > 20", + "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two)." }, { "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 Data (L1D) cache", "MetricExpr": "max( ( ( min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.STALLS_LDM_PENDING ) ) - CYCLE_ACTIVITY.STALLS_L1D_PENDING ) / tma_info_thread_clks , 0 )", - "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group;Stalls", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group;Stalls;tma_issueL1;tma_issueMC", "MetricName": "tma_l1_bound", "ScaleUnit": "100%", - "MetricThreshold": "tma_l1_bound > 10 & tma_memory_bound > 20 & tma_backend_bound > 20", - "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 Data (L1D) cache. The L1D cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1D. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_UOPS_RETIRED.L1_HIT." + "MetricThreshold": "tma_l1_bound > 0.1 & tma_memory_bound > 0.2 & tma_backend_bound > 0.2", + "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 Data (L1D) cache. The L1D cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1D. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_UOPS_RETIRED.L1_HIT. Related metrics: tma_machine_clears, tma_microcode_sequencer, tma_ms_switches, tma_ports_utilized_1." }, { "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", "MetricExpr": "( ( 8 ) * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.WALK_DURATION ) / tma_info_thread_clks", - "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_l1_bound_group;Clocks_Estimated", + "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_l1_bound_group;Clocks_Estimated;tma_issueTLB", "MetricName": "tma_dtlb_load", "ScaleUnit": "100%", - "MetricThreshold": "tma_dtlb_load > 10 & tma_l1_bound > 10 & tma_memory_bound > 20 & tma_backend_bound > 20", - "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS." + "MetricThreshold": "tma_dtlb_load > 0.1 & tma_l1_bound > 0.1 & tma_memory_bound > 0.2 & tma_backend_bound > 0.2", + "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS. Related metrics: tma_dtlb_store." }, { "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores", @@ -166,17 +166,17 @@ "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group;Clocks_Estimated", "MetricName": "tma_store_fwd_blk", "ScaleUnit": "100%", - "MetricThreshold": "tma_store_fwd_blk > 10 & tma_l1_bound > 10 & tma_memory_bound > 20 & tma_backend_bound > 20", + "MetricThreshold": "tma_store_fwd_blk > 0.1 & tma_l1_bound > 0.1 & tma_memory_bound > 0.2 & tma_backend_bound > 0.2", "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading." }, { "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations", "MetricExpr": "( MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) / tma_info_thread_clks", - "MetricGroup": "LockCont;Offcore;TopdownL4;tma_L4_group;tma_l1_bound_group;Clocks", + "MetricGroup": "LockCont;Offcore;TopdownL4;tma_L4_group;tma_l1_bound_group;Clocks;tma_issueRFO", "MetricName": "tma_lock_latency", "ScaleUnit": "100%", - "MetricThreshold": "tma_lock_latency > 20 & tma_l1_bound > 10 & tma_memory_bound > 20 & tma_backend_bound > 20", - "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_UOPS_RETIRED.LOCK_LOADS." + "MetricThreshold": "tma_lock_latency > 0.2 & tma_l1_bound > 0.1 & tma_memory_bound > 0.2 & tma_backend_bound > 0.2", + "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_UOPS_RETIRED.LOCK_LOADS. Related metrics: tma_store_latency." }, { "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary", @@ -184,7 +184,7 @@ "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group;Clocks_Calculated", "MetricName": "tma_split_loads", "ScaleUnit": "100%", - "MetricThreshold": "tma_split_loads > 30", + "MetricThreshold": "tma_split_loads > 0.3", "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_UOPS_RETIRED.SPLIT_LOADS." }, { @@ -193,17 +193,17 @@ "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group;Clocks_Estimated", "MetricName": "tma_4k_aliasing", "ScaleUnit": "100%", - "MetricThreshold": "tma_4k_aliasing > 20 & tma_l1_bound > 10 & tma_memory_bound > 20 & tma_backend_bound > 20", + "MetricThreshold": "tma_4k_aliasing > 0.2 & tma_l1_bound > 0.1 & tma_memory_bound > 0.2 & tma_backend_bound > 0.2", "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound)." }, { "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed", "MetricExpr": "tma_info_memory_load_miss_real_latency * cpu@L1D_PEND_MISS.REQUEST_FB_FULL\\,cmask\\=0x1@ / tma_info_thread_clks", - "MetricGroup": "BvMB;MemoryBW;TopdownL4;tma_L4_group;tma_l1_bound_group;Clocks_Calculated", + "MetricGroup": "BvMB;MemoryBW;TopdownL4;tma_L4_group;tma_l1_bound_group;Clocks_Calculated;tma_issueBW;tma_issueSL;tma_issueSmSt", "MetricName": "tma_fb_full", "ScaleUnit": "100%", - "MetricThreshold": "tma_fb_full > 30", - "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory)." + "MetricThreshold": "tma_fb_full > 0.3", + "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store_latency." }, { "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads", @@ -211,7 +211,7 @@ "MetricGroup": "BvML;CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group;Stalls", "MetricName": "tma_l2_bound", "ScaleUnit": "100%", - "MetricThreshold": "tma_l2_bound > 5 & tma_memory_bound > 20 & tma_backend_bound > 20", + "MetricThreshold": "tma_l2_bound > 0.05 & tma_memory_bound > 0.2 & tma_backend_bound > 0.2", "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L2_HIT." }, { @@ -220,43 +220,44 @@ "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group;Stalls", "MetricName": "tma_l3_bound", "ScaleUnit": "100%", - "MetricThreshold": "tma_l3_bound > 5 & tma_memory_bound > 20 & tma_backend_bound > 20", + "MetricThreshold": "tma_l3_bound > 0.05 & tma_memory_bound > 0.2 & tma_backend_bound > 0.2", "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT." }, { "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses", "MetricExpr": "( ( 60 ) * ( MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / ( ( MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS ) + MEM_LOAD_UOPS_RETIRED.L3_MISS ) ) ) + ( 43 ) * ( MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / ( ( MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS ) + MEM_LOAD_UOPS_RETIRED.L3_MISS ) ) ) ) / tma_info_thread_clks", - "MetricGroup": "BvMS;DataSharing;LockCont;Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group;Clocks_Estimated", + "MetricGroup": "BvMS;DataSharing;LockCont;Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group;Clocks_Estimated;tma_issueSyncxn", "MetricName": "tma_contested_accesses", "ScaleUnit": "100%", - "MetricThreshold": "tma_contested_accesses > 5 & tma_l3_bound > 5 & tma_memory_bound > 20 & tma_backend_bound > 20", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM, MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS." + "MetricThreshold": "tma_contested_accesses > 0.05 & tma_l3_bound > 0.05 & tma_memory_bound > 0.2 & tma_backend_bound > 0.2", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM, MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears." }, { "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses", "MetricExpr": "( 43 ) * ( MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / ( ( MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS ) + MEM_LOAD_UOPS_RETIRED.L3_MISS ) ) ) / tma_info_thread_clks", - "MetricGroup": "BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group;Clocks_Estimated", + "MetricGroup": "BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group;Clocks_Estimated;tma_issueSyncxn", "MetricName": "tma_data_sharing", "ScaleUnit": "100%", - "MetricThreshold": "tma_data_sharing > 5 & tma_l3_bound > 5 & tma_memory_bound > 20 & tma_backend_bound > 20", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT." + "MetricThreshold": "tma_data_sharing > 0.05 & tma_l3_bound > 0.05 & tma_memory_bound > 0.2 & tma_backend_bound > 0.2", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears." }, { "BriefDescription": "This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)", "MetricExpr": "( 29 ) * ( MEM_LOAD_UOPS_RETIRED.L3_HIT * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / ( ( MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS ) + MEM_LOAD_UOPS_RETIRED.L3_MISS ) ) ) / tma_info_thread_clks", - "MetricGroup": "BvML;MemoryLat;TopdownL4;tma_L4_group;tma_l3_bound_group;Clocks_Estimated", + "MetricGroup": "BvML;MemoryLat;TopdownL4;tma_L4_group;tma_l3_bound_group;Clocks_Estimated;tma_issueLat;tma_overlap", "MetricName": "tma_l3_hit_latency", "ScaleUnit": "100%", - "MetricThreshold": "tma_l3_hit_latency > 10 & tma_l3_bound > 5 & tma_memory_bound > 20 & tma_backend_bound > 20", - "PublicDescription": "This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT." + "MetricThreshold": "tma_l3_hit_latency > 0.1 & tma_l3_bound > 0.05 & tma_memory_bound > 0.2 & tma_backend_bound > 0.2", + "PublicDescription": "This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT. Related metrics: tma_branch_resteers, tma_mem_latency, tma_store_latency." }, { "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)", "MetricExpr": "( ( OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 ) if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL ) / tma_info_core_core_clks", - "MetricGroup": "BvMB;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_l3_bound_group;Clocks", + "MetricGroup": "BvMB;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_l3_bound_group;Clocks;tma_issueBW", "MetricName": "tma_sq_full", "ScaleUnit": "100%", - "MetricThreshold": "tma_sq_full > 30 & tma_l3_bound > 5 & tma_memory_bound > 20 & tma_backend_bound > 20" + "MetricThreshold": "tma_sq_full > 0.3 & tma_l3_bound > 0.05 & tma_memory_bound > 0.2 & tma_backend_bound > 0.2", + "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_fb_full, tma_info_system_dram_bw_use, tma_mem_bandwidth." }, { "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", @@ -264,26 +265,26 @@ "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group;Stalls", "MetricName": "tma_dram_bound", "ScaleUnit": "100%", - "MetricThreshold": "tma_dram_bound > 10 & tma_memory_bound > 20 & tma_backend_bound > 20", + "MetricThreshold": "tma_dram_bound > 0.1 & tma_memory_bound > 0.2 & tma_backend_bound > 0.2", "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS." }, { "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM)", "MetricExpr": "( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x6@ ) ) / tma_info_thread_clks", - "MetricGroup": "BvMB;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;Clocks", + "MetricGroup": "BvMB;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;Clocks;tma_issueBW", "MetricName": "tma_mem_bandwidth", "ScaleUnit": "100%", - "MetricThreshold": "tma_mem_bandwidth > 20 & tma_dram_bound > 10 & tma_memory_bound > 20 & tma_backend_bound > 20", - "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that)." + "MetricThreshold": "tma_mem_bandwidth > 0.2 & tma_dram_bound > 0.1 & tma_memory_bound > 0.2 & tma_backend_bound > 0.2", + "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_fb_full, tma_info_system_dram_bw_use, tma_sq_full." }, { "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM)", "MetricExpr": "( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / tma_info_thread_clks - tma_mem_bandwidth", - "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;Clocks", + "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;Clocks;tma_issueLat", "MetricName": "tma_mem_latency", "ScaleUnit": "100%", - "MetricThreshold": "tma_mem_latency > 10 & tma_dram_bound > 10 & tma_memory_bound > 20 & tma_backend_bound > 20", - "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that)." + "MetricThreshold": "tma_mem_latency > 0.1 & tma_dram_bound > 0.1 & tma_memory_bound > 0.2 & tma_backend_bound > 0.2", + "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that). Related metrics: tma_l3_hit_latency." }, { "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write", @@ -291,44 +292,44 @@ "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group;Stalls", "MetricName": "tma_store_bound", "ScaleUnit": "100%", - "MetricThreshold": "tma_store_bound > 20 & tma_memory_bound > 20 & tma_backend_bound > 20", + "MetricThreshold": "tma_store_bound > 0.2 & tma_memory_bound > 0.2 & tma_backend_bound > 0.2", "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_UOPS_RETIRED.ALL_STORES." }, { "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses", "MetricExpr": "( ( L2_RQSTS.RFO_HIT * ( 9 ) * ( 1 - ( MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / tma_info_thread_clks", - "MetricGroup": "BvML;LockCont;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group;Clocks_Estimated", + "MetricGroup": "BvML;LockCont;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group;Clocks_Estimated;tma_issueRFO;tma_issueSL;tma_overlap", "MetricName": "tma_store_latency", "ScaleUnit": "100%", - "MetricThreshold": "tma_store_latency > 10 & tma_store_bound > 20 & tma_memory_bound > 20 & tma_backend_bound > 20", - "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)." + "MetricThreshold": "tma_store_latency > 0.1 & tma_store_bound > 0.2 & tma_memory_bound > 0.2 & tma_backend_bound > 0.2", + "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_branch_resteers, tma_fb_full, tma_l3_hit_latency, tma_lock_latency." }, { "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing", "MetricExpr": "( 60 ) * OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE / tma_info_thread_clks", - "MetricGroup": "BvMS;DataSharing;LockCont;Offcore;Snoop;TopdownL4;tma_L4_group;tma_store_bound_group;Clocks_Estimated", + "MetricGroup": "BvMS;DataSharing;LockCont;Offcore;Snoop;TopdownL4;tma_L4_group;tma_store_bound_group;Clocks_Estimated;tma_issueSyncxn", "MetricName": "tma_false_sharing", "ScaleUnit": "100%", - "MetricThreshold": "tma_false_sharing > 5 & tma_store_bound > 20 & tma_memory_bound > 20 & tma_backend_bound > 20", - "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM, OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE." + "MetricThreshold": "tma_false_sharing > 0.05 & tma_store_bound > 0.2 & tma_memory_bound > 0.2 & tma_backend_bound > 0.2", + "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM, OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears." }, { "BriefDescription": "This metric represents rate of split store accesses", "MetricExpr": "2 * MEM_UOPS_RETIRED.SPLIT_STORES / tma_info_core_core_clks", - "MetricGroup": "TopdownL4;tma_L4_group;tma_store_bound_group;Core_Utilization", + "MetricGroup": "TopdownL4;tma_L4_group;tma_store_bound_group;Core_Utilization;tma_issueSpSt", "MetricName": "tma_split_stores", "ScaleUnit": "100%", - "MetricThreshold": "tma_split_stores > 20 & tma_store_bound > 20 & tma_memory_bound > 20 & tma_backend_bound > 20", - "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_UOPS_RETIRED.SPLIT_STORES." + "MetricThreshold": "tma_split_stores > 0.2 & tma_store_bound > 0.2 & tma_memory_bound > 0.2 & tma_backend_bound > 0.2", + "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_UOPS_RETIRED.SPLIT_STORES. Related metrics: tma_port_4." }, { "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses", "MetricExpr": "( ( 8 ) * DTLB_STORE_MISSES.STLB_HIT + DTLB_STORE_MISSES.WALK_DURATION ) / tma_info_thread_clks", - "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_store_bound_group;Clocks_Estimated", + "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_store_bound_group;Clocks_Estimated;tma_issueTLB", "MetricName": "tma_dtlb_store", "ScaleUnit": "100%", - "MetricThreshold": "tma_dtlb_store > 5 & tma_store_bound > 20 & tma_memory_bound > 20 & tma_backend_bound > 20", - "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_UOPS_RETIRED.STLB_MISS_STORES." + "MetricThreshold": "tma_dtlb_store > 0.05 & tma_store_bound > 0.2 & tma_memory_bound > 0.2 & tma_backend_bound > 0.2", + "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_UOPS_RETIRED.STLB_MISS_STORES. Related metrics: tma_dtlb_load." }, { "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck", @@ -336,7 +337,7 @@ "MetricGroup": "Backend;TmaL2;Compute;TopdownL2;tma_L2_group;tma_backend_bound_group;Slots", "MetricName": "tma_core_bound", "ScaleUnit": "100%", - "MetricThreshold": "tma_core_bound > 10 & tma_backend_bound > 20", + "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2", "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations)." }, { @@ -345,7 +346,7 @@ "MetricGroup": "BvCB;TopdownL3;tma_L3_group;tma_core_bound_group;Clocks", "MetricName": "tma_divider", "ScaleUnit": "100%", - "MetricThreshold": "tma_divider > 20 & tma_core_bound > 10 & tma_backend_bound > 20", + "MetricThreshold": "tma_divider > 0.2 & tma_core_bound > 0.1 & tma_backend_bound > 0.2", "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_UOPS." }, { @@ -354,7 +355,7 @@ "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group;Clocks", "MetricName": "tma_ports_utilization", "ScaleUnit": "100%", - "MetricThreshold": "tma_ports_utilization > 15 & tma_core_bound > 10 & tma_backend_bound > 20", + "MetricThreshold": "tma_ports_utilization > 0.15 & tma_core_bound > 0.1 & tma_backend_bound > 0.2", "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations." }, { @@ -363,26 +364,26 @@ "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group;Clocks", "MetricName": "tma_ports_utilized_0", "ScaleUnit": "100%", - "MetricThreshold": "tma_ports_utilized_0 > 20 & tma_ports_utilization > 15 & tma_core_bound > 10 & tma_backend_bound > 20", + "MetricThreshold": "tma_ports_utilized_0 > 0.2 & tma_ports_utilization > 0.15 & tma_core_bound > 0.1 & tma_backend_bound > 0.2", "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric." }, { "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", "MetricExpr": "( ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ ) / 2 if #SMT_on else ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ ) ) / tma_info_core_core_clks", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group;Clocks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group;Clocks;tma_issueL1", "MetricName": "tma_ports_utilized_1", "ScaleUnit": "100%", - "MetricThreshold": "tma_ports_utilized_1 > 20 & tma_ports_utilization > 15 & tma_core_bound > 10 & tma_backend_bound > 20", - "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful." + "MetricThreshold": "tma_ports_utilized_1 > 0.2 & tma_ports_utilization > 0.15 & tma_core_bound > 0.1 & tma_backend_bound > 0.2", + "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Related metrics: tma_l1_bound." }, { "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", "MetricExpr": "( ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ ) / 2 if #SMT_on else ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ ) ) / tma_info_core_core_clks", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group;Clocks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group;Clocks;tma_issue2P", "MetricName": "tma_ports_utilized_2", "ScaleUnit": "100%", - "MetricThreshold": "tma_ports_utilized_2 > 15 & tma_ports_utilization > 15 & tma_core_bound > 10 & tma_backend_bound > 20", - "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop." + "MetricThreshold": "tma_ports_utilized_2 > 0.15 & tma_ports_utilization > 0.15 & tma_core_bound > 0.1 & tma_backend_bound > 0.2", + "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Related metrics: tma_port_0, tma_port_1, tma_port_5, tma_port_6." }, { "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", @@ -390,7 +391,7 @@ "MetricGroup": "BvCB;PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group;Clocks", "MetricName": "tma_ports_utilized_3m", "ScaleUnit": "100%", - "MetricThreshold": "tma_ports_utilized_3m > 40 & tma_ports_utilization > 15 & tma_core_bound > 10 & tma_backend_bound > 20" + "MetricThreshold": "tma_ports_utilized_3m > 0.4 & tma_ports_utilization > 0.15 & tma_core_bound > 0.1 & tma_backend_bound > 0.2" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations", @@ -398,43 +399,43 @@ "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group;Core_Execution", "MetricName": "tma_alu_op_utilization", "ScaleUnit": "100%", - "MetricThreshold": "tma_alu_op_utilization > 40" + "MetricThreshold": "tma_alu_op_utilization > 0.4" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)", "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / tma_info_core_core_clks", - "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group;Core_Clocks", + "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group;Core_Clocks;tma_issue2P", "MetricName": "tma_port_0", "ScaleUnit": "100%", - "MetricThreshold": "tma_port_0 > 60", - "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch). Sample with: UOPS_DISPATCHED_PORT.PORT_0." + "MetricThreshold": "tma_port_0 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch). Sample with: UOPS_DISPATCHED_PORT.PORT_0. Related metrics: tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2." }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)", "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / tma_info_core_core_clks", - "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;Core_Clocks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;Core_Clocks;tma_issue2P", "MetricName": "tma_port_1", "ScaleUnit": "100%", - "MetricThreshold": "tma_port_1 > 60", - "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU). Sample with: UOPS_DISPATCHED_PORT.PORT_1." + "MetricThreshold": "tma_port_1 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU). Sample with: UOPS_DISPATCHED_PORT.PORT_1. Related metrics: tma_port_0, tma_port_5, tma_port_6, tma_ports_utilized_2." }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU)", "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / tma_info_core_core_clks", - "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;Core_Clocks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;Core_Clocks;tma_issue2P", "MetricName": "tma_port_5", "ScaleUnit": "100%", - "MetricThreshold": "tma_port_5 > 60", - "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU). Sample with: UOPS_DISPATCHED_PORT.PORT_5." + "MetricThreshold": "tma_port_5 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU). Sample with: UOPS_DISPATCHED_PORT.PORT_5. Related metrics: tma_port_0, tma_port_1, tma_port_6, tma_ports_utilized_2." }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU)", "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_6 / tma_info_core_core_clks", - "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;Core_Clocks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;Core_Clocks;tma_issue2P", "MetricName": "tma_port_6", "ScaleUnit": "100%", - "MetricThreshold": "tma_port_6 > 60", - "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU). Sample with: UOPS_DISPATCHED_PORT.PORT_1." + "MetricThreshold": "tma_port_6 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU). Sample with: UOPS_DISPATCHED_PORT.PORT_1. Related metrics: tma_port_0, tma_port_1, tma_port_5, tma_ports_utilized_2." }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations", @@ -442,7 +443,7 @@ "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group;Core_Execution", "MetricName": "tma_load_op_utilization", "ScaleUnit": "100%", - "MetricThreshold": "tma_load_op_utilization > 60" + "MetricThreshold": "tma_load_op_utilization > 0.6" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads)", @@ -450,7 +451,7 @@ "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group;Core_Clocks", "MetricName": "tma_port_2", "ScaleUnit": "100%", - "MetricThreshold": "tma_port_2 > 60", + "MetricThreshold": "tma_port_2 > 0.6", "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads). Sample with: UOPS_DISPATCHED_PORT.PORT_2." }, { @@ -459,7 +460,7 @@ "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group;Core_Clocks", "MetricName": "tma_port_3", "ScaleUnit": "100%", - "MetricThreshold": "tma_port_3 > 60", + "MetricThreshold": "tma_port_3 > 0.6", "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads). Sample with: UOPS_DISPATCHED_PORT.PORT_3." }, { @@ -468,16 +469,16 @@ "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group;Core_Execution", "MetricName": "tma_store_op_utilization", "ScaleUnit": "100%", - "MetricThreshold": "tma_store_op_utilization > 60" + "MetricThreshold": "tma_store_op_utilization > 0.6" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data)", "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / tma_info_core_core_clks", - "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group;Core_Clocks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group;Core_Clocks;tma_issueSpSt", "MetricName": "tma_port_4", "ScaleUnit": "100%", - "MetricThreshold": "tma_port_4 > 60", - "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data). Sample with: UOPS_DISPATCHED_PORT.PORT_4." + "MetricThreshold": "tma_port_4 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data). Sample with: UOPS_DISPATCHED_PORT.PORT_4. Related metrics: tma_split_stores." }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address)", @@ -485,7 +486,7 @@ "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group;Core_Clocks", "MetricName": "tma_port_7", "ScaleUnit": "100%", - "MetricThreshold": "tma_port_7 > 60", + "MetricThreshold": "tma_port_7 > 0.6", "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address). Sample with: UOPS_DISPATCHED_PORT.PORT_7." }, { @@ -494,7 +495,7 @@ "MetricGroup": "BvUW;TmaL1;TopdownL1;tma_L1_group;Slots", "MetricName": "tma_retiring", "ScaleUnit": "100%", - "MetricThreshold": "tma_retiring > 70 | tma_heavy_operations > 10", + "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1", "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS." }, { @@ -503,7 +504,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group;Slots", "MetricName": "tma_light_operations", "ScaleUnit": "100%", - "MetricThreshold": "tma_light_operations > 60", + "MetricThreshold": "tma_light_operations > 0.6", "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations , instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized code running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. ([ICL+] Note this may undercount due to approximation using indirect events; [ADL+] .). Sample with: INST_RETIRED.PREC_DIST." }, { @@ -512,17 +513,17 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group;Slots", "MetricName": "tma_heavy_operations", "ScaleUnit": "100%", - "MetricThreshold": "tma_heavy_operations > 10", + "MetricThreshold": "tma_heavy_operations > 0.1", "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations , instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.([ICL+] Note this may overcount due to approximation using indirect events; [ADL+])." }, { "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", "MetricExpr": "( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / tma_info_thread_slots", - "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;Slots", + "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;Slots;tma_issueMC;tma_issueMS", "MetricName": "tma_microcode_sequencer", "ScaleUnit": "100%", - "MetricThreshold": "tma_microcode_sequencer > 5 & tma_heavy_operations > 10", - "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS." + "MetricThreshold": "tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS. Related metrics: tma_l1_bound, tma_machine_clears, tma_ms_switches." }, { "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists", @@ -530,7 +531,7 @@ "MetricGroup": "BvIO;TopdownL4;tma_L4_group;tma_microcode_sequencer_group;Slots_Estimated", "MetricName": "tma_assists", "ScaleUnit": "100%", - "MetricThreshold": "tma_assists > 10 & tma_microcode_sequencer > 5 & tma_heavy_operations > 10", + "MetricThreshold": "tma_assists > 0.1 & tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1", "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.ANY_WB_ASSIST." }, { @@ -539,7 +540,7 @@ "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group;Slots", "MetricName": "tma_cisc", "ScaleUnit": "100%", - "MetricThreshold": "tma_cisc > 10 & tma_microcode_sequencer > 5 & tma_heavy_operations > 10", + "MetricThreshold": "tma_cisc > 0.1 & tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1", "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources." }, { @@ -630,9 +631,10 @@ { "BriefDescription": "Instructions per taken branch", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;Inst_Metric", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;Inst_Metric;tma_issueFB", "MetricName": "tma_info_inst_mix_iptb", - "MetricThreshold": "tma_info_inst_mix_iptb < 4 * 2 + 1" + "MetricThreshold": "tma_info_inst_mix_iptb < 4 * 2 + 1", + "PublicDescription": "Instructions per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, tma_lcp." }, { "BriefDescription": "Branch instructions per taken branch", @@ -656,9 +658,10 @@ { "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", "MetricExpr": "IDQ.DSB_UOPS / ( ( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )", - "MetricGroup": "DSB;Fed;FetchBW;Metric", + "MetricGroup": "DSB;Fed;FetchBW;Metric;tma_issueFB", "MetricName": "tma_info_frontend_dsb_coverage", - "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & ipc / 4 > 0.35" + "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 4 > 0.35", + "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_inst_mix_iptb, tma_lcp." }, { "BriefDescription": "Taken Branches retired Per Cycle", @@ -746,7 +749,7 @@ "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / tma_info_core_core_clks", "MetricGroup": "Mem;MemoryTLB;Core_Metric", "MetricName": "tma_info_memory_tlb_page_walks_utilization", - "MetricThreshold": "tma_info_memory_page_walks_utilization > 0.5" + "MetricThreshold": "tma_info_memory_tlb_page_walks_utilization > 0.5" }, { "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", @@ -831,8 +834,9 @@ { "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", "MetricExpr": "64 * ( UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL ) / ( 1000000 ) / tma_info_system_time / 1000", - "MetricGroup": "HPC;MemOffcore;MemoryBW;SoC;GB/sec", - "MetricName": "tma_info_system_dram_bw_use" + "MetricGroup": "HPC;MemOffcore;MemoryBW;SoC;GB/sec;tma_issueBW", + "MetricName": "tma_info_system_dram_bw_use", + "PublicDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_fb_full, tma_mem_bandwidth, tma_sq_full." }, { "BriefDescription": "Total package Power in Watts", diff --git a/HSX/metrics/haswellx_metrics.json b/HSX/metrics/haswellx_metrics.json index db2bce1a..34e73273 100644 --- a/HSX/metrics/haswellx_metrics.json +++ b/HSX/metrics/haswellx_metrics.json @@ -2,7 +2,7 @@ "Header": { "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.", "Info": "Performance Monitoring Metrics for Intel(R) Xeon(R) processor E5 v3 family based on the Haswell-E microarchitecture0", - "DatePublished": "11/05/2024", + "DatePublished": "12/02/2024", "Version": "1.0", "Legend": "", "TmaVersion": "5.01", @@ -5249,11 +5249,11 @@ }, { "Alias": "b", - "Value": "IPC" + "Value": "metric_TMA_Info_Thread_IPC" } ], "Formula": "a < 0.7 & b / 4 > 0.35", - "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & IPC / 4 > 0.35", + "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & metric_TMA_Info_Thread_IPC / 4 > 0.35", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", @@ -5723,11 +5723,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Memory_Page_Walks_Utilization" + "Value": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization" } ], "Formula": "a > 0.5", - "BaseFormula": "metric_TMA_Info_Memory_Page_Walks_Utilization > 0.5", + "BaseFormula": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization > 0.5", "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", @@ -6345,7 +6345,15 @@ "Category": "TMA", "CountDomain": "Seconds", "Threshold": { - "Formula": "metric_TMA_Info_System_Time < 1" + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_System_Time" + } + ], + "Formula": "a < 1", + "BaseFormula": "metric_TMA_Info_System_Time < 1", + "ThresholdIssues": "" }, "ResolutionLevels": "SOCKET, SYSTEM", "MetricGroup": "Summary", diff --git a/HSX/metrics/perf/haswellx_metrics_perf.json b/HSX/metrics/perf/haswellx_metrics_perf.json index e1e4c1ad..f84851c6 100644 --- a/HSX/metrics/perf/haswellx_metrics_perf.json +++ b/HSX/metrics/perf/haswellx_metrics_perf.json @@ -929,7 +929,7 @@ "MetricExpr": "IDQ.DSB_UOPS / ( ( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )", "MetricGroup": "DSB;Fed;FetchBW;Metric;tma_issueFB", "MetricName": "tma_info_frontend_dsb_coverage", - "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & ipc / 4 > 0.35", + "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 4 > 0.35", "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1018,7 +1018,7 @@ "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / tma_info_core_core_clks", "MetricGroup": "Mem;MemoryTLB;Core_Metric", "MetricName": "tma_info_memory_tlb_page_walks_utilization", - "MetricThreshold": "tma_info_memory_page_walks_utilization > 0.5" + "MetricThreshold": "tma_info_memory_tlb_page_walks_utilization > 0.5" }, { "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", diff --git a/ICL/metrics/icelake_metrics.json b/ICL/metrics/icelake_metrics.json index e5980af7..cd2e867e 100644 --- a/ICL/metrics/icelake_metrics.json +++ b/ICL/metrics/icelake_metrics.json @@ -2,7 +2,7 @@ "Header": { "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.", "Info": "Performance Monitoring Metrics for 10th Generation Intel(R) Core(TM) Processor0", - "DatePublished": "11/15/2024", + "DatePublished": "12/02/2024", "Version": "1.0", "Legend": "", "TmaVersion": "5.01", @@ -344,7 +344,7 @@ } ], "Formula": "100 * ( ( a / ( a + b + c + d ) - e / ( f ) ) - ( 1 - ( 10 * ( ( g / h ) * i / ( f ) ) * ( max( ( ( j / ( j + k ) ) * ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) + ( ( 5 ) * l ) / ( f ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * ( 1 - j / ( l - k ) ) , 0.0001 ) ) / ( ( j / ( j + k ) ) * ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) + ( ( 5 ) * l ) / ( f ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) ) ) * ( ( ( 5 ) * m - e ) / ( f ) ) * ( ( j / ( j + k ) ) * n / ( o ) ) / ( ( p / ( o ) ) + ( q / ( o ) ) + ( n / ( o ) + ( 10 ) * r / ( o ) ) + ( ( 3 ) * s / ( o ) ) + ( t / ( o ) ) + ( u / ( o ) ) ) - ( ( ( ( ( g / h ) * i / ( f ) ) / ( ( ( ( ( g / h ) * i / ( f ) ) + ( c / ( a + b + c + d ) ) * ( v - w ) / x ) - ( ( g / h ) * i / ( f ) ) ) + ( ( g / h ) * i / ( f ) ) ) ) * ( ( ( 34 ) * y / ( f ) ) / ( ( g / h ) * i / ( f ) ) ) ) * ( ( ( ( 5 ) * m - e ) / ( f ) ) * ( ( ( 3 ) * s / ( o ) ) + ( n / ( o ) + ( 10 ) * r / ( o ) ) * ( ( ( 1 - ( j / ( j + k ) ) ) * n / ( o ) ) + ( 10 * ( ( g / h ) * i / ( f ) ) * ( max( ( ( j / ( j + k ) ) * ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) + ( ( 5 ) * l ) / ( f ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * ( 1 - j / ( l - k ) ) , 0.0001 ) ) / ( ( j / ( j + k ) ) * ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) + ( ( 5 ) * l ) / ( f ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) ) * ( ( j / ( j + k ) ) * n / ( o ) ) ) / ( ( ( j / ( j + k ) ) * n / ( o ) ) + ( ( 1 - ( j / ( j + k ) ) ) * n / ( o ) ) + ( ( 10 ) * r / ( o ) ) ) ) / ( ( p / ( o ) ) + ( q / ( o ) ) + ( n / ( o ) + ( 10 ) * r / ( o ) ) + ( ( 3 ) * s / ( o ) ) + ( t / ( o ) ) + ( u / ( o ) ) ) + ( max( 0 , ( a / ( a + b + c + d ) - e / ( f ) ) - ( ( ( 5 ) * m - e ) / ( f ) ) ) ) * ( z / ( a_a if smt_on else ( o ) ) / 2 ) / ( ( ( a_b - a_c ) / ( a_a if smt_on else ( o ) ) / 2 ) + ( ( a_d - a_e ) / ( a_a if smt_on else ( o ) ) / 2 ) + ( ( a_f - a_g ) / ( a_a if smt_on else ( o ) ) / 2 ) + ( z / ( a_a if smt_on else ( o ) ) / 2 ) ) ) ) ) - ( 100 * ( ( ( 5 ) * m - e ) / ( f ) ) * ( ( q / ( o ) ) + ( p / ( o ) ) + ( ( 10 ) * r / ( o ) ) ) / ( ( p / ( o ) ) + ( q / ( o ) ) + ( n / ( o ) + ( 10 ) * r / ( o ) ) + ( ( 3 ) * s / ( o ) ) + ( t / ( o ) ) + ( u / ( o ) ) ) )", - "BaseFormula": " 100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( ( tma_microcode_sequencer / ( tma_few_uops_instructions + tma_microcode_sequencer ) ) * ( tma_assists / tma_microcode_sequencer ) ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) * tma_mispredicts_resteers ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) ) ) - tma_big_code", + "BaseFormula": " 100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( ( tma_microcode_sequencer / ( tma_few_uops_instructions + tma_microcode_sequencer ) ) * ( tma_assists / tma_microcode_sequencer ) ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) * tma_mispredicts_resteers ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) ) ) - tma_bottleneck_big_code", "Category": "TMA", "CountDomain": "Scaled_Slots", "Threshold": { @@ -1918,7 +1918,7 @@ } ], "Formula": "100 - ( ( 100 * ( ( ( 5 ) * a - b ) / ( c ) ) * ( ( d / ( e ) ) + ( f / ( e ) ) + ( ( 10 ) * g / ( e ) ) ) / ( ( f / ( e ) ) + ( d / ( e ) ) + ( h / ( e ) + ( 10 ) * g / ( e ) ) + ( ( 3 ) * i / ( e ) ) + ( j / ( e ) ) + ( k / ( e ) ) ) ) + ( 100 * ( ( l / ( l + m + n + o ) - b / ( c ) ) - ( 1 - ( 10 * ( ( p / q ) * r / ( c ) ) * ( max( ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) * ( 1 - s / ( u - t ) ) , 0.0001 ) ) / ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( ( ( 5 ) * a - b ) / ( c ) ) * ( ( s / ( s + t ) ) * h / ( e ) ) / ( ( f / ( e ) ) + ( d / ( e ) ) + ( h / ( e ) + ( 10 ) * g / ( e ) ) + ( ( 3 ) * i / ( e ) ) + ( j / ( e ) ) + ( k / ( e ) ) ) - ( ( ( ( ( p / q ) * r / ( c ) ) / ( ( ( ( ( p / q ) * r / ( c ) ) + ( n / ( l + m + n + o ) ) * ( v - w ) / x ) - ( ( p / q ) * r / ( c ) ) ) + ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( 34 ) * y / ( c ) ) / ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( ( 5 ) * a - b ) / ( c ) ) * ( ( ( 3 ) * i / ( e ) ) + ( h / ( e ) + ( 10 ) * g / ( e ) ) * ( ( ( 1 - ( s / ( s + t ) ) ) * h / ( e ) ) + ( 10 * ( ( p / q ) * r / ( c ) ) * ( max( ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) * ( 1 - s / ( u - t ) ) , 0.0001 ) ) / ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) * ( ( s / ( s + t ) ) * h / ( e ) ) ) / ( ( ( s / ( s + t ) ) * h / ( e ) ) + ( ( 1 - ( s / ( s + t ) ) ) * h / ( e ) ) + ( ( 10 ) * g / ( e ) ) ) ) / ( ( f / ( e ) ) + ( d / ( e ) ) + ( h / ( e ) + ( 10 ) * g / ( e ) ) + ( ( 3 ) * i / ( e ) ) + ( j / ( e ) ) + ( k / ( e ) ) ) + ( max( 0 , ( l / ( l + m + n + o ) - b / ( c ) ) - ( ( ( 5 ) * a - b ) / ( c ) ) ) ) * ( z / ( a_a if smt_on else ( e ) ) / 2 ) / ( ( ( a_b - a_c ) / ( a_a if smt_on else ( e ) ) / 2 ) + ( ( a_d - a_e ) / ( a_a if smt_on else ( e ) ) / 2 ) + ( ( a_f - a_g ) / ( a_a if smt_on else ( e ) ) / 2 ) + ( z / ( a_a if smt_on else ( e ) ) / 2 ) ) ) ) ) - ( 100 * ( ( ( 5 ) * a - b ) / ( c ) ) * ( ( d / ( e ) ) + ( f / ( e ) ) + ( ( 10 ) * g / ( e ) ) ) / ( ( f / ( e ) ) + ( d / ( e ) ) + ( h / ( e ) + ( 10 ) * g / ( e ) ) + ( ( 3 ) * i / ( e ) ) + ( j / ( e ) ) + ( k / ( e ) ) ) ) ) + ( 100 * ( 1 - ( 10 * ( ( p / q ) * r / ( c ) ) * ( max( ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) * ( 1 - s / ( u - t ) ) , 0.0001 ) ) / ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) + ( ( ( 5 ) * a - b ) / ( c ) ) * ( ( s / ( s + t ) ) * h / ( e ) ) / ( ( f / ( e ) ) + ( d / ( e ) ) + ( h / ( e ) + ( 10 ) * g / ( e ) ) + ( ( 3 ) * i / ( e ) ) + ( j / ( e ) ) + ( k / ( e ) ) ) ) ) + ( 100 * ( ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) * ( ( ( min( e , a_t ) ) / ( e ) ) / ( ( ( min( e , a_t ) ) / ( e ) ) + ( ( min( e , a_u ) ) / ( e ) - ( ( min( e , a_t ) ) / ( e ) ) ) ) ) ) + ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( ( a_o - a_m ) / ( e ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) * ( ( a_v / ( e ) ) / ( ( ( ( ( 32.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_z ) + ( ( 27 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_a ) ) * ( 1 + ( a_q / a_r ) / 2 ) / ( e ) ) + ( ( ( 27 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_b ) * ( 1 + ( a_q / a_r ) / 2 ) / ( e ) ) + ( ( ( 12.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_c * ( 1 + ( a_q / a_r ) / 2 ) ) / ( e ) ) + ( a_v / ( e ) ) ) ) ) + ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) * ( ( b_d / ( e ) ) / ( ( min( ( 7 ) * b_e + b_f , max( b_g - b_h , 0 ) ) / ( e ) ) + ( 13 * b_i / ( e ) ) + ( min( 2 * ( b_j - b_k - b_l ) * dependentloadsweight / 100 , max( b_g - b_h , 0 ) ) / ( e ) ) + ( ( 16 * max( 0 , b_n - b_o ) + ( b_n / b_p ) * ( ( 10 ) * b_q + ( min( e , b_r ) ) ) ) / ( e ) ) + ( ( b_s / ( b_l + b_k ) ) * b_t / ( e ) ) + ( b_u / ( e ) ) + ( b_d / ( e ) ) ) ) ) ) ) + ( 100 * ( ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) * ( ( ( min( e , a_u ) ) / ( e ) - ( ( min( e , a_t ) ) / ( e ) ) ) / ( ( ( min( e , a_t ) ) / ( e ) ) + ( ( min( e , a_u ) ) / ( e ) - ( ( min( e , a_t ) ) / ( e ) ) ) ) ) ) + ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( ( a_o - a_m ) / ( e ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) * ( ( ( ( 12.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_c * ( 1 + ( a_q / a_r ) / 2 ) ) / ( e ) ) / ( ( ( ( ( 32.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_z ) + ( ( 27 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_a ) ) * ( 1 + ( a_q / a_r ) / 2 ) / ( e ) ) + ( ( ( 27 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_b ) * ( 1 + ( a_q / a_r ) / 2 ) / ( e ) ) + ( ( ( 12.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_c * ( 1 + ( a_q / a_r ) / 2 ) ) / ( e ) ) + ( a_v / ( e ) ) ) ) ) + ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) + ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) * ( ( min( 2 * ( b_j - b_k - b_l ) * dependentloadsweight / 100 , max( b_g - b_h , 0 ) ) / ( e ) ) / ( ( min( ( 7 ) * b_e + b_f , max( b_g - b_h , 0 ) ) / ( e ) ) + ( 13 * b_i / ( e ) ) + ( min( 2 * ( b_j - b_k - b_l ) * dependentloadsweight / 100 , max( b_g - b_h , 0 ) ) / ( e ) ) + ( ( 16 * max( 0 , b_n - b_o ) + ( b_n / b_p ) * ( ( 10 ) * b_q + ( min( e , b_r ) ) ) ) / ( e ) ) + ( ( b_s / ( b_l + b_k ) ) * b_t / ( e ) ) + ( b_u / ( e ) ) + ( b_d / ( e ) ) ) ) ) + ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) * ( ( ( 16 * max( 0 , b_n - b_o ) + ( b_n / b_p ) * ( ( 10 ) * b_q + ( min( e , b_r ) ) ) ) / ( e ) ) / ( ( min( ( 7 ) * b_e + b_f , max( b_g - b_h , 0 ) ) / ( e ) ) + ( 13 * b_i / ( e ) ) + ( min( 2 * ( b_j - b_k - b_l ) * dependentloadsweight / 100 , max( b_g - b_h , 0 ) ) / ( e ) ) + ( ( 16 * max( 0 , b_n - b_o ) + ( b_n / b_p ) * ( ( 10 ) * b_q + ( min( e , b_r ) ) ) ) / ( e ) ) + ( ( b_s / ( b_l + b_k ) ) * b_t / ( e ) ) + ( b_u / ( e ) ) + ( b_d / ( e ) ) ) ) ) + ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) * ( ( ( b_s / ( b_l + b_k ) ) * b_t / ( e ) ) / ( ( min( ( 7 ) * b_e + b_f , max( b_g - b_h , 0 ) ) / ( e ) ) + ( 13 * b_i / ( e ) ) + ( min( 2 * ( b_j - b_k - b_l ) * dependentloadsweight / 100 , max( b_g - b_h , 0 ) ) / ( e ) ) + ( ( 16 * max( 0 , b_n - b_o ) + ( b_n / b_p ) * ( ( 10 ) * b_q + ( min( e , b_r ) ) ) ) / ( e ) ) + ( ( b_s / ( b_l + b_k ) ) * b_t / ( e ) ) + ( b_u / ( e ) ) + ( b_d / ( e ) ) ) ) ) + ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( a_i / ( e ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) * ( ( b_v / ( a_a if smt_on else ( e ) ) ) / ( ( ( ( b_q * ( 10 ) * ( 1 - ( b_n / b_p ) ) ) + ( 1 - ( b_n / b_p ) ) * ( min( e , b_r ) ) ) / ( e ) ) + ( ( 32.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_w / ( e ) ) + ( b_v / ( a_a if smt_on else ( e ) ) ) + ( 9 * b_x / ( e ) ) + ( ( ( 7 ) * b_y + b_z ) / ( a_a if smt_on else ( e ) ) ) ) ) ) + ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( a_i / ( e ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) * ( ( ( ( b_q * ( 10 ) * ( 1 - ( b_n / b_p ) ) ) + ( 1 - ( b_n / b_p ) ) * ( min( e , b_r ) ) ) / ( e ) ) / ( ( ( ( b_q * ( 10 ) * ( 1 - ( b_n / b_p ) ) ) + ( 1 - ( b_n / b_p ) ) * ( min( e , b_r ) ) ) / ( e ) ) + ( ( 32.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_w / ( e ) ) + ( b_v / ( a_a if smt_on else ( e ) ) ) + ( 9 * b_x / ( e ) ) + ( ( ( 7 ) * b_y + b_z ) / ( a_a if smt_on else ( e ) ) ) ) ) ) ) ) + ( 100 * ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) / max( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) , ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) ) * ( ( min( ( 7 ) * b_e + b_f , max( b_g - b_h , 0 ) ) / ( e ) ) / max( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) , ( ( min( ( 7 ) * b_e + b_f , max( b_g - b_h , 0 ) ) / ( e ) ) + ( 13 * b_i / ( e ) ) + ( min( 2 * ( b_j - b_k - b_l ) * dependentloadsweight / 100 , max( b_g - b_h , 0 ) ) / ( e ) ) + ( ( 16 * max( 0 , b_n - b_o ) + ( b_n / b_p ) * ( ( 10 ) * b_q + ( min( e , b_r ) ) ) ) / ( e ) ) + ( ( b_s / ( b_l + b_k ) ) * b_t / ( e ) ) + ( b_u / ( e ) ) + ( b_d / ( e ) ) ) ) ) + ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( a_i / ( e ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) * ( ( ( ( 7 ) * b_y + b_z ) / ( a_a if smt_on else ( e ) ) ) / ( ( ( ( b_q * ( 10 ) * ( 1 - ( b_n / b_p ) ) ) + ( 1 - ( b_n / b_p ) ) * ( min( e , b_r ) ) ) / ( e ) ) + ( ( 32.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_w / ( e ) ) + ( b_v / ( a_a if smt_on else ( e ) ) ) + ( 9 * b_x / ( e ) ) + ( ( ( 7 ) * b_y + b_z ) / ( a_a if smt_on else ( e ) ) ) ) ) ) ) ) + ( 100 * ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( ( ( a_o - a_m ) / ( e ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) * ( ( ( ( ( 32.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_z ) + ( ( 27 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_a ) ) * ( 1 + ( a_q / a_r ) / 2 ) / ( e ) ) + ( ( ( 27 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_b ) * ( 1 + ( a_q / a_r ) / 2 ) / ( e ) ) ) / ( ( ( ( ( 32.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_z ) + ( ( 27 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_a ) ) * ( 1 + ( a_q / a_r ) / 2 ) / ( e ) ) + ( ( ( 27 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_b ) * ( 1 + ( a_q / a_r ) / 2 ) / ( e ) ) + ( ( ( 12.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_c * ( 1 + ( a_q / a_r ) / 2 ) ) / ( e ) ) + ( a_v / ( e ) ) ) + ( ( a_i / ( e ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) * ( ( 32.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_w / ( e ) ) / ( ( ( ( ( b_q * ( 10 ) * ( 1 - ( b_n / b_p ) ) ) + ( 1 - ( b_n / b_p ) ) * ( min( e , b_r ) ) ) / ( e ) ) + ( ( 32.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_w / ( e ) ) + ( b_v / ( a_a if smt_on else ( e ) ) ) + ( 9 * b_x / ( e ) ) + ( ( ( 7 ) * b_y + b_z ) / ( a_a if smt_on else ( e ) ) ) ) - ( ( ( b_q * ( 10 ) * ( 1 - ( b_n / b_p ) ) ) + ( 1 - ( b_n / b_p ) ) * ( min( e , b_r ) ) ) / ( e ) ) ) ) + ( max( 0 , ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( 1 - ( max( ( max( 0 , ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( 1 - c_a / t ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( 1 - c_a / t ) , 0.0001 ) ) ) ) ) ) + ( 100 * ( ( ( max( 0 , ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) - ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) ) ) * ( c_b / ( e ) ) / ( ( c_b / ( e ) ) + ( c_c / ( e ) ) + ( ( ( c_d / ( e ) ) * ( e ) + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) ) / ( e ) if ( c_b < ( a_j - a_h ) ) else ( a_k + ( n / ( l + m + n + o ) ) * a_l ) / ( e ) ) ) ) + ( ( max( 0 , ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) - ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) ) ) * ( ( ( ( c_d / ( e ) ) * ( e ) + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) ) / ( e ) if ( c_b < ( a_j - a_h ) ) else ( a_k + ( n / ( l + m + n + o ) ) * a_l ) / ( e ) ) / ( ( c_b / ( e ) ) + ( c_c / ( e ) ) + ( ( ( c_d / ( e ) ) * ( e ) + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) ) / ( e ) if ( c_b < ( a_j - a_h ) ) else ( a_k + ( n / ( l + m + n + o ) ) * a_l ) / ( e ) ) ) ) * ( ( c_e / ( e ) ) / ( ( c_d / ( e ) ) + ( a_k / ( e ) ) + ( a_l / ( e ) ) + ( c_e / ( e ) ) ) ) ) ) ) + ( 100 * ( ( ( ( ( ( p / q ) * r / ( c ) ) / ( ( ( ( ( p / q ) * r / ( c ) ) + ( n / ( l + m + n + o ) ) * ( v - w ) / x ) - ( ( p / q ) * r / ( c ) ) ) + ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( 34 ) * y / ( c ) ) / ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( ( 5 ) * a - b ) / ( c ) ) * ( ( ( 3 ) * i / ( e ) ) + ( h / ( e ) + ( 10 ) * g / ( e ) ) * ( ( ( 1 - ( s / ( s + t ) ) ) * h / ( e ) ) + ( 10 * ( ( p / q ) * r / ( c ) ) * ( max( ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) * ( 1 - s / ( u - t ) ) , 0.0001 ) ) / ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) * ( ( s / ( s + t ) ) * h / ( e ) ) ) / ( ( ( s / ( s + t ) ) * h / ( e ) ) + ( ( 1 - ( s / ( s + t ) ) ) * h / ( e ) ) + ( ( 10 ) * g / ( e ) ) ) ) / ( ( f / ( e ) ) + ( d / ( e ) ) + ( h / ( e ) + ( 10 ) * g / ( e ) ) + ( ( 3 ) * i / ( e ) ) + ( j / ( e ) ) + ( k / ( e ) ) ) + ( max( 0 , ( l / ( l + m + n + o ) - b / ( c ) ) - ( ( ( 5 ) * a - b ) / ( c ) ) ) ) * ( z / ( a_a if smt_on else ( e ) ) / 2 ) / ( ( ( a_b - a_c ) / ( a_a if smt_on else ( e ) ) / 2 ) + ( ( a_d - a_e ) / ( a_a if smt_on else ( e ) ) / 2 ) + ( ( a_f - a_g ) / ( a_a if smt_on else ( e ) ) / 2 ) + ( z / ( a_a if smt_on else ( e ) ) / 2 ) ) ) ) + ( 10 * ( ( p / q ) * r / ( c ) ) * ( max( ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) * ( 1 - s / ( u - t ) ) , 0.0001 ) ) / ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) * ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) + ( ( max( 0 , ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( max( ( max( 0 , ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( 1 - c_a / t ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( 1 - c_a / t ) , 0.0001 ) ) ) ) + ( ( max( 0 , ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) - ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) ) ) * ( ( c_c / ( e ) ) + ( max( 0 , ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) - ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) ) ) * c_f / ( e ) * ( c_d / ( e ) ) ) / ( ( c_b / ( e ) ) + ( c_c / ( e ) ) + ( ( ( c_d / ( e ) ) * ( e ) + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) ) / ( e ) if ( c_b < ( a_j - a_h ) ) else ( a_k + ( n / ( l + m + n + o ) ) * a_l ) / ( e ) ) ) ) + ( ( ( ( ( p / q ) * r / ( c ) ) / ( ( ( ( ( p / q ) * r / ( c ) ) + ( n / ( l + m + n + o ) ) * ( v - w ) / x ) - ( ( p / q ) * r / ( c ) ) ) + ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( 34 ) * y / ( c ) ) / ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( p / q ) * r / ( c ) ) + ( n / ( l + m + n + o ) ) * ( v - w ) / x ) ) ) ) + ( 100 * ( ( c_g + 2 * c_h + c_i ) / ( c ) ) ) + ( 100 * ( ( n / ( l + m + n + o ) ) - ( ( c_g + 2 * c_h + c_i ) / ( c ) ) - ( ( ( ( ( p / q ) * r / ( c ) ) / ( ( ( ( ( p / q ) * r / ( c ) ) + ( n / ( l + m + n + o ) ) * ( v - w ) / x ) - ( ( p / q ) * r / ( c ) ) ) + ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( 34 ) * y / ( c ) ) / ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( p / q ) * r / ( c ) ) + ( n / ( l + m + n + o ) ) * ( v - w ) / x ) ) ) ) )", - "BaseFormula": " 100 - ( tma_big_code + tma_instruction_fetch_bw + tma_mispredictions + tma_cache_memory_bandwidth + tma_cache_memory_latency + tma_memory_data_tlbs + tma_memory_synchronization + tma_compute_bound_est + tma_irregular_overhead + tma_branching_overhead + tma_useful_work )", + "BaseFormula": " 100 - ( tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottleneck_mispredictions + tma_bottleneck_cache_memory_bandwidth + tma_bottleneck_cache_memory_latency + tma_bottleneck_memory_data_tlbs + tma_bottleneck_memory_synchronization + tma_bottleneck_compute_bound_est + tma_bottleneck_irregular_overhead + tma_bottleneck_branching_overhead + tma_bottleneck_useful_work )", "Category": "TMA", "CountDomain": "Scaled_Slots", "Threshold": { @@ -8258,11 +8258,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_Core_Bound_Likely" + "Value": "metric_TMA_Info_Botlnk_L0_Core_Bound_Likely" } ], "Formula": "a > 0.5", - "BaseFormula": "metric_TMA_Info_Botlnk_Core_Bound_Likely > 0.5", + "BaseFormula": "metric_TMA_Info_Botlnk_L0_Core_Bound_Likely > 0.5", "ThresholdIssues": "" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -9692,11 +9692,11 @@ }, { "Alias": "b", - "Value": "IPC" + "Value": "metric_TMA_Info_Thread_IPC" } ], "Formula": "a < 0.7 & b / 5 > 0.35", - "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & IPC / 5 > 0.35", + "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & metric_TMA_Info_Thread_IPC / 5 > 0.35", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -10037,11 +10037,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_DSB_Misses" + "Value": "metric_TMA_Info_Botlnk_L2_DSB_Misses" } ], "Formula": "a > 10", - "BaseFormula": "metric_TMA_Info_Botlnk_DSB_Misses > 10", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_DSB_Misses > 10", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -10138,11 +10138,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_DSB_Bandwidth" + "Value": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth" } ], "Formula": "a > 10", - "BaseFormula": "metric_TMA_Info_Botlnk_DSB_Bandwidth > 10", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth > 10", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -10210,11 +10210,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_IC_Misses" + "Value": "metric_TMA_Info_Botlnk_L2_IC_Misses" } ], "Formula": "a > 5", - "BaseFormula": "metric_TMA_Info_Botlnk_IC_Misses > 5", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_IC_Misses > 5", "ThresholdIssues": "$issueFL" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -10495,7 +10495,7 @@ ], "Constants": [], "Formula": "( 100 * ( 1 - ( 10 * ( ( a / b ) * c / ( d ) ) * ( max( ( ( e / ( e + f ) ) * ( max( 1 - ( ( g / ( g + h + i + j ) - k / ( d ) ) + ( j / ( g + h + i + j ) + ( ( 5 ) * l ) / ( d ) ) + ( i / ( g + h + i + j ) ) ) , 0 ) ) ) * ( 1 - e / ( l - f ) ) , 0.0001 ) ) / ( ( e / ( e + f ) ) * ( max( 1 - ( ( g / ( g + h + i + j ) - k / ( d ) ) + ( j / ( g + h + i + j ) + ( ( 5 ) * l ) / ( d ) ) + ( i / ( g + h + i + j ) ) ) , 0 ) ) ) ) ) * ( ( ( e / ( e + f ) ) * ( max( 1 - ( ( g / ( g + h + i + j ) - k / ( d ) ) + ( j / ( g + h + i + j ) + ( ( 5 ) * l ) / ( d ) ) + ( i / ( g + h + i + j ) ) ) , 0 ) ) ) + ( ( ( 5 ) * m - k ) / ( d ) ) * ( ( e / ( e + f ) ) * n / ( o ) ) / ( ( p / ( o ) ) + ( q / ( o ) ) + ( n / ( o ) + ( 10 ) * r / ( o ) ) + ( ( 3 ) * s / ( o ) ) + ( t / ( o ) ) + ( u / ( o ) ) ) ) ) * ( d ) / ( 5 ) / e / 100", - "BaseFormula": " tma_mispredictions * tma_info_thread_slots / ( 5 ) / br_misp_retired.all_branches / 100", + "BaseFormula": " tma_bottleneck_mispredictions * tma_info_thread_slots / ( 5 ) / br_misp_retired.all_branches / 100", "Category": "TMA", "CountDomain": "Core_Metric", "Threshold": { @@ -11235,11 +11235,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Memory_Page_Walks_Utilization" + "Value": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization" } ], "Formula": "a > 0.5", - "BaseFormula": "metric_TMA_Info_Memory_Page_Walks_Utilization > 0.5", + "BaseFormula": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization > 0.5", "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", @@ -11489,11 +11489,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Memory_Useless_HWPF" + "Value": "metric_TMA_Info_Memory_Prefetches_Useless_HWPF" } ], "Formula": "a > 0.15", - "BaseFormula": "metric_TMA_Info_Memory_Useless_HWPF > 0.15", + "BaseFormula": "metric_TMA_Info_Memory_Prefetches_Useless_HWPF > 0.15", "ThresholdIssues": "" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", diff --git a/ICL/metrics/perf/icelake_metrics_perf.json b/ICL/metrics/perf/icelake_metrics_perf.json index a39df88d..c0a176fb 100644 --- a/ICL/metrics/perf/icelake_metrics_perf.json +++ b/ICL/metrics/perf/icelake_metrics_perf.json @@ -20,7 +20,7 @@ }, { "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the back-end)", - "MetricExpr": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( ( tma_microcode_sequencer / ( tma_few_uops_instructions + tma_microcode_sequencer ) ) * ( tma_assists / tma_microcode_sequencer ) ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) * tma_mispredicts_resteers ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) ) ) - tma_big_code", + "MetricExpr": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( ( tma_microcode_sequencer / ( tma_few_uops_instructions + tma_microcode_sequencer ) ) * ( tma_assists / tma_microcode_sequencer ) ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) * tma_mispredicts_resteers ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) ) ) - tma_bottleneck_big_code", "MetricGroup": "BvFB;Fed;FetchBW;Frontend;TopdownL1;tma_L1_group;Default;Scaled_Slots", "MetricName": "tma_bottleneck_instruction_fetch_bw", "MetricThreshold": "tma_bottleneck_instruction_fetch_bw > 20", @@ -89,7 +89,7 @@ }, { "BriefDescription": "Total pipeline cost of remaining bottlenecks in the back-end", - "MetricExpr": "100 - ( tma_big_code + tma_instruction_fetch_bw + tma_mispredictions + tma_cache_memory_bandwidth + tma_cache_memory_latency + tma_memory_data_tlbs + tma_memory_synchronization + tma_compute_bound_est + tma_irregular_overhead + tma_branching_overhead + tma_useful_work )", + "MetricExpr": "100 - ( tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottleneck_mispredictions + tma_bottleneck_cache_memory_bandwidth + tma_bottleneck_cache_memory_latency + tma_bottleneck_memory_data_tlbs + tma_bottleneck_memory_synchronization + tma_bottleneck_compute_bound_est + tma_bottleneck_irregular_overhead + tma_bottleneck_branching_overhead + tma_bottleneck_useful_work )", "MetricGroup": "BvOB;Cor;Offcore;TopdownL1;tma_L1_group;Default;Scaled_Slots", "MetricName": "tma_bottleneck_other_bottlenecks", "MetricThreshold": "tma_bottleneck_other_bottlenecks > 20", @@ -1039,7 +1039,7 @@ "MetricExpr": "100 * ( 1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1 ) if tma_info_system_smt_2t_utilization > 0.5 else 0", "MetricGroup": "Cor;SMT;Metric", "MetricName": "tma_info_botlnk_l0_core_bound_likely", - "MetricThreshold": "tma_info_botlnk_core_bound_likely > 0.5" + "MetricThreshold": "tma_info_botlnk_l0_core_bound_likely > 0.5" }, { "BriefDescription": "Instructions Per Cycle (per Logical Processor)", @@ -1082,7 +1082,7 @@ }, { "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor", - "MetricExpr": "tma_info_thread_slots / ( TOPDOWN.SLOTS / 2 ) if #SMT_on else 1", + "MetricExpr": "tma_info_thread_slots / ( slots / 2 ) if #SMT_on else 1", "MetricGroup": "SMT;TmaL1;TopdownL1;tma_L1_group;Metric", "MetricName": "tma_info_thread_slots_utilization" }, @@ -1302,7 +1302,7 @@ "MetricExpr": "IDQ.DSB_UOPS / ( UOPS_ISSUED.ANY )", "MetricGroup": "DSB;Fed;FetchBW;Metric;tma_issueFB", "MetricName": "tma_info_frontend_dsb_coverage", - "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & ipc / 5 > 0.35", + "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 5 > 0.35", "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1353,7 +1353,7 @@ "MetricExpr": "100 * ( tma_fetch_latency * tma_dsb_switches / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_mite / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) )", "MetricGroup": "DSBmiss;Fed;Scaled_Slots;tma_issueFB", "MetricName": "tma_info_botlnk_l2_dsb_misses", - "MetricThreshold": "tma_info_botlnk_dsb_misses > 10", + "MetricThreshold": "tma_info_botlnk_l2_dsb_misses > 10", "PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1361,7 +1361,7 @@ "MetricExpr": "100 * ( tma_frontend_bound * ( tma_fetch_bandwidth / ( tma_fetch_latency + tma_fetch_bandwidth ) ) * ( tma_dsb / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) )", "MetricGroup": "DSB;Fed;FetchBW;Scaled_Slots;tma_issueFB", "MetricName": "tma_info_botlnk_l2_dsb_bandwidth", - "MetricThreshold": "tma_info_botlnk_dsb_bandwidth > 10", + "MetricThreshold": "tma_info_botlnk_l2_dsb_bandwidth > 10", "PublicDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1369,7 +1369,7 @@ "MetricExpr": "100 * ( tma_fetch_latency * tma_icache_misses / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) )", "MetricGroup": "Fed;FetchLat;IcMiss;Scaled_Slots;tma_issueFL", "MetricName": "tma_info_botlnk_l2_ic_misses", - "MetricThreshold": "tma_info_botlnk_ic_misses > 5", + "MetricThreshold": "tma_info_botlnk_l2_ic_misses > 5", "PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck." }, { @@ -1409,7 +1409,7 @@ }, { "BriefDescription": "Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricExpr": "tma_mispredictions * tma_info_thread_slots / ( 5 ) / BR_MISP_RETIRED.ALL_BRANCHES / 100", + "MetricExpr": "tma_bottleneck_mispredictions * tma_info_thread_slots / ( 5 ) / BR_MISP_RETIRED.ALL_BRANCHES / 100", "MetricGroup": "Bad;BrMispredicts;Core_Metric;tma_issueBM", "MetricName": "tma_info_bad_spec_branch_misprediction_cost", "PublicDescription": "Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_bottleneck_mispredictions, tma_branch_mispredicts, tma_mispredicts_resteers." @@ -1546,7 +1546,7 @@ "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 2 * tma_info_core_core_clks )", "MetricGroup": "Mem;MemoryTLB;Core_Metric", "MetricName": "tma_info_memory_tlb_page_walks_utilization", - "MetricThreshold": "tma_info_memory_page_walks_utilization > 0.5" + "MetricThreshold": "tma_info_memory_tlb_page_walks_utilization > 0.5" }, { "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", @@ -1595,7 +1595,7 @@ "MetricExpr": "L2_LINES_OUT.USELESS_HWPF / ( L2_LINES_OUT.SILENT + L2_LINES_OUT.NON_SILENT )", "MetricGroup": "Prefetches;Metric", "MetricName": "tma_info_memory_prefetches_useless_hwpf", - "MetricThreshold": "tma_info_memory_useless_hwpf > 0.15" + "MetricThreshold": "tma_info_memory_prefetches_useless_hwpf > 0.15" }, { "BriefDescription": "Average Latency for L2 cache miss demand Loads", diff --git a/ICX/metrics/icelakex_metrics.json b/ICX/metrics/icelakex_metrics.json index fcc4db46..b3c71d5c 100644 --- a/ICX/metrics/icelakex_metrics.json +++ b/ICX/metrics/icelakex_metrics.json @@ -2,7 +2,7 @@ "Header": { "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.", "Info": "Performance Monitoring Metrics for 3rd Generation Intel(R) Xeon(R) Processor Scalable Family based on Ice Lake microarchitecture0", - "DatePublished": "11/15/2024", + "DatePublished": "12/02/2024", "Version": "1.0", "Legend": "", "TmaVersion": "5.01", @@ -1456,7 +1456,7 @@ } ], "Formula": "100 * ( ( a / ( a + b + c + d ) - e / ( f ) ) - ( 1 - ( 10 * ( ( g / h ) * i / ( f ) ) * ( max( ( ( j / ( j + k ) ) * ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) + ( ( 5 ) * l ) / ( f ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * ( 1 - j / ( l - k ) ) , 0.0001 ) ) / ( ( j / ( j + k ) ) * ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) + ( ( 5 ) * l ) / ( f ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) ) ) * ( ( ( 5 ) * m - e ) / ( f ) ) * ( ( j / ( j + k ) ) * n / ( o ) ) / ( ( p / ( o ) ) + ( q / ( o ) ) + ( n / ( o ) + ( 10 ) * r / ( o ) ) + ( ( 3 ) * s / ( o ) ) + ( t / ( o ) ) + ( u / ( o ) ) ) - ( ( ( ( ( g / h ) * i / ( f ) ) / ( ( ( ( ( g / h ) * i / ( f ) ) + ( c / ( a + b + c + d ) ) * ( v - w ) / x ) - ( ( g / h ) * i / ( f ) ) ) + ( ( g / h ) * i / ( f ) ) ) ) * ( ( ( 34 ) * y / ( f ) ) / ( ( g / h ) * i / ( f ) ) ) ) * ( ( ( ( 5 ) * m - e ) / ( f ) ) * ( ( ( 3 ) * s / ( o ) ) + ( n / ( o ) + ( 10 ) * r / ( o ) ) * ( ( ( 1 - ( j / ( j + k ) ) ) * n / ( o ) ) + ( 10 * ( ( g / h ) * i / ( f ) ) * ( max( ( ( j / ( j + k ) ) * ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) + ( ( 5 ) * l ) / ( f ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * ( 1 - j / ( l - k ) ) , 0.0001 ) ) / ( ( j / ( j + k ) ) * ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) + ( ( 5 ) * l ) / ( f ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) ) * ( ( j / ( j + k ) ) * n / ( o ) ) ) / ( ( ( j / ( j + k ) ) * n / ( o ) ) + ( ( 1 - ( j / ( j + k ) ) ) * n / ( o ) ) + ( ( 10 ) * r / ( o ) ) ) ) / ( ( p / ( o ) ) + ( q / ( o ) ) + ( n / ( o ) + ( 10 ) * r / ( o ) ) + ( ( 3 ) * s / ( o ) ) + ( t / ( o ) ) + ( u / ( o ) ) ) + ( max( 0 , ( a / ( a + b + c + d ) - e / ( f ) ) - ( ( ( 5 ) * m - e ) / ( f ) ) ) ) * ( z / ( a_a if smt_on else ( o ) ) / 2 ) / ( ( ( a_b - a_c ) / ( a_a if smt_on else ( o ) ) / 2 ) + ( ( a_d - a_e ) / ( a_a if smt_on else ( o ) ) / 2 ) + ( z / ( a_a if smt_on else ( o ) ) / 2 ) ) ) ) ) - ( 100 * ( ( ( 5 ) * m - e ) / ( f ) ) * ( ( q / ( o ) ) + ( p / ( o ) ) + ( ( 10 ) * r / ( o ) ) ) / ( ( p / ( o ) ) + ( q / ( o ) ) + ( n / ( o ) + ( 10 ) * r / ( o ) ) + ( ( 3 ) * s / ( o ) ) + ( t / ( o ) ) + ( u / ( o ) ) ) )", - "BaseFormula": " 100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( ( tma_microcode_sequencer / ( tma_few_uops_instructions + tma_microcode_sequencer ) ) * ( tma_assists / tma_microcode_sequencer ) ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) * tma_mispredicts_resteers ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_ms ) ) ) ) - tma_big_code", + "BaseFormula": " 100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( ( tma_microcode_sequencer / ( tma_few_uops_instructions + tma_microcode_sequencer ) ) * ( tma_assists / tma_microcode_sequencer ) ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) * tma_mispredicts_resteers ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_ms ) ) ) ) - tma_bottleneck_big_code", "Category": "TMA", "CountDomain": "Scaled_Slots", "Threshold": { @@ -3102,7 +3102,7 @@ } ], "Formula": "100 - ( ( 100 * ( ( ( 5 ) * a - b ) / ( c ) ) * ( ( d / ( e ) ) + ( f / ( e ) ) + ( ( 10 ) * g / ( e ) ) ) / ( ( f / ( e ) ) + ( d / ( e ) ) + ( h / ( e ) + ( 10 ) * g / ( e ) ) + ( ( 3 ) * i / ( e ) ) + ( j / ( e ) ) + ( k / ( e ) ) ) ) + ( 100 * ( ( l / ( l + m + n + o ) - b / ( c ) ) - ( 1 - ( 10 * ( ( p / q ) * r / ( c ) ) * ( max( ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) * ( 1 - s / ( u - t ) ) , 0.0001 ) ) / ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( ( ( 5 ) * a - b ) / ( c ) ) * ( ( s / ( s + t ) ) * h / ( e ) ) / ( ( f / ( e ) ) + ( d / ( e ) ) + ( h / ( e ) + ( 10 ) * g / ( e ) ) + ( ( 3 ) * i / ( e ) ) + ( j / ( e ) ) + ( k / ( e ) ) ) - ( ( ( ( ( p / q ) * r / ( c ) ) / ( ( ( ( ( p / q ) * r / ( c ) ) + ( n / ( l + m + n + o ) ) * ( v - w ) / x ) - ( ( p / q ) * r / ( c ) ) ) + ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( 34 ) * y / ( c ) ) / ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( ( 5 ) * a - b ) / ( c ) ) * ( ( ( 3 ) * i / ( e ) ) + ( h / ( e ) + ( 10 ) * g / ( e ) ) * ( ( ( 1 - ( s / ( s + t ) ) ) * h / ( e ) ) + ( 10 * ( ( p / q ) * r / ( c ) ) * ( max( ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) * ( 1 - s / ( u - t ) ) , 0.0001 ) ) / ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) * ( ( s / ( s + t ) ) * h / ( e ) ) ) / ( ( ( s / ( s + t ) ) * h / ( e ) ) + ( ( 1 - ( s / ( s + t ) ) ) * h / ( e ) ) + ( ( 10 ) * g / ( e ) ) ) ) / ( ( f / ( e ) ) + ( d / ( e ) ) + ( h / ( e ) + ( 10 ) * g / ( e ) ) + ( ( 3 ) * i / ( e ) ) + ( j / ( e ) ) + ( k / ( e ) ) ) + ( max( 0 , ( l / ( l + m + n + o ) - b / ( c ) ) - ( ( ( 5 ) * a - b ) / ( c ) ) ) ) * ( z / ( a_a if smt_on else ( e ) ) / 2 ) / ( ( ( a_b - a_c ) / ( a_a if smt_on else ( e ) ) / 2 ) + ( ( a_d - a_e ) / ( a_a if smt_on else ( e ) ) / 2 ) + ( z / ( a_a if smt_on else ( e ) ) / 2 ) ) ) ) ) - ( 100 * ( ( ( 5 ) * a - b ) / ( c ) ) * ( ( d / ( e ) ) + ( f / ( e ) ) + ( ( 10 ) * g / ( e ) ) ) / ( ( f / ( e ) ) + ( d / ( e ) ) + ( h / ( e ) + ( 10 ) * g / ( e ) ) + ( ( 3 ) * i / ( e ) ) + ( j / ( e ) ) + ( k / ( e ) ) ) ) ) + ( 100 * ( 1 - ( 10 * ( ( p / q ) * r / ( c ) ) * ( max( ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) * ( 1 - s / ( u - t ) ) , 0.0001 ) ) / ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) + ( ( ( 5 ) * a - b ) / ( c ) ) * ( ( s / ( s + t ) ) * h / ( e ) ) / ( ( f / ( e ) ) + ( d / ( e ) ) + ( h / ( e ) + ( 10 ) * g / ( e ) ) + ( ( 3 ) * i / ( e ) ) + ( j / ( e ) ) + ( k / ( e ) ) ) ) ) + ( 100 * ( ( ( ( ( a_f + a_g ) / ( a_h + ( a_i + ( n / ( l + m + n + o ) ) * a_j ) + a_g ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( ( a_k / ( e ) + ( ( a_l - a_m ) / ( e ) ) - ( ( ( a_n * ( 1 + ( a_o / a_p ) ) ) / ( ( a_n * ( 1 + ( a_o / a_p ) ) ) + a_q ) ) * ( ( a_l - a_m ) / ( e ) ) ) ) ) / ( ( max( ( a_f - a_l ) / ( e ) , 0 ) ) + ( ( ( a_n * ( 1 + ( a_o / a_p ) ) ) / ( ( a_n * ( 1 + ( a_o / a_p ) ) ) + a_q ) ) * ( ( a_l - a_m ) / ( e ) ) ) + ( ( a_m - a_k ) / ( e ) ) + ( ( a_k / ( e ) + ( ( a_l - a_m ) / ( e ) ) - ( ( ( a_n * ( 1 + ( a_o / a_p ) ) ) / ( ( a_n * ( 1 + ( a_o / a_p ) ) ) + a_q ) ) * ( ( a_l - a_m ) / ( e ) ) ) ) ) + ( a_g / ( e ) ) ) ) * ( ( ( min( e , a_r ) ) / ( e ) ) / ( ( ( min( e , a_r ) ) / ( e ) ) + ( ( min( e , a_s ) ) / ( e ) - ( ( min( e , a_r ) ) / ( e ) ) ) ) ) ) + ( ( ( ( a_f + a_g ) / ( a_h + ( a_i + ( n / ( l + m + n + o ) ) * a_j ) + a_g ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( ( a_m - a_k ) / ( e ) ) / ( ( max( ( a_f - a_l ) / ( e ) , 0 ) ) + ( ( ( a_n * ( 1 + ( a_o / a_p ) ) ) / ( ( a_n * ( 1 + ( a_o / a_p ) ) ) + a_q ) ) * ( ( a_l - a_m ) / ( e ) ) ) + ( ( a_m - a_k ) / ( e ) ) + ( ( a_k / ( e ) + ( ( a_l - a_m ) / ( e ) ) - ( ( ( a_n * ( 1 + ( a_o / a_p ) ) ) / ( ( a_n * ( 1 + ( a_o / a_p ) ) ) + a_q ) ) * ( ( a_l - a_m ) / ( e ) ) ) ) ) + ( a_g / ( e ) ) ) ) * ( ( a_t / ( e ) ) / ( ( ( ( ( 48 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_x * ( a_y / ( a_y + a_z ) ) ) + ( ( 47.5 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_a ) ) * ( 1 + ( a_o / a_p ) / 2 ) / ( e ) ) + ( ( ( 47.5 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_b + a_x * ( 1 - ( a_y / ( a_y + a_z ) ) ) ) * ( 1 + ( a_o / a_p ) / 2 ) / ( e ) ) + ( ( ( 23 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_c * ( 1 + ( a_o / a_p ) / 2 ) ) / ( e ) ) + ( a_t / ( e ) ) ) ) ) + ( ( ( ( a_f + a_g ) / ( a_h + ( a_i + ( n / ( l + m + n + o ) ) * a_j ) + a_g ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( max( ( a_f - a_l ) / ( e ) , 0 ) ) / ( ( max( ( a_f - a_l ) / ( e ) , 0 ) ) + ( ( ( a_n * ( 1 + ( a_o / a_p ) ) ) / ( ( a_n * ( 1 + ( a_o / a_p ) ) ) + a_q ) ) * ( ( a_l - a_m ) / ( e ) ) ) + ( ( a_m - a_k ) / ( e ) ) + ( ( a_k / ( e ) + ( ( a_l - a_m ) / ( e ) ) - ( ( ( a_n * ( 1 + ( a_o / a_p ) ) ) / ( ( a_n * ( 1 + ( a_o / a_p ) ) ) + a_q ) ) * ( ( a_l - a_m ) / ( e ) ) ) ) ) + ( a_g / ( e ) ) ) ) * ( ( b_d / ( e ) ) / ( ( min( ( 7 ) * b_e + b_f , max( b_g - b_h , 0 ) ) / ( e ) ) + ( 13 * b_i / ( e ) ) + ( min( 2 * ( b_j - b_k - b_l ) * dependentloadsweight / 100 , max( b_g - b_h , 0 ) ) / ( e ) ) + ( ( 16 * max( 0 , b_n - b_o ) + ( b_n / b_p ) * ( ( 10 ) * b_q + ( min( e , b_r ) ) ) ) / ( e ) ) + ( ( b_s / ( b_l + b_k ) ) * b_t / ( e ) ) + ( b_u / ( e ) ) + ( b_d / ( e ) ) ) ) ) ) ) + ( 100 * ( ( ( ( ( a_f + a_g ) / ( a_h + ( a_i + ( n / ( l + m + n + o ) ) * a_j ) + a_g ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( ( a_k / ( e ) + ( ( a_l - a_m ) / ( e ) ) - ( ( ( a_n * ( 1 + ( a_o / a_p ) ) ) / ( ( a_n * ( 1 + ( a_o / a_p ) ) ) + a_q ) ) * ( ( a_l - a_m ) / ( e ) ) ) ) ) / ( ( max( ( a_f - a_l ) / ( e ) , 0 ) ) + ( ( ( a_n * ( 1 + ( a_o / a_p ) ) ) / ( ( a_n * ( 1 + ( a_o / a_p ) ) ) + a_q ) ) * ( ( a_l - a_m ) / ( e ) ) ) + ( ( a_m - a_k ) / ( e ) ) + ( ( a_k / ( e ) + ( ( a_l - a_m ) / ( e ) ) - ( ( ( a_n * ( 1 + ( a_o / a_p ) ) ) / ( ( a_n * ( 1 + ( a_o / a_p ) ) ) + a_q ) ) * ( ( a_l - a_m ) / ( e ) ) ) ) ) + ( a_g / ( e ) ) ) ) * ( ( ( min( e , a_s ) ) / ( e ) - ( ( min( e , a_r ) ) / ( e ) ) ) / ( ( ( min( e , a_r ) ) / ( e ) ) + ( ( min( e , a_s ) ) / ( e ) - ( ( min( e , a_r ) ) / ( e ) ) ) ) ) ) + ( ( ( ( a_f + a_g ) / ( a_h + ( a_i + ( n / ( l + m + n + o ) ) * a_j ) + a_g ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( ( a_m - a_k ) / ( e ) ) / ( ( max( ( a_f - a_l ) / ( e ) , 0 ) ) + ( ( ( a_n * ( 1 + ( a_o / a_p ) ) ) / ( ( a_n * ( 1 + ( a_o / a_p ) ) ) + a_q ) ) * ( ( a_l - a_m ) / ( e ) ) ) + ( ( a_m - a_k ) / ( e ) ) + ( ( a_k / ( e ) + ( ( a_l - a_m ) / ( e ) ) - ( ( ( a_n * ( 1 + ( a_o / a_p ) ) ) / ( ( a_n * ( 1 + ( a_o / a_p ) ) ) + a_q ) ) * ( ( a_l - a_m ) / ( e ) ) ) ) ) + ( a_g / ( e ) ) ) ) * ( ( ( ( 23 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_c * ( 1 + ( a_o / a_p ) / 2 ) ) / ( e ) ) / ( ( ( ( ( 48 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_x * ( a_y / ( a_y + a_z ) ) ) + ( ( 47.5 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_a ) ) * ( 1 + ( a_o / a_p ) / 2 ) / ( e ) ) + ( ( ( 47.5 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_b + a_x * ( 1 - ( a_y / ( a_y + a_z ) ) ) ) * ( 1 + ( a_o / a_p ) / 2 ) / ( e ) ) + ( ( ( 23 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_c * ( 1 + ( a_o / a_p ) / 2 ) ) / ( e ) ) + ( a_t / ( e ) ) ) ) ) + ( ( ( ( a_f + a_g ) / ( a_h + ( a_i + ( n / ( l + m + n + o ) ) * a_j ) + a_g ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( ( a_n * ( 1 + ( a_o / a_p ) ) ) / ( ( a_n * ( 1 + ( a_o / a_p ) ) ) + a_q ) ) * ( ( a_l - a_m ) / ( e ) ) ) / ( ( max( ( a_f - a_l ) / ( e ) , 0 ) ) + ( ( ( a_n * ( 1 + ( a_o / a_p ) ) ) / ( ( a_n * ( 1 + ( a_o / a_p ) ) ) + a_q ) ) * ( ( a_l - a_m ) / ( e ) ) ) + ( ( a_m - a_k ) / ( e ) ) + ( ( a_k / ( e ) + ( ( a_l - a_m ) / ( e ) ) - ( ( ( a_n * ( 1 + ( a_o / a_p ) ) ) / ( ( a_n * ( 1 + ( a_o / a_p ) ) ) + a_q ) ) * ( ( a_l - a_m ) / ( e ) ) ) ) ) + ( a_g / ( e ) ) ) ) + ( ( ( ( a_f + a_g ) / ( a_h + ( a_i + ( n / ( l + m + n + o ) ) * a_j ) + a_g ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( max( ( a_f - a_l ) / ( e ) , 0 ) ) / ( ( max( ( a_f - a_l ) / ( e ) , 0 ) ) + ( ( ( a_n * ( 1 + ( a_o / a_p ) ) ) / ( ( a_n * ( 1 + ( a_o / a_p ) ) ) + a_q ) ) * ( ( a_l - a_m ) / ( e ) ) ) + ( ( a_m - a_k ) / ( e ) ) + ( ( a_k / ( e ) + ( ( a_l - a_m ) / ( e ) ) - ( ( ( a_n * ( 1 + ( a_o / a_p ) ) ) / ( ( a_n * ( 1 + ( a_o / a_p ) ) ) + a_q ) ) * ( ( a_l - a_m ) / ( e ) ) ) ) ) + ( a_g / ( e ) ) ) ) * ( ( min( 2 * ( b_j - b_k - b_l ) * dependentloadsweight / 100 , max( b_g - b_h , 0 ) ) / ( e ) ) / ( ( min( ( 7 ) * b_e + b_f , max( b_g - b_h , 0 ) ) / ( e ) ) + ( 13 * b_i / ( e ) ) + ( min( 2 * ( b_j - b_k - b_l ) * dependentloadsweight / 100 , max( b_g - b_h , 0 ) ) / ( e ) ) + ( ( 16 * max( 0 , b_n - b_o ) + ( b_n / b_p ) * ( ( 10 ) * b_q + ( min( e , b_r ) ) ) ) / ( e ) ) + ( ( b_s / ( b_l + b_k ) ) * b_t / ( e ) ) + ( b_u / ( e ) ) + ( b_d / ( e ) ) ) ) ) + ( ( ( ( a_f + a_g ) / ( a_h + ( a_i + ( n / ( l + m + n + o ) ) * a_j ) + a_g ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( max( ( a_f - a_l ) / ( e ) , 0 ) ) / ( ( max( ( a_f - a_l ) / ( e ) , 0 ) ) + ( ( ( a_n * ( 1 + ( a_o / a_p ) ) ) / ( ( a_n * ( 1 + ( a_o / a_p ) ) ) + a_q ) ) * ( ( a_l - a_m ) / ( e ) ) ) + ( ( a_m - a_k ) / ( e ) ) + ( ( a_k / ( e ) + ( ( a_l - a_m ) / ( e ) ) - ( ( ( a_n * ( 1 + ( a_o / a_p ) ) ) / ( ( a_n * ( 1 + ( a_o / a_p ) ) ) + a_q ) ) * ( ( a_l - a_m ) / ( e ) ) ) ) ) + ( a_g / ( e ) ) ) ) * ( ( ( 16 * max( 0 , b_n - b_o ) + ( b_n / b_p ) * ( ( 10 ) * b_q + ( min( e , b_r ) ) ) ) / ( e ) ) / ( ( min( ( 7 ) * b_e + b_f , max( b_g - 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a_m ) / ( e ) ) ) + ( ( a_m - a_k ) / ( e ) ) + ( ( a_k / ( e ) + ( ( a_l - a_m ) / ( e ) ) - ( ( ( a_n * ( 1 + ( a_o / a_p ) ) ) / ( ( a_n * ( 1 + ( a_o / a_p ) ) ) + a_q ) ) * ( ( a_l - a_m ) / ( e ) ) ) ) ) + ( a_g / ( e ) ) ) ) * ( ( ( 120 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_w + ( 48 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_x ) / ( e ) ) / ( ( ( ( ( b_q * ( 10 ) * ( 1 - ( b_n / b_p ) ) ) + ( 1 - ( b_n / b_p ) ) * ( min( e , b_r ) ) ) / ( e ) ) + ( ( ( 120 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_w + ( 48 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_x ) / ( e ) ) + ( b_v / ( a_a if smt_on else ( e ) ) ) + ( 9 * b_y / ( e ) ) + ( ( ( 7 ) * b_z + c_a ) / ( a_a if smt_on else ( e ) ) ) ) - ( ( ( b_q * ( 10 ) * ( 1 - ( b_n / b_p ) ) ) + ( 1 - ( b_n / b_p ) ) * ( min( e , b_r ) ) ) / ( e ) ) ) ) + ( max( 0 , ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( 1 - ( max( ( max( 0 , ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( 1 - c_f / t ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( 1 - c_f / t ) , 0.0001 ) ) ) ) ) ) + ( 100 * ( ( ( max( 0 , ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) - ( ( ( a_f + a_g ) / ( a_h + ( a_i + ( n / ( l + m + n + o ) ) * a_j ) + a_g ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) ) ) * ( c_g / ( e ) ) / ( ( c_g / ( e ) ) + ( c_h / ( e ) ) + ( ( ( c_i / ( e ) ) * ( e ) + ( a_i + ( n / ( l + m + n + o ) ) * a_j ) ) / ( e ) if ( c_g < ( a_h - a_f ) ) else ( a_i + ( n / ( l + m + n + o ) ) * a_j ) / ( e ) ) ) ) + ( ( max( 0 , ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) - ( ( ( a_f + a_g ) / ( a_h + ( a_i + ( n / ( l + m + n + o ) ) * a_j ) + a_g ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) ) ) * ( ( ( ( c_i / ( e ) ) * ( e ) + ( a_i + ( n / ( l + m + n + o ) ) * a_j ) ) / ( e ) if ( c_g < ( a_h - a_f ) ) else ( a_i + ( n / ( l + m + n + o ) ) * a_j ) / ( e ) ) / ( ( c_g / ( e ) ) + ( c_h / ( e ) ) + ( ( ( c_i / ( e ) ) * ( e ) + ( a_i + ( n / ( l + m + n + o ) ) * a_j ) ) / ( e ) if ( c_g < ( a_h - a_f ) ) else ( a_i + ( n / ( l + m + n + o ) ) * a_j ) / ( e ) ) ) ) * ( ( c_j / ( e ) ) / ( ( c_i / ( e ) ) + ( a_i / ( e ) ) + ( a_j / ( e ) ) + ( c_j / ( e ) ) ) ) ) ) ) + ( 100 * ( ( ( ( ( ( p / q ) * r / ( c ) ) / ( ( ( ( ( p / q ) * r / ( c ) ) + ( n / ( l + m + n + o ) ) * ( v - w ) / x ) - ( ( p / q ) * r / ( c ) ) ) + ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( 34 ) * y / ( c ) ) / ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( ( 5 ) * a - b ) / ( c ) ) * ( ( ( 3 ) * i / ( e ) ) + ( h / ( e ) + ( 10 ) * g / ( e ) ) * ( ( ( 1 - ( s / ( s + t ) ) ) * h / ( e ) ) + ( 10 * ( ( p / q ) * r / ( c ) ) * ( max( ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) * ( 1 - s / ( u - t ) ) , 0.0001 ) ) / ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) * ( ( s / ( s + t ) ) * h / ( e ) ) ) / ( ( ( s / ( s + t ) ) * h / ( e ) ) + ( ( 1 - ( s / ( s + t ) ) ) * h / ( e ) ) + ( ( 10 ) * g / ( e ) ) ) ) / ( ( f / ( e ) ) + ( d / ( e ) ) + ( h / ( e ) + ( 10 ) * g / ( e ) ) + ( ( 3 ) * i / ( e ) ) + ( j / ( e ) ) + ( k / ( e ) ) ) + ( max( 0 , ( l / ( l + m + n + o ) - b / ( c ) ) - ( ( ( 5 ) * a - b ) / ( c ) ) ) ) * ( z / ( a_a if smt_on else ( e ) ) / 2 ) / ( ( ( a_b - a_c ) / ( a_a if smt_on else ( e ) ) / 2 ) + ( ( a_d - a_e ) / ( a_a if smt_on else ( e ) ) / 2 ) + ( z / ( a_a if smt_on else ( e ) ) / 2 ) ) ) ) + ( 10 * ( ( p / q ) * r / ( c ) ) * ( max( ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) * ( 1 - s / ( u - t ) ) , 0.0001 ) ) / ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) * ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) + ( ( max( 0 , ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( max( ( max( 0 , ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( 1 - c_f / t ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( 1 - c_f / t ) , 0.0001 ) ) ) ) + ( ( max( 0 , ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) - ( ( ( a_f + a_g ) / ( a_h + ( a_i + ( n / ( l + m + n + o ) ) * a_j ) + a_g ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) ) ) * ( ( c_h / ( e ) ) + ( max( 0 , ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) - ( ( ( a_f + a_g ) / ( a_h + ( a_i + ( n / ( l + m + n + o ) ) * a_j ) + a_g ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) ) ) * c_k / ( e ) * ( c_i / ( e ) ) ) / ( ( c_g / ( e ) ) + ( c_h / ( e ) ) + ( ( ( c_i / ( e ) ) * ( e ) + ( a_i + ( n / ( l + m + n + o ) ) * a_j ) ) / ( e ) if ( c_g < ( a_h - a_f ) ) else ( a_i + ( n / ( l + m + n + o ) ) * a_j ) / ( e ) ) ) ) + ( ( ( ( ( p / q ) * r / ( c ) ) / ( ( ( ( ( p / q ) * r / ( c ) ) + ( n / ( l + m + n + o ) ) * ( v - w ) / x ) - ( ( p / q ) * r / ( c ) ) ) + ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( 34 ) * y / ( c ) ) / ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( p / q ) * r / ( c ) ) + ( n / ( l + m + n + o ) ) * ( v - w ) / x ) ) ) ) + ( 100 * ( ( c_l + 2 * c_m + c_n ) / ( c ) ) ) + ( 100 * ( ( n / ( l + m + n + o ) ) - ( ( c_l + 2 * c_m + c_n ) / ( c ) ) - ( ( ( ( ( p / q ) * r / ( c ) ) / ( ( ( ( ( p / q ) * r / ( c ) ) + ( n / ( l + m + n + o ) ) * ( v - w ) / x ) - ( ( p / q ) * r / ( c ) ) ) + ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( 34 ) * y / ( c ) ) / ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( p / q ) * r / ( c ) ) + ( n / ( l + m + n + o ) ) * ( v - w ) / x ) ) ) ) )", - "BaseFormula": " 100 - ( tma_big_code + tma_instruction_fetch_bw + tma_mispredictions + tma_cache_memory_bandwidth + tma_cache_memory_latency + tma_memory_data_tlbs + tma_memory_synchronization + tma_compute_bound_est + tma_irregular_overhead + tma_branching_overhead + tma_useful_work )", + "BaseFormula": " 100 - ( tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottleneck_mispredictions + tma_bottleneck_cache_memory_bandwidth + tma_bottleneck_cache_memory_latency + tma_bottleneck_memory_data_tlbs + tma_bottleneck_memory_synchronization + tma_bottleneck_compute_bound_est + tma_bottleneck_irregular_overhead + tma_bottleneck_branching_overhead + tma_bottleneck_useful_work )", "Category": "TMA", "CountDomain": "Scaled_Slots", "Threshold": { @@ -9634,11 +9634,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_Core_Bound_Likely" + "Value": "metric_TMA_Info_Botlnk_L0_Core_Bound_Likely" } ], "Formula": "a > 0.5", - "BaseFormula": "metric_TMA_Info_Botlnk_Core_Bound_Likely > 0.5", + "BaseFormula": "metric_TMA_Info_Botlnk_L0_Core_Bound_Likely > 0.5", "ThresholdIssues": "" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -11008,11 +11008,11 @@ }, { "Alias": "b", - "Value": "IPC" + "Value": "metric_TMA_Info_Thread_IPC" } ], "Formula": "a < 0.7 & b / 5 > 0.35", - "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & IPC / 5 > 0.35", + "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & metric_TMA_Info_Thread_IPC / 5 > 0.35", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -11345,11 +11345,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_DSB_Misses" + "Value": "metric_TMA_Info_Botlnk_L2_DSB_Misses" } ], "Formula": "a > 10", - "BaseFormula": "metric_TMA_Info_Botlnk_DSB_Misses > 10", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_DSB_Misses > 10", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -11438,11 +11438,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_DSB_Bandwidth" + "Value": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth" } ], "Formula": "a > 10", - "BaseFormula": "metric_TMA_Info_Botlnk_DSB_Bandwidth > 10", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth > 10", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -11510,11 +11510,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_IC_Misses" + "Value": "metric_TMA_Info_Botlnk_L2_IC_Misses" } ], "Formula": "a > 5", - "BaseFormula": "metric_TMA_Info_Botlnk_IC_Misses > 5", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_IC_Misses > 5", "ThresholdIssues": "$issueFL" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -11795,7 +11795,7 @@ ], "Constants": [], "Formula": "( 100 * ( 1 - ( 10 * ( ( a / b ) * c / ( d ) ) * ( max( ( ( e / ( e + f ) ) * ( max( 1 - ( ( g / ( g + h + i + j ) - k / ( d ) ) + ( j / ( g + h + i + j ) + ( ( 5 ) * l ) / ( d ) ) + ( i / ( g + h + i + j ) ) ) , 0 ) ) ) * ( 1 - e / ( l - f ) ) , 0.0001 ) ) / ( ( e / ( e + f ) ) * ( max( 1 - ( ( g / ( g + h + i + j ) - k / ( d ) ) + ( j / ( g + h + i + j ) + ( ( 5 ) * l ) / ( d ) ) + ( i / ( g + h + i + j ) ) ) , 0 ) ) ) ) ) * ( ( ( e / ( e + f ) ) * ( max( 1 - ( ( g / ( g + h + i + j ) - k / ( d ) ) + ( j / ( g + h + i + j ) + ( ( 5 ) * l ) / ( d ) ) + ( i / ( g + h + i + j ) ) ) , 0 ) ) ) + ( ( ( 5 ) * m - k ) / ( d ) ) * ( ( e / ( e + f ) ) * n / ( o ) ) / ( ( p / ( o ) ) + ( q / ( o ) ) + ( n / ( o ) + ( 10 ) * r / ( o ) ) + ( ( 3 ) * s / ( o ) ) + ( t / ( o ) ) + ( u / ( o ) ) ) ) ) * ( d ) / ( 5 ) / e / 100", - "BaseFormula": " tma_mispredictions * tma_info_thread_slots / ( 5 ) / br_misp_retired.all_branches / 100", + "BaseFormula": " tma_bottleneck_mispredictions * tma_info_thread_slots / ( 5 ) / br_misp_retired.all_branches / 100", "Category": "TMA", "CountDomain": "Core_Metric", "Threshold": { @@ -12535,11 +12535,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Memory_Page_Walks_Utilization" + "Value": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization" } ], "Formula": "a > 0.5", - "BaseFormula": "metric_TMA_Info_Memory_Page_Walks_Utilization > 0.5", + "BaseFormula": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization > 0.5", "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", @@ -12849,11 +12849,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Memory_Useless_HWPF" + "Value": "metric_TMA_Info_Memory_Prefetches_Useless_HWPF" } ], "Formula": "a > 0.15", - "BaseFormula": "metric_TMA_Info_Memory_Useless_HWPF > 0.15", + "BaseFormula": "metric_TMA_Info_Memory_Prefetches_Useless_HWPF > 0.15", "ThresholdIssues": "" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", diff --git a/ICX/metrics/perf/icelakex_metrics_perf.json b/ICX/metrics/perf/icelakex_metrics_perf.json index 98c54963..9cd3449c 100644 --- a/ICX/metrics/perf/icelakex_metrics_perf.json +++ b/ICX/metrics/perf/icelakex_metrics_perf.json @@ -368,7 +368,7 @@ }, { "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the back-end)", - "MetricExpr": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( ( tma_microcode_sequencer / ( tma_few_uops_instructions + tma_microcode_sequencer ) ) * ( tma_assists / tma_microcode_sequencer ) ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) * tma_mispredicts_resteers ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_ms ) ) ) ) - tma_big_code", + "MetricExpr": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( ( tma_microcode_sequencer / ( tma_few_uops_instructions + tma_microcode_sequencer ) ) * ( tma_assists / tma_microcode_sequencer ) ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) * tma_mispredicts_resteers ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_ms ) ) ) ) - tma_bottleneck_big_code", "MetricGroup": "BvFB;Fed;FetchBW;Frontend;TopdownL1;tma_L1_group;Default;Scaled_Slots", "MetricName": "tma_bottleneck_instruction_fetch_bw", "MetricThreshold": "tma_bottleneck_instruction_fetch_bw > 20", @@ -437,7 +437,7 @@ }, { "BriefDescription": "Total pipeline cost of remaining bottlenecks in the back-end", - "MetricExpr": "100 - ( tma_big_code + tma_instruction_fetch_bw + tma_mispredictions + tma_cache_memory_bandwidth + tma_cache_memory_latency + tma_memory_data_tlbs + tma_memory_synchronization + tma_compute_bound_est + tma_irregular_overhead + tma_branching_overhead + tma_useful_work )", + "MetricExpr": "100 - ( tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottleneck_mispredictions + tma_bottleneck_cache_memory_bandwidth + tma_bottleneck_cache_memory_latency + tma_bottleneck_memory_data_tlbs + tma_bottleneck_memory_synchronization + tma_bottleneck_compute_bound_est + tma_bottleneck_irregular_overhead + tma_bottleneck_branching_overhead + tma_bottleneck_useful_work )", "MetricGroup": "BvOB;Cor;Offcore;TopdownL1;tma_L1_group;Default;Scaled_Slots", "MetricName": "tma_bottleneck_other_bottlenecks", "MetricThreshold": "tma_bottleneck_other_bottlenecks > 20", @@ -1405,7 +1405,7 @@ "MetricExpr": "100 * ( 1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1 ) if tma_info_system_smt_2t_utilization > 0.5 else 0", "MetricGroup": "Cor;SMT;Metric", "MetricName": "tma_info_botlnk_l0_core_bound_likely", - "MetricThreshold": "tma_info_botlnk_core_bound_likely > 0.5" + "MetricThreshold": "tma_info_botlnk_l0_core_bound_likely > 0.5" }, { "BriefDescription": "Instructions Per Cycle (per Logical Processor)", @@ -1448,7 +1448,7 @@ }, { "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor", - "MetricExpr": "tma_info_thread_slots / ( TOPDOWN.SLOTS / 2 ) if #SMT_on else 1", + "MetricExpr": "tma_info_thread_slots / ( slots / 2 ) if #SMT_on else 1", "MetricGroup": "SMT;TmaL1;TopdownL1;tma_L1_group;Metric", "MetricName": "tma_info_thread_slots_utilization" }, @@ -1656,7 +1656,7 @@ "MetricExpr": "IDQ.DSB_UOPS / ( UOPS_ISSUED.ANY )", "MetricGroup": "DSB;Fed;FetchBW;Metric;tma_issueFB", "MetricName": "tma_info_frontend_dsb_coverage", - "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & ipc / 5 > 0.35", + "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 5 > 0.35", "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1707,7 +1707,7 @@ "MetricExpr": "100 * ( tma_fetch_latency * tma_dsb_switches / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_mite / ( tma_mite + tma_dsb + tma_ms ) )", "MetricGroup": "DSBmiss;Fed;Scaled_Slots;tma_issueFB", "MetricName": "tma_info_botlnk_l2_dsb_misses", - "MetricThreshold": "tma_info_botlnk_dsb_misses > 10", + "MetricThreshold": "tma_info_botlnk_l2_dsb_misses > 10", "PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1715,7 +1715,7 @@ "MetricExpr": "100 * ( tma_frontend_bound * ( tma_fetch_bandwidth / ( tma_fetch_latency + tma_fetch_bandwidth ) ) * ( tma_dsb / ( tma_mite + tma_dsb + tma_ms ) ) )", "MetricGroup": "DSB;Fed;FetchBW;Scaled_Slots;tma_issueFB", "MetricName": "tma_info_botlnk_l2_dsb_bandwidth", - "MetricThreshold": "tma_info_botlnk_dsb_bandwidth > 10", + "MetricThreshold": "tma_info_botlnk_l2_dsb_bandwidth > 10", "PublicDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1723,7 +1723,7 @@ "MetricExpr": "100 * ( tma_fetch_latency * tma_icache_misses / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) )", "MetricGroup": "Fed;FetchLat;IcMiss;Scaled_Slots;tma_issueFL", "MetricName": "tma_info_botlnk_l2_ic_misses", - "MetricThreshold": "tma_info_botlnk_ic_misses > 5", + "MetricThreshold": "tma_info_botlnk_l2_ic_misses > 5", "PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck." }, { @@ -1763,7 +1763,7 @@ }, { "BriefDescription": "Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricExpr": "tma_mispredictions * tma_info_thread_slots / ( 5 ) / BR_MISP_RETIRED.ALL_BRANCHES / 100", + "MetricExpr": "tma_bottleneck_mispredictions * tma_info_thread_slots / ( 5 ) / BR_MISP_RETIRED.ALL_BRANCHES / 100", "MetricGroup": "Bad;BrMispredicts;Core_Metric;tma_issueBM", "MetricName": "tma_info_bad_spec_branch_misprediction_cost", "PublicDescription": "Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_bottleneck_mispredictions, tma_branch_mispredicts, tma_mispredicts_resteers." @@ -1900,7 +1900,7 @@ "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 2 * tma_info_core_core_clks )", "MetricGroup": "Mem;MemoryTLB;Core_Metric", "MetricName": "tma_info_memory_tlb_page_walks_utilization", - "MetricThreshold": "tma_info_memory_page_walks_utilization > 0.5" + "MetricThreshold": "tma_info_memory_tlb_page_walks_utilization > 0.5" }, { "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", @@ -1961,7 +1961,7 @@ "MetricExpr": "L2_LINES_OUT.USELESS_HWPF / ( L2_LINES_OUT.SILENT + L2_LINES_OUT.NON_SILENT )", "MetricGroup": "Prefetches;Metric", "MetricName": "tma_info_memory_prefetches_useless_hwpf", - "MetricThreshold": "tma_info_memory_useless_hwpf > 0.15" + "MetricThreshold": "tma_info_memory_prefetches_useless_hwpf > 0.15" }, { "BriefDescription": "Average Latency for L2 cache miss demand Loads", diff --git a/LNL/metrics/lunarlake_metrics_lioncove_core.json b/LNL/metrics/lunarlake_metrics_lioncove_core.json index 6f16bdc2..58c746e9 100644 --- a/LNL/metrics/lunarlake_metrics_lioncove_core.json +++ b/LNL/metrics/lunarlake_metrics_lioncove_core.json @@ -2,7 +2,7 @@ "Header": { "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.", "Info": "Performance Monitoring Metrics for Intel(R) Core(TM) processors based on Lunar Lake performance hybrid architecture0", - "DatePublished": "11/15/2024", + "DatePublished": "12/02/2024", "Version": "1.0", "Legend": "", "TmaVersion": "5.01", @@ -319,7 +319,7 @@ ], "Constants": [], "Formula": "100 * ( ( a / ( a + b + c + d ) ) - ( 1 - ( 10 * ( e / ( f ) ) * ( max( ( g / ( a + b + c + d ) ) * ( 1 - h / ( i - j ) ) , 0.0001 ) ) / ( g / ( a + b + c + d ) ) ) ) * ( k / ( a + b + c + d ) ) * ( ( ( g / ( a + b + c + d ) ) / ( b / ( a + b + c + d ) ) ) * l / ( m ) ) / ( ( n / ( m ) ) + ( o / ( m ) ) + ( l / ( m ) + ( p / ( m ) ) ) + ( ( 3 ) * q / ( m ) ) + ( r / ( m ) ) + ( s / ( m ) ) ) - ( ( 1 - t / u ) * ( ( k / ( a + b + c + d ) ) * ( ( ( 3 ) * q / ( m ) ) + ( l / ( m ) + ( p / ( m ) ) ) * ( ( ( 1 - ( ( g / ( a + b + c + d ) ) / ( b / ( a + b + c + d ) ) ) ) * l / ( m ) ) + ( ( ( g / ( a + b + c + d ) ) / ( b / ( a + b + c + d ) ) ) * l / ( m ) ) * ( max( ( g / ( a + b + c + d ) ) * ( 1 - h / ( i - j ) ) , 0.0001 ) ) / ( g / ( a + b + c + d ) ) ) / ( ( ( ( g / ( a + b + c + d ) ) / ( b / ( a + b + c + d ) ) ) * l / ( m ) ) + ( ( 1 - ( ( g / ( a + b + c + d ) ) / ( b / ( a + b + c + d ) ) ) ) * l / ( m ) ) + ( p / ( m ) ) ) ) / ( ( n / ( m ) ) + ( o / ( m ) ) + ( l / ( m ) + ( p / ( m ) ) ) + ( ( 3 ) * q / ( m ) ) + ( r / ( m ) ) + ( s / ( m ) ) ) + ( max( 0 , ( a / ( a + b + c + d ) ) - ( k / ( a + b + c + d ) ) ) ) * ( v / ( m ) ) / ( ( ( w / ( m ) + x / ( y + x ) * ( z - a_a ) ) / ( m ) ) + ( ( a_b + y / ( y + x ) * ( z - a_a ) ) / ( m ) ) + ( a_c / ( m ) ) + ( v / ( m ) ) ) ) ) ) - ( 100 * ( k / ( a + b + c + d ) ) * ( ( o / ( m ) ) + ( n / ( m ) ) + ( p / ( m ) ) ) / ( ( n / ( m ) ) + ( o / ( m ) ) + ( l / ( m ) + ( p / ( m ) ) ) + ( ( 3 ) * q / ( m ) ) + ( r / ( m ) ) + ( s / ( m ) ) ) )", - "BaseFormula": " 100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - inst_retired.rep_iteration / uops_retired.ms:c1 ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) ) ) - tma_big_code", + "BaseFormula": " 100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - inst_retired.rep_iteration / uops_retired.ms:c1 ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) ) ) - tma_bottleneck_big_code", "Category": "TMA", "CountDomain": "Scaled_Slots", "Threshold": { @@ -1844,7 +1844,7 @@ } ], "Formula": "100 - ( ( 100 * ( a / ( b + c + d + e ) ) * ( ( f / ( g ) ) + ( h / ( g ) ) + ( i / ( g ) ) ) / ( ( h / ( g ) ) + ( f / ( g ) ) + ( j / ( g ) + ( i / ( g ) ) ) + ( ( 3 ) * k / ( g ) ) + ( l / ( g ) ) + ( m / ( g ) ) ) ) + ( 100 * ( ( b / ( b + c + d + e ) ) - ( 1 - ( 10 * ( n / ( o ) ) * ( max( ( p / ( b + c + d + e ) ) * ( 1 - q / ( r - s ) ) , 0.0001 ) ) / ( p / ( b + c + d + e ) ) ) ) * ( a / ( b + c + d + e ) ) * ( ( ( p / ( b + c + d + e ) ) / ( c / ( b + c + d + e ) ) ) * j / ( g ) ) / ( ( h / ( g ) ) + ( f / ( g ) ) + ( j / ( g ) + ( i / ( g ) ) ) + ( ( 3 ) * k / ( g ) ) + ( l / ( g ) ) + ( m / ( g ) ) ) - ( ( 1 - t / u ) * ( ( a / ( b + c + d + e ) ) * ( ( ( 3 ) * k / ( g ) ) + ( j / ( g ) + ( i / ( g ) ) ) * ( ( ( 1 - ( ( p / ( b + c + d + e ) ) / ( c / ( b + c + d + e ) ) ) ) * j / ( g ) ) + ( ( ( p / ( b + c + d + e ) ) / ( c / ( b + c + d + e ) ) ) * j / ( g ) ) * ( max( ( p / ( b + c + d + e ) ) * ( 1 - q / ( r - s ) ) , 0.0001 ) ) / ( p / ( b + c + d + e ) ) ) / ( ( ( ( p / ( b + c + d + e ) ) / ( c / ( b + c + d + e ) ) ) * j / ( g ) ) + ( ( 1 - ( ( p / ( b + c + d + e ) ) / ( c / ( b + c + d + e ) ) ) ) * j / ( g ) ) + ( i / ( g ) ) ) ) / ( ( h / ( g ) ) + ( f / ( g ) ) + ( j / ( g ) + ( i / ( g ) ) ) + ( ( 3 ) * k / ( g ) ) + ( l / ( g ) ) + ( m / ( g ) ) ) + ( max( 0 , ( b / ( b + c + d + e ) ) - ( a / ( b + c + d + e ) ) ) ) * ( v / ( g ) ) / ( ( ( w / ( g ) + x / ( y + x ) * ( z - a_a ) ) / ( g ) ) + ( ( a_b + y / ( y + x ) * ( z - a_a ) ) / ( g ) ) + ( a_c / ( g ) ) + ( v / ( g ) ) ) ) ) ) - ( 100 * ( a / ( b + c + d + e ) ) * ( ( f / ( g ) ) + ( h / ( g ) ) + ( i / ( g ) ) ) / ( ( h / ( g ) ) + ( f / ( g ) ) + ( j / ( g ) + ( i / ( g ) ) ) + ( ( 3 ) * k / ( g ) ) + ( l / ( g ) ) + ( m / ( g ) ) ) ) ) + ( 100 * ( 1 - ( 10 * ( n / ( o ) ) * ( max( ( p / ( b + c + d + e ) ) * ( 1 - q / ( r - s ) ) , 0.0001 ) ) / ( p / ( b + c + d + e ) ) ) ) * ( ( p / ( b + c + d + e ) ) + ( a / ( b + c + d + e ) ) * ( ( ( p / ( b + c + d + e ) ) / ( c / ( b + c + d + e ) ) ) * j / ( g ) ) / ( ( h / ( g ) ) + ( f / ( g ) ) + ( j / ( g ) + ( i / ( g ) ) ) + ( ( 3 ) * k / ( g ) ) + ( l / ( g ) ) + ( m / ( g ) ) ) ) ) + ( 100 * ( ( ( a_d / ( b + c + d + e ) ) * ( ( ( a_e / ( g ) ) ) / ( ( a_f / ( g ) ) + ( a_g / ( g ) ) + ( a_h / ( g ) ) + ( ( a_e / ( g ) ) ) + ( a_i / ( g ) ) ) ) * ( ( ( min( g , a_j ) ) / ( g ) ) / ( ( ( min( g , a_j ) ) / ( g ) ) + ( ( min( g , a_k ) ) / ( g ) - ( ( min( g , a_j ) ) / ( g ) ) ) ) ) ) + ( ( a_d / ( b + c + d + e ) ) * ( ( a_h / ( g ) ) / ( ( a_f / ( g ) ) + ( a_g / ( g ) ) + ( a_h / ( g ) ) + ( ( a_e / ( g ) ) ) + ( a_i / ( g ) ) ) ) * ( ( ( a_l + a_m ) / ( g ) ) / ( ( ( ( min( ( a_n * a_o ) , a_n * ( 27 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_o > = 0 ) else ( a_n * ( 27 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) + ( min( ( a_s * a_t ) , a_s * ( 28 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_t > = 0 ) else ( a_s * ( 28 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) ) * ( 1 + ( a_u / a_v ) / 2 ) / ( g ) ) + ( ( ( min( ( a_w * a_x ) , a_w * ( 27 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_x > = 0 ) else ( a_w * ( 27 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) + ( min( ( a_y * a_z ) , a_y * ( 28 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_z > = 0 ) else ( a_y * ( 28 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) ) * ( 1 + ( a_u / a_v ) / 2 ) / ( g ) ) + ( ( min( ( b_a * b_b ) , b_a * ( 12 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( b_b > = 0 ) else ( b_a * ( 12 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( 1 + ( a_u / a_v ) / 2 ) / ( g ) ) + ( ( a_l + a_m ) / ( g ) ) ) ) ) + ( ( a_d / ( b + c + d + e ) ) * ( ( a_f / ( g ) ) / ( ( a_f / ( g ) ) + ( a_g / ( g ) ) + ( a_h / ( g ) ) + ( ( a_e / ( g ) ) ) + ( a_i / ( g ) ) ) ) * ( ( b_c / ( g ) ) / ( ( ( min( ( b_d * b_e ) , b_d * ( 7 ) ) if ( b_e > = 0 ) else ( b_d * ( 7 ) ) ) / ( g ) + ( b_f / ( g ) ) ) + ( 13 * b_g / ( g ) ) + ( 4 * b_h / ( g ) ) + ( ( min( ( b_i * b_j ) , b_i * 9 ) if ( b_j > = 0 ) else ( b_i * 9 ) ) / ( g ) ) + ( ( b_k * b_l ) / ( g ) ) + ( ( min( ( b_m * b_n ) , b_m * ( b_o / b_p ) ) if ( b_n > = 0 ) else ( b_m * ( b_o / b_p ) ) ) / ( g ) ) + ( b_c / ( g ) ) ) ) ) ) ) + ( 100 * ( ( ( a_d / ( b + c + d + e ) ) * ( ( ( a_e / ( g ) ) ) / ( ( a_f / ( g ) ) + ( a_g / ( g ) ) + ( a_h / ( g ) ) + ( ( a_e / ( g ) ) ) + ( a_i / ( g ) ) ) ) * ( ( ( min( g , a_k ) ) / ( g ) - ( ( min( g , a_j ) ) / ( g ) ) ) / ( ( ( min( g , a_j ) ) / ( g ) ) + ( ( min( g , a_k ) ) / ( g ) - ( ( min( g , a_j ) ) / ( g ) ) ) ) ) ) + ( ( a_d / ( b + c + d + e ) ) * ( ( a_h / ( g ) ) / ( ( a_f / ( g ) ) + ( a_g / ( g ) ) + ( a_h / ( g ) ) + ( ( a_e / ( g ) ) ) + ( a_i / ( g ) ) ) ) * ( ( ( min( ( b_a * b_b ) , b_a * ( 12 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( b_b > = 0 ) else ( b_a * ( 12 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( 1 + ( a_u / a_v ) / 2 ) / ( g ) ) / ( ( ( ( min( ( a_n * a_o ) , a_n * ( 27 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_o > = 0 ) else ( a_n * ( 27 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) + ( min( ( a_s * a_t ) , a_s * ( 28 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_t > = 0 ) else ( a_s * ( 28 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) ) * ( 1 + ( a_u / a_v ) / 2 ) / ( g ) ) + ( ( ( min( ( a_w * a_x ) , a_w * ( 27 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_x > = 0 ) else ( a_w * ( 27 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) + ( min( ( a_y * a_z ) , a_y * ( 28 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_z > = 0 ) else ( a_y * ( 28 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) ) * ( 1 + ( a_u / a_v ) / 2 ) / ( g ) ) + ( ( min( ( b_a * b_b ) , b_a * ( 12 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( b_b > = 0 ) else ( b_a * ( 12 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( 1 + ( a_u / a_v ) / 2 ) / ( g ) ) + ( ( a_l + a_m ) / ( g ) ) ) ) ) + ( ( a_d / ( b + c + d + e ) ) * ( a_g / ( g ) ) / ( ( a_f / ( g ) ) + ( a_g / ( g ) ) + ( a_h / ( g ) ) + ( ( a_e / ( g ) ) ) + ( a_i / ( g ) ) ) ) + ( ( a_d / ( b + c + d + e ) ) * ( ( a_f / ( g ) ) / ( ( a_f / ( g ) ) + ( a_g / ( g ) ) + ( a_h / ( g ) ) + ( ( a_e / ( g ) ) ) + ( a_i / ( g ) ) ) ) * ( ( 4 * b_h / ( g ) ) / ( ( ( min( ( b_d * b_e ) , b_d * ( 7 ) ) if ( b_e > = 0 ) else ( b_d * ( 7 ) ) ) / ( g ) + ( b_f / ( g ) ) ) + ( 13 * b_g / ( g ) ) + ( 4 * b_h / ( g ) ) + ( ( min( ( b_i * b_j ) , b_i * 9 ) if ( b_j > = 0 ) else ( b_i * 9 ) ) / ( g ) ) + ( ( b_k * b_l ) / ( g ) ) + ( ( min( ( b_m * b_n ) , b_m * ( b_o / b_p ) ) if ( b_n > = 0 ) else ( b_m * ( b_o / b_p ) ) ) / ( g ) ) + ( b_c / ( g ) ) ) ) ) + ( ( a_d / ( b + c + d + e ) ) * ( ( a_f / ( g ) ) / ( ( a_f / ( g ) ) + ( a_g / ( g ) ) + ( a_h / ( g ) ) + ( ( a_e / ( g ) ) ) + ( a_i / ( g ) ) ) ) * ( ( ( min( ( b_i * b_j ) , b_i * 9 ) if ( b_j > = 0 ) else ( b_i * 9 ) ) / ( g ) ) / ( ( ( min( ( b_d * b_e ) , b_d * ( 7 ) ) if ( b_e > = 0 ) else ( b_d * ( 7 ) ) ) / ( g ) + ( b_f / ( g ) ) ) + ( 13 * b_g / ( g ) ) + ( 4 * b_h / ( g ) ) + ( ( min( ( b_i * b_j ) , b_i * 9 ) if ( b_j > = 0 ) else ( b_i * 9 ) ) / ( g ) ) + ( ( b_k * b_l ) / ( g ) ) + ( ( min( ( b_m * b_n ) , b_m * ( b_o / b_p ) ) if ( b_n > = 0 ) else ( b_m * ( b_o / b_p ) ) ) / ( g ) ) + ( b_c / ( g ) ) ) ) ) + ( ( a_d / ( b + c + d + e ) ) * ( ( a_f / ( g ) ) / ( ( a_f / ( g ) ) + ( a_g / ( g ) ) + ( a_h / ( g ) ) + ( ( a_e / ( g ) ) ) + ( a_i / ( g ) ) ) ) * ( ( ( b_k * b_l ) / ( g ) ) / ( ( ( min( ( b_d * b_e ) , b_d * ( 7 ) ) if ( b_e > = 0 ) else ( b_d * ( 7 ) ) ) / ( g ) + ( b_f / ( g ) ) ) + ( 13 * b_g / ( g ) ) + ( 4 * b_h / ( g ) ) + ( ( min( ( b_i * b_j ) , b_i * 9 ) if ( b_j > = 0 ) else ( b_i * 9 ) ) / ( g ) ) + ( ( b_k * b_l ) / ( g ) ) + ( ( min( ( b_m * b_n ) , b_m * ( b_o / b_p ) ) if ( b_n > = 0 ) else ( b_m * ( b_o / b_p ) ) ) / ( g ) ) + ( b_c / ( g ) ) ) ) ) + ( ( a_d / ( b + c + d + e ) ) * ( ( a_f / ( g ) ) / ( ( a_f / ( g ) ) + ( a_g / ( g ) ) + ( a_h / ( g ) ) + ( ( a_e / ( g ) ) ) + ( a_i / ( g ) ) ) ) * ( ( ( min( ( b_m * b_n ) , b_m * ( b_o / b_p ) ) if ( b_n > = 0 ) else ( b_m * ( b_o / b_p ) ) ) / ( g ) ) / ( ( ( min( ( b_d * b_e ) , b_d * ( 7 ) ) if ( b_e > = 0 ) else ( b_d * ( 7 ) ) ) / ( g ) + ( b_f / ( g ) ) ) + ( 13 * b_g / ( g ) ) + ( 4 * b_h / ( g ) ) + ( ( min( ( b_i * b_j ) , b_i * 9 ) if ( b_j > = 0 ) else ( b_i * 9 ) ) / ( g ) ) + ( ( b_k * b_l ) / ( g ) ) + ( ( min( ( b_m * b_n ) , b_m * ( b_o / b_p ) ) if ( b_n > = 0 ) else ( b_m * ( b_o / b_p ) ) ) / ( g ) ) + ( b_c / ( g ) ) ) ) ) + ( ( a_d / ( b + c + d + e ) ) * ( ( a_i / ( g ) ) / ( ( a_f / ( g ) ) + ( a_g / ( g ) ) + ( a_h / ( g ) ) + ( ( a_e / ( g ) ) ) + ( a_i / ( g ) ) ) ) * ( ( ( min( ( b_q * b_r ) , b_q * 1 ) if ( b_r > = 0 ) else ( b_q * 1 ) ) / ( g ) ) / ( ( ( ( b_s * ( 10 ) * ( 1 - ( b_k / b_t ) ) ) + ( 1 - ( b_k / b_t ) ) * ( min( g , b_u ) ) ) / ( g ) ) + ( ( 28 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_v / ( g ) ) + ( ( min( ( b_q * b_r ) , b_q * 1 ) if ( b_r > = 0 ) else ( b_q * 1 ) ) / ( g ) ) + ( 9 * b_w / ( g ) ) + ( ( min( ( b_x * b_y ) , b_x * ( 7 ) ) if ( b_y > = 0 ) else ( b_x * ( 7 ) ) ) / ( g ) + ( b_z / ( g ) ) ) ) ) ) + ( ( a_d / ( b + c + d + e ) ) * ( ( a_i / ( g ) ) / ( ( a_f / ( g ) ) + ( a_g / ( g ) ) + ( a_h / ( g ) ) + ( ( a_e / ( g ) ) ) + ( a_i / ( g ) ) ) ) * ( ( ( ( b_s * ( 10 ) * ( 1 - ( b_k / b_t ) ) ) + ( 1 - ( b_k / b_t ) ) * ( min( g , b_u ) ) ) / ( g ) ) / ( ( ( ( b_s * ( 10 ) * ( 1 - ( b_k / b_t ) ) ) + ( 1 - ( b_k / b_t ) ) * ( min( g , b_u ) ) ) / ( g ) ) + ( ( 28 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_v / ( g ) ) + ( ( min( ( b_q * b_r ) , b_q * 1 ) if ( b_r > = 0 ) else ( b_q * 1 ) ) / ( g ) ) + ( 9 * b_w / ( g ) ) + ( ( min( ( b_x * b_y ) , b_x * ( 7 ) ) if ( b_y > = 0 ) else ( b_x * ( 7 ) ) ) / ( g ) + ( b_z / ( g ) ) ) ) ) ) ) ) + ( 100 * ( ( ( a_d / ( b + c + d + e ) ) * ( ( a_f / ( g ) ) / ( ( a_f / ( g ) ) + ( a_g / ( g ) ) + ( a_h / ( g ) ) + ( ( a_e / ( g ) ) ) + ( a_i / ( g ) ) ) ) * ( ( ( min( ( b_d * b_e ) , b_d * ( 7 ) ) if ( b_e > = 0 ) else ( b_d * ( 7 ) ) ) / ( g ) + ( b_f / ( g ) ) ) / ( ( ( min( ( b_d * b_e ) , b_d * ( 7 ) ) if ( b_e > = 0 ) else ( b_d * ( 7 ) ) ) / ( g ) + ( b_f / ( g ) ) ) + ( 13 * b_g / ( g ) ) + ( 4 * b_h / ( g ) ) + ( ( min( ( b_i * b_j ) , b_i * 9 ) if ( b_j > = 0 ) else ( b_i * 9 ) ) / ( g ) ) + ( ( b_k * b_l ) / ( g ) ) + ( ( min( ( b_m * b_n ) , b_m * ( b_o / b_p ) ) if ( b_n > = 0 ) else ( b_m * ( b_o / b_p ) ) ) / ( g ) ) + ( b_c / ( g ) ) ) ) ) + ( ( a_d / ( b + c + d + e ) ) * ( ( a_i / ( g ) ) / ( ( a_f / ( g ) ) + ( a_g / ( g ) ) + ( a_h / ( g ) ) + ( ( a_e / ( g ) ) ) + ( a_i / ( g ) ) ) ) * ( ( ( min( ( b_x * b_y ) , b_x * ( 7 ) ) if ( b_y > = 0 ) else ( b_x * ( 7 ) ) ) / ( g ) + ( b_z / ( g ) ) ) / ( ( ( ( b_s * ( 10 ) * ( 1 - ( b_k / b_t ) ) ) + ( 1 - ( b_k / b_t ) ) * ( min( g , b_u ) ) ) / ( g ) ) + ( ( 28 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_v / ( g ) ) + ( ( min( ( b_q * b_r ) , b_q * 1 ) if ( b_r > = 0 ) else ( b_q * 1 ) ) / ( g ) ) + ( 9 * b_w / ( g ) ) + ( ( min( ( b_x * b_y ) , b_x * ( 7 ) ) if ( b_y > = 0 ) else ( b_x * ( 7 ) ) ) / ( g ) + ( b_z / ( g ) ) ) ) ) ) ) ) + ( 100 * ( ( a_d / ( b + c + d + e ) ) * ( ( ( a_h / ( g ) ) / ( ( a_f / ( g ) ) + ( a_g / ( g ) ) + ( a_h / ( g ) ) + ( ( a_e / ( g ) ) ) + ( a_i / ( g ) ) ) ) * ( ( ( ( min( ( a_n * a_o ) , a_n * ( 27 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_o > = 0 ) else ( a_n * ( 27 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) + ( min( ( a_s * a_t ) , a_s * ( 28 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_t > = 0 ) else ( a_s * ( 28 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) ) * ( 1 + ( a_u / a_v ) / 2 ) / ( g ) ) + ( ( ( min( ( a_w * a_x ) , a_w * ( 27 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_x > = 0 ) else ( a_w * ( 27 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) + ( min( ( a_y * a_z ) , a_y * ( 28 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_z > = 0 ) else ( a_y * ( 28 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) ) * ( 1 + ( a_u / a_v ) / 2 ) / ( g ) ) ) / ( ( ( ( min( ( a_n * a_o ) , a_n * ( 27 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_o > = 0 ) else ( a_n * ( 27 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) + ( min( ( a_s * a_t ) , a_s * ( 28 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_t > = 0 ) else ( a_s * ( 28 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) ) * ( 1 + ( a_u / a_v ) / 2 ) / ( g ) ) + ( ( ( min( ( a_w * a_x ) , a_w * ( 27 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_x > = 0 ) else ( a_w * ( 27 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) + ( min( ( a_y * a_z ) , a_y * ( 28 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_z > = 0 ) else ( a_y * ( 28 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) ) * ( 1 + ( a_u / a_v ) / 2 ) / ( g ) ) + ( ( min( ( b_a * b_b ) , b_a * ( 12 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( b_b > = 0 ) else ( b_a * ( 12 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( 1 + ( a_u / a_v ) / 2 ) / ( g ) ) + ( ( a_l + a_m ) / ( g ) ) ) + ( ( a_i / ( g ) ) / ( ( a_f / ( g ) ) + ( a_g / ( g ) ) + ( a_h / ( g ) ) + ( ( a_e / ( g ) ) ) + ( a_i / ( g ) ) ) ) * ( ( 28 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_v / ( g ) ) / ( ( ( ( ( b_s * ( 10 ) * ( 1 - ( b_k / b_t ) ) ) + ( 1 - ( b_k / b_t ) ) * ( min( g , b_u ) ) ) / ( g ) ) + ( ( 28 * ( ( ( g ) / a_p ) * a_q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_v / ( g ) ) + ( ( min( ( b_q * b_r ) , b_q * 1 ) if ( b_r > = 0 ) else ( b_q * 1 ) ) / ( g ) ) + ( 9 * b_w / ( g ) ) + ( ( min( ( b_x * b_y ) , b_x * ( 7 ) ) if ( b_y > = 0 ) else ( b_x * ( 7 ) ) ) / ( g ) + ( b_z / ( g ) ) ) ) - ( ( ( b_s * ( 10 ) * ( 1 - ( b_k / b_t ) ) ) + ( 1 - ( b_k / b_t ) ) * ( min( g , b_u ) ) ) / ( g ) ) ) ) + ( max( 0 , ( c / ( b + c + d + e ) ) - ( p / ( b + c + d + e ) ) ) ) * ( 1 - ( max( ( max( 0 , ( c / ( b + c + d + e ) ) - ( p / ( b + c + d + e ) ) ) ) * ( 1 - c_a / s ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( c / ( b + c + d + e ) ) - ( p / ( b + c + d + e ) ) ) ) * ( 1 - c_a / s ) , 0.0001 ) ) ) ) ) ) + ( 100 * ( ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_d / ( b + c + d + e ) ) ) ) * ( c_b / ( g ) ) / ( ( c_b / ( g ) ) + ( ( c_c + c_d ) / ( g ) ) + ( ( c_e + ( c_f + ( d / ( b + c + d + e ) ) * c_g ) ) / ( g ) if ( c_b < ( c_h - c_i ) ) else ( c_f + ( d / ( b + c + d + e ) ) * c_g ) / ( g ) ) ) ) + ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_d / ( b + c + d + e ) ) ) ) * ( ( ( c_e + ( c_f + ( d / ( b + c + d + e ) ) * c_g ) ) / ( g ) if ( c_b < ( c_h - c_i ) ) else ( c_f + ( d / ( b + c + d + e ) ) * c_g ) / ( g ) ) / ( ( c_b / ( g ) ) + ( ( c_c + c_d ) / ( g ) ) + ( ( c_e + ( c_f + ( d / ( b + c + d + e ) ) * c_g ) ) / ( g ) if ( c_b < ( c_h - c_i ) ) else ( c_f + ( d / ( b + c + d + e ) ) * c_g ) / ( g ) ) ) ) * ( ( c_j / ( g ) ) / ( ( c_e / ( g ) ) + ( c_f / ( g ) ) + ( c_k / ( g ) ) + ( c_j / ( g ) ) ) ) ) ) ) + ( 100 * ( ( ( 1 - t / u ) * ( ( a / ( b + c + d + e ) ) * ( ( ( 3 ) * k / ( g ) ) + ( j / ( g ) + ( i / ( g ) ) ) * ( ( ( 1 - ( ( p / ( b + c + d + e ) ) / ( c / ( b + c + d + e ) ) ) ) * j / ( g ) ) + ( ( ( p / ( b + c + d + e ) ) / ( c / ( b + c + d + e ) ) ) * j / ( g ) ) * ( max( ( p / ( b + c + d + e ) ) * ( 1 - q / ( r - s ) ) , 0.0001 ) ) / ( p / ( b + c + d + e ) ) ) / ( ( ( ( p / ( b + c + d + e ) ) / ( c / ( b + c + d + e ) ) ) * j / ( g ) ) + ( ( 1 - ( ( p / ( b + c + d + e ) ) / ( c / ( b + c + d + e ) ) ) ) * j / ( g ) ) + ( i / ( g ) ) ) ) / ( ( h / ( g ) ) + ( f / ( g ) ) + ( j / ( g ) + ( i / ( g ) ) ) + ( ( 3 ) * k / ( g ) ) + ( l / ( g ) ) + ( m / ( g ) ) ) + ( max( 0 , ( b / ( b + c + d + e ) ) - ( a / ( b + c + d + e ) ) ) ) * ( v / ( g ) ) / ( ( ( w / ( g ) + x / ( y + x ) * ( z - a_a ) ) / ( g ) ) + ( ( a_b + y / ( y + x ) * ( z - a_a ) ) / ( g ) ) + ( a_c / ( g ) ) + ( v / ( g ) ) ) ) ) + ( 10 * ( n / ( o ) ) * ( max( ( p / ( b + c + d + e ) ) * ( 1 - q / ( r - s ) ) , 0.0001 ) ) / ( p / ( b + c + d + e ) ) ) * ( p / ( b + c + d + e ) ) + ( ( max( 0 , ( c / ( b + c + d + e ) ) - ( p / ( b + c + d + e ) ) ) ) * ( max( ( max( 0 , ( c / ( b + c + d + e ) ) - ( p / ( b + c + d + e ) ) ) ) * ( 1 - c_a / s ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( c / ( b + c + d + e ) ) - ( p / ( b + c + d + e ) ) ) ) * ( 1 - c_a / s ) , 0.0001 ) ) ) ) + ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_d / ( b + c + d + e ) ) ) ) * ( ( ( c_c + c_d ) / ( g ) ) + c_l / ( g ) * ( c_e / ( g ) ) ) / ( ( c_b / ( g ) ) + ( ( c_c + c_d ) / ( g ) ) + ( ( c_e + ( c_f + ( d / ( b + c + d + e ) ) * c_g ) ) / ( g ) if ( c_b < ( c_h - c_i ) ) else ( c_f + ( d / ( b + c + d + e ) ) * c_g ) / ( g ) ) ) ) + ( ( ( ( n / ( o ) ) / ( ( n / ( o ) ) + max( 0 , ( c_m / ( b + c + d + e ) ) - ( n / ( o ) ) ) ) ) * ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * c_n / ( o ) / ( n / ( o ) ) ) ) * ( c_m / ( b + c + d + e ) ) ) ) ) + ( 100 * ( ( c_o + 2 * c_p + c_q ) / ( o ) ) ) + ( 100 * ( ( d / ( b + c + d + e ) ) - ( ( c_o + 2 * c_p + c_q ) / ( o ) ) - ( ( ( ( n / ( o ) ) / ( ( n / ( o ) ) + max( 0 , ( c_m / ( b + c + d + e ) ) - ( n / ( o ) ) ) ) ) * ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * c_n / ( o ) / ( n / ( o ) ) ) ) * ( c_m / ( b + c + d + e ) ) ) ) ) )", - "BaseFormula": " 100 - ( tma_big_code + tma_instruction_fetch_bw + tma_mispredictions + tma_cache_memory_bandwidth + tma_cache_memory_latency + tma_memory_data_tlbs + tma_memory_synchronization + tma_compute_bound_est + tma_irregular_overhead + tma_branching_overhead + tma_useful_work )", + "BaseFormula": " 100 - ( tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottleneck_mispredictions + tma_bottleneck_cache_memory_bandwidth + tma_bottleneck_cache_memory_latency + tma_bottleneck_memory_data_tlbs + tma_bottleneck_memory_synchronization + tma_bottleneck_compute_bound_est + tma_bottleneck_irregular_overhead + tma_bottleneck_branching_overhead + tma_bottleneck_useful_work )", "Category": "TMA", "CountDomain": "Scaled_Slots", "Threshold": { @@ -9328,11 +9328,11 @@ }, { "Alias": "b", - "Value": "IPC" + "Value": "metric_TMA_Info_Thread_IPC" } ], "Formula": "a < 0.7 & b / 8 > 0.35", - "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & IPC / 8 > 0.35", + "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & metric_TMA_Info_Thread_IPC / 8 > 0.35", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -9800,11 +9800,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_DSB_Misses" + "Value": "metric_TMA_Info_Botlnk_L2_DSB_Misses" } ], "Formula": "a > 10", - "BaseFormula": "metric_TMA_Info_Botlnk_DSB_Misses > 10", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_DSB_Misses > 10", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -9884,11 +9884,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_DSB_Bandwidth" + "Value": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth" } ], "Formula": "a > 10", - "BaseFormula": "metric_TMA_Info_Botlnk_DSB_Bandwidth > 10", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth > 10", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -9964,11 +9964,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_IC_Misses" + "Value": "metric_TMA_Info_Botlnk_L2_IC_Misses" } ], "Formula": "a > 5", - "BaseFormula": "metric_TMA_Info_Botlnk_IC_Misses > 5", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_IC_Misses > 5", "ThresholdIssues": "$issueFL" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -10265,7 +10265,7 @@ ], "Constants": [], "Formula": "( 100 * ( 1 - ( 10 * ( a / ( b ) ) * ( max( ( c / ( d + e + f + g ) ) * ( 1 - h / ( i - j ) ) , 0.0001 ) ) / ( c / ( d + e + f + g ) ) ) ) * ( ( c / ( d + e + f + g ) ) + ( k / ( d + e + f + g ) ) * ( ( ( c / ( d + e + f + g ) ) / ( e / ( d + e + f + g ) ) ) * l / ( m ) ) / ( ( n / ( m ) ) + ( o / ( m ) ) + ( l / ( m ) + ( p / ( m ) ) ) + ( ( 3 ) * q / ( m ) ) + ( r / ( m ) ) + ( s / ( m ) ) ) ) ) * ( b ) / ( 8 ) / h / 100", - "BaseFormula": " tma_mispredictions * tma_info_thread_slots / ( 8 ) / br_misp_retired.all_branches / 100", + "BaseFormula": " tma_bottleneck_mispredictions * tma_info_thread_slots / ( 8 ) / br_misp_retired.all_branches / 100", "Category": "TMA", "CountDomain": "Core_Metric", "Threshold": { @@ -11091,11 +11091,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Memory_Page_Walks_Utilization" + "Value": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization" } ], "Formula": "a > 0.5", - "BaseFormula": "metric_TMA_Info_Memory_Page_Walks_Utilization > 0.5", + "BaseFormula": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization > 0.5", "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", @@ -11221,11 +11221,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Memory_Load_STLB_Miss_Ret" + "Value": "metric_TMA_Info_Memory_TLB_Load_STLB_Miss_Ret" } ], "Formula": "a > 0.05", - "BaseFormula": "metric_TMA_Info_Memory_Load_STLB_Miss_Ret > 0.05", + "BaseFormula": "metric_TMA_Info_Memory_TLB_Load_STLB_Miss_Ret > 0.05", "ThresholdIssues": "" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -11261,11 +11261,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Memory_Store_STLB_Miss_Ret" + "Value": "metric_TMA_Info_Memory_TLB_Store_STLB_Miss_Ret" } ], "Formula": "a > 0.05", - "BaseFormula": "metric_TMA_Info_Memory_Store_STLB_Miss_Ret > 0.05", + "BaseFormula": "metric_TMA_Info_Memory_TLB_Store_STLB_Miss_Ret > 0.05", "ThresholdIssues": "" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -11301,11 +11301,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Memory_Useless_HWPF" + "Value": "metric_TMA_Info_Memory_Prefetches_Useless_HWPF" } ], "Formula": "a > 0.15", - "BaseFormula": "metric_TMA_Info_Memory_Useless_HWPF > 0.15", + "BaseFormula": "metric_TMA_Info_Memory_Prefetches_Useless_HWPF > 0.15", "ThresholdIssues": "" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", diff --git a/LNL/metrics/perf/lunarlake_metrics_lioncove_core_perf.json b/LNL/metrics/perf/lunarlake_metrics_lioncove_core_perf.json index f1944578..fad64026 100644 --- a/LNL/metrics/perf/lunarlake_metrics_lioncove_core_perf.json +++ b/LNL/metrics/perf/lunarlake_metrics_lioncove_core_perf.json @@ -20,7 +20,7 @@ }, { "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the back-end)", - "MetricExpr": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\\,cmask\\=0x1@ ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) ) ) - tma_big_code", + "MetricExpr": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\\,cmask\\=0x1@ ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) ) ) - tma_bottleneck_big_code", "MetricGroup": "BvFB;Fed;FetchBW;Frontend;TopdownL1;tma_L1_group;Default;Scaled_Slots", "MetricName": "tma_bottleneck_instruction_fetch_bw", "MetricThreshold": "tma_bottleneck_instruction_fetch_bw > 20", @@ -33,7 +33,7 @@ "MetricGroup": "BvMB;Mem;MemoryBW;Offcore;TopdownL1;tma_L1_group;Default;Scaled_Slots;tma_issueBW", "MetricName": "tma_bottleneck_cache_memory_bandwidth", "MetricThreshold": "tma_bottleneck_cache_memory_bandwidth > 20", - "PublicDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full.", + "PublicDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_mem_bandwidth, tma_sq_full.", "DefaultMetricgroupName": "TopdownL1", "MetricGroupnoGroup": "TopdownL1;Default" }, @@ -89,7 +89,7 @@ }, { "BriefDescription": "Total pipeline cost of remaining bottlenecks in the back-end", - "MetricExpr": "100 - ( tma_big_code + tma_instruction_fetch_bw + tma_mispredictions + tma_cache_memory_bandwidth + tma_cache_memory_latency + tma_memory_data_tlbs + tma_memory_synchronization + tma_compute_bound_est + tma_irregular_overhead + tma_branching_overhead + tma_useful_work )", + "MetricExpr": "100 - ( tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottleneck_mispredictions + tma_bottleneck_cache_memory_bandwidth + tma_bottleneck_cache_memory_latency + tma_bottleneck_memory_data_tlbs + tma_bottleneck_memory_synchronization + tma_bottleneck_compute_bound_est + tma_bottleneck_irregular_overhead + tma_bottleneck_branching_overhead + tma_bottleneck_useful_work )", "MetricGroup": "BvOB;Cor;Offcore;TopdownL1;tma_L1_group;Default;Scaled_Slots", "MetricName": "tma_bottleneck_other_bottlenecks", "MetricThreshold": "tma_bottleneck_other_bottlenecks > 20", @@ -541,7 +541,7 @@ "MetricName": "tma_fb_full", "ScaleUnit": "100%", "MetricThreshold": "tma_fb_full > 0.3", - "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_bottleneck_cache_memory_bandwidth, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store_latency, tma_streaming_stores." + "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_bottleneck_cache_memory_bandwidth, tma_mem_bandwidth, tma_sq_full, tma_store_latency, tma_streaming_stores." }, { "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads", @@ -604,7 +604,7 @@ "MetricName": "tma_sq_full", "ScaleUnit": "100%", "MetricThreshold": "tma_sq_full > 0.3 & tma_l3_bound > 0.05 & tma_memory_bound > 0.2 & tma_backend_bound > 0.2", - "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_bottleneck_cache_memory_bandwidth, tma_fb_full, tma_info_system_dram_bw_use, tma_mem_bandwidth." + "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_bottleneck_cache_memory_bandwidth, tma_fb_full, tma_mem_bandwidth." }, { "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", @@ -622,7 +622,7 @@ "MetricName": "tma_mem_bandwidth", "ScaleUnit": "100%", "MetricThreshold": "tma_mem_bandwidth > 0.2 & tma_dram_bound > 0.1 & tma_memory_bound > 0.2 & tma_backend_bound > 0.2", - "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_bottleneck_cache_memory_bandwidth, tma_fb_full, tma_info_system_dram_bw_use, tma_sq_full." + "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_bottleneck_cache_memory_bandwidth, tma_fb_full, tma_sq_full." }, { "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM)", @@ -1350,7 +1350,7 @@ "MetricExpr": "IDQ.DSB_UOPS / ( UOPS_ISSUED.ANY )", "MetricGroup": "DSB;Fed;FetchBW;Metric;tma_issueFB", "MetricName": "tma_info_frontend_dsb_coverage", - "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & ipc / 8 > 0.35", + "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 8 > 0.35", "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1428,7 +1428,7 @@ "MetricExpr": "100 * ( tma_fetch_latency * tma_dsb_switches / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_mite / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) )", "MetricGroup": "DSBmiss;Fed;Scaled_Slots;tma_issueFB", "MetricName": "tma_info_botlnk_l2_dsb_misses", - "MetricThreshold": "tma_info_botlnk_dsb_misses > 10", + "MetricThreshold": "tma_info_botlnk_l2_dsb_misses > 10", "PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1436,7 +1436,7 @@ "MetricExpr": "100 * ( tma_frontend_bound * ( tma_fetch_bandwidth / ( tma_fetch_latency + tma_fetch_bandwidth ) ) * ( tma_dsb / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) )", "MetricGroup": "DSB;Fed;FetchBW;Scaled_Slots;tma_issueFB", "MetricName": "tma_info_botlnk_l2_dsb_bandwidth", - "MetricThreshold": "tma_info_botlnk_dsb_bandwidth > 10", + "MetricThreshold": "tma_info_botlnk_l2_dsb_bandwidth > 10", "PublicDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1444,7 +1444,7 @@ "MetricExpr": "100 * ( tma_fetch_latency * tma_icache_misses / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) )", "MetricGroup": "Fed;FetchLat;IcMiss;Scaled_Slots;tma_issueFL", "MetricName": "tma_info_botlnk_l2_ic_misses", - "MetricThreshold": "tma_info_botlnk_ic_misses > 5", + "MetricThreshold": "tma_info_botlnk_l2_ic_misses > 5", "PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck." }, { @@ -1489,7 +1489,7 @@ }, { "BriefDescription": "Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricExpr": "tma_mispredictions * tma_info_thread_slots / ( 8 ) / BR_MISP_RETIRED.ALL_BRANCHES / 100", + "MetricExpr": "tma_bottleneck_mispredictions * tma_info_thread_slots / ( 8 ) / BR_MISP_RETIRED.ALL_BRANCHES / 100", "MetricGroup": "Bad;BrMispredicts;Core_Metric;tma_issueBM", "MetricName": "tma_info_bad_spec_branch_misprediction_cost", "PublicDescription": "Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_bottleneck_mispredictions, tma_branch_mispredicts, tma_mispredicts_resteers." @@ -1646,7 +1646,7 @@ "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 4 * tma_info_thread_clks )", "MetricGroup": "Mem;MemoryTLB;Core_Metric", "MetricName": "tma_info_memory_tlb_page_walks_utilization", - "MetricThreshold": "tma_info_memory_page_walks_utilization > 0.5" + "MetricThreshold": "tma_info_memory_tlb_page_walks_utilization > 0.5" }, { "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", @@ -1671,21 +1671,21 @@ "MetricExpr": "( MEM_INST_RETIRED.STLB_MISS_LOADS * cpu_core@MEM_INST_RETIRED.STLB_MISS_LOADS@R ) / tma_info_thread_clks", "MetricGroup": "Mem;MemoryTLB;Clocks_Retired", "MetricName": "tma_info_memory_tlb_load_stlb_miss_ret", - "MetricThreshold": "tma_info_memory_load_stlb_miss_ret > 0.05" + "MetricThreshold": "tma_info_memory_tlb_load_stlb_miss_ret > 0.05" }, { "BriefDescription": "This metric represents fraction of cycles the CPU retirement was stalled likely due to STLB misses by demand stores", "MetricExpr": "( MEM_INST_RETIRED.STLB_MISS_STORES * cpu_core@MEM_INST_RETIRED.STLB_MISS_STORES@R ) / tma_info_thread_clks", "MetricGroup": "Mem;MemoryTLB;Clocks_Retired", "MetricName": "tma_info_memory_tlb_store_stlb_miss_ret", - "MetricThreshold": "tma_info_memory_store_stlb_miss_ret > 0.05" + "MetricThreshold": "tma_info_memory_tlb_store_stlb_miss_ret > 0.05" }, { "BriefDescription": "Rate of L2 HW prefetched lines that were not used by demand accesses", "MetricExpr": "L2_LINES_OUT.USELESS_HWPF / ( L2_LINES_OUT.SILENT + L2_LINES_OUT.NON_SILENT )", "MetricGroup": "Prefetches;Metric", "MetricName": "tma_info_memory_prefetches_useless_hwpf", - "MetricThreshold": "tma_info_memory_useless_hwpf > 0.15" + "MetricThreshold": "tma_info_memory_prefetches_useless_hwpf > 0.15" }, { "BriefDescription": "Average Latency for L2 cache miss demand Loads", diff --git a/MTL/metrics/meteorlake_metrics_redwoodcove_core.json b/MTL/metrics/meteorlake_metrics_redwoodcove_core.json index 3a488b7b..525982bd 100644 --- a/MTL/metrics/meteorlake_metrics_redwoodcove_core.json +++ b/MTL/metrics/meteorlake_metrics_redwoodcove_core.json @@ -2,7 +2,7 @@ "Header": { "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.", "Info": "Performance Monitoring Metrics for Intel(R) Core(TM) processors based on Meteor Lake performance hybrid architecture0", - "DatePublished": "11/18/2024", + "DatePublished": "12/02/2024", "Version": "1.0", "Legend": "", "TmaVersion": "5.01", @@ -368,7 +368,7 @@ } ], "Formula": "100 * ( ( a / ( a + b + c + d ) - e / ( f ) ) - ( 1 - ( 10 * ( g / ( f ) ) * ( max( ( h / ( a + b + c + d ) ) * ( 1 - i / ( j - k ) ) , 0.0001 ) ) / ( h / ( a + b + c + d ) ) ) ) * ( ( l / ( a + b + c + d ) - e / ( f ) ) ) * ( ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * m / ( n ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) - ( ( 1 - w / x ) * ( ( ( l / ( a + b + c + d ) - e / ( f ) ) ) * ( ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) * ( ( ( 1 - ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) ) * m / ( n ) ) + ( ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * m / ( n ) ) * ( max( ( h / ( a + b + c + d ) ) * ( 1 - i / ( j - k ) ) , 0.0001 ) ) / ( h / ( a + b + c + d ) ) ) / ( ( ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * m / ( n ) ) + ( ( 1 - ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) ) * m / ( n ) ) + ( q / ( n ) ) ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) + ( max( 0 , ( a / ( a + b + c + d ) - e / ( f ) ) - ( ( l / ( a + b + c + d ) - e / ( f ) ) ) ) ) * ( max( y , x / ( s / t ) ) / ( z if smt_on else ( n ) ) / 2 ) / ( ( ( a_a - a_b ) / ( z if smt_on else ( n ) ) / 2 ) + ( ( a_c - a_d ) / ( z if smt_on else ( n ) ) / 2 ) + ( ( a_e - a_f ) / ( z if smt_on else ( n ) ) / 2 ) + ( max( y , x / ( s / t ) ) / ( z if smt_on else ( n ) ) / 2 ) ) ) ) ) - ( 100 * ( ( l / ( a + b + c + d ) - e / ( f ) ) ) * ( ( p / ( n ) ) + ( o / ( n ) ) + ( q / ( n ) ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) )", - "BaseFormula": " 100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - inst_retired.rep_iteration / uops_retired.ms:c1 ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) ) ) - tma_big_code", + "BaseFormula": " 100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - inst_retired.rep_iteration / uops_retired.ms:c1 ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) ) ) - tma_bottleneck_big_code", "Category": "TMA", "CountDomain": "Scaled_Slots", "Threshold": { @@ -1998,7 +1998,7 @@ } ], "Formula": "100 - ( ( 100 * ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( h / ( i ) ) + ( j / ( i ) ) + ( k / ( i ) ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) ) + ( 100 * ( ( b / ( b + c + d + e ) - f / ( g ) ) - ( 1 - ( 10 * ( r / ( g ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) ) * ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) - ( ( 1 - w / x ) * ( ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) * ( ( ( 1 - ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * l / ( i ) ) + ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) / ( ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) + ( ( 1 - ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * l / ( i ) ) + ( k / ( i ) ) ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) + ( max( 0 , ( b / ( b + c + d + e ) - f / ( g ) ) - ( ( a / ( b + c + d + e ) - f / ( g ) ) ) ) ) * ( max( y , x / ( n / o ) ) / ( z if smt_on else ( i ) ) / 2 ) / ( ( ( a_a - a_b ) / ( z if smt_on else ( i ) ) / 2 ) + ( ( a_c - a_d ) / ( z if smt_on else ( i ) ) / 2 ) + ( ( a_e - a_f ) / ( z if smt_on else ( i ) ) / 2 ) + ( max( y , x / ( n / o ) ) / ( z if smt_on else ( i ) ) / 2 ) ) ) ) ) - ( 100 * ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( h / ( i ) ) + ( j / ( i ) ) + ( k / ( i ) ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) ) ) + ( 100 * ( 1 - ( 10 * ( r / ( g ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) ) * ( ( s / ( b + c + d + e ) ) + ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) ) ) + ( 100 * ( ( ( a_g / ( b + c + d + e ) ) * ( ( ( a_h / ( i ) ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_h ) / ( i ) ) + ( ( a_h / ( i ) ) ) + ( a_l / ( i ) ) ) ) * ( ( ( min( i , a_m ) ) / ( i ) ) / ( ( ( min( i , a_m ) ) / ( i ) ) + ( ( min( i , a_n ) ) / ( i ) - ( ( min( i , a_m ) ) / ( i ) ) ) ) ) ) + ( ( a_g / ( b + c + d + e ) ) * ( ( ( a_k - a_h ) / ( i ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_h ) / ( i ) ) + ( ( a_h / ( i ) ) ) + ( a_l / ( i ) ) ) ) * ( ( ( a_o + a_p ) / ( i ) ) / ( ( ( ( min( ( a_q * a_r ) , a_q * ( 27 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_r > = 0 ) else ( a_q * ( 27 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) + ( min( ( a_v * a_w ) , a_v * ( 28 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_w > = 0 ) else ( a_v * ( 28 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( a_x / ( a_x + a_y ) ) ) * ( 1 + ( a_z / b_a ) / 2 ) / ( i ) ) + ( ( ( min( ( b_b * b_c ) , b_b * ( 27 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( b_c > = 0 ) else ( b_b * ( 27 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) + ( min( ( a_v * a_w ) , a_v * ( 27 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_w > = 0 ) else ( a_v * ( 27 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( 1 - ( a_x / ( a_x + a_y ) ) ) ) * ( 1 + ( a_z / b_a ) / 2 ) / ( i ) ) + ( ( min( ( b_d * b_e ) , b_d * ( 12 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( b_e > = 0 ) else ( b_d * ( 12 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( 1 + ( a_z / b_a ) / 2 ) / ( i ) ) + ( ( a_o + a_p ) / ( i ) ) ) ) ) + ( ( a_g / ( b + c + d + e ) ) * ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_h ) / ( i ) ) + ( ( a_h / ( i ) ) ) + ( a_l / ( i ) ) ) ) * ( ( b_f / ( i ) ) / ( ( ( min( ( b_g * b_h ) , b_g * ( 7 ) ) if ( b_h > = 0 ) else ( b_g * ( 7 ) ) ) / ( i ) + ( b_i / ( i ) ) ) + ( 13 * b_j / ( i ) ) + ( min( 2 * ( b_k - a_z - b_a ) * dependentloadsweight / 100 , max( b_m - b_n , 0 ) ) / ( i ) ) + ( ( b_o * b_p ) / ( i ) ) + ( ( min( ( b_q * b_r ) , b_q * ( b_s / b_t ) ) if ( b_r > = 0 ) else ( b_q * ( b_s / b_t ) ) ) / ( i ) ) + ( b_f / ( i ) ) ) ) ) ) ) + ( 100 * ( ( ( a_g / ( b + c + d + e ) ) * ( ( ( a_h / ( i ) ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_h ) / ( i ) ) + ( ( a_h / ( i ) ) ) + ( a_l / ( i ) ) ) ) * ( ( ( min( i , a_n ) ) / ( i ) - ( ( min( i , a_m ) ) / ( i ) ) ) / ( ( ( min( i , a_m ) ) / ( i ) ) + ( ( min( i , a_n ) ) / ( i ) - ( ( min( i , a_m ) ) / ( i ) ) ) ) ) ) + ( ( a_g / ( b + c + d + e ) ) * ( ( ( a_k - a_h ) / ( i ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_h ) / ( i ) ) + ( ( a_h / ( i ) ) ) + ( a_l / ( i ) ) ) ) * ( ( ( min( ( b_d * b_e ) , b_d * ( 12 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( b_e > = 0 ) else ( b_d * ( 12 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( 1 + ( a_z / b_a ) / 2 ) / ( i ) ) / ( ( ( ( min( ( a_q * a_r ) , a_q * ( 27 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_r > = 0 ) else ( a_q * ( 27 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) + ( min( ( a_v * a_w ) , a_v * ( 28 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_w > = 0 ) else ( a_v * ( 28 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( a_x / ( a_x + a_y ) ) ) * ( 1 + ( a_z / b_a ) / 2 ) / ( i ) ) + ( ( ( min( ( b_b * b_c ) , b_b * ( 27 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( b_c > = 0 ) else ( b_b * ( 27 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) + ( min( ( a_v * a_w ) , a_v * ( 27 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_w > = 0 ) else ( a_v * ( 27 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( 1 - ( a_x / ( a_x + a_y ) ) ) ) * ( 1 + ( a_z / b_a ) / 2 ) / ( i ) ) + ( ( min( ( b_d * b_e ) , b_d * ( 12 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( b_e > = 0 ) else ( b_d * ( 12 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( 1 + ( a_z / b_a ) / 2 ) / ( i ) ) + ( ( a_o + a_p ) / ( i ) ) ) ) ) + ( ( a_g / ( b + c + d + e ) ) * ( ( a_j - a_k ) / ( i ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_h ) / ( i ) ) + ( ( a_h / ( i ) ) ) + ( a_l / ( i ) ) ) ) + ( ( a_g / ( b + c + d + e ) ) * ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_h ) / ( i ) ) + ( ( a_h / ( i ) ) ) + ( a_l / ( i ) ) ) ) * ( ( min( 2 * ( b_k - a_z - b_a ) * dependentloadsweight / 100 , max( b_m - b_n , 0 ) ) / ( i ) ) / ( ( ( min( ( b_g * b_h ) , b_g * ( 7 ) ) if ( b_h > = 0 ) else ( b_g * ( 7 ) ) ) / ( i ) + ( b_i / ( i ) ) ) + ( 13 * b_j / ( i ) ) + ( min( 2 * ( b_k - a_z - b_a ) * dependentloadsweight / 100 , max( b_m - b_n , 0 ) ) / ( i ) ) + ( ( b_o * b_p ) / ( i ) ) + ( ( min( ( b_q * b_r ) , b_q * ( b_s / b_t ) ) if ( b_r > = 0 ) else ( b_q * ( b_s / b_t ) ) ) / ( i ) ) + ( b_f / ( i ) ) ) ) ) + ( ( a_g / ( b + c + d + e ) ) * ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_h ) / ( i ) ) + ( ( a_h / ( i ) ) ) + ( a_l / ( i ) ) ) ) * ( ( ( b_o * b_p ) / ( i ) ) / ( ( ( min( ( b_g * b_h ) , b_g * ( 7 ) ) if ( b_h > = 0 ) else ( b_g * ( 7 ) ) ) / ( i ) + ( b_i / ( i ) ) ) + ( 13 * b_j / ( i ) ) + ( min( 2 * ( b_k - a_z - b_a ) * dependentloadsweight / 100 , max( b_m - b_n , 0 ) ) / ( i ) ) + ( ( b_o * b_p ) / ( i ) ) + ( ( min( ( b_q * b_r ) , b_q * ( b_s / b_t ) ) if ( b_r > = 0 ) else ( b_q * ( b_s / b_t ) ) ) / ( i ) ) + ( b_f / ( i ) ) ) ) ) + ( ( a_g / ( b + c + d + e ) ) * ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_h ) / ( i ) ) + ( ( a_h / ( i ) ) ) + ( a_l / ( i ) ) ) ) * ( ( ( min( ( b_q * b_r ) , b_q * ( b_s / b_t ) ) if ( b_r > = 0 ) else ( b_q * ( b_s / b_t ) ) ) / ( i ) ) / ( ( ( min( ( b_g * b_h ) , b_g * ( 7 ) ) if ( b_h > = 0 ) else ( b_g * ( 7 ) ) ) / ( i ) + ( b_i / ( i ) ) ) + ( 13 * b_j / ( i ) ) + ( min( 2 * ( b_k - a_z - b_a ) * dependentloadsweight / 100 , max( b_m - b_n , 0 ) ) / ( i ) ) + ( ( b_o * b_p ) / ( i ) ) + ( ( min( ( b_q * b_r ) , b_q * ( b_s / b_t ) ) if ( b_r > = 0 ) else ( b_q * ( b_s / b_t ) ) ) / ( i ) ) + ( b_f / ( i ) ) ) ) ) + ( ( a_g / ( b + c + d + e ) ) * ( ( a_l / ( i ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_h ) / ( i ) ) + ( ( a_h / ( i ) ) ) + ( a_l / ( i ) ) ) ) * ( ( ( min( ( b_u * b_v ) , b_u * 1 ) if ( b_v > = 0 ) else ( b_u * 1 ) ) / ( i ) ) / ( ( ( ( b_w * ( 10 ) * ( 1 - ( b_o / b_x ) ) ) + ( 1 - ( b_o / b_x ) ) * ( min( i , b_y ) ) ) / ( i ) ) + ( ( 28 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_z / ( i ) ) + ( ( min( ( b_u * b_v ) , b_u * 1 ) if ( b_v > = 0 ) else ( b_u * 1 ) ) / ( i ) ) + ( 9 * c_a / ( i ) ) + ( ( min( ( c_b * c_c ) , c_b * ( 7 ) ) if ( c_c > = 0 ) else ( c_b * ( 7 ) ) ) / ( i ) + ( c_d / ( z if smt_on else ( i ) ) ) ) ) ) ) + ( ( a_g / ( b + c + d + e ) ) * ( ( a_l / ( i ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_h ) / ( i ) ) + ( ( a_h / ( i ) ) ) + ( a_l / ( i ) ) ) ) * ( ( ( ( b_w * ( 10 ) * ( 1 - ( b_o / b_x ) ) ) + ( 1 - ( b_o / b_x ) ) * ( min( i , b_y ) ) ) / ( i ) ) / ( ( ( ( b_w * ( 10 ) * ( 1 - ( b_o / b_x ) ) ) + ( 1 - ( b_o / b_x ) ) * ( min( i , b_y ) ) ) / ( i ) ) + ( ( 28 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_z / ( i ) ) + ( ( min( ( b_u * b_v ) , b_u * 1 ) if ( b_v > = 0 ) else ( b_u * 1 ) ) / ( i ) ) + ( 9 * c_a / ( i ) ) + ( ( min( ( c_b * c_c ) , c_b * ( 7 ) ) if ( c_c > = 0 ) else ( c_b * ( 7 ) ) ) / ( i ) + ( c_d / ( z if smt_on else ( i ) ) ) ) ) ) ) ) ) + ( 100 * ( ( ( a_g / ( b + c + d + e ) ) * ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_h ) / ( i ) ) + ( ( a_h / ( i ) ) ) + ( a_l / ( i ) ) ) ) * ( ( ( min( ( b_g * b_h ) , b_g * ( 7 ) ) if ( b_h > = 0 ) else ( b_g * ( 7 ) ) ) / ( i ) + ( b_i / ( i ) ) ) / ( ( ( min( ( b_g * b_h ) , b_g * ( 7 ) ) if ( b_h > = 0 ) else ( b_g * ( 7 ) ) ) / ( i ) + ( b_i / ( i ) ) ) + ( 13 * b_j / ( i ) ) + ( min( 2 * ( b_k - a_z - b_a ) * dependentloadsweight / 100 , max( b_m - b_n , 0 ) ) / ( i ) ) + ( ( b_o * b_p ) / ( i ) ) + ( ( min( ( b_q * b_r ) , b_q * ( b_s / b_t ) ) if ( b_r > = 0 ) else ( b_q * ( b_s / b_t ) ) ) / ( i ) ) + ( b_f / ( i ) ) ) ) ) + ( ( a_g / ( b + c + d + e ) ) * ( ( a_l / ( i ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_h ) / ( i ) ) + ( ( a_h / ( i ) ) ) + ( a_l / ( i ) ) ) ) * ( ( ( min( ( c_b * c_c ) , c_b * ( 7 ) ) if ( c_c > = 0 ) else ( c_b * ( 7 ) ) ) / ( i ) + ( c_d / ( z if smt_on else ( i ) ) ) ) / ( ( ( ( b_w * ( 10 ) * ( 1 - ( b_o / b_x ) ) ) + ( 1 - ( b_o / b_x ) ) * ( min( i , b_y ) ) ) / ( i ) ) + ( ( 28 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_z / ( i ) ) + ( ( min( ( b_u * b_v ) , b_u * 1 ) if ( b_v > = 0 ) else ( b_u * 1 ) ) / ( i ) ) + ( 9 * c_a / ( i ) ) + ( ( min( ( c_b * c_c ) , c_b * ( 7 ) ) if ( c_c > = 0 ) else ( c_b * ( 7 ) ) ) / ( i ) + ( c_d / ( z if smt_on else ( i ) ) ) ) ) ) ) ) ) + ( 100 * ( ( a_g / ( b + c + d + e ) ) * ( ( ( ( a_k - a_h ) / ( i ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_h ) / ( i ) ) + ( ( a_h / ( i ) ) ) + ( a_l / ( i ) ) ) ) * ( ( ( ( min( ( a_q * a_r ) , a_q * ( 27 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_r > = 0 ) else ( a_q * ( 27 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) + ( min( ( a_v * a_w ) , a_v * ( 28 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_w > = 0 ) else ( a_v * ( 28 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( a_x / ( a_x + a_y ) ) ) * ( 1 + ( a_z / b_a ) / 2 ) / ( i ) ) + ( ( ( min( ( b_b * b_c ) , b_b * ( 27 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( b_c > = 0 ) else ( b_b * ( 27 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) + ( min( ( a_v * a_w ) , a_v * ( 27 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_w > = 0 ) else ( a_v * ( 27 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( 1 - ( a_x / ( a_x + a_y ) ) ) ) * ( 1 + ( a_z / b_a ) / 2 ) / ( i ) ) ) / ( ( ( ( min( ( a_q * a_r ) , a_q * ( 27 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_r > = 0 ) else ( a_q * ( 27 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) + ( min( ( a_v * a_w ) , a_v * ( 28 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_w > = 0 ) else ( a_v * ( 28 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( a_x / ( a_x + a_y ) ) ) * ( 1 + ( a_z / b_a ) / 2 ) / ( i ) ) + ( ( ( min( ( b_b * b_c ) , b_b * ( 27 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( b_c > = 0 ) else ( b_b * ( 27 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) + ( min( ( a_v * a_w ) , a_v * ( 27 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_w > = 0 ) else ( a_v * ( 27 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( 1 - ( a_x / ( a_x + a_y ) ) ) ) * ( 1 + ( a_z / b_a ) / 2 ) / ( i ) ) + ( ( min( ( b_d * b_e ) , b_d * ( 12 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( b_e > = 0 ) else ( b_d * ( 12 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( 1 + ( a_z / b_a ) / 2 ) / ( i ) ) + ( ( a_o + a_p ) / ( i ) ) ) + ( ( a_l / ( i ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_h ) / ( i ) ) + ( ( a_h / ( i ) ) ) + ( a_l / ( i ) ) ) ) * ( ( 28 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_z / ( i ) ) / ( ( ( ( ( b_w * ( 10 ) * ( 1 - ( b_o / b_x ) ) ) + ( 1 - ( b_o / b_x ) ) * ( min( i , b_y ) ) ) / ( i ) ) + ( ( 28 * ( ( ( i ) / a_s ) * a_t / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_z / ( i ) ) + ( ( min( ( b_u * b_v ) , b_u * 1 ) if ( b_v > = 0 ) else ( b_u * 1 ) ) / ( i ) ) + ( 9 * c_a / ( i ) ) + ( ( min( ( c_b * c_c ) , c_b * ( 7 ) ) if ( c_c > = 0 ) else ( c_b * ( 7 ) ) ) / ( i ) + ( c_d / ( z if smt_on else ( i ) ) ) ) ) - ( ( ( b_w * ( 10 ) * ( 1 - ( b_o / b_x ) ) ) + ( 1 - ( b_o / b_x ) ) * ( min( i , b_y ) ) ) / ( i ) ) ) ) + ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - c_e / v ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - c_e / v ) , 0.0001 ) ) ) ) ) ) + ( 100 * ( ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_g / ( b + c + d + e ) ) ) ) * ( c_f / ( i ) ) / ( ( c_f / ( i ) ) + ( c_g / ( i ) + ( c_h / ( i ) ) ) + ( ( ( max( c_i - c_g , 0 ) / ( i ) ) * ( i ) + ( c_j + ( d / ( b + c + d + e ) ) * c_k ) ) / ( i ) if ( c_f < ( c_l - a_i ) ) else ( c_j + ( d / ( b + c + d + e ) ) * c_k ) / ( i ) ) ) ) + ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_g / ( b + c + d + e ) ) ) ) * ( ( ( ( max( c_i - c_g , 0 ) / ( i ) ) * ( i ) + ( c_j + ( d / ( b + c + d + e ) ) * c_k ) ) / ( i ) if ( c_f < ( c_l - a_i ) ) else ( c_j + ( d / ( b + c + d + e ) ) * c_k ) / ( i ) ) / ( ( c_f / ( i ) ) + ( c_g / ( i ) + ( c_h / ( i ) ) ) + ( ( ( max( c_i - c_g , 0 ) / ( i ) ) * ( i ) + ( c_j + ( d / ( b + c + d + e ) ) * c_k ) ) / ( i ) if ( c_f < ( c_l - a_i ) ) else ( c_j + ( d / ( b + c + d + e ) ) * c_k ) / ( i ) ) ) ) * ( ( c_m / ( i ) ) / ( ( max( c_i - c_g , 0 ) / ( i ) ) + ( c_j / ( i ) ) + ( c_n / ( i ) ) + ( c_m / ( i ) ) ) ) ) ) ) + ( 100 * ( ( ( 1 - w / x ) * ( ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) * ( ( ( 1 - ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * l / ( i ) ) + ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) / ( ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) + ( ( 1 - ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * l / ( i ) ) + ( k / ( i ) ) ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) + ( max( 0 , ( b / ( b + c + d + e ) - f / ( g ) ) - ( ( a / ( b + c + d + e ) - f / ( g ) ) ) ) ) * ( max( y , x / ( n / o ) ) / ( z if smt_on else ( i ) ) / 2 ) / ( ( ( a_a - a_b ) / ( z if smt_on else ( i ) ) / 2 ) + ( ( a_c - a_d ) / ( z if smt_on else ( i ) ) / 2 ) + ( ( a_e - a_f ) / ( z if smt_on else ( i ) ) / 2 ) + ( max( y , x / ( n / o ) ) / ( z if smt_on else ( i ) ) / 2 ) ) ) ) + ( 10 * ( r / ( g ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) * ( s / ( b + c + d + e ) ) + ( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - c_e / v ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - c_e / v ) , 0.0001 ) ) ) ) + ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_g / ( b + c + d + e ) ) ) ) * ( ( c_g / ( i ) + ( c_h / ( i ) ) ) + c_o / ( i ) * ( max( c_i - c_g , 0 ) / ( i ) ) ) / ( ( c_f / ( i ) ) + ( c_g / ( i ) + ( c_h / ( i ) ) ) + ( ( ( max( c_i - c_g , 0 ) / ( i ) ) * ( i ) + ( c_j + ( d / ( b + c + d + e ) ) * c_k ) ) / ( i ) if ( c_f < ( c_l - a_i ) ) else ( c_j + ( d / ( b + c + d + e ) ) * c_k ) / ( i ) ) ) ) + ( ( ( ( r / ( g ) ) / ( ( max( 0 , ( c_p / ( b + c + d + e ) ) - ( r / ( g ) ) ) ) + ( r / ( g ) ) ) ) * ( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * c_q / ( g ) ) / ( r / ( g ) ) ) ) * ( c_p / ( b + c + d + e ) ) ) ) ) + ( 100 * ( ( c_r + 2 * c_s + c_t ) / ( g ) ) ) + ( 100 * ( ( d / ( b + c + d + e ) ) - ( ( c_r + 2 * c_s + c_t ) / ( g ) ) - ( ( ( ( r / ( g ) ) / ( ( max( 0 , ( c_p / ( b + c + d + e ) ) - ( r / ( g ) ) ) ) + ( r / ( g ) ) ) ) * ( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * c_q / ( g ) ) / ( r / ( g ) ) ) ) * ( c_p / ( b + c + d + e ) ) ) ) ) )", - "BaseFormula": " 100 - ( tma_big_code + tma_instruction_fetch_bw + tma_mispredictions + tma_cache_memory_bandwidth + tma_cache_memory_latency + tma_memory_data_tlbs + tma_memory_synchronization + tma_compute_bound_est + tma_irregular_overhead + tma_branching_overhead + tma_useful_work )", + "BaseFormula": " 100 - ( tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottleneck_mispredictions + tma_bottleneck_cache_memory_bandwidth + tma_bottleneck_cache_memory_latency + tma_bottleneck_memory_data_tlbs + tma_bottleneck_memory_synchronization + tma_bottleneck_compute_bound_est + tma_bottleneck_irregular_overhead + tma_bottleneck_branching_overhead + tma_bottleneck_useful_work )", "Category": "TMA", "CountDomain": "Scaled_Slots", "Threshold": { @@ -8775,11 +8775,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_Core_Bound_Likely" + "Value": "metric_TMA_Info_Botlnk_L0_Core_Bound_Likely" } ], "Formula": "a > 0.5", - "BaseFormula": "metric_TMA_Info_Botlnk_Core_Bound_Likely > 0.5", + "BaseFormula": "metric_TMA_Info_Botlnk_L0_Core_Bound_Likely > 0.5", "ThresholdIssues": "" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -10201,11 +10201,11 @@ }, { "Alias": "b", - "Value": "IPC" + "Value": "metric_TMA_Info_Thread_IPC" } ], "Formula": "a < 0.7 & b / 6 > 0.35", - "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & IPC / 6 > 0.35", + "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & metric_TMA_Info_Thread_IPC / 6 > 0.35", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -10702,11 +10702,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_DSB_Misses" + "Value": "metric_TMA_Info_Botlnk_L2_DSB_Misses" } ], "Formula": "a > 10", - "BaseFormula": "metric_TMA_Info_Botlnk_DSB_Misses > 10", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_DSB_Misses > 10", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -10815,11 +10815,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_DSB_Bandwidth" + "Value": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth" } ], "Formula": "a > 10", - "BaseFormula": "metric_TMA_Info_Botlnk_DSB_Bandwidth > 10", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth > 10", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -10911,11 +10911,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_IC_Misses" + "Value": "metric_TMA_Info_Botlnk_L2_IC_Misses" } ], "Formula": "a > 5", - "BaseFormula": "metric_TMA_Info_Botlnk_IC_Misses > 5", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_IC_Misses > 5", "ThresholdIssues": "$issueFL" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -11200,7 +11200,7 @@ ], "Constants": [], "Formula": "( 100 * ( 1 - ( 10 * ( a / ( b ) ) * ( max( ( c / ( d + e + f + g ) ) * ( 1 - h / ( i - j ) ) , 0.0001 ) ) / ( c / ( d + e + f + g ) ) ) ) * ( ( c / ( d + e + f + g ) ) + ( ( k / ( d + e + f + g ) - l / ( b ) ) ) * ( ( ( c / ( d + e + f + g ) ) / ( max( 1 - ( ( d / ( d + e + f + g ) - l / ( b ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) ) * m / ( n ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) ) ) * ( b ) / ( 6 ) / h / 100", - "BaseFormula": " tma_mispredictions * tma_info_thread_slots / ( 6 ) / br_misp_retired.all_branches / 100", + "BaseFormula": " tma_bottleneck_mispredictions * tma_info_thread_slots / ( 6 ) / br_misp_retired.all_branches / 100", "Category": "TMA", "CountDomain": "Core_Metric", "Threshold": { @@ -11958,11 +11958,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Memory_Page_Walks_Utilization" + "Value": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization" } ], "Formula": "a > 0.5", - "BaseFormula": "metric_TMA_Info_Memory_Page_Walks_Utilization > 0.5", + "BaseFormula": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization > 0.5", "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", @@ -12088,11 +12088,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Memory_Load_STLB_Miss_Ret" + "Value": "metric_TMA_Info_Memory_TLB_Load_STLB_Miss_Ret" } ], "Formula": "a > 0.05", - "BaseFormula": "metric_TMA_Info_Memory_Load_STLB_Miss_Ret > 0.05", + "BaseFormula": "metric_TMA_Info_Memory_TLB_Load_STLB_Miss_Ret > 0.05", "ThresholdIssues": "" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -12128,11 +12128,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Memory_Store_STLB_Miss_Ret" + "Value": "metric_TMA_Info_Memory_TLB_Store_STLB_Miss_Ret" } ], "Formula": "a > 0.05", - "BaseFormula": "metric_TMA_Info_Memory_Store_STLB_Miss_Ret > 0.05", + "BaseFormula": "metric_TMA_Info_Memory_TLB_Store_STLB_Miss_Ret > 0.05", "ThresholdIssues": "" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -12292,11 +12292,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Memory_Useless_HWPF" + "Value": "metric_TMA_Info_Memory_Prefetches_Useless_HWPF" } ], "Formula": "a > 0.15", - "BaseFormula": "metric_TMA_Info_Memory_Useless_HWPF > 0.15", + "BaseFormula": "metric_TMA_Info_Memory_Prefetches_Useless_HWPF > 0.15", "ThresholdIssues": "" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -12863,6 +12863,38 @@ "MetricGroup": "Power;SoC", "LocateWith": "" }, + { + "MetricName": "Info_System_Time", + "LegacyName": "metric_TMA_Info_System_Time", + "Level": 1, + "BriefDescription": "Run duration time in seconds", + "UnitOfMeasure": "", + "Events": [], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( durationtimeinmilliseconds / 1000 )", + "BaseFormula": " duration_time", + "Category": "TMA", + "CountDomain": "Seconds", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_System_Time" + } + ], + "Formula": "a < 1", + "BaseFormula": "metric_TMA_Info_System_Time < 1", + "ThresholdIssues": "" + }, + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Summary", + "LocateWith": "" + }, { "MetricName": "Info_System_MUX", "LegacyName": "metric_TMA_Info_System_MUX", diff --git a/MTL/metrics/perf/meteorlake_metrics_redwoodcove_core_perf.json b/MTL/metrics/perf/meteorlake_metrics_redwoodcove_core_perf.json index 12820aa3..ebceaa21 100644 --- a/MTL/metrics/perf/meteorlake_metrics_redwoodcove_core_perf.json +++ b/MTL/metrics/perf/meteorlake_metrics_redwoodcove_core_perf.json @@ -20,7 +20,7 @@ }, { "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the back-end)", - "MetricExpr": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\\,cmask\\=0x1@ ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) ) ) - tma_big_code", + "MetricExpr": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\\,cmask\\=0x1@ ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) ) ) - tma_bottleneck_big_code", "MetricGroup": "BvFB;Fed;FetchBW;Frontend;TopdownL1;tma_L1_group;Default;Scaled_Slots", "MetricName": "tma_bottleneck_instruction_fetch_bw", "MetricThreshold": "tma_bottleneck_instruction_fetch_bw > 20", @@ -89,7 +89,7 @@ }, { "BriefDescription": "Total pipeline cost of remaining bottlenecks in the back-end", - "MetricExpr": "100 - ( tma_big_code + tma_instruction_fetch_bw + tma_mispredictions + tma_cache_memory_bandwidth + tma_cache_memory_latency + tma_memory_data_tlbs + tma_memory_synchronization + tma_compute_bound_est + tma_irregular_overhead + tma_branching_overhead + tma_useful_work )", + "MetricExpr": "100 - ( tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottleneck_mispredictions + tma_bottleneck_cache_memory_bandwidth + tma_bottleneck_cache_memory_latency + tma_bottleneck_memory_data_tlbs + tma_bottleneck_memory_synchronization + tma_bottleneck_compute_bound_est + tma_bottleneck_irregular_overhead + tma_bottleneck_branching_overhead + tma_bottleneck_useful_work )", "MetricGroup": "BvOB;Cor;Offcore;TopdownL1;tma_L1_group;Default;Scaled_Slots", "MetricName": "tma_bottleneck_other_bottlenecks", "MetricThreshold": "tma_bottleneck_other_bottlenecks > 20", @@ -141,7 +141,7 @@ { "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses", "MetricExpr": "ICACHE_DATA.STALLS / tma_info_thread_clks", - "MetricGroup": "BigFootprint;BvBC;FetchLat;IcMiss;TopdownL3;tma_L3_group;Clocks", + "MetricGroup": "BigFootprint;BvBC;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group;Clocks", "MetricName": "tma_icache_misses", "ScaleUnit": "100%", "MetricThreshold": "tma_icache_misses > 0.05 & tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", @@ -207,7 +207,7 @@ { "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", "MetricExpr": "INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_thread_clks + tma_unknown_branches", - "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;Clocks;tma_overlap", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;Clocks;tma_overlap", "MetricName": "tma_branch_resteers", "ScaleUnit": "100%", "MetricThreshold": "tma_branch_resteers > 0.05 & tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", @@ -243,7 +243,7 @@ { "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)", "MetricExpr": "( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / tma_info_thread_clks", - "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;Clocks_Estimated;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO", + "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;Clocks_Estimated;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO", "MetricName": "tma_ms_switches", "ScaleUnit": "100%", "MetricThreshold": "tma_ms_switches > 0.05 & tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", @@ -261,7 +261,7 @@ { "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines", "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / tma_info_thread_clks", - "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;Clocks;tma_issueFB", + "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;Clocks;tma_issueFB", "MetricName": "tma_dsb_switches", "ScaleUnit": "100%", "MetricThreshold": "tma_dsb_switches > 0.05 & tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", @@ -281,7 +281,7 @@ { "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)", "MetricExpr": "( IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK ) / tma_info_core_core_clks / 2", - "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;Slots_Estimated", + "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group;Slots_Estimated", "MetricName": "tma_mite", "ScaleUnit": "100%", "MetricThreshold": "tma_mite > 0.1 & tma_fetch_bandwidth > 0.2", @@ -299,7 +299,7 @@ { "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline", "MetricExpr": "( IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK ) / tma_info_core_core_clks / 2", - "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;Slots_Estimated", + "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group;Slots_Estimated", "MetricName": "tma_dsb", "ScaleUnit": "100%", "MetricThreshold": "tma_dsb > 0.15 & tma_fetch_bandwidth > 0.2", @@ -387,7 +387,7 @@ { "BriefDescription": "This metric estimates fraction of slots the CPU was stalled due to other cases of misprediction (non-retired x86 branches or other types)", "MetricExpr": "max( tma_branch_mispredicts * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 )", - "MetricGroup": "BvIO;BrMispredicts;TopdownL3;tma_L3_group;Slots", + "MetricGroup": "BvIO;BrMispredicts;TopdownL3;tma_L3_group;tma_branch_mispredicts_group;Slots", "MetricName": "tma_other_mispredicts", "ScaleUnit": "100%", "MetricThreshold": "tma_other_mispredicts > 0.05 & tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15" @@ -406,7 +406,7 @@ { "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Nukes (Machine Clears) not related to memory ordering", "MetricExpr": "max( tma_machine_clears * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 )", - "MetricGroup": "BvIO;Machine_Clears;TopdownL3;tma_L3_group;Slots", + "MetricGroup": "BvIO;Machine_Clears;TopdownL3;tma_L3_group;tma_machine_clears_group;Slots", "MetricName": "tma_other_nukes", "ScaleUnit": "100%", "MetricThreshold": "tma_other_nukes > 0.05 & tma_machine_clears > 0.1 & tma_bad_speculation > 0.15" @@ -425,7 +425,7 @@ { "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", "MetricExpr": "( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( 0 * slots )", - "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;Default;Slots", + "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group;Default;Slots", "MetricName": "tma_memory_bound", "ScaleUnit": "100%", "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", @@ -445,7 +445,7 @@ { "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", "MetricExpr": "( min( ( MEM_INST_RETIRED.STLB_HIT_LOADS * cpu_core@MEM_INST_RETIRED.STLB_HIT_LOADS@R ) , MEM_INST_RETIRED.STLB_HIT_LOADS * ( 7 ) ) if ( cpu_core@MEM_INST_RETIRED.STLB_HIT_LOADS@R >= 0 ) else ( MEM_INST_RETIRED.STLB_HIT_LOADS * ( 7 ) ) ) / tma_info_thread_clks + tma_load_stlb_miss", - "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;Clocks_Estimated;tma_issueTLB", + "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_l1_bound_group;Clocks_Estimated;tma_issueTLB", "MetricName": "tma_dtlb_load", "ScaleUnit": "100%", "MetricThreshold": "tma_dtlb_load > 0.1 & tma_l1_bound > 0.1 & tma_memory_bound > 0.2 & tma_backend_bound > 0.2", @@ -521,7 +521,7 @@ { "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary", "MetricExpr": "( min( ( MEM_INST_RETIRED.SPLIT_LOADS * cpu_core@MEM_INST_RETIRED.SPLIT_LOADS@R ) , MEM_INST_RETIRED.SPLIT_LOADS * tma_info_memory_load_miss_real_latency ) if ( cpu_core@MEM_INST_RETIRED.SPLIT_LOADS@R >= 0 ) else ( MEM_INST_RETIRED.SPLIT_LOADS * tma_info_memory_load_miss_real_latency ) ) / tma_info_thread_clks", - "MetricGroup": "TopdownL4;tma_L4_group;Clocks_Calculated", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group;Clocks_Calculated", "MetricName": "tma_split_loads", "ScaleUnit": "100%", "MetricThreshold": "tma_split_loads > 0.3", @@ -566,7 +566,7 @@ { "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses", "MetricExpr": "( ( min( ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS * cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS@R ) , MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS * ( 27 * tma_info_system_core_frequency ) - ( 3 * tma_info_system_core_frequency ) ) if ( cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS@R >= 0 ) else ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS * ( 27 * tma_info_system_core_frequency ) - ( 3 * tma_info_system_core_frequency ) ) ) + ( min( ( MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD@R ) , MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * ( 28 * tma_info_system_core_frequency ) - ( 3 * tma_info_system_core_frequency ) ) if ( cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD@R >= 0 ) else ( MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * ( 28 * tma_info_system_core_frequency ) - ( 3 * tma_info_system_core_frequency ) ) ) * ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / tma_info_thread_clks", - "MetricGroup": "BvMS;DataSharing;LockCont;Offcore;Snoop;TopdownL4;tma_L4_group;Clocks_Estimated;tma_issueSyncxn", + "MetricGroup": "BvMS;DataSharing;LockCont;Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group;Clocks_Estimated;tma_issueSyncxn", "MetricName": "tma_contested_accesses", "ScaleUnit": "100%", "MetricThreshold": "tma_contested_accesses > 0.05 & tma_l3_bound > 0.05 & tma_memory_bound > 0.2 & tma_backend_bound > 0.2", @@ -584,7 +584,7 @@ { "BriefDescription": "This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)", "MetricExpr": "( min( ( MEM_LOAD_RETIRED.L3_HIT * cpu_core@MEM_LOAD_RETIRED.L3_HIT@R ) , MEM_LOAD_RETIRED.L3_HIT * ( 12 * tma_info_system_core_frequency ) - ( 3 * tma_info_system_core_frequency ) ) if ( cpu_core@MEM_LOAD_RETIRED.L3_HIT@R >= 0 ) else ( MEM_LOAD_RETIRED.L3_HIT * ( 12 * tma_info_system_core_frequency ) - ( 3 * tma_info_system_core_frequency ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / tma_info_thread_clks", - "MetricGroup": "BvML;MemoryLat;TopdownL4;tma_L4_group;Clocks_Estimated;tma_issueLat;tma_overlap", + "MetricGroup": "BvML;MemoryLat;TopdownL4;tma_L4_group;tma_l3_bound_group;Clocks_Estimated;tma_issueLat;tma_overlap", "MetricName": "tma_l3_hit_latency", "ScaleUnit": "100%", "MetricThreshold": "tma_l3_hit_latency > 0.1 & tma_l3_bound > 0.05 & tma_memory_bound > 0.2 & tma_backend_bound > 0.2", @@ -638,7 +638,7 @@ { "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses", "MetricExpr": "( ( MEM_STORE_RETIRED.L2_HIT * ( 10 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / tma_info_thread_clks", - "MetricGroup": "BvML;LockCont;MemoryLat;Offcore;TopdownL4;tma_L4_group;Clocks_Estimated;tma_issueRFO;tma_issueSL;tma_overlap", + "MetricGroup": "BvML;LockCont;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group;Clocks_Estimated;tma_issueRFO;tma_issueSL;tma_overlap", "MetricName": "tma_store_latency", "ScaleUnit": "100%", "MetricThreshold": "tma_store_latency > 0.1 & tma_store_bound > 0.2 & tma_memory_bound > 0.2 & tma_backend_bound > 0.2", @@ -656,7 +656,7 @@ { "BriefDescription": "This metric represents rate of split store accesses", "MetricExpr": "( min( ( MEM_INST_RETIRED.SPLIT_STORES * cpu_core@MEM_INST_RETIRED.SPLIT_STORES@R ) , MEM_INST_RETIRED.SPLIT_STORES * 1 ) if ( cpu_core@MEM_INST_RETIRED.SPLIT_STORES@R >= 0 ) else ( MEM_INST_RETIRED.SPLIT_STORES * 1 ) ) / tma_info_thread_clks", - "MetricGroup": "TopdownL4;tma_L4_group;Core_Utilization;tma_issueSpSt", + "MetricGroup": "TopdownL4;tma_L4_group;tma_store_bound_group;Core_Utilization;tma_issueSpSt", "MetricName": "tma_split_stores", "ScaleUnit": "100%", "MetricThreshold": "tma_split_stores > 0.2 & tma_store_bound > 0.2 & tma_memory_bound > 0.2 & tma_backend_bound > 0.2", @@ -674,7 +674,7 @@ { "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses", "MetricExpr": "( min( ( MEM_INST_RETIRED.STLB_HIT_STORES * cpu_core@MEM_INST_RETIRED.STLB_HIT_STORES@R ) , MEM_INST_RETIRED.STLB_HIT_STORES * ( 7 ) ) if ( cpu_core@MEM_INST_RETIRED.STLB_HIT_STORES@R >= 0 ) else ( MEM_INST_RETIRED.STLB_HIT_STORES * ( 7 ) ) ) / tma_info_thread_clks + tma_store_stlb_miss", - "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;Clocks_Estimated;tma_issueTLB", + "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_store_bound_group;Clocks_Estimated;tma_issueTLB", "MetricName": "tma_dtlb_store", "ScaleUnit": "100%", "MetricThreshold": "tma_dtlb_store > 0.05 & tma_store_bound > 0.2 & tma_memory_bound > 0.2 & tma_backend_bound > 0.2", @@ -734,7 +734,7 @@ { "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active", "MetricExpr": "ARITH.DIV_ACTIVE / tma_info_thread_clks", - "MetricGroup": "BvCB;TopdownL3;tma_L3_group;Clocks", + "MetricGroup": "BvCB;TopdownL3;tma_L3_group;tma_core_bound_group;Clocks", "MetricName": "tma_divider", "ScaleUnit": "100%", "MetricThreshold": "tma_divider > 0.2 & tma_core_bound > 0.1 & tma_backend_bound > 0.2", @@ -768,7 +768,7 @@ { "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions", "MetricExpr": "CPU_CLK_UNHALTED.PAUSE / tma_info_thread_clks", - "MetricGroup": "TopdownL4;tma_L4_group;Clocks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_serializing_operation_group;Clocks", "MetricName": "tma_slow_pause", "ScaleUnit": "100%", "MetricThreshold": "tma_slow_pause > 0.05 & tma_serializing_operation > 0.1 & tma_core_bound > 0.1 & tma_backend_bound > 0.2", @@ -785,7 +785,7 @@ { "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due staying in C0.2 power-performance optimized state (Slower wakeup time; Larger power savings)", "MetricExpr": "CPU_CLK_UNHALTED.C02 / tma_info_thread_clks", - "MetricGroup": "C0Wait;TopdownL4;tma_L4_group;Clocks", + "MetricGroup": "C0Wait;TopdownL4;tma_L4_group;tma_serializing_operation_group;Clocks", "MetricName": "tma_c02_wait", "ScaleUnit": "100%", "MetricThreshold": "tma_c02_wait > 0.05 & tma_serializing_operation > 0.1 & tma_core_bound > 0.1 & tma_backend_bound > 0.2" @@ -801,7 +801,7 @@ { "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)", "MetricExpr": "( tma_ports_utilized_0 * tma_info_thread_clks + ( EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_3_PORTS_UTIL ) ) / tma_info_thread_clks if ( ARITH.DIV_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_3_PORTS_UTIL ) / tma_info_thread_clks", - "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;Clocks", + "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group;Clocks", "MetricName": "tma_ports_utilization", "ScaleUnit": "100%", "MetricThreshold": "tma_ports_utilization > 0.15 & tma_core_bound > 0.1 & tma_backend_bound > 0.2", @@ -819,7 +819,7 @@ { "BriefDescription": "This metric estimates penalty in terms of percentage of([SKL+] injected blend uops out of all Uops Issued , the Count Domain; [ADL+] cycles)", "MetricExpr": "160 * ASSISTS.SSE_AVX_MIX / tma_info_thread_clks", - "MetricGroup": "TopdownL5;tma_L5_group;Clocks;tma_issueMV", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_0_group;Clocks;tma_issueMV", "MetricName": "tma_mixing_vectors", "ScaleUnit": "100%", "MetricThreshold": "tma_mixing_vectors > 0.05", @@ -855,7 +855,7 @@ { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations", "MetricExpr": "( UOPS_DISPATCHED.PORT_0 + UOPS_DISPATCHED.PORT_1 + UOPS_DISPATCHED.PORT_5_11 + UOPS_DISPATCHED.PORT_6 ) / ( 5 * tma_info_core_core_clks )", - "MetricGroup": "TopdownL5;tma_L5_group;Core_Execution", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group;Core_Execution", "MetricName": "tma_alu_op_utilization", "ScaleUnit": "100%", "MetricThreshold": "tma_alu_op_utilization > 0.4" @@ -890,7 +890,7 @@ { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations", "MetricExpr": "UOPS_DISPATCHED.PORT_2_3_10 / ( 3 * tma_info_core_core_clks )", - "MetricGroup": "TopdownL5;tma_L5_group;Core_Execution", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group;Core_Execution", "MetricName": "tma_load_op_utilization", "ScaleUnit": "100%", "MetricThreshold": "tma_load_op_utilization > 0.6", @@ -930,7 +930,7 @@ { "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)", "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector", - "MetricGroup": "HPC;TopdownL3;tma_L3_group;Uops", + "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group;Uops", "MetricName": "tma_fp_arith", "ScaleUnit": "100%", "MetricThreshold": "tma_fp_arith > 0.2 & tma_light_operations > 0.6", @@ -966,7 +966,7 @@ { "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors", "MetricExpr": "( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE ) / ( tma_retiring * tma_info_thread_slots )", - "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;Uops;tma_issue2P", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;Uops;tma_issue2P", "MetricName": "tma_fp_vector_128b", "ScaleUnit": "100%", "MetricThreshold": "tma_fp_vector_128b > 0.1 & tma_fp_vector > 0.1 & tma_fp_arith > 0.2 & tma_light_operations > 0.6", @@ -984,7 +984,7 @@ { "BriefDescription": "This metric represents overall Integer (Int) select operations fraction the CPU has executed (retired)", "MetricExpr": "tma_int_vector_128b + tma_int_vector_256b", - "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;Uops", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group;Uops", "MetricName": "tma_int_operations", "ScaleUnit": "100%", "MetricThreshold": "tma_int_operations > 0.1 & tma_light_operations > 0.6", @@ -1019,7 +1019,7 @@ { "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions , where one uop can represent multiple contiguous instructions", "MetricExpr": "tma_light_operations * INST_RETIRED.MACRO_FUSED / ( tma_retiring * tma_info_thread_slots )", - "MetricGroup": "Branches;BvBO;Pipeline;TopdownL3;tma_L3_group;Slots", + "MetricGroup": "Branches;BvBO;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group;Slots", "MetricName": "tma_fused_instructions", "ScaleUnit": "100%", "MetricThreshold": "tma_fused_instructions > 0.1 & tma_light_operations > 0.6", @@ -1037,7 +1037,7 @@ { "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes", "MetricExpr": "max( 0 , tma_light_operations - ( tma_fp_arith + tma_int_operations + tma_memory_operations + tma_fused_instructions + tma_non_fused_branches ) )", - "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;Slots", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group;Slots", "MetricName": "tma_other_light_ops", "ScaleUnit": "100%", "MetricThreshold": "tma_other_light_ops > 0.3 & tma_light_operations > 0.6", @@ -1075,7 +1075,7 @@ { "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or more uops", "MetricExpr": "max( 0 , tma_heavy_operations - tma_microcode_sequencer )", - "MetricGroup": "TopdownL3;tma_L3_group;Slots;tma_issueD0", + "MetricGroup": "TopdownL3;tma_L3_group;tma_heavy_operations_group;Slots;tma_issueD0", "MetricName": "tma_few_uops_instructions", "ScaleUnit": "100%", "MetricThreshold": "tma_few_uops_instructions > 0.05 & tma_heavy_operations > 0.1", @@ -1093,7 +1093,7 @@ { "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists", "MetricExpr": "( ( 99 *3 + 63 + 30 ) / 5 ) * ASSISTS.ANY / tma_info_thread_slots", - "MetricGroup": "BvIO;TopdownL4;tma_L4_group;Slots_Estimated", + "MetricGroup": "BvIO;TopdownL4;tma_L4_group;tma_microcode_sequencer_group;Slots_Estimated", "MetricName": "tma_assists", "ScaleUnit": "100%", "MetricThreshold": "tma_assists > 0.1 & tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1", @@ -1128,7 +1128,7 @@ { "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction", "MetricExpr": "max( 0 , tma_microcode_sequencer - tma_assists )", - "MetricGroup": "TopdownL4;tma_L4_group;Slots", + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group;Slots", "MetricName": "tma_cisc", "ScaleUnit": "100%", "MetricThreshold": "tma_cisc > 0.1 & tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1", @@ -1139,7 +1139,7 @@ "MetricExpr": "100 * ( 1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1 ) if tma_info_system_smt_2t_utilization > 0.5 else 0", "MetricGroup": "Cor;SMT;Metric", "MetricName": "tma_info_botlnk_l0_core_bound_likely", - "MetricThreshold": "tma_info_botlnk_core_bound_likely > 0.5" + "MetricThreshold": "tma_info_botlnk_l0_core_bound_likely > 0.5" }, { "BriefDescription": "Instructions Per Cycle (per Logical Processor)", @@ -1182,7 +1182,7 @@ }, { "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor", - "MetricExpr": "tma_info_thread_slots / ( TOPDOWN.SLOTS / 2 ) if #SMT_on else 1", + "MetricExpr": "tma_info_thread_slots / ( slots / 2 ) if #SMT_on else 1", "MetricGroup": "SMT;TmaL1;TopdownL1;tma_L1_group;Metric", "MetricName": "tma_info_thread_slots_utilization" }, @@ -1401,7 +1401,7 @@ "MetricExpr": "IDQ.DSB_UOPS / ( UOPS_ISSUED.ANY )", "MetricGroup": "DSB;Fed;FetchBW;Metric;tma_issueFB", "MetricName": "tma_info_frontend_dsb_coverage", - "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & ipc / 6 > 0.35", + "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 6 > 0.35", "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1479,7 +1479,7 @@ "MetricExpr": "100 * ( tma_fetch_latency * tma_dsb_switches / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_mite / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) )", "MetricGroup": "DSBmiss;Fed;Scaled_Slots;tma_issueFB", "MetricName": "tma_info_botlnk_l2_dsb_misses", - "MetricThreshold": "tma_info_botlnk_dsb_misses > 10", + "MetricThreshold": "tma_info_botlnk_l2_dsb_misses > 10", "PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1487,7 +1487,7 @@ "MetricExpr": "100 * ( tma_frontend_bound * ( tma_fetch_bandwidth / ( tma_fetch_latency + tma_fetch_bandwidth ) ) * ( tma_dsb / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) )", "MetricGroup": "DSB;Fed;FetchBW;Scaled_Slots;tma_issueFB", "MetricName": "tma_info_botlnk_l2_dsb_bandwidth", - "MetricThreshold": "tma_info_botlnk_dsb_bandwidth > 10", + "MetricThreshold": "tma_info_botlnk_l2_dsb_bandwidth > 10", "PublicDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1495,7 +1495,7 @@ "MetricExpr": "100 * ( tma_fetch_latency * tma_icache_misses / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) )", "MetricGroup": "Fed;FetchLat;IcMiss;Scaled_Slots;tma_issueFL", "MetricName": "tma_info_botlnk_l2_ic_misses", - "MetricThreshold": "tma_info_botlnk_ic_misses > 5", + "MetricThreshold": "tma_info_botlnk_l2_ic_misses > 5", "PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck." }, { @@ -1535,7 +1535,7 @@ }, { "BriefDescription": "Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricExpr": "tma_mispredictions * tma_info_thread_slots / ( 6 ) / BR_MISP_RETIRED.ALL_BRANCHES / 100", + "MetricExpr": "tma_bottleneck_mispredictions * tma_info_thread_slots / ( 6 ) / BR_MISP_RETIRED.ALL_BRANCHES / 100", "MetricGroup": "Bad;BrMispredicts;Core_Metric;tma_issueBM", "MetricName": "tma_info_bad_spec_branch_misprediction_cost", "PublicDescription": "Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_bottleneck_mispredictions, tma_branch_mispredicts, tma_mispredicts_resteers." @@ -1678,7 +1678,7 @@ "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 4 * tma_info_core_core_clks )", "MetricGroup": "Mem;MemoryTLB;Core_Metric", "MetricName": "tma_info_memory_tlb_page_walks_utilization", - "MetricThreshold": "tma_info_memory_page_walks_utilization > 0.5" + "MetricThreshold": "tma_info_memory_tlb_page_walks_utilization > 0.5" }, { "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", @@ -1703,14 +1703,14 @@ "MetricExpr": "( MEM_INST_RETIRED.STLB_MISS_LOADS * cpu_core@MEM_INST_RETIRED.STLB_MISS_LOADS@R ) / tma_info_thread_clks", "MetricGroup": "Mem;MemoryTLB;Clocks_Retired", "MetricName": "tma_info_memory_tlb_load_stlb_miss_ret", - "MetricThreshold": "tma_info_memory_load_stlb_miss_ret > 0.05" + "MetricThreshold": "tma_info_memory_tlb_load_stlb_miss_ret > 0.05" }, { "BriefDescription": "This metric represents fraction of cycles the CPU retirement was stalled likely due to STLB misses by demand stores", "MetricExpr": "( MEM_INST_RETIRED.STLB_MISS_STORES * cpu_core@MEM_INST_RETIRED.STLB_MISS_STORES@R ) / tma_info_thread_clks", "MetricGroup": "Mem;MemoryTLB;Clocks_Retired", "MetricName": "tma_info_memory_tlb_store_stlb_miss_ret", - "MetricThreshold": "tma_info_memory_store_stlb_miss_ret > 0.05" + "MetricThreshold": "tma_info_memory_tlb_store_stlb_miss_ret > 0.05" }, { "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", @@ -1741,7 +1741,7 @@ "MetricExpr": "L2_LINES_OUT.USELESS_HWPF / ( L2_LINES_OUT.SILENT + L2_LINES_OUT.NON_SILENT )", "MetricGroup": "Prefetches;Metric", "MetricName": "tma_info_memory_prefetches_useless_hwpf", - "MetricThreshold": "tma_info_memory_useless_hwpf > 0.15" + "MetricThreshold": "tma_info_memory_prefetches_useless_hwpf > 0.15" }, { "BriefDescription": "Average Latency for L2 cache miss demand Loads", @@ -1839,7 +1839,7 @@ }, { "BriefDescription": "Average number of parallel data read requests to external memory", - "MetricExpr": "UNC_ARB_DAT_OCCUPANCY.RD / cpu@UNC_ARB_DAT_OCCUPANCY.RD\\,cmask\\=0x1@", + "MetricExpr": "UNC_ARB_DAT_OCCUPANCY.RD / UNC_ARB_DAT_OCCUPANCY.RD@cmask\\=0x1@", "MetricGroup": "Mem;MemoryBW;SoC;System_Metric", "MetricName": "tma_info_system_mem_parallel_reads", "PublicDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches." diff --git a/RKL/metrics/perf/rocketlake_metrics_perf.json b/RKL/metrics/perf/rocketlake_metrics_perf.json index 02c95bae..db7ba2e5 100644 --- a/RKL/metrics/perf/rocketlake_metrics_perf.json +++ b/RKL/metrics/perf/rocketlake_metrics_perf.json @@ -20,7 +20,7 @@ }, { "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the back-end)", - "MetricExpr": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( ( tma_microcode_sequencer / ( tma_few_uops_instructions + tma_microcode_sequencer ) ) * ( tma_assists / tma_microcode_sequencer ) ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) * tma_mispredicts_resteers ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) ) ) - tma_big_code", + "MetricExpr": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( ( tma_microcode_sequencer / ( tma_few_uops_instructions + tma_microcode_sequencer ) ) * ( tma_assists / tma_microcode_sequencer ) ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) * tma_mispredicts_resteers ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) ) ) - tma_bottleneck_big_code", "MetricGroup": "BvFB;Fed;FetchBW;Frontend;TopdownL1;tma_L1_group;Default;Scaled_Slots", "MetricName": "tma_bottleneck_instruction_fetch_bw", "MetricThreshold": "tma_bottleneck_instruction_fetch_bw > 20", @@ -89,7 +89,7 @@ }, { "BriefDescription": "Total pipeline cost of remaining bottlenecks in the back-end", - "MetricExpr": "100 - ( tma_big_code + tma_instruction_fetch_bw + tma_mispredictions + tma_cache_memory_bandwidth + tma_cache_memory_latency + tma_memory_data_tlbs + tma_memory_synchronization + tma_compute_bound_est + tma_irregular_overhead + tma_branching_overhead + tma_useful_work )", + "MetricExpr": "100 - ( tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottleneck_mispredictions + tma_bottleneck_cache_memory_bandwidth + tma_bottleneck_cache_memory_latency + tma_bottleneck_memory_data_tlbs + tma_bottleneck_memory_synchronization + tma_bottleneck_compute_bound_est + tma_bottleneck_irregular_overhead + tma_bottleneck_branching_overhead + tma_bottleneck_useful_work )", "MetricGroup": "BvOB;Cor;Offcore;TopdownL1;tma_L1_group;Default;Scaled_Slots", "MetricName": "tma_bottleneck_other_bottlenecks", "MetricThreshold": "tma_bottleneck_other_bottlenecks > 20", @@ -1039,7 +1039,7 @@ "MetricExpr": "100 * ( 1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1 ) if tma_info_system_smt_2t_utilization > 0.5 else 0", "MetricGroup": "Cor;SMT;Metric", "MetricName": "tma_info_botlnk_l0_core_bound_likely", - "MetricThreshold": "tma_info_botlnk_core_bound_likely > 0.5" + "MetricThreshold": "tma_info_botlnk_l0_core_bound_likely > 0.5" }, { "BriefDescription": "Instructions Per Cycle (per Logical Processor)", @@ -1082,7 +1082,7 @@ }, { "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor", - "MetricExpr": "tma_info_thread_slots / ( TOPDOWN.SLOTS / 2 ) if #SMT_on else 1", + "MetricExpr": "tma_info_thread_slots / ( slots / 2 ) if #SMT_on else 1", "MetricGroup": "SMT;TmaL1;TopdownL1;tma_L1_group;Metric", "MetricName": "tma_info_thread_slots_utilization" }, @@ -1302,7 +1302,7 @@ "MetricExpr": "IDQ.DSB_UOPS / ( UOPS_ISSUED.ANY )", "MetricGroup": "DSB;Fed;FetchBW;Metric;tma_issueFB", "MetricName": "tma_info_frontend_dsb_coverage", - "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & ipc / 5 > 0.35", + "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 5 > 0.35", "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1353,7 +1353,7 @@ "MetricExpr": "100 * ( tma_fetch_latency * tma_dsb_switches / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_mite / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) )", "MetricGroup": "DSBmiss;Fed;Scaled_Slots;tma_issueFB", "MetricName": "tma_info_botlnk_l2_dsb_misses", - "MetricThreshold": "tma_info_botlnk_dsb_misses > 10", + "MetricThreshold": "tma_info_botlnk_l2_dsb_misses > 10", "PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1361,7 +1361,7 @@ "MetricExpr": "100 * ( tma_frontend_bound * ( tma_fetch_bandwidth / ( tma_fetch_latency + tma_fetch_bandwidth ) ) * ( tma_dsb / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) )", "MetricGroup": "DSB;Fed;FetchBW;Scaled_Slots;tma_issueFB", "MetricName": "tma_info_botlnk_l2_dsb_bandwidth", - "MetricThreshold": "tma_info_botlnk_dsb_bandwidth > 10", + "MetricThreshold": "tma_info_botlnk_l2_dsb_bandwidth > 10", "PublicDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1369,7 +1369,7 @@ "MetricExpr": "100 * ( tma_fetch_latency * tma_icache_misses / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) )", "MetricGroup": "Fed;FetchLat;IcMiss;Scaled_Slots;tma_issueFL", "MetricName": "tma_info_botlnk_l2_ic_misses", - "MetricThreshold": "tma_info_botlnk_ic_misses > 5", + "MetricThreshold": "tma_info_botlnk_l2_ic_misses > 5", "PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck." }, { @@ -1409,7 +1409,7 @@ }, { "BriefDescription": "Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricExpr": "tma_mispredictions * tma_info_thread_slots / ( 5 ) / BR_MISP_RETIRED.ALL_BRANCHES / 100", + "MetricExpr": "tma_bottleneck_mispredictions * tma_info_thread_slots / ( 5 ) / BR_MISP_RETIRED.ALL_BRANCHES / 100", "MetricGroup": "Bad;BrMispredicts;Core_Metric;tma_issueBM", "MetricName": "tma_info_bad_spec_branch_misprediction_cost", "PublicDescription": "Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_bottleneck_mispredictions, tma_branch_mispredicts, tma_mispredicts_resteers." @@ -1552,7 +1552,7 @@ "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 2 * tma_info_core_core_clks )", "MetricGroup": "Mem;MemoryTLB;Core_Metric", "MetricName": "tma_info_memory_tlb_page_walks_utilization", - "MetricThreshold": "tma_info_memory_page_walks_utilization > 0.5" + "MetricThreshold": "tma_info_memory_tlb_page_walks_utilization > 0.5" }, { "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", @@ -1601,7 +1601,7 @@ "MetricExpr": "L2_LINES_OUT.USELESS_HWPF / ( L2_LINES_OUT.SILENT + L2_LINES_OUT.NON_SILENT )", "MetricGroup": "Prefetches;Metric", "MetricName": "tma_info_memory_prefetches_useless_hwpf", - "MetricThreshold": "tma_info_memory_useless_hwpf > 0.15" + "MetricThreshold": "tma_info_memory_prefetches_useless_hwpf > 0.15" }, { "BriefDescription": "Average Latency for L2 cache miss demand Loads", diff --git a/RKL/metrics/rocketlake_metrics.json b/RKL/metrics/rocketlake_metrics.json index b154f99e..ed71a665 100644 --- a/RKL/metrics/rocketlake_metrics.json +++ b/RKL/metrics/rocketlake_metrics.json @@ -2,7 +2,7 @@ "Header": { "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.", "Info": "Performance Monitoring Metrics for 11th Generation Intel(R) Core(TM) Processor0", - "DatePublished": "11/15/2024", + "DatePublished": "12/02/2024", "Version": "1.0", "Legend": "", "TmaVersion": "5.01", @@ -344,7 +344,7 @@ } ], "Formula": "100 * ( ( a / ( a + b + c + d ) - e / ( f ) ) - ( 1 - ( 10 * ( ( g / h ) * i / ( f ) ) * ( max( ( ( j / ( j + k ) ) * ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) + ( ( 5 ) * l ) / ( f ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * ( 1 - j / ( l - k ) ) , 0.0001 ) ) / ( ( j / ( j + k ) ) * ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) + ( ( 5 ) * l ) / ( f ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) ) ) * ( ( ( 5 ) * m - e ) / ( f ) ) * ( ( j / ( j + k ) ) * n / ( o ) ) / ( ( p / ( o ) ) + ( q / ( o ) ) + ( n / ( o ) + ( 10 ) * r / ( o ) ) + ( ( 3 ) * s / ( o ) ) + ( t / ( o ) ) + ( u / ( o ) ) ) - ( ( ( ( ( g / h ) * i / ( f ) ) / ( ( ( ( ( g / h ) * i / ( f ) ) + ( c / ( a + b + c + d ) ) * ( v - w ) / x ) - ( ( g / h ) * i / ( f ) ) ) + ( ( g / h ) * i / ( f ) ) ) ) * ( ( ( 34 ) * y / ( f ) ) / ( ( g / h ) * i / ( f ) ) ) ) * ( ( ( ( 5 ) * m - e ) / ( f ) ) * ( ( ( 3 ) * s / ( o ) ) + ( n / ( o ) + ( 10 ) * r / ( o ) ) * ( ( ( 1 - ( j / ( j + k ) ) ) * n / ( o ) ) + ( 10 * ( ( g / h ) * i / ( f ) ) * ( max( ( ( j / ( j + k ) ) * ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) + ( ( 5 ) * l ) / ( f ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * ( 1 - j / ( l - k ) ) , 0.0001 ) ) / ( ( j / ( j + k ) ) * ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) + ( ( 5 ) * l ) / ( f ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) ) * ( ( j / ( j + k ) ) * n / ( o ) ) ) / ( ( ( j / ( j + k ) ) * n / ( o ) ) + ( ( 1 - ( j / ( j + k ) ) ) * n / ( o ) ) + ( ( 10 ) * r / ( o ) ) ) ) / ( ( p / ( o ) ) + ( q / ( o ) ) + ( n / ( o ) + ( 10 ) * r / ( o ) ) + ( ( 3 ) * s / ( o ) ) + ( t / ( o ) ) + ( u / ( o ) ) ) + ( max( 0 , ( a / ( a + b + c + d ) - e / ( f ) ) - ( ( ( 5 ) * m - e ) / ( f ) ) ) ) * ( z / ( a_a if smt_on else ( o ) ) / 2 ) / ( ( ( a_b - a_c ) / ( a_a if smt_on else ( o ) ) / 2 ) + ( ( a_d - a_e ) / ( a_a if smt_on else ( o ) ) / 2 ) + ( ( a_f - a_g ) / ( a_a if smt_on else ( o ) ) / 2 ) + ( z / ( a_a if smt_on else ( o ) ) / 2 ) ) ) ) ) - ( 100 * ( ( ( 5 ) * m - e ) / ( f ) ) * ( ( q / ( o ) ) + ( p / ( o ) ) + ( ( 10 ) * r / ( o ) ) ) / ( ( p / ( o ) ) + ( q / ( o ) ) + ( n / ( o ) + ( 10 ) * r / ( o ) ) + ( ( 3 ) * s / ( o ) ) + ( t / ( o ) ) + ( u / ( o ) ) ) )", - "BaseFormula": " 100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( ( tma_microcode_sequencer / ( tma_few_uops_instructions + tma_microcode_sequencer ) ) * ( tma_assists / tma_microcode_sequencer ) ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) * tma_mispredicts_resteers ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) ) ) - tma_big_code", + "BaseFormula": " 100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( ( tma_microcode_sequencer / ( tma_few_uops_instructions + tma_microcode_sequencer ) ) * ( tma_assists / tma_microcode_sequencer ) ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) * tma_mispredicts_resteers ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) ) ) - tma_bottleneck_big_code", "Category": "TMA", "CountDomain": "Scaled_Slots", "Threshold": { @@ -1918,7 +1918,7 @@ } ], "Formula": "100 - ( ( 100 * ( ( ( 5 ) * a - b ) / ( c ) ) * ( ( d / ( e ) ) + ( f / ( e ) ) + ( ( 10 ) * g / ( e ) ) ) / ( ( f / ( e ) ) + ( d / ( e ) ) + ( h / ( e ) + ( 10 ) * g / ( e ) ) + ( ( 3 ) * i / ( e ) ) + ( j / ( e ) ) + ( k / ( e ) ) ) ) + ( 100 * ( ( l / ( l + m + n + o ) - b / ( c ) ) - ( 1 - ( 10 * ( ( p / q ) * r / ( c ) ) * ( max( ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) * ( 1 - s / ( u - t ) ) , 0.0001 ) ) / ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( ( ( 5 ) * a - b ) / ( c ) ) * ( ( s / ( s + t ) ) * h / ( e ) ) / ( ( f / ( e ) ) + ( d / ( e ) ) + ( h / ( e ) + ( 10 ) * g / ( e ) ) + ( ( 3 ) * i / ( e ) ) + ( j / ( e ) ) + ( k / ( e ) ) ) - ( ( ( ( ( p / q ) * r / ( c ) ) / ( ( ( ( ( p / q ) * r / ( c ) ) + ( n / ( l + m + n + o ) ) * ( v - w ) / x ) - ( ( p / q ) * r / ( c ) ) ) + ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( 34 ) * y / ( c ) ) / ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( ( 5 ) * a - b ) / ( c ) ) * ( ( ( 3 ) * i / ( e ) ) + ( h / ( e ) + ( 10 ) * g / ( e ) ) * ( ( ( 1 - ( s / ( s + t ) ) ) * h / ( e ) ) + ( 10 * ( ( p / q ) * r / ( c ) ) * ( max( ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) * ( 1 - s / ( u - t ) ) , 0.0001 ) ) / ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) * ( ( s / ( s + t ) ) * h / ( e ) ) ) / ( ( ( s / ( s + t ) ) * h / ( e ) ) + ( ( 1 - ( s / ( s + t ) ) ) * h / ( e ) ) + ( ( 10 ) * g / ( e ) ) ) ) / ( ( f / ( e ) ) + ( d / ( e ) ) + ( h / ( e ) + ( 10 ) * g / ( e ) ) + ( ( 3 ) * i / ( e ) ) + ( j / ( e ) ) + ( k / ( e ) ) ) + ( max( 0 , ( l / ( l + m + n + o ) - b / ( c ) ) - ( ( ( 5 ) * a - b ) / ( c ) ) ) ) * ( z / ( a_a if smt_on else ( e ) ) / 2 ) / ( ( ( a_b - a_c ) / ( a_a if smt_on else ( e ) ) / 2 ) + ( ( a_d - a_e ) / ( a_a if smt_on else ( e ) ) / 2 ) + ( ( a_f - a_g ) / ( a_a if smt_on else ( e ) ) / 2 ) + ( z / ( a_a if smt_on else ( e ) ) / 2 ) ) ) ) ) - ( 100 * ( ( ( 5 ) * a - b ) / ( c ) ) * ( ( d / ( e ) ) + ( f / ( e ) ) + ( ( 10 ) * g / ( e ) ) ) / ( ( f / ( e ) ) + ( d / ( e ) ) + ( h / ( e ) + ( 10 ) * g / ( e ) ) + ( ( 3 ) * i / ( e ) ) + ( j / ( e ) ) + ( k / ( e ) ) ) ) ) + ( 100 * ( 1 - ( 10 * ( ( p / q ) * r / ( c ) ) * ( max( ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) * ( 1 - s / ( u - t ) ) , 0.0001 ) ) / ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) + ( ( ( 5 ) * a - b ) / ( c ) ) * ( ( s / ( s + t ) ) * h / ( e ) ) / ( ( f / ( e ) ) + ( d / ( e ) ) + ( h / ( e ) + ( 10 ) * g / ( e ) ) + ( ( 3 ) * i / ( e ) ) + ( j / ( e ) ) + ( k / ( e ) ) ) ) ) + ( 100 * ( ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) * ( ( ( min( e , a_t ) ) / ( e ) ) / ( ( ( min( e , a_t ) ) / ( e ) ) + ( ( min( e , a_u ) ) / ( e ) - ( ( min( e , a_t ) ) / ( e ) ) ) ) ) ) + ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( ( a_o - a_m ) / ( e ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) * ( ( a_v / ( e ) ) / ( ( ( ( ( 32.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_z ) + ( ( 27 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_a ) ) * ( 1 + ( a_q / a_r ) / 2 ) / ( e ) ) + ( ( ( 27 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_b ) * ( 1 + ( a_q / a_r ) / 2 ) / ( e ) ) + ( ( ( 12.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_c * ( 1 + ( a_q / a_r ) / 2 ) ) / ( e ) ) + ( a_v / ( e ) ) ) ) ) + ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) * ( ( b_d / ( e ) ) / ( ( min( ( 7 ) * b_e + b_f , max( b_g - b_h , 0 ) ) / ( e ) ) + ( 13 * b_i / ( e ) ) + ( min( 2 * ( b_j - b_k - b_l ) * dependentloadsweight / 100 , max( b_g - b_h , 0 ) ) / ( e ) ) + ( ( 16 * max( 0 , b_n - b_o ) + ( b_n / b_p ) * ( ( 10 ) * b_q + ( min( e , b_r ) ) ) ) / ( e ) ) + ( ( b_s / ( b_l + b_k ) ) * b_t / ( e ) ) + ( b_u / ( e ) ) + ( b_d / ( e ) ) ) ) ) ) ) + ( 100 * ( ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) * ( ( ( min( e , a_u ) ) / ( e ) - ( ( min( e , a_t ) ) / ( e ) ) ) / ( ( ( min( e , a_t ) ) / ( e ) ) + ( ( min( e , a_u ) ) / ( e ) - ( ( min( e , a_t ) ) / ( e ) ) ) ) ) ) + ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( ( a_o - a_m ) / ( e ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) * ( ( ( ( 12.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_c * ( 1 + ( a_q / a_r ) / 2 ) ) / ( e ) ) / ( ( ( ( ( 32.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_z ) + ( ( 27 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_a ) ) * ( 1 + ( a_q / a_r ) / 2 ) / ( e ) ) + ( ( ( 27 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_b ) * ( 1 + ( a_q / a_r ) / 2 ) / ( e ) ) + ( ( ( 12.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_c * ( 1 + ( a_q / a_r ) / 2 ) ) / ( e ) ) + ( a_v / ( e ) ) ) ) ) + ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) + ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) * ( ( min( 2 * ( b_j - b_k - b_l ) * dependentloadsweight / 100 , max( b_g - b_h , 0 ) ) / ( e ) ) / ( ( min( ( 7 ) * b_e + b_f , max( b_g - b_h , 0 ) ) / ( e ) ) + ( 13 * b_i / ( e ) ) + ( min( 2 * ( b_j - b_k - b_l ) * dependentloadsweight / 100 , max( b_g - b_h , 0 ) ) / ( e ) ) + ( ( 16 * max( 0 , b_n - b_o ) + ( b_n / b_p ) * ( ( 10 ) * b_q + ( min( e , b_r ) ) ) ) / ( e ) ) + ( ( b_s / ( b_l + b_k ) ) * b_t / ( e ) ) + ( b_u / ( e ) ) + ( b_d / ( e ) ) ) ) ) + ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) * ( ( ( 16 * max( 0 , b_n - b_o ) + ( b_n / b_p ) * ( ( 10 ) * b_q + ( min( e , b_r ) ) ) ) / ( e ) ) / ( ( min( ( 7 ) * b_e + b_f , max( b_g - b_h , 0 ) ) / ( e ) ) + ( 13 * b_i / ( e ) ) + ( min( 2 * ( b_j - b_k - b_l ) * dependentloadsweight / 100 , max( b_g - b_h , 0 ) ) / ( e ) ) + ( ( 16 * max( 0 , b_n - b_o ) + ( b_n / b_p ) * ( ( 10 ) * b_q + ( min( e , b_r ) ) ) ) / ( e ) ) + ( ( b_s / ( b_l + b_k ) ) * b_t / ( e ) ) + ( b_u / ( e ) ) + ( b_d / ( e ) ) ) ) ) + ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) * ( ( ( b_s / ( b_l + b_k ) ) * b_t / ( e ) ) / ( ( min( ( 7 ) * b_e + b_f , max( b_g - b_h , 0 ) ) / ( e ) ) + ( 13 * b_i / ( e ) ) + ( min( 2 * ( b_j - b_k - b_l ) * dependentloadsweight / 100 , max( b_g - b_h , 0 ) ) / ( e ) ) + ( ( 16 * max( 0 , b_n - b_o ) + ( b_n / b_p ) * ( ( 10 ) * b_q + ( min( e , b_r ) ) ) ) / ( e ) ) + ( ( b_s / ( b_l + b_k ) ) * b_t / ( e ) ) + ( b_u / ( e ) ) + ( b_d / ( e ) ) ) ) ) + ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( a_i / ( e ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) * ( ( b_v / ( a_a if smt_on else ( e ) ) ) / ( ( ( ( b_q * ( 10 ) * ( 1 - ( b_n / b_p ) ) ) + ( 1 - ( b_n / b_p ) ) * ( min( e , b_r ) ) ) / ( e ) ) + ( ( 32.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_w / ( e ) ) + ( b_v / ( a_a if smt_on else ( e ) ) ) + ( 9 * b_x / ( e ) ) + ( ( ( 7 ) * b_y + b_z ) / ( a_a if smt_on else ( e ) ) ) ) ) ) + ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( a_i / ( e ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) * ( ( ( ( b_q * ( 10 ) * ( 1 - ( b_n / b_p ) ) ) + ( 1 - ( b_n / b_p ) ) * ( min( e , b_r ) ) ) / ( e ) ) / ( ( ( ( b_q * ( 10 ) * ( 1 - ( b_n / b_p ) ) ) + ( 1 - ( b_n / b_p ) ) * ( min( e , b_r ) ) ) / ( e ) ) + ( ( 32.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_w / ( e ) ) + ( b_v / ( a_a if smt_on else ( e ) ) ) + ( 9 * b_x / ( e ) ) + ( ( ( 7 ) * b_y + b_z ) / ( a_a if smt_on else ( e ) ) ) ) ) ) ) ) + ( 100 * ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) / max( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) , ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) ) * ( ( min( ( 7 ) * b_e + b_f , max( b_g - b_h , 0 ) ) / ( e ) ) / max( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) , ( ( min( ( 7 ) * b_e + b_f , max( b_g - b_h , 0 ) ) / ( e ) ) + ( 13 * b_i / ( e ) ) + ( min( 2 * ( b_j - b_k - b_l ) * dependentloadsweight / 100 , max( b_g - b_h , 0 ) ) / ( e ) ) + ( ( 16 * max( 0 , b_n - b_o ) + ( b_n / b_p ) * ( ( 10 ) * b_q + ( min( e , b_r ) ) ) ) / ( e ) ) + ( ( b_s / ( b_l + b_k ) ) * b_t / ( e ) ) + ( b_u / ( e ) ) + ( b_d / ( e ) ) ) ) ) + ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( a_i / ( e ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) * ( ( ( ( 7 ) * b_y + b_z ) / ( a_a if smt_on else ( e ) ) ) / ( ( ( ( b_q * ( 10 ) * ( 1 - ( b_n / b_p ) ) ) + ( 1 - ( b_n / b_p ) ) * ( min( e , b_r ) ) ) / ( e ) ) + ( ( 32.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_w / ( e ) ) + ( b_v / ( a_a if smt_on else ( e ) ) ) + ( 9 * b_x / ( e ) ) + ( ( ( 7 ) * b_y + b_z ) / ( a_a if smt_on else ( e ) ) ) ) ) ) ) ) + ( 100 * ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( ( ( a_o - a_m ) / ( e ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) * ( ( ( ( ( 32.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_z ) + ( ( 27 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_a ) ) * ( 1 + ( a_q / a_r ) / 2 ) / ( e ) ) + ( ( ( 27 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_b ) * ( 1 + ( a_q / a_r ) / 2 ) / ( e ) ) ) / ( ( ( ( ( 32.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_z ) + ( ( 27 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_a ) ) * ( 1 + ( a_q / a_r ) / 2 ) / ( e ) ) + ( ( ( 27 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_b ) * ( 1 + ( a_q / a_r ) / 2 ) / ( e ) ) + ( ( ( 12.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_c * ( 1 + ( a_q / a_r ) / 2 ) ) / ( e ) ) + ( a_v / ( e ) ) ) + ( ( a_i / ( e ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) * ( ( 32.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_w / ( e ) ) / ( ( ( ( ( b_q * ( 10 ) * ( 1 - ( b_n / b_p ) ) ) + ( 1 - ( b_n / b_p ) ) * ( min( e , b_r ) ) ) / ( e ) ) + ( ( 32.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_w / ( e ) ) + ( b_v / ( a_a if smt_on else ( e ) ) ) + ( 9 * b_x / ( e ) ) + ( ( ( 7 ) * b_y + b_z ) / ( a_a if smt_on else ( e ) ) ) ) - ( ( ( b_q * ( 10 ) * ( 1 - ( b_n / b_p ) ) ) + ( 1 - ( b_n / b_p ) ) * ( min( e , b_r ) ) ) / ( e ) ) ) ) + ( max( 0 , ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( 1 - ( max( ( max( 0 , ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( 1 - c_a / t ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( 1 - c_a / t ) , 0.0001 ) ) ) ) ) ) + ( 100 * ( ( ( max( 0 , ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) - ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) ) ) * ( c_b / ( e ) ) / ( ( c_b / ( e ) ) + ( c_c / ( e ) ) + ( ( ( c_d / ( e ) ) * ( e ) + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) ) / ( e ) if ( c_b < ( a_j - a_h ) ) else ( a_k + ( n / ( l + m + n + o ) ) * a_l ) / ( e ) ) ) ) + ( ( max( 0 , ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) - ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) ) ) * ( ( ( ( c_d / ( e ) ) * ( e ) + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) ) / ( e ) if ( c_b < ( a_j - a_h ) ) else ( a_k + ( n / ( l + m + n + o ) ) * a_l ) / ( e ) ) / ( ( c_b / ( e ) ) + ( c_c / ( e ) ) + ( ( ( c_d / ( e ) ) * ( e ) + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) ) / ( e ) if ( c_b < ( a_j - a_h ) ) else ( a_k + ( n / ( l + m + n + o ) ) * a_l ) / ( e ) ) ) ) * ( ( c_e / ( e ) ) / ( ( c_d / ( e ) ) + ( a_k / ( e ) ) + ( a_l / ( e ) ) + ( c_e / ( e ) ) ) ) ) ) ) + ( 100 * ( ( ( ( ( ( p / q ) * r / ( c ) ) / ( ( ( ( ( p / q ) * r / ( c ) ) + ( n / ( l + m + n + o ) ) * ( v - w ) / x ) - ( ( p / q ) * r / ( c ) ) ) + ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( 34 ) * y / ( c ) ) / ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( ( 5 ) * a - b ) / ( c ) ) * ( ( ( 3 ) * i / ( e ) ) + ( h / ( e ) + ( 10 ) * g / ( e ) ) * ( ( ( 1 - ( s / ( s + t ) ) ) * h / ( e ) ) + ( 10 * ( ( p / q ) * r / ( c ) ) * ( max( ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) * ( 1 - s / ( u - t ) ) , 0.0001 ) ) / ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) * ( ( s / ( s + t ) ) * h / ( e ) ) ) / ( ( ( s / ( s + t ) ) * h / ( e ) ) + ( ( 1 - ( s / ( s + t ) ) ) * h / ( e ) ) + ( ( 10 ) * g / ( e ) ) ) ) / ( ( f / ( e ) ) + ( d / ( e ) ) + ( h / ( e ) + ( 10 ) * g / ( e ) ) + ( ( 3 ) * i / ( e ) ) + ( j / ( e ) ) + ( k / ( e ) ) ) + ( max( 0 , ( l / ( l + m + n + o ) - b / ( c ) ) - ( ( ( 5 ) * a - b ) / ( c ) ) ) ) * ( z / ( a_a if smt_on else ( e ) ) / 2 ) / ( ( ( a_b - a_c ) / ( a_a if smt_on else ( e ) ) / 2 ) + ( ( a_d - a_e ) / ( a_a if smt_on else ( e ) ) / 2 ) + ( ( a_f - a_g ) / ( a_a if smt_on else ( e ) ) / 2 ) + ( z / ( a_a if smt_on else ( e ) ) / 2 ) ) ) ) + ( 10 * ( ( p / q ) * r / ( c ) ) * ( max( ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) * ( 1 - s / ( u - t ) ) , 0.0001 ) ) / ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) * ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) + ( ( max( 0 , ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( max( ( max( 0 , ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( 1 - c_a / t ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( 1 - c_a / t ) , 0.0001 ) ) ) ) + ( ( max( 0 , ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) - ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) ) ) * ( ( c_c / ( e ) ) + ( max( 0 , ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) - ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) ) ) * c_f / ( e ) * ( c_d / ( e ) ) ) / ( ( c_b / ( e ) ) + ( c_c / ( e ) ) + ( ( ( c_d / ( e ) ) * ( e ) + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) ) / ( e ) if ( c_b < ( a_j - a_h ) ) else ( a_k + ( n / ( l + m + n + o ) ) * a_l ) / ( e ) ) ) ) + ( ( ( ( ( p / q ) * r / ( c ) ) / ( ( ( ( ( p / q ) * r / ( c ) ) + ( n / ( l + m + n + o ) ) * ( v - w ) / x ) - ( ( p / q ) * r / ( c ) ) ) + ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( 34 ) * y / ( c ) ) / ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( p / q ) * r / ( c ) ) + ( n / ( l + m + n + o ) ) * ( v - w ) / x ) ) ) ) + ( 100 * ( ( c_g + 2 * c_h + c_i ) / ( c ) ) ) + ( 100 * ( ( n / ( l + m + n + o ) ) - ( ( c_g + 2 * c_h + c_i ) / ( c ) ) - ( ( ( ( ( p / q ) * r / ( c ) ) / ( ( ( ( ( p / q ) * r / ( c ) ) + ( n / ( l + m + n + o ) ) * ( v - w ) / x ) - ( ( p / q ) * r / ( c ) ) ) + ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( 34 ) * y / ( c ) ) / ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( p / q ) * r / ( c ) ) + ( n / ( l + m + n + o ) ) * ( v - w ) / x ) ) ) ) )", - "BaseFormula": " 100 - ( tma_big_code + tma_instruction_fetch_bw + tma_mispredictions + tma_cache_memory_bandwidth + tma_cache_memory_latency + tma_memory_data_tlbs + tma_memory_synchronization + tma_compute_bound_est + tma_irregular_overhead + tma_branching_overhead + tma_useful_work )", + "BaseFormula": " 100 - ( tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottleneck_mispredictions + tma_bottleneck_cache_memory_bandwidth + tma_bottleneck_cache_memory_latency + tma_bottleneck_memory_data_tlbs + tma_bottleneck_memory_synchronization + tma_bottleneck_compute_bound_est + tma_bottleneck_irregular_overhead + tma_bottleneck_branching_overhead + tma_bottleneck_useful_work )", "Category": "TMA", "CountDomain": "Scaled_Slots", "Threshold": { @@ -8258,11 +8258,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_Core_Bound_Likely" + "Value": "metric_TMA_Info_Botlnk_L0_Core_Bound_Likely" } ], "Formula": "a > 0.5", - "BaseFormula": "metric_TMA_Info_Botlnk_Core_Bound_Likely > 0.5", + "BaseFormula": "metric_TMA_Info_Botlnk_L0_Core_Bound_Likely > 0.5", "ThresholdIssues": "" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -9692,11 +9692,11 @@ }, { "Alias": "b", - "Value": "IPC" + "Value": "metric_TMA_Info_Thread_IPC" } ], "Formula": "a < 0.7 & b / 5 > 0.35", - "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & IPC / 5 > 0.35", + "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & metric_TMA_Info_Thread_IPC / 5 > 0.35", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -10037,11 +10037,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_DSB_Misses" + "Value": "metric_TMA_Info_Botlnk_L2_DSB_Misses" } ], "Formula": "a > 10", - "BaseFormula": "metric_TMA_Info_Botlnk_DSB_Misses > 10", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_DSB_Misses > 10", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -10138,11 +10138,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_DSB_Bandwidth" + "Value": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth" } ], "Formula": "a > 10", - "BaseFormula": "metric_TMA_Info_Botlnk_DSB_Bandwidth > 10", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth > 10", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -10210,11 +10210,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_IC_Misses" + "Value": "metric_TMA_Info_Botlnk_L2_IC_Misses" } ], "Formula": "a > 5", - "BaseFormula": "metric_TMA_Info_Botlnk_IC_Misses > 5", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_IC_Misses > 5", "ThresholdIssues": "$issueFL" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -10495,7 +10495,7 @@ ], "Constants": [], "Formula": "( 100 * ( 1 - ( 10 * ( ( a / b ) * c / ( d ) ) * ( max( ( ( e / ( e + f ) ) * ( max( 1 - ( ( g / ( g + h + i + j ) - k / ( d ) ) + ( j / ( g + h + i + j ) + ( ( 5 ) * l ) / ( d ) ) + ( i / ( g + h + i + j ) ) ) , 0 ) ) ) * ( 1 - e / ( l - f ) ) , 0.0001 ) ) / ( ( e / ( e + f ) ) * ( max( 1 - ( ( g / ( g + h + i + j ) - k / ( d ) ) + ( j / ( g + h + i + j ) + ( ( 5 ) * l ) / ( d ) ) + ( i / ( g + h + i + j ) ) ) , 0 ) ) ) ) ) * ( ( ( e / ( e + f ) ) * ( max( 1 - ( ( g / ( g + h + i + j ) - k / ( d ) ) + ( j / ( g + h + i + j ) + ( ( 5 ) * l ) / ( d ) ) + ( i / ( g + h + i + j ) ) ) , 0 ) ) ) + ( ( ( 5 ) * m - k ) / ( d ) ) * ( ( e / ( e + f ) ) * n / ( o ) ) / ( ( p / ( o ) ) + ( q / ( o ) ) + ( n / ( o ) + ( 10 ) * r / ( o ) ) + ( ( 3 ) * s / ( o ) ) + ( t / ( o ) ) + ( u / ( o ) ) ) ) ) * ( d ) / ( 5 ) / e / 100", - "BaseFormula": " tma_mispredictions * tma_info_thread_slots / ( 5 ) / br_misp_retired.all_branches / 100", + "BaseFormula": " tma_bottleneck_mispredictions * tma_info_thread_slots / ( 5 ) / br_misp_retired.all_branches / 100", "Category": "TMA", "CountDomain": "Core_Metric", "Threshold": { @@ -11257,11 +11257,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Memory_Page_Walks_Utilization" + "Value": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization" } ], "Formula": "a > 0.5", - "BaseFormula": "metric_TMA_Info_Memory_Page_Walks_Utilization > 0.5", + "BaseFormula": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization > 0.5", "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", @@ -11511,11 +11511,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Memory_Useless_HWPF" + "Value": "metric_TMA_Info_Memory_Prefetches_Useless_HWPF" } ], "Formula": "a > 0.15", - "BaseFormula": "metric_TMA_Info_Memory_Useless_HWPF > 0.15", + "BaseFormula": "metric_TMA_Info_Memory_Prefetches_Useless_HWPF > 0.15", "ThresholdIssues": "" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", diff --git a/SKL/metrics/perf/skylake_metrics_perf.json b/SKL/metrics/perf/skylake_metrics_perf.json index 236f8cef..2c56e32d 100644 --- a/SKL/metrics/perf/skylake_metrics_perf.json +++ b/SKL/metrics/perf/skylake_metrics_perf.json @@ -16,7 +16,7 @@ }, { "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the back-end)", - "MetricExpr": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( ( tma_microcode_sequencer / ( tma_few_uops_instructions + tma_microcode_sequencer ) ) * ( tma_assists / tma_microcode_sequencer ) ) * tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) ) ) - tma_big_code", + "MetricExpr": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( ( tma_microcode_sequencer / ( tma_few_uops_instructions + tma_microcode_sequencer ) ) * ( tma_assists / tma_microcode_sequencer ) ) * tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) ) ) - tma_bottleneck_big_code", "MetricGroup": "BvFB;Fed;FetchBW;Frontend;TopdownL1;tma_L1_group;Scaled_Slots", "MetricName": "tma_bottleneck_instruction_fetch_bw", "MetricThreshold": "tma_bottleneck_instruction_fetch_bw > 20" @@ -71,7 +71,7 @@ }, { "BriefDescription": "Total pipeline cost of remaining bottlenecks in the back-end", - "MetricExpr": "100 - ( tma_big_code + tma_instruction_fetch_bw + tma_mispredictions + tma_cache_memory_bandwidth + tma_cache_memory_latency + tma_memory_data_tlbs + tma_memory_synchronization + tma_compute_bound_est + tma_irregular_overhead + tma_branching_overhead + tma_useful_work )", + "MetricExpr": "100 - ( tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottleneck_mispredictions + tma_bottleneck_cache_memory_bandwidth + tma_bottleneck_cache_memory_latency + tma_bottleneck_memory_data_tlbs + tma_bottleneck_memory_synchronization + tma_bottleneck_compute_bound_est + tma_bottleneck_irregular_overhead + tma_bottleneck_branching_overhead + tma_bottleneck_useful_work )", "MetricGroup": "BvOB;Cor;Offcore;TopdownL1;tma_L1_group;Scaled_Slots", "MetricName": "tma_bottleneck_other_bottlenecks", "MetricThreshold": "tma_bottleneck_other_bottlenecks > 20", @@ -958,7 +958,7 @@ "MetricExpr": "100 * ( 1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1 ) if tma_info_system_smt_2t_utilization > 0.5 else 0", "MetricGroup": "Cor;SMT;Metric", "MetricName": "tma_info_botlnk_l0_core_bound_likely", - "MetricThreshold": "tma_info_botlnk_core_bound_likely > 0.5" + "MetricThreshold": "tma_info_botlnk_l0_core_bound_likely > 0.5" }, { "BriefDescription": "Instructions Per Cycle (per Logical Processor)", @@ -1189,7 +1189,7 @@ "MetricExpr": "IDQ.DSB_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS )", "MetricGroup": "DSB;Fed;FetchBW;Metric;tma_issueFB", "MetricName": "tma_info_frontend_dsb_coverage", - "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & ipc / 4 > 0.35", + "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 4 > 0.35", "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1240,7 +1240,7 @@ "MetricExpr": "100 * ( tma_fetch_latency * tma_dsb_switches / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_mite / ( tma_mite + tma_dsb ) )", "MetricGroup": "DSBmiss;Fed;Scaled_Slots;tma_issueFB", "MetricName": "tma_info_botlnk_l2_dsb_misses", - "MetricThreshold": "tma_info_botlnk_dsb_misses > 10", + "MetricThreshold": "tma_info_botlnk_l2_dsb_misses > 10", "PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1248,7 +1248,7 @@ "MetricExpr": "100 * ( tma_frontend_bound * ( tma_fetch_bandwidth / ( tma_fetch_latency + tma_fetch_bandwidth ) ) * ( tma_dsb / ( tma_mite + tma_dsb ) ) )", "MetricGroup": "DSB;Fed;FetchBW;Scaled_Slots;tma_issueFB", "MetricName": "tma_info_botlnk_l2_dsb_bandwidth", - "MetricThreshold": "tma_info_botlnk_dsb_bandwidth > 10", + "MetricThreshold": "tma_info_botlnk_l2_dsb_bandwidth > 10", "PublicDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1256,7 +1256,7 @@ "MetricExpr": "100 * ( tma_fetch_latency * tma_icache_misses / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) )", "MetricGroup": "Fed;FetchLat;IcMiss;Scaled_Slots;tma_issueFL", "MetricName": "tma_info_botlnk_l2_ic_misses", - "MetricThreshold": "tma_info_botlnk_ic_misses > 5", + "MetricThreshold": "tma_info_botlnk_l2_ic_misses > 5", "PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck." }, { @@ -1275,7 +1275,7 @@ }, { "BriefDescription": "Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricExpr": "tma_mispredictions * tma_info_thread_slots / ( 4 ) / BR_MISP_RETIRED.ALL_BRANCHES / 100", + "MetricExpr": "tma_bottleneck_mispredictions * tma_info_thread_slots / ( 4 ) / BR_MISP_RETIRED.ALL_BRANCHES / 100", "MetricGroup": "Bad;BrMispredicts;Core_Metric;tma_issueBM", "MetricName": "tma_info_bad_spec_branch_misprediction_cost", "PublicDescription": "Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_bottleneck_mispredictions, tma_branch_mispredicts, tma_mispredicts_resteers." @@ -1412,7 +1412,7 @@ "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING ) / ( 2 * tma_info_core_core_clks )", "MetricGroup": "Mem;MemoryTLB;Core_Metric", "MetricName": "tma_info_memory_tlb_page_walks_utilization", - "MetricThreshold": "tma_info_memory_page_walks_utilization > 0.5" + "MetricThreshold": "tma_info_memory_tlb_page_walks_utilization > 0.5" }, { "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", @@ -1547,7 +1547,7 @@ }, { "BriefDescription": "Average number of parallel data read requests to external memory", - "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.DATA_READ / UNC_ARB_TRK_OCCUPANCY.DATA_READ\\,cmask\\=0x1@", + "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.DATA_READ / UNC_ARB_TRK_OCCUPANCY.DATA_READ@cmask\\=0x1@", "MetricGroup": "Mem;MemoryBW;SoC;System_Metric", "MetricName": "tma_info_system_mem_parallel_reads", "PublicDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches." diff --git a/SKL/metrics/skylake_metrics.json b/SKL/metrics/skylake_metrics.json index 161f0a14..2e7894d8 100644 --- a/SKL/metrics/skylake_metrics.json +++ b/SKL/metrics/skylake_metrics.json @@ -2,7 +2,7 @@ "Header": { "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.", "Info": "Performance Monitoring Metrics for 6th Generation Intel(R) Core(TM) Processor0", - "DatePublished": "11/15/2024", + "DatePublished": "12/02/2024", "Version": "1.0", "Legend": "", "TmaVersion": "5.01", @@ -318,7 +318,7 @@ } ], "Formula": "100 * ( ( a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( 1 - ( 10 * ( ( ( d ) / e ) * f / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( max( ( ( g / ( g + h ) ) * ( ( e - ( d ) + ( 4 ) * ( ( i / 2 ) if smt_on else j ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( 1 - g / ( k - h ) ) , 0.0001 ) ) / ( ( g / ( g + h ) ) * ( ( e - ( d ) + ( 4 ) * ( ( i / 2 ) if smt_on else j ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) ) * ( ( 4 ) * l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( ( g / ( g + h ) ) * m / ( c ) ) / ( ( ( n + 2 * o ) / ( c ) ) + ( p / ( c ) ) + ( m / ( c ) + ( 9 ) * q / ( c ) ) + ( ( 2 ) * r / ( c ) ) + ( s / ( c ) ) + ( t / ( c ) ) ) - ( ( ( ( ( ( d ) / e ) * f / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) / ( ( ( ( ( d ) + u - v ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( d ) / e ) * f / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) + ( ( ( d ) / e ) * f / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( ( ( 34 ) * ( w + x ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) / ( ( ( d ) / e ) * f / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( ( 4 ) * l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( ( ( 2 ) * r / ( c ) ) + ( m / ( c ) + ( 9 ) * q / ( c ) ) * ( ( ( 1 - ( g / ( g + h ) ) ) * m / ( c ) ) + ( ( g / ( g + h ) ) * m / ( c ) ) * ( 10 * ( ( ( d ) / e ) * f / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( max( ( ( g / ( g + h ) ) * ( ( e - ( d ) + ( 4 ) * ( ( i / 2 ) if smt_on else j ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( 1 - g / ( k - h ) ) , 0.0001 ) ) / ( ( g / ( g + h ) ) * ( ( e - ( d ) + ( 4 ) * ( ( i / 2 ) if smt_on else j ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) ) / ( ( ( g / ( g + h ) ) * m / ( c ) ) + ( ( 1 - ( g / ( g + h ) ) ) * m / ( c ) ) + ( ( 9 ) * q / ( c ) ) ) ) / ( ( ( n + 2 * o ) / ( c ) ) + ( p / ( c ) ) + ( m / ( c ) + ( 9 ) * q / ( c ) ) + ( ( 2 ) * r / ( c ) ) + ( s / ( c ) ) + ( t / ( c ) ) ) ) ) - ( 100 * ( ( 4 ) * l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( ( p / ( c ) ) + ( ( n + 2 * o ) / ( c ) ) + ( ( 9 ) * q / ( c ) ) ) / ( ( ( n + 2 * o ) / ( c ) ) + ( p / ( c ) ) + ( m / ( c ) + ( 9 ) * q / ( c ) ) + ( ( 2 ) * r / ( c ) ) + ( s / ( c ) ) + ( t / ( c ) ) ) )", - "BaseFormula": " 100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( ( tma_microcode_sequencer / ( tma_few_uops_instructions + tma_microcode_sequencer ) ) * ( tma_assists / tma_microcode_sequencer ) ) * tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) ) ) - tma_big_code", + "BaseFormula": " 100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( ( tma_microcode_sequencer / ( tma_few_uops_instructions + tma_microcode_sequencer ) ) * ( tma_assists / tma_microcode_sequencer ) ) * tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) ) ) - tma_bottleneck_big_code", "Category": "TMA", "CountDomain": "Scaled_Slots", "Threshold": { @@ -1805,7 +1805,7 @@ } ], "Formula": "100 - ( ( 100 * ( ( 4 ) * a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( ( d / ( c ) ) + ( ( e + 2 * f ) / ( c ) ) + ( ( 9 ) * g / ( c ) ) ) / ( ( ( e + 2 * f ) / ( c ) ) + ( d / ( c ) ) + ( h / ( c ) + ( 9 ) * g / ( c ) ) + ( ( 2 ) * i / ( c ) ) + ( j / ( c ) ) + ( k / ( c ) ) ) ) + ( 100 * ( ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( 1 - ( 10 * ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( max( ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( 1 - p / ( t - q ) ) , 0.0001 ) ) / ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) ) * ( ( 4 ) * a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( ( p / ( p + q ) ) * h / ( c ) ) / ( ( ( e + 2 * f ) / ( c ) ) + ( d / ( c ) ) + ( h / ( c ) + ( 9 ) * g / ( c ) ) + ( ( 2 ) * i / ( c ) ) + ( j / ( c ) ) + ( k / ( c ) ) ) - ( ( ( ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) / ( ( ( ( ( m ) + u - v ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) + ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( ( ( 34 ) * ( w + x ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) / ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( ( 4 ) * a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( ( ( 2 ) * i / ( c ) ) + ( h / ( c ) + ( 9 ) * g / ( c ) ) * ( ( ( 1 - ( p / ( p + q ) ) ) * h / ( c ) ) + ( ( p / ( p + q ) ) * h / ( c ) ) * ( 10 * ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( max( ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( 1 - p / ( t - q ) ) , 0.0001 ) ) / ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) ) / ( ( ( p / ( p + q ) ) * h / ( c ) ) + ( ( 1 - ( p / ( p + q ) ) ) * h / ( c ) ) + ( ( 9 ) * g / ( c ) ) ) ) / ( ( ( e + 2 * f ) / ( c ) ) + ( d / ( c ) ) + ( h / ( c ) + ( 9 ) * g / ( c ) ) + ( ( 2 ) * i / ( c ) ) + ( j / ( c ) ) + ( k / ( c ) ) ) ) ) - ( 100 * ( ( 4 ) * a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( ( d / ( c ) ) + ( ( e + 2 * f ) / ( c ) ) + ( ( 9 ) * g / ( c ) ) ) / ( ( ( e + 2 * f ) / ( c ) ) + ( d / ( c ) ) + ( h / ( c ) + ( 9 ) * g / ( c ) ) + ( ( 2 ) * i / ( c ) ) + ( j / ( c ) ) + ( k / ( c ) ) ) ) ) + ( 100 * ( 1 - ( 10 * ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( max( ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( 1 - p / ( t - q ) ) , 0.0001 ) ) / ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) ) * ( ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) + ( ( 4 ) * a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( ( p / ( p + q ) ) * h / ( c ) ) / ( ( ( e + 2 * f ) / ( c ) ) + ( d / ( c ) ) + ( h / ( c ) + ( 9 ) * g / ( c ) ) + ( ( 2 ) * i / ( c ) ) + ( j / ( c ) ) + ( k / ( c ) ) ) ) ) + ( 100 * ( ( ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) / ( ( max( ( y - a_e ) / ( c ) , 0 ) ) + ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) + ( ( a_f - a_d ) / ( c ) ) + ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) + ( z / ( c ) ) ) ) * ( ( ( min( c , a_k ) ) / ( c ) ) / ( ( ( min( c , a_k ) ) / ( c ) ) + ( ( min( c , a_l ) ) / ( c ) - ( ( min( c , a_k ) ) / ( c ) ) ) ) ) ) + ( ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( ( ( a_f - a_d ) / ( c ) ) / ( ( max( ( y - a_e ) / ( c ) , 0 ) ) + ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) + ( ( a_f - a_d ) / ( c ) ) + ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) + ( z / ( c ) ) ) ) * ( ( ( ( a_m / 2 ) if smt_on else a_m ) / ( ( b / 2 ) if smt_on else ( c ) ) ) / ( ( ( ( ( 22 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_q ) + ( ( 20 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_r ) ) * ( 1 + ( a_h / a_i ) / 2 ) / ( c ) ) + ( ( ( 20 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_s ) * ( 1 + ( a_h / a_i ) / 2 ) / ( c ) ) + ( ( ( 10 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_t * ( 1 + ( a_h / a_i ) / 2 ) ) / ( c ) ) + ( ( ( a_m / 2 ) if smt_on else a_m ) / ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) + ( ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( ( max( ( y - a_e ) / ( c ) , 0 ) ) / ( ( max( ( y - a_e ) / ( c ) , 0 ) ) + ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) + ( ( a_f - a_d ) / ( c ) ) + ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) + ( z / ( c ) ) ) ) * ( ( ( a_u / ( a_v + a_w ) ) * a_j / ( c ) ) / ( ( min( ( 9 ) * a_x + a_y , max( a_z - b_a , 0 ) ) / ( c ) ) + ( 13 * b_b / ( c ) ) + ( min( 2 * ( b_c - a_w - a_v ) * dependentloadsweight / 100 , max( a_z - b_a , 0 ) ) / ( c ) ) + ( ( 12 * max( 0 , b_e - b_f ) + ( b_e / b_g ) * ( ( 9 ) * b_h + ( min( c , b_i ) ) ) ) / ( c ) ) + ( ( a_u / ( a_v + a_w ) ) * b_j / ( c ) ) + ( b_k / ( c ) ) + ( ( a_u / ( a_v + a_w ) ) * a_j / ( c ) ) ) ) ) ) ) + ( 100 * ( ( ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) / ( ( max( ( y - a_e ) / ( c ) , 0 ) ) + ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) + ( ( a_f - a_d ) / ( c ) ) + ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) + ( z / ( c ) ) ) ) * ( ( ( min( c , a_l ) ) / ( c ) - ( ( min( c , a_k ) ) / ( c ) ) ) / ( ( ( min( c , a_k ) ) / ( c ) ) + ( ( min( c , a_l ) ) / ( c ) - ( ( min( c , a_k ) ) / ( c ) ) ) ) ) ) + ( ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( ( ( a_f - a_d ) / ( c ) ) / ( ( max( ( y - a_e ) / ( c ) , 0 ) ) + ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) + ( ( a_f - a_d ) / ( c ) ) + ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) + ( z / ( c ) ) ) ) * ( ( ( ( 10 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_t * ( 1 + ( a_h / a_i ) / 2 ) ) / ( c ) ) / ( ( ( ( ( 22 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_q ) + ( ( 20 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_r ) ) * ( 1 + ( a_h / a_i ) / 2 ) / ( c ) ) + ( ( ( 20 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_s ) * ( 1 + ( a_h / a_i ) / 2 ) / ( c ) ) + ( ( ( 10 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_t * ( 1 + ( a_h / a_i ) / 2 ) ) / ( c ) ) + ( ( ( a_m / 2 ) if smt_on else a_m ) / ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) + ( ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) / ( ( max( ( y - a_e ) / ( c ) , 0 ) ) + ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) + ( ( a_f - a_d ) / ( c ) ) + ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) + ( z / ( c ) ) ) ) + ( ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( ( max( ( y - a_e ) / ( c ) , 0 ) ) / ( ( max( ( y - a_e ) / ( c ) , 0 ) ) + ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - 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( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( 1 - b_p / q ) , 0.0001 ) ) ) ) ) ) + ( 100 * ( ( ( ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( b_q / ( c ) ) / ( ( b_q / ( c ) ) + ( b_r / ( c ) ) + ( ( ( b_s / ( c ) ) * ( c ) + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) ) / ( c ) if ( b_q < ( a_a - y ) ) else ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) / ( c ) ) ) ) + ( ( ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( ( ( ( b_s / ( c ) ) * ( c ) + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) ) / ( c ) if ( b_q < ( a_a - y ) ) else ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) / ( c ) ) / ( ( b_q / ( c ) ) + ( b_r / ( c ) ) + ( ( ( b_s / ( c ) ) * ( c ) + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) ) / ( c ) if ( b_q < ( a_a - y ) ) else ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) / ( c ) ) ) ) * ( ( ( b_t / 2 if smt_on else b_t ) / ( ( b / 2 ) if smt_on else ( c ) ) ) / ( ( b_s / ( c ) ) + ( ( ( b_u - b_v ) / 2 if smt_on else a_b ) / ( ( b / 2 ) if smt_on else ( c ) ) ) + ( ( ( b_v - b_t ) / 2 if smt_on else a_c ) / ( ( b / 2 ) if smt_on else ( c ) ) ) + ( ( b_t / 2 if smt_on else b_t ) / ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) ) ) + ( 100 * ( ( ( ( ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) / ( ( ( ( ( m ) + u - v ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) + ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( ( ( 34 ) * ( w + x ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) / ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( ( 4 ) * a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( ( ( 2 ) * i / ( c ) ) + ( h / ( c ) + ( 9 ) * g / ( c ) ) * ( ( ( 1 - ( p / ( p + q ) ) ) * h / ( c ) ) + ( ( p / ( p + q ) ) * h / ( c ) ) * ( 10 * ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( max( ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( 1 - p / ( t - q ) ) , 0.0001 ) ) / ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) ) / ( ( ( p / ( p + q ) ) * h / ( c ) ) + ( ( 1 - ( p / ( p + q ) ) ) * h / ( c ) ) + ( ( 9 ) * g / ( c ) ) ) ) / ( ( ( e + 2 * f ) / ( c ) ) + ( d / ( c ) ) + ( h / ( c ) + ( 9 ) * g / ( c ) ) + ( ( 2 ) * i / ( c ) ) + ( j / ( c ) ) + ( k / ( c ) ) ) ) + ( 10 * ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( max( ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( 1 - p / ( t - q ) ) , 0.0001 ) ) / ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) + ( ( ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( max( ( ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( 1 - b_p / q ) , 0.0001 ) ) / ( ( max( ( ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( 1 - b_p / q ) , 0.0001 ) ) ) ) + ( ( ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( ( b_r / ( c ) ) + ( ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * b_w / ( c ) * ( b_s / ( c ) ) ) / ( ( b_q / ( c ) ) + ( b_r / ( c ) ) + ( ( ( b_s / ( c ) ) * ( c ) + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) ) / ( c ) if ( b_q < ( a_a - y ) ) else ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) / ( c ) ) ) ) + ( ( ( ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) / ( ( ( ( ( m ) + u - v ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) + ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( ( ( 34 ) * ( w + x ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) / ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( ( ( m ) + u - v ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) ) + ( 100 * ( ( b_x + 2 * b_y + b_z ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) + ( 100 * ( ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( b_x + 2 * b_y + b_z ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) / ( ( ( ( ( m ) + u - v ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) + ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( ( ( 34 ) * ( w + x ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) / ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( ( ( m ) + u - v ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) ) )", - "BaseFormula": " 100 - ( tma_big_code + tma_instruction_fetch_bw + tma_mispredictions + tma_cache_memory_bandwidth + tma_cache_memory_latency + tma_memory_data_tlbs + tma_memory_synchronization + tma_compute_bound_est + tma_irregular_overhead + tma_branching_overhead + tma_useful_work )", + "BaseFormula": " 100 - ( tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottleneck_mispredictions + tma_bottleneck_cache_memory_bandwidth + tma_bottleneck_cache_memory_latency + tma_bottleneck_memory_data_tlbs + tma_bottleneck_memory_synchronization + tma_bottleneck_compute_bound_est + tma_bottleneck_irregular_overhead + tma_bottleneck_branching_overhead + tma_bottleneck_useful_work )", "Category": "TMA", "CountDomain": "Scaled_Slots", "Threshold": { @@ -7947,11 +7947,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_Core_Bound_Likely" + "Value": "metric_TMA_Info_Botlnk_L0_Core_Bound_Likely" } ], "Formula": "a > 0.5", - "BaseFormula": "metric_TMA_Info_Botlnk_Core_Bound_Likely > 0.5", + "BaseFormula": "metric_TMA_Info_Botlnk_L0_Core_Bound_Likely > 0.5", "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", @@ -9177,11 +9177,11 @@ }, { "Alias": "b", - "Value": "IPC" + "Value": "metric_TMA_Info_Thread_IPC" } ], "Formula": "a < 0.7 & b / 4 > 0.35", - "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & IPC / 4 > 0.35", + "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & metric_TMA_Info_Thread_IPC / 4 > 0.35", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", @@ -9494,11 +9494,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_DSB_Misses" + "Value": "metric_TMA_Info_Botlnk_L2_DSB_Misses" } ], "Formula": "a > 10", - "BaseFormula": "metric_TMA_Info_Botlnk_DSB_Misses > 10", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_DSB_Misses > 10", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", @@ -9563,11 +9563,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_DSB_Bandwidth" + "Value": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth" } ], "Formula": "a > 10", - "BaseFormula": "metric_TMA_Info_Botlnk_DSB_Bandwidth > 10", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth > 10", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", @@ -9644,11 +9644,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_IC_Misses" + "Value": "metric_TMA_Info_Botlnk_L2_IC_Misses" } ], "Formula": "a > 5", - "BaseFormula": "metric_TMA_Info_Botlnk_IC_Misses > 5", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_IC_Misses > 5", "ThresholdIssues": "$issueFL" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", @@ -9830,7 +9830,7 @@ } ], "Formula": "( 100 * ( 1 - ( 10 * ( ( ( a ) / b ) * c / ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) ) * ( max( ( ( f / ( f + g ) ) * ( ( b - ( a ) + ( 4 ) * ( ( h / 2 ) if smt_on else i ) ) / ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) ) ) * ( 1 - f / ( j - g ) ) , 0.0001 ) ) / ( ( f / ( f + g ) ) * ( ( b - ( a ) + ( 4 ) * ( ( h / 2 ) if smt_on else i ) ) / ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) ) ) ) ) * ( ( ( f / ( f + g ) ) * ( ( b - ( a ) + ( 4 ) * ( ( h / 2 ) if smt_on else i ) ) / ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) ) ) + ( ( 4 ) * k / ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) ) * ( ( f / ( f + g ) ) * l / ( e ) ) / ( ( ( m + 2 * n ) / ( e ) ) + ( o / ( e ) ) + ( l / ( e ) + ( 9 ) * p / ( e ) ) + ( ( 2 ) * q / ( e ) ) + ( r / ( e ) ) + ( s / ( e ) ) ) ) ) * ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) / ( 4 ) / f / 100", - "BaseFormula": " tma_mispredictions * tma_info_thread_slots / ( 4 ) / br_misp_retired.all_branches / 100", + "BaseFormula": " tma_bottleneck_mispredictions * tma_info_thread_slots / ( 4 ) / br_misp_retired.all_branches / 100", "Category": "TMA", "CountDomain": "Core_Metric", "Threshold": { @@ -10558,11 +10558,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Memory_Page_Walks_Utilization" + "Value": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization" } ], "Formula": "a > 0.5", - "BaseFormula": "metric_TMA_Info_Memory_Page_Walks_Utilization > 0.5", + "BaseFormula": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization > 0.5", "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", diff --git a/SKX/metrics/perf/skylakex_metrics_perf.json b/SKX/metrics/perf/skylakex_metrics_perf.json index a02af914..75dcc040 100644 --- a/SKX/metrics/perf/skylakex_metrics_perf.json +++ b/SKX/metrics/perf/skylakex_metrics_perf.json @@ -294,7 +294,7 @@ }, { "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the back-end)", - "MetricExpr": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( ( tma_microcode_sequencer / ( tma_few_uops_instructions + tma_microcode_sequencer ) ) * ( tma_assists / tma_microcode_sequencer ) ) * tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) ) ) - tma_big_code", + "MetricExpr": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( ( tma_microcode_sequencer / ( tma_few_uops_instructions + tma_microcode_sequencer ) ) * ( tma_assists / tma_microcode_sequencer ) ) * tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) ) ) - tma_bottleneck_big_code", "MetricGroup": "BvFB;Fed;FetchBW;Frontend;TopdownL1;tma_L1_group;Scaled_Slots", "MetricName": "tma_bottleneck_instruction_fetch_bw", "MetricThreshold": "tma_bottleneck_instruction_fetch_bw > 20" @@ -349,7 +349,7 @@ }, { "BriefDescription": "Total pipeline cost of remaining bottlenecks in the back-end", - "MetricExpr": "100 - ( tma_big_code + tma_instruction_fetch_bw + tma_mispredictions + tma_cache_memory_bandwidth + tma_cache_memory_latency + tma_memory_data_tlbs + tma_memory_synchronization + tma_compute_bound_est + tma_irregular_overhead + tma_branching_overhead + tma_useful_work )", + "MetricExpr": "100 - ( tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottleneck_mispredictions + tma_bottleneck_cache_memory_bandwidth + tma_bottleneck_cache_memory_latency + tma_bottleneck_memory_data_tlbs + tma_bottleneck_memory_synchronization + tma_bottleneck_compute_bound_est + tma_bottleneck_irregular_overhead + tma_bottleneck_branching_overhead + tma_bottleneck_useful_work )", "MetricGroup": "BvOB;Cor;Offcore;TopdownL1;tma_L1_group;Scaled_Slots", "MetricName": "tma_bottleneck_other_bottlenecks", "MetricThreshold": "tma_bottleneck_other_bottlenecks > 20", @@ -1272,7 +1272,7 @@ "MetricExpr": "100 * ( 1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1 ) if tma_info_system_smt_2t_utilization > 0.5 else 0", "MetricGroup": "Cor;SMT;Metric", "MetricName": "tma_info_botlnk_l0_core_bound_likely", - "MetricThreshold": "tma_info_botlnk_core_bound_likely > 0.5" + "MetricThreshold": "tma_info_botlnk_l0_core_bound_likely > 0.5" }, { "BriefDescription": "Instructions Per Cycle (per Logical Processor)", @@ -1511,7 +1511,7 @@ "MetricExpr": "IDQ.DSB_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS )", "MetricGroup": "DSB;Fed;FetchBW;Metric;tma_issueFB", "MetricName": "tma_info_frontend_dsb_coverage", - "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & ipc / 4 > 0.35", + "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 4 > 0.35", "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1562,7 +1562,7 @@ "MetricExpr": "100 * ( tma_fetch_latency * tma_dsb_switches / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_mite / ( tma_mite + tma_dsb ) )", "MetricGroup": "DSBmiss;Fed;Scaled_Slots;tma_issueFB", "MetricName": "tma_info_botlnk_l2_dsb_misses", - "MetricThreshold": "tma_info_botlnk_dsb_misses > 10", + "MetricThreshold": "tma_info_botlnk_l2_dsb_misses > 10", "PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1570,7 +1570,7 @@ "MetricExpr": "100 * ( tma_frontend_bound * ( tma_fetch_bandwidth / ( tma_fetch_latency + tma_fetch_bandwidth ) ) * ( tma_dsb / ( tma_mite + tma_dsb ) ) )", "MetricGroup": "DSB;Fed;FetchBW;Scaled_Slots;tma_issueFB", "MetricName": "tma_info_botlnk_l2_dsb_bandwidth", - "MetricThreshold": "tma_info_botlnk_dsb_bandwidth > 10", + "MetricThreshold": "tma_info_botlnk_l2_dsb_bandwidth > 10", "PublicDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1578,7 +1578,7 @@ "MetricExpr": "100 * ( tma_fetch_latency * tma_icache_misses / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) )", "MetricGroup": "Fed;FetchLat;IcMiss;Scaled_Slots;tma_issueFL", "MetricName": "tma_info_botlnk_l2_ic_misses", - "MetricThreshold": "tma_info_botlnk_ic_misses > 5", + "MetricThreshold": "tma_info_botlnk_l2_ic_misses > 5", "PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck." }, { @@ -1597,7 +1597,7 @@ }, { "BriefDescription": "Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricExpr": "tma_mispredictions * tma_info_thread_slots / ( 4 ) / BR_MISP_RETIRED.ALL_BRANCHES / 100", + "MetricExpr": "tma_bottleneck_mispredictions * tma_info_thread_slots / ( 4 ) / BR_MISP_RETIRED.ALL_BRANCHES / 100", "MetricGroup": "Bad;BrMispredicts;Core_Metric;tma_issueBM", "MetricName": "tma_info_bad_spec_branch_misprediction_cost", "PublicDescription": "Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_bottleneck_mispredictions, tma_branch_mispredicts, tma_mispredicts_resteers." @@ -1734,7 +1734,7 @@ "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING ) / ( 2 * tma_info_core_core_clks )", "MetricGroup": "Mem;MemoryTLB;Core_Metric", "MetricName": "tma_info_memory_tlb_page_walks_utilization", - "MetricThreshold": "tma_info_memory_page_walks_utilization > 0.5" + "MetricThreshold": "tma_info_memory_tlb_page_walks_utilization > 0.5" }, { "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", diff --git a/SKX/metrics/skylakex_metrics.json b/SKX/metrics/skylakex_metrics.json index 48cbc4ef..47f63bbd 100644 --- a/SKX/metrics/skylakex_metrics.json +++ b/SKX/metrics/skylakex_metrics.json @@ -2,7 +2,7 @@ "Header": { "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.", "Info": "Performance Monitoring Metrics for Intel(R) Xeon(R) Processor Scalable Family based on Skylake microarchitecture0", - "DatePublished": "11/15/2024", + "DatePublished": "12/02/2024", "Version": "1.0", "Legend": "", "TmaVersion": "5.01", @@ -1170,7 +1170,7 @@ } ], "Formula": "100 * ( ( a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( 1 - ( 10 * ( ( ( d ) / e ) * f / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( max( ( ( g / ( g + h ) ) * ( ( e - ( d ) + ( 4 ) * ( ( i / 2 ) if smt_on else j ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( 1 - g / ( k - h ) ) , 0.0001 ) ) / ( ( g / ( g + h ) ) * ( ( e - ( d ) + ( 4 ) * ( ( i / 2 ) if smt_on else j ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) ) * ( ( 4 ) * l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( ( g / ( g + h ) ) * m / ( c ) ) / ( ( ( n + 2 * o ) / ( c ) ) + ( p / ( c ) ) + ( m / ( c ) + ( 9 ) * q / ( c ) ) + ( ( 2 ) * r / ( c ) ) + ( s / ( c ) ) + ( t / ( c ) ) ) - ( ( ( ( ( ( d ) / e ) * f / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) / ( ( ( ( ( d ) + u - v ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( d ) / e ) * f / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) + ( ( ( d ) / e ) * f / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( ( ( 34 ) * ( w + x ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) / ( ( ( d ) / e ) * f / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( ( 4 ) * l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( ( ( 2 ) * r / ( c ) ) + ( m / ( c ) + ( 9 ) * q / ( c ) ) * ( ( ( 1 - ( g / ( g + h ) ) ) * m / ( c ) ) + ( ( g / ( g + h ) ) * m / ( c ) ) * ( 10 * ( ( ( d ) / e ) * f / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( max( ( ( g / ( g + h ) ) * ( ( e - ( d ) + ( 4 ) * ( ( i / 2 ) if smt_on else j ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( 1 - g / ( k - h ) ) , 0.0001 ) ) / ( ( g / ( g + h ) ) * ( ( e - ( d ) + ( 4 ) * ( ( i / 2 ) if smt_on else j ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) ) / ( ( ( g / ( g + h ) ) * m / ( c ) ) + ( ( 1 - ( g / ( g + h ) ) ) * m / ( c ) ) + ( ( 9 ) * q / ( c ) ) ) ) / ( ( ( n + 2 * o ) / ( c ) ) + ( p / ( c ) ) + ( m / ( c ) + ( 9 ) * q / ( c ) ) + ( ( 2 ) * r / ( c ) ) + ( s / ( c ) ) + ( t / ( c ) ) ) ) ) - ( 100 * ( ( 4 ) * l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( ( p / ( c ) ) + ( ( n + 2 * o ) / ( c ) ) + ( ( 9 ) * q / ( c ) ) ) / ( ( ( n + 2 * o ) / ( c ) ) + ( p / ( c ) ) + ( m / ( c ) + ( 9 ) * q / ( c ) ) + ( ( 2 ) * r / ( c ) ) + ( s / ( c ) ) + ( t / ( c ) ) ) )", - "BaseFormula": " 100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( ( tma_microcode_sequencer / ( tma_few_uops_instructions + tma_microcode_sequencer ) ) * ( tma_assists / tma_microcode_sequencer ) ) * tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) ) ) - tma_big_code", + "BaseFormula": " 100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( ( tma_microcode_sequencer / ( tma_few_uops_instructions + tma_microcode_sequencer ) ) * ( tma_assists / tma_microcode_sequencer ) ) * tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) ) ) - tma_bottleneck_big_code", "Category": "TMA", "CountDomain": "Scaled_Slots", "Threshold": { @@ -2777,7 +2777,7 @@ } ], "Formula": "100 - ( ( 100 * ( ( 4 ) * a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( ( d / ( c ) ) + ( ( e + 2 * f ) / ( c ) ) + ( ( 9 ) * g / ( c ) ) ) / ( ( ( e + 2 * f ) / ( c ) ) + ( d / ( c ) ) + ( h / ( c ) + ( 9 ) * g / ( c ) ) + ( ( 2 ) * i / ( c ) ) + ( j / ( c ) ) + ( k / ( c ) ) ) ) + ( 100 * ( ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( 1 - ( 10 * ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( max( ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( 1 - p / ( t - q ) ) , 0.0001 ) ) / ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) ) * ( ( 4 ) * a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( ( p / ( p + q ) ) * h / ( c ) ) / ( ( ( e + 2 * f ) / ( c ) ) + ( d / ( c ) ) + ( h / ( c ) + ( 9 ) * g / ( c ) ) + ( ( 2 ) * i / ( c ) ) + ( j / ( c ) ) + ( k / ( c ) ) ) - ( ( ( ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) / ( ( ( ( ( m ) + u - v ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) + ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( ( ( 34 ) * ( w + x ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) / ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( ( 4 ) * a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( ( ( 2 ) * i / ( c ) ) + ( h / ( c ) + ( 9 ) * g / ( c ) ) * ( ( ( 1 - ( p / ( p + q ) ) ) * h / ( c ) ) + ( ( p / ( p + q ) ) * h / ( c ) ) * ( 10 * ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( max( ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( 1 - p / ( t - q ) ) , 0.0001 ) ) / ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) ) / ( ( ( p / ( p + q ) ) * h / ( c ) ) + ( ( 1 - ( p / ( p + q ) ) ) * h / ( c ) ) + ( ( 9 ) * g / ( c ) ) ) ) / ( ( ( e + 2 * f ) / ( c ) ) + ( d / ( c ) ) + ( h / ( c ) + ( 9 ) * g / ( c ) ) + ( ( 2 ) * i / ( c ) ) + ( j / ( c ) ) + ( k / ( c ) ) ) ) ) - ( 100 * ( ( 4 ) * a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( ( d / ( c ) ) + ( ( e + 2 * f ) / ( c ) ) + ( ( 9 ) * g / ( c ) ) ) / ( ( ( e + 2 * f ) / ( c ) ) + ( d / ( c ) ) + ( h / ( c ) + ( 9 ) * g / ( c ) ) + ( ( 2 ) * i / ( c ) ) + ( j / ( c ) ) + ( k / ( c ) ) ) ) ) + ( 100 * ( 1 - ( 10 * ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( max( ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( 1 - p / ( t - q ) ) , 0.0001 ) ) / ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) ) * ( ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) + ( ( 4 ) * a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( ( p / ( p + q ) ) * h / ( c ) ) / ( ( ( e + 2 * f ) / ( c ) ) + ( d / ( c ) ) + ( h / ( c ) + ( 9 ) * g / ( c ) ) + ( ( 2 ) * i / ( c ) ) + ( j / ( c ) ) + ( k / ( c ) ) ) ) ) + ( 100 * ( ( ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) / ( ( max( ( y - a_e ) / ( c ) , 0 ) ) + ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) + ( ( a_f - a_d ) / ( c ) ) + ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) + ( z / ( c ) ) ) ) * ( ( ( min( c , a_k ) ) / ( c ) ) / ( ( ( min( c , a_k ) ) / ( c ) ) + ( ( min( c , a_l ) ) / ( c ) - ( ( min( c , a_k ) ) / ( c ) ) ) ) ) ) + ( ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( ( ( a_f - a_d ) / ( c ) ) / ( ( max( ( y - a_e ) / ( c ) , 0 ) ) + ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) + ( ( a_f - a_d ) / ( c ) ) + ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) + ( z / ( c ) ) ) ) * ( ( ( ( a_m / 2 ) if smt_on else a_m ) / ( ( b / 2 ) if smt_on else ( c ) ) ) / ( ( ( ( ( 47.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_q * ( a_r / ( a_r + a_s ) ) ) + ( ( 47.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_t ) ) * ( 1 + ( a_h / a_i ) / 2 ) / ( c ) ) + ( ( ( 47.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_u + a_q * ( 1 - ( a_r / ( a_r + a_s ) ) ) ) * ( 1 + ( a_h / a_i ) / 2 ) / ( c ) ) + ( ( ( 20.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_v * ( 1 + ( a_h / a_i ) / 2 ) ) / ( c ) ) + ( ( ( a_m / 2 ) if smt_on else a_m ) / ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) + ( ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( ( max( ( y - a_e ) / ( c ) , 0 ) ) / ( ( max( ( y - a_e ) / ( c ) , 0 ) ) + ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) + ( ( a_f - a_d ) / ( c ) ) + ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) + ( z / ( c ) ) ) ) * ( ( ( a_w / ( a_x + a_y ) ) * a_j / ( c ) ) / ( ( min( ( 9 ) * a_z + b_a , max( b_b - b_c , 0 ) ) / ( c ) ) + ( 13 * b_d / ( c ) ) + ( min( 2 * ( b_e - a_y - a_x ) * dependentloadsweight / 100 , max( b_b - b_c , 0 ) ) / ( c ) ) + ( ( 12 * max( 0 , b_g - b_h ) + ( b_g / b_i ) * ( ( 11 ) * b_j + ( min( c , b_k ) ) ) ) / ( c ) ) + ( ( a_w / ( a_x + a_y ) ) * b_l / ( c ) ) + ( b_m / ( c ) ) + ( ( a_w / ( a_x + a_y ) ) * a_j / ( c ) ) ) ) ) ) ) + ( 100 * ( ( ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) / ( ( max( ( y - a_e ) / ( c ) , 0 ) ) + ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) + ( ( a_f - a_d ) / ( c ) ) + ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) + ( z / ( c ) ) ) ) * ( ( ( min( c , a_l ) ) / ( c ) - ( ( min( c , a_k ) ) / ( c ) ) ) / ( ( ( min( c , a_k ) ) / ( c ) ) + ( ( min( c , a_l ) ) / ( c ) - ( ( min( c , a_k ) ) / ( c ) ) ) ) ) ) + ( ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( ( ( a_f - a_d ) / ( c ) ) / ( ( max( ( y - a_e ) / ( c ) , 0 ) ) + ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) + ( ( a_f - a_d ) / ( c ) ) + ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - 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( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( ( ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) / ( ( max( ( y - a_e ) / ( c ) , 0 ) ) + ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) + ( ( a_f - a_d ) / ( c ) ) + ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) + ( z / ( c ) ) ) ) * ( ( ( min( c , a_l ) ) / ( c ) - ( ( min( c , a_k ) ) / ( c ) ) ) / ( ( ( min( c , a_k ) ) / ( c ) ) + ( ( min( c , a_l ) ) / ( c ) - ( ( min( c , a_k ) ) / ( c ) ) ) ) ) * ( ( ( ( 110 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 20.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_u + ( ( 110 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - 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a_d ) / ( c ) ) / ( ( max( ( y - a_e ) / ( c ) , 0 ) ) + ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) + ( ( a_f - a_d ) / ( c ) ) + ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) + ( z / ( c ) ) ) ) * ( ( ( ( ( 47.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_q * ( a_r / ( a_r + a_s ) ) ) + ( ( 47.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_t ) ) * ( 1 + ( a_h / a_i ) / 2 ) / ( c ) ) + ( ( ( 47.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_u + a_q * ( 1 - ( a_r / ( a_r + a_s ) ) ) ) * ( 1 + ( a_h / a_i ) / 2 ) / ( c ) ) ) / ( ( ( ( ( 47.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_q * ( a_r / ( a_r + a_s ) ) ) + ( ( 47.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_t ) ) * ( 1 + ( a_h / a_i ) / 2 ) / ( c ) ) + ( ( ( 47.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_u + a_q * ( 1 - ( a_r / ( a_r + a_s ) ) ) ) * ( 1 + ( a_h / a_i ) / 2 ) / ( c ) ) + ( ( ( 20.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_v * ( 1 + ( a_h / a_i ) / 2 ) ) / ( c ) ) + ( ( ( a_m / 2 ) if smt_on else a_m ) / ( ( b / 2 ) if smt_on else ( c ) ) ) ) + ( ( z / ( c ) ) / ( ( max( ( y - a_e ) / ( c ) , 0 ) ) + ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) + ( ( a_f - a_d ) / ( c ) ) + ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) + ( z / ( c ) ) ) ) * ( ( ( 110 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * ( b_o + b_p ) + ( 47.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * ( b_q + b_r ) ) / ( c ) ) / ( ( ( ( ( b_j * ( 11 ) * ( 1 - ( b_g / b_i ) ) ) + ( 1 - ( b_g / b_i ) ) * ( min( c , b_k ) ) ) / ( c ) ) + ( ( ( 110 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * ( b_o + b_p ) + ( 47.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * ( b_q + b_r ) ) / ( c ) ) + ( b_n / ( ( b / 2 ) if smt_on else ( c ) ) ) + ( ( ( 9 ) * b_s + b_t ) / ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( b_j * ( 11 ) * ( 1 - ( b_g / b_i ) ) ) + ( 1 - ( b_g / b_i ) ) * ( min( c , b_k ) ) ) / ( c ) ) ) ) + ( ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( 1 - ( max( ( ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( 1 - b_y / q ) , 0.0001 ) ) / ( ( max( ( ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( 1 - b_y / q ) , 0.0001 ) ) ) ) ) ) + ( 100 * ( ( ( ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( b_z / ( c ) ) / ( ( b_z / ( c ) ) + ( c_a / ( c ) ) + ( ( ( c_b / ( c ) ) * ( c ) + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) ) / ( c ) if ( b_z < ( a_a - y ) ) else ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) / ( c ) ) ) ) + ( ( ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( ( ( ( c_b / ( c ) ) * ( c ) + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) ) / ( c ) if ( b_z < ( a_a - y ) ) else ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) / ( c ) ) / ( ( b_z / ( c ) ) + ( c_a / ( c ) ) + ( ( ( c_b / ( c ) ) * ( c ) + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) ) / ( c ) if ( b_z < ( a_a - y ) ) else ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) / ( c ) ) ) ) * ( ( ( c_c / 2 if smt_on else c_c ) / ( ( b / 2 ) if smt_on else ( c ) ) ) / ( ( c_b / ( c ) ) + ( ( ( c_d - c_e ) / 2 if smt_on else a_b ) / ( ( b / 2 ) if smt_on else ( c ) ) ) + ( ( ( c_e - c_c ) / 2 if smt_on else a_c ) / ( ( b / 2 ) if smt_on else ( c ) ) ) + ( ( c_c / 2 if smt_on else c_c ) / ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) ) ) + ( 100 * ( ( ( ( ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) / ( ( ( ( ( m ) + u - v ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) + ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( ( ( 34 ) * ( w + x ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) / ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( ( 4 ) * a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( ( ( 2 ) * i / ( c ) ) + ( h / ( c ) + ( 9 ) * g / ( c ) ) * ( ( ( 1 - ( p / ( p + q ) ) ) * h / ( c ) ) + ( ( p / ( p + q ) ) * h / ( c ) ) * ( 10 * ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( max( ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( 1 - p / ( t - q ) ) , 0.0001 ) ) / ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) ) / ( ( ( p / ( p + q ) ) * h / ( c ) ) + ( ( 1 - ( p / ( p + q ) ) ) * h / ( c ) ) + ( ( 9 ) * g / ( c ) ) ) ) / ( ( ( e + 2 * f ) / ( c ) ) + ( d / ( c ) ) + ( h / ( c ) + ( 9 ) * g / ( c ) ) + ( ( 2 ) * i / ( c ) ) + ( j / ( c ) ) + ( k / ( c ) ) ) ) + ( 10 * ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * ( max( ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( 1 - p / ( t - q ) ) , 0.0001 ) ) / ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) + ( ( ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( max( ( ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( 1 - b_y / q ) , 0.0001 ) ) / ( ( max( ( ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( 1 - b_y / q ) , 0.0001 ) ) ) ) + ( ( ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( ( c_a / ( c ) ) + ( ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if smt_on else s ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * c_f / ( c ) * ( c_b / ( c ) ) ) / ( ( b_z / ( c ) ) + ( c_a / ( c ) ) + ( ( ( c_b / ( c ) ) * ( c ) + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) ) / ( c ) if ( b_z < ( a_a - y ) ) else ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * a_c ) / ( c ) ) ) ) + ( ( ( ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) / ( ( ( ( ( m ) + u - v ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) + ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( ( ( 34 ) * ( w + x ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) / ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( ( ( m ) + u - v ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) ) + ( 100 * ( ( c_g + 2 * c_h + c_i ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) + ( 100 * ( ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( c_g + 2 * c_h + c_i ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) / ( ( ( ( ( m ) + u - v ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) + ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( ( ( 34 ) * ( w + x ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) / ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) * ( ( ( m ) + u - v ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) ) )", - "BaseFormula": " 100 - ( tma_big_code + tma_instruction_fetch_bw + tma_mispredictions + tma_cache_memory_bandwidth + tma_cache_memory_latency + tma_memory_data_tlbs + tma_memory_synchronization + tma_compute_bound_est + tma_irregular_overhead + tma_branching_overhead + tma_useful_work )", + "BaseFormula": " 100 - ( tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottleneck_mispredictions + tma_bottleneck_cache_memory_bandwidth + tma_bottleneck_cache_memory_latency + tma_bottleneck_memory_data_tlbs + tma_bottleneck_memory_synchronization + tma_bottleneck_compute_bound_est + tma_bottleneck_irregular_overhead + tma_bottleneck_branching_overhead + tma_bottleneck_useful_work )", "Category": "TMA", "CountDomain": "Scaled_Slots", "Threshold": { @@ -9230,11 +9230,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_Core_Bound_Likely" + "Value": "metric_TMA_Info_Botlnk_L0_Core_Bound_Likely" } ], "Formula": "a > 0.5", - "BaseFormula": "metric_TMA_Info_Botlnk_Core_Bound_Likely > 0.5", + "BaseFormula": "metric_TMA_Info_Botlnk_L0_Core_Bound_Likely > 0.5", "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", @@ -10508,11 +10508,11 @@ }, { "Alias": "b", - "Value": "IPC" + "Value": "metric_TMA_Info_Thread_IPC" } ], "Formula": "a < 0.7 & b / 4 > 0.35", - "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & IPC / 4 > 0.35", + "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & metric_TMA_Info_Thread_IPC / 4 > 0.35", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", @@ -10825,11 +10825,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_DSB_Misses" + "Value": "metric_TMA_Info_Botlnk_L2_DSB_Misses" } ], "Formula": "a > 10", - "BaseFormula": "metric_TMA_Info_Botlnk_DSB_Misses > 10", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_DSB_Misses > 10", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", @@ -10894,11 +10894,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_DSB_Bandwidth" + "Value": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth" } ], "Formula": "a > 10", - "BaseFormula": "metric_TMA_Info_Botlnk_DSB_Bandwidth > 10", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth > 10", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", @@ -10975,11 +10975,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_IC_Misses" + "Value": "metric_TMA_Info_Botlnk_L2_IC_Misses" } ], "Formula": "a > 5", - "BaseFormula": "metric_TMA_Info_Botlnk_IC_Misses > 5", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_IC_Misses > 5", "ThresholdIssues": "$issueFL" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", @@ -11161,7 +11161,7 @@ } ], "Formula": "( 100 * ( 1 - ( 10 * ( ( ( a ) / b ) * c / ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) ) * ( max( ( ( f / ( f + g ) ) * ( ( b - ( a ) + ( 4 ) * ( ( h / 2 ) if smt_on else i ) ) / ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) ) ) * ( 1 - f / ( j - g ) ) , 0.0001 ) ) / ( ( f / ( f + g ) ) * ( ( b - ( a ) + ( 4 ) * ( ( h / 2 ) if smt_on else i ) ) / ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) ) ) ) ) * ( ( ( f / ( f + g ) ) * ( ( b - ( a ) + ( 4 ) * ( ( h / 2 ) if smt_on else i ) ) / ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) ) ) + ( ( 4 ) * k / ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) ) * ( ( f / ( f + g ) ) * l / ( e ) ) / ( ( ( m + 2 * n ) / ( e ) ) + ( o / ( e ) ) + ( l / ( e ) + ( 9 ) * p / ( e ) ) + ( ( 2 ) * q / ( e ) ) + ( r / ( e ) ) + ( s / ( e ) ) ) ) ) * ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) / ( 4 ) / f / 100", - "BaseFormula": " tma_mispredictions * tma_info_thread_slots / ( 4 ) / br_misp_retired.all_branches / 100", + "BaseFormula": " tma_bottleneck_mispredictions * tma_info_thread_slots / ( 4 ) / br_misp_retired.all_branches / 100", "Category": "TMA", "CountDomain": "Core_Metric", "Threshold": { @@ -11889,11 +11889,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Memory_Page_Walks_Utilization" + "Value": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization" } ], "Formula": "a > 0.5", - "BaseFormula": "metric_TMA_Info_Memory_Page_Walks_Utilization > 0.5", + "BaseFormula": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization > 0.5", "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", diff --git a/SPR/metrics/perf/sapphirerapids_metrics_perf.json b/SPR/metrics/perf/sapphirerapids_metrics_perf.json index ee6e9cb2..97695f07 100644 --- a/SPR/metrics/perf/sapphirerapids_metrics_perf.json +++ b/SPR/metrics/perf/sapphirerapids_metrics_perf.json @@ -403,7 +403,7 @@ }, { "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the back-end)", - "MetricExpr": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\\,cmask\\=0x1@ ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_ms ) ) ) ) - tma_big_code", + "MetricExpr": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\\,cmask\\=0x1@ ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_ms ) ) ) ) - tma_bottleneck_big_code", "MetricGroup": "BvFB;Fed;FetchBW;Frontend;TopdownL1;tma_L1_group;Default;Scaled_Slots", "MetricName": "tma_bottleneck_instruction_fetch_bw", "MetricThreshold": "tma_bottleneck_instruction_fetch_bw > 20", @@ -472,7 +472,7 @@ }, { "BriefDescription": "Total pipeline cost of remaining bottlenecks in the back-end", - "MetricExpr": "100 - ( tma_big_code + tma_instruction_fetch_bw + tma_mispredictions + tma_cache_memory_bandwidth + tma_cache_memory_latency + tma_memory_data_tlbs + tma_memory_synchronization + tma_compute_bound_est + tma_irregular_overhead + tma_branching_overhead + tma_useful_work )", + "MetricExpr": "100 - ( tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottleneck_mispredictions + tma_bottleneck_cache_memory_bandwidth + tma_bottleneck_cache_memory_latency + tma_bottleneck_memory_data_tlbs + tma_bottleneck_memory_synchronization + tma_bottleneck_compute_bound_est + tma_bottleneck_irregular_overhead + tma_bottleneck_branching_overhead + tma_bottleneck_useful_work )", "MetricGroup": "BvOB;Cor;Offcore;TopdownL1;tma_L1_group;Default;Scaled_Slots", "MetricName": "tma_bottleneck_other_bottlenecks", "MetricThreshold": "tma_bottleneck_other_bottlenecks > 20", @@ -1525,7 +1525,7 @@ "MetricExpr": "100 * ( 1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1 ) if tma_info_system_smt_2t_utilization > 0.5 else 0", "MetricGroup": "Cor;SMT;Metric", "MetricName": "tma_info_botlnk_l0_core_bound_likely", - "MetricThreshold": "tma_info_botlnk_core_bound_likely > 0.5" + "MetricThreshold": "tma_info_botlnk_l0_core_bound_likely > 0.5" }, { "BriefDescription": "Instructions Per Cycle (per Logical Processor)", @@ -1568,7 +1568,7 @@ }, { "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor", - "MetricExpr": "tma_info_thread_slots / ( TOPDOWN.SLOTS / 2 ) if #SMT_on else 1", + "MetricExpr": "tma_info_thread_slots / ( slots / 2 ) if #SMT_on else 1", "MetricGroup": "SMT;TmaL1;TopdownL1;tma_L1_group;Metric", "MetricName": "tma_info_thread_slots_utilization" }, @@ -1791,7 +1791,7 @@ "MetricExpr": "IDQ.DSB_UOPS / ( UOPS_ISSUED.ANY )", "MetricGroup": "DSB;Fed;FetchBW;Metric;tma_issueFB", "MetricName": "tma_info_frontend_dsb_coverage", - "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & ipc / 6 > 0.35", + "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 6 > 0.35", "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1849,7 +1849,7 @@ "MetricExpr": "100 * ( tma_fetch_latency * tma_dsb_switches / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_mite / ( tma_mite + tma_dsb + tma_ms ) )", "MetricGroup": "DSBmiss;Fed;Scaled_Slots;tma_issueFB", "MetricName": "tma_info_botlnk_l2_dsb_misses", - "MetricThreshold": "tma_info_botlnk_dsb_misses > 10", + "MetricThreshold": "tma_info_botlnk_l2_dsb_misses > 10", "PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1857,7 +1857,7 @@ "MetricExpr": "100 * ( tma_frontend_bound * ( tma_fetch_bandwidth / ( tma_fetch_latency + tma_fetch_bandwidth ) ) * ( tma_dsb / ( tma_mite + tma_dsb + tma_ms ) ) )", "MetricGroup": "DSB;Fed;FetchBW;Scaled_Slots;tma_issueFB", "MetricName": "tma_info_botlnk_l2_dsb_bandwidth", - "MetricThreshold": "tma_info_botlnk_dsb_bandwidth > 10", + "MetricThreshold": "tma_info_botlnk_l2_dsb_bandwidth > 10", "PublicDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1865,7 +1865,7 @@ "MetricExpr": "100 * ( tma_fetch_latency * tma_icache_misses / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) )", "MetricGroup": "Fed;FetchLat;IcMiss;Scaled_Slots;tma_issueFL", "MetricName": "tma_info_botlnk_l2_ic_misses", - "MetricThreshold": "tma_info_botlnk_ic_misses > 5", + "MetricThreshold": "tma_info_botlnk_l2_ic_misses > 5", "PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck." }, { @@ -1905,7 +1905,7 @@ }, { "BriefDescription": "Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricExpr": "tma_mispredictions * tma_info_thread_slots / ( 6 ) / BR_MISP_RETIRED.ALL_BRANCHES / 100", + "MetricExpr": "tma_bottleneck_mispredictions * tma_info_thread_slots / ( 6 ) / BR_MISP_RETIRED.ALL_BRANCHES / 100", "MetricGroup": "Bad;BrMispredicts;Core_Metric;tma_issueBM", "MetricName": "tma_info_bad_spec_branch_misprediction_cost", "PublicDescription": "Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_bottleneck_mispredictions, tma_branch_mispredicts, tma_mispredicts_resteers." @@ -2048,7 +2048,7 @@ "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 4 * tma_info_core_core_clks )", "MetricGroup": "Mem;MemoryTLB;Core_Metric", "MetricName": "tma_info_memory_tlb_page_walks_utilization", - "MetricThreshold": "tma_info_memory_page_walks_utilization > 0.5" + "MetricThreshold": "tma_info_memory_tlb_page_walks_utilization > 0.5" }, { "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", @@ -2109,7 +2109,7 @@ "MetricExpr": "L2_LINES_OUT.USELESS_HWPF / ( L2_LINES_OUT.SILENT + L2_LINES_OUT.NON_SILENT )", "MetricGroup": "Prefetches;Metric", "MetricName": "tma_info_memory_prefetches_useless_hwpf", - "MetricThreshold": "tma_info_memory_useless_hwpf > 0.15" + "MetricThreshold": "tma_info_memory_prefetches_useless_hwpf > 0.15" }, { "BriefDescription": "Average Latency for L2 cache miss demand Loads", diff --git a/SPR/metrics/perf/sapphirerapidshbm_metrics_perf.json b/SPR/metrics/perf/sapphirerapidshbm_metrics_perf.json index f10cb0a6..29484783 100644 --- a/SPR/metrics/perf/sapphirerapidshbm_metrics_perf.json +++ b/SPR/metrics/perf/sapphirerapidshbm_metrics_perf.json @@ -403,7 +403,7 @@ }, { "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the back-end)", - "MetricExpr": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\\,cmask\\=0x1@ ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_ms ) ) ) ) - tma_big_code", + "MetricExpr": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\\,cmask\\=0x1@ ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_ms ) ) ) ) - tma_bottleneck_big_code", "MetricGroup": "BvFB;Fed;FetchBW;Frontend;TopdownL1;tma_L1_group;Default;Scaled_Slots", "MetricName": "tma_bottleneck_instruction_fetch_bw", "MetricThreshold": "tma_bottleneck_instruction_fetch_bw > 20", @@ -472,7 +472,7 @@ }, { "BriefDescription": "Total pipeline cost of remaining bottlenecks in the back-end", - "MetricExpr": "100 - ( tma_big_code + tma_instruction_fetch_bw + tma_mispredictions + tma_cache_memory_bandwidth + tma_cache_memory_latency + tma_memory_data_tlbs + tma_memory_synchronization + tma_compute_bound_est + tma_irregular_overhead + tma_branching_overhead + tma_useful_work )", + "MetricExpr": "100 - ( tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottleneck_mispredictions + tma_bottleneck_cache_memory_bandwidth + tma_bottleneck_cache_memory_latency + tma_bottleneck_memory_data_tlbs + tma_bottleneck_memory_synchronization + tma_bottleneck_compute_bound_est + tma_bottleneck_irregular_overhead + tma_bottleneck_branching_overhead + tma_bottleneck_useful_work )", "MetricGroup": "BvOB;Cor;Offcore;TopdownL1;tma_L1_group;Default;Scaled_Slots", "MetricName": "tma_bottleneck_other_bottlenecks", "MetricThreshold": "tma_bottleneck_other_bottlenecks > 20", @@ -1533,7 +1533,7 @@ "MetricExpr": "100 * ( 1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1 ) if tma_info_system_smt_2t_utilization > 0.5 else 0", "MetricGroup": "Cor;SMT;Metric", "MetricName": "tma_info_botlnk_l0_core_bound_likely", - "MetricThreshold": "tma_info_botlnk_core_bound_likely > 0.5" + "MetricThreshold": "tma_info_botlnk_l0_core_bound_likely > 0.5" }, { "BriefDescription": "Instructions Per Cycle (per Logical Processor)", @@ -1576,7 +1576,7 @@ }, { "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor", - "MetricExpr": "tma_info_thread_slots / ( TOPDOWN.SLOTS / 2 ) if #SMT_on else 1", + "MetricExpr": "tma_info_thread_slots / ( slots / 2 ) if #SMT_on else 1", "MetricGroup": "SMT;TmaL1;TopdownL1;tma_L1_group;Metric", "MetricName": "tma_info_thread_slots_utilization" }, @@ -1799,7 +1799,7 @@ "MetricExpr": "IDQ.DSB_UOPS / ( UOPS_ISSUED.ANY )", "MetricGroup": "DSB;Fed;FetchBW;Metric;tma_issueFB", "MetricName": "tma_info_frontend_dsb_coverage", - "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & ipc / 6 > 0.35", + "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 6 > 0.35", "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1857,7 +1857,7 @@ "MetricExpr": "100 * ( tma_fetch_latency * tma_dsb_switches / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_mite / ( tma_mite + tma_dsb + tma_ms ) )", "MetricGroup": "DSBmiss;Fed;Scaled_Slots;tma_issueFB", "MetricName": "tma_info_botlnk_l2_dsb_misses", - "MetricThreshold": "tma_info_botlnk_dsb_misses > 10", + "MetricThreshold": "tma_info_botlnk_l2_dsb_misses > 10", "PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1865,7 +1865,7 @@ "MetricExpr": "100 * ( tma_frontend_bound * ( tma_fetch_bandwidth / ( tma_fetch_latency + tma_fetch_bandwidth ) ) * ( tma_dsb / ( tma_mite + tma_dsb + tma_ms ) ) )", "MetricGroup": "DSB;Fed;FetchBW;Scaled_Slots;tma_issueFB", "MetricName": "tma_info_botlnk_l2_dsb_bandwidth", - "MetricThreshold": "tma_info_botlnk_dsb_bandwidth > 10", + "MetricThreshold": "tma_info_botlnk_l2_dsb_bandwidth > 10", "PublicDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1873,7 +1873,7 @@ "MetricExpr": "100 * ( tma_fetch_latency * tma_icache_misses / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) )", "MetricGroup": "Fed;FetchLat;IcMiss;Scaled_Slots;tma_issueFL", "MetricName": "tma_info_botlnk_l2_ic_misses", - "MetricThreshold": "tma_info_botlnk_ic_misses > 5", + "MetricThreshold": "tma_info_botlnk_l2_ic_misses > 5", "PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck." }, { @@ -1913,7 +1913,7 @@ }, { "BriefDescription": "Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricExpr": "tma_mispredictions * tma_info_thread_slots / ( 6 ) / BR_MISP_RETIRED.ALL_BRANCHES / 100", + "MetricExpr": "tma_bottleneck_mispredictions * tma_info_thread_slots / ( 6 ) / BR_MISP_RETIRED.ALL_BRANCHES / 100", "MetricGroup": "Bad;BrMispredicts;Core_Metric;tma_issueBM", "MetricName": "tma_info_bad_spec_branch_misprediction_cost", "PublicDescription": "Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_bottleneck_mispredictions, tma_branch_mispredicts, tma_mispredicts_resteers." @@ -2056,7 +2056,7 @@ "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 4 * tma_info_core_core_clks )", "MetricGroup": "Mem;MemoryTLB;Core_Metric", "MetricName": "tma_info_memory_tlb_page_walks_utilization", - "MetricThreshold": "tma_info_memory_page_walks_utilization > 0.5" + "MetricThreshold": "tma_info_memory_tlb_page_walks_utilization > 0.5" }, { "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", @@ -2117,7 +2117,7 @@ "MetricExpr": "L2_LINES_OUT.USELESS_HWPF / ( L2_LINES_OUT.SILENT + L2_LINES_OUT.NON_SILENT )", "MetricGroup": "Prefetches;Metric", "MetricName": "tma_info_memory_prefetches_useless_hwpf", - "MetricThreshold": "tma_info_memory_useless_hwpf > 0.15" + "MetricThreshold": "tma_info_memory_prefetches_useless_hwpf > 0.15" }, { "BriefDescription": "Average Latency for L2 cache miss demand Loads", diff --git a/SPR/metrics/sapphirerapids_metrics.json b/SPR/metrics/sapphirerapids_metrics.json index 3fc7e13d..a8e520f8 100644 --- a/SPR/metrics/sapphirerapids_metrics.json +++ b/SPR/metrics/sapphirerapids_metrics.json @@ -2,7 +2,7 @@ "Header": { "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.", "Info": "Performance Monitoring Metrics for 4th Generation Intel(R) Xeon(R) Processor Scalable Family based on Sapphire Rapids microarchitecture0", - "DatePublished": "11/15/2024", + "DatePublished": "12/02/2024", "Version": "1.0", "Legend": "", "TmaVersion": "5.01", @@ -1569,7 +1569,7 @@ } ], "Formula": "100 * ( ( a / ( a + b + c + d ) - e / ( f ) ) - ( 1 - ( 10 * ( g / ( f ) ) * ( max( ( h / ( a + b + c + d ) ) * ( 1 - i / ( j - k ) ) , 0.0001 ) ) / ( h / ( a + b + c + d ) ) ) ) * ( ( l / ( a + b + c + d ) - e / ( f ) ) ) * ( ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * m / ( n ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) - ( ( 1 - w / x ) * ( ( ( l / ( a + b + c + d ) - e / ( f ) ) ) * ( ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) * ( ( ( 1 - ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) ) * m / ( n ) ) + ( ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * m / ( n ) ) * ( max( ( h / ( a + b + c + d ) ) * ( 1 - i / ( j - k ) ) , 0.0001 ) ) / ( h / ( a + b + c + d ) ) ) / ( ( ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * m / ( n ) ) + ( ( 1 - ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) ) * m / ( n ) ) + ( q / ( n ) ) ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) + ( max( 0 , ( a / ( a + b + c + d ) - e / ( f ) ) - ( ( l / ( a + b + c + d ) - e / ( f ) ) ) ) ) * ( max( y , x / ( s / t ) ) / ( z if smt_on else ( n ) ) / 2 ) / ( ( ( a_a - a_b ) / ( z if smt_on else ( n ) ) / 2 ) + ( ( a_c - a_d ) / ( z if smt_on else ( n ) ) / 2 ) + ( max( y , x / ( s / t ) ) / ( z if smt_on else ( n ) ) / 2 ) ) ) ) ) - ( 100 * ( ( l / ( a + b + c + d ) - e / ( f ) ) ) * ( ( p / ( n ) ) + ( o / ( n ) ) + ( q / ( n ) ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) )", - "BaseFormula": " 100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - inst_retired.rep_iteration / uops_retired.ms:c1 ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_ms ) ) ) ) - tma_big_code", + "BaseFormula": " 100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - inst_retired.rep_iteration / uops_retired.ms:c1 ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_ms ) ) ) ) - tma_bottleneck_big_code", "Category": "TMA", "CountDomain": "Scaled_Slots", "Threshold": { @@ -3164,7 +3164,7 @@ } ], "Formula": "100 - ( ( 100 * ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( h / ( i ) ) + ( j / ( i ) ) + ( k / ( i ) ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) ) + ( 100 * ( ( b / ( b + c + d + e ) - f / ( g ) ) - ( 1 - ( 10 * ( r / ( g ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) ) * ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) - ( ( 1 - w / x ) * ( ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) * ( ( ( 1 - ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * l / ( i ) ) + ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) / ( ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) + ( ( 1 - ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * l / ( i ) ) + ( k / ( i ) ) ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) + ( max( 0 , ( b / ( b + c + d + e ) - f / ( g ) ) - ( ( a / ( b + c + d + e ) - f / ( g ) ) ) ) ) * ( max( y , x / ( n / o ) ) / ( z if smt_on else ( i ) ) / 2 ) / ( ( ( a_a - a_b ) / ( z if smt_on else ( i ) ) / 2 ) + ( ( a_c - a_d ) / ( z if smt_on else ( i ) ) / 2 ) + ( max( y , x / ( n / o ) ) / ( z if smt_on else ( i ) ) / 2 ) ) ) ) ) - ( 100 * ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( h / ( i ) ) + ( j / ( i ) ) + ( k / ( i ) ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) ) ) + ( 100 * ( 1 - ( 10 * ( r / ( g ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) ) * ( ( s / ( b + c + d + e ) ) + ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) ) ) + ( 100 * ( ( ( a_e / ( b + c + d + e ) ) * ( ( ( a_f / ( i ) ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( min( i , a_k ) ) / ( i ) ) / ( ( ( min( i , a_k ) ) / ( i ) ) + ( ( min( i , a_l ) ) / ( i ) - ( ( min( i , a_k ) ) / ( i ) ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( ( a_i - a_f ) / ( i ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( a_m + a_n ) / ( i ) ) / ( ( ( ( ( 81 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_r * ( a_s / ( a_s + a_t ) ) ) + ( ( 79 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_u ) ) * ( 1 + ( a_v / a_w ) / 2 ) / ( i ) ) + ( ( ( 79 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_x + a_r * ( 1 - ( a_s / ( a_s + a_t ) ) ) ) * ( 1 + ( a_v / a_w ) / 2 ) / ( i ) ) + ( ( ( 37 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_y * ( 1 + ( a_v / a_w ) / 2 ) ) / ( i ) ) + ( ( a_m + a_n ) / ( i ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( a_z / ( i ) ) / ( ( min( ( 7 ) * b_a + b_b , max( b_c - b_d , 0 ) ) / ( i ) ) + ( 13 * b_e / ( i ) ) + ( min( 2 * ( b_f - a_v - a_w ) * dependentloadsweight / 100 , max( b_c - b_d , 0 ) ) / ( i ) ) + ( ( 16 * max( 0 , b_h - b_i ) + ( b_h / b_j ) * ( ( 10 ) * b_k + ( min( i , b_l ) ) ) ) / ( i ) ) + ( ( b_m / b_n ) * b_o / ( i ) ) + ( a_z / ( i ) ) ) ) ) ) ) + ( 100 * ( ( ( a_e / ( b + c + d + e ) ) * ( ( ( a_f / ( i ) ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( min( i , a_l ) ) / ( i ) - ( ( min( i , a_k ) ) / ( i ) ) ) / ( ( ( min( i , a_k ) ) / ( i ) ) + ( ( min( i , a_l ) ) / ( i ) - ( ( min( i , a_k ) ) / ( i ) ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( ( a_i - a_f ) / ( i ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( ( 37 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_y * ( 1 + ( a_v / a_w ) / 2 ) ) / ( i ) ) / ( ( ( ( ( 81 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_r * ( a_s / ( a_s + a_t ) ) ) + ( ( 79 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_u ) ) * ( 1 + ( a_v / a_w ) / 2 ) / ( i ) ) + ( ( ( 79 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_x + a_r * ( 1 - ( a_s / ( a_s + a_t ) ) ) ) * ( 1 + ( a_v / a_w ) / 2 ) / ( i ) ) + ( ( ( 37 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_y * ( 1 + ( a_v / a_w ) / 2 ) ) / ( i ) ) + ( ( a_m + a_n ) / ( i ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( a_h - a_i ) / ( i ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( min( 2 * ( b_f - a_v - a_w ) * dependentloadsweight / 100 , max( b_c - b_d , 0 ) ) / ( i ) ) / ( ( min( ( 7 ) * b_a + b_b , max( b_c - b_d , 0 ) ) / ( i ) ) + ( 13 * b_e / ( i ) ) + ( min( 2 * ( b_f - a_v - a_w ) * dependentloadsweight / 100 , max( b_c - b_d , 0 ) ) / ( i ) ) + ( ( 16 * max( 0 , b_h - b_i ) + ( b_h / b_j ) * ( ( 10 ) * b_k + ( min( i , b_l ) ) ) ) / ( i ) ) + ( ( b_m / b_n ) * b_o / ( i ) ) + ( a_z / ( i ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( 16 * max( 0 , b_h - b_i ) + ( b_h / b_j ) * ( ( 10 ) * b_k + ( min( i , b_l ) ) ) ) / ( i ) ) / ( ( min( ( 7 ) * b_a + b_b , max( b_c - b_d , 0 ) ) / ( i ) ) + ( 13 * b_e / ( i ) ) + ( min( 2 * ( b_f - a_v - a_w ) * dependentloadsweight / 100 , max( b_c - b_d , 0 ) ) / ( i ) ) + ( ( 16 * max( 0 , b_h - b_i ) + ( b_h / b_j ) * ( ( 10 ) * b_k + ( min( i , b_l ) ) ) ) / ( i ) ) + ( ( b_m / b_n ) * b_o / ( i ) ) + ( a_z / ( i ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( b_m / b_n ) * b_o / ( i ) ) / ( ( min( ( 7 ) * b_a + b_b , max( b_c - b_d , 0 ) ) / ( i ) ) + ( 13 * b_e / ( i ) ) + ( min( 2 * ( b_f - a_v - a_w ) * dependentloadsweight / 100 , max( b_c - b_d , 0 ) ) / ( i ) ) + ( ( 16 * max( 0 , b_h - b_i ) + ( b_h / b_j ) * ( ( 10 ) * b_k + ( min( i , b_l ) ) ) ) / ( i ) ) + ( ( b_m / b_n ) * b_o / ( i ) ) + ( a_z / ( i ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( a_j / ( i ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( b_p / ( z if smt_on else ( i ) ) ) / ( ( ( ( b_q * ( 10 ) * ( 1 - ( b_h / b_j ) ) ) + ( 1 - ( b_h / b_j ) ) * ( min( i , b_l ) ) ) / ( i ) ) + ( ( ( 170 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_r + ( 81 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_s ) / ( i ) ) + ( b_p / ( z if smt_on else ( i ) ) ) + ( 9 * b_t / ( i ) ) + ( ( ( 7 ) * b_u + b_v ) / ( z if smt_on else ( i ) ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( a_j / ( i ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( ( b_q * ( 10 ) * ( 1 - ( b_h / b_j ) ) ) + ( 1 - ( b_h / b_j ) ) * ( min( i , b_l ) ) ) / ( i ) ) / ( ( ( ( b_q * ( 10 ) * ( 1 - ( b_h / b_j ) ) ) + ( 1 - ( b_h / b_j ) ) * ( min( i , b_l ) ) ) / ( i ) ) + ( ( ( 170 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_r + ( 81 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_s ) / ( i ) ) + ( b_p / ( z if smt_on else ( i ) ) ) + ( 9 * b_t / ( i ) ) + ( ( ( 7 ) * b_u + b_v ) / ( z if smt_on else ( i ) ) ) ) ) ) ) ) + ( 100 * ( ( a_e / ( b + c + d + e ) ) * ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) / max( ( a_e / ( b + c + d + e ) ) , ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) ) * ( ( min( ( 7 ) * b_a + b_b , max( b_c - b_d , 0 ) ) / ( i ) ) / max( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) , ( ( min( ( 7 ) * b_a + b_b , max( b_c - b_d , 0 ) ) / ( i ) ) + ( 13 * b_e / ( i ) ) + ( min( 2 * ( b_f - a_v - a_w ) * dependentloadsweight / 100 , max( b_c - b_d , 0 ) ) / ( i ) ) + ( ( 16 * max( 0 , b_h - b_i ) + ( b_h / b_j ) * ( ( 10 ) * b_k + ( min( i , b_l ) ) ) ) / ( i ) ) + ( ( b_m / b_n ) * b_o / ( i ) ) + ( a_z / ( i ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( a_j / ( i ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( ( 7 ) * b_u + b_v ) / ( z if smt_on else ( i ) ) ) / ( ( ( ( b_q * ( 10 ) * ( 1 - ( b_h / b_j ) ) ) + ( 1 - ( b_h / b_j ) ) * ( min( i , b_l ) ) ) / ( i ) ) + ( ( ( 170 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_r + ( 81 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_s ) / ( i ) ) + ( b_p / ( z if smt_on else ( i ) ) ) + ( 9 * b_t / ( i ) ) + ( ( ( 7 ) * b_u + b_v ) / ( z if smt_on else ( i ) ) ) ) ) ) ) ) + ( 100 * ( ( a_e / ( b + c + d + e ) ) * ( ( ( ( a_f / ( i ) ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( min( i , a_l ) ) / ( i ) - ( ( min( i , a_k ) ) / ( i ) ) ) / ( ( ( min( i , a_k ) ) / ( i ) ) + ( ( min( i , a_l ) ) / ( i ) - ( ( min( i , a_k ) ) / ( i ) ) ) ) ) * ( ( ( ( 170 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_w + ( ( 170 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_x ) * ( 1 + ( a_v / a_w ) / 2 ) / ( i ) ) / ( ( ( ( 109 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_y * ( 1 + ( a_v / a_w ) / 2 ) / ( i ) ) + ( ( ( 190 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_z * ( 1 + ( a_v / a_w ) / 2 ) / ( i ) ) + ( ( ( ( 170 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_w + ( ( 170 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_x ) * ( 1 + ( a_v / a_w ) / 2 ) / ( i ) ) ) + ( ( ( a_i - a_f ) / ( i ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( ( ( 81 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_r * ( a_s / ( a_s + a_t ) ) ) + ( ( 79 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_u ) ) * ( 1 + ( a_v / a_w ) / 2 ) / ( i ) ) + ( ( ( 79 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_x + a_r * ( 1 - ( a_s / ( a_s + a_t ) ) ) ) * ( 1 + ( a_v / a_w ) / 2 ) / ( i ) ) ) / ( ( ( ( ( 81 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_r * ( a_s / ( a_s + a_t ) ) ) + ( ( 79 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_u ) ) * ( 1 + ( a_v / a_w ) / 2 ) / ( i ) ) + ( ( ( 79 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_x + a_r * ( 1 - ( a_s / ( a_s + a_t ) ) ) ) * ( 1 + ( a_v / a_w ) / 2 ) / ( i ) ) + ( ( ( 37 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_y * ( 1 + ( a_v / a_w ) / 2 ) ) / ( i ) ) + ( ( a_m + a_n ) / ( i ) ) ) + ( ( a_j / ( i ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( 170 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_r + ( 81 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_s ) / ( i ) ) / ( ( ( ( ( b_q * ( 10 ) * ( 1 - ( b_h / b_j ) ) ) + ( 1 - ( b_h / b_j ) ) * ( min( i , b_l ) ) ) / ( i ) ) + ( ( ( 170 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_r + ( 81 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_s ) / ( i ) ) + ( b_p / ( z if smt_on else ( i ) ) ) + ( 9 * b_t / ( i ) ) + ( ( ( 7 ) * b_u + b_v ) / ( z if smt_on else ( i ) ) ) ) - ( ( ( b_q * ( 10 ) * ( 1 - ( b_h / b_j ) ) ) + ( 1 - ( b_h / b_j ) ) * ( min( i , b_l ) ) ) / ( i ) ) ) ) + ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - c_a / v ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - c_a / v ) , 0.0001 ) ) ) ) ) ) + ( 100 * ( ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_e / ( b + c + d + e ) ) ) ) * ( c_b / ( i ) ) / ( ( c_b / ( i ) ) + ( c_c / ( i ) + ( c_d / ( i ) ) ) + ( c_e / ( z if smt_on else ( i ) ) ) + ( ( ( ( c_f + max( c_g - c_c , 0 ) ) / ( i ) * ( c_h - a_g ) / ( i ) ) * ( i ) + ( c_i + ( d / ( b + c + d + e ) ) * c_j ) ) / ( i ) if ( c_b < ( c_h - a_g ) ) else ( c_i + ( d / ( b + c + d + e ) ) * c_j ) / ( i ) ) ) ) + ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_e / ( b + c + d + e ) ) ) ) * ( c_e / ( z if smt_on else ( i ) ) ) / ( ( c_b / ( i ) ) + ( c_c / ( i ) + ( c_d / ( i ) ) ) + ( c_e / ( z if smt_on else ( i ) ) ) + ( ( ( ( c_f + max( c_g - c_c , 0 ) ) / ( i ) * ( c_h - a_g ) / ( i ) ) * ( i ) + ( c_i + ( d / ( b + c + d + e ) ) * c_j ) ) / ( i ) if ( c_b < ( c_h - a_g ) ) else ( c_i + ( d / ( b + c + d + e ) ) * c_j ) / ( i ) ) ) ) + ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_e / ( b + c + d + e ) ) ) ) * ( ( ( ( ( c_f + max( c_g - c_c , 0 ) ) / ( i ) * ( c_h - a_g ) / ( i ) ) * ( i ) + ( c_i + ( d / ( b + c + d + e ) ) * c_j ) ) / ( i ) if ( c_b < ( c_h - a_g ) ) else ( c_i + ( d / ( b + c + d + e ) ) * c_j ) / ( i ) ) / ( ( c_b / ( i ) ) + ( c_c / ( i ) + ( c_d / ( i ) ) ) + ( c_e / ( z if smt_on else ( i ) ) ) + ( ( ( ( c_f + max( c_g - c_c , 0 ) ) / ( i ) * ( c_h - a_g ) / ( i ) ) * ( i ) + ( c_i + ( d / ( b + c + d + e ) ) * c_j ) ) / ( i ) if ( c_b < ( c_h - a_g ) ) else ( c_i + ( d / ( b + c + d + e ) ) * c_j ) / ( i ) ) ) ) * ( ( c_k / ( i ) ) / ( ( ( c_f + max( c_g - c_c , 0 ) ) / ( i ) * ( c_h - a_g ) / ( i ) ) + ( c_i / ( i ) ) + ( c_l / ( i ) ) + ( c_k / ( i ) ) ) ) ) ) ) + ( 100 * ( ( ( 1 - w / x ) * ( ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) * ( ( ( 1 - ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * l / ( i ) ) + ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) / ( ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) + ( ( 1 - ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * l / ( i ) ) + ( k / ( i ) ) ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) + ( max( 0 , ( b / ( b + c + d + e ) - f / ( g ) ) - ( ( a / ( b + c + d + e ) - f / ( g ) ) ) ) ) * ( max( y , x / ( n / o ) ) / ( z if smt_on else ( i ) ) / 2 ) / ( ( ( a_a - a_b ) / ( z if smt_on else ( i ) ) / 2 ) + ( ( a_c - a_d ) / ( z if smt_on else ( i ) ) / 2 ) + ( max( y , x / ( n / o ) ) / ( z if smt_on else ( i ) ) / 2 ) ) ) ) + ( 10 * ( r / ( g ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) * ( s / ( b + c + d + e ) ) + ( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - c_a / v ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - c_a / v ) , 0.0001 ) ) ) ) + ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_e / ( b + c + d + e ) ) ) ) * ( ( c_c / ( i ) + ( c_d / ( i ) ) ) + c_g / ( i ) * ( ( c_f + max( c_g - c_c , 0 ) ) / ( i ) * ( c_h - a_g ) / ( i ) ) ) / ( ( c_b / ( i ) ) + ( c_c / ( i ) + ( c_d / ( i ) ) ) + ( c_e / ( z if smt_on else ( i ) ) ) + ( ( ( ( c_f + max( c_g - c_c , 0 ) ) / ( i ) * ( c_h - a_g ) / ( i ) ) * ( i ) + ( c_i + ( d / ( b + c + d + e ) ) * c_j ) ) / ( i ) if ( c_b < ( c_h - a_g ) ) else ( c_i + ( d / ( b + c + d + e ) ) * c_j ) / ( i ) ) ) ) + ( ( ( ( r / ( g ) ) / ( ( max( 0 , ( c_m / ( b + c + d + e ) ) - ( r / ( g ) ) ) ) + ( r / ( g ) ) ) ) * ( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * c_n / ( g ) ) / ( r / ( g ) ) ) ) * ( c_m / ( b + c + d + e ) ) ) ) ) + ( 100 * ( ( c_o + 2 * c_p + c_q ) / ( g ) ) ) + ( 100 * ( ( d / ( b + c + d + e ) ) - ( ( c_o + 2 * c_p + c_q ) / ( g ) ) - ( ( ( ( r / ( g ) ) / ( ( max( 0 , ( c_m / ( b + c + d + e ) ) - ( r / ( g ) ) ) ) + ( r / ( g ) ) ) ) * ( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * c_n / ( g ) ) / ( r / ( g ) ) ) ) * ( c_m / ( b + c + d + e ) ) ) ) ) )", - "BaseFormula": " 100 - ( tma_big_code + tma_instruction_fetch_bw + tma_mispredictions + tma_cache_memory_bandwidth + tma_cache_memory_latency + tma_memory_data_tlbs + tma_memory_synchronization + tma_compute_bound_est + tma_irregular_overhead + tma_branching_overhead + tma_useful_work )", + "BaseFormula": " 100 - ( tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottleneck_mispredictions + tma_bottleneck_cache_memory_bandwidth + tma_bottleneck_cache_memory_latency + tma_bottleneck_memory_data_tlbs + tma_bottleneck_memory_synchronization + tma_bottleneck_compute_bound_est + tma_bottleneck_irregular_overhead + tma_bottleneck_branching_overhead + tma_bottleneck_useful_work )", "Category": "TMA", "CountDomain": "Scaled_Slots", "Threshold": { @@ -10065,11 +10065,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_Core_Bound_Likely" + "Value": "metric_TMA_Info_Botlnk_L0_Core_Bound_Likely" } ], "Formula": "a > 0.5", - "BaseFormula": "metric_TMA_Info_Botlnk_Core_Bound_Likely > 0.5", + "BaseFormula": "metric_TMA_Info_Botlnk_L0_Core_Bound_Likely > 0.5", "ThresholdIssues": "" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -11575,11 +11575,11 @@ }, { "Alias": "b", - "Value": "IPC" + "Value": "metric_TMA_Info_Thread_IPC" } ], "Formula": "a < 0.7 & b / 6 > 0.35", - "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & IPC / 6 > 0.35", + "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & metric_TMA_Info_Thread_IPC / 6 > 0.35", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -11954,11 +11954,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_DSB_Misses" + "Value": "metric_TMA_Info_Botlnk_L2_DSB_Misses" } ], "Formula": "a > 10", - "BaseFormula": "metric_TMA_Info_Botlnk_DSB_Misses > 10", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_DSB_Misses > 10", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -12059,11 +12059,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_DSB_Bandwidth" + "Value": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth" } ], "Formula": "a > 10", - "BaseFormula": "metric_TMA_Info_Botlnk_DSB_Bandwidth > 10", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth > 10", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -12155,11 +12155,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_IC_Misses" + "Value": "metric_TMA_Info_Botlnk_L2_IC_Misses" } ], "Formula": "a > 5", - "BaseFormula": "metric_TMA_Info_Botlnk_IC_Misses > 5", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_IC_Misses > 5", "ThresholdIssues": "$issueFL" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -12444,7 +12444,7 @@ ], "Constants": [], "Formula": "( 100 * ( 1 - ( 10 * ( a / ( b ) ) * ( max( ( c / ( d + e + f + g ) ) * ( 1 - h / ( i - j ) ) , 0.0001 ) ) / ( c / ( d + e + f + g ) ) ) ) * ( ( c / ( d + e + f + g ) ) + ( ( k / ( d + e + f + g ) - l / ( b ) ) ) * ( ( ( c / ( d + e + f + g ) ) / ( max( 1 - ( ( d / ( d + e + f + g ) - l / ( b ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) ) * m / ( n ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) ) ) * ( b ) / ( 6 ) / h / 100", - "BaseFormula": " tma_mispredictions * tma_info_thread_slots / ( 6 ) / br_misp_retired.all_branches / 100", + "BaseFormula": " tma_bottleneck_mispredictions * tma_info_thread_slots / ( 6 ) / br_misp_retired.all_branches / 100", "Category": "TMA", "CountDomain": "Core_Metric", "Threshold": { @@ -13202,11 +13202,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Memory_Page_Walks_Utilization" + "Value": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization" } ], "Formula": "a > 0.5", - "BaseFormula": "metric_TMA_Info_Memory_Page_Walks_Utilization > 0.5", + "BaseFormula": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization > 0.5", "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", @@ -13516,11 +13516,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Memory_Useless_HWPF" + "Value": "metric_TMA_Info_Memory_Prefetches_Useless_HWPF" } ], "Formula": "a > 0.15", - "BaseFormula": "metric_TMA_Info_Memory_Useless_HWPF > 0.15", + "BaseFormula": "metric_TMA_Info_Memory_Prefetches_Useless_HWPF > 0.15", "ThresholdIssues": "" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", diff --git a/SPR/metrics/sapphirerapidshbm_metrics.json b/SPR/metrics/sapphirerapidshbm_metrics.json index 30110c32..4080ad37 100644 --- a/SPR/metrics/sapphirerapidshbm_metrics.json +++ b/SPR/metrics/sapphirerapidshbm_metrics.json @@ -2,8 +2,8 @@ "Header": { "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.", "Info": "Performance Monitoring Metrics for 4th Generation Intel(R) Xeon(R) Processor Scalable Family based on Sapphire Rapids microarchitecture0", - "DatePublished": "11/20/2024", - "Version": "0", + "DatePublished": "12/02/2024", + "Version": "1.0", "Legend": "", "TmaVersion": "5.01", "TmaFlavor": "Full" @@ -1569,7 +1569,7 @@ } ], "Formula": "100 * ( ( a / ( a + b + c + d ) - e / ( f ) ) - ( 1 - ( 10 * ( g / ( f ) ) * ( max( ( h / ( a + b + c + d ) ) * ( 1 - i / ( j - k ) ) , 0.0001 ) ) / ( h / ( a + b + c + d ) ) ) ) * ( ( l / ( a + b + c + d ) - e / ( f ) ) ) * ( ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * m / ( n ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) - ( ( 1 - w / x ) * ( ( ( l / ( a + b + c + d ) - e / ( f ) ) ) * ( ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) * ( ( ( 1 - ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) ) * m / ( n ) ) + ( ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * m / ( n ) ) * ( max( ( h / ( a + b + c + d ) ) * ( 1 - i / ( j - k ) ) , 0.0001 ) ) / ( h / ( a + b + c + d ) ) ) / ( ( ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * m / ( n ) ) + ( ( 1 - ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) ) * m / ( n ) ) + ( q / ( n ) ) ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) + ( max( 0 , ( a / ( a + b + c + d ) - e / ( f ) ) - ( ( l / ( a + b + c + d ) - e / ( f ) ) ) ) ) * ( max( y , x / ( s / t ) ) / ( z if smt_on else ( n ) ) / 2 ) / ( ( ( a_a - a_b ) / ( z if smt_on else ( n ) ) / 2 ) + ( ( a_c - a_d ) / ( z if smt_on else ( n ) ) / 2 ) + ( max( y , x / ( s / t ) ) / ( z if smt_on else ( n ) ) / 2 ) ) ) ) ) - ( 100 * ( ( l / ( a + b + c + d ) - e / ( f ) ) ) * ( ( p / ( n ) ) + ( o / ( n ) ) + ( q / ( n ) ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) )", - "BaseFormula": " 100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - inst_retired.rep_iteration / uops_retired.ms:c1 ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_ms ) ) ) ) - tma_big_code", + "BaseFormula": " 100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - inst_retired.rep_iteration / uops_retired.ms:c1 ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_ms ) ) ) ) - tma_bottleneck_big_code", "Category": "TMA", "CountDomain": "Scaled_Slots", "Threshold": { @@ -1598,73 +1598,65 @@ "Name": "PERF_METRICS.MEMORY_BOUND", "Alias": "a" }, - { - "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", - "Alias": "a_a" - }, - { - "Name": "MEM_LOAD_RETIRED.L3_HIT", - "Alias": "a_b" - }, { "Name": "L1D_PEND_MISS.FB_FULL", - "Alias": "a_c" + "Alias": "a_a" }, { "Name": "DTLB_LOAD_MISSES.STLB_HIT:c1", - "Alias": "a_d" + "Alias": "a_b" }, { "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", - "Alias": "a_e" + "Alias": "a_c" }, { "Name": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", - "Alias": "a_f" + "Alias": "a_d" }, { "Name": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", - "Alias": "a_g" + "Alias": "a_e" }, { "Name": "LD_BLOCKS.STORE_FORWARD", - "Alias": "a_h" + "Alias": "a_f" }, { "Name": "MEM_INST_RETIRED.ALL_LOADS", - "Alias": "a_i" + "Alias": "a_g" }, { "Name": "MEM_INST_RETIRED.LOCK_LOADS", - "Alias": "a_k" + "Alias": "a_i" }, { "Name": "L2_RQSTS.ALL_RFO", - "Alias": "a_l" + "Alias": "a_j" }, { "Name": "MEM_INST_RETIRED.ALL_STORES", - "Alias": "a_m" + "Alias": "a_k" }, { "Name": "L2_RQSTS.RFO_HIT", - "Alias": "a_n" + "Alias": "a_l" }, { "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", - "Alias": "a_o" + "Alias": "a_m" }, { "Name": "L1D_PEND_MISS.PENDING", - "Alias": "a_p" + "Alias": "a_n" }, { "Name": "MEM_LOAD_COMPLETED.L1_MISS_ANY", - "Alias": "a_q" + "Alias": "a_o" }, { "Name": "LD_BLOCKS.NO_SR", - "Alias": "a_r" + "Alias": "a_p" }, { "Name": "PERF_METRICS.FRONTEND_BOUND", @@ -1691,71 +1683,71 @@ "Alias": "g" }, { - "Name": "OCR.DEMAND_DATA_RD.PMM", + "Name": "MEMORY_ACTIVITY.STALLS_L2_MISS", "Alias": "h" }, { - "Name": "OCR.READS_TO_CORE.L3_MISS", + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", "Alias": "i" }, { - "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Name": "MEMORY_ACTIVITY.STALLS_L1D_MISS", "Alias": "j" }, { - "Name": "MEMORY_ACTIVITY.STALLS_L1D_MISS", + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", "Alias": "k" }, { - "Name": "MEMORY_ACTIVITY.STALLS_L2_MISS", + "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4", "Alias": "l" }, { - "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", "Alias": "m" }, { - "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4", + "Name": "XQ.FULL_CYCLES", "Alias": "n" }, { - "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Name": "L1D_PEND_MISS.L2_STALLS", "Alias": "o" }, { - "Name": "XQ.FULL_CYCLES", + "Name": "CPU_CLK_UNHALTED.REF_TSC", "Alias": "p" }, { - "Name": "L1D_PEND_MISS.L2_STALLS", - "Alias": "q" + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "Alias": "s" }, { - "Name": "CPU_CLK_UNHALTED.REF_TSC", - "Alias": "r" + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "Alias": "t" }, { - "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "Alias": "u" }, { - "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", "Alias": "v" }, { - "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Name": "MEM_LOAD_RETIRED.FB_HIT", "Alias": "w" }, { - "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "Name": "MEM_LOAD_RETIRED.L1_MISS", "Alias": "x" }, { - "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", "Alias": "y" }, { - "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Name": "MEM_LOAD_RETIRED.L3_HIT", "Alias": "z" } ], @@ -1770,10 +1762,10 @@ }, { "Name": "SYSTEM_TSC_FREQ", - "Alias": "s" + "Alias": "q" } ], - "Formula": "( 100 * ( ( ( a / ( b + c + d + e ) ) * ( ( ( f / ( g ) ) - ( ( f / ( g ) ) * h / i ) ) / ( ( max( ( j - k ) / ( g ) , 0 ) ) + ( ( k - l ) / ( g ) ) + ( ( l - f ) / ( g ) ) + ( ( f / ( g ) ) * h / i ) + ( ( f / ( g ) ) - ( ( f / ( g ) ) * h / i ) ) + ( m / ( g ) ) ) ) * ( ( ( min( g , n ) ) / ( g ) ) / ( ( ( min( g , n ) ) / ( g ) ) + ( ( min( g , o ) ) / ( g ) - ( ( min( g , n ) ) / ( g ) ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( f / ( g ) ) * h / i ) / ( ( max( ( j - k ) / ( g ) , 0 ) ) + ( ( k - l ) / ( g ) ) + ( ( l - f ) / ( g ) ) + ( ( f / ( g ) ) * h / i ) + ( ( f / ( g ) ) - ( ( f / ( g ) ) * h / i ) ) + ( m / ( g ) ) ) ) * ( ( min( g , n ) ) / ( g ) ) / ( ( ( min( g , n ) ) / ( g ) ) + ( ( min( g , o ) ) / ( g ) - ( ( min( g , n ) ) / ( g ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( ( l - f ) / ( g ) ) / ( ( max( ( j - k ) / ( g ) , 0 ) ) + ( ( k - l ) / ( g ) ) + ( ( l - f ) / ( g ) ) + ( ( f / ( g ) ) * h / i ) + ( ( f / ( g ) ) - ( ( f / ( g ) ) * h / i ) ) + ( m / ( g ) ) ) ) * ( ( ( p + q ) / ( g ) ) / ( ( ( ( ( 81 * ( ( ( g ) / r ) * s / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / r ) * s / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( u * ( v / ( v + w ) ) ) + ( ( 79 * ( ( ( g ) / r ) * s / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / r ) * s / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( x ) ) * ( 1 + ( y / z ) / 2 ) / ( g ) ) + ( ( ( 79 * ( ( ( g ) / r ) * s / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / r ) * s / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_a + u * ( 1 - ( v / ( v + w ) ) ) ) * ( 1 + ( y / z ) / 2 ) / ( g ) ) + ( ( ( 37 * ( ( ( g ) / r ) * s / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / r ) * s / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_b * ( 1 + ( y / z ) / 2 ) ) / ( g ) ) + ( ( p + q ) / ( g ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( max( ( j - k ) / ( g ) , 0 ) ) / ( ( max( ( j - k ) / ( g ) , 0 ) ) + ( ( k - l ) / ( g ) ) + ( ( l - f ) / ( g ) ) + ( ( f / ( g ) ) * h / i ) + ( ( f / ( g ) ) - ( ( f / ( g ) ) * h / i ) ) + ( m / ( g ) ) ) ) * ( ( a_c / ( g ) ) / ( ( min( ( 7 ) * a_d + a_e , max( a_f - a_g , 0 ) ) / ( g ) ) + ( 13 * a_h / ( g ) ) + ( min( 2 * ( a_i - y - z ) * dependentloadsweight / 100 , max( a_f - a_g , 0 ) ) / ( g ) ) + ( ( 16 * max( 0 , a_k - a_l ) + ( a_k / a_m ) * ( ( 10 ) * a_n + ( min( g , a_o ) ) ) ) / ( g ) ) + ( ( a_p / a_q ) * a_r / ( g ) ) + ( a_c / ( g ) ) ) ) ) ) )", + "Formula": "( 100 * ( ( ( a / ( b + c + d + e ) ) * ( ( ( f / ( g ) ) - ( ( h - f ) / ( g ) ) ) / ( ( max( ( i - j ) / ( g ) , 0 ) ) + ( ( j - h ) / ( g ) ) + ( ( h - f ) / ( g ) ) + ( ( h - f ) / ( g ) ) + ( ( f / ( g ) ) - ( ( h - f ) / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( min( g , l ) ) / ( g ) ) / ( ( ( min( g , l ) ) / ( g ) ) + ( ( min( g , m ) ) / ( g ) - ( ( min( g , l ) ) / ( g ) ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( h - f ) / ( g ) ) / ( ( max( ( i - j ) / ( g ) , 0 ) ) + ( ( j - h ) / ( g ) ) + ( ( h - f ) / ( g ) ) + ( ( h - f ) / ( g ) ) + ( ( f / ( g ) ) - ( ( h - f ) / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( min( g , l ) ) / ( g ) ) / ( ( ( min( g , l ) ) / ( g ) ) + ( ( min( g , m ) ) / ( g ) - ( ( min( g , l ) ) / ( g ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( ( h - f ) / ( g ) ) / ( ( max( ( i - j ) / ( g ) , 0 ) ) + ( ( j - h ) / ( g ) ) + ( ( h - f ) / ( g ) ) + ( ( h - f ) / ( g ) ) + ( ( f / ( g ) ) - ( ( h - f ) / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( n + o ) / ( g ) ) / ( ( ( ( ( 81 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( s * ( t / ( t + u ) ) ) + ( ( 79 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( v ) ) * ( 1 + ( w / x ) / 2 ) / ( g ) ) + ( ( ( 79 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( y + s * ( 1 - ( t / ( t + u ) ) ) ) * ( 1 + ( w / x ) / 2 ) / ( g ) ) + ( ( ( 37 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( z * ( 1 + ( w / x ) / 2 ) ) / ( g ) ) + ( ( n + o ) / ( g ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( max( ( i - j ) / ( g ) , 0 ) ) / ( ( max( ( i - j ) / ( g ) , 0 ) ) + ( ( j - h ) / ( g ) ) + ( ( h - f ) / ( g ) ) + ( ( h - f ) / ( g ) ) + ( ( f / ( g ) ) - ( ( h - f ) / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( a_a / ( g ) ) / ( ( min( ( 7 ) * a_b + a_c , max( a_d - a_e , 0 ) ) / ( g ) ) + ( 13 * a_f / ( g ) ) + ( min( 2 * ( a_g - w - x ) * dependentloadsweight / 100 , max( a_d - a_e , 0 ) ) / ( g ) ) + ( ( 16 * max( 0 , a_i - a_j ) + ( a_i / a_k ) * ( ( 10 ) * a_l + ( min( g , a_m ) ) ) ) / ( g ) ) + ( ( a_n / a_o ) * a_p / ( g ) ) + ( a_a / ( g ) ) ) ) ) ) )", "BaseFormula": " ( 100 * ( ( tma_memory_bound * ( tma_dram_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_hbm_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_mem_bandwidth / ( tma_mem_bandwidth + tma_mem_latency ) ) ) + ( tma_memory_bound * tma_hbm_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_hbm_bound + tma_dram_bound + tma_store_bound ) ) * tma_mem_bandwidth / ( tma_mem_bandwidth + tma_mem_latency ) + ( tma_memory_bound * ( tma_l3_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_hbm_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_sq_full / ( tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full ) ) ) + ( tma_memory_bound * ( tma_l1_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_hbm_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_fb_full / ( tma_dtlb_load + tma_store_fwd_blk + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_fb_full ) ) ) ) )", "Category": "TMA", "CountDomain": "Scaled_Slots", @@ -1803,105 +1795,97 @@ "Name": "PERF_METRICS.MEMORY_BOUND", "Alias": "a" }, - { - "Name": "XQ.FULL_CYCLES", - "Alias": "a_a" - }, - { - "Name": "L1D_PEND_MISS.L2_STALLS", - "Alias": "a_b" - }, { "Name": "MEM_INST_RETIRED.ALL_LOADS", - "Alias": "a_c" + "Alias": "a_a" }, { "Name": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", - "Alias": "a_e" + "Alias": "a_c" }, { "Name": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", - "Alias": "a_f" + "Alias": "a_d" }, { "Name": "DTLB_LOAD_MISSES.STLB_HIT:c1", - "Alias": "a_g" + "Alias": "a_e" }, { "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", - "Alias": "a_h" + "Alias": "a_f" }, { "Name": "LD_BLOCKS.STORE_FORWARD", - "Alias": "a_i" + "Alias": "a_g" }, { "Name": "MEM_INST_RETIRED.LOCK_LOADS", - "Alias": "a_j" + "Alias": "a_h" }, { "Name": "L2_RQSTS.ALL_RFO", - "Alias": "a_k" + "Alias": "a_i" }, { "Name": "MEM_INST_RETIRED.ALL_STORES", - "Alias": "a_l" + "Alias": "a_j" }, { "Name": "L2_RQSTS.RFO_HIT", - "Alias": "a_m" + "Alias": "a_k" }, { "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", - "Alias": "a_n" + "Alias": "a_l" }, { "Name": "L1D_PEND_MISS.PENDING", - "Alias": "a_o" + "Alias": "a_m" }, { "Name": "MEM_LOAD_COMPLETED.L1_MISS_ANY", - "Alias": "a_p" + "Alias": "a_n" }, { "Name": "LD_BLOCKS.NO_SR", - "Alias": "a_q" + "Alias": "a_o" }, { "Name": "L1D_PEND_MISS.FB_FULL", - "Alias": "a_r" + "Alias": "a_p" }, { "Name": "MEM_INST_RETIRED.SPLIT_STORES", - "Alias": "a_s" + "Alias": "a_q" }, { "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", - "Alias": "a_t" + "Alias": "a_r" }, { "Name": "MEM_STORE_RETIRED.L2_HIT", - "Alias": "a_u" + "Alias": "a_s" }, { "Name": "OCR.DEMAND_RFO.L3_MISS:ocr_msr_val=0x103b800002", - "Alias": "a_v" + "Alias": "a_t" }, { "Name": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", - "Alias": "a_w" + "Alias": "a_u" }, { "Name": "OCR.STREAMING_WR.ANY_RESPONSE", - "Alias": "a_x" + "Alias": "a_v" }, { "Name": "DTLB_STORE_MISSES.STLB_HIT:c1", - "Alias": "a_y" + "Alias": "a_w" }, { "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", - "Alias": "a_z" + "Alias": "a_x" }, { "Name": "PERF_METRICS.FRONTEND_BOUND", @@ -1928,71 +1912,71 @@ "Alias": "g" }, { - "Name": "OCR.DEMAND_DATA_RD.PMM", + "Name": "MEMORY_ACTIVITY.STALLS_L2_MISS", "Alias": "h" }, { - "Name": "OCR.READS_TO_CORE.L3_MISS", + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", "Alias": "i" }, { - "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Name": "MEMORY_ACTIVITY.STALLS_L1D_MISS", "Alias": "j" }, { - "Name": "MEMORY_ACTIVITY.STALLS_L1D_MISS", + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", "Alias": "k" }, { - "Name": "MEMORY_ACTIVITY.STALLS_L2_MISS", + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", "Alias": "l" }, { - "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4", "Alias": "m" }, { - "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Name": "CPU_CLK_UNHALTED.REF_TSC", "Alias": "n" }, { - "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4", - "Alias": "o" + "Name": "MEM_LOAD_RETIRED.L3_HIT", + "Alias": "q" }, { - "Name": "CPU_CLK_UNHALTED.REF_TSC", - "Alias": "p" + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "r" }, { - "Name": "MEM_LOAD_RETIRED.L3_HIT", + "Name": "MEM_LOAD_RETIRED.L1_MISS", "Alias": "s" }, { - "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", "Alias": "t" }, { - "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", "Alias": "u" }, { - "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "Alias": "v" }, { - "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", "Alias": "w" }, { - "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", "Alias": "x" }, { - "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "Name": "XQ.FULL_CYCLES", "Alias": "y" }, { - "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", + "Name": "L1D_PEND_MISS.L2_STALLS", "Alias": "z" } ], @@ -2007,7 +1991,7 @@ }, { "Name": "SYSTEM_TSC_FREQ", - "Alias": "q" + "Alias": "o" }, { "Name": "HYPERTHREADING_ON", @@ -2018,7 +2002,7 @@ "Alias": "threads" } ], - "Formula": "100 * ( ( ( a / ( b + c + d + e ) ) * ( ( ( f / ( g ) ) - ( ( f / ( g ) ) * h / i ) ) / ( ( max( ( j - k ) / ( g ) , 0 ) ) + ( ( k - l ) / ( g ) ) + ( ( l - f ) / ( g ) ) + ( ( f / ( g ) ) * h / i ) + ( ( f / ( g ) ) - ( ( f / ( g ) ) * h / i ) ) + ( m / ( g ) ) ) ) * ( ( ( min( g , n ) ) / ( g ) - ( ( min( g , o ) ) / ( g ) ) ) / ( ( ( min( g , o ) ) / ( g ) ) + ( ( min( g , n ) ) / ( g ) - ( ( min( g , o ) ) / ( g ) ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( f / ( g ) ) * h / i ) / ( ( max( ( j - k ) / ( g ) , 0 ) ) + ( ( k - l ) / ( g ) ) + ( ( l - f ) / ( g ) ) + ( ( f / ( g ) ) * h / i ) + ( ( f / ( g ) ) - ( ( f / ( g ) ) * h / i ) ) + ( m / ( g ) ) ) ) * ( ( min( g , n ) ) / ( g ) - ( ( min( g , o ) ) / ( g ) ) ) / ( ( ( min( g , o ) ) / ( g ) ) + ( ( min( g , n ) ) / ( g ) - ( ( min( g , o ) ) / ( g ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( ( l - f ) / ( g ) ) / ( ( max( ( j - k ) / ( g ) , 0 ) ) + ( ( k - l ) / ( g ) ) + ( ( l - f ) / ( g ) ) + ( ( f / ( g ) ) * h / i ) + ( ( f / ( g ) ) - ( ( f / ( g ) ) * h / i ) ) + ( m / ( g ) ) ) ) * ( ( ( ( 37 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( s * ( 1 + ( t / u ) / 2 ) ) / ( g ) ) / ( ( ( ( ( 81 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( v * ( w / ( w + x ) ) ) + ( ( 79 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( y ) ) * ( 1 + ( t / u ) / 2 ) / ( g ) ) + ( ( ( 79 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( z + v * ( 1 - ( w / ( w + x ) ) ) ) * ( 1 + ( t / u ) / 2 ) / ( g ) ) + ( ( ( 37 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( s * ( 1 + ( t / u ) / 2 ) ) / ( g ) ) + ( ( a_a + a_b ) / ( g ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( k - l ) / ( g ) ) / ( ( max( ( j - k ) / ( g ) , 0 ) ) + ( ( k - l ) / ( g ) ) + ( ( l - f ) / ( g ) ) + ( ( f / ( g ) ) * h / i ) + ( ( f / ( g ) ) - ( ( f / ( g ) ) * h / i ) ) + ( m / ( g ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( max( ( j - k ) / ( g ) , 0 ) ) / ( ( max( ( j - k ) / ( g ) , 0 ) ) + ( ( k - l ) / ( g ) ) + ( ( l - f ) / ( g ) ) + ( ( f / ( g ) ) * h / i ) + ( ( f / ( g ) ) - ( ( f / ( g ) ) * h / i ) ) + ( m / ( g ) ) ) ) * ( ( min( 2 * ( a_c - t - u ) * dependentloadsweight / 100 , max( a_e - a_f , 0 ) ) / ( g ) ) / ( ( min( ( 7 ) * a_g + a_h , max( a_e - a_f , 0 ) ) / ( g ) ) + ( 13 * a_i / ( g ) ) + ( min( 2 * ( a_c - t - u ) * dependentloadsweight / 100 , max( a_e - a_f , 0 ) ) / ( g ) ) + ( ( 16 * max( 0 , a_j - a_k ) + ( a_j / a_l ) * ( ( 10 ) * a_m + ( min( g , a_n ) ) ) ) / ( g ) ) + ( ( a_o / a_p ) * a_q / ( g ) ) + ( a_r / ( g ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( max( ( j - k ) / ( g ) , 0 ) ) / ( ( max( ( j - k ) / ( g ) , 0 ) ) + ( ( k - l ) / ( g ) ) + ( ( l - f ) / ( g ) ) + ( ( f / ( g ) ) * h / i ) + ( ( f / ( g ) ) - ( ( f / ( g ) ) * h / i ) ) + ( m / ( g ) ) ) ) * ( ( ( 16 * max( 0 , a_j - a_k ) + ( a_j / a_l ) * ( ( 10 ) * a_m + ( min( g , a_n ) ) ) ) / ( g ) ) / ( ( min( ( 7 ) * a_g + a_h , max( a_e - a_f , 0 ) ) / ( g ) ) + ( 13 * a_i / ( g ) ) + ( min( 2 * ( a_c - t - u ) * dependentloadsweight / 100 , max( a_e - a_f , 0 ) ) / ( g ) ) + ( ( 16 * max( 0 , a_j - a_k ) + ( a_j / a_l ) * ( ( 10 ) * a_m + ( min( g , a_n ) ) ) ) / ( g ) ) + ( ( a_o / a_p ) * a_q / ( g ) ) + ( a_r / ( g ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( max( ( j - k ) / ( g ) , 0 ) ) / ( ( max( ( j - k ) / ( g ) , 0 ) ) + ( ( k - l ) / ( g ) ) + ( ( l - f ) / ( g ) ) + ( ( f / ( g ) ) * h / i ) + ( ( f / ( g ) ) - ( ( f / ( g ) ) * h / i ) ) + ( m / ( g ) ) ) ) * ( ( ( a_o / a_p ) * a_q / ( g ) ) / ( ( min( ( 7 ) * a_g + a_h , max( a_e - a_f , 0 ) ) / ( g ) ) + ( 13 * a_i / ( g ) ) + ( min( 2 * ( a_c - t - u ) * dependentloadsweight / 100 , max( a_e - a_f , 0 ) ) / ( g ) ) + ( ( 16 * max( 0 , a_j - a_k ) + ( a_j / a_l ) * ( ( 10 ) * a_m + ( min( g , a_n ) ) ) ) / ( g ) ) + ( ( a_o / a_p ) * a_q / ( g ) ) + ( a_r / ( g ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( m / ( g ) ) / ( ( max( ( j - k ) / ( g ) , 0 ) ) + ( ( k - l ) / ( g ) ) + ( ( l - f ) / ( g ) ) + ( ( f / ( g ) ) * h / i ) + ( ( f / ( g ) ) - ( ( f / ( g ) ) * h / i ) ) + ( m / ( g ) ) ) ) * ( ( a_s / ( a_t if smt_on else ( g ) ) ) / ( ( ( ( a_u * ( 10 ) * ( 1 - ( a_j / a_l ) ) ) + ( 1 - ( a_j / a_l ) ) * ( min( g , a_n ) ) ) / ( g ) ) + ( ( ( 170 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_v + ( 81 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_w ) / ( g ) ) + ( a_s / ( a_t if smt_on else ( g ) ) ) + ( 9 * a_x / ( g ) ) + ( ( ( 7 ) * a_y + a_z ) / ( a_t if smt_on else ( g ) ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( m / ( g ) ) / ( ( max( ( j - k ) / ( g ) , 0 ) ) + ( ( k - l ) / ( g ) ) + ( ( l - f ) / ( g ) ) + ( ( f / ( g ) ) * h / i ) + ( ( f / ( g ) ) - ( ( f / ( g ) ) * h / i ) ) + ( m / ( g ) ) ) ) * ( ( ( ( a_u * ( 10 ) * ( 1 - ( a_j / a_l ) ) ) + ( 1 - ( a_j / a_l ) ) * ( min( g , a_n ) ) ) / ( g ) ) / ( ( ( ( a_u * ( 10 ) * ( 1 - ( a_j / a_l ) ) ) + ( 1 - ( a_j / a_l ) ) * ( min( g , a_n ) ) ) / ( g ) ) + ( ( ( 170 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_v + ( 81 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_w ) / ( g ) ) + ( a_s / ( a_t if smt_on else ( g ) ) ) + ( 9 * a_x / ( g ) ) + ( ( ( 7 ) * a_y + a_z ) / ( a_t if smt_on else ( g ) ) ) ) ) ) )", + "Formula": "100 * ( ( ( a / ( b + c + d + e ) ) * ( ( ( f / ( g ) ) - ( ( h - f ) / ( g ) ) ) / ( ( max( ( i - j ) / ( g ) , 0 ) ) + ( ( j - h ) / ( g ) ) + ( ( h - f ) / ( g ) ) + ( ( h - f ) / ( g ) ) + ( ( f / ( g ) ) - ( ( h - f ) / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( min( g , l ) ) / ( g ) - ( ( min( g , m ) ) / ( g ) ) ) / ( ( ( min( g , m ) ) / ( g ) ) + ( ( min( g , l ) ) / ( g ) - ( ( min( g , m ) ) / ( g ) ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( h - f ) / ( g ) ) / ( ( max( ( i - j ) / ( g ) , 0 ) ) + ( ( j - h ) / ( g ) ) + ( ( h - f ) / ( g ) ) + ( ( h - f ) / ( g ) ) + ( ( f / ( g ) ) - ( ( h - f ) / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( min( g , l ) ) / ( g ) - ( ( min( g , m ) ) / ( g ) ) ) / ( ( ( min( g , m ) ) / ( g ) ) + ( ( min( g , l ) ) / ( g ) - ( ( min( g , m ) ) / ( g ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( ( h - f ) / ( g ) ) / ( ( max( ( i - j ) / ( g ) , 0 ) ) + ( ( j - h ) / ( g ) ) + ( ( h - f ) / ( g ) ) + ( ( h - f ) / ( g ) ) + ( ( f / ( g ) ) - ( ( h - f ) / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( ( 37 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( q * ( 1 + ( r / s ) / 2 ) ) / ( g ) ) / ( ( ( ( ( 81 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( t * ( u / ( u + v ) ) ) + ( ( 79 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( w ) ) * ( 1 + ( r / s ) / 2 ) / ( g ) ) + ( ( ( 79 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( x + t * ( 1 - ( u / ( u + v ) ) ) ) * ( 1 + ( r / s ) / 2 ) / ( g ) ) + ( ( ( 37 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( q * ( 1 + ( r / s ) / 2 ) ) / ( g ) ) + ( ( y + z ) / ( g ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( j - h ) / ( g ) ) / ( ( max( ( i - j ) / ( g ) , 0 ) ) + ( ( j - h ) / ( g ) ) + ( ( h - f ) / ( g ) ) + ( ( h - f ) / ( g ) ) + ( ( f / ( g ) ) - ( ( h - f ) / ( g ) ) ) + ( k / ( g ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( max( ( i - j ) / ( g ) , 0 ) ) / ( ( max( ( i - j ) / ( g ) , 0 ) ) + ( ( j - h ) / ( g ) ) + ( ( h - f ) / ( g ) ) + ( ( h - f ) / ( g ) ) + ( ( f / ( g ) ) - ( ( h - f ) / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( min( 2 * ( a_a - r - s ) * dependentloadsweight / 100 , max( a_c - a_d , 0 ) ) / ( g ) ) / ( ( min( ( 7 ) * a_e + a_f , max( a_c - a_d , 0 ) ) / ( g ) ) + ( 13 * a_g / ( g ) ) + ( min( 2 * ( a_a - r - s ) * dependentloadsweight / 100 , max( a_c - a_d , 0 ) ) / ( g ) ) + ( ( 16 * max( 0 , a_h - a_i ) + ( a_h / a_j ) * ( ( 10 ) * a_k + ( min( g , a_l ) ) ) ) / ( g ) ) + ( ( a_m / a_n ) * a_o / ( g ) ) + ( a_p / ( g ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( max( ( i - j ) / ( g ) , 0 ) ) / ( ( max( ( i - j ) / ( g ) , 0 ) ) + ( ( j - h ) / ( g ) ) + ( ( h - f ) / ( g ) ) + ( ( h - f ) / ( g ) ) + ( ( f / ( g ) ) - ( ( h - f ) / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( 16 * max( 0 , a_h - a_i ) + ( a_h / a_j ) * ( ( 10 ) * a_k + ( min( g , a_l ) ) ) ) / ( g ) ) / ( ( min( ( 7 ) * a_e + a_f , max( a_c - a_d , 0 ) ) / ( g ) ) + ( 13 * a_g / ( g ) ) + ( min( 2 * ( a_a - r - s ) * dependentloadsweight / 100 , max( a_c - a_d , 0 ) ) / ( g ) ) + ( ( 16 * max( 0 , a_h - a_i ) + ( a_h / a_j ) * ( ( 10 ) * a_k + ( min( g , a_l ) ) ) ) / ( g ) ) + ( ( a_m / a_n ) * a_o / ( g ) ) + ( a_p / ( g ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( max( ( i - j ) / ( g ) , 0 ) ) / ( ( max( ( i - j ) / ( g ) , 0 ) ) + ( ( j - h ) / ( g ) ) + ( ( h - f ) / ( g ) ) + ( ( h - f ) / ( g ) ) + ( ( f / ( g ) ) - ( ( h - f ) / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( a_m / a_n ) * a_o / ( g ) ) / ( ( min( ( 7 ) * a_e + a_f , max( a_c - a_d , 0 ) ) / ( g ) ) + ( 13 * a_g / ( g ) ) + ( min( 2 * ( a_a - r - s ) * dependentloadsweight / 100 , max( a_c - a_d , 0 ) ) / ( g ) ) + ( ( 16 * max( 0 , a_h - a_i ) + ( a_h / a_j ) * ( ( 10 ) * a_k + ( min( g , a_l ) ) ) ) / ( g ) ) + ( ( a_m / a_n ) * a_o / ( g ) ) + ( a_p / ( g ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( k / ( g ) ) / ( ( max( ( i - j ) / ( g ) , 0 ) ) + ( ( j - h ) / ( g ) ) + ( ( h - f ) / ( g ) ) + ( ( h - f ) / ( g ) ) + ( ( f / ( g ) ) - ( ( h - f ) / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( a_q / ( a_r if smt_on else ( g ) ) ) / ( ( ( ( a_s * ( 10 ) * ( 1 - ( a_h / a_j ) ) ) + ( 1 - ( a_h / a_j ) ) * ( min( g , a_l ) ) ) / ( g ) ) + ( ( ( 170 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_t + ( 81 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_u ) / ( g ) ) + ( a_q / ( a_r if smt_on else ( g ) ) ) + ( 9 * a_v / ( g ) ) + ( ( ( 7 ) * a_w + a_x ) / ( a_r if smt_on else ( g ) ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( k / ( g ) ) / ( ( max( ( i - j ) / ( g ) , 0 ) ) + ( ( j - h ) / ( g ) ) + ( ( h - f ) / ( g ) ) + ( ( h - f ) / ( g ) ) + ( ( f / ( g ) ) - ( ( h - f ) / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( ( a_s * ( 10 ) * ( 1 - ( a_h / a_j ) ) ) + ( 1 - ( a_h / a_j ) ) * ( min( g , a_l ) ) ) / ( g ) ) / ( ( ( ( a_s * ( 10 ) * ( 1 - ( a_h / a_j ) ) ) + ( 1 - ( a_h / a_j ) ) * ( min( g , a_l ) ) ) / ( g ) ) + ( ( ( 170 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_t + ( 81 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_u ) / ( g ) ) + ( a_q / ( a_r if smt_on else ( g ) ) ) + ( 9 * a_v / ( g ) ) + ( ( ( 7 ) * a_w + a_x ) / ( a_r if smt_on else ( g ) ) ) ) ) ) )", "BaseFormula": " 100 * ( ( tma_memory_bound * ( tma_dram_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_hbm_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_mem_latency / ( tma_mem_bandwidth + tma_mem_latency ) ) ) + ( tma_memory_bound * tma_hbm_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_hbm_bound + tma_dram_bound + tma_store_bound ) ) * tma_mem_latency / ( tma_mem_bandwidth + tma_mem_latency ) + ( tma_memory_bound * ( tma_l3_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_hbm_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_l3_hit_latency / ( tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full ) ) ) + ( tma_memory_bound * tma_l2_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_hbm_bound + tma_dram_bound + tma_store_bound ) ) + ( tma_memory_bound * ( tma_l1_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_hbm_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_l1_latency_dependency / ( tma_dtlb_load + tma_store_fwd_blk + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_fb_full ) ) ) + ( tma_memory_bound * ( tma_l1_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_hbm_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_lock_latency / ( tma_dtlb_load + tma_store_fwd_blk + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_fb_full ) ) ) + ( tma_memory_bound * ( tma_l1_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_hbm_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_split_loads / ( tma_dtlb_load + tma_store_fwd_blk + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_fb_full ) ) ) + ( tma_memory_bound * ( tma_store_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_hbm_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_split_stores / ( tma_store_latency + tma_false_sharing + tma_split_stores + tma_streaming_stores + tma_dtlb_store ) ) ) + ( tma_memory_bound * ( tma_store_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_hbm_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_store_latency / ( tma_store_latency + tma_false_sharing + tma_split_stores + tma_streaming_stores + tma_dtlb_store ) ) ) )", "Category": "TMA", "CountDomain": "Scaled_Slots", @@ -2048,61 +2032,53 @@ "Name": "PERF_METRICS.MEMORY_BOUND", "Alias": "a" }, - { - "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", - "Alias": "a_a" - }, - { - "Name": "L1D_PEND_MISS.PENDING", - "Alias": "a_b" - }, { "Name": "MEM_LOAD_COMPLETED.L1_MISS_ANY", - "Alias": "a_c" + "Alias": "a_a" }, { "Name": "LD_BLOCKS.NO_SR", - "Alias": "a_d" + "Alias": "a_b" }, { "Name": "L1D_PEND_MISS.FB_FULL", - "Alias": "a_e" + "Alias": "a_c" }, { "Name": "DTLB_STORE_MISSES.STLB_HIT:c1", - "Alias": "a_f" + "Alias": "a_d" }, { "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", - "Alias": "a_g" + "Alias": "a_e" }, { "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", - "Alias": "a_h" + "Alias": "a_f" }, { "Name": "MEM_STORE_RETIRED.L2_HIT", - "Alias": "a_i" + "Alias": "a_g" }, { "Name": "CPU_CLK_UNHALTED.REF_TSC", - "Alias": "a_j" + "Alias": "a_h" }, { "Name": "OCR.DEMAND_RFO.L3_MISS:ocr_msr_val=0x103b800002", - "Alias": "a_m" + "Alias": "a_k" }, { "Name": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", - "Alias": "a_n" + "Alias": "a_l" }, { "Name": "MEM_INST_RETIRED.SPLIT_STORES", - "Alias": "a_o" + "Alias": "a_m" }, { "Name": "OCR.STREAMING_WR.ANY_RESPONSE", - "Alias": "a_p" + "Alias": "a_n" }, { "Name": "PERF_METRICS.FRONTEND_BOUND", @@ -2141,70 +2117,70 @@ "Alias": "j" }, { - "Name": "OCR.DEMAND_DATA_RD.PMM", + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", "Alias": "k" }, { - "Name": "OCR.READS_TO_CORE.L3_MISS", + "Name": "DTLB_LOAD_MISSES.STLB_HIT:c1", "Alias": "l" }, { - "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", "Alias": "m" }, { - "Name": "DTLB_LOAD_MISSES.STLB_HIT:c1", + "Name": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", "Alias": "n" }, { - "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Name": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", "Alias": "o" }, { - "Name": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "Name": "LD_BLOCKS.STORE_FORWARD", "Alias": "p" }, { - "Name": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", + "Name": "MEM_INST_RETIRED.ALL_LOADS", "Alias": "q" }, { - "Name": "LD_BLOCKS.STORE_FORWARD", + "Name": "MEM_LOAD_RETIRED.FB_HIT", "Alias": "r" }, { - "Name": "MEM_INST_RETIRED.ALL_LOADS", + "Name": "MEM_LOAD_RETIRED.L1_MISS", "Alias": "s" }, { - "Name": "MEM_LOAD_RETIRED.FB_HIT", - "Alias": "t" + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "u" }, { - "Name": "MEM_LOAD_RETIRED.L1_MISS", - "Alias": "u" + "Name": "L2_RQSTS.ALL_RFO", + "Alias": "v" }, { - "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Name": "MEM_INST_RETIRED.ALL_STORES", "Alias": "w" }, { - "Name": "L2_RQSTS.ALL_RFO", + "Name": "L2_RQSTS.RFO_HIT", "Alias": "x" }, { - "Name": "MEM_INST_RETIRED.ALL_STORES", + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", "Alias": "y" }, { - "Name": "L2_RQSTS.RFO_HIT", + "Name": "L1D_PEND_MISS.PENDING", "Alias": "z" } ], "Constants": [ { "Name": "SYSTEM_TSC_FREQ", - "Alias": "a_k" + "Alias": "a_i" }, { "Name": "20", @@ -2223,7 +2199,7 @@ "Alias": "threads" } ], - "Formula": "100 * ( ( a / ( b + c + d + e ) ) * ( ( max( ( f - g ) / ( h ) , 0 ) ) / max( ( a / ( b + c + d + e ) ) , ( ( max( ( f - g ) / ( h ) , 0 ) ) + ( ( g - i ) / ( h ) ) + ( ( i - j ) / ( h ) ) + ( ( j / ( h ) ) * k / l ) + ( ( j / ( h ) ) - ( ( j / ( h ) ) * k / l ) ) + ( m / ( h ) ) ) ) ) * ( ( min( ( 7 ) * n + o , max( p - q , 0 ) ) / ( h ) ) / max( ( max( ( f - g ) / ( h ) , 0 ) ) , ( ( min( ( 7 ) * n + o , max( p - q , 0 ) ) / ( h ) ) + ( 13 * r / ( h ) ) + ( min( 2 * ( s - t - u ) * dependentloadsweight / 100 , max( p - q , 0 ) ) / ( h ) ) + ( ( 16 * max( 0 , w - x ) + ( w / y ) * ( ( 10 ) * z + ( min( h , a_a ) ) ) ) / ( h ) ) + ( ( a_b / a_c ) * a_d / ( h ) ) + ( a_e / ( h ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( m / ( h ) ) / ( ( max( ( f - g ) / ( h ) , 0 ) ) + ( ( g - i ) / ( h ) ) + ( ( i - j ) / ( h ) ) + ( ( j / ( h ) ) * k / l ) + ( ( j / ( h ) ) - ( ( j / ( h ) ) * k / l ) ) + ( m / ( h ) ) ) ) * ( ( ( ( 7 ) * a_f + a_g ) / ( a_h if smt_on else ( h ) ) ) / ( ( ( ( a_i * ( 10 ) * ( 1 - ( w / y ) ) ) + ( 1 - ( w / y ) ) * ( min( h , a_a ) ) ) / ( h ) ) + ( ( ( 170 * ( ( ( h ) / a_j ) * a_k / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_m + ( 81 * ( ( ( h ) / a_j ) * a_k / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_n ) / ( h ) ) + ( a_o / ( a_h if smt_on else ( h ) ) ) + ( 9 * a_p / ( h ) ) + ( ( ( 7 ) * a_f + a_g ) / ( a_h if smt_on else ( h ) ) ) ) ) ) )", + "Formula": "100 * ( ( a / ( b + c + d + e ) ) * ( ( max( ( f - g ) / ( h ) , 0 ) ) / max( ( a / ( b + c + d + e ) ) , ( ( max( ( f - g ) / ( h ) , 0 ) ) + ( ( g - i ) / ( h ) ) + ( ( i - j ) / ( h ) ) + ( ( i - j ) / ( h ) ) + ( ( j / ( h ) ) - ( ( i - j ) / ( h ) ) ) + ( k / ( h ) ) ) ) ) * ( ( min( ( 7 ) * l + m , max( n - o , 0 ) ) / ( h ) ) / max( ( max( ( f - g ) / ( h ) , 0 ) ) , ( ( min( ( 7 ) * l + m , max( n - o , 0 ) ) / ( h ) ) + ( 13 * p / ( h ) ) + ( min( 2 * ( q - r - s ) * dependentloadsweight / 100 , max( n - o , 0 ) ) / ( h ) ) + ( ( 16 * max( 0 , u - v ) + ( u / w ) * ( ( 10 ) * x + ( min( h , y ) ) ) ) / ( h ) ) + ( ( z / a_a ) * a_b / ( h ) ) + ( a_c / ( h ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( k / ( h ) ) / ( ( max( ( f - g ) / ( h ) , 0 ) ) + ( ( g - i ) / ( h ) ) + ( ( i - j ) / ( h ) ) + ( ( i - j ) / ( h ) ) + ( ( j / ( h ) ) - ( ( i - j ) / ( h ) ) ) + ( k / ( h ) ) ) ) * ( ( ( ( 7 ) * a_d + a_e ) / ( a_f if smt_on else ( h ) ) ) / ( ( ( ( a_g * ( 10 ) * ( 1 - ( u / w ) ) ) + ( 1 - ( u / w ) ) * ( min( h , y ) ) ) / ( h ) ) + ( ( ( 170 * ( ( ( h ) / a_h ) * a_i / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_k + ( 81 * ( ( ( h ) / a_h ) * a_i / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_l ) / ( h ) ) + ( a_m / ( a_f if smt_on else ( h ) ) ) + ( 9 * a_n / ( h ) ) + ( ( ( 7 ) * a_d + a_e ) / ( a_f if smt_on else ( h ) ) ) ) ) ) )", "BaseFormula": " 100 * ( tma_memory_bound * ( tma_l1_bound / max( tma_memory_bound , ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_hbm_bound + tma_dram_bound + tma_store_bound ) ) ) * ( tma_dtlb_load / max( tma_l1_bound , ( tma_dtlb_load + tma_store_fwd_blk + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_fb_full ) ) ) + ( tma_memory_bound * ( tma_store_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_hbm_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_dtlb_store / ( tma_store_latency + tma_false_sharing + tma_split_stores + tma_streaming_stores + tma_dtlb_store ) ) ) )", "Category": "TMA", "CountDomain": "Scaled_Slots", @@ -2253,93 +2229,85 @@ "Name": "PERF_METRICS.MEMORY_BOUND", "Alias": "a" }, - { - "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", - "Alias": "a_a" - }, - { - "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", - "Alias": "a_b" - }, { "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", - "Alias": "a_c" + "Alias": "a_a" }, { "Name": "MEM_LOAD_RETIRED.L3_HIT", - "Alias": "a_d" + "Alias": "a_b" }, { "Name": "XQ.FULL_CYCLES", - "Alias": "a_e" + "Alias": "a_c" }, { "Name": "L1D_PEND_MISS.L2_STALLS", - "Alias": "a_f" + "Alias": "a_d" }, { "Name": "OCR.DEMAND_RFO.L3_MISS:ocr_msr_val=0x103b800002", - "Alias": "a_g" + "Alias": "a_e" }, { "Name": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", - "Alias": "a_h" + "Alias": "a_f" }, { "Name": "MEM_STORE_RETIRED.L2_HIT", - "Alias": "a_i" + "Alias": "a_g" }, { "Name": "MEM_INST_RETIRED.LOCK_LOADS", - "Alias": "a_j" + "Alias": "a_h" }, { "Name": "MEM_INST_RETIRED.ALL_STORES", - "Alias": "a_k" + "Alias": "a_i" }, { "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", - "Alias": "a_l" + "Alias": "a_j" }, { "Name": "MEM_INST_RETIRED.SPLIT_STORES", - "Alias": "a_m" + "Alias": "a_k" }, { "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", - "Alias": "a_n" + "Alias": "a_l" }, { "Name": "OCR.STREAMING_WR.ANY_RESPONSE", - "Alias": "a_o" + "Alias": "a_m" }, { "Name": "DTLB_STORE_MISSES.STLB_HIT:c1", - "Alias": "a_p" + "Alias": "a_n" }, { "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", - "Alias": "a_q" + "Alias": "a_o" }, { "Name": "INT_MISC.UOP_DROPPING", - "Alias": "a_r" + "Alias": "a_p" }, { "Name": "TOPDOWN.SLOTS:perf_metrics", - "Alias": "a_s" + "Alias": "a_q" }, { "Name": "PERF_METRICS.BRANCH_MISPREDICTS", - "Alias": "a_t" + "Alias": "a_r" }, { "Name": "MACHINE_CLEARS.MEMORY_ORDERING", - "Alias": "a_u" + "Alias": "a_s" }, { "Name": "MACHINE_CLEARS.COUNT", - "Alias": "a_v" + "Alias": "a_t" }, { "Name": "PERF_METRICS.FRONTEND_BOUND", @@ -2366,71 +2334,71 @@ "Alias": "g" }, { - "Name": "OCR.DEMAND_DATA_RD.PMM", + "Name": "MEMORY_ACTIVITY.STALLS_L2_MISS", "Alias": "h" }, { - "Name": "OCR.READS_TO_CORE.L3_MISS", + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", "Alias": "i" }, { - "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Name": "MEMORY_ACTIVITY.STALLS_L1D_MISS", "Alias": "j" }, { - "Name": "MEMORY_ACTIVITY.STALLS_L1D_MISS", + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", "Alias": "k" }, { - "Name": "MEMORY_ACTIVITY.STALLS_L2_MISS", + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", "Alias": "l" }, { - "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4", "Alias": "m" }, { - "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Name": "CPU_CLK_UNHALTED.REF_TSC", "Alias": "n" }, { - "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4", - "Alias": "o" + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", + "Alias": "q" }, { - "Name": "CPU_CLK_UNHALTED.REF_TSC", - "Alias": "p" + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", + "Alias": "r" }, { - "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", + "Name": "MEM_LOAD_RETIRED.FB_HIT", "Alias": "s" }, { - "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", + "Name": "MEM_LOAD_RETIRED.L1_MISS", "Alias": "t" }, { - "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Name": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", "Alias": "u" }, { - "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", "Alias": "v" }, { - "Name": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", "Alias": "w" }, { - "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", "Alias": "x" }, { - "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "Alias": "y" }, { - "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", "Alias": "z" } ], @@ -2441,7 +2409,7 @@ }, { "Name": "SYSTEM_TSC_FREQ", - "Alias": "q" + "Alias": "o" }, { "Name": "HYPERTHREADING_ON", @@ -2452,7 +2420,7 @@ "Alias": "threads" } ], - "Formula": "100 * ( ( a / ( b + c + d + e ) ) * ( ( ( ( f / ( g ) ) - ( ( f / ( g ) ) * h / i ) ) / ( ( max( ( j - k ) / ( g ) , 0 ) ) + ( ( k - l ) / ( g ) ) + ( ( l - f ) / ( g ) ) + ( ( f / ( g ) ) * h / i ) + ( ( f / ( g ) ) - ( ( f / ( g ) ) * h / i ) ) + ( m / ( g ) ) ) ) * ( ( ( min( g , n ) ) / ( g ) - ( ( min( g , o ) ) / ( g ) ) ) / ( ( ( min( g , o ) ) / ( g ) ) + ( ( min( g , n ) ) / ( g ) - ( ( min( g , o ) ) / ( g ) ) ) ) ) * ( ( ( ( 170 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * s + ( ( 170 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * t ) * ( 1 + ( u / v ) / 2 ) / ( g ) ) / ( ( ( ( 109 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * w * ( 1 + ( u / v ) / 2 ) / ( g ) ) + ( ( ( 190 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * x * ( 1 + ( u / v ) / 2 ) / ( g ) ) + ( ( ( ( 170 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * s + ( ( 170 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * t ) * ( 1 + ( u / v ) / 2 ) / ( g ) ) ) + ( ( ( l - f ) / ( g ) ) / ( ( max( ( j - k ) / ( g ) , 0 ) ) + ( ( k - l ) / ( g ) ) + ( ( l - f ) / ( g ) ) + ( ( f / ( g ) ) * h / i ) + ( ( f / ( g ) ) - ( ( f / ( g ) ) * h / i ) ) + ( m / ( g ) ) ) ) * ( ( ( ( ( 81 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( y * ( z / ( z + a_a ) ) ) + ( ( 79 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_b ) ) * ( 1 + ( u / v ) / 2 ) / ( g ) ) + ( ( ( 79 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_c + y * ( 1 - ( z / ( z + a_a ) ) ) ) * ( 1 + ( u / v ) / 2 ) / ( g ) ) ) / ( ( ( ( ( 81 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( y * ( z / ( z + a_a ) ) ) + ( ( 79 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_b ) ) * ( 1 + ( u / v ) / 2 ) / ( g ) ) + ( ( ( 79 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_c + y * ( 1 - ( z / ( z + a_a ) ) ) ) * ( 1 + ( u / v ) / 2 ) / ( g ) ) + ( ( ( 37 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_d * ( 1 + ( u / v ) / 2 ) ) / ( g ) ) + ( ( a_e + a_f ) / ( g ) ) ) + ( ( m / ( g ) ) / ( ( max( ( j - k ) / ( g ) , 0 ) ) + ( ( k - l ) / ( g ) ) + ( ( l - f ) / ( g ) ) + ( ( f / ( g ) ) * h / i ) + ( ( f / ( g ) ) - ( ( f / ( g ) ) * h / i ) ) + ( m / ( g ) ) ) ) * ( ( ( 170 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_g + ( 81 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_h ) / ( g ) ) / ( ( ( ( ( a_i * ( 10 ) * ( 1 - ( a_j / a_k ) ) ) + ( 1 - ( a_j / a_k ) ) * ( min( g , a_l ) ) ) / ( g ) ) + ( ( ( 170 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_g + ( 81 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_h ) / ( g ) ) + ( a_m / ( a_n if smt_on else ( g ) ) ) + ( 9 * a_o / ( g ) ) + ( ( ( 7 ) * a_p + a_q ) / ( a_n if smt_on else ( g ) ) ) ) - ( ( ( a_i * ( 10 ) * ( 1 - ( a_j / a_k ) ) ) + ( 1 - ( a_j / a_k ) ) * ( min( g , a_l ) ) ) / ( g ) ) ) ) + ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - a_r / ( a_s ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( a_t / ( b + c + d + e ) ) ) ) * ( 1 - ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - a_r / ( a_s ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( a_t / ( b + c + d + e ) ) ) ) * ( 1 - a_u / a_v ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - a_r / ( a_s ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( a_t / ( b + c + d + e ) ) ) ) * ( 1 - a_u / a_v ) , 0.0001 ) ) ) ) )", + "Formula": "100 * ( ( a / ( b + c + d + e ) ) * ( ( ( ( f / ( g ) ) - ( ( h - f ) / ( g ) ) ) / ( ( max( ( i - j ) / ( g ) , 0 ) ) + ( ( j - h ) / ( g ) ) + ( ( h - f ) / ( g ) ) + ( ( h - f ) / ( g ) ) + ( ( f / ( g ) ) - ( ( h - f ) / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( min( g , l ) ) / ( g ) - ( ( min( g , m ) ) / ( g ) ) ) / ( ( ( min( g , m ) ) / ( g ) ) + ( ( min( g , l ) ) / ( g ) - ( ( min( g , m ) ) / ( g ) ) ) ) ) * ( ( ( ( 170 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * q + ( ( 170 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * r ) * ( 1 + ( s / t ) / 2 ) / ( g ) ) / ( ( ( ( 109 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * u * ( 1 + ( s / t ) / 2 ) / ( g ) ) + ( ( ( 190 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * v * ( 1 + ( s / t ) / 2 ) / ( g ) ) + ( ( ( ( 170 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * q + ( ( 170 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * r ) * ( 1 + ( s / t ) / 2 ) / ( g ) ) ) + ( ( ( h - f ) / ( g ) ) / ( ( max( ( i - j ) / ( g ) , 0 ) ) + ( ( j - h ) / ( g ) ) + ( ( h - f ) / ( g ) ) + ( ( h - f ) / ( g ) ) + ( ( f / ( g ) ) - ( ( h - f ) / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( ( ( 81 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( w * ( x / ( x + y ) ) ) + ( ( 79 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( z ) ) * ( 1 + ( s / t ) / 2 ) / ( g ) ) + ( ( ( 79 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_a + w * ( 1 - ( x / ( x + y ) ) ) ) * ( 1 + ( s / t ) / 2 ) / ( g ) ) ) / ( ( ( ( ( 81 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( w * ( x / ( x + y ) ) ) + ( ( 79 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( z ) ) * ( 1 + ( s / t ) / 2 ) / ( g ) ) + ( ( ( 79 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_a + w * ( 1 - ( x / ( x + y ) ) ) ) * ( 1 + ( s / t ) / 2 ) / ( g ) ) + ( ( ( 37 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_b * ( 1 + ( s / t ) / 2 ) ) / ( g ) ) + ( ( a_c + a_d ) / ( g ) ) ) + ( ( k / ( g ) ) / ( ( max( ( i - j ) / ( g ) , 0 ) ) + ( ( j - h ) / ( g ) ) + ( ( h - f ) / ( g ) ) + ( ( h - f ) / ( g ) ) + ( ( f / ( g ) ) - ( ( h - f ) / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( 170 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_e + ( 81 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_f ) / ( g ) ) / ( ( ( ( ( a_g * ( 10 ) * ( 1 - ( a_h / a_i ) ) ) + ( 1 - ( a_h / a_i ) ) * ( min( g , a_j ) ) ) / ( g ) ) + ( ( ( 170 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_e + ( 81 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_f ) / ( g ) ) + ( a_k / ( a_l if smt_on else ( g ) ) ) + ( 9 * a_m / ( g ) ) + ( ( ( 7 ) * a_n + a_o ) / ( a_l if smt_on else ( g ) ) ) ) - ( ( ( a_g * ( 10 ) * ( 1 - ( a_h / a_i ) ) ) + ( 1 - ( a_h / a_i ) ) * ( min( g , a_j ) ) ) / ( g ) ) ) ) + ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - a_p / ( a_q ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( a_r / ( b + c + d + e ) ) ) ) * ( 1 - ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - a_p / ( a_q ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( a_r / ( b + c + d + e ) ) ) ) * ( 1 - a_s / a_t ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - a_p / ( a_q ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( a_r / ( b + c + d + e ) ) ) ) * ( 1 - a_s / a_t ) , 0.0001 ) ) ) ) )", "BaseFormula": " 100 * ( tma_memory_bound * ( ( tma_dram_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_hbm_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_mem_latency / ( tma_mem_bandwidth + tma_mem_latency ) ) * tma_remote_cache / ( tma_local_mem + tma_remote_mem + tma_remote_cache ) + ( tma_l3_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_hbm_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_contested_accesses + tma_data_sharing ) / ( tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full ) + ( tma_store_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_hbm_bound + tma_dram_bound + tma_store_bound ) ) * tma_false_sharing / ( ( tma_store_latency + tma_false_sharing + tma_split_stores + tma_streaming_stores + tma_dtlb_store ) - tma_store_latency ) ) + tma_machine_clears * ( 1 - tma_other_nukes / ( tma_other_nukes ) ) )", "Category": "TMA", "CountDomain": "Scaled_Slots", @@ -2833,75 +2801,75 @@ "Alias": "a_f" }, { - "Name": "OCR.DEMAND_DATA_RD.PMM", + "Name": "MEMORY_ACTIVITY.STALLS_L2_MISS", "Alias": "a_g" }, { - "Name": "OCR.READS_TO_CORE.L3_MISS", + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", "Alias": "a_h" }, { - "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Name": "MEMORY_ACTIVITY.STALLS_L1D_MISS", "Alias": "a_i" }, { - "Name": "MEMORY_ACTIVITY.STALLS_L1D_MISS", + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", "Alias": "a_j" }, { - "Name": "MEMORY_ACTIVITY.STALLS_L2_MISS", + "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4", "Alias": "a_k" }, { - "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", "Alias": "a_l" }, { - "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4", + "Name": "XQ.FULL_CYCLES", "Alias": "a_m" }, { - "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Name": "L1D_PEND_MISS.L2_STALLS", "Alias": "a_n" }, { - "Name": "XQ.FULL_CYCLES", + "Name": "CPU_CLK_UNHALTED.REF_TSC", "Alias": "a_o" }, { - "Name": "L1D_PEND_MISS.L2_STALLS", - "Alias": "a_p" + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "Alias": "a_r" }, { - "Name": "CPU_CLK_UNHALTED.REF_TSC", - "Alias": "a_q" + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "Alias": "a_s" }, { - "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "Alias": "a_t" }, { - "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", "Alias": "a_u" }, { - "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Name": "MEM_LOAD_RETIRED.FB_HIT", "Alias": "a_v" }, { - "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "Name": "MEM_LOAD_RETIRED.L1_MISS", "Alias": "a_w" }, { - "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", "Alias": "a_x" }, { - "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Name": "MEM_LOAD_RETIRED.L3_HIT", "Alias": "a_y" }, { - "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", + "Name": "L1D_PEND_MISS.FB_FULL", "Alias": "a_z" }, { @@ -2909,184 +2877,176 @@ "Alias": "b" }, { - "Name": "MEM_LOAD_RETIRED.L3_HIT", + "Name": "DTLB_LOAD_MISSES.STLB_HIT:c1", "Alias": "b_a" }, { - "Name": "L1D_PEND_MISS.FB_FULL", + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", "Alias": "b_b" }, { - "Name": "DTLB_LOAD_MISSES.STLB_HIT:c1", + "Name": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", "Alias": "b_c" }, { - "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Name": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", "Alias": "b_d" }, { - "Name": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "Name": "LD_BLOCKS.STORE_FORWARD", "Alias": "b_e" }, { - "Name": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", + "Name": "MEM_INST_RETIRED.ALL_LOADS", "Alias": "b_f" }, { - "Name": "LD_BLOCKS.STORE_FORWARD", - "Alias": "b_g" + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "b_h" }, { - "Name": "MEM_INST_RETIRED.ALL_LOADS", - "Alias": "b_h" + "Name": "L2_RQSTS.ALL_RFO", + "Alias": "b_i" }, { - "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Name": "MEM_INST_RETIRED.ALL_STORES", "Alias": "b_j" }, { - "Name": "L2_RQSTS.ALL_RFO", + "Name": "L2_RQSTS.RFO_HIT", "Alias": "b_k" }, { - "Name": "MEM_INST_RETIRED.ALL_STORES", + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", "Alias": "b_l" }, { - "Name": "L2_RQSTS.RFO_HIT", + "Name": "L1D_PEND_MISS.PENDING", "Alias": "b_m" }, { - "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "Name": "MEM_LOAD_COMPLETED.L1_MISS_ANY", "Alias": "b_n" }, { - "Name": "L1D_PEND_MISS.PENDING", + "Name": "LD_BLOCKS.NO_SR", "Alias": "b_o" }, { - "Name": "MEM_LOAD_COMPLETED.L1_MISS_ANY", + "Name": "MEM_INST_RETIRED.SPLIT_STORES", "Alias": "b_p" }, { - "Name": "LD_BLOCKS.NO_SR", + "Name": "MEM_STORE_RETIRED.L2_HIT", "Alias": "b_q" }, { - "Name": "MEM_INST_RETIRED.SPLIT_STORES", + "Name": "OCR.DEMAND_RFO.L3_MISS:ocr_msr_val=0x103b800002", "Alias": "b_r" }, { - "Name": "MEM_STORE_RETIRED.L2_HIT", + "Name": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", "Alias": "b_s" }, { - "Name": "OCR.DEMAND_RFO.L3_MISS:ocr_msr_val=0x103b800002", + "Name": "OCR.STREAMING_WR.ANY_RESPONSE", "Alias": "b_t" }, { - "Name": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "Name": "DTLB_STORE_MISSES.STLB_HIT:c1", "Alias": "b_u" }, { - "Name": "OCR.STREAMING_WR.ANY_RESPONSE", + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", "Alias": "b_v" }, { - "Name": "DTLB_STORE_MISSES.STLB_HIT:c1", + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", "Alias": "b_w" }, { - "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", "Alias": "b_x" }, { - "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", + "Name": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", "Alias": "b_y" }, { - "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", "Alias": "b_z" }, { "Name": "PERF_METRICS.BAD_SPECULATION", "Alias": "c" }, - { - "Name": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", - "Alias": "c_a" - }, - { - "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", - "Alias": "c_b" - }, { "Name": "MACHINE_CLEARS.MEMORY_ORDERING", - "Alias": "c_c" + "Alias": "c_a" }, { "Name": "ARITH.DIV_ACTIVE", - "Alias": "c_d" + "Alias": "c_b" }, { "Name": "RESOURCE_STALLS.SCOREBOARD", - "Alias": "c_e" + "Alias": "c_c" }, { "Name": "CPU_CLK_UNHALTED.C02", - "Alias": "c_f" + "Alias": "c_d" }, { "Name": "EXE.AMX_BUSY", - "Alias": "c_g" + "Alias": "c_e" }, { "Name": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", - "Alias": "c_h" + "Alias": "c_f" }, { "Name": "RS.EMPTY_RESOURCE", - "Alias": "c_i" + "Alias": "c_g" }, { "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", - "Alias": "c_j" + "Alias": "c_h" }, { "Name": "EXE_ACTIVITY.1_PORTS_UTIL", - "Alias": "c_k" + "Alias": "c_i" }, { "Name": "EXE_ACTIVITY.2_3_PORTS_UTIL", - "Alias": "c_l" + "Alias": "c_j" }, { "Name": "UOPS_EXECUTED.CYCLES_GE_3", - "Alias": "c_m" + "Alias": "c_k" }, { "Name": "EXE_ACTIVITY.2_PORTS_UTIL", - "Alias": "c_n" + "Alias": "c_l" }, { "Name": "PERF_METRICS.HEAVY_OPERATIONS", - "Alias": "c_o" + "Alias": "c_m" }, { "Name": "ASSISTS.ANY", - "Alias": "c_p" + "Alias": "c_n" }, { "Name": "BR_INST_RETIRED.ALL_BRANCHES", - "Alias": "c_q" + "Alias": "c_o" }, { "Name": "BR_INST_RETIRED.NEAR_CALL", - "Alias": "c_r" + "Alias": "c_p" }, { "Name": "INST_RETIRED.NOP", - "Alias": "c_s" + "Alias": "c_q" }, { "Name": "PERF_METRICS.RETIRING", @@ -3184,7 +3144,7 @@ "Constants": [ { "Name": "SYSTEM_TSC_FREQ", - "Alias": "a_r" + "Alias": "a_p" }, { "Name": "20", @@ -3203,8 +3163,8 @@ "Alias": "threads" } ], - "Formula": "100 - ( ( 100 * ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( h / ( i ) ) + ( j / ( i ) ) + ( k / ( i ) ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) ) + ( 100 * ( ( b / ( b + c + d + e ) - f / ( g ) ) - ( 1 - ( 10 * ( r / ( g ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) ) * ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) - ( ( 1 - w / x ) * ( ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) * ( ( ( 1 - ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * l / ( i ) ) + ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) / ( ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) + ( ( 1 - ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * l / ( i ) ) + ( k / ( i ) ) ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) + ( max( 0 , ( b / ( b + c + d + e ) - f / ( g ) ) - ( ( a / ( b + c + d + e ) - f / ( g ) ) ) ) ) * ( max( y , x / ( n / o ) ) / ( z if smt_on else ( i ) ) / 2 ) / ( ( ( a_a - a_b ) / ( z if smt_on else ( i ) ) / 2 ) + ( ( a_c - a_d ) / ( z if smt_on else ( i ) ) / 2 ) + ( max( y , x / ( n / o ) ) / ( z if smt_on else ( i ) ) / 2 ) ) ) ) ) - ( 100 * ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( h / ( i ) ) + ( j / ( i ) ) + ( k / ( i ) ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) ) ) + ( 100 * ( 1 - ( 10 * ( r / ( g ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) ) * ( ( s / ( b + c + d + e ) ) + ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) ) ) + ( ( 100 * ( ( ( a_e / ( b + c + d + e ) ) * ( ( ( a_f / ( i ) ) - ( ( a_f / ( i ) ) * a_g / a_h ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) * a_g / a_h ) + ( ( a_f / ( i ) ) - ( ( a_f / ( i ) ) * a_g / a_h ) ) + ( a_l / ( i ) ) ) ) * ( ( ( min( i , a_m ) ) / ( i ) ) / ( ( ( min( i , a_m ) ) / ( i ) ) + ( ( min( i , a_n ) ) / ( i ) - ( ( min( i , a_m ) ) / ( i ) ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( a_f / ( i ) ) * a_g / a_h ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) * a_g / a_h ) + ( ( a_f / ( i ) ) - ( ( a_f / ( i ) ) * a_g / a_h ) ) + ( a_l / ( i ) ) ) ) * ( ( min( i , a_m ) ) / ( i ) ) / ( ( ( min( i , a_m ) ) / ( i ) ) + ( ( min( i , a_n ) ) / ( i ) - ( ( min( i , a_m ) ) / ( i ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( ( a_k - a_f ) / ( i ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) * a_g / a_h ) + ( ( a_f / ( i ) ) - ( ( a_f / ( i ) ) * a_g / a_h ) ) + ( a_l / ( i ) ) ) ) * ( ( ( a_o + a_p ) / ( i ) ) / ( ( ( ( ( 81 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_t * ( a_u / ( a_u + a_v ) ) ) + ( ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_w ) ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) + ( ( ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_z + a_t * ( 1 - ( a_u / ( a_u + a_v ) ) ) ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) + ( ( ( 37 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_a * ( 1 + ( a_x / a_y ) / 2 ) ) / ( i ) ) + ( ( a_o + a_p ) / ( i ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) * a_g / a_h ) + ( ( a_f / ( i ) ) - ( ( a_f / ( i ) ) * a_g / a_h ) ) + ( a_l / ( i ) ) ) ) * ( ( b_b / ( i ) ) / ( ( min( ( 7 ) * b_c + b_d , max( b_e - b_f , 0 ) ) / ( i ) ) + ( 13 * b_g / ( i ) ) + ( min( 2 * ( b_h - a_x - a_y ) * dependentloadsweight / 100 , max( b_e - b_f , 0 ) ) / ( i ) ) + ( ( 16 * max( 0 , b_j - b_k ) + ( b_j / b_l ) * ( ( 10 ) * b_m + ( min( i , b_n ) ) ) ) / ( i ) ) + ( ( b_o / b_p ) * b_q / ( i ) ) + ( b_b / ( i ) ) ) ) ) ) ) ) + ( 100 * ( ( ( a_e / ( b + c + d + e ) ) * ( ( ( a_f / ( i ) ) - ( ( a_f / ( i ) ) * a_g / a_h ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) * a_g / a_h ) + ( ( a_f / ( i ) ) - ( ( a_f / ( i ) ) * a_g / a_h ) ) + ( a_l / ( i ) ) ) ) * ( ( ( min( i , a_n ) ) / ( i ) - ( ( min( i , a_m ) ) / ( i ) ) ) / ( ( ( min( i , a_m ) ) / ( i ) ) + ( ( min( i , a_n ) ) / ( i ) - ( ( min( i , a_m ) ) / ( i ) ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( a_f / ( i ) ) * a_g / a_h ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) * a_g / a_h ) + ( ( a_f / ( i ) ) - ( ( a_f / ( i ) ) * a_g / a_h ) ) + ( a_l / ( i ) ) ) ) * ( ( min( i , a_n ) ) / ( i ) - ( ( min( i , a_m ) ) / ( i ) ) ) / ( ( ( min( i , a_m ) ) / ( i ) ) + ( ( min( i , a_n ) ) / ( i ) - ( ( min( i , a_m ) ) / ( i ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( ( a_k - a_f ) / ( i ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) * a_g / a_h ) + ( ( a_f / ( i ) ) - ( ( a_f / ( i ) ) * a_g / a_h ) ) + ( a_l / ( i ) ) ) ) * ( ( ( ( 37 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_a * ( 1 + ( a_x / a_y ) / 2 ) ) / ( i ) ) / ( ( ( ( ( 81 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - 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a_k ) / ( i ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) * a_g / a_h ) + ( ( a_f / ( i ) ) - ( ( a_f / ( i ) ) * a_g / a_h ) ) + ( a_l / ( i ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) * a_g / a_h ) + ( ( a_f / ( i ) ) - ( ( a_f / ( i ) ) * a_g / a_h ) ) + ( a_l / ( i ) ) ) ) * ( ( min( 2 * ( b_h - a_x - a_y ) * dependentloadsweight / 100 , max( b_e - b_f , 0 ) ) / ( i ) ) / ( ( min( ( 7 ) * b_c + b_d , max( b_e - b_f , 0 ) ) / ( i ) ) + ( 13 * b_g / ( i ) ) + ( min( 2 * ( b_h - a_x - a_y ) * dependentloadsweight / 100 , max( b_e - b_f , 0 ) ) / ( i ) ) + ( ( 16 * max( 0 , b_j - b_k ) + ( b_j / b_l ) * ( ( 10 ) * b_m + ( min( i , b_n ) ) ) ) / ( i ) ) + ( ( b_o / b_p ) * b_q / ( i ) ) + ( b_b / ( i ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) / ( ( max( ( a_i - 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a_x - a_y ) * dependentloadsweight / 100 , max( b_e - b_f , 0 ) ) / ( i ) ) + ( ( 16 * max( 0 , b_j - b_k ) + ( b_j / b_l ) * ( ( 10 ) * b_m + ( min( i , b_n ) ) ) ) / ( i ) ) + ( ( b_o / b_p ) * b_q / ( i ) ) + ( b_b / ( i ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( a_l / ( i ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) * a_g / a_h ) + ( ( a_f / ( i ) ) - ( ( a_f / ( i ) ) * a_g / a_h ) ) + ( a_l / ( i ) ) ) ) * ( ( b_r / ( z if smt_on else ( i ) ) ) / ( ( ( ( b_s * ( 10 ) * ( 1 - ( b_j / b_l ) ) ) + ( 1 - ( b_j / b_l ) ) * ( min( i , b_n ) ) ) / ( i ) ) + ( ( ( 170 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_t + ( 81 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_u ) / ( i ) ) + ( b_r / ( z if smt_on else ( i ) ) ) + ( 9 * b_v / ( i ) ) + ( ( ( 7 ) * b_w + b_x ) / ( z if smt_on else ( i ) ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( a_l / ( i ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) * a_g / a_h ) + ( ( a_f / ( i ) ) - ( ( a_f / ( i ) ) * a_g / a_h ) ) + ( a_l / ( i ) ) ) ) * ( ( ( ( b_s * ( 10 ) * ( 1 - ( b_j / b_l ) ) ) + ( 1 - ( b_j / b_l ) ) * ( min( i , b_n ) ) ) / ( i ) ) / ( ( ( ( b_s * ( 10 ) * ( 1 - ( b_j / b_l ) ) ) + ( 1 - ( b_j / b_l ) ) * ( min( i , b_n ) ) ) / ( i ) ) + ( ( ( 170 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_t + ( 81 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_u ) / ( i ) ) + ( b_r / ( z if smt_on else ( i ) ) ) + ( 9 * b_v / ( i ) ) + ( ( ( 7 ) * b_w + b_x ) / ( z if smt_on else ( i ) ) ) ) ) ) ) ) + ( 100 * ( ( a_e / ( b + c + d + e ) ) * ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) / max( ( a_e / ( b + c + d + e ) ) , ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) * a_g / a_h ) + ( ( a_f / ( i ) ) - ( ( a_f / ( i ) ) * a_g / a_h ) ) + ( a_l / ( i ) ) ) ) ) * ( ( min( ( 7 ) * b_c + b_d , max( b_e - b_f , 0 ) ) / ( i ) ) / max( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) , ( ( min( ( 7 ) * b_c + b_d , max( b_e - b_f , 0 ) ) / ( i ) ) + ( 13 * b_g / ( i ) ) + ( min( 2 * ( b_h - a_x - a_y ) * dependentloadsweight / 100 , max( b_e - b_f , 0 ) ) / ( i ) ) + ( ( 16 * max( 0 , b_j - b_k ) + ( b_j / b_l ) * ( ( 10 ) * b_m + ( min( i , b_n ) ) ) ) / ( i ) ) + ( ( b_o / b_p ) * b_q / ( i ) ) + ( b_b / ( i ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( a_l / ( i ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) * a_g / a_h ) + ( ( a_f / ( i ) ) - ( ( a_f / ( i ) ) * a_g / a_h ) ) + ( a_l / ( i ) ) ) ) * ( ( ( ( 7 ) * b_w + b_x ) / ( z if smt_on else ( i ) ) ) / ( ( ( ( b_s * ( 10 ) * ( 1 - ( b_j / b_l ) ) ) + ( 1 - ( b_j / b_l ) ) * ( min( i , b_n ) ) ) / ( i ) ) + ( ( ( 170 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_t + ( 81 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_u ) / ( i ) ) + ( b_r / ( z if smt_on else ( i ) ) ) + ( 9 * b_v / ( i ) ) + ( ( ( 7 ) * b_w + b_x ) / ( z if smt_on else ( i ) ) ) ) ) ) ) ) + ( 100 * ( ( a_e / ( b + c + d + e ) ) * ( ( ( ( a_f / ( i ) ) - ( ( a_f / ( i ) ) * a_g / a_h ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) * a_g / a_h ) + ( ( a_f / ( i ) ) - ( ( a_f / ( i ) ) * a_g / a_h ) ) + ( a_l / ( i ) ) ) ) * ( ( ( min( i , a_n ) ) / ( i ) - ( ( min( i , a_m ) ) / ( i ) ) ) / ( ( ( min( i , a_m ) ) / ( i ) ) + ( ( min( i , a_n ) ) / ( i ) - ( ( min( i , a_m ) ) / ( i ) ) ) ) ) * ( ( ( ( 170 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_y + ( ( 170 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_z ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) / ( ( ( ( 109 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * c_a * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) + ( ( ( 190 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * c_b * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) + ( ( ( ( 170 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_y + ( ( 170 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_z ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) ) + ( ( ( a_k - a_f ) / ( i ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) * a_g / a_h ) + ( ( a_f / ( i ) ) - ( ( a_f / ( i ) ) * a_g / a_h ) ) + ( a_l / ( i ) ) ) ) * ( ( ( ( ( 81 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_t * ( a_u / ( a_u + a_v ) ) ) + ( ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_w ) ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) + ( ( ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_z + a_t * ( 1 - ( a_u / ( a_u + a_v ) ) ) ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) ) / ( ( ( ( ( 81 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_t * ( a_u / ( a_u + a_v ) ) ) + ( ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_w ) ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) + ( ( ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_z + a_t * ( 1 - ( a_u / ( a_u + a_v ) ) ) ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) + ( ( ( 37 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_a * ( 1 + ( a_x / a_y ) / 2 ) ) / ( i ) ) + ( ( a_o + a_p ) / ( i ) ) ) + ( ( a_l / ( i ) ) / ( ( max( ( a_i - a_j ) / ( i ) , 0 ) ) + ( ( a_j - a_k ) / ( i ) ) + ( ( a_k - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) * a_g / a_h ) + ( ( a_f / ( i ) ) - ( ( a_f / ( i ) ) * a_g / a_h ) ) + ( a_l / ( i ) ) ) ) * ( ( ( 170 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_t + ( 81 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_u ) / ( i ) ) / ( ( ( ( ( b_s * ( 10 ) * ( 1 - ( b_j / b_l ) ) ) + ( 1 - ( b_j / b_l ) ) * ( min( i , b_n ) ) ) / ( i ) ) + ( ( ( 170 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_t + ( 81 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_u ) / ( i ) ) + ( b_r / ( z if smt_on else ( i ) ) ) + ( 9 * b_v / ( i ) ) + ( ( ( 7 ) * b_w + b_x ) / ( z if smt_on else ( i ) ) ) ) - ( ( ( b_s * ( 10 ) * ( 1 - ( b_j / b_l ) ) ) + ( 1 - ( b_j / b_l ) ) * ( min( i , b_n ) ) ) / ( i ) ) ) ) + ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - c_c / v ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - c_c / v ) , 0.0001 ) ) ) ) ) ) + ( 100 * ( ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_e / ( b + c + d + e ) ) ) ) * ( c_d / ( i ) ) / ( ( c_d / ( i ) ) + ( c_e / ( i ) + ( c_f / ( i ) ) ) + ( c_g / ( z if smt_on else ( i ) ) ) + ( ( ( ( c_h + max( c_i - c_e , 0 ) ) / ( i ) * ( c_j - a_i ) / ( i ) ) * ( i ) + ( c_k + ( d / ( b + c + d + e ) ) * c_l ) ) / ( i ) if ( c_d < ( c_j - a_i ) ) else ( c_k + ( d / ( b + c + d + e ) ) * c_l ) / ( i ) ) ) ) + ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_e / ( b + c + d + e ) ) ) ) * ( c_g / ( z if smt_on else ( i ) ) ) / ( ( c_d / ( i ) ) + ( c_e / ( i ) + ( c_f / ( i ) ) ) + ( c_g / ( z if smt_on else ( i ) ) ) + ( ( ( ( c_h + max( c_i - c_e , 0 ) ) / ( i ) * ( c_j - a_i ) / ( i ) ) * ( i ) + ( c_k + ( d / ( b + c + d + e ) ) * c_l ) ) / ( i ) if ( c_d < ( c_j - a_i ) ) else ( c_k + ( d / ( b + c + d + e ) ) * c_l ) / ( i ) ) ) ) + ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_e / ( b + c + d + e ) ) ) ) * ( ( ( ( ( c_h + max( c_i - c_e , 0 ) ) / ( i ) * ( c_j - a_i ) / ( i ) ) * ( i ) + ( c_k + ( d / ( b + c + d + e ) ) * c_l ) ) / ( i ) if ( c_d < ( c_j - a_i ) ) else ( c_k + ( d / ( b + c + d + e ) ) * c_l ) / ( i ) ) / ( ( c_d / ( i ) ) + ( c_e / ( i ) + ( c_f / ( i ) ) ) + ( c_g / ( z if smt_on else ( i ) ) ) + ( ( ( ( c_h + max( c_i - c_e , 0 ) ) / ( i ) * ( c_j - a_i ) / ( i ) ) * ( i ) + ( c_k + ( d / ( b + c + d + e ) ) * c_l ) ) / ( i ) if ( c_d < ( c_j - a_i ) ) else ( c_k + ( d / ( b + c + d + e ) ) * c_l ) / ( i ) ) ) ) * ( ( c_m / ( i ) ) / ( ( ( c_h + max( c_i - c_e , 0 ) ) / ( i ) * ( c_j - a_i ) / ( i ) ) + ( c_k / ( i ) ) + ( c_n / ( i ) ) + ( c_m / ( i ) ) ) ) ) ) ) + ( 100 * ( ( ( 1 - w / x ) * ( ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) * ( ( ( 1 - ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * l / ( i ) ) + ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) / ( ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) + ( ( 1 - ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * l / ( i ) ) + ( k / ( i ) ) ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) + ( max( 0 , ( b / ( b + c + d + e ) - f / ( g ) ) - ( ( a / ( b + c + d + e ) - f / ( g ) ) ) ) ) * ( max( y , x / ( n / o ) ) / ( z if smt_on else ( i ) ) / 2 ) / ( ( ( a_a - a_b ) / ( z if smt_on else ( i ) ) / 2 ) + ( ( a_c - a_d ) / ( z if smt_on else ( i ) ) / 2 ) + ( max( y , x / ( n / o ) ) / ( z if smt_on else ( i ) ) / 2 ) ) ) ) + ( 10 * ( r / ( g ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) * ( s / ( b + c + d + e ) ) + ( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - c_c / v ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - c_c / v ) , 0.0001 ) ) ) ) + ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_e / ( b + c + d + e ) ) ) ) * ( ( c_e / ( i ) + ( c_f / ( i ) ) ) + c_i / ( i ) * ( ( c_h + max( c_i - c_e , 0 ) ) / ( i ) * ( c_j - a_i ) / ( i ) ) ) / ( ( c_d / ( i ) ) + ( c_e / ( i ) + ( c_f / ( i ) ) ) + ( c_g / ( z if smt_on else ( i ) ) ) + ( ( ( ( c_h + max( c_i - c_e , 0 ) ) / ( i ) * ( c_j - a_i ) / ( i ) ) * ( i ) + ( c_k + ( d / ( b + c + d + e ) ) * c_l ) ) / ( i ) if ( c_d < ( c_j - a_i ) ) else ( c_k + ( d / ( b + c + d + e ) ) * c_l ) / ( i ) ) ) ) + ( ( ( ( r / ( g ) ) / ( ( max( 0 , ( c_o / ( b + c + d + e ) ) - ( r / ( g ) ) ) ) + ( r / ( g ) ) ) ) * ( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * c_p / ( g ) ) / ( r / ( g ) ) ) ) * ( c_o / ( b + c + d + e ) ) ) ) ) + ( 100 * ( ( c_q + 2 * c_r + c_s ) / ( g ) ) ) + ( 100 * ( ( d / ( b + c + d + e ) ) - ( ( c_q + 2 * c_r + c_s ) / ( g ) ) - ( ( ( ( r / ( g ) ) / ( ( max( 0 , ( c_o / ( b + c + d + e ) ) - ( r / ( g ) ) ) ) + ( r / ( g ) ) ) ) * ( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * c_p / ( g ) ) / ( r / ( g ) ) ) ) * ( c_o / ( b + c + d + e ) ) ) ) ) )", - "BaseFormula": " 100 - ( tma_big_code + tma_instruction_fetch_bw + tma_mispredictions + tma_cache_memory_bandwidth + tma_cache_memory_latency + tma_memory_data_tlbs + tma_memory_synchronization + tma_compute_bound_est + tma_irregular_overhead + tma_branching_overhead + tma_useful_work )", + "Formula": "100 - ( ( 100 * ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( h / ( i ) ) + ( j / ( i ) ) + ( k / ( i ) ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) ) + ( 100 * ( ( b / ( b + c + d + e ) - f / ( g ) ) - ( 1 - ( 10 * ( r / ( g ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) ) * ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) - ( ( 1 - w / x ) * ( ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) * ( ( ( 1 - ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * l / ( i ) ) + ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) / ( ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) + ( ( 1 - ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * l / ( i ) ) + ( k / ( i ) ) ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) + ( max( 0 , ( b / ( b + c + d + e ) - f / ( g ) ) - ( ( a / ( b + c + d + e ) - f / ( g ) ) ) ) ) * ( max( y , x / ( n / o ) ) / ( z if smt_on else ( i ) ) / 2 ) / ( ( ( a_a - a_b ) / ( z if smt_on else ( i ) ) / 2 ) + ( ( a_c - a_d ) / ( z if smt_on else ( i ) ) / 2 ) + ( max( y , x / ( n / o ) ) / ( z if smt_on else ( i ) ) / 2 ) ) ) ) ) - ( 100 * ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( h / ( i ) ) + ( j / ( i ) ) + ( k / ( i ) ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) ) ) + ( 100 * ( 1 - ( 10 * ( r / ( g ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) ) * ( ( s / ( b + c + d + e ) ) + ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) ) ) + ( ( 100 * ( ( ( a_e / ( b + c + d + e ) ) * ( ( ( a_f / ( i ) ) - ( ( a_g - a_f ) / ( i ) ) ) / ( ( max( ( a_h - a_i ) / ( i ) , 0 ) ) + ( ( a_i - a_g ) / ( i ) ) + ( ( a_g - a_f ) / ( i ) ) + ( ( a_g - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) - ( ( a_g - a_f ) / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( min( i , a_k ) ) / ( i ) ) / ( ( ( min( i , a_k ) ) / ( i ) ) + ( ( min( i , a_l ) ) / ( i ) - ( ( min( i , a_k ) ) / ( i ) ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( a_g - a_f ) / ( i ) ) / ( ( max( ( a_h - a_i ) / ( i ) , 0 ) ) + ( ( a_i - a_g ) / ( i ) ) + ( ( a_g - a_f ) / ( i ) ) + ( ( a_g - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) - ( ( a_g - a_f ) / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( min( i , a_k ) ) / ( i ) ) / ( ( ( min( i , a_k ) ) / ( i ) ) + ( ( min( i , a_l ) ) / ( i ) - ( ( min( i , a_k ) ) / ( i ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( ( a_g - a_f ) / ( i ) ) / ( ( max( ( a_h - a_i ) / ( i ) , 0 ) ) + ( ( a_i - a_g ) / ( i ) ) + ( ( a_g - a_f ) / ( i ) ) + ( ( a_g - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) - ( ( a_g - a_f ) / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( a_m + a_n ) / ( i ) ) / ( ( ( ( ( 81 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_r * ( a_s / ( a_s + a_t ) ) ) + ( ( 79 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_u ) ) * ( 1 + ( a_v / a_w ) / 2 ) / ( i ) ) + ( ( ( 79 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_x + a_r * ( 1 - ( a_s / ( a_s + a_t ) ) ) ) * ( 1 + ( a_v / a_w ) / 2 ) / ( i ) ) + ( ( ( 37 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_y * ( 1 + ( a_v / a_w ) / 2 ) ) / ( i ) ) + ( ( a_m + a_n ) / ( i ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( max( ( a_h - a_i ) / ( i ) , 0 ) ) / ( ( max( ( a_h - a_i ) / ( i ) , 0 ) ) + ( ( a_i - a_g ) / ( i ) ) + ( ( a_g - a_f ) / ( i ) ) + ( ( a_g - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) - ( ( a_g - a_f ) / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( a_z / ( i ) ) / ( ( min( ( 7 ) * b_a + b_b , max( b_c - b_d , 0 ) ) / ( i ) ) + ( 13 * b_e / ( i ) ) + ( min( 2 * ( b_f - a_v - a_w ) * dependentloadsweight / 100 , max( b_c - b_d , 0 ) ) / ( i ) ) + ( ( 16 * max( 0 , b_h - b_i ) + ( b_h / b_j ) * ( ( 10 ) * b_k + ( min( i , b_l ) ) ) ) / ( i ) ) + ( ( b_m / b_n ) * b_o / ( i ) ) + ( a_z / ( i ) ) ) ) ) ) ) ) + ( 100 * ( ( ( a_e / ( b + c + d + e ) ) * ( ( ( a_f / ( i ) ) - ( ( a_g - a_f ) / ( i ) ) ) / ( ( max( ( a_h - a_i ) / ( i ) , 0 ) ) + ( ( a_i - a_g ) / ( i ) ) + ( ( a_g - a_f ) / ( i ) ) + ( ( a_g - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) - ( ( a_g - a_f ) / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( min( i , a_l ) ) / ( i ) - ( ( min( i , a_k ) ) / ( i ) ) ) / ( ( ( min( i , a_k ) ) / ( i ) ) + ( ( min( i , a_l ) ) / ( i ) - ( ( min( i , a_k ) ) / ( i ) ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( a_g - a_f ) / ( i ) ) / ( ( max( ( a_h - a_i ) / ( i ) , 0 ) ) + ( ( a_i - a_g ) / ( i ) ) + ( ( a_g - a_f ) / ( i ) ) + ( ( a_g - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) - ( ( a_g - a_f ) / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( min( i , a_l ) ) / ( i ) - ( ( min( i , a_k ) ) / ( i ) ) ) / ( ( ( min( i , a_k ) ) / ( i ) ) + ( ( min( i , a_l ) ) / ( i ) - ( ( min( i , a_k ) ) / ( i ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( ( a_g - a_f ) / ( i ) ) / ( ( max( ( a_h - a_i ) / ( i ) , 0 ) ) + ( ( a_i - a_g ) / ( i ) ) + ( ( a_g - a_f ) / ( i ) ) + ( ( a_g - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) - ( ( a_g - a_f ) / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( ( 37 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_y * ( 1 + ( a_v / a_w ) / 2 ) ) / ( i ) ) / ( ( ( ( ( 81 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_r * ( a_s / ( a_s + a_t ) ) ) + ( ( 79 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_u ) ) * ( 1 + ( a_v / a_w ) / 2 ) / ( i ) ) + ( ( ( 79 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_x + a_r * ( 1 - ( a_s / ( a_s + a_t ) ) ) ) * ( 1 + ( a_v / a_w ) / 2 ) / ( i ) ) + ( ( ( 37 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_y * ( 1 + ( a_v / a_w ) / 2 ) ) / ( i ) ) + ( ( a_m + a_n ) / ( i ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( a_i - a_g ) / ( i ) ) / ( ( max( ( a_h - a_i ) / ( i ) , 0 ) ) + ( ( a_i - a_g ) / ( i ) ) + ( ( a_g - a_f ) / ( i ) ) + ( ( a_g - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) - ( ( a_g - a_f ) / ( i ) ) ) + ( a_j / ( i ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( max( ( a_h - a_i ) / ( i ) , 0 ) ) / ( ( max( ( a_h - a_i ) / ( i ) , 0 ) ) + ( ( a_i - a_g ) / ( i ) ) + ( ( a_g - a_f ) / ( i ) ) + ( ( a_g - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) - ( ( a_g - a_f ) / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( min( 2 * ( b_f - a_v - a_w ) * dependentloadsweight / 100 , max( b_c - b_d , 0 ) ) / ( i ) ) / ( ( min( ( 7 ) * b_a + b_b , max( b_c - b_d , 0 ) ) / ( i ) ) + ( 13 * b_e / ( i ) ) + ( min( 2 * ( b_f - a_v - a_w ) * dependentloadsweight / 100 , max( b_c - b_d , 0 ) ) / ( i ) ) + ( ( 16 * max( 0 , b_h - b_i ) + ( b_h / b_j ) * ( ( 10 ) * b_k + ( min( i , b_l ) ) ) ) / ( i ) ) + ( ( b_m / b_n ) * b_o / ( i ) ) + ( a_z / ( i ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( max( ( a_h - a_i ) / ( i ) , 0 ) ) / ( ( max( ( a_h - a_i ) / ( i ) , 0 ) ) + ( ( a_i - a_g ) / ( i ) ) + ( ( a_g - a_f ) / ( i ) ) + ( ( a_g - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) - ( ( a_g - a_f ) / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( 16 * max( 0 , b_h - b_i ) + ( b_h / b_j ) * ( ( 10 ) * b_k + ( min( i , b_l ) ) ) ) / ( i ) ) / ( ( min( ( 7 ) * b_a + b_b , max( b_c - b_d , 0 ) ) / ( i ) ) + ( 13 * b_e / ( i ) ) + ( min( 2 * ( b_f - a_v - a_w ) * dependentloadsweight / 100 , max( b_c - b_d , 0 ) ) / ( i ) ) + ( ( 16 * max( 0 , b_h - b_i ) + ( b_h / b_j ) * ( ( 10 ) * b_k + ( min( i , b_l ) ) ) ) / ( i ) ) + ( ( b_m / b_n ) * b_o / ( i ) ) + ( a_z / ( i ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( max( ( a_h - a_i ) / ( i ) , 0 ) ) / ( ( max( ( a_h - a_i ) / ( i ) , 0 ) ) + ( ( a_i - a_g ) / ( i ) ) + ( ( a_g - a_f ) / ( i ) ) + ( ( a_g - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) - ( ( a_g - a_f ) / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( b_m / b_n ) * b_o / ( i ) ) / ( ( min( ( 7 ) * b_a + b_b , max( b_c - b_d , 0 ) ) / ( i ) ) + ( 13 * b_e / ( i ) ) + ( min( 2 * ( b_f - a_v - a_w ) * dependentloadsweight / 100 , max( b_c - b_d , 0 ) ) / ( i ) ) + ( ( 16 * max( 0 , b_h - b_i ) + ( b_h / b_j ) * ( ( 10 ) * b_k + ( min( i , b_l ) ) ) ) / ( i ) ) + ( ( b_m / b_n ) * b_o / ( i ) ) + ( a_z / ( i ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( a_j / ( i ) ) / ( ( max( ( a_h - a_i ) / ( i ) , 0 ) ) + ( ( a_i - a_g ) / ( i ) ) + ( ( a_g - a_f ) / ( i ) ) + ( ( a_g - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) - ( ( a_g - a_f ) / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( b_p / ( z if smt_on else ( i ) ) ) / ( ( ( ( b_q * ( 10 ) * ( 1 - ( b_h / b_j ) ) ) + ( 1 - ( b_h / b_j ) ) * ( min( i , b_l ) ) ) / ( i ) ) + ( ( ( 170 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_r + ( 81 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_s ) / ( i ) ) + ( b_p / ( z if smt_on else ( i ) ) ) + ( 9 * b_t / ( i ) ) + ( ( ( 7 ) * b_u + b_v ) / ( z if smt_on else ( i ) ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( a_j / ( i ) ) / ( ( max( ( a_h - a_i ) / ( i ) , 0 ) ) + ( ( a_i - a_g ) / ( i ) ) + ( ( a_g - a_f ) / ( i ) ) + ( ( a_g - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) - ( ( a_g - a_f ) / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( ( b_q * ( 10 ) * ( 1 - ( b_h / b_j ) ) ) + ( 1 - ( b_h / b_j ) ) * ( min( i , b_l ) ) ) / ( i ) ) / ( ( ( ( b_q * ( 10 ) * ( 1 - ( b_h / b_j ) ) ) + ( 1 - ( b_h / b_j ) ) * ( min( i , b_l ) ) ) / ( i ) ) + ( ( ( 170 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_r + ( 81 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_s ) / ( i ) ) + ( b_p / ( z if smt_on else ( i ) ) ) + ( 9 * b_t / ( i ) ) + ( ( ( 7 ) * b_u + b_v ) / ( z if smt_on else ( i ) ) ) ) ) ) ) ) + ( 100 * ( ( a_e / ( b + c + d + e ) ) * ( ( max( ( a_h - a_i ) / ( i ) , 0 ) ) / max( ( a_e / ( b + c + d + e ) ) , ( ( max( ( a_h - a_i ) / ( i ) , 0 ) ) + ( ( a_i - a_g ) / ( i ) ) + ( ( a_g - a_f ) / ( i ) ) + ( ( a_g - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) - ( ( a_g - a_f ) / ( i ) ) ) + ( a_j / ( i ) ) ) ) ) * ( ( min( ( 7 ) * b_a + b_b , max( b_c - b_d , 0 ) ) / ( i ) ) / max( ( max( ( a_h - a_i ) / ( i ) , 0 ) ) , ( ( min( ( 7 ) * b_a + b_b , max( b_c - b_d , 0 ) ) / ( i ) ) + ( 13 * b_e / ( i ) ) + ( min( 2 * ( b_f - a_v - a_w ) * dependentloadsweight / 100 , max( b_c - b_d , 0 ) ) / ( i ) ) + ( ( 16 * max( 0 , b_h - b_i ) + ( b_h / b_j ) * ( ( 10 ) * b_k + ( min( i , b_l ) ) ) ) / ( i ) ) + ( ( b_m / b_n ) * b_o / ( i ) ) + ( a_z / ( i ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( a_j / ( i ) ) / ( ( max( ( a_h - a_i ) / ( i ) , 0 ) ) + ( ( a_i - a_g ) / ( i ) ) + ( ( a_g - a_f ) / ( i ) ) + ( ( a_g - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) - ( ( a_g - a_f ) / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( ( 7 ) * b_u + b_v ) / ( z if smt_on else ( i ) ) ) / ( ( ( ( b_q * ( 10 ) * ( 1 - ( b_h / b_j ) ) ) + ( 1 - ( b_h / b_j ) ) * ( min( i , b_l ) ) ) / ( i ) ) + ( ( ( 170 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_r + ( 81 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_s ) / ( i ) ) + ( b_p / ( z if smt_on else ( i ) ) ) + ( 9 * b_t / ( i ) ) + ( ( ( 7 ) * b_u + b_v ) / ( z if smt_on else ( i ) ) ) ) ) ) ) ) + ( 100 * ( ( a_e / ( b + c + d + e ) ) * ( ( ( ( a_f / ( i ) ) - ( ( a_g - a_f ) / ( i ) ) ) / ( ( max( ( a_h - a_i ) / ( i ) , 0 ) ) + ( ( a_i - a_g ) / ( i ) ) + ( ( a_g - a_f ) / ( i ) ) + ( ( a_g - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) - ( ( a_g - a_f ) / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( min( i , a_l ) ) / ( i ) - ( ( min( i , a_k ) ) / ( i ) ) ) / ( ( ( min( i , a_k ) ) / ( i ) ) + ( ( min( i , a_l ) ) / ( i ) - ( ( min( i , a_k ) ) / ( i ) ) ) ) ) * ( ( ( ( 170 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_w + ( ( 170 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_x ) * ( 1 + ( a_v / a_w ) / 2 ) / ( i ) ) / ( ( ( ( 109 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_y * ( 1 + ( a_v / a_w ) / 2 ) / ( i ) ) + ( ( ( 190 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_z * ( 1 + ( a_v / a_w ) / 2 ) / ( i ) ) + ( ( ( ( 170 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_w + ( ( 170 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_x ) * ( 1 + ( a_v / a_w ) / 2 ) / ( i ) ) ) + ( ( ( a_g - a_f ) / ( i ) ) / ( ( max( ( a_h - a_i ) / ( i ) , 0 ) ) + ( ( a_i - a_g ) / ( i ) ) + ( ( a_g - a_f ) / ( i ) ) + ( ( a_g - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) - ( ( a_g - a_f ) / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( ( ( 81 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_r * ( a_s / ( a_s + a_t ) ) ) + ( ( 79 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_u ) ) * ( 1 + ( a_v / a_w ) / 2 ) / ( i ) ) + ( ( ( 79 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_x + a_r * ( 1 - ( a_s / ( a_s + a_t ) ) ) ) * ( 1 + ( a_v / a_w ) / 2 ) / ( i ) ) ) / ( ( ( ( ( 81 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_r * ( a_s / ( a_s + a_t ) ) ) + ( ( 79 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_u ) ) * ( 1 + ( a_v / a_w ) / 2 ) / ( i ) ) + ( ( ( 79 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_x + a_r * ( 1 - ( a_s / ( a_s + a_t ) ) ) ) * ( 1 + ( a_v / a_w ) / 2 ) / ( i ) ) + ( ( ( 37 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_y * ( 1 + ( a_v / a_w ) / 2 ) ) / ( i ) ) + ( ( a_m + a_n ) / ( i ) ) ) + ( ( a_j / ( i ) ) / ( ( max( ( a_h - a_i ) / ( i ) , 0 ) ) + ( ( a_i - a_g ) / ( i ) ) + ( ( a_g - a_f ) / ( i ) ) + ( ( a_g - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) - ( ( a_g - a_f ) / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( 170 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_r + ( 81 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_s ) / ( i ) ) / ( ( ( ( ( b_q * ( 10 ) * ( 1 - ( b_h / b_j ) ) ) + ( 1 - ( b_h / b_j ) ) * ( min( i , b_l ) ) ) / ( i ) ) + ( ( ( 170 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_r + ( 81 * ( ( ( i ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_s ) / ( i ) ) + ( b_p / ( z if smt_on else ( i ) ) ) + ( 9 * b_t / ( i ) ) + ( ( ( 7 ) * b_u + b_v ) / ( z if smt_on else ( i ) ) ) ) - ( ( ( b_q * ( 10 ) * ( 1 - ( b_h / b_j ) ) ) + ( 1 - ( b_h / b_j ) ) * ( min( i , b_l ) ) ) / ( i ) ) ) ) + ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - c_a / v ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - c_a / v ) , 0.0001 ) ) ) ) ) ) + ( 100 * ( ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_e / ( b + c + d + e ) ) ) ) * ( c_b / ( i ) ) / ( ( c_b / ( i ) ) + ( c_c / ( i ) + ( c_d / ( i ) ) ) + ( c_e / ( z if smt_on else ( i ) ) ) + ( ( ( ( c_f + max( c_g - c_c , 0 ) ) / ( i ) * ( c_h - a_h ) / ( i ) ) * ( i ) + ( c_i + ( d / ( b + c + d + e ) ) * c_j ) ) / ( i ) if ( c_b < ( c_h - a_h ) ) else ( c_i + ( d / ( b + c + d + e ) ) * c_j ) / ( i ) ) ) ) + ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_e / ( b + c + d + e ) ) ) ) * ( c_e / ( z if smt_on else ( i ) ) ) / ( ( c_b / ( i ) ) + ( c_c / ( i ) + ( c_d / ( i ) ) ) + ( c_e / ( z if smt_on else ( i ) ) ) + ( ( ( ( c_f + max( c_g - c_c , 0 ) ) / ( i ) * ( c_h - a_h ) / ( i ) ) * ( i ) + ( c_i + ( d / ( b + c + d + e ) ) * c_j ) ) / ( i ) if ( c_b < ( c_h - a_h ) ) else ( c_i + ( d / ( b + c + d + e ) ) * c_j ) / ( i ) ) ) ) + ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_e / ( b + c + d + e ) ) ) ) * ( ( ( ( ( c_f + max( c_g - c_c , 0 ) ) / ( i ) * ( c_h - a_h ) / ( i ) ) * ( i ) + ( c_i + ( d / ( b + c + d + e ) ) * c_j ) ) / ( i ) if ( c_b < ( c_h - a_h ) ) else ( c_i + ( d / ( b + c + d + e ) ) * c_j ) / ( i ) ) / ( ( c_b / ( i ) ) + ( c_c / ( i ) + ( c_d / ( i ) ) ) + ( c_e / ( z if smt_on else ( i ) ) ) + ( ( ( ( c_f + max( c_g - c_c , 0 ) ) / ( i ) * ( c_h - a_h ) / ( i ) ) * ( i ) + ( c_i + ( d / ( b + c + d + e ) ) * c_j ) ) / ( i ) if ( c_b < ( c_h - a_h ) ) else ( c_i + ( d / ( b + c + d + e ) ) * c_j ) / ( i ) ) ) ) * ( ( c_k / ( i ) ) / ( ( ( c_f + max( c_g - c_c , 0 ) ) / ( i ) * ( c_h - a_h ) / ( i ) ) + ( c_i / ( i ) ) + ( c_l / ( i ) ) + ( c_k / ( i ) ) ) ) ) ) ) + ( 100 * ( ( ( 1 - w / x ) * ( ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) * ( ( ( 1 - ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * l / ( i ) ) + ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) / ( ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) + ( ( 1 - ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * l / ( i ) ) + ( k / ( i ) ) ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) + ( max( 0 , ( b / ( b + c + d + e ) - f / ( g ) ) - ( ( a / ( b + c + d + e ) - f / ( g ) ) ) ) ) * ( max( y , x / ( n / o ) ) / ( z if smt_on else ( i ) ) / 2 ) / ( ( ( a_a - a_b ) / ( z if smt_on else ( i ) ) / 2 ) + ( ( a_c - a_d ) / ( z if smt_on else ( i ) ) / 2 ) + ( max( y , x / ( n / o ) ) / ( z if smt_on else ( i ) ) / 2 ) ) ) ) + ( 10 * ( r / ( g ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) * ( s / ( b + c + d + e ) ) + ( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - c_a / v ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - c_a / v ) , 0.0001 ) ) ) ) + ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_e / ( b + c + d + e ) ) ) ) * ( ( c_c / ( i ) + ( c_d / ( i ) ) ) + c_g / ( i ) * ( ( c_f + max( c_g - c_c , 0 ) ) / ( i ) * ( c_h - a_h ) / ( i ) ) ) / ( ( c_b / ( i ) ) + ( c_c / ( i ) + ( c_d / ( i ) ) ) + ( c_e / ( z if smt_on else ( i ) ) ) + ( ( ( ( c_f + max( c_g - c_c , 0 ) ) / ( i ) * ( c_h - a_h ) / ( i ) ) * ( i ) + ( c_i + ( d / ( b + c + d + e ) ) * c_j ) ) / ( i ) if ( c_b < ( c_h - a_h ) ) else ( c_i + ( d / ( b + c + d + e ) ) * c_j ) / ( i ) ) ) ) + ( ( ( ( r / ( g ) ) / ( ( max( 0 , ( c_m / ( b + c + d + e ) ) - ( r / ( g ) ) ) ) + ( r / ( g ) ) ) ) * ( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * c_n / ( g ) ) / ( r / ( g ) ) ) ) * ( c_m / ( b + c + d + e ) ) ) ) ) + ( 100 * ( ( c_o + 2 * c_p + c_q ) / ( g ) ) ) + ( 100 * ( ( d / ( b + c + d + e ) ) - ( ( c_o + 2 * c_p + c_q ) / ( g ) ) - ( ( ( ( r / ( g ) ) / ( ( max( 0 , ( c_m / ( b + c + d + e ) ) - ( r / ( g ) ) ) ) + ( r / ( g ) ) ) ) * ( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * c_n / ( g ) ) / ( r / ( g ) ) ) ) * ( c_m / ( b + c + d + e ) ) ) ) ) )", + "BaseFormula": " 100 - ( tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottleneck_mispredictions + tma_bottleneck_cache_memory_bandwidth + tma_bottleneck_cache_memory_latency + tma_bottleneck_memory_data_tlbs + tma_bottleneck_memory_synchronization + tma_bottleneck_compute_bound_est + tma_bottleneck_irregular_overhead + tma_bottleneck_branching_overhead + tma_bottleneck_useful_work )", "Category": "TMA", "CountDomain": "Scaled_Slots", "Threshold": { @@ -6193,16 +6153,12 @@ "Alias": "b" }, { - "Name": "OCR.DEMAND_DATA_RD.PMM", + "Name": "MEMORY_ACTIVITY.STALLS_L2_MISS", "Alias": "c" - }, - { - "Name": "OCR.READS_TO_CORE.L3_MISS", - "Alias": "d" } ], "Constants": [], - "Formula": "100 * ( ( a / ( b ) ) - ( ( a / ( b ) ) * c / d ) )", + "Formula": "100 * ( ( a / ( b ) ) - ( ( c - a ) / ( b ) ) )", "BaseFormula": " ( memory_activity.stalls_l3_miss / tma_info_thread_clks ) - tma_hbm_bound", "Category": "TMA", "CountDomain": "Stalls", @@ -10165,11 +10121,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_Core_Bound_Likely" + "Value": "metric_TMA_Info_Botlnk_L0_Core_Bound_Likely" } ], "Formula": "a > 0.5", - "BaseFormula": "metric_TMA_Info_Botlnk_Core_Bound_Likely > 0.5", + "BaseFormula": "metric_TMA_Info_Botlnk_L0_Core_Bound_Likely > 0.5", "ThresholdIssues": "" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -11675,11 +11631,11 @@ }, { "Alias": "b", - "Value": "IPC" + "Value": "metric_TMA_Info_Thread_IPC" } ], "Formula": "a < 0.7 & b / 6 > 0.35", - "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & IPC / 6 > 0.35", + "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & metric_TMA_Info_Thread_IPC / 6 > 0.35", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -12054,11 +12010,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_DSB_Misses" + "Value": "metric_TMA_Info_Botlnk_L2_DSB_Misses" } ], "Formula": "a > 10", - "BaseFormula": "metric_TMA_Info_Botlnk_DSB_Misses > 10", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_DSB_Misses > 10", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -12159,11 +12115,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_DSB_Bandwidth" + "Value": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth" } ], "Formula": "a > 10", - "BaseFormula": "metric_TMA_Info_Botlnk_DSB_Bandwidth > 10", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth > 10", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -12255,11 +12211,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_IC_Misses" + "Value": "metric_TMA_Info_Botlnk_L2_IC_Misses" } ], "Formula": "a > 5", - "BaseFormula": "metric_TMA_Info_Botlnk_IC_Misses > 5", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_IC_Misses > 5", "ThresholdIssues": "$issueFL" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -12544,7 +12500,7 @@ ], "Constants": [], "Formula": "( 100 * ( 1 - ( 10 * ( a / ( b ) ) * ( max( ( c / ( d + e + f + g ) ) * ( 1 - h / ( i - j ) ) , 0.0001 ) ) / ( c / ( d + e + f + g ) ) ) ) * ( ( c / ( d + e + f + g ) ) + ( ( k / ( d + e + f + g ) - l / ( b ) ) ) * ( ( ( c / ( d + e + f + g ) ) / ( max( 1 - ( ( d / ( d + e + f + g ) - l / ( b ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) ) * m / ( n ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) ) ) * ( b ) / ( 6 ) / h / 100", - "BaseFormula": " tma_mispredictions * tma_info_thread_slots / ( 6 ) / br_misp_retired.all_branches / 100", + "BaseFormula": " tma_bottleneck_mispredictions * tma_info_thread_slots / ( 6 ) / br_misp_retired.all_branches / 100", "Category": "TMA", "CountDomain": "Core_Metric", "Threshold": { @@ -13302,11 +13258,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Memory_Page_Walks_Utilization" + "Value": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization" } ], "Formula": "a > 0.5", - "BaseFormula": "metric_TMA_Info_Memory_Page_Walks_Utilization > 0.5", + "BaseFormula": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization > 0.5", "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", @@ -13616,11 +13572,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Memory_Useless_HWPF" + "Value": "metric_TMA_Info_Memory_Prefetches_Useless_HWPF" } ], "Formula": "a > 0.15", - "BaseFormula": "metric_TMA_Info_Memory_Useless_HWPF > 0.15", + "BaseFormula": "metric_TMA_Info_Memory_Prefetches_Useless_HWPF > 0.15", "ThresholdIssues": "" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", diff --git a/TGL/metrics/perf/tigerlake_metrics_perf.json b/TGL/metrics/perf/tigerlake_metrics_perf.json index 6943aef2..a7904c7c 100644 --- a/TGL/metrics/perf/tigerlake_metrics_perf.json +++ b/TGL/metrics/perf/tigerlake_metrics_perf.json @@ -20,7 +20,7 @@ }, { "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the back-end)", - "MetricExpr": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( ( tma_microcode_sequencer / ( tma_few_uops_instructions + tma_microcode_sequencer ) ) * ( tma_assists / tma_microcode_sequencer ) ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) * tma_mispredicts_resteers ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) ) ) - tma_big_code", + "MetricExpr": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( ( tma_microcode_sequencer / ( tma_few_uops_instructions + tma_microcode_sequencer ) ) * ( tma_assists / tma_microcode_sequencer ) ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) * tma_mispredicts_resteers ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) ) ) - tma_bottleneck_big_code", "MetricGroup": "BvFB;Fed;FetchBW;Frontend;TopdownL1;tma_L1_group;Default;Scaled_Slots", "MetricName": "tma_bottleneck_instruction_fetch_bw", "MetricThreshold": "tma_bottleneck_instruction_fetch_bw > 20", @@ -89,7 +89,7 @@ }, { "BriefDescription": "Total pipeline cost of remaining bottlenecks in the back-end", - "MetricExpr": "100 - ( tma_big_code + tma_instruction_fetch_bw + tma_mispredictions + tma_cache_memory_bandwidth + tma_cache_memory_latency + tma_memory_data_tlbs + tma_memory_synchronization + tma_compute_bound_est + tma_irregular_overhead + tma_branching_overhead + tma_useful_work )", + "MetricExpr": "100 - ( tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottleneck_mispredictions + tma_bottleneck_cache_memory_bandwidth + tma_bottleneck_cache_memory_latency + tma_bottleneck_memory_data_tlbs + tma_bottleneck_memory_synchronization + tma_bottleneck_compute_bound_est + tma_bottleneck_irregular_overhead + tma_bottleneck_branching_overhead + tma_bottleneck_useful_work )", "MetricGroup": "BvOB;Cor;Offcore;TopdownL1;tma_L1_group;Default;Scaled_Slots", "MetricName": "tma_bottleneck_other_bottlenecks", "MetricThreshold": "tma_bottleneck_other_bottlenecks > 20", @@ -1039,7 +1039,7 @@ "MetricExpr": "100 * ( 1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1 ) if tma_info_system_smt_2t_utilization > 0.5 else 0", "MetricGroup": "Cor;SMT;Metric", "MetricName": "tma_info_botlnk_l0_core_bound_likely", - "MetricThreshold": "tma_info_botlnk_core_bound_likely > 0.5" + "MetricThreshold": "tma_info_botlnk_l0_core_bound_likely > 0.5" }, { "BriefDescription": "Instructions Per Cycle (per Logical Processor)", @@ -1082,7 +1082,7 @@ }, { "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor", - "MetricExpr": "tma_info_thread_slots / ( TOPDOWN.SLOTS / 2 ) if #SMT_on else 1", + "MetricExpr": "tma_info_thread_slots / ( slots / 2 ) if #SMT_on else 1", "MetricGroup": "SMT;TmaL1;TopdownL1;tma_L1_group;Metric", "MetricName": "tma_info_thread_slots_utilization" }, @@ -1302,7 +1302,7 @@ "MetricExpr": "IDQ.DSB_UOPS / ( UOPS_ISSUED.ANY )", "MetricGroup": "DSB;Fed;FetchBW;Metric;tma_issueFB", "MetricName": "tma_info_frontend_dsb_coverage", - "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & ipc / 5 > 0.35", + "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 5 > 0.35", "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1353,7 +1353,7 @@ "MetricExpr": "100 * ( tma_fetch_latency * tma_dsb_switches / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_mite / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) )", "MetricGroup": "DSBmiss;Fed;Scaled_Slots;tma_issueFB", "MetricName": "tma_info_botlnk_l2_dsb_misses", - "MetricThreshold": "tma_info_botlnk_dsb_misses > 10", + "MetricThreshold": "tma_info_botlnk_l2_dsb_misses > 10", "PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1361,7 +1361,7 @@ "MetricExpr": "100 * ( tma_frontend_bound * ( tma_fetch_bandwidth / ( tma_fetch_latency + tma_fetch_bandwidth ) ) * ( tma_dsb / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) )", "MetricGroup": "DSB;Fed;FetchBW;Scaled_Slots;tma_issueFB", "MetricName": "tma_info_botlnk_l2_dsb_bandwidth", - "MetricThreshold": "tma_info_botlnk_dsb_bandwidth > 10", + "MetricThreshold": "tma_info_botlnk_l2_dsb_bandwidth > 10", "PublicDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp." }, { @@ -1369,7 +1369,7 @@ "MetricExpr": "100 * ( tma_fetch_latency * tma_icache_misses / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) )", "MetricGroup": "Fed;FetchLat;IcMiss;Scaled_Slots;tma_issueFL", "MetricName": "tma_info_botlnk_l2_ic_misses", - "MetricThreshold": "tma_info_botlnk_ic_misses > 5", + "MetricThreshold": "tma_info_botlnk_l2_ic_misses > 5", "PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck." }, { @@ -1409,7 +1409,7 @@ }, { "BriefDescription": "Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricExpr": "tma_mispredictions * tma_info_thread_slots / ( 5 ) / BR_MISP_RETIRED.ALL_BRANCHES / 100", + "MetricExpr": "tma_bottleneck_mispredictions * tma_info_thread_slots / ( 5 ) / BR_MISP_RETIRED.ALL_BRANCHES / 100", "MetricGroup": "Bad;BrMispredicts;Core_Metric;tma_issueBM", "MetricName": "tma_info_bad_spec_branch_misprediction_cost", "PublicDescription": "Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_bottleneck_mispredictions, tma_branch_mispredicts, tma_mispredicts_resteers." @@ -1552,7 +1552,7 @@ "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 2 * tma_info_core_core_clks )", "MetricGroup": "Mem;MemoryTLB;Core_Metric", "MetricName": "tma_info_memory_tlb_page_walks_utilization", - "MetricThreshold": "tma_info_memory_page_walks_utilization > 0.5" + "MetricThreshold": "tma_info_memory_tlb_page_walks_utilization > 0.5" }, { "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", @@ -1601,7 +1601,7 @@ "MetricExpr": "L2_LINES_OUT.USELESS_HWPF / ( L2_LINES_OUT.SILENT + L2_LINES_OUT.NON_SILENT )", "MetricGroup": "Prefetches;Metric", "MetricName": "tma_info_memory_prefetches_useless_hwpf", - "MetricThreshold": "tma_info_memory_useless_hwpf > 0.15" + "MetricThreshold": "tma_info_memory_prefetches_useless_hwpf > 0.15" }, { "BriefDescription": "Average Latency for L2 cache miss demand Loads", diff --git a/TGL/metrics/tigerlake_metrics.json b/TGL/metrics/tigerlake_metrics.json index 7227dca9..6f4974a1 100644 --- a/TGL/metrics/tigerlake_metrics.json +++ b/TGL/metrics/tigerlake_metrics.json @@ -2,7 +2,7 @@ "Header": { "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.", "Info": "Performance Monitoring Metrics for 11th Generation Intel(R) Core(TM) Processor0", - "DatePublished": "11/15/2024", + "DatePublished": "12/02/2024", "Version": "1.0", "Legend": "", "TmaVersion": "5.01", @@ -344,7 +344,7 @@ } ], "Formula": "100 * ( ( a / ( a + b + c + d ) - e / ( f ) ) - ( 1 - ( 10 * ( ( g / h ) * i / ( f ) ) * ( max( ( ( j / ( j + k ) ) * ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) + ( ( 5 ) * l ) / ( f ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * ( 1 - j / ( l - k ) ) , 0.0001 ) ) / ( ( j / ( j + k ) ) * ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) + ( ( 5 ) * l ) / ( f ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) ) ) * ( ( ( 5 ) * m - e ) / ( f ) ) * ( ( j / ( j + k ) ) * n / ( o ) ) / ( ( p / ( o ) ) + ( q / ( o ) ) + ( n / ( o ) + ( 10 ) * r / ( o ) ) + ( ( 3 ) * s / ( o ) ) + ( t / ( o ) ) + ( u / ( o ) ) ) - ( ( ( ( ( g / h ) * i / ( f ) ) / ( ( ( ( ( g / h ) * i / ( f ) ) + ( c / ( a + b + c + d ) ) * ( v - w ) / x ) - ( ( g / h ) * i / ( f ) ) ) + ( ( g / h ) * i / ( f ) ) ) ) * ( ( ( 34 ) * y / ( f ) ) / ( ( g / h ) * i / ( f ) ) ) ) * ( ( ( ( 5 ) * m - e ) / ( f ) ) * ( ( ( 3 ) * s / ( o ) ) + ( n / ( o ) + ( 10 ) * r / ( o ) ) * ( ( ( 1 - ( j / ( j + k ) ) ) * n / ( o ) ) + ( 10 * ( ( g / h ) * i / ( f ) ) * ( max( ( ( j / ( j + k ) ) * ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) + ( ( 5 ) * l ) / ( f ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * ( 1 - j / ( l - k ) ) , 0.0001 ) ) / ( ( j / ( j + k ) ) * ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) + ( ( 5 ) * l ) / ( f ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) ) * ( ( j / ( j + k ) ) * n / ( o ) ) ) / ( ( ( j / ( j + k ) ) * n / ( o ) ) + ( ( 1 - ( j / ( j + k ) ) ) * n / ( o ) ) + ( ( 10 ) * r / ( o ) ) ) ) / ( ( p / ( o ) ) + ( q / ( o ) ) + ( n / ( o ) + ( 10 ) * r / ( o ) ) + ( ( 3 ) * s / ( o ) ) + ( t / ( o ) ) + ( u / ( o ) ) ) + ( max( 0 , ( a / ( a + b + c + d ) - e / ( f ) ) - ( ( ( 5 ) * m - e ) / ( f ) ) ) ) * ( z / ( a_a if smt_on else ( o ) ) / 2 ) / ( ( ( a_b - a_c ) / ( a_a if smt_on else ( o ) ) / 2 ) + ( ( a_d - a_e ) / ( a_a if smt_on else ( o ) ) / 2 ) + ( ( a_f - a_g ) / ( a_a if smt_on else ( o ) ) / 2 ) + ( z / ( a_a if smt_on else ( o ) ) / 2 ) ) ) ) ) - ( 100 * ( ( ( 5 ) * m - e ) / ( f ) ) * ( ( q / ( o ) ) + ( p / ( o ) ) + ( ( 10 ) * r / ( o ) ) ) / ( ( p / ( o ) ) + ( q / ( o ) ) + ( n / ( o ) + ( 10 ) * r / ( o ) ) + ( ( 3 ) * s / ( o ) ) + ( t / ( o ) ) + ( u / ( o ) ) ) )", - "BaseFormula": " 100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( ( tma_microcode_sequencer / ( tma_few_uops_instructions + tma_microcode_sequencer ) ) * ( tma_assists / tma_microcode_sequencer ) ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) * tma_mispredicts_resteers ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) ) ) - tma_big_code", + "BaseFormula": " 100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( ( tma_microcode_sequencer / ( tma_few_uops_instructions + tma_microcode_sequencer ) ) * ( tma_assists / tma_microcode_sequencer ) ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) * tma_mispredicts_resteers ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) ) ) - tma_bottleneck_big_code", "Category": "TMA", "CountDomain": "Scaled_Slots", "Threshold": { @@ -1950,7 +1950,7 @@ } ], "Formula": "100 - ( ( 100 * ( ( ( 5 ) * a - b ) / ( c ) ) * ( ( d / ( e ) ) + ( f / ( e ) ) + ( ( 10 ) * g / ( e ) ) ) / ( ( f / ( e ) ) + ( d / ( e ) ) + ( h / ( e ) + ( 10 ) * g / ( e ) ) + ( ( 3 ) * i / ( e ) ) + ( j / ( e ) ) + ( k / ( e ) ) ) ) + ( 100 * ( ( l / ( l + m + n + o ) - b / ( c ) ) - ( 1 - ( 10 * ( ( p / q ) * r / ( c ) ) * ( max( ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) * ( 1 - s / ( u - t ) ) , 0.0001 ) ) / ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( ( ( 5 ) * a - b ) / ( c ) ) * ( ( s / ( s + t ) ) * h / ( e ) ) / ( ( f / ( e ) ) + ( d / ( e ) ) + ( h / ( e ) + ( 10 ) * g / ( e ) ) + ( ( 3 ) * i / ( e ) ) + ( j / ( e ) ) + ( k / ( e ) ) ) - ( ( ( ( ( p / q ) * r / ( c ) ) / ( ( ( ( ( p / q ) * r / ( c ) ) + ( n / ( l + m + n + o ) ) * ( v - w ) / x ) - ( ( p / q ) * r / ( c ) ) ) + ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( 34 ) * y / ( c ) ) / ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( ( 5 ) * a - b ) / ( c ) ) * ( ( ( 3 ) * i / ( e ) ) + ( h / ( e ) + ( 10 ) * g / ( e ) ) * ( ( ( 1 - ( s / ( s + t ) ) ) * h / ( e ) ) + ( 10 * ( ( p / q ) * r / ( c ) ) * ( max( ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) * ( 1 - s / ( u - t ) ) , 0.0001 ) ) / ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) * ( ( s / ( s + t ) ) * h / ( e ) ) ) / ( ( ( s / ( s + t ) ) * h / ( e ) ) + ( ( 1 - ( s / ( s + t ) ) ) * h / ( e ) ) + ( ( 10 ) * g / ( e ) ) ) ) / ( ( f / ( e ) ) + ( d / ( e ) ) + ( h / ( e ) + ( 10 ) * g / ( e ) ) + ( ( 3 ) * i / ( e ) ) + ( j / ( e ) ) + ( k / ( e ) ) ) + ( max( 0 , ( l / ( l + m + n + o ) - b / ( c ) ) - ( ( ( 5 ) * a - b ) / ( c ) ) ) ) * ( z / ( a_a if smt_on else ( e ) ) / 2 ) / ( ( ( a_b - a_c ) / ( a_a if smt_on else ( e ) ) / 2 ) + ( ( a_d - a_e ) / ( a_a if smt_on else ( e ) ) / 2 ) + ( ( a_f - a_g ) / ( a_a if smt_on else ( e ) ) / 2 ) + ( z / ( a_a if smt_on else ( e ) ) / 2 ) ) ) ) ) - ( 100 * ( ( ( 5 ) * a - b ) / ( c ) ) * ( ( d / ( e ) ) + ( f / ( e ) ) + ( ( 10 ) * g / ( e ) ) ) / ( ( f / ( e ) ) + ( d / ( e ) ) + ( h / ( e ) + ( 10 ) * g / ( e ) ) + ( ( 3 ) * i / ( e ) ) + ( j / ( e ) ) + ( k / ( e ) ) ) ) ) + ( 100 * ( 1 - ( 10 * ( ( p / q ) * r / ( c ) ) * ( max( ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) * ( 1 - s / ( u - t ) ) , 0.0001 ) ) / ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) + ( ( ( 5 ) * a - b ) / ( c ) ) * ( ( s / ( s + t ) ) * h / ( e ) ) / ( ( f / ( e ) ) + ( d / ( e ) ) + ( h / ( e ) + ( 10 ) * g / ( e ) ) + ( ( 3 ) * i / ( e ) ) + ( j / ( e ) ) + ( k / ( e ) ) ) ) ) + ( 100 * ( ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) * ( ( ( min( e , a_t ) ) / ( e ) ) / ( ( ( min( e , a_t ) ) / ( e ) ) + ( ( min( e , a_u ) ) / ( e ) - ( ( min( e , a_t ) ) / ( e ) ) ) ) ) ) + ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( ( a_o - a_m ) / ( e ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) * ( ( a_v / ( e ) ) / ( ( ( ( ( 54 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_z * ( b_a / ( b_a + b_b ) ) ) + ( ( 53 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_c ) ) * ( 1 + ( a_q / a_r ) / 2 ) / ( e ) ) + ( ( ( 53 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_d + a_z * ( 1 - ( b_a / ( b_a + b_b ) ) ) ) * ( 1 + ( a_q / a_r ) / 2 ) / ( e ) ) + ( ( ( 22.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_e * ( 1 + ( a_q / a_r ) / 2 ) ) / ( e ) ) + ( a_v / ( e ) ) ) ) ) + ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) * ( ( b_f / ( e ) ) / ( ( min( ( 7 ) * b_g + b_h , max( b_i - b_j , 0 ) ) / ( e ) ) + ( 13 * b_k / ( e ) ) + ( min( 2 * ( b_l - b_m - b_n ) * dependentloadsweight / 100 , max( b_i - b_j , 0 ) ) / ( e ) ) + ( ( 16 * max( 0 , b_p - b_q ) + ( b_p / b_r ) * ( ( 10 ) * b_s + ( min( e , b_t ) ) ) ) / ( e ) ) + ( ( b_u / ( b_n + b_m ) ) * b_v / ( e ) ) + ( b_w / ( e ) ) + ( b_f / ( e ) ) ) ) ) ) ) + ( 100 * ( ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) * ( ( ( min( e , a_u ) ) / ( e ) - ( ( min( e , a_t ) ) / ( e ) ) ) / ( ( ( min( e , a_t ) ) / ( e ) ) + ( ( min( e , a_u ) ) / ( e ) - ( ( min( e , a_t ) ) / ( e ) ) ) ) ) ) + ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( ( a_o - a_m ) / ( e ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) * ( ( ( ( 22.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_e * ( 1 + ( a_q / a_r ) / 2 ) ) / ( e ) ) / ( ( ( ( ( 54 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_z * ( b_a / ( b_a + b_b ) ) ) + ( ( 53 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_c ) ) * ( 1 + ( a_q / a_r ) / 2 ) / ( e ) ) + ( ( ( 53 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_d + a_z * ( 1 - ( b_a / ( b_a + b_b ) ) ) ) * ( 1 + ( a_q / a_r ) / 2 ) / ( e ) ) + ( ( ( 22.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_e * ( 1 + ( a_q / a_r ) / 2 ) ) / ( e ) ) + ( a_v / ( e ) ) ) ) ) + ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) + ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) * ( ( min( 2 * ( b_l - b_m - b_n ) * dependentloadsweight / 100 , max( b_i - b_j , 0 ) ) / ( e ) ) / ( ( min( ( 7 ) * b_g + b_h , max( b_i - b_j , 0 ) ) / ( e ) ) + ( 13 * b_k / ( e ) ) + ( min( 2 * ( b_l - b_m - b_n ) * dependentloadsweight / 100 , max( b_i - b_j , 0 ) ) / ( e ) ) + ( ( 16 * max( 0 , b_p - b_q ) + ( b_p / b_r ) * ( ( 10 ) * b_s + ( min( e , b_t ) ) ) ) / ( e ) ) + ( ( b_u / ( b_n + b_m ) ) * b_v / ( e ) ) + ( b_w / ( e ) ) + ( b_f / ( e ) ) ) ) ) + ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) * ( ( ( 16 * max( 0 , b_p - b_q ) + ( b_p / b_r ) * ( ( 10 ) * b_s + ( min( e , b_t ) ) ) ) / ( e ) ) / ( ( min( ( 7 ) * b_g + b_h , max( b_i - b_j , 0 ) ) / ( e ) ) + ( 13 * b_k / ( e ) ) + ( min( 2 * ( b_l - b_m - b_n ) * dependentloadsweight / 100 , max( b_i - b_j , 0 ) ) / ( e ) ) + ( ( 16 * max( 0 , b_p - b_q ) + ( b_p / b_r ) * ( ( 10 ) * b_s + ( min( e , b_t ) ) ) ) / ( e ) ) + ( ( b_u / ( b_n + b_m ) ) * b_v / ( e ) ) + ( b_w / ( e ) ) + ( b_f / ( e ) ) ) ) ) + ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) * ( ( ( b_u / ( b_n + b_m ) ) * b_v / ( e ) ) / ( ( min( ( 7 ) * b_g + b_h , max( b_i - b_j , 0 ) ) / ( e ) ) + ( 13 * b_k / ( e ) ) + ( min( 2 * ( b_l - b_m - b_n ) * dependentloadsweight / 100 , max( b_i - b_j , 0 ) ) / ( e ) ) + ( ( 16 * max( 0 , b_p - b_q ) + ( b_p / b_r ) * ( ( 10 ) * b_s + ( min( e , b_t ) ) ) ) / ( e ) ) + ( ( b_u / ( b_n + b_m ) ) * b_v / ( e ) ) + ( b_w / ( e ) ) + ( b_f / ( e ) ) ) ) ) + ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( a_i / ( e ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) * ( ( b_x / ( a_a if smt_on else ( e ) ) ) / ( ( ( ( b_s * ( 10 ) * ( 1 - ( b_p / b_r ) ) ) + ( 1 - ( b_p / b_r ) ) * ( min( e , b_t ) ) ) / ( e ) ) + ( ( 54 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_y / ( e ) ) + ( b_x / ( a_a if smt_on else ( e ) ) ) + ( 9 * b_z / ( e ) ) + ( ( ( 7 ) * c_a + c_b ) / ( a_a if smt_on else ( e ) ) ) ) ) ) + ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( a_i / ( e ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) * ( ( ( ( b_s * ( 10 ) * ( 1 - ( b_p / b_r ) ) ) + ( 1 - ( b_p / b_r ) ) * ( min( e , b_t ) ) ) / ( e ) ) / ( ( ( ( b_s * ( 10 ) * ( 1 - ( b_p / b_r ) ) ) + ( 1 - ( b_p / b_r ) ) * ( min( e , b_t ) ) ) / ( e ) ) + ( ( 54 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_y / ( e ) ) + ( b_x / ( a_a if smt_on else ( e ) ) ) + ( 9 * b_z / ( e ) ) + ( ( ( 7 ) * c_a + c_b ) / ( a_a if smt_on else ( e ) ) ) ) ) ) ) ) + ( 100 * ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) / max( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) , ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) ) * ( ( min( ( 7 ) * b_g + b_h , max( b_i - b_j , 0 ) ) / ( e ) ) / max( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) , ( ( min( ( 7 ) * b_g + b_h , max( b_i - b_j , 0 ) ) / ( e ) ) + ( 13 * b_k / ( e ) ) + ( min( 2 * ( b_l - b_m - b_n ) * dependentloadsweight / 100 , max( b_i - b_j , 0 ) ) / ( e ) ) + ( ( 16 * max( 0 , b_p - b_q ) + ( b_p / b_r ) * ( ( 10 ) * b_s + ( min( e , b_t ) ) ) ) / ( e ) ) + ( ( b_u / ( b_n + b_m ) ) * b_v / ( e ) ) + ( b_w / ( e ) ) + ( b_f / ( e ) ) ) ) ) + ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( a_i / ( e ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) * ( ( ( ( 7 ) * c_a + c_b ) / ( a_a if smt_on else ( e ) ) ) / ( ( ( ( b_s * ( 10 ) * ( 1 - ( b_p / b_r ) ) ) + ( 1 - ( b_p / b_r ) ) * ( min( e , b_t ) ) ) / ( e ) ) + ( ( 54 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_y / ( e ) ) + ( b_x / ( a_a if smt_on else ( e ) ) ) + ( 9 * b_z / ( e ) ) + ( ( ( 7 ) * c_a + c_b ) / ( a_a if smt_on else ( e ) ) ) ) ) ) ) ) + ( 100 * ( ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( ( ( a_o - a_m ) / ( e ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) * ( ( ( ( ( 54 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_z * ( b_a / ( b_a + b_b ) ) ) + ( ( 53 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_c ) ) * ( 1 + ( a_q / a_r ) / 2 ) / ( e ) ) + ( ( ( 53 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_d + a_z * ( 1 - ( b_a / ( b_a + b_b ) ) ) ) * ( 1 + ( a_q / a_r ) / 2 ) / ( e ) ) ) / ( ( ( ( ( 54 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_z * ( b_a / ( b_a + b_b ) ) ) + ( ( 53 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_c ) ) * ( 1 + ( a_q / a_r ) / 2 ) / ( e ) ) + ( ( ( 53 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_d + a_z * ( 1 - ( b_a / ( b_a + b_b ) ) ) ) * ( 1 + ( a_q / a_r ) / 2 ) / ( e ) ) + ( ( ( 22.5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 5 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_e * ( 1 + ( a_q / a_r ) / 2 ) ) / ( e ) ) + ( a_v / ( e ) ) ) + ( ( a_i / ( e ) ) / ( ( max( ( a_h - a_n ) / ( e ) , 0 ) ) + ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) + ( ( a_o - a_m ) / ( e ) ) + ( ( a_m / ( e ) + ( ( a_n - a_o ) / ( e ) ) - ( ( ( a_p * ( 1 + ( a_q / a_r ) ) ) / ( ( a_p * ( 1 + ( a_q / a_r ) ) ) + a_s ) ) * ( ( a_n - a_o ) / ( e ) ) ) ) ) + ( a_i / ( e ) ) ) ) * ( ( 54 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_y / ( e ) ) / ( ( ( ( ( b_s * ( 10 ) * ( 1 - ( b_p / b_r ) ) ) + ( 1 - ( b_p / b_r ) ) * ( min( e , b_t ) ) ) / ( e ) ) + ( ( 54 * ( ( ( e ) / a_w ) * a_x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_y / ( e ) ) + ( b_x / ( a_a if smt_on else ( e ) ) ) + ( 9 * b_z / ( e ) ) + ( ( ( 7 ) * c_a + c_b ) / ( a_a if smt_on else ( e ) ) ) ) - ( ( ( b_s * ( 10 ) * ( 1 - ( b_p / b_r ) ) ) + ( 1 - ( b_p / b_r ) ) * ( min( e , b_t ) ) ) / ( e ) ) ) ) + ( max( 0 , ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( 1 - ( max( ( max( 0 , ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( 1 - c_c / t ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( 1 - c_c / t ) , 0.0001 ) ) ) ) ) ) + ( 100 * ( ( ( max( 0 , ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) - ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) ) ) * ( c_d / ( e ) ) / ( ( c_d / ( e ) ) + ( c_e / ( e ) ) + ( ( ( c_f / ( e ) ) * ( e ) + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) ) / ( e ) if ( c_d < ( a_j - a_h ) ) else ( a_k + ( n / ( l + m + n + o ) ) * a_l ) / ( e ) ) ) ) + ( ( max( 0 , ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) - ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) ) ) * ( ( ( ( c_f / ( e ) ) * ( e ) + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) ) / ( e ) if ( c_d < ( a_j - a_h ) ) else ( a_k + ( n / ( l + m + n + o ) ) * a_l ) / ( e ) ) / ( ( c_d / ( e ) ) + ( c_e / ( e ) ) + ( ( ( c_f / ( e ) ) * ( e ) + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) ) / ( e ) if ( c_d < ( a_j - a_h ) ) else ( a_k + ( n / ( l + m + n + o ) ) * a_l ) / ( e ) ) ) ) * ( ( c_g / ( e ) ) / ( ( c_f / ( e ) ) + ( a_k / ( e ) ) + ( a_l / ( e ) ) + ( c_g / ( e ) ) ) ) ) ) ) + ( 100 * ( ( ( ( ( ( p / q ) * r / ( c ) ) / ( ( ( ( ( p / q ) * r / ( c ) ) + ( n / ( l + m + n + o ) ) * ( v - w ) / x ) - ( ( p / q ) * r / ( c ) ) ) + ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( 34 ) * y / ( c ) ) / ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( ( 5 ) * a - b ) / ( c ) ) * ( ( ( 3 ) * i / ( e ) ) + ( h / ( e ) + ( 10 ) * g / ( e ) ) * ( ( ( 1 - ( s / ( s + t ) ) ) * h / ( e ) ) + ( 10 * ( ( p / q ) * r / ( c ) ) * ( max( ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) * ( 1 - s / ( u - t ) ) , 0.0001 ) ) / ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) * ( ( s / ( s + t ) ) * h / ( e ) ) ) / ( ( ( s / ( s + t ) ) * h / ( e ) ) + ( ( 1 - ( s / ( s + t ) ) ) * h / ( e ) ) + ( ( 10 ) * g / ( e ) ) ) ) / ( ( f / ( e ) ) + ( d / ( e ) ) + ( h / ( e ) + ( 10 ) * g / ( e ) ) + ( ( 3 ) * i / ( e ) ) + ( j / ( e ) ) + ( k / ( e ) ) ) + ( max( 0 , ( l / ( l + m + n + o ) - b / ( c ) ) - ( ( ( 5 ) * a - b ) / ( c ) ) ) ) * ( z / ( a_a if smt_on else ( e ) ) / 2 ) / ( ( ( a_b - a_c ) / ( a_a if smt_on else ( e ) ) / 2 ) + ( ( a_d - a_e ) / ( a_a if smt_on else ( e ) ) / 2 ) + ( ( a_f - a_g ) / ( a_a if smt_on else ( e ) ) / 2 ) + ( z / ( a_a if smt_on else ( e ) ) / 2 ) ) ) ) + ( 10 * ( ( p / q ) * r / ( c ) ) * ( max( ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) * ( 1 - s / ( u - t ) ) , 0.0001 ) ) / ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) * ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) + ( ( max( 0 , ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( max( ( max( 0 , ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( 1 - c_c / t ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( 1 - c_c / t ) , 0.0001 ) ) ) ) + ( ( max( 0 , ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) - ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) ) ) * ( ( c_e / ( e ) ) + ( max( 0 , ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) - ( ( ( a_h + a_i ) / ( a_j + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) + a_i ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) ) ) * c_h / ( e ) * ( c_f / ( e ) ) ) / ( ( c_d / ( e ) ) + ( c_e / ( e ) ) + ( ( ( c_f / ( e ) ) * ( e ) + ( a_k + ( n / ( l + m + n + o ) ) * a_l ) ) / ( e ) if ( c_d < ( a_j - a_h ) ) else ( a_k + ( n / ( l + m + n + o ) ) * a_l ) / ( e ) ) ) ) + ( ( ( ( ( p / q ) * r / ( c ) ) / ( ( ( ( ( p / q ) * r / ( c ) ) + ( n / ( l + m + n + o ) ) * ( v - w ) / x ) - ( ( p / q ) * r / ( c ) ) ) + ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( 34 ) * y / ( c ) ) / ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( p / q ) * r / ( c ) ) + ( n / ( l + m + n + o ) ) * ( v - w ) / x ) ) ) ) + ( 100 * ( ( c_i + 2 * c_j + c_k ) / ( c ) ) ) + ( 100 * ( ( n / ( l + m + n + o ) ) - ( ( c_i + 2 * c_j + c_k ) / ( c ) ) - ( ( ( ( ( p / q ) * r / ( c ) ) / ( ( ( ( ( p / q ) * r / ( c ) ) + ( n / ( l + m + n + o ) ) * ( v - w ) / x ) - ( ( p / q ) * r / ( c ) ) ) + ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( 34 ) * y / ( c ) ) / ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( p / q ) * r / ( c ) ) + ( n / ( l + m + n + o ) ) * ( v - w ) / x ) ) ) ) )", - "BaseFormula": " 100 - ( tma_big_code + tma_instruction_fetch_bw + tma_mispredictions + tma_cache_memory_bandwidth + tma_cache_memory_latency + tma_memory_data_tlbs + tma_memory_synchronization + tma_compute_bound_est + tma_irregular_overhead + tma_branching_overhead + tma_useful_work )", + "BaseFormula": " 100 - ( tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottleneck_mispredictions + tma_bottleneck_cache_memory_bandwidth + tma_bottleneck_cache_memory_latency + tma_bottleneck_memory_data_tlbs + tma_bottleneck_memory_synchronization + tma_bottleneck_compute_bound_est + tma_bottleneck_irregular_overhead + tma_bottleneck_branching_overhead + tma_bottleneck_useful_work )", "Category": "TMA", "CountDomain": "Scaled_Slots", "Threshold": { @@ -8310,11 +8310,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_Core_Bound_Likely" + "Value": "metric_TMA_Info_Botlnk_L0_Core_Bound_Likely" } ], "Formula": "a > 0.5", - "BaseFormula": "metric_TMA_Info_Botlnk_Core_Bound_Likely > 0.5", + "BaseFormula": "metric_TMA_Info_Botlnk_L0_Core_Bound_Likely > 0.5", "ThresholdIssues": "" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -9744,11 +9744,11 @@ }, { "Alias": "b", - "Value": "IPC" + "Value": "metric_TMA_Info_Thread_IPC" } ], "Formula": "a < 0.7 & b / 5 > 0.35", - "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & IPC / 5 > 0.35", + "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & metric_TMA_Info_Thread_IPC / 5 > 0.35", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -10089,11 +10089,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_DSB_Misses" + "Value": "metric_TMA_Info_Botlnk_L2_DSB_Misses" } ], "Formula": "a > 10", - "BaseFormula": "metric_TMA_Info_Botlnk_DSB_Misses > 10", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_DSB_Misses > 10", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -10190,11 +10190,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_DSB_Bandwidth" + "Value": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth" } ], "Formula": "a > 10", - "BaseFormula": "metric_TMA_Info_Botlnk_DSB_Bandwidth > 10", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth > 10", "ThresholdIssues": "$issueFB" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -10262,11 +10262,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Botlnk_IC_Misses" + "Value": "metric_TMA_Info_Botlnk_L2_IC_Misses" } ], "Formula": "a > 5", - "BaseFormula": "metric_TMA_Info_Botlnk_IC_Misses > 5", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_IC_Misses > 5", "ThresholdIssues": "$issueFL" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -10547,7 +10547,7 @@ ], "Constants": [], "Formula": "( 100 * ( 1 - ( 10 * ( ( a / b ) * c / ( d ) ) * ( max( ( ( e / ( e + f ) ) * ( max( 1 - ( ( g / ( g + h + i + j ) - k / ( d ) ) + ( j / ( g + h + i + j ) + ( ( 5 ) * l ) / ( d ) ) + ( i / ( g + h + i + j ) ) ) , 0 ) ) ) * ( 1 - e / ( l - f ) ) , 0.0001 ) ) / ( ( e / ( e + f ) ) * ( max( 1 - ( ( g / ( g + h + i + j ) - k / ( d ) ) + ( j / ( g + h + i + j ) + ( ( 5 ) * l ) / ( d ) ) + ( i / ( g + h + i + j ) ) ) , 0 ) ) ) ) ) * ( ( ( e / ( e + f ) ) * ( max( 1 - ( ( g / ( g + h + i + j ) - k / ( d ) ) + ( j / ( g + h + i + j ) + ( ( 5 ) * l ) / ( d ) ) + ( i / ( g + h + i + j ) ) ) , 0 ) ) ) + ( ( ( 5 ) * m - k ) / ( d ) ) * ( ( e / ( e + f ) ) * n / ( o ) ) / ( ( p / ( o ) ) + ( q / ( o ) ) + ( n / ( o ) + ( 10 ) * r / ( o ) ) + ( ( 3 ) * s / ( o ) ) + ( t / ( o ) ) + ( u / ( o ) ) ) ) ) * ( d ) / ( 5 ) / e / 100", - "BaseFormula": " tma_mispredictions * tma_info_thread_slots / ( 5 ) / br_misp_retired.all_branches / 100", + "BaseFormula": " tma_bottleneck_mispredictions * tma_info_thread_slots / ( 5 ) / br_misp_retired.all_branches / 100", "Category": "TMA", "CountDomain": "Core_Metric", "Threshold": { @@ -11309,11 +11309,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Memory_Page_Walks_Utilization" + "Value": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization" } ], "Formula": "a > 0.5", - "BaseFormula": "metric_TMA_Info_Memory_Page_Walks_Utilization > 0.5", + "BaseFormula": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization > 0.5", "ThresholdIssues": "" }, "ResolutionLevels": "CORE, SOCKET, SYSTEM", @@ -11563,11 +11563,11 @@ "ThresholdMetrics": [ { "Alias": "a", - "Value": "metric_TMA_Info_Memory_Useless_HWPF" + "Value": "metric_TMA_Info_Memory_Prefetches_Useless_HWPF" } ], "Formula": "a > 0.15", - "BaseFormula": "metric_TMA_Info_Memory_Useless_HWPF > 0.15", + "BaseFormula": "metric_TMA_Info_Memory_Prefetches_Useless_HWPF > 0.15", "ThresholdIssues": "" }, "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM",