diff --git a/.github/labeler.yml b/.github/labeler.yml
index b437fdd710..38bc906e51 100644
--- a/.github/labeler.yml
+++ b/.github/labeler.yml
@@ -48,6 +48,13 @@ Alpha:
   - tests/MC/Alpha/**
   - tests/details/alpha.yaml
 
+ARC:
+- arch/ARC/*
+- cstool/cstool_arc.c
+- include/capstone/arc.h
+- suite/MC/ARC/*
+- tests/test_arc.c
+
 BPF:
   - arch/BPF/**
   - cstool/cstool_bpf.c
diff --git a/.github/workflows/auto-sync.yml b/.github/workflows/auto-sync.yml
index a24e58bedb..7dfca69841 100644
--- a/.github/workflows/auto-sync.yml
+++ b/.github/workflows/auto-sync.yml
@@ -55,7 +55,7 @@ jobs:
           cd vendor/llvm_root
           mkdir build
           cd build
-          cmake -G Ninja -DCMAKE_BUILD_TYPE=Debug ../llvm
+          cmake -G Ninja -DCMAKE_BUILD_TYPE=Debug -DLLVM_EXPERIMENTAL_TARGETS_TO_BUILD=ARC ../llvm
           cmake --build . --target llvm-tblgen --config Debug
           cd ../../../
 
@@ -74,6 +74,7 @@ jobs:
         run: |
           ./src/autosync/ASUpdater.py -d -a AArch64 -s IncGen
           ./src/autosync/ASUpdater.py -d -a Alpha -s IncGen
+          ./src/autosync/ASUpdater.py -d -a ARC -s IncGen
           ./src/autosync/ASUpdater.py -d -a ARM -s IncGen
           ./src/autosync/ASUpdater.py -d -a PPC -s IncGen
           ./src/autosync/ASUpdater.py -d -a LoongArch -s IncGen
@@ -93,6 +94,7 @@ jobs:
       - name: CppTranslator - Test translation
         run: |
           ./src/autosync/ASUpdater.py --ci -d -a AArch64 -s Translate
+          ./src/autosync/ASUpdater.py --ci -d -a ARC -s Translate
           ./src/autosync/ASUpdater.py --ci -d -a ARM -s Translate
           ./src/autosync/ASUpdater.py --ci -d -a PPC -s Translate
           ./src/autosync/ASUpdater.py --ci -d -a LoongArch -s Translate
diff --git a/.gitignore b/.gitignore
index 2e28a30614..cad0502e82 100644
--- a/.gitignore
+++ b/.gitignore
@@ -79,6 +79,7 @@ tests/test_riscv
 tests/test_sh
 tests/test_alpha
 tests/test_hppa
+tests/test_arc
 
 # regress binaries
 suite/regress/invalid_read_in_print_operand
diff --git a/BUILDING.md b/BUILDING.md
index a6c51c7cfb..ad411aedea 100644
--- a/BUILDING.md
+++ b/BUILDING.md
@@ -34,6 +34,7 @@ By default all are enabled.
 - `CAPSTONE_ARM_SUPPORT`: Support ARM.
 - `CAPSTONE_AARCH64_SUPPORT`: Support AARCH64.
 - `CAPSTONE_ALPHA_SUPPORT`: Support Alpha.
+- `CAPSTONE_ARC_SUPPORT`: Support ARC.
 - `CAPSTONE_HPPA_SUPPORT`: Support HPPA.
 - `CAPSTONE_LOONGARCH_SUPPORT`: Support LoongArch.
 - `CAPSTONE_M680X_SUPPORT`: Support M680X.
diff --git a/CMakeLists.txt b/CMakeLists.txt
index b4c77a7996..9b4aff7a46 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -99,8 +99,8 @@ if(APPLE AND NOT CAPSTONE_BUILD_MACOS_THIN)
     set(CMAKE_OSX_ARCHITECTURES "x86_64;arm64")
 endif()
 
-set(SUPPORTED_ARCHITECTURES ARM AARCH64 M68K MIPS PPC SPARC SYSTEMZ XCORE X86 TMS320C64X M680X EVM MOS65XX WASM BPF RISCV SH TRICORE ALPHA HPPA LOONGARCH XTENSA)
-set(SUPPORTED_ARCHITECTURE_LABELS ARM AARCH64 M68K MIPS PowerPC Sparc SystemZ XCore x86 TMS320C64x M680x EVM MOS65XX WASM BPF RISCV SH TriCore Alpha HPPA LoongArch Xtensa)
+set(SUPPORTED_ARCHITECTURES ARM AARCH64 M68K MIPS PPC SPARC SYSTEMZ XCORE X86 TMS320C64X M680X EVM MOS65XX WASM BPF RISCV SH TRICORE ALPHA HPPA LOONGARCH XTENSA ARC)
+set(SUPPORTED_ARCHITECTURE_LABELS ARM AARCH64 M68K MIPS PowerPC Sparc SystemZ XCore x86 TMS320C64x M680x EVM MOS65XX WASM BPF RISCV SH TriCore Alpha HPPA LoongArch Xtensa ARC)
 
 # If building for OSX it's best to allow CMake to handle building both architectures
 if(APPLE AND NOT CAPSTONE_BUILD_MACOS_THIN)
@@ -226,6 +226,7 @@ set(HEADERS_COMMON
     include/capstone/hppa.h
     include/capstone/loongarch.h
     include/capstone/xtensa.h
+    include/capstone/arc.h
 )
 
 ## architecture support
@@ -710,6 +711,22 @@ if(CAPSTONE_XTENSA_SUPPORT)
     )
 endif()
 
+if (CAPSTONE_ARC_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_ARC)
+    set(SOURCES_ARC
+            arch/ARC/ARCDisassembler.c
+            arch/ARC/ARCInstPrinter.c
+            arch/ARC/ARCMapping.c
+            arch/ARC/ARCModule.c
+            )
+    set(HEADERS_ARC
+            arch/ARC/ARCInstPrinter.h
+            arch/ARC/ARCMapping.h
+            arch/ARC/ARCModule.h
+            arch/ARC/ARCLinkage.h
+            )
+endif ()
+
 if (CAPSTONE_OSXKERNEL_SUPPORT)
     add_definitions(-DCAPSTONE_HAS_OSXKERNEL)
 endif()
@@ -738,6 +755,7 @@ set(ALL_SOURCES
     ${SOURCES_HPPA}
     ${SOURCES_LOONGARCH}
     ${SOURCES_XTENSA}
+    ${SOURCES_ARC}
 )
 
 set(ALL_HEADERS
@@ -765,6 +783,7 @@ set(ALL_HEADERS
     ${HEADERS_HPPA}
     ${HEADERS_LOONGARCH}
     ${HEADERS_XTENSA}
+    ${HEADERS_ARC}
 )
 
 ## properties
@@ -833,6 +852,7 @@ source_group("Source\\Alpha" FILES ${SOURCES_ALPHA})
 source_group("Source\\HPPA" FILES ${SOURCES_HPPA})
 source_group("Source\\LoongArch" FILES ${SOURCES_LOONGARCH})
 source_group("Source\\Xtensa" FILES ${SOURCES_XTENSA})
+source_group("Source\\ARC" FILES ${SOURCES_ARC})
 
 source_group("Include\\Common" FILES ${HEADERS_COMMON})
 source_group("Include\\Engine" FILES ${HEADERS_ENGINE})
@@ -858,6 +878,7 @@ source_group("Include\\Alpha" FILES ${HEADERS_ALPHA})
 source_group("Include\\HPPA" FILES ${HEADERS_HPPA})
 source_group("Include\\LoongArch" FILES ${HEADERS_LOONGARCH})
 source_group("Include\\Xtensa" FILES ${HEADERS_XTENSA})
+source_group("Include\\ARC" FILES ${HEADERS_ARC})
 
 ## installation
 if(CAPSTONE_INSTALL)
diff --git a/COMPILE_MAKE.TXT b/COMPILE_MAKE.TXT
index ae17cbb551..a27291271d 100644
--- a/COMPILE_MAKE.TXT
+++ b/COMPILE_MAKE.TXT
@@ -94,6 +94,7 @@ Capstone requires no prerequisite packages, so it is easy to compile & install.
 	/usr/include/capstone/arm.h
 	/usr/include/capstone/arm64.h
 	/usr/include/capstone/alpha.h
+	/usr/include/capstone/arc.h
 	/usr/include/capstone/bpf.h
 	/usr/include/capstone/capstone.h
 	/usr/include/capstone/evm.h
diff --git a/CREDITS.TXT b/CREDITS.TXT
index 6f4aff5aff..a7f8c6a4e0 100644
--- a/CREDITS.TXT
+++ b/CREDITS.TXT
@@ -88,6 +88,6 @@ fanfuqiang & citypw & porto703 : RISCV architecture.
 Josh "blacktop" Maine: Arm64 architecture improvements.
 Finn Wilkinson: AArch64 update to Armv9.2-a (SME + SVE2 support)
 Billow & Sidneyp: TriCore architecture.
-Dmitry Sibirtsev: Alpha & HPPA architecture.
+Dmitry Sibirtsev: Alpha, HPPA, ARC architecture.
 Jiajie Chen & Yanglin Xun: LoongArch architecture.
 Billow: Xtensa architecture.
diff --git a/Makefile b/Makefile
index 198bc30316..f11d9d4d15 100644
--- a/Makefile
+++ b/Makefile
@@ -365,11 +365,21 @@ ifneq (,$(findstring xtensa,$(CAPSTONE_ARCHS)))
 	LIBOBJ_XTENSA += $(LIBSRC_XTENSA:%.c=$(OBJDIR)/%.o)
 endif
 
+DEP_ARC =
+DEP_ARC += $(wildcard arch/ARC/ARC*.inc)
+
+LIBOBJ_ARC =
+ifneq (,$(findstring arc,$(CAPSTONE_ARCHS)))
+	CFLAGS += -DCAPSTONE_HAS_ARC
+	LIBSRC_ARC += $(wildcard arch/ARC/ARC*.c)
+	LIBOBJ_ARC += $(LIBSRC_ARC:%.c=$(OBJDIR)/%.o)
+endif
+
 LIBOBJ =
 LIBOBJ += $(OBJDIR)/cs.o $(OBJDIR)/utils.o $(OBJDIR)/SStream.o $(OBJDIR)/MCInstrDesc.o $(OBJDIR)/MCRegisterInfo.o $(OBJDIR)/MCInst.o $(OBJDIR)/MCInstPrinter.o $(OBJDIR)/Mapping.o
 LIBOBJ += $(LIBOBJ_ARM) $(LIBOBJ_AARCH64) $(LIBOBJ_M68K) $(LIBOBJ_MIPS) $(LIBOBJ_PPC) $(LIBOBJ_RISCV) $(LIBOBJ_SPARC) $(LIBOBJ_SYSZ) $(LIBOBJ_SH)
 LIBOBJ += $(LIBOBJ_X86) $(LIBOBJ_XCORE) $(LIBOBJ_TMS320C64X) $(LIBOBJ_M680X) $(LIBOBJ_EVM) $(LIBOBJ_MOS65XX) $(LIBOBJ_WASM) $(LIBOBJ_BPF)
-LIBOBJ += $(LIBOBJ_TRICORE) $(LIBOBJ_ALPHA) $(LIBOBJ_HPPA) $(LIBOBJ_LOONGARCH) $(LIBOBJ_XTENSA)
+LIBOBJ += $(LIBOBJ_TRICORE) $(LIBOBJ_ALPHA) $(LIBOBJ_HPPA) $(LIBOBJ_LOONGARCH) $(LIBOBJ_XTENSA) $(LIBOBJ_ARC)
 
 
 ifeq ($(PKG_EXTRA),)
@@ -503,6 +513,7 @@ $(LIBOBJ_ALPHA): $(DEP_ALPHA)
 $(LIBOBJ_HPPA): $(DEP_HPPA)
 $(LIBOBJ_LOONGARCH): $(DEP_LOONGARCH)
 $(LIBOBJ_XTENSA): $(DEP_XTENSA)
+$(LIBOBJ_ARC): $(DEP_ARC)
 
 ifeq ($(CAPSTONE_STATIC),yes)
 $(ARCHIVE): $(LIBOBJ)
diff --git a/Mapping.c b/Mapping.c
index 5dcb05bb0f..63c85e14b0 100644
--- a/Mapping.c
+++ b/Mapping.c
@@ -354,6 +354,7 @@ DEFINE_get_detail_op(riscv, RISCV);
 DEFINE_get_detail_op(systemz, SystemZ);
 DEFINE_get_detail_op(xtensa, Xtensa);
 DEFINE_get_detail_op(bpf, BPF);
+DEFINE_get_detail_op(arc, ARC);
 
 /// Returns true if for this architecture the
 /// alias operands should be filled.
diff --git a/Mapping.h b/Mapping.h
index 20206b83a2..8eecf4c1f0 100644
--- a/Mapping.h
+++ b/Mapping.h
@@ -146,6 +146,7 @@ DECL_get_detail_op(riscv, RISCV);
 DECL_get_detail_op(systemz, SystemZ);
 DECL_get_detail_op(xtensa, Xtensa);
 DECL_get_detail_op(bpf, BPF);
+DECL_get_detail_op(arc, ARC);
 
 /// Increments the detail->arch.op_count by one.
 #define DEFINE_inc_detail_op_count(arch, ARCH) \
@@ -185,6 +186,8 @@ DEFINE_inc_detail_op_count(xtensa, Xtensa);
 DEFINE_dec_detail_op_count(xtensa, Xtensa);
 DEFINE_inc_detail_op_count(bpf, BPF);
 DEFINE_dec_detail_op_count(bpf, BPF);
+DEFINE_inc_detail_op_count(arc, ARC);
+DEFINE_dec_detail_op_count(arc, ARC);
 
 /// Returns true if a memory operand is currently edited.
 static inline bool doing_mem(const MCInst *MI)
@@ -215,6 +218,7 @@ DEFINE_get_arch_detail(hppa, HPPA);
 DEFINE_get_arch_detail(loongarch, LoongArch);
 DEFINE_get_arch_detail(mips, Mips);
 DEFINE_get_arch_detail(riscv, RISCV);
+DEFINE_get_arch_detail(arc, ARC);
 DEFINE_get_arch_detail(systemz, SystemZ);
 DEFINE_get_arch_detail(xtensa, Xtensa);
 DEFINE_get_arch_detail(bpf, BPF);
@@ -235,6 +239,7 @@ DEFINE_check_safe_inc(RISCV, RISCV);
 DEFINE_check_safe_inc(SystemZ, SYSTEMZ);
 DEFINE_check_safe_inc(Mips, MIPS);
 DEFINE_check_safe_inc(BPF, BPF);
+DEFINE_check_safe_inc(ARC, ARC);
 
 static inline bool detail_is_set(const MCInst *MI)
 {
diff --git a/MathExtras.h b/MathExtras.h
index 847b56602b..803aa57f4a 100644
--- a/MathExtras.h
+++ b/MathExtras.h
@@ -493,4 +493,12 @@ static inline uint32_t get_insn_bit(uint32_t insn, uint8_t bit)
 	return get_insn_field(insn, bit, bit);
 }
 
+/// \brief Create a bitmask with the N right-most bits set to 1, and all other
+/// bits set to 0.  Only unsigned types are allowed.
+static inline uint32_t maskTrailingOnes32(uint32_t N) 
+{
+	const unsigned Bits = CHAR_BIT * sizeof(uint32_t);
+	return N == 0 ? 0 : (((uint32_t) -1) >> (Bits - N));
+}
+
 #endif
diff --git a/README.md b/README.md
index e562938477..41f515f80d 100644
--- a/README.md
+++ b/README.md
@@ -16,7 +16,7 @@ disasm engine for binary analysis and reversing in the security community.
 Created by Nguyen Anh Quynh, then developed and maintained by a small community,
 Capstone offers some unparalleled features:
 
-- Support multiple hardware architectures: ARM, AArch64, Alpha, BPF, Ethereum VM,
+- Support multiple hardware architectures: ARM, AArch64, Alpha, ARC, BPF, Ethereum VM,
   LoongArch, HP PA-RISC (HPPA), M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH,
   Sparc, SystemZ, TMS320C64X, TriCore, Webassembly, XCore and X86 (16, 32, 64), Xtensa.
 
diff --git a/arch/ARC/ARCDisassembler.c b/arch/ARC/ARCDisassembler.c
new file mode 100644
index 0000000000..3655d573dc
--- /dev/null
+++ b/arch/ARC/ARCDisassembler.c
@@ -0,0 +1,473 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Only small edits allowed. */
+/* For multiple similar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+//===- ARCDisassembler.cpp - Disassembler for ARC ---------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// \file
+/// This file is part of the ARC Disassembler.
+///
+//===----------------------------------------------------------------------===//
+
+#ifdef CAPSTONE_HAS_ARC
+
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include <capstone/platform.h>
+
+#include "../../MCInst.h"
+#include "../../SStream.h"
+#include "../../MCDisassembler.h"
+#include "../../MCFixedLenDisassembler.h"
+#include "../../MathExtras.h"
+#include "../../utils.h"
+#define CONCAT(a, b) CONCAT_(a, b)
+#define CONCAT_(a, b) a##_##b
+
+#define DEBUG_TYPE "arc-disassembler"
+
+/// A disassembler class for ARC.
+static DecodeStatus getInstruction(MCInst *Instr, uint64_t *Size, const uint8_t *Bytes,
+			    size_t BytesLen, uint64_t Address,
+			    SStream *CStream);
+
+// end anonymous namespace
+
+static bool readInstruction32(const uint8_t *Bytes, size_t BytesLen,
+			      uint64_t Address, uint64_t *Size, uint32_t *Insn)
+{
+	*Size = 4;
+	// Read 2 16-bit values, but swap hi/lo parts.
+	*Insn = (Bytes[0] << 16) | (Bytes[1] << 24) | (Bytes[2] << 0) |
+	       (Bytes[3] << 8);
+	return true;
+}
+
+static bool readInstruction64(const uint8_t *Bytes, size_t BytesLen,
+			      uint64_t Address, uint64_t *Size, uint64_t *Insn)
+{
+	*Size = 8;
+	*Insn = ((uint64_t)Bytes[0] << 16) | ((uint64_t)Bytes[1] << 24) |
+	       ((uint64_t)Bytes[2] << 0) | ((uint64_t)Bytes[3] << 8) |
+	       ((uint64_t)Bytes[4] << 48) | ((uint64_t)Bytes[5] << 56) |
+	       ((uint64_t)Bytes[6] << 32) | ((uint64_t)Bytes[7] << 40);
+	return true;
+}
+
+static bool readInstruction48(const uint8_t *Bytes, size_t BytesLen,
+			      uint64_t Address, uint64_t *Size, uint64_t *Insn)
+{
+	*Size = 6;
+	*Insn = ((uint64_t)Bytes[0] << 0) | ((uint64_t)Bytes[1] << 8) |
+	       ((uint64_t)Bytes[2] << 32) | ((uint64_t)Bytes[3] << 40) |
+	       ((uint64_t)Bytes[4] << 16) | ((uint64_t)Bytes[5] << 24);
+	return true;
+}
+
+static bool readInstruction16(const uint8_t *Bytes, size_t BytesLen,
+			      uint64_t Address, uint64_t *Size, uint32_t *Insn)
+{
+	*Size = 2;
+	*Insn = (Bytes[0] << 0) | (Bytes[1] << 8);
+	return true;
+}
+
+#define DECLARE_DecodeSignedOperand(B) \
+	static DecodeStatus CONCAT(DecodeSignedOperand, B)( \
+		MCInst * Inst, unsigned InsnS, uint64_t Address, \
+		const void *Decoder);
+DECLARE_DecodeSignedOperand(11);
+DECLARE_DecodeSignedOperand(9);
+DECLARE_DecodeSignedOperand(10);
+DECLARE_DecodeSignedOperand(12);
+
+#define DECLARE_DecodeFromCyclicRange(B) \
+	static DecodeStatus CONCAT(DecodeFromCyclicRange, B)( \
+		MCInst * Inst, unsigned InsnS, uint64_t Address, \
+		const void *Decoder);
+DECLARE_DecodeFromCyclicRange(3);
+
+#define DECLARE_DecodeBranchTargetS(B) \
+	static DecodeStatus CONCAT(DecodeBranchTargetS, \
+				   B)(MCInst * Inst, unsigned InsnS, \
+				      uint64_t Address, const void *Decoder);
+DECLARE_DecodeBranchTargetS(8);
+DECLARE_DecodeBranchTargetS(10);
+DECLARE_DecodeBranchTargetS(7);
+DECLARE_DecodeBranchTargetS(13);
+DECLARE_DecodeBranchTargetS(21);
+DECLARE_DecodeBranchTargetS(25);
+DECLARE_DecodeBranchTargetS(9);
+
+static DecodeStatus DecodeMEMrs9(MCInst *, unsigned, uint64_t,
+				 const void *);
+
+static DecodeStatus DecodeLdLImmInstruction(MCInst *, uint64_t, uint64_t,
+					    const void *);
+
+static DecodeStatus DecodeStLImmInstruction(MCInst *, uint64_t, uint64_t,
+					    const void *);
+
+static DecodeStatus DecodeLdRLImmInstruction(MCInst *, uint64_t, uint64_t,
+					     const void *);
+
+static DecodeStatus DecodeSOPwithRS12(MCInst *, uint64_t, uint64_t,
+				      const void *);
+
+static DecodeStatus DecodeSOPwithRU6(MCInst *, uint64_t, uint64_t,
+				     const void *);
+
+static DecodeStatus DecodeCCRU6Instruction(MCInst *, uint64_t, uint64_t,
+					   const void *);
+
+static DecodeStatus DecodeMoveHRegInstruction(MCInst *Inst, uint64_t, uint64_t,
+					      const void *);
+
+#define GET_REGINFO_ENUM
+#include "ARCGenRegisterInfo.inc"
+
+static const uint16_t GPR32DecoderTable[] = {
+	ARC_R0,	 ARC_R1,    ARC_R2,  ARC_R3,   ARC_R4,	ARC_R5,	 ARC_R6,
+	ARC_R7,	 ARC_R8,    ARC_R9,  ARC_R10,  ARC_R11, ARC_R12, ARC_R13,
+	ARC_R14, ARC_R15,   ARC_R16, ARC_R17,  ARC_R18, ARC_R19, ARC_R20,
+	ARC_R21, ARC_R22,   ARC_R23, ARC_R24,  ARC_R25, ARC_GP,	 ARC_FP,
+	ARC_SP,	 ARC_ILINK, ARC_R30, ARC_BLINK
+};
+
+static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo,
+					     uint64_t Address,
+					     const void *Decoder)
+{
+	if (RegNo >= 32) {
+		;
+		return MCDisassembler_Fail;
+	}
+
+	unsigned Reg = GPR32DecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, (Reg));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeGBR32ShortRegister(MCInst *Inst, unsigned RegNo,
+					     uint64_t Address,
+					     const void *Decoder)
+{
+	// Enumerates registers from ranges [r0-r3],[r12-r15].
+	if (RegNo > 3)
+		RegNo += 8; // 4 for r12, etc...
+
+	return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
+}
+
+#include "ARCGenDisassemblerTables.inc"
+
+static unsigned decodeCField(unsigned Insn)
+{
+	return fieldFromInstruction_4(Insn, 6, 6);
+}
+
+static unsigned decodeBField(unsigned Insn)
+{
+	return (fieldFromInstruction_4(Insn, 12, 3) << 3) |
+	       fieldFromInstruction_4(Insn, 24, 3);
+}
+
+static unsigned decodeAField(unsigned Insn)
+{
+	return fieldFromInstruction_4(Insn, 0, 6);
+}
+
+static DecodeStatus DecodeMEMrs9(MCInst *Inst, unsigned Insn, uint64_t Address,
+				 const void *Decoder)
+{
+	// We have the 9-bit immediate in the low bits, 6-bit register in high bits.
+	unsigned S9 = Insn & 0x1ff;
+	unsigned R = (Insn & (0x7fff & ~0x1ff)) >> 9;
+	if (DecodeGPR32RegisterClass(Inst, R, Address, Decoder) == MCDisassembler_Fail) {
+		return MCDisassembler_Fail;
+	}
+	MCOperand_CreateImm0(Inst, (SignExtend32((S9), 9)));
+	return MCDisassembler_Success;
+}
+
+static void DecodeSymbolicOperandOff(MCInst *Inst, uint64_t Address,
+				     uint64_t Offset, const void *Decoder)
+{
+	uint64_t NextAddress = Address + Offset;
+
+	MCOperand_CreateImm0(Inst, (NextAddress));
+}
+
+#define DEFINE_DecodeBranchTargetS(B) \
+	static DecodeStatus CONCAT(DecodeBranchTargetS, \
+				   B)(MCInst * Inst, unsigned InsnS, \
+				      uint64_t Address, const void *Decoder) \
+	{ \
+		CS_ASSERT(B > 0 && "field is empty"); \
+		DecodeSymbolicOperandOff(Inst, Address, \
+					 SignExtend32((InsnS), B), Decoder); \
+		return MCDisassembler_Success; \
+	}
+DEFINE_DecodeBranchTargetS(8);
+DEFINE_DecodeBranchTargetS(10);
+DEFINE_DecodeBranchTargetS(7);
+DEFINE_DecodeBranchTargetS(13);
+DEFINE_DecodeBranchTargetS(21);
+DEFINE_DecodeBranchTargetS(25);
+DEFINE_DecodeBranchTargetS(9);
+
+#define DEFINE_DecodeSignedOperand(B) \
+	static DecodeStatus CONCAT(DecodeSignedOperand, B)( \
+		MCInst * Inst, unsigned InsnS, uint64_t Address, \
+		const void * Decoder) \
+	{ \
+		CS_ASSERT(B > 0 && "field is empty"); \
+		MCOperand_CreateImm0( \
+			Inst, SignExtend32(maskTrailingOnes32(B) & \
+						    InsnS, B) \
+					    ); \
+		return MCDisassembler_Success; \
+	}
+DEFINE_DecodeSignedOperand(11);
+DEFINE_DecodeSignedOperand(9);
+DEFINE_DecodeSignedOperand(10);
+DEFINE_DecodeSignedOperand(12);
+
+#define DEFINE_DecodeFromCyclicRange(B) \
+	static DecodeStatus CONCAT(DecodeFromCyclicRange, B)( \
+		MCInst * Inst, unsigned InsnS, uint64_t Address, \
+		const void * Decoder) \
+	{ \
+		CS_ASSERT(B > 0 && "field is empty"); \
+		const unsigned max = (1u << B) - 1; \
+		MCOperand_CreateImm0(Inst, (InsnS < max ? (int)(InsnS) : -1)); \
+		return MCDisassembler_Success; \
+	}
+DEFINE_DecodeFromCyclicRange(3);
+
+static DecodeStatus DecodeStLImmInstruction(MCInst *Inst, uint64_t Insn,
+					    uint64_t Address,
+					    const void *Decoder)
+{
+	unsigned SrcC, DstB, LImm;
+	DstB = decodeBField(Insn);
+	if (DstB != 62) {
+		return MCDisassembler_Fail;
+	}
+	SrcC = decodeCField(Insn);
+	if (DecodeGPR32RegisterClass(Inst, SrcC, Address, Decoder) == MCDisassembler_Fail) {
+		return MCDisassembler_Fail;
+	}
+	LImm = (Insn >> 32);
+	MCOperand_CreateImm0(Inst, (LImm));
+	MCOperand_CreateImm0(Inst, (0));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeLdLImmInstruction(MCInst *Inst, uint64_t Insn,
+					    uint64_t Address,
+					    const void *Decoder)
+{
+	unsigned DstA, SrcB, LImm;
+	;
+	SrcB = decodeBField(Insn);
+	if (SrcB != 62) {
+		;
+		return MCDisassembler_Fail;
+	}
+	DstA = decodeAField(Insn);
+	if (DecodeGPR32RegisterClass(Inst, DstA, Address, Decoder) == MCDisassembler_Fail) {
+		return MCDisassembler_Fail;
+	}
+	LImm = (Insn >> 32);
+	MCOperand_CreateImm0(Inst, (LImm));
+	MCOperand_CreateImm0(Inst, (0));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeLdRLImmInstruction(MCInst *Inst, uint64_t Insn,
+					     uint64_t Address,
+					     const void *Decoder)
+{
+	unsigned DstA, SrcB;
+	;
+	DstA = decodeAField(Insn);
+	if (DecodeGPR32RegisterClass(Inst, DstA, Address, Decoder) == MCDisassembler_Fail) {
+		return MCDisassembler_Fail;
+	}
+	SrcB = decodeBField(Insn);
+	if (DecodeGPR32RegisterClass(Inst, SrcB, Address, Decoder) == MCDisassembler_Fail) {
+		return MCDisassembler_Fail;
+	}
+	if (decodeCField(Insn) != 62) {
+		;
+		return MCDisassembler_Fail;
+	}
+	MCOperand_CreateImm0(Inst, ((uint32_t)(Insn >> 32)));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeRegisterOrImm(MCInst *Inst, uint64_t Address, 
+						const void *Decoder, uint64_t RegNum, 
+						uint64_t Value) 
+{
+	if (30 == RegNum) {
+		MCOperand_CreateImm0(Inst, (Value));
+		return MCDisassembler_Success;
+	}
+	return DecodeGPR32RegisterClass(Inst, RegNum, Address, Decoder);
+}
+
+
+static DecodeStatus DecodeMoveHRegInstruction(MCInst *Inst, uint64_t Insn,
+					      uint64_t Address,
+					      const void *Decoder)
+{
+	;
+
+	uint64_t H = fieldFromInstruction_8(Insn, 5, 3) |
+		  (fieldFromInstruction_8(Insn, 0, 2) << 3);
+	uint64_t G = fieldFromInstruction_8(Insn, 8, 3) |
+		  (fieldFromInstruction_8(Insn, 3, 2) << 3);
+
+	if (MCDisassembler_Success != DecodeRegisterOrImm(Inst, Address, 
+									Decoder, G, 0))
+		return MCDisassembler_Fail;
+
+	return DecodeRegisterOrImm(Inst, Address, Decoder, H, Insn >> 16u);
+}
+
+static DecodeStatus DecodeCCRU6Instruction(MCInst *Inst, uint64_t Insn,
+					   uint64_t Address,
+					   const void *Decoder)
+{
+	unsigned DstB;
+	;
+	DstB = decodeBField(Insn);
+	if (DecodeGPR32RegisterClass(Inst, DstB, Address, Decoder) == MCDisassembler_Fail) {
+		return MCDisassembler_Fail;
+	}
+
+	uint64_t U6Field = fieldFromInstruction_8(Insn, 6, 6);
+	MCOperand_CreateImm0(Inst, (U6Field));
+	uint64_t CCField = fieldFromInstruction_8(Insn, 0, 4);
+	MCOperand_CreateImm0(Inst, (CCField));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeSOPwithRU6(MCInst *Inst, uint64_t Insn,
+				     uint64_t Address, const void *Decoder)
+{
+	unsigned DstB = decodeBField(Insn);
+	if (DecodeGPR32RegisterClass(Inst, DstB, Address, Decoder) == MCDisassembler_Fail) {
+		return MCDisassembler_Fail;
+	}
+
+	uint64_t U6 = fieldFromInstruction_8(Insn, 6, 6);
+	MCOperand_CreateImm0(Inst, (U6));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeSOPwithRS12(MCInst *Inst, uint64_t Insn,
+				      uint64_t Address, const void *Decoder)
+{
+	unsigned DstB = decodeBField(Insn);
+	if (DecodeGPR32RegisterClass(Inst, DstB, Address, Decoder) == MCDisassembler_Fail) {
+		return MCDisassembler_Fail;
+	}
+
+	uint64_t Lower = fieldFromInstruction_8(Insn, 6, 6);
+	uint64_t Upper = fieldFromInstruction_8(Insn, 0, 5);
+	uint64_t Sign = fieldFromInstruction_8(Insn, 5, 1) ? -1 : 1;
+	uint64_t Result = Sign * ((Upper << 6) + Lower);
+	MCOperand_CreateImm0(Inst, (Result));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus getInstruction(MCInst *Instr, uint64_t *Size, const uint8_t *Bytes,
+			    size_t BytesLen, uint64_t Address, SStream *cStream)
+{
+	DecodeStatus Result;
+	if (BytesLen < 2) {
+		*Size = 0;
+		return MCDisassembler_Fail;
+	}
+	uint8_t DecodeByte = (Bytes[1] & 0xF7) >> 3;
+	// 0x00 -> 0x07 are 32-bit instructions.
+	// 0x08 -> 0x1F are 16-bit instructions.
+	if (DecodeByte < 0x08) {
+		// 32-bit instruction.
+		if (BytesLen < 4) {
+			// Did we decode garbage?
+			*Size = 0;
+			return MCDisassembler_Fail;
+		}
+		if (BytesLen >= 8) {
+			// Attempt to decode 64-bit instruction.
+			uint64_t Insn64;
+			if (!readInstruction64(Bytes, BytesLen, Address, Size, &Insn64))
+				return MCDisassembler_Fail;
+			Result = decodeInstruction_8(DecoderTable64, Instr,
+						   Insn64, Address, NULL);
+			if (MCDisassembler_Success == Result) {
+				;
+				return Result;
+			};
+		}
+		uint32_t Insn32;
+		if (!readInstruction32(Bytes, BytesLen, Address, Size, &Insn32)) {
+			return MCDisassembler_Fail;
+		}
+		// Calling the auto-generated decoder function.
+		return decodeInstruction_4(DecoderTable32, Instr, Insn32,
+					   Address, NULL);
+	} else {
+		if (BytesLen >= 6) {
+			// Attempt to treat as instr. with limm data.
+			uint64_t Insn48;
+			if (!readInstruction48(Bytes, BytesLen, Address, Size, &Insn48))
+				return MCDisassembler_Fail;
+			Result = decodeInstruction_8(DecoderTable48, Instr,
+						   Insn48, Address, NULL);
+			if (MCDisassembler_Success == Result) {
+				;
+				return Result;
+			};
+		}
+
+		uint32_t Insn16;
+		if (!readInstruction16(Bytes, BytesLen, Address, Size, &Insn16))
+			return MCDisassembler_Fail;
+
+		// Calling the auto-generated decoder function.
+		return decodeInstruction_2(DecoderTable16, Instr, Insn16,
+					   Address, NULL);
+	}
+}
+
+DecodeStatus ARC_LLVM_getInstruction(MCInst *MI, uint64_t *Size,
+					   const uint8_t *Bytes,
+					   size_t BytesLen, uint64_t Address,
+					   SStream *CS)
+{
+	return getInstruction(MI, Size, Bytes, BytesLen, Address, CS);
+}
+
+#endif
\ No newline at end of file
diff --git a/arch/ARC/ARCGenAsmWriter.inc b/arch/ARC/ARCGenAsmWriter.inc
new file mode 100644
index 0000000000..4804bc06da
--- /dev/null
+++ b/arch/ARC/ARCGenAsmWriter.inc
@@ -0,0 +1,1324 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+#include <capstone/platform.h>
+#include "../../cs_priv.h"
+
+/// getMnemonic - This method is automatically generated by tablegen
+/// from the instruction set description.
+static MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) {
+#ifndef CAPSTONE_DIET
+  static const char AsmStrs[] = {
+  /* 0 */ "sub1\t\0"
+  /* 6 */ "sub2\t\0"
+  /* 12 */ "sub3\t\0"
+  /* 18 */ "ldb.ab\t\0"
+  /* 26 */ "stb.ab\t\0"
+  /* 34 */ "ld.ab\t\0"
+  /* 41 */ "ldh.ab\t\0"
+  /* 49 */ "sth.ab\t\0"
+  /* 57 */ "ldb.di.ab\t\0"
+  /* 68 */ "stb.di.ab\t\0"
+  /* 79 */ "ld.di.ab\t\0"
+  /* 89 */ "ldh.di.ab\t\0"
+  /* 100 */ "sth.di.ab\t\0"
+  /* 111 */ "st.di.ab\t\0"
+  /* 121 */ "ldb.x.di.ab\t\0"
+  /* 134 */ "ldh.x.di.ab\t\0"
+  /* 147 */ "st.ab\t\0"
+  /* 154 */ "ldb.x.ab\t\0"
+  /* 164 */ "ldh.x.ab\t\0"
+  /* 174 */ "ldb\t\0"
+  /* 179 */ "stb\t\0"
+  /* 184 */ "rsub\t\0"
+  /* 190 */ "sexb\t\0"
+  /* 196 */ "sbc\t\0"
+  /* 201 */ "adc\t\0"
+  /* 206 */ "add\t\0"
+  /* 211 */ "ld\t\0"
+  /* 215 */ "and\t\0"
+  /* 220 */ "sub_s.ne\t\0"
+  /* 230 */ "mov_s.ne\t\0"
+  /* 240 */ "sub1.f\t\0"
+  /* 248 */ "sub2.f\t\0"
+  /* 256 */ "sub3.f\t\0"
+  /* 264 */ "rsub.f\t\0"
+  /* 272 */ "sexb.f\t\0"
+  /* 280 */ "sbc.f\t\0"
+  /* 287 */ "adc.f\t\0"
+  /* 294 */ "add.f\t\0"
+  /* 301 */ "and.f\t\0"
+  /* 308 */ "normh.f\t\0"
+  /* 317 */ "sexh.f\t\0"
+  /* 325 */ "asl.f\t\0"
+  /* 332 */ "norm.f\t\0"
+  /* 340 */ "mpym.f\t\0"
+  /* 348 */ "min.f\t\0"
+  /* 355 */ "seteq.f\t\0"
+  /* 364 */ "ror.f\t\0"
+  /* 371 */ "xor.f\t\0"
+  /* 378 */ "asr.f\t\0"
+  /* 385 */ "lsr.f\t\0"
+  /* 392 */ "ffs.f\t\0"
+  /* 399 */ "fls.f\t\0"
+  /* 406 */ "mpymu.f\t\0"
+  /* 415 */ "mov.f\t\0"
+  /* 422 */ "max.f\t\0"
+  /* 429 */ "mpy.f\t\0"
+  /* 436 */ "ldh\t\0"
+  /* 441 */ "normh\t\0"
+  /* 448 */ "sth\t\0"
+  /* 453 */ "sexh\t\0"
+  /* 459 */ "ldb.di\t\0"
+  /* 467 */ "stb.di\t\0"
+  /* 475 */ "ld.di\t\0"
+  /* 482 */ "ldh.di\t\0"
+  /* 490 */ "sth.di\t\0"
+  /* 498 */ "st.di\t\0"
+  /* 505 */ "ldb.x.di\t\0"
+  /* 515 */ "ldh.x.di\t\0"
+  /* 525 */ "j\t\0"
+  /* 528 */ "bl\t\0"
+  /* 532 */ "jl\t\0"
+  /* 536 */ "asl\t\0"
+  /* 541 */ "norm\t\0"
+  /* 547 */ "mpym\t\0"
+  /* 553 */ "min\t\0"
+  /* 558 */ "cmp\t\0"
+  /* 563 */ "seteq\t\0"
+  /* 570 */ "lr\t\0"
+  /* 574 */ "ror\t\0"
+  /* 579 */ "xor\t\0"
+  /* 584 */ "asr\t\0"
+  /* 589 */ "lsr\t\0"
+  /* 594 */ "add1_s\t\0"
+  /* 602 */ "add2_s\t\0"
+  /* 610 */ "add3_s\t\0"
+  /* 618 */ "ldb_s\t\0"
+  /* 625 */ "stb_s\t\0"
+  /* 632 */ "extb_s\t\0"
+  /* 640 */ "sub_s\t\0"
+  /* 647 */ "sexb_s\t\0"
+  /* 655 */ "bic_s\t\0"
+  /* 662 */ "add_s\t\0"
+  /* 669 */ "ld_s\t\0"
+  /* 675 */ "and_s\t\0"
+  /* 682 */ "bge_s\t\0"
+  /* 689 */ "ble_s\t\0"
+  /* 696 */ "bne_s\t\0"
+  /* 703 */ "brne_s\t\0"
+  /* 711 */ "leave_s\t\0"
+  /* 720 */ "neg_s\t\0"
+  /* 727 */ "ldh_s\t\0"
+  /* 734 */ "push_s\t\0"
+  /* 742 */ "sth_s\t\0"
+  /* 749 */ "exth_s\t\0"
+  /* 757 */ "sexh_s\t\0"
+  /* 765 */ "ldi_s\t\0"
+  /* 772 */ "ei_s\t\0"
+  /* 778 */ "bhi_s\t\0"
+  /* 785 */ "jli_s\t\0"
+  /* 792 */ "bmsk_s\t\0"
+  /* 800 */ "bl_s\t\0"
+  /* 806 */ "asl_s\t\0"
+  /* 813 */ "blo_s\t\0"
+  /* 820 */ "trap_s\t\0"
+  /* 828 */ "cmp_s\t\0"
+  /* 835 */ "pop_s\t\0"
+  /* 842 */ "beq_s\t\0"
+  /* 849 */ "breq_s\t\0"
+  /* 857 */ "enter_s\t\0"
+  /* 866 */ "bclr_s\t\0"
+  /* 874 */ "xor_s\t\0"
+  /* 881 */ "asr_s\t\0"
+  /* 888 */ "lsr_s\t\0"
+  /* 895 */ "abs_s\t\0"
+  /* 902 */ "bhs_s\t\0"
+  /* 909 */ "bls_s\t\0"
+  /* 916 */ "bset_s\t\0"
+  /* 924 */ "bgt_s\t\0"
+  /* 931 */ "blt_s\t\0"
+  /* 938 */ "not_s\t\0"
+  /* 945 */ "btst_s\t\0"
+  /* 953 */ "mov_s\t\0"
+  /* 960 */ "mpyuw_s\t\0"
+  /* 969 */ "mpyw_s\t\0"
+  /* 977 */ "mpy_s\t\0"
+  /* 984 */ "ld_s.as\t\0"
+  /* 993 */ "ffs\t\0"
+  /* 998 */ "fls\t\0"
+  /* 1003 */ "st\t\0"
+  /* 1007 */ "mpymu\t\0"
+  /* 1014 */ "mov\t\0"
+  /* 1019 */ "ldb.aw\t\0"
+  /* 1027 */ "stb.aw\t\0"
+  /* 1035 */ "ld.aw\t\0"
+  /* 1042 */ "ldh.aw\t\0"
+  /* 1050 */ "sth.aw\t\0"
+  /* 1058 */ "ldb.di.aw\t\0"
+  /* 1069 */ "stb.di.aw\t\0"
+  /* 1080 */ "ld.di.aw\t\0"
+  /* 1090 */ "ldh.di.aw\t\0"
+  /* 1101 */ "sth.di.aw\t\0"
+  /* 1112 */ "st.di.aw\t\0"
+  /* 1122 */ "ldb.x.di.aw\t\0"
+  /* 1135 */ "ldh.x.di.aw\t\0"
+  /* 1148 */ "st.aw\t\0"
+  /* 1155 */ "ldb.x.aw\t\0"
+  /* 1165 */ "ldh.x.aw\t\0"
+  /* 1175 */ "ldb.x\t\0"
+  /* 1182 */ "ldh.x\t\0"
+  /* 1189 */ "ldh_s.x\t\0"
+  /* 1198 */ "max\t\0"
+  /* 1203 */ "mpy\t\0"
+  /* 1208 */ "add_s\t0, \0"
+  /* 1218 */ "mov_s\t0, \0"
+  /* 1228 */ "add_s\t%r0, %gp, \0"
+  /* 1245 */ "ldb_s\t%r0, [%gp, \0"
+  /* 1263 */ "ld_s\t%r0, [%gp, \0"
+  /* 1280 */ "ldh_s\t%r0, [%gp, \0"
+  /* 1298 */ "st_s\t%r0, [%gp, \0"
+  /* 1315 */ "ld_s\t%r1, [%gp, \0"
+  /* 1332 */ "sub_s\t%sp, %sp, \0"
+  /* 1349 */ "add_s\t%sp, %sp, \0"
+  /* 1366 */ "# ADJCALLSTACKDOWN \0"
+  /* 1386 */ "# ADJCALLSTACKUP \0"
+  /* 1404 */ "STB_FAR \0"
+  /* 1413 */ "STH_FAR \0"
+  /* 1422 */ "ST_FAR \0"
+  /* 1430 */ "pldfi \0"
+  /* 1437 */ "error.ffs \0"
+  /* 1448 */ "error.fls \0"
+  /* 1459 */ "sub1.\0"
+  /* 1465 */ "sub2.\0"
+  /* 1471 */ "sub3.\0"
+  /* 1477 */ "# XRay Function Patchable RET.\0"
+  /* 1508 */ "rsub.\0"
+  /* 1514 */ "sbc.\0"
+  /* 1519 */ "adc.\0"
+  /* 1524 */ "add.\0"
+  /* 1529 */ "and.\0"
+  /* 1534 */ "# XRay Typed Event Log.\0"
+  /* 1558 */ "# XRay Custom Event Log.\0"
+  /* 1583 */ "asl.\0"
+  /* 1588 */ "mpym.\0"
+  /* 1594 */ "min.\0"
+  /* 1599 */ "seteq.\0"
+  /* 1606 */ "# XRay Function Enter.\0"
+  /* 1629 */ "ror.\0"
+  /* 1634 */ "xor.\0"
+  /* 1639 */ "asr.\0"
+  /* 1644 */ "lsr.\0"
+  /* 1649 */ "# XRay Tail Call Exit.\0"
+  /* 1672 */ "# XRay Function Exit.\0"
+  /* 1694 */ "mpymu.\0"
+  /* 1701 */ "mov.\0"
+  /* 1706 */ "max.\0"
+  /* 1711 */ "mpy.\0"
+  /* 1716 */ "LIFETIME_END\0"
+  /* 1729 */ "PSEUDO_PROBE\0"
+  /* 1742 */ "BUNDLE\0"
+  /* 1749 */ "DBG_VALUE\0"
+  /* 1759 */ "DBG_INSTR_REF\0"
+  /* 1773 */ "DBG_PHI\0"
+  /* 1781 */ "DBG_LABEL\0"
+  /* 1791 */ "LIFETIME_START\0"
+  /* 1806 */ "DBG_VALUE_LIST\0"
+  /* 1821 */ "j_s.d\t[\0"
+  /* 1829 */ "jl_s.d\t[\0"
+  /* 1838 */ "j\t[\0"
+  /* 1842 */ "jl\t[\0"
+  /* 1847 */ "j_s\t[\0"
+  /* 1853 */ "jl_s\t[\0"
+  /* 1860 */ "j_s.d\t[%blink]\0"
+  /* 1875 */ "jne_s\t[%blink]\0"
+  /* 1890 */ "j_s\t[%blink]\0"
+  /* 1903 */ "jeq_s\t[%blink]\0"
+  /* 1918 */ "b\0"
+  /* 1920 */ "push_s\t%blink\0"
+  /* 1934 */ "pop_s\t%blink\0"
+  /* 1947 */ "# FEntry call\0"
+  /* 1961 */ "pbr\0"
+  /* 1965 */ "swi_s\0"
+  /* 1971 */ "brk_s\0"
+  /* 1977 */ "unimp_s\0"
+  /* 1985 */ "nop_s\0"
+};
+#endif // CAPSTONE_DIET
+
+  static const uint32_t OpInfo0[] = {
+    0U,	// PHI
+    0U,	// INLINEASM
+    0U,	// INLINEASM_BR
+    0U,	// CFI_INSTRUCTION
+    0U,	// EH_LABEL
+    0U,	// GC_LABEL
+    0U,	// ANNOTATION_LABEL
+    0U,	// KILL
+    0U,	// EXTRACT_SUBREG
+    0U,	// INSERT_SUBREG
+    0U,	// IMPLICIT_DEF
+    0U,	// SUBREG_TO_REG
+    0U,	// COPY_TO_REGCLASS
+    1750U,	// DBG_VALUE
+    1807U,	// DBG_VALUE_LIST
+    1760U,	// DBG_INSTR_REF
+    1774U,	// DBG_PHI
+    1782U,	// DBG_LABEL
+    0U,	// REG_SEQUENCE
+    0U,	// COPY
+    1743U,	// BUNDLE
+    1792U,	// LIFETIME_START
+    1717U,	// LIFETIME_END
+    1730U,	// PSEUDO_PROBE
+    0U,	// ARITH_FENCE
+    0U,	// STACKMAP
+    1948U,	// FENTRY_CALL
+    0U,	// PATCHPOINT
+    0U,	// LOAD_STACK_GUARD
+    0U,	// PREALLOCATED_SETUP
+    0U,	// PREALLOCATED_ARG
+    0U,	// STATEPOINT
+    0U,	// LOCAL_ESCAPE
+    0U,	// FAULTING_OP
+    0U,	// PATCHABLE_OP
+    1607U,	// PATCHABLE_FUNCTION_ENTER
+    1478U,	// PATCHABLE_RET
+    1673U,	// PATCHABLE_FUNCTION_EXIT
+    1650U,	// PATCHABLE_TAIL_CALL
+    1559U,	// PATCHABLE_EVENT_CALL
+    1535U,	// PATCHABLE_TYPED_EVENT_CALL
+    0U,	// ICALL_BRANCH_FUNNEL
+    0U,	// MEMBARRIER
+    0U,	// JUMP_TABLE_DEBUG_INFO
+    0U,	// G_ASSERT_SEXT
+    0U,	// G_ASSERT_ZEXT
+    0U,	// G_ASSERT_ALIGN
+    0U,	// G_ADD
+    0U,	// G_SUB
+    0U,	// G_MUL
+    0U,	// G_SDIV
+    0U,	// G_UDIV
+    0U,	// G_SREM
+    0U,	// G_UREM
+    0U,	// G_SDIVREM
+    0U,	// G_UDIVREM
+    0U,	// G_AND
+    0U,	// G_OR
+    0U,	// G_XOR
+    0U,	// G_IMPLICIT_DEF
+    0U,	// G_PHI
+    0U,	// G_FRAME_INDEX
+    0U,	// G_GLOBAL_VALUE
+    0U,	// G_CONSTANT_POOL
+    0U,	// G_EXTRACT
+    0U,	// G_UNMERGE_VALUES
+    0U,	// G_INSERT
+    0U,	// G_MERGE_VALUES
+    0U,	// G_BUILD_VECTOR
+    0U,	// G_BUILD_VECTOR_TRUNC
+    0U,	// G_CONCAT_VECTORS
+    0U,	// G_PTRTOINT
+    0U,	// G_INTTOPTR
+    0U,	// G_BITCAST
+    0U,	// G_FREEZE
+    0U,	// G_CONSTANT_FOLD_BARRIER
+    0U,	// G_INTRINSIC_FPTRUNC_ROUND
+    0U,	// G_INTRINSIC_TRUNC
+    0U,	// G_INTRINSIC_ROUND
+    0U,	// G_INTRINSIC_LRINT
+    0U,	// G_INTRINSIC_ROUNDEVEN
+    0U,	// G_READCYCLECOUNTER
+    0U,	// G_LOAD
+    0U,	// G_SEXTLOAD
+    0U,	// G_ZEXTLOAD
+    0U,	// G_INDEXED_LOAD
+    0U,	// G_INDEXED_SEXTLOAD
+    0U,	// G_INDEXED_ZEXTLOAD
+    0U,	// G_STORE
+    0U,	// G_INDEXED_STORE
+    0U,	// G_ATOMIC_CMPXCHG_WITH_SUCCESS
+    0U,	// G_ATOMIC_CMPXCHG
+    0U,	// G_ATOMICRMW_XCHG
+    0U,	// G_ATOMICRMW_ADD
+    0U,	// G_ATOMICRMW_SUB
+    0U,	// G_ATOMICRMW_AND
+    0U,	// G_ATOMICRMW_NAND
+    0U,	// G_ATOMICRMW_OR
+    0U,	// G_ATOMICRMW_XOR
+    0U,	// G_ATOMICRMW_MAX
+    0U,	// G_ATOMICRMW_MIN
+    0U,	// G_ATOMICRMW_UMAX
+    0U,	// G_ATOMICRMW_UMIN
+    0U,	// G_ATOMICRMW_FADD
+    0U,	// G_ATOMICRMW_FSUB
+    0U,	// G_ATOMICRMW_FMAX
+    0U,	// G_ATOMICRMW_FMIN
+    0U,	// G_ATOMICRMW_UINC_WRAP
+    0U,	// G_ATOMICRMW_UDEC_WRAP
+    0U,	// G_FENCE
+    0U,	// G_PREFETCH
+    0U,	// G_BRCOND
+    0U,	// G_BRINDIRECT
+    0U,	// G_INVOKE_REGION_START
+    0U,	// G_INTRINSIC
+    0U,	// G_INTRINSIC_W_SIDE_EFFECTS
+    0U,	// G_INTRINSIC_CONVERGENT
+    0U,	// G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
+    0U,	// G_ANYEXT
+    0U,	// G_TRUNC
+    0U,	// G_CONSTANT
+    0U,	// G_FCONSTANT
+    0U,	// G_VASTART
+    0U,	// G_VAARG
+    0U,	// G_SEXT
+    0U,	// G_SEXT_INREG
+    0U,	// G_ZEXT
+    0U,	// G_SHL
+    0U,	// G_LSHR
+    0U,	// G_ASHR
+    0U,	// G_FSHL
+    0U,	// G_FSHR
+    0U,	// G_ROTR
+    0U,	// G_ROTL
+    0U,	// G_ICMP
+    0U,	// G_FCMP
+    0U,	// G_SELECT
+    0U,	// G_UADDO
+    0U,	// G_UADDE
+    0U,	// G_USUBO
+    0U,	// G_USUBE
+    0U,	// G_SADDO
+    0U,	// G_SADDE
+    0U,	// G_SSUBO
+    0U,	// G_SSUBE
+    0U,	// G_UMULO
+    0U,	// G_SMULO
+    0U,	// G_UMULH
+    0U,	// G_SMULH
+    0U,	// G_UADDSAT
+    0U,	// G_SADDSAT
+    0U,	// G_USUBSAT
+    0U,	// G_SSUBSAT
+    0U,	// G_USHLSAT
+    0U,	// G_SSHLSAT
+    0U,	// G_SMULFIX
+    0U,	// G_UMULFIX
+    0U,	// G_SMULFIXSAT
+    0U,	// G_UMULFIXSAT
+    0U,	// G_SDIVFIX
+    0U,	// G_UDIVFIX
+    0U,	// G_SDIVFIXSAT
+    0U,	// G_UDIVFIXSAT
+    0U,	// G_FADD
+    0U,	// G_FSUB
+    0U,	// G_FMUL
+    0U,	// G_FMA
+    0U,	// G_FMAD
+    0U,	// G_FDIV
+    0U,	// G_FREM
+    0U,	// G_FPOW
+    0U,	// G_FPOWI
+    0U,	// G_FEXP
+    0U,	// G_FEXP2
+    0U,	// G_FEXP10
+    0U,	// G_FLOG
+    0U,	// G_FLOG2
+    0U,	// G_FLOG10
+    0U,	// G_FLDEXP
+    0U,	// G_FFREXP
+    0U,	// G_FNEG
+    0U,	// G_FPEXT
+    0U,	// G_FPTRUNC
+    0U,	// G_FPTOSI
+    0U,	// G_FPTOUI
+    0U,	// G_SITOFP
+    0U,	// G_UITOFP
+    0U,	// G_FABS
+    0U,	// G_FCOPYSIGN
+    0U,	// G_IS_FPCLASS
+    0U,	// G_FCANONICALIZE
+    0U,	// G_FMINNUM
+    0U,	// G_FMAXNUM
+    0U,	// G_FMINNUM_IEEE
+    0U,	// G_FMAXNUM_IEEE
+    0U,	// G_FMINIMUM
+    0U,	// G_FMAXIMUM
+    0U,	// G_GET_FPENV
+    0U,	// G_SET_FPENV
+    0U,	// G_RESET_FPENV
+    0U,	// G_GET_FPMODE
+    0U,	// G_SET_FPMODE
+    0U,	// G_RESET_FPMODE
+    0U,	// G_PTR_ADD
+    0U,	// G_PTRMASK
+    0U,	// G_SMIN
+    0U,	// G_SMAX
+    0U,	// G_UMIN
+    0U,	// G_UMAX
+    0U,	// G_ABS
+    0U,	// G_LROUND
+    0U,	// G_LLROUND
+    0U,	// G_BR
+    0U,	// G_BRJT
+    0U,	// G_INSERT_VECTOR_ELT
+    0U,	// G_EXTRACT_VECTOR_ELT
+    0U,	// G_SHUFFLE_VECTOR
+    0U,	// G_CTTZ
+    0U,	// G_CTTZ_ZERO_UNDEF
+    0U,	// G_CTLZ
+    0U,	// G_CTLZ_ZERO_UNDEF
+    0U,	// G_CTPOP
+    0U,	// G_BSWAP
+    0U,	// G_BITREVERSE
+    0U,	// G_FCEIL
+    0U,	// G_FCOS
+    0U,	// G_FSIN
+    0U,	// G_FSQRT
+    0U,	// G_FFLOOR
+    0U,	// G_FRINT
+    0U,	// G_FNEARBYINT
+    0U,	// G_ADDRSPACE_CAST
+    0U,	// G_BLOCK_ADDR
+    0U,	// G_JUMP_TABLE
+    0U,	// G_DYN_STACKALLOC
+    0U,	// G_STACKSAVE
+    0U,	// G_STACKRESTORE
+    0U,	// G_STRICT_FADD
+    0U,	// G_STRICT_FSUB
+    0U,	// G_STRICT_FMUL
+    0U,	// G_STRICT_FDIV
+    0U,	// G_STRICT_FREM
+    0U,	// G_STRICT_FMA
+    0U,	// G_STRICT_FSQRT
+    0U,	// G_STRICT_FLDEXP
+    0U,	// G_READ_REGISTER
+    0U,	// G_WRITE_REGISTER
+    0U,	// G_MEMCPY
+    0U,	// G_MEMCPY_INLINE
+    0U,	// G_MEMMOVE
+    0U,	// G_MEMSET
+    0U,	// G_BZERO
+    0U,	// G_VECREDUCE_SEQ_FADD
+    0U,	// G_VECREDUCE_SEQ_FMUL
+    0U,	// G_VECREDUCE_FADD
+    0U,	// G_VECREDUCE_FMUL
+    0U,	// G_VECREDUCE_FMAX
+    0U,	// G_VECREDUCE_FMIN
+    0U,	// G_VECREDUCE_FMAXIMUM
+    0U,	// G_VECREDUCE_FMINIMUM
+    0U,	// G_VECREDUCE_ADD
+    0U,	// G_VECREDUCE_MUL
+    0U,	// G_VECREDUCE_AND
+    0U,	// G_VECREDUCE_OR
+    0U,	// G_VECREDUCE_XOR
+    0U,	// G_VECREDUCE_SMAX
+    0U,	// G_VECREDUCE_SMIN
+    0U,	// G_VECREDUCE_UMAX
+    0U,	// G_VECREDUCE_UMIN
+    0U,	// G_SBFX
+    0U,	// G_UBFX
+    3415U,	// ADJCALLSTACKDOWN
+    36203U,	// ADJCALLSTACKUP
+    6058U,	// BRcc_rr_p
+    6058U,	// BRcc_ru6_p
+    3497U,	// CTLZ
+    3486U,	// CTTZ
+    3479U,	// GETFI
+    527741U,	// STB_FAR
+    527750U,	// STH_FAR
+    527759U,	// ST_FAR
+    1121776U,	// ADC_cc_f_rru6
+    1154544U,	// ADC_cc_rru6
+    4196640U,	// ADC_f_rrlimm
+    4196640U,	// ADC_f_rrr
+    4196640U,	// ADC_f_rrs12
+    4196640U,	// ADC_f_rru6
+    4196554U,	// ADC_rrlimm
+    4196554U,	// ADC_rrr
+    4196554U,	// ADC_rrs12
+    4196554U,	// ADC_rru6
+    1582265U,	// ADD_S_limms3
+    22547095U,	// ADD_S_rlimm
+    22547095U,	// ADD_S_rr
+    4197015U,	// ADD_S_rrr
+    4197015U,	// ADD_S_rru6
+    22547095U,	// ADD_S_rs3
+    4197015U,	// ADD_S_ru3
+    22547095U,	// ADD_S_u7
+    1121781U,	// ADD_cc_f_rru6
+    1154549U,	// ADD_cc_rru6
+    4196647U,	// ADD_f_rrlimm
+    4196647U,	// ADD_f_rrr
+    4196647U,	// ADD_f_rrs12
+    4196647U,	// ADD_f_rru6
+    4196559U,	// ADD_rrlimm
+    4196559U,	// ADD_rrr
+    4196559U,	// ADD_rrs12
+    4196559U,	// ADD_rru6
+    1121786U,	// AND_cc_f_rru6
+    1154554U,	// AND_cc_rru6
+    4196654U,	// AND_f_rrlimm
+    4196654U,	// AND_f_rrr
+    4196654U,	// AND_f_rrs12
+    4196654U,	// AND_f_rru6
+    4196568U,	// AND_rrlimm
+    4196568U,	// AND_rrr
+    4196568U,	// AND_rrs12
+    4196568U,	// AND_rru6
+    4197159U,	// ASL_S_ru3
+    22547239U,	// ASL_S_ru5
+    1121840U,	// ASL_cc_f_rru6
+    1154608U,	// ASL_cc_rru6
+    4196678U,	// ASL_f_rrlimm
+    4196678U,	// ASL_f_rrr
+    4196678U,	// ASL_f_rrs12
+    4196678U,	// ASL_f_rru6
+    4196889U,	// ASL_rrlimm
+    4196889U,	// ASL_rrr
+    4196889U,	// ASL_rrs12
+    4196889U,	// ASL_rru6
+    4197234U,	// ASR_S_ru3
+    22547314U,	// ASR_S_ru5
+    1121896U,	// ASR_cc_f_rru6
+    1154664U,	// ASR_cc_rru6
+    4196731U,	// ASR_f_rrlimm
+    4196731U,	// ASR_f_rrr
+    4196731U,	// ASR_f_rrs12
+    4196731U,	// ASR_f_rru6
+    4196937U,	// ASR_rrlimm
+    4196937U,	// ASR_rrr
+    4196937U,	// ASR_rrs12
+    4196937U,	// ASR_rru6
+    22547299U,	// BCLR_S_ru5
+    11083U,	// BEQ_S
+    10923U,	// BGE_S
+    11165U,	// BGT_S
+    11019U,	// BHI_S
+    11143U,	// BHS_S
+    10769U,	// BL
+    10930U,	// BLE_S
+    11054U,	// BLO_S
+    11150U,	// BLS_S
+    11172U,	// BLT_S
+    11041U,	// BL_S
+    22547225U,	// BMSK_S_ru5
+    10937U,	// BNE_S
+    10264U,	// BR
+    133970U,	// BREQ_S
+    133824U,	// BRNE_S
+    14251U,	// BRcc_rr
+    14251U,	// BRcc_ru6
+    22547349U,	// BSET_S_ru5
+    2994U,	// BTST_S_ru5
+    10861U,	// B_S
+    16255U,	// Bcc
+    1581885U,	// CMP_S_limms3
+    2877U,	// CMP_S_rlimm
+    2877U,	// CMP_S_rr
+    2877U,	// CMP_S_rs3
+    2877U,	// CMP_S_u7
+    2607U,	// CMP_rlimm
+    2607U,	// CMP_rr
+    2607U,	// CMP_ru6
+    71469726U,	// COMPACT_LD_S
+    3002U,	// COMPACT_MOV_S_hreg
+    3002U,	// COMPACT_MOV_S_limm
+    35589U,	// EI_S
+    35674U,	// ENTER_S
+    2441U,	// FFS_f_rr
+    3042U,	// FFS_rr
+    2448U,	// FLS_f_rr
+    3047U,	// FLS_rr
+    2944U,	// GEN_ABS_S
+    22547027U,	// GEN_ADD1_S
+    22547035U,	// GEN_ADD2_S
+    22547043U,	// GEN_ADD3_S
+    22547108U,	// GEN_AND_S
+    2855U,	// GEN_AS1L_S
+    2930U,	// GEN_AS1R_S
+    22547239U,	// GEN_ASL_S
+    22547314U,	// GEN_ASR_S
+    22547088U,	// GEN_BIC_S
+    1972U,	// GEN_BRK_S
+    2681U,	// GEN_EXTB_S
+    2798U,	// GEN_EXTH_S
+    1904U,	// GEN_JEQ_S
+    200510U,	// GEN_JL_S
+    200486U,	// GEN_JL_S_D
+    1876U,	// GEN_JNE_S
+    200504U,	// GEN_J_S
+    200478U,	// GEN_J_S_D
+    1861U,	// GEN_J_S_D_BLINK
+    2937U,	// GEN_LS1R_S
+    22547321U,	// GEN_LSR_S
+    22547393U,	// GEN_MPYUW_S
+    22547402U,	// GEN_MPYW_S
+    22547410U,	// GEN_MPY_S
+    2769U,	// GEN_NEG_S
+    1986U,	// GEN_NOP_S
+    2987U,	// GEN_NOT_S
+    22547308U,	// GEN_OR_S
+    2696U,	// GEN_SEXB_S
+    2806U,	// GEN_SEXH_S
+    22547073U,	// GEN_SUB_S
+    39323869U,	// GEN_SUB_S_NE
+    1966U,	// GEN_SWI_S
+    35637U,	// GEN_TRAP_S
+    2995U,	// GEN_TST_S
+    1978U,	// GEN_UNIMP_S
+    22547307U,	// GEN_XOR_S
+    36045U,	// GP_ADD_S
+    199902U,	// GP_LDB_S
+    199937U,	// GP_LDH_S
+    199920U,	// GP_LD_S
+    200495U,	// J
+    200499U,	// JL
+    35602U,	// JLI_S
+    35349U,	// JL_LImm
+    35342U,	// J_LImm
+    1891U,	// J_S_BLINK
+    2263059U,	// LDB_AB_rs9
+    2264060U,	// LDB_AW_rs9
+    2263098U,	// LDB_DI_AB_rs9
+    2264099U,	// LDB_DI_AW_rs9
+    8554956U,	// LDB_DI_limm
+    9079244U,	// LDB_DI_rlimm
+    9079244U,	// LDB_DI_rs9
+    71469675U,	// LDB_S_OFF
+    71469675U,	// LDB_S_rrr
+    2263195U,	// LDB_X_AB_rs9
+    2264196U,	// LDB_X_AW_rs9
+    2263162U,	// LDB_X_DI_AB_rs9
+    2264163U,	// LDB_X_DI_AW_rs9
+    8555002U,	// LDB_X_DI_limm
+    9079290U,	// LDB_X_DI_rlimm
+    9079290U,	// LDB_X_DI_rs9
+    8555672U,	// LDB_X_limm
+    9079960U,	// LDB_X_rlimm
+    9079960U,	// LDB_X_rs9
+    8554671U,	// LDB_limm
+    9078959U,	// LDB_rlimm
+    9078959U,	// LDB_rs9
+    2263082U,	// LDH_AB_rs9
+    2264083U,	// LDH_AW_rs9
+    2263130U,	// LDH_DI_AB_rs9
+    2264131U,	// LDH_DI_AW_rs9
+    8554979U,	// LDH_DI_limm
+    9079267U,	// LDH_DI_rlimm
+    9079267U,	// LDH_DI_rs9
+    71469784U,	// LDH_S_OFF
+    71470246U,	// LDH_S_X_OFF
+    71469784U,	// LDH_S_rrr
+    2263205U,	// LDH_X_AB_rs9
+    2264206U,	// LDH_X_AW_rs9
+    2263175U,	// LDH_X_DI_AB_rs9
+    2264176U,	// LDH_X_DI_AW_rs9
+    8555012U,	// LDH_X_DI_limm
+    9079300U,	// LDH_X_DI_rlimm
+    9079300U,	// LDH_X_DI_rs9
+    8555679U,	// LDH_X_limm
+    9079967U,	// LDH_X_rlimm
+    9079967U,	// LDH_X_rs9
+    8554933U,	// LDH_limm
+    9079221U,	// LDH_rlimm
+    9079221U,	// LDH_rs9
+    8555262U,	// LDI_S_u7
+    2263075U,	// LD_AB_rs9
+    2264076U,	// LD_AW_rs9
+    2263120U,	// LD_DI_AB_rs9
+    2264121U,	// LD_DI_AW_rs9
+    8554972U,	// LD_DI_limm
+    9079260U,	// LD_DI_rlimm
+    9079260U,	// LD_DI_rs9
+    71470041U,	// LD_S_AS_rrr
+    71469726U,	// LD_S_OFF
+    71469726U,	// LD_S_rrr
+    199972U,	// LD_S_s11
+    8554708U,	// LD_limm
+    9078996U,	// LD_rlimm
+    9078996U,	// LD_rs9
+    35528U,	// LEAVE_S
+    8555067U,	// LR_rs12
+    8555067U,	// LR_ru6
+    22547321U,	// LSR_S_ru5
+    1121901U,	// LSR_cc_f_rru6
+    1154669U,	// LSR_cc_rru6
+    4196738U,	// LSR_f_rrlimm
+    4196738U,	// LSR_f_rrr
+    4196738U,	// LSR_f_rrs12
+    4196738U,	// LSR_f_rru6
+    4196942U,	// LSR_rrlimm
+    4196942U,	// LSR_rrr
+    4196942U,	// LSR_rrs12
+    4196942U,	// LSR_rru6
+    1121963U,	// MAX_cc_f_rru6
+    1154731U,	// MAX_cc_rru6
+    4196775U,	// MAX_f_rrlimm
+    4196775U,	// MAX_f_rrr
+    4196775U,	// MAX_f_rrs12
+    4196775U,	// MAX_f_rru6
+    4197551U,	// MAX_rrlimm
+    4197551U,	// MAX_rrr
+    4197551U,	// MAX_rrs12
+    4197551U,	// MAX_rru6
+    1121851U,	// MIN_cc_f_rru6
+    1154619U,	// MIN_cc_rru6
+    4196701U,	// MIN_f_rrlimm
+    4196701U,	// MIN_f_rrr
+    4196701U,	// MIN_f_rrs12
+    4196701U,	// MIN_f_rru6
+    4196906U,	// MIN_rrlimm
+    4196906U,	// MIN_rrr
+    4196906U,	// MIN_rrs12
+    4196906U,	// MIN_rru6
+    2279U,	// MOV_S_NE_rlimm
+    2279U,	// MOV_S_NE_rr
+    3002U,	// MOV_S_rs3
+    36035U,	// MOV_S_s3
+    3002U,	// MOV_S_u8
+    18086U,	// MOV_cc
+    2707110U,	// MOV_cc_f_ru6
+    2739878U,	// MOV_cc_ru6
+    2623904U,	// MOV_f_ru6
+    3063U,	// MOV_rlimm
+    3063U,	// MOV_rr
+    3063U,	// MOV_rs12
+    3063U,	// MOV_ru6
+    1121951U,	// MPYMU_cc_f_rru6
+    1154719U,	// MPYMU_cc_rru6
+    4196759U,	// MPYMU_f_rrlimm
+    4196759U,	// MPYMU_f_rrr
+    4196759U,	// MPYMU_f_rrs12
+    4196759U,	// MPYMU_f_rru6
+    4197360U,	// MPYMU_rrlimm
+    4197360U,	// MPYMU_rrr
+    4197360U,	// MPYMU_rrs12
+    4197360U,	// MPYMU_rru6
+    1121845U,	// MPYM_cc_f_rru6
+    1154613U,	// MPYM_cc_rru6
+    4196693U,	// MPYM_f_rrlimm
+    4196693U,	// MPYM_f_rrr
+    4196693U,	// MPYM_f_rrs12
+    4196693U,	// MPYM_f_rru6
+    4196900U,	// MPYM_rrlimm
+    4196900U,	// MPYM_rrr
+    4196900U,	// MPYM_rrs12
+    4196900U,	// MPYM_rru6
+    1121968U,	// MPY_cc_f_rru6
+    1154736U,	// MPY_cc_rru6
+    4196782U,	// MPY_f_rrlimm
+    4196782U,	// MPY_f_rrr
+    4196782U,	// MPY_f_rrs12
+    4196782U,	// MPY_f_rru6
+    4197556U,	// MPY_rrlimm
+    4197556U,	// MPY_rrr
+    4197556U,	// MPY_rrs12
+    4197556U,	// MPY_rru6
+    2357U,	// NORMH_f_rr
+    2490U,	// NORMH_rr
+    2381U,	// NORM_f_rr
+    2590U,	// NORM_rr
+    1121887U,	// OR_cc_f_rru6
+    1154655U,	// OR_cc_rru6
+    4196718U,	// OR_f_rrlimm
+    4196718U,	// OR_f_rrr
+    4196718U,	// OR_f_rrs12
+    4196718U,	// OR_f_rru6
+    4196928U,	// OR_rrlimm
+    4196928U,	// OR_rrr
+    4196928U,	// OR_rrs12
+    4196928U,	// OR_rru6
+    232094U,	// PCL_LD
+    1935U,	// POP_S_BLINK
+    35652U,	// POP_S_r
+    1921U,	// PUSH_S_BLINK
+    35551U,	// PUSH_S_r
+    1121886U,	// ROR_cc_f_rru6
+    1154654U,	// ROR_cc_rru6
+    4196717U,	// ROR_f_rrlimm
+    4196717U,	// ROR_f_rrr
+    4196717U,	// ROR_f_rrs12
+    4196717U,	// ROR_f_rru6
+    4196927U,	// ROR_rrlimm
+    4196927U,	// ROR_rrr
+    4196927U,	// ROR_rrs12
+    4196927U,	// ROR_rru6
+    1121765U,	// RSUB_cc_f_rru6
+    1154533U,	// RSUB_cc_rru6
+    4196617U,	// RSUB_f_rrlimm
+    4196617U,	// RSUB_f_rrr
+    4196617U,	// RSUB_f_rrs12
+    4196617U,	// RSUB_f_rru6
+    4196537U,	// RSUB_rrlimm
+    4196537U,	// RSUB_rrr
+    4196537U,	// RSUB_rrs12
+    4196537U,	// RSUB_rru6
+    1121771U,	// SBC_cc_f_rru6
+    1154539U,	// SBC_cc_rru6
+    4196633U,	// SBC_f_rrlimm
+    4196633U,	// SBC_f_rrr
+    4196633U,	// SBC_f_rrs12
+    4196633U,	// SBC_f_rru6
+    4196549U,	// SBC_rrlimm
+    4196549U,	// SBC_rrr
+    4196549U,	// SBC_rrs12
+    4196549U,	// SBC_rru6
+    1121856U,	// SETEQ_cc_f_rru6
+    1154624U,	// SETEQ_cc_rru6
+    4196708U,	// SETEQ_f_rrlimm
+    4196708U,	// SETEQ_f_rrr
+    4196708U,	// SETEQ_f_rrs12
+    4196708U,	// SETEQ_f_rru6
+    4196916U,	// SETEQ_rrlimm
+    4196916U,	// SETEQ_rrr
+    4196916U,	// SETEQ_rrs12
+    4196916U,	// SETEQ_rru6
+    2321U,	// SEXB_f_rr
+    2239U,	// SEXB_rr
+    2366U,	// SEXH_f_rr
+    2502U,	// SEXH_rr
+    264855U,	// SP_ADD_S
+    36166U,	// SP_ADD_SP_S
+    297579U,	// SP_LDB_S
+    297630U,	// SP_LD_S
+    297586U,	// SP_STB_S
+    297908U,	// SP_ST_S
+    36149U,	// SP_SUB_SP_S
+    2269211U,	// STB_AB_rs9
+    2270212U,	// STB_AW_rs9
+    2269253U,	// STB_DI_AB_rs9
+    2270254U,	// STB_DI_AW_rs9
+    8554964U,	// STB_DI_limm
+    9079252U,	// STB_DI_rs9
+    71469682U,	// STB_S_OFF
+    8554676U,	// STB_limm
+    9078964U,	// STB_rs9
+    2269234U,	// STH_AB_rs9
+    2270235U,	// STH_AW_rs9
+    2269285U,	// STH_DI_AB_rs9
+    2270286U,	// STH_DI_AW_rs9
+    8554987U,	// STH_DI_limm
+    9079275U,	// STH_DI_rs9
+    71469799U,	// STH_S_OFF
+    8554945U,	// STH_limm
+    9079233U,	// STH_rs9
+    2269332U,	// ST_AB_rs9
+    2270333U,	// ST_AW_rs9
+    2269296U,	// ST_DI_AB_rs9
+    2270297U,	// ST_DI_AW_rs9
+    8554995U,	// ST_DI_limm
+    9079283U,	// ST_DI_rs9
+    71470004U,	// ST_S_OFF
+    199955U,	// ST_S_s11
+    8555500U,	// ST_limm
+    9079788U,	// ST_rs9
+    1121716U,	// SUB1_cc_f_rru6
+    1154484U,	// SUB1_cc_rru6
+    4196593U,	// SUB1_f_rrlimm
+    4196593U,	// SUB1_f_rrr
+    4196593U,	// SUB1_f_rrs12
+    4196593U,	// SUB1_f_rru6
+    4196353U,	// SUB1_rrlimm
+    4196353U,	// SUB1_rrr
+    4196353U,	// SUB1_rrs12
+    4196353U,	// SUB1_rru6
+    1121722U,	// SUB2_cc_f_rru6
+    1154490U,	// SUB2_cc_rru6
+    4196601U,	// SUB2_f_rrlimm
+    4196601U,	// SUB2_f_rrr
+    4196601U,	// SUB2_f_rrs12
+    4196601U,	// SUB2_f_rru6
+    4196359U,	// SUB2_rrlimm
+    4196359U,	// SUB2_rrr
+    4196359U,	// SUB2_rrs12
+    4196359U,	// SUB2_rru6
+    1121728U,	// SUB3_cc_f_rru6
+    1154496U,	// SUB3_cc_rru6
+    4196609U,	// SUB3_f_rrlimm
+    4196609U,	// SUB3_f_rrr
+    4196609U,	// SUB3_f_rrs12
+    4196609U,	// SUB3_f_rru6
+    4196365U,	// SUB3_rrlimm
+    4196365U,	// SUB3_rrr
+    4196365U,	// SUB3_rrs12
+    4196365U,	// SUB3_rru6
+    4196993U,	// SUB_S_rrr
+    4196993U,	// SUB_S_ru3
+    22547073U,	// SUB_S_ru5
+    1121766U,	// SUB_cc_f_rru6
+    1154534U,	// SUB_cc_rru6
+    4196618U,	// SUB_f_rrlimm
+    4196618U,	// SUB_f_rrr
+    4196618U,	// SUB_f_rrs12
+    4196618U,	// SUB_f_rru6
+    4196538U,	// SUB_rrlimm
+    4196538U,	// SUB_rrr
+    4196538U,	// SUB_rrs12
+    4196538U,	// SUB_rru6
+    1121891U,	// XOR_cc_f_rru6
+    1154659U,	// XOR_cc_rru6
+    4196724U,	// XOR_f_rrlimm
+    4196724U,	// XOR_f_rrr
+    4196724U,	// XOR_f_rrs12
+    4196724U,	// XOR_f_rru6
+    4196932U,	// XOR_rrlimm
+    4196932U,	// XOR_rrr
+    4196932U,	// XOR_rrs12
+    4196932U,	// XOR_rru6
+  };
+
+  // Emit the opcode for the instruction.
+  uint32_t Bits = 0;
+  Bits |= OpInfo0[MCInst_getOpcode(MI)] << 0;
+  MnemonicBitsInfo MBI = {
+#ifndef CAPSTONE_DIET
+    AsmStrs+(Bits & 2047)-1,
+#else
+    NULL,
+#endif // CAPSTONE_DIET
+    Bits
+  };
+  return MBI;
+}
+
+/// printInstruction - This method is automatically generated by tablegen
+/// from the instruction set description.
+static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
+  SStream_concat0(O, "");
+  MnemonicBitsInfo MnemonicInfo = getMnemonic(MI, O);
+
+  SStream_concat0(O, MnemonicInfo.first);
+
+  uint32_t Bits = MnemonicInfo.second;
+  CS_ASSERT_RET(Bits != 0 && "Cannot print this instruction.");
+
+  // Fragment 0 encoded into 4 bits for 10 unique commands.
+  switch ((Bits >> 11) & 15) {
+  default: CS_ASSERT_RET(0 && "Invalid command number.");
+  case 0:
+    // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ...
+    return;
+    break;
+  case 1:
+    // ADJCALLSTACKDOWN, ADJCALLSTACKUP, CTLZ, CTTZ, GETFI, STB_FAR, STH_FAR,...
+    printOperand(MI, 0, O);
+    break;
+  case 2:
+    // BRcc_rr_p, BRcc_ru6_p
+    printPredicateOperand(MI, 3, O);
+    SStream_concat0(O, "\t");
+    printOperand(MI, 1, O);
+    SStream_concat0(O, ", ");
+    printOperand(MI, 2, O);
+    SStream_concat0(O, ", ");
+    printOperandAddr(MI, Address, 0, O);
+    return;
+    break;
+  case 3:
+    // ADC_cc_f_rru6, ADC_cc_rru6, ADD_cc_f_rru6, ADD_cc_rru6, AND_cc_f_rru6,...
+    printPredicateOperand(MI, 2, O);
+    break;
+  case 4:
+    // ADD_S_limms3, CMP_S_limms3, STB_AB_rs9, STB_AW_rs9, STB_DI_AB_rs9, STB...
+    printOperand(MI, 1, O);
+    break;
+  case 5:
+    // BEQ_S, BGE_S, BGT_S, BHI_S, BHS_S, BL, BLE_S, BLO_S, BLS_S, BLT_S, BL_...
+    printOperandAddr(MI, Address, 0, O);
+    return;
+    break;
+  case 6:
+    // BRcc_rr, BRcc_ru6
+    printBRCCPredicateOperand(MI, 3, O);
+    SStream_concat0(O, "\t");
+    printOperand(MI, 1, O);
+    SStream_concat0(O, ", ");
+    printOperand(MI, 2, O);
+    SStream_concat0(O, ", ");
+    printOperandAddr(MI, Address, 0, O);
+    return;
+    break;
+  case 7:
+    // Bcc
+    printPredicateOperand(MI, 1, O);
+    SStream_concat0(O, "\t");
+    printOperandAddr(MI, Address, 0, O);
+    return;
+    break;
+  case 8:
+    // MOV_cc
+    printCCOperand(MI, 3, O);
+    SStream_concat0(O, "\t");
+    printOperand(MI, 0, O);
+    SStream_concat0(O, ", ");
+    printOperand(MI, 1, O);
+    return;
+    break;
+  case 9:
+    // MOV_cc_f_ru6, MOV_cc_ru6
+    printCCOperand(MI, 2, O);
+    break;
+  }
+
+
+  // Fragment 1 encoded into 4 bits for 10 unique commands.
+  switch ((Bits >> 15) & 15) {
+  default: CS_ASSERT_RET(0 && "Invalid command number.");
+  case 0:
+    // ADJCALLSTACKDOWN, CTLZ, CTTZ, GETFI, STB_FAR, STH_FAR, ST_FAR, ADC_f_r...
+    SStream_concat0(O, ", ");
+    break;
+  case 1:
+    // ADJCALLSTACKUP, EI_S, ENTER_S, GEN_TRAP_S, GP_ADD_S, JLI_S, JL_LImm, J...
+    return;
+    break;
+  case 2:
+    // ADC_cc_f_rru6, ADD_cc_f_rru6, AND_cc_f_rru6, ASL_cc_f_rru6, ASR_cc_f_r...
+    SStream_concat0(O, ".f\t");
+    printOperand(MI, 0, O);
+    SStream_concat0(O, ", ");
+    break;
+  case 3:
+    // ADC_cc_rru6, ADD_cc_rru6, AND_cc_rru6, ASL_cc_rru6, ASR_cc_rru6, LSR_c...
+    SStream_concat0(O, "\t");
+    printOperand(MI, 0, O);
+    SStream_concat0(O, ", ");
+    break;
+  case 4:
+    // BREQ_S, BRNE_S
+    SStream_concat0(O, ", 0, ");
+    printOperandAddr(MI, Address, 1, O);
+    return;
+    break;
+  case 5:
+    // COMPACT_LD_S, LDB_AB_rs9, LDB_AW_rs9, LDB_DI_AB_rs9, LDB_DI_AW_rs9, LD...
+    SStream_concat0(O, ", [");
+    break;
+  case 6:
+    // GEN_JL_S, GEN_JL_S_D, GEN_J_S, GEN_J_S_D, GP_LDB_S, GP_LDH_S, GP_LD_S,...
+    SStream_concat1(O, ']');
+    return;
+    break;
+  case 7:
+    // PCL_LD
+    SStream_concat0(O, ", [%pcl, ");
+    printOperand(MI, 1, O);
+    SStream_concat1(O, ']');
+    return;
+    break;
+  case 8:
+    // SP_ADD_S
+    SStream_concat0(O, ", %sp, ");
+    printOperand(MI, 1, O);
+    return;
+    break;
+  case 9:
+    // SP_LDB_S, SP_LD_S, SP_STB_S, SP_ST_S
+    SStream_concat0(O, ", [%sp, ");
+    printOperand(MI, 1, O);
+    SStream_concat1(O, ']');
+    return;
+    break;
+  }
+
+
+  // Fragment 2 encoded into 3 bits for 6 unique commands.
+  switch ((Bits >> 19) & 7) {
+  default: CS_ASSERT_RET(0 && "Invalid command number.");
+  case 0:
+    // ADJCALLSTACKDOWN, CTLZ, CTTZ, GETFI, ADC_f_rrlimm, ADC_f_rrr, ADC_f_rr...
+    printOperand(MI, 1, O);
+    break;
+  case 1:
+    // STB_FAR, STH_FAR, ST_FAR, LDB_DI_rlimm, LDB_DI_rs9, LDB_X_DI_rlimm, LD...
+    printMemOperandRI(MI, 1, O);
+    break;
+  case 2:
+    // ADC_cc_f_rru6, ADC_cc_rru6, ADD_cc_f_rru6, ADD_cc_rru6, AND_cc_f_rru6,...
+    printOperand(MI, 3, O);
+    SStream_concat0(O, ", ");
+    printOperand(MI, 1, O);
+    return;
+    break;
+  case 3:
+    // ADD_S_limms3, ADD_S_rlimm, ADD_S_rr, ADD_S_rs3, ADD_S_u7, ASL_S_ru5, A...
+    printOperand(MI, 0, O);
+    break;
+  case 4:
+    // LDB_AB_rs9, LDB_AW_rs9, LDB_DI_AB_rs9, LDB_DI_AW_rs9, LDB_X_AB_rs9, LD...
+    printOperand(MI, 2, O);
+    SStream_concat1(O, ',');
+    printOperand(MI, 3, O);
+    SStream_concat1(O, ']');
+    return;
+    break;
+  case 5:
+    // MOV_cc_f_ru6, MOV_cc_ru6, MOV_f_ru6
+    printU6(MI, 1, O);
+    return;
+    break;
+  }
+
+
+  // Fragment 3 encoded into 2 bits for 3 unique commands.
+  switch ((Bits >> 22) & 3) {
+  default: CS_ASSERT_RET(0 && "Invalid command number.");
+  case 0:
+    // ADJCALLSTACKDOWN, CTLZ, CTTZ, GETFI, STB_FAR, STH_FAR, ST_FAR, ADD_S_l...
+    return;
+    break;
+  case 1:
+    // ADC_f_rrlimm, ADC_f_rrr, ADC_f_rrs12, ADC_f_rru6, ADC_rrlimm, ADC_rrr,...
+    SStream_concat0(O, ", ");
+    break;
+  case 2:
+    // LDB_DI_limm, LDB_DI_rlimm, LDB_DI_rs9, LDB_X_DI_limm, LDB_X_DI_rlimm, ...
+    SStream_concat1(O, ']');
+    return;
+    break;
+  }
+
+
+  // Fragment 4 encoded into 2 bits for 3 unique commands.
+  switch ((Bits >> 24) & 3) {
+  default: CS_ASSERT_RET(0 && "Invalid command number.");
+  case 0:
+    // ADC_f_rrlimm, ADC_f_rrr, ADC_f_rrs12, ADC_f_rru6, ADC_rrlimm, ADC_rrr,...
+    printOperand(MI, 2, O);
+    break;
+  case 1:
+    // ADD_S_rlimm, ADD_S_rr, ADD_S_rs3, ADD_S_u7, ASL_S_ru5, ASR_S_ru5, BCLR...
+    printOperand(MI, 1, O);
+    return;
+    break;
+  case 2:
+    // GEN_SUB_S_NE
+    printOperand(MI, 0, O);
+    return;
+    break;
+  }
+
+
+  // Fragment 5 encoded into 1 bits for 2 unique commands.
+  if ((Bits >> 26) & 1) {
+    // COMPACT_LD_S, LDB_S_OFF, LDB_S_rrr, LDH_S_OFF, LDH_S_X_OFF, LDH_S_rrr,...
+    SStream_concat1(O, ']');
+    return;
+  } else {
+    // ADC_f_rrlimm, ADC_f_rrr, ADC_f_rrs12, ADC_f_rru6, ADC_rrlimm, ADC_rrr,...
+    return;
+  }
+
+}
+
+
+/// getRegisterName - This method is automatically generated by tblgen
+/// from the register set description.  This returns the assembler name
+/// for the specified register.
+static const char *getRegisterName(unsigned RegNo) {
+#ifndef CAPSTONE_DIET
+  CS_ASSERT_RET_VAL(RegNo && RegNo < 66 && "Invalid register number!", NULL);
+
+  static const char AsmStrs[] = {
+  /* 0 */ "%r10\0"
+  /* 5 */ "%r20\0"
+  /* 10 */ "%r30\0"
+  /* 15 */ "%r40\0"
+  /* 20 */ "%r50\0"
+  /* 25 */ "%r60\0"
+  /* 30 */ "%r0\0"
+  /* 34 */ "%r11\0"
+  /* 39 */ "%r21\0"
+  /* 44 */ "%r41\0"
+  /* 49 */ "%r51\0"
+  /* 54 */ "%r61\0"
+  /* 59 */ "%r1\0"
+  /* 63 */ "%r12\0"
+  /* 68 */ "%r22\0"
+  /* 73 */ "%r32\0"
+  /* 78 */ "status32\0"
+  /* 87 */ "%r42\0"
+  /* 92 */ "%r52\0"
+  /* 97 */ "%r62\0"
+  /* 102 */ "%r2\0"
+  /* 106 */ "%r13\0"
+  /* 111 */ "%r23\0"
+  /* 116 */ "%r33\0"
+  /* 121 */ "%r43\0"
+  /* 126 */ "%r53\0"
+  /* 131 */ "%r63\0"
+  /* 136 */ "%r3\0"
+  /* 140 */ "%r14\0"
+  /* 145 */ "%r24\0"
+  /* 150 */ "%r34\0"
+  /* 155 */ "%r44\0"
+  /* 160 */ "%r54\0"
+  /* 165 */ "%r4\0"
+  /* 169 */ "%r15\0"
+  /* 174 */ "%r25\0"
+  /* 179 */ "%r35\0"
+  /* 184 */ "%r45\0"
+  /* 189 */ "%r55\0"
+  /* 194 */ "%r5\0"
+  /* 198 */ "%r16\0"
+  /* 203 */ "%r36\0"
+  /* 208 */ "%r46\0"
+  /* 213 */ "%r56\0"
+  /* 218 */ "%r6\0"
+  /* 222 */ "%r17\0"
+  /* 227 */ "%r37\0"
+  /* 232 */ "%r47\0"
+  /* 237 */ "%r57\0"
+  /* 242 */ "%r7\0"
+  /* 246 */ "%r18\0"
+  /* 251 */ "%r38\0"
+  /* 256 */ "%r48\0"
+  /* 261 */ "%r58\0"
+  /* 266 */ "%r8\0"
+  /* 270 */ "%r19\0"
+  /* 275 */ "%r39\0"
+  /* 280 */ "%r49\0"
+  /* 285 */ "%r59\0"
+  /* 290 */ "%r9\0"
+  /* 294 */ "%blink\0"
+  /* 301 */ "%ilink\0"
+  /* 308 */ "%fp\0"
+  /* 312 */ "%gp\0"
+  /* 316 */ "%sp\0"
+};
+  static const uint16_t RegAsmOffset[] = {
+    294, 308, 312, 301, 316, 30, 59, 102, 136, 165, 194, 218, 242, 266, 
+    290, 0, 34, 63, 106, 140, 169, 198, 222, 246, 270, 5, 39, 68, 
+    111, 145, 174, 10, 73, 116, 150, 179, 203, 227, 251, 275, 15, 44, 
+    87, 121, 155, 184, 208, 232, 256, 280, 20, 49, 92, 126, 160, 189, 
+    213, 237, 261, 285, 25, 54, 97, 131, 78, 
+  };
+
+  CS_ASSERT_RET_VAL(*(AsmStrs+RegAsmOffset[RegNo-1]) &&
+          "Invalid alt name index for register!", NULL);
+  return AsmStrs+RegAsmOffset[RegNo-1];
+#else
+  return NULL;
+#endif // CAPSTONE_DIET
+}
+#ifdef PRINT_ALIAS_INSTR
+#undef PRINT_ALIAS_INSTR
+
+static bool printAliasInstr(MCInst *MI, uint64_t Address, SStream *OS) {
+#ifndef CAPSTONE_DIET
+  return false;
+#endif // CAPSTONE_DIET
+}
+
+#endif // PRINT_ALIAS_INSTR
diff --git a/arch/ARC/ARCGenCSInsnEnum.inc b/arch/ARC/ARCGenCSInsnEnum.inc
new file mode 100644
index 0000000000..5176afb396
--- /dev/null
+++ b/arch/ARC/ARCGenCSInsnEnum.inc
@@ -0,0 +1,204 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+  ARC_INS_INVALID,
+  ARC_INS_h,
+  ARC_INS_PBR,
+  ARC_INS_ERROR_FLS,
+  ARC_INS_ERROR_FFS,
+  ARC_INS_PLDFI,
+  ARC_INS_STB_FAR,
+  ARC_INS_STH_FAR,
+  ARC_INS_ST_FAR,
+  ARC_INS_ADC,
+  ARC_INS_ADC_F,
+  ARC_INS_ADD_S,
+  ARC_INS_ADD,
+  ARC_INS_ADD_F,
+  ARC_INS_AND,
+  ARC_INS_AND_F,
+  ARC_INS_ASL_S,
+  ARC_INS_ASL,
+  ARC_INS_ASL_F,
+  ARC_INS_ASR_S,
+  ARC_INS_ASR,
+  ARC_INS_ASR_F,
+  ARC_INS_BCLR_S,
+  ARC_INS_BEQ_S,
+  ARC_INS_BGE_S,
+  ARC_INS_BGT_S,
+  ARC_INS_BHI_S,
+  ARC_INS_BHS_S,
+  ARC_INS_BL,
+  ARC_INS_BLE_S,
+  ARC_INS_BLO_S,
+  ARC_INS_BLS_S,
+  ARC_INS_BLT_S,
+  ARC_INS_BL_S,
+  ARC_INS_BMSK_S,
+  ARC_INS_BNE_S,
+  ARC_INS_B,
+  ARC_INS_BREQ_S,
+  ARC_INS_BRNE_S,
+  ARC_INS_BR,
+  ARC_INS_BSET_S,
+  ARC_INS_BTST_S,
+  ARC_INS_B_S,
+  ARC_INS_CMP_S,
+  ARC_INS_CMP,
+  ARC_INS_LD_S,
+  ARC_INS_MOV_S,
+  ARC_INS_EI_S,
+  ARC_INS_ENTER_S,
+  ARC_INS_FFS_F,
+  ARC_INS_FFS,
+  ARC_INS_FLS_F,
+  ARC_INS_FLS,
+  ARC_INS_ABS_S,
+  ARC_INS_ADD1_S,
+  ARC_INS_ADD2_S,
+  ARC_INS_ADD3_S,
+  ARC_INS_AND_S,
+  ARC_INS_BIC_S,
+  ARC_INS_BRK_S,
+  ARC_INS_EXTB_S,
+  ARC_INS_EXTH_S,
+  ARC_INS_JEQ_S,
+  ARC_INS_JL_S,
+  ARC_INS_JL_S_D,
+  ARC_INS_JNE_S,
+  ARC_INS_J_S,
+  ARC_INS_J_S_D,
+  ARC_INS_LSR_S,
+  ARC_INS_MPYUW_S,
+  ARC_INS_MPYW_S,
+  ARC_INS_MPY_S,
+  ARC_INS_NEG_S,
+  ARC_INS_NOP_S,
+  ARC_INS_NOT_S,
+  ARC_INS_OR_S,
+  ARC_INS_SEXB_S,
+  ARC_INS_SEXH_S,
+  ARC_INS_SUB_S,
+  ARC_INS_SUB_S_NE,
+  ARC_INS_SWI_S,
+  ARC_INS_TRAP_S,
+  ARC_INS_TST_S,
+  ARC_INS_UNIMP_S,
+  ARC_INS_XOR_S,
+  ARC_INS_LDB_S,
+  ARC_INS_LDH_S,
+  ARC_INS_J,
+  ARC_INS_JL,
+  ARC_INS_JLI_S,
+  ARC_INS_LDB_AB,
+  ARC_INS_LDB_AW,
+  ARC_INS_LDB_DI_AB,
+  ARC_INS_LDB_DI_AW,
+  ARC_INS_LDB_DI,
+  ARC_INS_LDB_X_AB,
+  ARC_INS_LDB_X_AW,
+  ARC_INS_LDB_X_DI_AB,
+  ARC_INS_LDB_X_DI_AW,
+  ARC_INS_LDB_X_DI,
+  ARC_INS_LDB_X,
+  ARC_INS_LDB,
+  ARC_INS_LDH_AB,
+  ARC_INS_LDH_AW,
+  ARC_INS_LDH_DI_AB,
+  ARC_INS_LDH_DI_AW,
+  ARC_INS_LDH_DI,
+  ARC_INS_LDH_S_X,
+  ARC_INS_LDH_X_AB,
+  ARC_INS_LDH_X_AW,
+  ARC_INS_LDH_X_DI_AB,
+  ARC_INS_LDH_X_DI_AW,
+  ARC_INS_LDH_X_DI,
+  ARC_INS_LDH_X,
+  ARC_INS_LDH,
+  ARC_INS_LDI_S,
+  ARC_INS_LD_AB,
+  ARC_INS_LD_AW,
+  ARC_INS_LD_DI_AB,
+  ARC_INS_LD_DI_AW,
+  ARC_INS_LD_DI,
+  ARC_INS_LD_S_AS,
+  ARC_INS_LD,
+  ARC_INS_LEAVE_S,
+  ARC_INS_LR,
+  ARC_INS_LSR,
+  ARC_INS_LSR_F,
+  ARC_INS_MAX,
+  ARC_INS_MAX_F,
+  ARC_INS_MIN,
+  ARC_INS_MIN_F,
+  ARC_INS_MOV_S_NE,
+  ARC_INS_MOV,
+  ARC_INS_MOV_F,
+  ARC_INS_MPYMU,
+  ARC_INS_MPYMU_F,
+  ARC_INS_MPYM,
+  ARC_INS_MPYM_F,
+  ARC_INS_MPY,
+  ARC_INS_MPY_F,
+  ARC_INS_NORMH_F,
+  ARC_INS_NORMH,
+  ARC_INS_NORM_F,
+  ARC_INS_NORM,
+  ARC_INS_OR,
+  ARC_INS_OR_F,
+  ARC_INS_POP_S,
+  ARC_INS_PUSH_S,
+  ARC_INS_ROR,
+  ARC_INS_ROR_F,
+  ARC_INS_RSUB,
+  ARC_INS_RSUB_F,
+  ARC_INS_SBC,
+  ARC_INS_SBC_F,
+  ARC_INS_SETEQ,
+  ARC_INS_SETEQ_F,
+  ARC_INS_SEXB_F,
+  ARC_INS_SEXB,
+  ARC_INS_SEXH_F,
+  ARC_INS_SEXH,
+  ARC_INS_STB_S,
+  ARC_INS_ST_S,
+  ARC_INS_STB_AB,
+  ARC_INS_STB_AW,
+  ARC_INS_STB_DI_AB,
+  ARC_INS_STB_DI_AW,
+  ARC_INS_STB_DI,
+  ARC_INS_STB,
+  ARC_INS_STH_AB,
+  ARC_INS_STH_AW,
+  ARC_INS_STH_DI_AB,
+  ARC_INS_STH_DI_AW,
+  ARC_INS_STH_DI,
+  ARC_INS_STH_S,
+  ARC_INS_STH,
+  ARC_INS_ST_AB,
+  ARC_INS_ST_AW,
+  ARC_INS_ST_DI_AB,
+  ARC_INS_ST_DI_AW,
+  ARC_INS_ST_DI,
+  ARC_INS_ST,
+  ARC_INS_SUB1,
+  ARC_INS_SUB1_F,
+  ARC_INS_SUB2,
+  ARC_INS_SUB2_F,
+  ARC_INS_SUB3,
+  ARC_INS_SUB3_F,
+  ARC_INS_SUB,
+  ARC_INS_SUB_F,
+  ARC_INS_XOR,
+  ARC_INS_XOR_F,
diff --git a/arch/ARC/ARCGenCSMappingInsn.inc b/arch/ARC/ARCGenCSMappingInsn.inc
new file mode 100644
index 0000000000..54ef471c2d
--- /dev/null
+++ b/arch/ARC/ARCGenCSMappingInsn.inc
@@ -0,0 +1,5494 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+{
+  /* PHINODE */
+  ARC_PHI /* 0 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_INLINEASM /* 1 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_INLINEASM_BR /* 2 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_CFI_INSTRUCTION /* 3 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_EH_LABEL /* 4 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_GC_LABEL /* 5 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_ANNOTATION_LABEL /* 6 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_KILL /* 7 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_EXTRACT_SUBREG /* 8 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_INSERT_SUBREG /* 9 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_IMPLICIT_DEF /* 10 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_SUBREG_TO_REG /* 11 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_COPY_TO_REGCLASS /* 12 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* DBG_VALUE */
+  ARC_DBG_VALUE /* 13 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* DBG_VALUE_LIST */
+  ARC_DBG_VALUE_LIST /* 14 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* DBG_INSTR_REF */
+  ARC_DBG_INSTR_REF /* 15 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* DBG_PHI */
+  ARC_DBG_PHI /* 16 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* DBG_LABEL */
+  ARC_DBG_LABEL /* 17 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_REG_SEQUENCE /* 18 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_COPY /* 19 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* BUNDLE */
+  ARC_BUNDLE /* 20 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* LIFETIME_START */
+  ARC_LIFETIME_START /* 21 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* LIFETIME_END */
+  ARC_LIFETIME_END /* 22 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* PSEUDO_PROBE */
+  ARC_PSEUDO_PROBE /* 23 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_ARITH_FENCE /* 24 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_STACKMAP /* 25 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* # FEntry call */
+  ARC_FENTRY_CALL /* 26 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_PATCHPOINT /* 27 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_LOAD_STACK_GUARD /* 28 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_PREALLOCATED_SETUP /* 29 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_PREALLOCATED_ARG /* 30 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_STATEPOINT /* 31 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_LOCAL_ESCAPE /* 32 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_FAULTING_OP /* 33 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_PATCHABLE_OP /* 34 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* # XRay Function Enter. */
+  ARC_PATCHABLE_FUNCTION_ENTER /* 35 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* # XRay Function Patchable RET. */
+  ARC_PATCHABLE_RET /* 36 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* # XRay Function Exit. */
+  ARC_PATCHABLE_FUNCTION_EXIT /* 37 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* # XRay Tail Call Exit. */
+  ARC_PATCHABLE_TAIL_CALL /* 38 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* # XRay Custom Event Log. */
+  ARC_PATCHABLE_EVENT_CALL /* 39 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* # XRay Typed Event Log. */
+  ARC_PATCHABLE_TYPED_EVENT_CALL /* 40 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_ICALL_BRANCH_FUNNEL /* 41 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_MEMBARRIER /* 42 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_JUMP_TABLE_DEBUG_INFO /* 43 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_ASSERT_SEXT /* 44 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_ASSERT_ZEXT /* 45 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_ASSERT_ALIGN /* 46 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_ADD /* 47 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_SUB /* 48 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_MUL /* 49 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_SDIV /* 50 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_UDIV /* 51 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_SREM /* 52 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_UREM /* 53 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_SDIVREM /* 54 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_UDIVREM /* 55 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_AND /* 56 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_OR /* 57 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_XOR /* 58 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_IMPLICIT_DEF /* 59 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_PHI /* 60 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FRAME_INDEX /* 61 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_GLOBAL_VALUE /* 62 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_CONSTANT_POOL /* 63 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_EXTRACT /* 64 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_UNMERGE_VALUES /* 65 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_INSERT /* 66 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_MERGE_VALUES /* 67 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_BUILD_VECTOR /* 68 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_BUILD_VECTOR_TRUNC /* 69 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_CONCAT_VECTORS /* 70 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_PTRTOINT /* 71 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_INTTOPTR /* 72 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_BITCAST /* 73 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FREEZE /* 74 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_CONSTANT_FOLD_BARRIER /* 75 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_INTRINSIC_FPTRUNC_ROUND /* 76 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_INTRINSIC_TRUNC /* 77 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_INTRINSIC_ROUND /* 78 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_INTRINSIC_LRINT /* 79 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_INTRINSIC_ROUNDEVEN /* 80 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_READCYCLECOUNTER /* 81 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_LOAD /* 82 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_SEXTLOAD /* 83 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_ZEXTLOAD /* 84 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_INDEXED_LOAD /* 85 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_INDEXED_SEXTLOAD /* 86 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_INDEXED_ZEXTLOAD /* 87 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_STORE /* 88 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_INDEXED_STORE /* 89 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_ATOMIC_CMPXCHG_WITH_SUCCESS /* 90 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_ATOMIC_CMPXCHG /* 91 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_ATOMICRMW_XCHG /* 92 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_ATOMICRMW_ADD /* 93 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_ATOMICRMW_SUB /* 94 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_ATOMICRMW_AND /* 95 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_ATOMICRMW_NAND /* 96 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_ATOMICRMW_OR /* 97 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_ATOMICRMW_XOR /* 98 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_ATOMICRMW_MAX /* 99 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_ATOMICRMW_MIN /* 100 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_ATOMICRMW_UMAX /* 101 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_ATOMICRMW_UMIN /* 102 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_ATOMICRMW_FADD /* 103 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_ATOMICRMW_FSUB /* 104 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_ATOMICRMW_FMAX /* 105 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_ATOMICRMW_FMIN /* 106 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_ATOMICRMW_UINC_WRAP /* 107 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_ATOMICRMW_UDEC_WRAP /* 108 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FENCE /* 109 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_PREFETCH /* 110 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_BRCOND /* 111 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_BRINDIRECT /* 112 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_INVOKE_REGION_START /* 113 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_INTRINSIC /* 114 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_INTRINSIC_W_SIDE_EFFECTS /* 115 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_INTRINSIC_CONVERGENT /* 116 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS /* 117 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_ANYEXT /* 118 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_TRUNC /* 119 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_CONSTANT /* 120 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FCONSTANT /* 121 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_VASTART /* 122 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_VAARG /* 123 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_SEXT /* 124 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_SEXT_INREG /* 125 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_ZEXT /* 126 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_SHL /* 127 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_LSHR /* 128 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_ASHR /* 129 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FSHL /* 130 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FSHR /* 131 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_ROTR /* 132 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_ROTL /* 133 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_ICMP /* 134 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FCMP /* 135 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_SELECT /* 136 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_UADDO /* 137 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_UADDE /* 138 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_USUBO /* 139 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_USUBE /* 140 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_SADDO /* 141 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_SADDE /* 142 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_SSUBO /* 143 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_SSUBE /* 144 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_UMULO /* 145 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_SMULO /* 146 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_UMULH /* 147 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_SMULH /* 148 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_UADDSAT /* 149 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_SADDSAT /* 150 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_USUBSAT /* 151 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_SSUBSAT /* 152 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_USHLSAT /* 153 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_SSHLSAT /* 154 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_SMULFIX /* 155 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_UMULFIX /* 156 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_SMULFIXSAT /* 157 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_UMULFIXSAT /* 158 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_SDIVFIX /* 159 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_UDIVFIX /* 160 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_SDIVFIXSAT /* 161 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_UDIVFIXSAT /* 162 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FADD /* 163 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FSUB /* 164 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FMUL /* 165 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FMA /* 166 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FMAD /* 167 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FDIV /* 168 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FREM /* 169 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FPOW /* 170 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FPOWI /* 171 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FEXP /* 172 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FEXP2 /* 173 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FEXP10 /* 174 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FLOG /* 175 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FLOG2 /* 176 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FLOG10 /* 177 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FLDEXP /* 178 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FFREXP /* 179 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FNEG /* 180 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FPEXT /* 181 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FPTRUNC /* 182 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FPTOSI /* 183 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FPTOUI /* 184 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_SITOFP /* 185 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_UITOFP /* 186 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FABS /* 187 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FCOPYSIGN /* 188 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_IS_FPCLASS /* 189 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FCANONICALIZE /* 190 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FMINNUM /* 191 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FMAXNUM /* 192 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FMINNUM_IEEE /* 193 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FMAXNUM_IEEE /* 194 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FMINIMUM /* 195 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FMAXIMUM /* 196 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_GET_FPENV /* 197 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_SET_FPENV /* 198 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_RESET_FPENV /* 199 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_GET_FPMODE /* 200 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_SET_FPMODE /* 201 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_RESET_FPMODE /* 202 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_PTR_ADD /* 203 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_PTRMASK /* 204 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_SMIN /* 205 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_SMAX /* 206 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_UMIN /* 207 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_UMAX /* 208 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_ABS /* 209 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_LROUND /* 210 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_LLROUND /* 211 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_BR /* 212 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_BRJT /* 213 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_INSERT_VECTOR_ELT /* 214 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_EXTRACT_VECTOR_ELT /* 215 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_SHUFFLE_VECTOR /* 216 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_CTTZ /* 217 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_CTTZ_ZERO_UNDEF /* 218 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_CTLZ /* 219 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_CTLZ_ZERO_UNDEF /* 220 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_CTPOP /* 221 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_BSWAP /* 222 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_BITREVERSE /* 223 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FCEIL /* 224 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FCOS /* 225 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FSIN /* 226 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FSQRT /* 227 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FFLOOR /* 228 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FRINT /* 229 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_FNEARBYINT /* 230 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_ADDRSPACE_CAST /* 231 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_BLOCK_ADDR /* 232 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_JUMP_TABLE /* 233 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_DYN_STACKALLOC /* 234 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_STACKSAVE /* 235 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_STACKRESTORE /* 236 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_STRICT_FADD /* 237 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_STRICT_FSUB /* 238 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_STRICT_FMUL /* 239 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_STRICT_FDIV /* 240 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_STRICT_FREM /* 241 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_STRICT_FMA /* 242 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_STRICT_FSQRT /* 243 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_STRICT_FLDEXP /* 244 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_READ_REGISTER /* 245 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_WRITE_REGISTER /* 246 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_MEMCPY /* 247 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_MEMCPY_INLINE /* 248 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_MEMMOVE /* 249 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_MEMSET /* 250 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_BZERO /* 251 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_VECREDUCE_SEQ_FADD /* 252 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_VECREDUCE_SEQ_FMUL /* 253 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_VECREDUCE_FADD /* 254 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_VECREDUCE_FMUL /* 255 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_VECREDUCE_FMAX /* 256 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_VECREDUCE_FMIN /* 257 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_VECREDUCE_FMAXIMUM /* 258 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_VECREDUCE_FMINIMUM /* 259 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_VECREDUCE_ADD /* 260 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_VECREDUCE_MUL /* 261 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_VECREDUCE_AND /* 262 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_VECREDUCE_OR /* 263 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_VECREDUCE_XOR /* 264 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_VECREDUCE_SMAX /* 265 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_VECREDUCE_SMIN /* 266 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_VECREDUCE_UMAX /* 267 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_VECREDUCE_UMIN /* 268 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_SBFX /* 269 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARC_G_UBFX /* 270 */, ARC_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+  #endif
+},
+{
+  /* # ADJCALLSTACKDOWN $amt, $amt2 */
+  ARC_ADJCALLSTACKDOWN /* 271 */, ARC_INS_h,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_SP, 0 }, { ARC_REG_SP, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* # ADJCALLSTACKUP $amt1 */
+  ARC_ADJCALLSTACKUP /* 272 */, ARC_INS_h,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_SP, 0 }, { ARC_REG_SP, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* pbr$cc	$B, $C, $T */
+  ARC_BRcc_rr_p /* 273 */, ARC_INS_PBR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARC_GRP_JUMP, ARC_GRP_BRANCH_RELATIVE, 0 }, 1, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* pbr$cc	$B, $C, $T */
+  ARC_BRcc_ru6_p /* 274 */, ARC_INS_PBR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARC_GRP_JUMP, ARC_GRP_BRANCH_RELATIVE, 0 }, 1, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* error.fls $A, $B */
+  ARC_CTLZ /* 275 */, ARC_INS_ERROR_FLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* error.ffs $A, $B */
+  ARC_CTTZ /* 276 */, ARC_INS_ERROR_FFS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* pldfi $dst, $addr */
+  ARC_GETFI /* 277 */, ARC_INS_PLDFI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* STB_FAR $dst, $addr */
+  ARC_STB_FAR /* 278 */, ARC_INS_STB_FAR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* STH_FAR $dst, $addr */
+  ARC_STH_FAR /* 279 */, ARC_INS_STH_FAR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ST_FAR $dst, $addr */
+  ARC_ST_FAR /* 280 */, ARC_INS_ST_FAR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* adc.${cc}.f	$A, $B, $U6 */
+  ARC_ADC_cc_f_rru6 /* 281 */, ARC_INS_ADC,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* adc.$cc	$A, $B, $U6 */
+  ARC_ADC_cc_rru6 /* 282 */, ARC_INS_ADC,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* adc.f	$A, $B, $LImm */
+  ARC_ADC_f_rrlimm /* 283 */, ARC_INS_ADC_F,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* adc.f	$A, $B, $C */
+  ARC_ADC_f_rrr /* 284 */, ARC_INS_ADC_F,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* adc.f	$B, $in, $S12 */
+  ARC_ADC_f_rrs12 /* 285 */, ARC_INS_ADC_F,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* adc.f	$A, $B, $U6 */
+  ARC_ADC_f_rru6 /* 286 */, ARC_INS_ADC_F,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* adc	$A, $B, $LImm */
+  ARC_ADC_rrlimm /* 287 */, ARC_INS_ADC,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* adc	$A, $B, $C */
+  ARC_ADC_rrr /* 288 */, ARC_INS_ADC,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* adc	$B, $in, $S12 */
+  ARC_ADC_rrs12 /* 289 */, ARC_INS_ADC,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* adc	$A, $B, $U6 */
+  ARC_ADC_rru6 /* 290 */, ARC_INS_ADC,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* add_s	0, $LImm, $b_s3 */
+  ARC_ADD_S_limms3 /* 291 */, ARC_INS_ADD_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* add_s	$b_s3, $b_s3, $LImm */
+  ARC_ADD_S_rlimm /* 292 */, ARC_INS_ADD_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* add_s	$b_s3, $b_s3, $h */
+  ARC_ADD_S_rr /* 293 */, ARC_INS_ADD_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* add_s	$a, $b, $c */
+  ARC_ADD_S_rrr /* 294 */, ARC_INS_ADD_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* add_s	$r, $b, $u6 */
+  ARC_ADD_S_rru6 /* 295 */, ARC_INS_ADD_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* add_s	$h, $h, $b_s3 */
+  ARC_ADD_S_rs3 /* 296 */, ARC_INS_ADD_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* add_s	$c, $b, $u3 */
+  ARC_ADD_S_ru3 /* 297 */, ARC_INS_ADD_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* add_s	$b, $b, $u7 */
+  ARC_ADD_S_u7 /* 298 */, ARC_INS_ADD_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* add.${cc}.f	$A, $B, $U6 */
+  ARC_ADD_cc_f_rru6 /* 299 */, ARC_INS_ADD,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* add.$cc	$A, $B, $U6 */
+  ARC_ADD_cc_rru6 /* 300 */, ARC_INS_ADD,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* add.f	$A, $B, $LImm */
+  ARC_ADD_f_rrlimm /* 301 */, ARC_INS_ADD_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* add.f	$A, $B, $C */
+  ARC_ADD_f_rrr /* 302 */, ARC_INS_ADD_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* add.f	$B, $in, $S12 */
+  ARC_ADD_f_rrs12 /* 303 */, ARC_INS_ADD_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* add.f	$A, $B, $U6 */
+  ARC_ADD_f_rru6 /* 304 */, ARC_INS_ADD_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* add	$A, $B, $LImm */
+  ARC_ADD_rrlimm /* 305 */, ARC_INS_ADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* add	$A, $B, $C */
+  ARC_ADD_rrr /* 306 */, ARC_INS_ADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* add	$B, $in, $S12 */
+  ARC_ADD_rrs12 /* 307 */, ARC_INS_ADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* add	$A, $B, $U6 */
+  ARC_ADD_rru6 /* 308 */, ARC_INS_ADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* and.${cc}.f	$A, $B, $U6 */
+  ARC_AND_cc_f_rru6 /* 309 */, ARC_INS_AND,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* and.$cc	$A, $B, $U6 */
+  ARC_AND_cc_rru6 /* 310 */, ARC_INS_AND,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* and.f	$A, $B, $LImm */
+  ARC_AND_f_rrlimm /* 311 */, ARC_INS_AND_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* and.f	$A, $B, $C */
+  ARC_AND_f_rrr /* 312 */, ARC_INS_AND_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* and.f	$B, $in, $S12 */
+  ARC_AND_f_rrs12 /* 313 */, ARC_INS_AND_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* and.f	$A, $B, $U6 */
+  ARC_AND_f_rru6 /* 314 */, ARC_INS_AND_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* and	$A, $B, $LImm */
+  ARC_AND_rrlimm /* 315 */, ARC_INS_AND,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* and	$A, $B, $C */
+  ARC_AND_rrr /* 316 */, ARC_INS_AND,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* and	$B, $in, $S12 */
+  ARC_AND_rrs12 /* 317 */, ARC_INS_AND,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* and	$A, $B, $U6 */
+  ARC_AND_rru6 /* 318 */, ARC_INS_AND,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* asl_s	$c, $b, $u3 */
+  ARC_ASL_S_ru3 /* 319 */, ARC_INS_ASL_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* asl_s	$b, $b, $u5 */
+  ARC_ASL_S_ru5 /* 320 */, ARC_INS_ASL_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* asl.${cc}.f	$A, $B, $U6 */
+  ARC_ASL_cc_f_rru6 /* 321 */, ARC_INS_ASL,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* asl.$cc	$A, $B, $U6 */
+  ARC_ASL_cc_rru6 /* 322 */, ARC_INS_ASL,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* asl.f	$A, $B, $LImm */
+  ARC_ASL_f_rrlimm /* 323 */, ARC_INS_ASL_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* asl.f	$A, $B, $C */
+  ARC_ASL_f_rrr /* 324 */, ARC_INS_ASL_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* asl.f	$B, $in, $S12 */
+  ARC_ASL_f_rrs12 /* 325 */, ARC_INS_ASL_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* asl.f	$A, $B, $U6 */
+  ARC_ASL_f_rru6 /* 326 */, ARC_INS_ASL_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* asl	$A, $B, $LImm */
+  ARC_ASL_rrlimm /* 327 */, ARC_INS_ASL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* asl	$A, $B, $C */
+  ARC_ASL_rrr /* 328 */, ARC_INS_ASL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* asl	$B, $in, $S12 */
+  ARC_ASL_rrs12 /* 329 */, ARC_INS_ASL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* asl	$A, $B, $U6 */
+  ARC_ASL_rru6 /* 330 */, ARC_INS_ASL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* asr_s	$c, $b, $u3 */
+  ARC_ASR_S_ru3 /* 331 */, ARC_INS_ASR_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* asr_s	$b, $b, $u5 */
+  ARC_ASR_S_ru5 /* 332 */, ARC_INS_ASR_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* asr.${cc}.f	$A, $B, $U6 */
+  ARC_ASR_cc_f_rru6 /* 333 */, ARC_INS_ASR,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* asr.$cc	$A, $B, $U6 */
+  ARC_ASR_cc_rru6 /* 334 */, ARC_INS_ASR,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* asr.f	$A, $B, $LImm */
+  ARC_ASR_f_rrlimm /* 335 */, ARC_INS_ASR_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* asr.f	$A, $B, $C */
+  ARC_ASR_f_rrr /* 336 */, ARC_INS_ASR_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* asr.f	$B, $in, $S12 */
+  ARC_ASR_f_rrs12 /* 337 */, ARC_INS_ASR_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* asr.f	$A, $B, $U6 */
+  ARC_ASR_f_rru6 /* 338 */, ARC_INS_ASR_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* asr	$A, $B, $LImm */
+  ARC_ASR_rrlimm /* 339 */, ARC_INS_ASR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* asr	$A, $B, $C */
+  ARC_ASR_rrr /* 340 */, ARC_INS_ASR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* asr	$B, $in, $S12 */
+  ARC_ASR_rrs12 /* 341 */, ARC_INS_ASR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* asr	$A, $B, $U6 */
+  ARC_ASR_rru6 /* 342 */, ARC_INS_ASR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* bclr_s	$b, $b, $u5 */
+  ARC_BCLR_S_ru5 /* 343 */, ARC_INS_BCLR_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* beq_s	$s */
+  ARC_BEQ_S /* 344 */, ARC_INS_BEQ_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARC_GRP_JUMP, ARC_GRP_BRANCH_RELATIVE, 0 }, 1, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* bge_s	$s */
+  ARC_BGE_S /* 345 */, ARC_INS_BGE_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARC_GRP_JUMP, ARC_GRP_BRANCH_RELATIVE, 0 }, 1, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* bgt_s	$s */
+  ARC_BGT_S /* 346 */, ARC_INS_BGT_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARC_GRP_JUMP, ARC_GRP_BRANCH_RELATIVE, 0 }, 1, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* bhi_s	$s */
+  ARC_BHI_S /* 347 */, ARC_INS_BHI_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARC_GRP_JUMP, ARC_GRP_BRANCH_RELATIVE, 0 }, 1, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* bhs_s	$s */
+  ARC_BHS_S /* 348 */, ARC_INS_BHS_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARC_GRP_JUMP, ARC_GRP_BRANCH_RELATIVE, 0 }, 1, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* bl	$S25 */
+  ARC_BL /* 349 */, ARC_INS_BL,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_SP, 0 }, { ARC_REG_BLINK, 0 }, { ARC_GRP_CALL, ARC_GRP_BRANCH_RELATIVE, 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ble_s	$s */
+  ARC_BLE_S /* 350 */, ARC_INS_BLE_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARC_GRP_JUMP, ARC_GRP_BRANCH_RELATIVE, 0 }, 1, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* blo_s	$s */
+  ARC_BLO_S /* 351 */, ARC_INS_BLO_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARC_GRP_JUMP, ARC_GRP_BRANCH_RELATIVE, 0 }, 1, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* bls_s	$s */
+  ARC_BLS_S /* 352 */, ARC_INS_BLS_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARC_GRP_JUMP, ARC_GRP_BRANCH_RELATIVE, 0 }, 1, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* blt_s	$s */
+  ARC_BLT_S /* 353 */, ARC_INS_BLT_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARC_GRP_JUMP, ARC_GRP_BRANCH_RELATIVE, 0 }, 1, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* bl_s	$s13 */
+  ARC_BL_S /* 354 */, ARC_INS_BL_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARC_GRP_CALL, ARC_GRP_BRANCH_RELATIVE, 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* bmsk_s	$b, $b, $u5 */
+  ARC_BMSK_S_ru5 /* 355 */, ARC_INS_BMSK_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* bne_s	$s */
+  ARC_BNE_S /* 356 */, ARC_INS_BNE_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARC_GRP_JUMP, ARC_GRP_BRANCH_RELATIVE, 0 }, 1, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* b	$S25 */
+  ARC_BR /* 357 */, ARC_INS_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARC_GRP_JUMP, ARC_GRP_BRANCH_RELATIVE, 0 }, 1, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* breq_s	$b, 0, $s8 */
+  ARC_BREQ_S /* 358 */, ARC_INS_BREQ_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARC_GRP_JUMP, ARC_GRP_BRANCH_RELATIVE, 0 }, 1, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* brne_s	$b, 0, $s8 */
+  ARC_BRNE_S /* 359 */, ARC_INS_BRNE_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARC_GRP_JUMP, ARC_GRP_BRANCH_RELATIVE, 0 }, 1, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* br$cc	$B, $C, $S9 */
+  ARC_BRcc_rr /* 360 */, ARC_INS_BR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARC_GRP_JUMP, ARC_GRP_BRANCH_RELATIVE, 0 }, 1, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* br$cc	$B, $C, $S9 */
+  ARC_BRcc_ru6 /* 361 */, ARC_INS_BR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARC_GRP_JUMP, ARC_GRP_BRANCH_RELATIVE, 0 }, 1, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* bset_s	$b, $b, $u5 */
+  ARC_BSET_S_ru5 /* 362 */, ARC_INS_BSET_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* btst_s	$b, $u5 */
+  ARC_BTST_S_ru5 /* 363 */, ARC_INS_BTST_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* b_s	$s */
+  ARC_B_S /* 364 */, ARC_INS_B_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARC_GRP_JUMP, ARC_GRP_BRANCH_RELATIVE, 0 }, 1, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* b$cc	$S21 */
+  ARC_Bcc /* 365 */, ARC_INS_B,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { 0 }, { ARC_GRP_JUMP, ARC_GRP_BRANCH_RELATIVE, 0 }, 1, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* cmp_s	$LImm, $b_s3 */
+  ARC_CMP_S_limms3 /* 366 */, ARC_INS_CMP_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* cmp_s	$b_s3, $LImm */
+  ARC_CMP_S_rlimm /* 367 */, ARC_INS_CMP_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* cmp_s	$b_s3, $h */
+  ARC_CMP_S_rr /* 368 */, ARC_INS_CMP_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* cmp_s	$h, $b_s3 */
+  ARC_CMP_S_rs3 /* 369 */, ARC_INS_CMP_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* cmp_s	$b, $u7 */
+  ARC_CMP_S_u7 /* 370 */, ARC_INS_CMP_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* cmp	$B, $LImm */
+  ARC_CMP_rlimm /* 371 */, ARC_INS_CMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* cmp	$B, $C */
+  ARC_CMP_rr /* 372 */, ARC_INS_CMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* cmp	$B, $U6 */
+  ARC_CMP_ru6 /* 373 */, ARC_INS_CMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ld_s	$r, [$h, $u5] */
+  ARC_COMPACT_LD_S /* 374 */, ARC_INS_LD_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mov_s	$g, $h */
+  ARC_COMPACT_MOV_S_hreg /* 375 */, ARC_INS_MOV_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mov_s	$g, $h */
+  ARC_COMPACT_MOV_S_limm /* 376 */, ARC_INS_MOV_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ei_s	$u10 */
+  ARC_EI_S /* 377 */, ARC_INS_EI_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* enter_s	$u6 */
+  ARC_ENTER_S /* 378 */, ARC_INS_ENTER_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ffs.f	$B, $C */
+  ARC_FFS_f_rr /* 379 */, ARC_INS_FFS_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ffs	$B, $C */
+  ARC_FFS_rr /* 380 */, ARC_INS_FFS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* fls.f	$B, $C */
+  ARC_FLS_f_rr /* 381 */, ARC_INS_FLS_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* fls	$B, $C */
+  ARC_FLS_rr /* 382 */, ARC_INS_FLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* abs_s	$b, $c */
+  ARC_GEN_ABS_S /* 383 */, ARC_INS_ABS_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* add1_s	$b, $b, $c */
+  ARC_GEN_ADD1_S /* 384 */, ARC_INS_ADD1_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* add2_s	$b, $b, $c */
+  ARC_GEN_ADD2_S /* 385 */, ARC_INS_ADD2_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* add3_s	$b, $b, $c */
+  ARC_GEN_ADD3_S /* 386 */, ARC_INS_ADD3_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* and_s	$b, $b, $c */
+  ARC_GEN_AND_S /* 387 */, ARC_INS_AND_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* asl_s	$b, $c */
+  ARC_GEN_AS1L_S /* 388 */, ARC_INS_ASL_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* asr_s	$b, $c */
+  ARC_GEN_AS1R_S /* 389 */, ARC_INS_ASR_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* asl_s	$b, $b, $c */
+  ARC_GEN_ASL_S /* 390 */, ARC_INS_ASL_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* asr_s	$b, $b, $c */
+  ARC_GEN_ASR_S /* 391 */, ARC_INS_ASR_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* bic_s	$b, $b, $c */
+  ARC_GEN_BIC_S /* 392 */, ARC_INS_BIC_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* brk_s */
+  ARC_GEN_BRK_S /* 393 */, ARC_INS_BRK_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* extb_s	$b, $c */
+  ARC_GEN_EXTB_S /* 394 */, ARC_INS_EXTB_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* exth_s	$b, $c */
+  ARC_GEN_EXTH_S /* 395 */, ARC_INS_EXTH_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* jeq_s	[%blink] */
+  ARC_GEN_JEQ_S /* 396 */, ARC_INS_JEQ_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARC_GRP_JUMP, ARC_GRP_RET, 0 }, 1, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* jl_s	[$b] */
+  ARC_GEN_JL_S /* 397 */, ARC_INS_JL_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARC_GRP_CALL, 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* jl_s.d	[$b] */
+  ARC_GEN_JL_S_D /* 398 */, ARC_INS_JL_S_D,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARC_GRP_CALL, 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* jne_s	[%blink] */
+  ARC_GEN_JNE_S /* 399 */, ARC_INS_JNE_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARC_GRP_JUMP, ARC_GRP_RET, 0 }, 1, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* j_s	[$b] */
+  ARC_GEN_J_S /* 400 */, ARC_INS_J_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARC_GRP_JUMP, 0 }, 1, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* j_s.d	[$b] */
+  ARC_GEN_J_S_D /* 401 */, ARC_INS_J_S_D,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARC_GRP_JUMP, 0 }, 1, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* j_s.d	[%blink] */
+  ARC_GEN_J_S_D_BLINK /* 402 */, ARC_INS_J_S_D,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARC_GRP_JUMP, ARC_GRP_RET, 0 }, 1, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* lsr_s	$b, $c */
+  ARC_GEN_LS1R_S /* 403 */, ARC_INS_LSR_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* lsr_s	$b, $b, $c */
+  ARC_GEN_LSR_S /* 404 */, ARC_INS_LSR_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mpyuw_s	$b, $b, $c */
+  ARC_GEN_MPYUW_S /* 405 */, ARC_INS_MPYUW_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mpyw_s	$b, $b, $c */
+  ARC_GEN_MPYW_S /* 406 */, ARC_INS_MPYW_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mpy_s	$b, $b, $c */
+  ARC_GEN_MPY_S /* 407 */, ARC_INS_MPY_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* neg_s	$b, $c */
+  ARC_GEN_NEG_S /* 408 */, ARC_INS_NEG_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* nop_s */
+  ARC_GEN_NOP_S /* 409 */, ARC_INS_NOP_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* not_s	$b, $c */
+  ARC_GEN_NOT_S /* 410 */, ARC_INS_NOT_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* or_s	$b, $b, $c */
+  ARC_GEN_OR_S /* 411 */, ARC_INS_OR_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sexb_s	$b, $c */
+  ARC_GEN_SEXB_S /* 412 */, ARC_INS_SEXB_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sexh_s	$b, $c */
+  ARC_GEN_SEXH_S /* 413 */, ARC_INS_SEXH_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub_s	$b, $b, $c */
+  ARC_GEN_SUB_S /* 414 */, ARC_INS_SUB_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub_s.ne	$b, $b, $b */
+  ARC_GEN_SUB_S_NE /* 415 */, ARC_INS_SUB_S_NE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* swi_s */
+  ARC_GEN_SWI_S /* 416 */, ARC_INS_SWI_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* trap_s	$u6 */
+  ARC_GEN_TRAP_S /* 417 */, ARC_INS_TRAP_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* tst_s	$b, $c */
+  ARC_GEN_TST_S /* 418 */, ARC_INS_TST_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* unimp_s */
+  ARC_GEN_UNIMP_S /* 419 */, ARC_INS_UNIMP_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* xor_s	$b, $b, $c */
+  ARC_GEN_XOR_S /* 420 */, ARC_INS_XOR_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* add_s	%r0, %gp, $s */
+  ARC_GP_ADD_S /* 421 */, ARC_INS_ADD_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldb_s	%r0, [%gp, $s] */
+  ARC_GP_LDB_S /* 422 */, ARC_INS_LDB_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldh_s	%r0, [%gp, $s] */
+  ARC_GP_LDH_S /* 423 */, ARC_INS_LDH_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ld_s	%r0, [%gp, $s] */
+  ARC_GP_LD_S /* 424 */, ARC_INS_LD_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* j	[$C] */
+  ARC_J /* 425 */, ARC_INS_J,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARC_GRP_JUMP, 0 }, 1, 1, {{ 0 }}
+
+  #endif
+},
+{
+  /* jl	[$C] */
+  ARC_JL /* 426 */, ARC_INS_JL,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_SP, 0 }, { ARC_REG_BLINK, 0 }, { ARC_GRP_CALL, 0 }, 0, 1, {{ 0 }}
+
+  #endif
+},
+{
+  /* jli_s	$u10 */
+  ARC_JLI_S /* 427 */, ARC_INS_JLI_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* jl	$LImm */
+  ARC_JL_LImm /* 428 */, ARC_INS_JL,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_SP, 0 }, { ARC_REG_BLINK, 0 }, { ARC_GRP_CALL, 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* j	$LImm */
+  ARC_J_LImm /* 429 */, ARC_INS_J,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARC_GRP_JUMP, 0 }, 1, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* j_s	[%blink] */
+  ARC_J_S_BLINK /* 430 */, ARC_INS_J_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARC_GRP_JUMP, ARC_GRP_RET, 0 }, 1, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldb.ab	$A, [$B,$S9] */
+  ARC_LDB_AB_rs9 /* 431 */, ARC_INS_LDB_AB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldb.aw	$A, [$B,$S9] */
+  ARC_LDB_AW_rs9 /* 432 */, ARC_INS_LDB_AW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldb.di.ab	$A, [$B,$S9] */
+  ARC_LDB_DI_AB_rs9 /* 433 */, ARC_INS_LDB_DI_AB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldb.di.aw	$A, [$B,$S9] */
+  ARC_LDB_DI_AW_rs9 /* 434 */, ARC_INS_LDB_DI_AW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldb.di	$A, [$addr] */
+  ARC_LDB_DI_limm /* 435 */, ARC_INS_LDB_DI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldb.di	$A, [$addr] */
+  ARC_LDB_DI_rlimm /* 436 */, ARC_INS_LDB_DI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldb.di	$A, [$addr] */
+  ARC_LDB_DI_rs9 /* 437 */, ARC_INS_LDB_DI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldb_s	$c, [$b, $off] */
+  ARC_LDB_S_OFF /* 438 */, ARC_INS_LDB_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldb_s	$a, [$b, $c] */
+  ARC_LDB_S_rrr /* 439 */, ARC_INS_LDB_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldb.x.ab	$A, [$B,$S9] */
+  ARC_LDB_X_AB_rs9 /* 440 */, ARC_INS_LDB_X_AB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldb.x.aw	$A, [$B,$S9] */
+  ARC_LDB_X_AW_rs9 /* 441 */, ARC_INS_LDB_X_AW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldb.x.di.ab	$A, [$B,$S9] */
+  ARC_LDB_X_DI_AB_rs9 /* 442 */, ARC_INS_LDB_X_DI_AB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldb.x.di.aw	$A, [$B,$S9] */
+  ARC_LDB_X_DI_AW_rs9 /* 443 */, ARC_INS_LDB_X_DI_AW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldb.x.di	$A, [$addr] */
+  ARC_LDB_X_DI_limm /* 444 */, ARC_INS_LDB_X_DI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldb.x.di	$A, [$addr] */
+  ARC_LDB_X_DI_rlimm /* 445 */, ARC_INS_LDB_X_DI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldb.x.di	$A, [$addr] */
+  ARC_LDB_X_DI_rs9 /* 446 */, ARC_INS_LDB_X_DI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldb.x	$A, [$addr] */
+  ARC_LDB_X_limm /* 447 */, ARC_INS_LDB_X,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldb.x	$A, [$addr] */
+  ARC_LDB_X_rlimm /* 448 */, ARC_INS_LDB_X,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldb.x	$A, [$addr] */
+  ARC_LDB_X_rs9 /* 449 */, ARC_INS_LDB_X,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldb	$A, [$addr] */
+  ARC_LDB_limm /* 450 */, ARC_INS_LDB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldb	$A, [$addr] */
+  ARC_LDB_rlimm /* 451 */, ARC_INS_LDB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldb	$A, [$addr] */
+  ARC_LDB_rs9 /* 452 */, ARC_INS_LDB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldh.ab	$A, [$B,$S9] */
+  ARC_LDH_AB_rs9 /* 453 */, ARC_INS_LDH_AB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldh.aw	$A, [$B,$S9] */
+  ARC_LDH_AW_rs9 /* 454 */, ARC_INS_LDH_AW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldh.di.ab	$A, [$B,$S9] */
+  ARC_LDH_DI_AB_rs9 /* 455 */, ARC_INS_LDH_DI_AB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldh.di.aw	$A, [$B,$S9] */
+  ARC_LDH_DI_AW_rs9 /* 456 */, ARC_INS_LDH_DI_AW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldh.di	$A, [$addr] */
+  ARC_LDH_DI_limm /* 457 */, ARC_INS_LDH_DI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldh.di	$A, [$addr] */
+  ARC_LDH_DI_rlimm /* 458 */, ARC_INS_LDH_DI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldh.di	$A, [$addr] */
+  ARC_LDH_DI_rs9 /* 459 */, ARC_INS_LDH_DI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldh_s	$c, [$b, $off] */
+  ARC_LDH_S_OFF /* 460 */, ARC_INS_LDH_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldh_s.x	$c, [$b, $off] */
+  ARC_LDH_S_X_OFF /* 461 */, ARC_INS_LDH_S_X,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldh_s	$a, [$b, $c] */
+  ARC_LDH_S_rrr /* 462 */, ARC_INS_LDH_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldh.x.ab	$A, [$B,$S9] */
+  ARC_LDH_X_AB_rs9 /* 463 */, ARC_INS_LDH_X_AB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldh.x.aw	$A, [$B,$S9] */
+  ARC_LDH_X_AW_rs9 /* 464 */, ARC_INS_LDH_X_AW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldh.x.di.ab	$A, [$B,$S9] */
+  ARC_LDH_X_DI_AB_rs9 /* 465 */, ARC_INS_LDH_X_DI_AB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldh.x.di.aw	$A, [$B,$S9] */
+  ARC_LDH_X_DI_AW_rs9 /* 466 */, ARC_INS_LDH_X_DI_AW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldh.x.di	$A, [$addr] */
+  ARC_LDH_X_DI_limm /* 467 */, ARC_INS_LDH_X_DI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldh.x.di	$A, [$addr] */
+  ARC_LDH_X_DI_rlimm /* 468 */, ARC_INS_LDH_X_DI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldh.x.di	$A, [$addr] */
+  ARC_LDH_X_DI_rs9 /* 469 */, ARC_INS_LDH_X_DI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldh.x	$A, [$addr] */
+  ARC_LDH_X_limm /* 470 */, ARC_INS_LDH_X,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldh.x	$A, [$addr] */
+  ARC_LDH_X_rlimm /* 471 */, ARC_INS_LDH_X,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldh.x	$A, [$addr] */
+  ARC_LDH_X_rs9 /* 472 */, ARC_INS_LDH_X,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldh	$A, [$addr] */
+  ARC_LDH_limm /* 473 */, ARC_INS_LDH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldh	$A, [$addr] */
+  ARC_LDH_rlimm /* 474 */, ARC_INS_LDH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldh	$A, [$addr] */
+  ARC_LDH_rs9 /* 475 */, ARC_INS_LDH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldi_s	$b, [$u7] */
+  ARC_LDI_S_u7 /* 476 */, ARC_INS_LDI_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ld.ab	$A, [$B,$S9] */
+  ARC_LD_AB_rs9 /* 477 */, ARC_INS_LD_AB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ld.aw	$A, [$B,$S9] */
+  ARC_LD_AW_rs9 /* 478 */, ARC_INS_LD_AW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ld.di.ab	$A, [$B,$S9] */
+  ARC_LD_DI_AB_rs9 /* 479 */, ARC_INS_LD_DI_AB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ld.di.aw	$A, [$B,$S9] */
+  ARC_LD_DI_AW_rs9 /* 480 */, ARC_INS_LD_DI_AW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ld.di	$A, [$addr] */
+  ARC_LD_DI_limm /* 481 */, ARC_INS_LD_DI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ld.di	$A, [$addr] */
+  ARC_LD_DI_rlimm /* 482 */, ARC_INS_LD_DI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ld.di	$A, [$addr] */
+  ARC_LD_DI_rs9 /* 483 */, ARC_INS_LD_DI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ld_s.as	$a, [$b, $c] */
+  ARC_LD_S_AS_rrr /* 484 */, ARC_INS_LD_S_AS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ld_s	$c, [$b, $off] */
+  ARC_LD_S_OFF /* 485 */, ARC_INS_LD_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ld_s	$a, [$b, $c] */
+  ARC_LD_S_rrr /* 486 */, ARC_INS_LD_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ld_s	%r1, [%gp, $s11] */
+  ARC_LD_S_s11 /* 487 */, ARC_INS_LD_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ld	$A, [$addr] */
+  ARC_LD_limm /* 488 */, ARC_INS_LD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ld	$A, [$addr] */
+  ARC_LD_rlimm /* 489 */, ARC_INS_LD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ld	$A, [$addr] */
+  ARC_LD_rs9 /* 490 */, ARC_INS_LD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* leave_s	$u7 */
+  ARC_LEAVE_S /* 491 */, ARC_INS_LEAVE_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* lr	$B, [$C] */
+  ARC_LR_rs12 /* 492 */, ARC_INS_LR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* lr	$B, [$C] */
+  ARC_LR_ru6 /* 493 */, ARC_INS_LR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* lsr_s	$b, $b, $u5 */
+  ARC_LSR_S_ru5 /* 494 */, ARC_INS_LSR_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* lsr.${cc}.f	$A, $B, $U6 */
+  ARC_LSR_cc_f_rru6 /* 495 */, ARC_INS_LSR,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* lsr.$cc	$A, $B, $U6 */
+  ARC_LSR_cc_rru6 /* 496 */, ARC_INS_LSR,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* lsr.f	$A, $B, $LImm */
+  ARC_LSR_f_rrlimm /* 497 */, ARC_INS_LSR_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* lsr.f	$A, $B, $C */
+  ARC_LSR_f_rrr /* 498 */, ARC_INS_LSR_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* lsr.f	$B, $in, $S12 */
+  ARC_LSR_f_rrs12 /* 499 */, ARC_INS_LSR_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* lsr.f	$A, $B, $U6 */
+  ARC_LSR_f_rru6 /* 500 */, ARC_INS_LSR_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* lsr	$A, $B, $LImm */
+  ARC_LSR_rrlimm /* 501 */, ARC_INS_LSR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* lsr	$A, $B, $C */
+  ARC_LSR_rrr /* 502 */, ARC_INS_LSR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* lsr	$B, $in, $S12 */
+  ARC_LSR_rrs12 /* 503 */, ARC_INS_LSR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* lsr	$A, $B, $U6 */
+  ARC_LSR_rru6 /* 504 */, ARC_INS_LSR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* max.${cc}.f	$A, $B, $U6 */
+  ARC_MAX_cc_f_rru6 /* 505 */, ARC_INS_MAX,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* max.$cc	$A, $B, $U6 */
+  ARC_MAX_cc_rru6 /* 506 */, ARC_INS_MAX,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* max.f	$A, $B, $LImm */
+  ARC_MAX_f_rrlimm /* 507 */, ARC_INS_MAX_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* max.f	$A, $B, $C */
+  ARC_MAX_f_rrr /* 508 */, ARC_INS_MAX_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* max.f	$B, $in, $S12 */
+  ARC_MAX_f_rrs12 /* 509 */, ARC_INS_MAX_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* max.f	$A, $B, $U6 */
+  ARC_MAX_f_rru6 /* 510 */, ARC_INS_MAX_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* max	$A, $B, $LImm */
+  ARC_MAX_rrlimm /* 511 */, ARC_INS_MAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* max	$A, $B, $C */
+  ARC_MAX_rrr /* 512 */, ARC_INS_MAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* max	$B, $in, $S12 */
+  ARC_MAX_rrs12 /* 513 */, ARC_INS_MAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* max	$A, $B, $U6 */
+  ARC_MAX_rru6 /* 514 */, ARC_INS_MAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* min.${cc}.f	$A, $B, $U6 */
+  ARC_MIN_cc_f_rru6 /* 515 */, ARC_INS_MIN,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* min.$cc	$A, $B, $U6 */
+  ARC_MIN_cc_rru6 /* 516 */, ARC_INS_MIN,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* min.f	$A, $B, $LImm */
+  ARC_MIN_f_rrlimm /* 517 */, ARC_INS_MIN_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* min.f	$A, $B, $C */
+  ARC_MIN_f_rrr /* 518 */, ARC_INS_MIN_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* min.f	$B, $in, $S12 */
+  ARC_MIN_f_rrs12 /* 519 */, ARC_INS_MIN_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* min.f	$A, $B, $U6 */
+  ARC_MIN_f_rru6 /* 520 */, ARC_INS_MIN_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* min	$A, $B, $LImm */
+  ARC_MIN_rrlimm /* 521 */, ARC_INS_MIN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* min	$A, $B, $C */
+  ARC_MIN_rrr /* 522 */, ARC_INS_MIN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* min	$B, $in, $S12 */
+  ARC_MIN_rrs12 /* 523 */, ARC_INS_MIN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* min	$A, $B, $U6 */
+  ARC_MIN_rru6 /* 524 */, ARC_INS_MIN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mov_s.ne	$b_s3, $LImm */
+  ARC_MOV_S_NE_rlimm /* 525 */, ARC_INS_MOV_S_NE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mov_s.ne	$b_s3, $h */
+  ARC_MOV_S_NE_rr /* 526 */, ARC_INS_MOV_S_NE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mov_s	$h, $b_s3 */
+  ARC_MOV_S_rs3 /* 527 */, ARC_INS_MOV_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mov_s	0, $b_s3 */
+  ARC_MOV_S_s3 /* 528 */, ARC_INS_MOV_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mov_s	$b, $u8 */
+  ARC_MOV_S_u8 /* 529 */, ARC_INS_MOV_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mov.$cc	$B, $C */
+  ARC_MOV_cc /* 530 */, ARC_INS_MOV,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mov.${cc}.f	$B, $C */
+  ARC_MOV_cc_f_ru6 /* 531 */, ARC_INS_MOV,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mov.$cc	$B, $C */
+  ARC_MOV_cc_ru6 /* 532 */, ARC_INS_MOV,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mov.f	$B, $U6 */
+  ARC_MOV_f_ru6 /* 533 */, ARC_INS_MOV_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mov	$B, $LImm */
+  ARC_MOV_rlimm /* 534 */, ARC_INS_MOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mov	$B, $C */
+  ARC_MOV_rr /* 535 */, ARC_INS_MOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mov	$B, $S12 */
+  ARC_MOV_rs12 /* 536 */, ARC_INS_MOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mov	$B, $U6 */
+  ARC_MOV_ru6 /* 537 */, ARC_INS_MOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mpymu.${cc}.f	$A, $B, $U6 */
+  ARC_MPYMU_cc_f_rru6 /* 538 */, ARC_INS_MPYMU,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mpymu.$cc	$A, $B, $U6 */
+  ARC_MPYMU_cc_rru6 /* 539 */, ARC_INS_MPYMU,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mpymu.f	$A, $B, $LImm */
+  ARC_MPYMU_f_rrlimm /* 540 */, ARC_INS_MPYMU_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mpymu.f	$A, $B, $C */
+  ARC_MPYMU_f_rrr /* 541 */, ARC_INS_MPYMU_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mpymu.f	$B, $in, $S12 */
+  ARC_MPYMU_f_rrs12 /* 542 */, ARC_INS_MPYMU_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mpymu.f	$A, $B, $U6 */
+  ARC_MPYMU_f_rru6 /* 543 */, ARC_INS_MPYMU_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mpymu	$A, $B, $LImm */
+  ARC_MPYMU_rrlimm /* 544 */, ARC_INS_MPYMU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mpymu	$A, $B, $C */
+  ARC_MPYMU_rrr /* 545 */, ARC_INS_MPYMU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mpymu	$B, $in, $S12 */
+  ARC_MPYMU_rrs12 /* 546 */, ARC_INS_MPYMU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mpymu	$A, $B, $U6 */
+  ARC_MPYMU_rru6 /* 547 */, ARC_INS_MPYMU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mpym.${cc}.f	$A, $B, $U6 */
+  ARC_MPYM_cc_f_rru6 /* 548 */, ARC_INS_MPYM,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mpym.$cc	$A, $B, $U6 */
+  ARC_MPYM_cc_rru6 /* 549 */, ARC_INS_MPYM,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mpym.f	$A, $B, $LImm */
+  ARC_MPYM_f_rrlimm /* 550 */, ARC_INS_MPYM_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mpym.f	$A, $B, $C */
+  ARC_MPYM_f_rrr /* 551 */, ARC_INS_MPYM_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mpym.f	$B, $in, $S12 */
+  ARC_MPYM_f_rrs12 /* 552 */, ARC_INS_MPYM_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mpym.f	$A, $B, $U6 */
+  ARC_MPYM_f_rru6 /* 553 */, ARC_INS_MPYM_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mpym	$A, $B, $LImm */
+  ARC_MPYM_rrlimm /* 554 */, ARC_INS_MPYM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mpym	$A, $B, $C */
+  ARC_MPYM_rrr /* 555 */, ARC_INS_MPYM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mpym	$B, $in, $S12 */
+  ARC_MPYM_rrs12 /* 556 */, ARC_INS_MPYM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mpym	$A, $B, $U6 */
+  ARC_MPYM_rru6 /* 557 */, ARC_INS_MPYM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mpy.${cc}.f	$A, $B, $U6 */
+  ARC_MPY_cc_f_rru6 /* 558 */, ARC_INS_MPY,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mpy.$cc	$A, $B, $U6 */
+  ARC_MPY_cc_rru6 /* 559 */, ARC_INS_MPY,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mpy.f	$A, $B, $LImm */
+  ARC_MPY_f_rrlimm /* 560 */, ARC_INS_MPY_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mpy.f	$A, $B, $C */
+  ARC_MPY_f_rrr /* 561 */, ARC_INS_MPY_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mpy.f	$B, $in, $S12 */
+  ARC_MPY_f_rrs12 /* 562 */, ARC_INS_MPY_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mpy.f	$A, $B, $U6 */
+  ARC_MPY_f_rru6 /* 563 */, ARC_INS_MPY_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mpy	$A, $B, $LImm */
+  ARC_MPY_rrlimm /* 564 */, ARC_INS_MPY,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mpy	$A, $B, $C */
+  ARC_MPY_rrr /* 565 */, ARC_INS_MPY,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mpy	$B, $in, $S12 */
+  ARC_MPY_rrs12 /* 566 */, ARC_INS_MPY,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* mpy	$A, $B, $U6 */
+  ARC_MPY_rru6 /* 567 */, ARC_INS_MPY,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* normh.f	$B, $C */
+  ARC_NORMH_f_rr /* 568 */, ARC_INS_NORMH_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* normh	$B, $C */
+  ARC_NORMH_rr /* 569 */, ARC_INS_NORMH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* norm.f	$B, $C */
+  ARC_NORM_f_rr /* 570 */, ARC_INS_NORM_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* norm	$B, $C */
+  ARC_NORM_rr /* 571 */, ARC_INS_NORM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* or.${cc}.f	$A, $B, $U6 */
+  ARC_OR_cc_f_rru6 /* 572 */, ARC_INS_OR,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* or.$cc	$A, $B, $U6 */
+  ARC_OR_cc_rru6 /* 573 */, ARC_INS_OR,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* or.f	$A, $B, $LImm */
+  ARC_OR_f_rrlimm /* 574 */, ARC_INS_OR_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* or.f	$A, $B, $C */
+  ARC_OR_f_rrr /* 575 */, ARC_INS_OR_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* or.f	$B, $in, $S12 */
+  ARC_OR_f_rrs12 /* 576 */, ARC_INS_OR_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* or.f	$A, $B, $U6 */
+  ARC_OR_f_rru6 /* 577 */, ARC_INS_OR_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* or	$A, $B, $LImm */
+  ARC_OR_rrlimm /* 578 */, ARC_INS_OR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* or	$A, $B, $C */
+  ARC_OR_rrr /* 579 */, ARC_INS_OR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* or	$B, $in, $S12 */
+  ARC_OR_rrs12 /* 580 */, ARC_INS_OR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* or	$A, $B, $U6 */
+  ARC_OR_rru6 /* 581 */, ARC_INS_OR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ld_s	$b, [%pcl, $u10] */
+  ARC_PCL_LD /* 582 */, ARC_INS_LD_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* pop_s	%blink */
+  ARC_POP_S_BLINK /* 583 */, ARC_INS_POP_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_BLINK, ARC_REG_SP, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* pop_s	$b3 */
+  ARC_POP_S_r /* 584 */, ARC_INS_POP_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* push_s	%blink */
+  ARC_PUSH_S_BLINK /* 585 */, ARC_INS_PUSH_S,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_BLINK, 0 }, { ARC_REG_SP, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* push_s	$b3 */
+  ARC_PUSH_S_r /* 586 */, ARC_INS_PUSH_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ror.${cc}.f	$A, $B, $U6 */
+  ARC_ROR_cc_f_rru6 /* 587 */, ARC_INS_ROR,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ror.$cc	$A, $B, $U6 */
+  ARC_ROR_cc_rru6 /* 588 */, ARC_INS_ROR,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ror.f	$A, $B, $LImm */
+  ARC_ROR_f_rrlimm /* 589 */, ARC_INS_ROR_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ror.f	$A, $B, $C */
+  ARC_ROR_f_rrr /* 590 */, ARC_INS_ROR_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ror.f	$B, $in, $S12 */
+  ARC_ROR_f_rrs12 /* 591 */, ARC_INS_ROR_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ror.f	$A, $B, $U6 */
+  ARC_ROR_f_rru6 /* 592 */, ARC_INS_ROR_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ror	$A, $B, $LImm */
+  ARC_ROR_rrlimm /* 593 */, ARC_INS_ROR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ror	$A, $B, $C */
+  ARC_ROR_rrr /* 594 */, ARC_INS_ROR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ror	$B, $in, $S12 */
+  ARC_ROR_rrs12 /* 595 */, ARC_INS_ROR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ror	$A, $B, $U6 */
+  ARC_ROR_rru6 /* 596 */, ARC_INS_ROR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* rsub.${cc}.f	$A, $B, $U6 */
+  ARC_RSUB_cc_f_rru6 /* 597 */, ARC_INS_RSUB,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* rsub.$cc	$A, $B, $U6 */
+  ARC_RSUB_cc_rru6 /* 598 */, ARC_INS_RSUB,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* rsub.f	$A, $B, $LImm */
+  ARC_RSUB_f_rrlimm /* 599 */, ARC_INS_RSUB_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* rsub.f	$A, $B, $C */
+  ARC_RSUB_f_rrr /* 600 */, ARC_INS_RSUB_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* rsub.f	$B, $in, $S12 */
+  ARC_RSUB_f_rrs12 /* 601 */, ARC_INS_RSUB_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* rsub.f	$A, $B, $U6 */
+  ARC_RSUB_f_rru6 /* 602 */, ARC_INS_RSUB_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* rsub	$A, $B, $LImm */
+  ARC_RSUB_rrlimm /* 603 */, ARC_INS_RSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* rsub	$A, $B, $C */
+  ARC_RSUB_rrr /* 604 */, ARC_INS_RSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* rsub	$B, $in, $S12 */
+  ARC_RSUB_rrs12 /* 605 */, ARC_INS_RSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* rsub	$A, $B, $U6 */
+  ARC_RSUB_rru6 /* 606 */, ARC_INS_RSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sbc.${cc}.f	$A, $B, $U6 */
+  ARC_SBC_cc_f_rru6 /* 607 */, ARC_INS_SBC,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sbc.$cc	$A, $B, $U6 */
+  ARC_SBC_cc_rru6 /* 608 */, ARC_INS_SBC,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sbc.f	$A, $B, $LImm */
+  ARC_SBC_f_rrlimm /* 609 */, ARC_INS_SBC_F,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sbc.f	$A, $B, $C */
+  ARC_SBC_f_rrr /* 610 */, ARC_INS_SBC_F,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sbc.f	$B, $in, $S12 */
+  ARC_SBC_f_rrs12 /* 611 */, ARC_INS_SBC_F,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sbc.f	$A, $B, $U6 */
+  ARC_SBC_f_rru6 /* 612 */, ARC_INS_SBC_F,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sbc	$A, $B, $LImm */
+  ARC_SBC_rrlimm /* 613 */, ARC_INS_SBC,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sbc	$A, $B, $C */
+  ARC_SBC_rrr /* 614 */, ARC_INS_SBC,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sbc	$B, $in, $S12 */
+  ARC_SBC_rrs12 /* 615 */, ARC_INS_SBC,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sbc	$A, $B, $U6 */
+  ARC_SBC_rru6 /* 616 */, ARC_INS_SBC,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* seteq.${cc}.f	$A, $B, $U6 */
+  ARC_SETEQ_cc_f_rru6 /* 617 */, ARC_INS_SETEQ,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* seteq.$cc	$A, $B, $U6 */
+  ARC_SETEQ_cc_rru6 /* 618 */, ARC_INS_SETEQ,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* seteq.f	$A, $B, $LImm */
+  ARC_SETEQ_f_rrlimm /* 619 */, ARC_INS_SETEQ_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* seteq.f	$A, $B, $C */
+  ARC_SETEQ_f_rrr /* 620 */, ARC_INS_SETEQ_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* seteq.f	$B, $in, $S12 */
+  ARC_SETEQ_f_rrs12 /* 621 */, ARC_INS_SETEQ_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* seteq.f	$A, $B, $U6 */
+  ARC_SETEQ_f_rru6 /* 622 */, ARC_INS_SETEQ_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* seteq	$A, $B, $LImm */
+  ARC_SETEQ_rrlimm /* 623 */, ARC_INS_SETEQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* seteq	$A, $B, $C */
+  ARC_SETEQ_rrr /* 624 */, ARC_INS_SETEQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* seteq	$B, $in, $S12 */
+  ARC_SETEQ_rrs12 /* 625 */, ARC_INS_SETEQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* seteq	$A, $B, $U6 */
+  ARC_SETEQ_rru6 /* 626 */, ARC_INS_SETEQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sexb.f	$B, $C */
+  ARC_SEXB_f_rr /* 627 */, ARC_INS_SEXB_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sexb	$B, $C */
+  ARC_SEXB_rr /* 628 */, ARC_INS_SEXB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sexh.f	$B, $C */
+  ARC_SEXH_f_rr /* 629 */, ARC_INS_SEXH_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sexh	$B, $C */
+  ARC_SEXH_rr /* 630 */, ARC_INS_SEXH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* add_s	$b3, %sp, $u7 */
+  ARC_SP_ADD_S /* 631 */, ARC_INS_ADD_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* add_s	%sp, %sp, $u7 */
+  ARC_SP_ADD_SP_S /* 632 */, ARC_INS_ADD_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ldb_s	$b3, [%sp, $u7] */
+  ARC_SP_LDB_S /* 633 */, ARC_INS_LDB_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* ld_s	$b3, [%sp, $u7] */
+  ARC_SP_LD_S /* 634 */, ARC_INS_LD_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* stb_s	$b3, [%sp, $u7] */
+  ARC_SP_STB_S /* 635 */, ARC_INS_STB_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* st_s	$b3, [%sp, $u7] */
+  ARC_SP_ST_S /* 636 */, ARC_INS_ST_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub_s	%sp, %sp, $u7 */
+  ARC_SP_SUB_SP_S /* 637 */, ARC_INS_SUB_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* stb.ab	$C, [$B,$S9] */
+  ARC_STB_AB_rs9 /* 638 */, ARC_INS_STB_AB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* stb.aw	$C, [$B,$S9] */
+  ARC_STB_AW_rs9 /* 639 */, ARC_INS_STB_AW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* stb.di.ab	$C, [$B,$S9] */
+  ARC_STB_DI_AB_rs9 /* 640 */, ARC_INS_STB_DI_AB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* stb.di.aw	$C, [$B,$S9] */
+  ARC_STB_DI_AW_rs9 /* 641 */, ARC_INS_STB_DI_AW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* stb.di	$C, [$addr] */
+  ARC_STB_DI_limm /* 642 */, ARC_INS_STB_DI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* stb.di	$C, [$addr] */
+  ARC_STB_DI_rs9 /* 643 */, ARC_INS_STB_DI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* stb_s	$c, [$b, $off] */
+  ARC_STB_S_OFF /* 644 */, ARC_INS_STB_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* stb	$C, [$addr] */
+  ARC_STB_limm /* 645 */, ARC_INS_STB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* stb	$C, [$addr] */
+  ARC_STB_rs9 /* 646 */, ARC_INS_STB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sth.ab	$C, [$B,$S9] */
+  ARC_STH_AB_rs9 /* 647 */, ARC_INS_STH_AB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sth.aw	$C, [$B,$S9] */
+  ARC_STH_AW_rs9 /* 648 */, ARC_INS_STH_AW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sth.di.ab	$C, [$B,$S9] */
+  ARC_STH_DI_AB_rs9 /* 649 */, ARC_INS_STH_DI_AB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sth.di.aw	$C, [$B,$S9] */
+  ARC_STH_DI_AW_rs9 /* 650 */, ARC_INS_STH_DI_AW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sth.di	$C, [$addr] */
+  ARC_STH_DI_limm /* 651 */, ARC_INS_STH_DI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sth.di	$C, [$addr] */
+  ARC_STH_DI_rs9 /* 652 */, ARC_INS_STH_DI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sth_s	$c, [$b, $off] */
+  ARC_STH_S_OFF /* 653 */, ARC_INS_STH_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sth	$C, [$addr] */
+  ARC_STH_limm /* 654 */, ARC_INS_STH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sth	$C, [$addr] */
+  ARC_STH_rs9 /* 655 */, ARC_INS_STH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* st.ab	$C, [$B,$S9] */
+  ARC_ST_AB_rs9 /* 656 */, ARC_INS_ST_AB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* st.aw	$C, [$B,$S9] */
+  ARC_ST_AW_rs9 /* 657 */, ARC_INS_ST_AW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* st.di.ab	$C, [$B,$S9] */
+  ARC_ST_DI_AB_rs9 /* 658 */, ARC_INS_ST_DI_AB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* st.di.aw	$C, [$B,$S9] */
+  ARC_ST_DI_AW_rs9 /* 659 */, ARC_INS_ST_DI_AW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* st.di	$C, [$addr] */
+  ARC_ST_DI_limm /* 660 */, ARC_INS_ST_DI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* st.di	$C, [$addr] */
+  ARC_ST_DI_rs9 /* 661 */, ARC_INS_ST_DI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* st_s	$c, [$b, $off] */
+  ARC_ST_S_OFF /* 662 */, ARC_INS_ST_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* st_s	%r0, [%gp, $s11] */
+  ARC_ST_S_s11 /* 663 */, ARC_INS_ST_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* st	$C, [$addr] */
+  ARC_ST_limm /* 664 */, ARC_INS_ST,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* st	$C, [$addr] */
+  ARC_ST_rs9 /* 665 */, ARC_INS_ST,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub1.${cc}.f	$A, $B, $U6 */
+  ARC_SUB1_cc_f_rru6 /* 666 */, ARC_INS_SUB1,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub1.$cc	$A, $B, $U6 */
+  ARC_SUB1_cc_rru6 /* 667 */, ARC_INS_SUB1,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub1.f	$A, $B, $LImm */
+  ARC_SUB1_f_rrlimm /* 668 */, ARC_INS_SUB1_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub1.f	$A, $B, $C */
+  ARC_SUB1_f_rrr /* 669 */, ARC_INS_SUB1_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub1.f	$B, $in, $S12 */
+  ARC_SUB1_f_rrs12 /* 670 */, ARC_INS_SUB1_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub1.f	$A, $B, $U6 */
+  ARC_SUB1_f_rru6 /* 671 */, ARC_INS_SUB1_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub1	$A, $B, $LImm */
+  ARC_SUB1_rrlimm /* 672 */, ARC_INS_SUB1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub1	$A, $B, $C */
+  ARC_SUB1_rrr /* 673 */, ARC_INS_SUB1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub1	$B, $in, $S12 */
+  ARC_SUB1_rrs12 /* 674 */, ARC_INS_SUB1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub1	$A, $B, $U6 */
+  ARC_SUB1_rru6 /* 675 */, ARC_INS_SUB1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub2.${cc}.f	$A, $B, $U6 */
+  ARC_SUB2_cc_f_rru6 /* 676 */, ARC_INS_SUB2,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub2.$cc	$A, $B, $U6 */
+  ARC_SUB2_cc_rru6 /* 677 */, ARC_INS_SUB2,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub2.f	$A, $B, $LImm */
+  ARC_SUB2_f_rrlimm /* 678 */, ARC_INS_SUB2_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub2.f	$A, $B, $C */
+  ARC_SUB2_f_rrr /* 679 */, ARC_INS_SUB2_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub2.f	$B, $in, $S12 */
+  ARC_SUB2_f_rrs12 /* 680 */, ARC_INS_SUB2_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub2.f	$A, $B, $U6 */
+  ARC_SUB2_f_rru6 /* 681 */, ARC_INS_SUB2_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub2	$A, $B, $LImm */
+  ARC_SUB2_rrlimm /* 682 */, ARC_INS_SUB2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub2	$A, $B, $C */
+  ARC_SUB2_rrr /* 683 */, ARC_INS_SUB2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub2	$B, $in, $S12 */
+  ARC_SUB2_rrs12 /* 684 */, ARC_INS_SUB2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub2	$A, $B, $U6 */
+  ARC_SUB2_rru6 /* 685 */, ARC_INS_SUB2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub3.${cc}.f	$A, $B, $U6 */
+  ARC_SUB3_cc_f_rru6 /* 686 */, ARC_INS_SUB3,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub3.$cc	$A, $B, $U6 */
+  ARC_SUB3_cc_rru6 /* 687 */, ARC_INS_SUB3,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub3.f	$A, $B, $LImm */
+  ARC_SUB3_f_rrlimm /* 688 */, ARC_INS_SUB3_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub3.f	$A, $B, $C */
+  ARC_SUB3_f_rrr /* 689 */, ARC_INS_SUB3_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub3.f	$B, $in, $S12 */
+  ARC_SUB3_f_rrs12 /* 690 */, ARC_INS_SUB3_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub3.f	$A, $B, $U6 */
+  ARC_SUB3_f_rru6 /* 691 */, ARC_INS_SUB3_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub3	$A, $B, $LImm */
+  ARC_SUB3_rrlimm /* 692 */, ARC_INS_SUB3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub3	$A, $B, $C */
+  ARC_SUB3_rrr /* 693 */, ARC_INS_SUB3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub3	$B, $in, $S12 */
+  ARC_SUB3_rrs12 /* 694 */, ARC_INS_SUB3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub3	$A, $B, $U6 */
+  ARC_SUB3_rru6 /* 695 */, ARC_INS_SUB3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub_s	$a, $b, $c */
+  ARC_SUB_S_rrr /* 696 */, ARC_INS_SUB_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub_s	$c, $b, $u3 */
+  ARC_SUB_S_ru3 /* 697 */, ARC_INS_SUB_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub_s	$b, $b, $u5 */
+  ARC_SUB_S_ru5 /* 698 */, ARC_INS_SUB_S,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub.${cc}.f	$A, $B, $U6 */
+  ARC_SUB_cc_f_rru6 /* 699 */, ARC_INS_SUB,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub.$cc	$A, $B, $U6 */
+  ARC_SUB_cc_rru6 /* 700 */, ARC_INS_SUB,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub.f	$A, $B, $LImm */
+  ARC_SUB_f_rrlimm /* 701 */, ARC_INS_SUB_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub.f	$A, $B, $C */
+  ARC_SUB_f_rrr /* 702 */, ARC_INS_SUB_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub.f	$B, $in, $S12 */
+  ARC_SUB_f_rrs12 /* 703 */, ARC_INS_SUB_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub.f	$A, $B, $U6 */
+  ARC_SUB_f_rru6 /* 704 */, ARC_INS_SUB_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub	$A, $B, $LImm */
+  ARC_SUB_rrlimm /* 705 */, ARC_INS_SUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub	$A, $B, $C */
+  ARC_SUB_rrr /* 706 */, ARC_INS_SUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub	$B, $in, $S12 */
+  ARC_SUB_rrs12 /* 707 */, ARC_INS_SUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* sub	$A, $B, $U6 */
+  ARC_SUB_rru6 /* 708 */, ARC_INS_SUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* xor.${cc}.f	$A, $B, $U6 */
+  ARC_XOR_cc_f_rru6 /* 709 */, ARC_INS_XOR,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* xor.$cc	$A, $B, $U6 */
+  ARC_XOR_cc_rru6 /* 710 */, ARC_INS_XOR,
+  #ifndef CAPSTONE_DIET
+    { ARC_REG_STATUS32, 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* xor.f	$A, $B, $LImm */
+  ARC_XOR_f_rrlimm /* 711 */, ARC_INS_XOR_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* xor.f	$A, $B, $C */
+  ARC_XOR_f_rrr /* 712 */, ARC_INS_XOR_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* xor.f	$B, $in, $S12 */
+  ARC_XOR_f_rrs12 /* 713 */, ARC_INS_XOR_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* xor.f	$A, $B, $U6 */
+  ARC_XOR_f_rru6 /* 714 */, ARC_INS_XOR_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARC_REG_STATUS32, 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* xor	$A, $B, $LImm */
+  ARC_XOR_rrlimm /* 715 */, ARC_INS_XOR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* xor	$A, $B, $C */
+  ARC_XOR_rrr /* 716 */, ARC_INS_XOR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* xor	$B, $in, $S12 */
+  ARC_XOR_rrs12 /* 717 */, ARC_INS_XOR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
+{
+  /* xor	$A, $B, $U6 */
+  ARC_XOR_rru6 /* 718 */, ARC_INS_XOR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
+
+  #endif
+},
diff --git a/arch/ARC/ARCGenCSMappingInsnName.inc b/arch/ARC/ARCGenCSMappingInsnName.inc
new file mode 100644
index 0000000000..11297666e8
--- /dev/null
+++ b/arch/ARC/ARCGenCSMappingInsnName.inc
@@ -0,0 +1,204 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+  "invalid", // ARC_INS_INVALID
+  "h", // ARC_INS_h
+  "pbr", // ARC_INS_PBR
+  "error_fls", // ARC_INS_ERROR_FLS
+  "error_ffs", // ARC_INS_ERROR_FFS
+  "pldfi", // ARC_INS_PLDFI
+  "STB_FAR", // ARC_INS_STB_FAR
+  "STH_FAR", // ARC_INS_STH_FAR
+  "ST_FAR", // ARC_INS_ST_FAR
+  "adc", // ARC_INS_ADC
+  "adc_f", // ARC_INS_ADC_F
+  "add_s", // ARC_INS_ADD_S
+  "add", // ARC_INS_ADD
+  "add_f", // ARC_INS_ADD_F
+  "and", // ARC_INS_AND
+  "and_f", // ARC_INS_AND_F
+  "asl_s", // ARC_INS_ASL_S
+  "asl", // ARC_INS_ASL
+  "asl_f", // ARC_INS_ASL_F
+  "asr_s", // ARC_INS_ASR_S
+  "asr", // ARC_INS_ASR
+  "asr_f", // ARC_INS_ASR_F
+  "bclr_s", // ARC_INS_BCLR_S
+  "beq_s", // ARC_INS_BEQ_S
+  "bge_s", // ARC_INS_BGE_S
+  "bgt_s", // ARC_INS_BGT_S
+  "bhi_s", // ARC_INS_BHI_S
+  "bhs_s", // ARC_INS_BHS_S
+  "bl", // ARC_INS_BL
+  "ble_s", // ARC_INS_BLE_S
+  "blo_s", // ARC_INS_BLO_S
+  "bls_s", // ARC_INS_BLS_S
+  "blt_s", // ARC_INS_BLT_S
+  "bl_s", // ARC_INS_BL_S
+  "bmsk_s", // ARC_INS_BMSK_S
+  "bne_s", // ARC_INS_BNE_S
+  "b", // ARC_INS_B
+  "breq_s", // ARC_INS_BREQ_S
+  "brne_s", // ARC_INS_BRNE_S
+  "br", // ARC_INS_BR
+  "bset_s", // ARC_INS_BSET_S
+  "btst_s", // ARC_INS_BTST_S
+  "b_s", // ARC_INS_B_S
+  "cmp_s", // ARC_INS_CMP_S
+  "cmp", // ARC_INS_CMP
+  "ld_s", // ARC_INS_LD_S
+  "mov_s", // ARC_INS_MOV_S
+  "ei_s", // ARC_INS_EI_S
+  "enter_s", // ARC_INS_ENTER_S
+  "ffs_f", // ARC_INS_FFS_F
+  "ffs", // ARC_INS_FFS
+  "fls_f", // ARC_INS_FLS_F
+  "fls", // ARC_INS_FLS
+  "abs_s", // ARC_INS_ABS_S
+  "add1_s", // ARC_INS_ADD1_S
+  "add2_s", // ARC_INS_ADD2_S
+  "add3_s", // ARC_INS_ADD3_S
+  "and_s", // ARC_INS_AND_S
+  "bic_s", // ARC_INS_BIC_S
+  "brk_s", // ARC_INS_BRK_S
+  "extb_s", // ARC_INS_EXTB_S
+  "exth_s", // ARC_INS_EXTH_S
+  "jeq_s", // ARC_INS_JEQ_S
+  "jl_s", // ARC_INS_JL_S
+  "jl_s_d", // ARC_INS_JL_S_D
+  "jne_s", // ARC_INS_JNE_S
+  "j_s", // ARC_INS_J_S
+  "j_s_d", // ARC_INS_J_S_D
+  "lsr_s", // ARC_INS_LSR_S
+  "mpyuw_s", // ARC_INS_MPYUW_S
+  "mpyw_s", // ARC_INS_MPYW_S
+  "mpy_s", // ARC_INS_MPY_S
+  "neg_s", // ARC_INS_NEG_S
+  "nop_s", // ARC_INS_NOP_S
+  "not_s", // ARC_INS_NOT_S
+  "or_s", // ARC_INS_OR_S
+  "sexb_s", // ARC_INS_SEXB_S
+  "sexh_s", // ARC_INS_SEXH_S
+  "sub_s", // ARC_INS_SUB_S
+  "sub_s_ne", // ARC_INS_SUB_S_NE
+  "swi_s", // ARC_INS_SWI_S
+  "trap_s", // ARC_INS_TRAP_S
+  "tst_s", // ARC_INS_TST_S
+  "unimp_s", // ARC_INS_UNIMP_S
+  "xor_s", // ARC_INS_XOR_S
+  "ldb_s", // ARC_INS_LDB_S
+  "ldh_s", // ARC_INS_LDH_S
+  "j", // ARC_INS_J
+  "jl", // ARC_INS_JL
+  "jli_s", // ARC_INS_JLI_S
+  "ldb_ab", // ARC_INS_LDB_AB
+  "ldb_aw", // ARC_INS_LDB_AW
+  "ldb_di_ab", // ARC_INS_LDB_DI_AB
+  "ldb_di_aw", // ARC_INS_LDB_DI_AW
+  "ldb_di", // ARC_INS_LDB_DI
+  "ldb_x_ab", // ARC_INS_LDB_X_AB
+  "ldb_x_aw", // ARC_INS_LDB_X_AW
+  "ldb_x_di_ab", // ARC_INS_LDB_X_DI_AB
+  "ldb_x_di_aw", // ARC_INS_LDB_X_DI_AW
+  "ldb_x_di", // ARC_INS_LDB_X_DI
+  "ldb_x", // ARC_INS_LDB_X
+  "ldb", // ARC_INS_LDB
+  "ldh_ab", // ARC_INS_LDH_AB
+  "ldh_aw", // ARC_INS_LDH_AW
+  "ldh_di_ab", // ARC_INS_LDH_DI_AB
+  "ldh_di_aw", // ARC_INS_LDH_DI_AW
+  "ldh_di", // ARC_INS_LDH_DI
+  "ldh_s_x", // ARC_INS_LDH_S_X
+  "ldh_x_ab", // ARC_INS_LDH_X_AB
+  "ldh_x_aw", // ARC_INS_LDH_X_AW
+  "ldh_x_di_ab", // ARC_INS_LDH_X_DI_AB
+  "ldh_x_di_aw", // ARC_INS_LDH_X_DI_AW
+  "ldh_x_di", // ARC_INS_LDH_X_DI
+  "ldh_x", // ARC_INS_LDH_X
+  "ldh", // ARC_INS_LDH
+  "ldi_s", // ARC_INS_LDI_S
+  "ld_ab", // ARC_INS_LD_AB
+  "ld_aw", // ARC_INS_LD_AW
+  "ld_di_ab", // ARC_INS_LD_DI_AB
+  "ld_di_aw", // ARC_INS_LD_DI_AW
+  "ld_di", // ARC_INS_LD_DI
+  "ld_s_as", // ARC_INS_LD_S_AS
+  "ld", // ARC_INS_LD
+  "leave_s", // ARC_INS_LEAVE_S
+  "lr", // ARC_INS_LR
+  "lsr", // ARC_INS_LSR
+  "lsr_f", // ARC_INS_LSR_F
+  "max", // ARC_INS_MAX
+  "max_f", // ARC_INS_MAX_F
+  "min", // ARC_INS_MIN
+  "min_f", // ARC_INS_MIN_F
+  "mov_s_ne", // ARC_INS_MOV_S_NE
+  "mov", // ARC_INS_MOV
+  "mov_f", // ARC_INS_MOV_F
+  "mpymu", // ARC_INS_MPYMU
+  "mpymu_f", // ARC_INS_MPYMU_F
+  "mpym", // ARC_INS_MPYM
+  "mpym_f", // ARC_INS_MPYM_F
+  "mpy", // ARC_INS_MPY
+  "mpy_f", // ARC_INS_MPY_F
+  "normh_f", // ARC_INS_NORMH_F
+  "normh", // ARC_INS_NORMH
+  "norm_f", // ARC_INS_NORM_F
+  "norm", // ARC_INS_NORM
+  "or", // ARC_INS_OR
+  "or_f", // ARC_INS_OR_F
+  "pop_s", // ARC_INS_POP_S
+  "push_s", // ARC_INS_PUSH_S
+  "ror", // ARC_INS_ROR
+  "ror_f", // ARC_INS_ROR_F
+  "rsub", // ARC_INS_RSUB
+  "rsub_f", // ARC_INS_RSUB_F
+  "sbc", // ARC_INS_SBC
+  "sbc_f", // ARC_INS_SBC_F
+  "seteq", // ARC_INS_SETEQ
+  "seteq_f", // ARC_INS_SETEQ_F
+  "sexb_f", // ARC_INS_SEXB_F
+  "sexb", // ARC_INS_SEXB
+  "sexh_f", // ARC_INS_SEXH_F
+  "sexh", // ARC_INS_SEXH
+  "stb_s", // ARC_INS_STB_S
+  "st_s", // ARC_INS_ST_S
+  "stb_ab", // ARC_INS_STB_AB
+  "stb_aw", // ARC_INS_STB_AW
+  "stb_di_ab", // ARC_INS_STB_DI_AB
+  "stb_di_aw", // ARC_INS_STB_DI_AW
+  "stb_di", // ARC_INS_STB_DI
+  "stb", // ARC_INS_STB
+  "sth_ab", // ARC_INS_STH_AB
+  "sth_aw", // ARC_INS_STH_AW
+  "sth_di_ab", // ARC_INS_STH_DI_AB
+  "sth_di_aw", // ARC_INS_STH_DI_AW
+  "sth_di", // ARC_INS_STH_DI
+  "sth_s", // ARC_INS_STH_S
+  "sth", // ARC_INS_STH
+  "st_ab", // ARC_INS_ST_AB
+  "st_aw", // ARC_INS_ST_AW
+  "st_di_ab", // ARC_INS_ST_DI_AB
+  "st_di_aw", // ARC_INS_ST_DI_AW
+  "st_di", // ARC_INS_ST_DI
+  "st", // ARC_INS_ST
+  "sub1", // ARC_INS_SUB1
+  "sub1_f", // ARC_INS_SUB1_F
+  "sub2", // ARC_INS_SUB2
+  "sub2_f", // ARC_INS_SUB2_F
+  "sub3", // ARC_INS_SUB3
+  "sub3_f", // ARC_INS_SUB3_F
+  "sub", // ARC_INS_SUB
+  "sub_f", // ARC_INS_SUB_F
+  "xor", // ARC_INS_XOR
+  "xor_f", // ARC_INS_XOR_F
diff --git a/arch/ARC/ARCGenCSMappingInsnOp.inc b/arch/ARC/ARCGenCSMappingInsnOp.inc
new file mode 100644
index 0000000000..540edc765e
--- /dev/null
+++ b/arch/ARC/ARCGenCSMappingInsnOp.inc
@@ -0,0 +1,3850 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+{{{ /* ARC_PHI (0) - ARC_INS_INVALID - PHINODE */
+ 0
+}}},
+{{{ /* ARC_INLINEASM (1) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_INLINEASM_BR (2) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_CFI_INSTRUCTION (3) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_EH_LABEL (4) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_GC_LABEL (5) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_ANNOTATION_LABEL (6) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_KILL (7) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_EXTRACT_SUBREG (8) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_INSERT_SUBREG (9) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_IMPLICIT_DEF (10) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_SUBREG_TO_REG (11) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_COPY_TO_REGCLASS (12) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_DBG_VALUE (13) - ARC_INS_INVALID - DBG_VALUE */
+ 0
+}}},
+{{{ /* ARC_DBG_VALUE_LIST (14) - ARC_INS_INVALID - DBG_VALUE_LIST */
+ 0
+}}},
+{{{ /* ARC_DBG_INSTR_REF (15) - ARC_INS_INVALID - DBG_INSTR_REF */
+ 0
+}}},
+{{{ /* ARC_DBG_PHI (16) - ARC_INS_INVALID - DBG_PHI */
+ 0
+}}},
+{{{ /* ARC_DBG_LABEL (17) - ARC_INS_INVALID - DBG_LABEL */
+ 0
+}}},
+{{{ /* ARC_REG_SEQUENCE (18) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_COPY (19) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_BUNDLE (20) - ARC_INS_INVALID - BUNDLE */
+ 0
+}}},
+{{{ /* ARC_LIFETIME_START (21) - ARC_INS_INVALID - LIFETIME_START */
+ 0
+}}},
+{{{ /* ARC_LIFETIME_END (22) - ARC_INS_INVALID - LIFETIME_END */
+ 0
+}}},
+{{{ /* ARC_PSEUDO_PROBE (23) - ARC_INS_INVALID - PSEUDO_PROBE */
+ 0
+}}},
+{{{ /* ARC_ARITH_FENCE (24) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_STACKMAP (25) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_FENTRY_CALL (26) - ARC_INS_INVALID - # FEntry call */
+ 0
+}}},
+{{{ /* ARC_PATCHPOINT (27) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_LOAD_STACK_GUARD (28) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_PREALLOCATED_SETUP (29) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_PREALLOCATED_ARG (30) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_STATEPOINT (31) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_LOCAL_ESCAPE (32) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_FAULTING_OP (33) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_PATCHABLE_OP (34) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_PATCHABLE_FUNCTION_ENTER (35) - ARC_INS_INVALID - # XRay Function Enter. */
+ 0
+}}},
+{{{ /* ARC_PATCHABLE_RET (36) - ARC_INS_INVALID - # XRay Function Patchable RET. */
+ 0
+}}},
+{{{ /* ARC_PATCHABLE_FUNCTION_EXIT (37) - ARC_INS_INVALID - # XRay Function Exit. */
+ 0
+}}},
+{{{ /* ARC_PATCHABLE_TAIL_CALL (38) - ARC_INS_INVALID - # XRay Tail Call Exit. */
+ 0
+}}},
+{{{ /* ARC_PATCHABLE_EVENT_CALL (39) - ARC_INS_INVALID - # XRay Custom Event Log. */
+ 0
+}}},
+{{{ /* ARC_PATCHABLE_TYPED_EVENT_CALL (40) - ARC_INS_INVALID - # XRay Typed Event Log. */
+ 0
+}}},
+{{{ /* ARC_ICALL_BRANCH_FUNNEL (41) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_MEMBARRIER (42) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_JUMP_TABLE_DEBUG_INFO (43) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_ASSERT_SEXT (44) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_ASSERT_ZEXT (45) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_ASSERT_ALIGN (46) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_ADD (47) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_SUB (48) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_MUL (49) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_SDIV (50) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_UDIV (51) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_SREM (52) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_UREM (53) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_SDIVREM (54) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_UDIVREM (55) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_AND (56) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_OR (57) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_XOR (58) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_IMPLICIT_DEF (59) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_PHI (60) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FRAME_INDEX (61) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_GLOBAL_VALUE (62) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_CONSTANT_POOL (63) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_EXTRACT (64) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_UNMERGE_VALUES (65) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_INSERT (66) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_MERGE_VALUES (67) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_BUILD_VECTOR (68) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_BUILD_VECTOR_TRUNC (69) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_CONCAT_VECTORS (70) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_PTRTOINT (71) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_INTTOPTR (72) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_BITCAST (73) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FREEZE (74) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_CONSTANT_FOLD_BARRIER (75) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_INTRINSIC_FPTRUNC_ROUND (76) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_INTRINSIC_TRUNC (77) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_INTRINSIC_ROUND (78) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_INTRINSIC_LRINT (79) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_INTRINSIC_ROUNDEVEN (80) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_READCYCLECOUNTER (81) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_LOAD (82) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_SEXTLOAD (83) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_ZEXTLOAD (84) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_INDEXED_LOAD (85) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_INDEXED_SEXTLOAD (86) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_INDEXED_ZEXTLOAD (87) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_STORE (88) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_INDEXED_STORE (89) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_ATOMIC_CMPXCHG_WITH_SUCCESS (90) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_ATOMIC_CMPXCHG (91) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_ATOMICRMW_XCHG (92) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_ATOMICRMW_ADD (93) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_ATOMICRMW_SUB (94) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_ATOMICRMW_AND (95) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_ATOMICRMW_NAND (96) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_ATOMICRMW_OR (97) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_ATOMICRMW_XOR (98) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_ATOMICRMW_MAX (99) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_ATOMICRMW_MIN (100) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_ATOMICRMW_UMAX (101) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_ATOMICRMW_UMIN (102) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_ATOMICRMW_FADD (103) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_ATOMICRMW_FSUB (104) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_ATOMICRMW_FMAX (105) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_ATOMICRMW_FMIN (106) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_ATOMICRMW_UINC_WRAP (107) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_ATOMICRMW_UDEC_WRAP (108) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FENCE (109) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_PREFETCH (110) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_BRCOND (111) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_BRINDIRECT (112) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_INVOKE_REGION_START (113) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_INTRINSIC (114) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_INTRINSIC_W_SIDE_EFFECTS (115) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_INTRINSIC_CONVERGENT (116) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS (117) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_ANYEXT (118) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_TRUNC (119) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_CONSTANT (120) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FCONSTANT (121) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_VASTART (122) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_VAARG (123) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_SEXT (124) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_SEXT_INREG (125) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_ZEXT (126) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_SHL (127) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_LSHR (128) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_ASHR (129) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FSHL (130) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FSHR (131) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_ROTR (132) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_ROTL (133) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_ICMP (134) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FCMP (135) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_SELECT (136) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_UADDO (137) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_UADDE (138) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_USUBO (139) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_USUBE (140) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_SADDO (141) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_SADDE (142) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_SSUBO (143) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_SSUBE (144) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_UMULO (145) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_SMULO (146) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_UMULH (147) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_SMULH (148) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_UADDSAT (149) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_SADDSAT (150) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_USUBSAT (151) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_SSUBSAT (152) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_USHLSAT (153) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_SSHLSAT (154) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_SMULFIX (155) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_UMULFIX (156) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_SMULFIXSAT (157) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_UMULFIXSAT (158) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_SDIVFIX (159) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_UDIVFIX (160) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_SDIVFIXSAT (161) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_UDIVFIXSAT (162) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FADD (163) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FSUB (164) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FMUL (165) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FMA (166) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FMAD (167) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FDIV (168) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FREM (169) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FPOW (170) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FPOWI (171) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FEXP (172) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FEXP2 (173) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FEXP10 (174) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FLOG (175) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FLOG2 (176) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FLOG10 (177) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FLDEXP (178) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FFREXP (179) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FNEG (180) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FPEXT (181) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FPTRUNC (182) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FPTOSI (183) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FPTOUI (184) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_SITOFP (185) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_UITOFP (186) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FABS (187) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FCOPYSIGN (188) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_IS_FPCLASS (189) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FCANONICALIZE (190) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FMINNUM (191) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FMAXNUM (192) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FMINNUM_IEEE (193) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FMAXNUM_IEEE (194) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FMINIMUM (195) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FMAXIMUM (196) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_GET_FPENV (197) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_SET_FPENV (198) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_RESET_FPENV (199) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_GET_FPMODE (200) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_SET_FPMODE (201) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_RESET_FPMODE (202) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_PTR_ADD (203) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_PTRMASK (204) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_SMIN (205) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_SMAX (206) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_UMIN (207) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_UMAX (208) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_ABS (209) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_LROUND (210) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_LLROUND (211) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_BR (212) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_BRJT (213) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_INSERT_VECTOR_ELT (214) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_EXTRACT_VECTOR_ELT (215) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_SHUFFLE_VECTOR (216) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_CTTZ (217) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_CTTZ_ZERO_UNDEF (218) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_CTLZ (219) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_CTLZ_ZERO_UNDEF (220) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_CTPOP (221) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_BSWAP (222) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_BITREVERSE (223) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FCEIL (224) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FCOS (225) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FSIN (226) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FSQRT (227) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FFLOOR (228) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FRINT (229) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_FNEARBYINT (230) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_ADDRSPACE_CAST (231) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_BLOCK_ADDR (232) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_JUMP_TABLE (233) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_DYN_STACKALLOC (234) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_STACKSAVE (235) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_STACKRESTORE (236) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_STRICT_FADD (237) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_STRICT_FSUB (238) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_STRICT_FMUL (239) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_STRICT_FDIV (240) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_STRICT_FREM (241) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_STRICT_FMA (242) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_STRICT_FSQRT (243) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_STRICT_FLDEXP (244) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_READ_REGISTER (245) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_WRITE_REGISTER (246) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_MEMCPY (247) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_MEMCPY_INLINE (248) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_MEMMOVE (249) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_MEMSET (250) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_BZERO (251) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_VECREDUCE_SEQ_FADD (252) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_VECREDUCE_SEQ_FMUL (253) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_VECREDUCE_FADD (254) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_VECREDUCE_FMUL (255) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_VECREDUCE_FMAX (256) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_VECREDUCE_FMIN (257) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_VECREDUCE_FMAXIMUM (258) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_VECREDUCE_FMINIMUM (259) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_VECREDUCE_ADD (260) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_VECREDUCE_MUL (261) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_VECREDUCE_AND (262) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_VECREDUCE_OR (263) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_VECREDUCE_XOR (264) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_VECREDUCE_SMAX (265) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_VECREDUCE_SMIN (266) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_VECREDUCE_UMAX (267) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_VECREDUCE_UMIN (268) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_SBFX (269) - ARC_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARC_G_UBFX (270) - ARC_INS_INVALID -  */
+ 0
+}}},
+{ /* ARC_ADJCALLSTACKDOWN (271) - ARC_INS_h - # ADJCALLSTACKDOWN $amt, $amt2 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* amt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* amt2 */
+  { 0 }
+}},
+{ /* ARC_ADJCALLSTACKUP (272) - ARC_INS_h - # ADJCALLSTACKUP $amt1 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* amt1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* amt2 */
+  { 0 }
+}},
+{ /* ARC_BRcc_rr_p (273) - ARC_INS_PBR - pbr$cc	$B, $C, $T */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* T */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { 0 }
+}},
+{ /* ARC_BRcc_ru6_p (274) - ARC_INS_PBR - pbr$cc	$B, $C, $T */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* T */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { 0 }
+}},
+{ /* ARC_CTLZ (275) - ARC_INS_ERROR_FLS - error.fls $A, $B */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_CTTZ (276) - ARC_INS_ERROR_FFS - error.ffs $A, $B */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_GETFI (277) - ARC_INS_PLDFI - pldfi $dst, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARC_STB_FAR (278) - ARC_INS_STB_FAR - STB_FAR $dst, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR32 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARC_STH_FAR (279) - ARC_INS_STH_FAR - STH_FAR $dst, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR32 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARC_ST_FAR (280) - ARC_INS_ST_FAR - ST_FAR $dst, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR32 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARC_ADC_cc_f_rru6 (281) - ARC_INS_ADC - adc.${cc}.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_ADC_cc_rru6 (282) - ARC_INS_ADC - adc.$cc	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_ADC_f_rrlimm (283) - ARC_INS_ADC_F - adc.f	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_ADC_f_rrr (284) - ARC_INS_ADC_F - adc.f	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_ADC_f_rrs12 (285) - ARC_INS_ADC_F - adc.f	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_ADC_f_rru6 (286) - ARC_INS_ADC_F - adc.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_ADC_rrlimm (287) - ARC_INS_ADC - adc	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_ADC_rrr (288) - ARC_INS_ADC - adc	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_ADC_rrs12 (289) - ARC_INS_ADC - adc	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_ADC_rru6 (290) - ARC_INS_ADC - adc	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_ADD_S_limms3 (291) - ARC_INS_ADD_S - add_s	0, $LImm, $b_s3 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b_s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_ADD_S_rlimm (292) - ARC_INS_ADD_S - add_s	$b_s3, $b_s3, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b_s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_ADD_S_rr (293) - ARC_INS_ADD_S - add_s	$b_s3, $b_s3, $h */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b_s3 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* h */
+  { 0 }
+}},
+{ /* ARC_ADD_S_rrr (294) - ARC_INS_ADD_S - add_s	$a, $b, $c */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* a */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { 0 }
+}},
+{ /* ARC_ADD_S_rru6 (295) - ARC_INS_ADD_S - add_s	$r, $b, $u6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u6 */
+  { 0 }
+}},
+{ /* ARC_ADD_S_rs3 (296) - ARC_INS_ADD_S - add_s	$h, $h, $b_s3 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* h */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b_s3 */
+  { 0 }
+}},
+{ /* ARC_ADD_S_ru3 (297) - ARC_INS_ADD_S - add_s	$c, $b, $u3 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u3 */
+  { 0 }
+}},
+{ /* ARC_ADD_S_u7 (298) - ARC_INS_ADD_S - add_s	$b, $b, $u7 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u7 */
+  { 0 }
+}},
+{ /* ARC_ADD_cc_f_rru6 (299) - ARC_INS_ADD - add.${cc}.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_ADD_cc_rru6 (300) - ARC_INS_ADD - add.$cc	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_ADD_f_rrlimm (301) - ARC_INS_ADD_F - add.f	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_ADD_f_rrr (302) - ARC_INS_ADD_F - add.f	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_ADD_f_rrs12 (303) - ARC_INS_ADD_F - add.f	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_ADD_f_rru6 (304) - ARC_INS_ADD_F - add.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_ADD_rrlimm (305) - ARC_INS_ADD - add	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_ADD_rrr (306) - ARC_INS_ADD - add	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_ADD_rrs12 (307) - ARC_INS_ADD - add	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_ADD_rru6 (308) - ARC_INS_ADD - add	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_AND_cc_f_rru6 (309) - ARC_INS_AND - and.${cc}.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_AND_cc_rru6 (310) - ARC_INS_AND - and.$cc	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_AND_f_rrlimm (311) - ARC_INS_AND_F - and.f	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_AND_f_rrr (312) - ARC_INS_AND_F - and.f	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_AND_f_rrs12 (313) - ARC_INS_AND_F - and.f	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_AND_f_rru6 (314) - ARC_INS_AND_F - and.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_AND_rrlimm (315) - ARC_INS_AND - and	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_AND_rrr (316) - ARC_INS_AND - and	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_AND_rrs12 (317) - ARC_INS_AND - and	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_AND_rru6 (318) - ARC_INS_AND - and	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_ASL_S_ru3 (319) - ARC_INS_ASL_S - asl_s	$c, $b, $u3 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u3 */
+  { 0 }
+}},
+{ /* ARC_ASL_S_ru5 (320) - ARC_INS_ASL_S - asl_s	$b, $b, $u5 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u5 */
+  { 0 }
+}},
+{ /* ARC_ASL_cc_f_rru6 (321) - ARC_INS_ASL - asl.${cc}.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_ASL_cc_rru6 (322) - ARC_INS_ASL - asl.$cc	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_ASL_f_rrlimm (323) - ARC_INS_ASL_F - asl.f	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_ASL_f_rrr (324) - ARC_INS_ASL_F - asl.f	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_ASL_f_rrs12 (325) - ARC_INS_ASL_F - asl.f	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_ASL_f_rru6 (326) - ARC_INS_ASL_F - asl.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_ASL_rrlimm (327) - ARC_INS_ASL - asl	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_ASL_rrr (328) - ARC_INS_ASL - asl	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_ASL_rrs12 (329) - ARC_INS_ASL - asl	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_ASL_rru6 (330) - ARC_INS_ASL - asl	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_ASR_S_ru3 (331) - ARC_INS_ASR_S - asr_s	$c, $b, $u3 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u3 */
+  { 0 }
+}},
+{ /* ARC_ASR_S_ru5 (332) - ARC_INS_ASR_S - asr_s	$b, $b, $u5 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u5 */
+  { 0 }
+}},
+{ /* ARC_ASR_cc_f_rru6 (333) - ARC_INS_ASR - asr.${cc}.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_ASR_cc_rru6 (334) - ARC_INS_ASR - asr.$cc	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_ASR_f_rrlimm (335) - ARC_INS_ASR_F - asr.f	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_ASR_f_rrr (336) - ARC_INS_ASR_F - asr.f	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_ASR_f_rrs12 (337) - ARC_INS_ASR_F - asr.f	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_ASR_f_rru6 (338) - ARC_INS_ASR_F - asr.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_ASR_rrlimm (339) - ARC_INS_ASR - asr	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_ASR_rrr (340) - ARC_INS_ASR - asr	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_ASR_rrs12 (341) - ARC_INS_ASR - asr	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_ASR_rru6 (342) - ARC_INS_ASR - asr	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_BCLR_S_ru5 (343) - ARC_INS_BCLR_S - bclr_s	$b, $b, $u5 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u5 */
+  { 0 }
+}},
+{ /* ARC_BEQ_S (344) - ARC_INS_BEQ_S - beq_s	$s */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* s */
+  { 0 }
+}},
+{ /* ARC_BGE_S (345) - ARC_INS_BGE_S - bge_s	$s */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* s */
+  { 0 }
+}},
+{ /* ARC_BGT_S (346) - ARC_INS_BGT_S - bgt_s	$s */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* s */
+  { 0 }
+}},
+{ /* ARC_BHI_S (347) - ARC_INS_BHI_S - bhi_s	$s */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* s */
+  { 0 }
+}},
+{ /* ARC_BHS_S (348) - ARC_INS_BHS_S - bhs_s	$s */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* s */
+  { 0 }
+}},
+{ /* ARC_BL (349) - ARC_INS_BL - bl	$S25 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S25 */
+  { 0 }
+}},
+{ /* ARC_BLE_S (350) - ARC_INS_BLE_S - ble_s	$s */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* s */
+  { 0 }
+}},
+{ /* ARC_BLO_S (351) - ARC_INS_BLO_S - blo_s	$s */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* s */
+  { 0 }
+}},
+{ /* ARC_BLS_S (352) - ARC_INS_BLS_S - bls_s	$s */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* s */
+  { 0 }
+}},
+{ /* ARC_BLT_S (353) - ARC_INS_BLT_S - blt_s	$s */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* s */
+  { 0 }
+}},
+{ /* ARC_BL_S (354) - ARC_INS_BL_S - bl_s	$s13 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* s13 */
+  { 0 }
+}},
+{ /* ARC_BMSK_S_ru5 (355) - ARC_INS_BMSK_S - bmsk_s	$b, $b, $u5 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u5 */
+  { 0 }
+}},
+{ /* ARC_BNE_S (356) - ARC_INS_BNE_S - bne_s	$s */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* s */
+  { 0 }
+}},
+{ /* ARC_BR (357) - ARC_INS_B - b	$S25 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* S25 */
+  { 0 }
+}},
+{ /* ARC_BREQ_S (358) - ARC_INS_BREQ_S - breq_s	$b, 0, $s8 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* s8 */
+  { 0 }
+}},
+{ /* ARC_BRNE_S (359) - ARC_INS_BRNE_S - brne_s	$b, 0, $s8 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* s8 */
+  { 0 }
+}},
+{ /* ARC_BRcc_rr (360) - ARC_INS_BR - br$cc	$B, $C, $S9 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* S9 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { 0 }
+}},
+{ /* ARC_BRcc_ru6 (361) - ARC_INS_BR - br$cc	$B, $C, $S9 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* S9 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { 0 }
+}},
+{ /* ARC_BSET_S_ru5 (362) - ARC_INS_BSET_S - bset_s	$b, $b, $u5 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u5 */
+  { 0 }
+}},
+{ /* ARC_BTST_S_ru5 (363) - ARC_INS_BTST_S - btst_s	$b, $u5 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u5 */
+  { 0 }
+}},
+{ /* ARC_B_S (364) - ARC_INS_B_S - b_s	$s */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* s */
+  { 0 }
+}},
+{ /* ARC_Bcc (365) - ARC_INS_B - b$cc	$S21 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* S21 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { 0 }
+}},
+{ /* ARC_CMP_S_limms3 (366) - ARC_INS_CMP_S - cmp_s	$LImm, $b_s3 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b_s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_CMP_S_rlimm (367) - ARC_INS_CMP_S - cmp_s	$b_s3, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b_s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_CMP_S_rr (368) - ARC_INS_CMP_S - cmp_s	$b_s3, $h */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b_s3 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* h */
+  { 0 }
+}},
+{ /* ARC_CMP_S_rs3 (369) - ARC_INS_CMP_S - cmp_s	$h, $b_s3 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* h */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b_s3 */
+  { 0 }
+}},
+{ /* ARC_CMP_S_u7 (370) - ARC_INS_CMP_S - cmp_s	$b, $u7 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u7 */
+  { 0 }
+}},
+{ /* ARC_CMP_rlimm (371) - ARC_INS_CMP - cmp	$B, $LImm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_CMP_rr (372) - ARC_INS_CMP - cmp	$B, $C */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_CMP_ru6 (373) - ARC_INS_CMP - cmp	$B, $U6 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_COMPACT_LD_S (374) - ARC_INS_LD_S - ld_s	$r, [$h, $u5] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* h */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u5 */
+  { 0 }
+}},
+{ /* ARC_COMPACT_MOV_S_hreg (375) - ARC_INS_MOV_S - mov_s	$g, $h */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* g */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* h */
+  { 0 }
+}},
+{ /* ARC_COMPACT_MOV_S_limm (376) - ARC_INS_MOV_S - mov_s	$g, $h */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* g */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* h */
+  { 0 }
+}},
+{ /* ARC_EI_S (377) - ARC_INS_EI_S - ei_s	$u10 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u10 */
+  { 0 }
+}},
+{ /* ARC_ENTER_S (378) - ARC_INS_ENTER_S - enter_s	$u6 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u6 */
+  { 0 }
+}},
+{ /* ARC_FFS_f_rr (379) - ARC_INS_FFS_F - ffs.f	$B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_FFS_rr (380) - ARC_INS_FFS - ffs	$B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_FLS_f_rr (381) - ARC_INS_FLS_F - fls.f	$B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_FLS_rr (382) - ARC_INS_FLS - fls	$B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_GEN_ABS_S (383) - ARC_INS_ABS_S - abs_s	$b, $c */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { 0 }
+}},
+{ /* ARC_GEN_ADD1_S (384) - ARC_INS_ADD1_S - add1_s	$b, $b, $c */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { 0 }
+}},
+{ /* ARC_GEN_ADD2_S (385) - ARC_INS_ADD2_S - add2_s	$b, $b, $c */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { 0 }
+}},
+{ /* ARC_GEN_ADD3_S (386) - ARC_INS_ADD3_S - add3_s	$b, $b, $c */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { 0 }
+}},
+{ /* ARC_GEN_AND_S (387) - ARC_INS_AND_S - and_s	$b, $b, $c */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { 0 }
+}},
+{ /* ARC_GEN_AS1L_S (388) - ARC_INS_ASL_S - asl_s	$b, $c */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { 0 }
+}},
+{ /* ARC_GEN_AS1R_S (389) - ARC_INS_ASR_S - asr_s	$b, $c */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { 0 }
+}},
+{ /* ARC_GEN_ASL_S (390) - ARC_INS_ASL_S - asl_s	$b, $b, $c */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { 0 }
+}},
+{ /* ARC_GEN_ASR_S (391) - ARC_INS_ASR_S - asr_s	$b, $b, $c */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { 0 }
+}},
+{ /* ARC_GEN_BIC_S (392) - ARC_INS_BIC_S - bic_s	$b, $b, $c */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { 0 }
+}},
+{ /* ARC_GEN_BRK_S (393) - ARC_INS_BRK_S - brk_s */
+{
+  { 0 }
+}},
+{ /* ARC_GEN_EXTB_S (394) - ARC_INS_EXTB_S - extb_s	$b, $c */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { 0 }
+}},
+{ /* ARC_GEN_EXTH_S (395) - ARC_INS_EXTH_S - exth_s	$b, $c */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { 0 }
+}},
+{ /* ARC_GEN_JEQ_S (396) - ARC_INS_JEQ_S - jeq_s	[%blink] */
+{
+  { 0 }
+}},
+{ /* ARC_GEN_JL_S (397) - ARC_INS_JL_S - jl_s	[$b] */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { 0 }
+}},
+{ /* ARC_GEN_JL_S_D (398) - ARC_INS_JL_S_D - jl_s.d	[$b] */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { 0 }
+}},
+{ /* ARC_GEN_JNE_S (399) - ARC_INS_JNE_S - jne_s	[%blink] */
+{
+  { 0 }
+}},
+{ /* ARC_GEN_J_S (400) - ARC_INS_J_S - j_s	[$b] */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { 0 }
+}},
+{ /* ARC_GEN_J_S_D (401) - ARC_INS_J_S_D - j_s.d	[$b] */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { 0 }
+}},
+{ /* ARC_GEN_J_S_D_BLINK (402) - ARC_INS_J_S_D - j_s.d	[%blink] */
+{
+  { 0 }
+}},
+{ /* ARC_GEN_LS1R_S (403) - ARC_INS_LSR_S - lsr_s	$b, $c */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { 0 }
+}},
+{ /* ARC_GEN_LSR_S (404) - ARC_INS_LSR_S - lsr_s	$b, $b, $c */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { 0 }
+}},
+{ /* ARC_GEN_MPYUW_S (405) - ARC_INS_MPYUW_S - mpyuw_s	$b, $b, $c */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { 0 }
+}},
+{ /* ARC_GEN_MPYW_S (406) - ARC_INS_MPYW_S - mpyw_s	$b, $b, $c */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { 0 }
+}},
+{ /* ARC_GEN_MPY_S (407) - ARC_INS_MPY_S - mpy_s	$b, $b, $c */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { 0 }
+}},
+{ /* ARC_GEN_NEG_S (408) - ARC_INS_NEG_S - neg_s	$b, $c */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { 0 }
+}},
+{ /* ARC_GEN_NOP_S (409) - ARC_INS_NOP_S - nop_s */
+{
+  { 0 }
+}},
+{ /* ARC_GEN_NOT_S (410) - ARC_INS_NOT_S - not_s	$b, $c */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { 0 }
+}},
+{ /* ARC_GEN_OR_S (411) - ARC_INS_OR_S - or_s	$b, $b, $c */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { 0 }
+}},
+{ /* ARC_GEN_SEXB_S (412) - ARC_INS_SEXB_S - sexb_s	$b, $c */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { 0 }
+}},
+{ /* ARC_GEN_SEXH_S (413) - ARC_INS_SEXH_S - sexh_s	$b, $c */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { 0 }
+}},
+{ /* ARC_GEN_SUB_S (414) - ARC_INS_SUB_S - sub_s	$b, $b, $c */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { 0 }
+}},
+{ /* ARC_GEN_SUB_S_NE (415) - ARC_INS_SUB_S_NE - sub_s.ne	$b, $b, $b */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { 0 }
+}},
+{ /* ARC_GEN_SWI_S (416) - ARC_INS_SWI_S - swi_s */
+{
+  { 0 }
+}},
+{ /* ARC_GEN_TRAP_S (417) - ARC_INS_TRAP_S - trap_s	$u6 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u6 */
+  { 0 }
+}},
+{ /* ARC_GEN_TST_S (418) - ARC_INS_TST_S - tst_s	$b, $c */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { 0 }
+}},
+{ /* ARC_GEN_UNIMP_S (419) - ARC_INS_UNIMP_S - unimp_s */
+{
+  { 0 }
+}},
+{ /* ARC_GEN_XOR_S (420) - ARC_INS_XOR_S - xor_s	$b, $b, $c */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { 0 }
+}},
+{ /* ARC_GP_ADD_S (421) - ARC_INS_ADD_S - add_s	%r0, %gp, $s */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */
+  { 0 }
+}},
+{ /* ARC_GP_LDB_S (422) - ARC_INS_LDB_S - ldb_s	%r0, [%gp, $s] */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */
+  { 0 }
+}},
+{ /* ARC_GP_LDH_S (423) - ARC_INS_LDH_S - ldh_s	%r0, [%gp, $s] */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */
+  { 0 }
+}},
+{ /* ARC_GP_LD_S (424) - ARC_INS_LD_S - ld_s	%r0, [%gp, $s] */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */
+  { 0 }
+}},
+{ /* ARC_J (425) - ARC_INS_J - j	[$C] */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_JL (426) - ARC_INS_JL - jl	[$C] */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_JLI_S (427) - ARC_INS_JLI_S - jli_s	$u10 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u10 */
+  { 0 }
+}},
+{ /* ARC_JL_LImm (428) - ARC_INS_JL - jl	$LImm */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_J_LImm (429) - ARC_INS_J - j	$LImm */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_J_S_BLINK (430) - ARC_INS_J_S - j_s	[%blink] */
+{
+  { 0 }
+}},
+{ /* ARC_LDB_AB_rs9 (431) - ARC_INS_LDB_AB - ldb.ab	$A, [$B,$S9] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addrout */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S9 */
+  { 0 }
+}},
+{ /* ARC_LDB_AW_rs9 (432) - ARC_INS_LDB_AW - ldb.aw	$A, [$B,$S9] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addrout */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S9 */
+  { 0 }
+}},
+{ /* ARC_LDB_DI_AB_rs9 (433) - ARC_INS_LDB_DI_AB - ldb.di.ab	$A, [$B,$S9] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addrout */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S9 */
+  { 0 }
+}},
+{ /* ARC_LDB_DI_AW_rs9 (434) - ARC_INS_LDB_DI_AW - ldb.di.aw	$A, [$B,$S9] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addrout */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S9 */
+  { 0 }
+}},
+{ /* ARC_LDB_DI_limm (435) - ARC_INS_LDB_DI - ldb.di	$A, [$addr] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARC_LDB_DI_rlimm (436) - ARC_INS_LDB_DI - ldb.di	$A, [$addr] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR32 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARC_LDB_DI_rs9 (437) - ARC_INS_LDB_DI - ldb.di	$A, [$addr] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR32 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - anonymous_7198 */
+  { 0 }
+}},
+{ /* ARC_LDB_S_OFF (438) - ARC_INS_LDB_S - ldb_s	$c, [$b, $off] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off */
+  { 0 }
+}},
+{ /* ARC_LDB_S_rrr (439) - ARC_INS_LDB_S - ldb_s	$a, [$b, $c] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* a */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { 0 }
+}},
+{ /* ARC_LDB_X_AB_rs9 (440) - ARC_INS_LDB_X_AB - ldb.x.ab	$A, [$B,$S9] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addrout */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S9 */
+  { 0 }
+}},
+{ /* ARC_LDB_X_AW_rs9 (441) - ARC_INS_LDB_X_AW - ldb.x.aw	$A, [$B,$S9] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addrout */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S9 */
+  { 0 }
+}},
+{ /* ARC_LDB_X_DI_AB_rs9 (442) - ARC_INS_LDB_X_DI_AB - ldb.x.di.ab	$A, [$B,$S9] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addrout */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S9 */
+  { 0 }
+}},
+{ /* ARC_LDB_X_DI_AW_rs9 (443) - ARC_INS_LDB_X_DI_AW - ldb.x.di.aw	$A, [$B,$S9] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addrout */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S9 */
+  { 0 }
+}},
+{ /* ARC_LDB_X_DI_limm (444) - ARC_INS_LDB_X_DI - ldb.x.di	$A, [$addr] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARC_LDB_X_DI_rlimm (445) - ARC_INS_LDB_X_DI - ldb.x.di	$A, [$addr] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR32 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARC_LDB_X_DI_rs9 (446) - ARC_INS_LDB_X_DI - ldb.x.di	$A, [$addr] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR32 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - anonymous_7198 */
+  { 0 }
+}},
+{ /* ARC_LDB_X_limm (447) - ARC_INS_LDB_X - ldb.x	$A, [$addr] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARC_LDB_X_rlimm (448) - ARC_INS_LDB_X - ldb.x	$A, [$addr] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR32 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARC_LDB_X_rs9 (449) - ARC_INS_LDB_X - ldb.x	$A, [$addr] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR32 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - anonymous_7198 */
+  { 0 }
+}},
+{ /* ARC_LDB_limm (450) - ARC_INS_LDB - ldb	$A, [$addr] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARC_LDB_rlimm (451) - ARC_INS_LDB - ldb	$A, [$addr] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR32 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARC_LDB_rs9 (452) - ARC_INS_LDB - ldb	$A, [$addr] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR32 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - anonymous_7198 */
+  { 0 }
+}},
+{ /* ARC_LDH_AB_rs9 (453) - ARC_INS_LDH_AB - ldh.ab	$A, [$B,$S9] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addrout */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S9 */
+  { 0 }
+}},
+{ /* ARC_LDH_AW_rs9 (454) - ARC_INS_LDH_AW - ldh.aw	$A, [$B,$S9] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addrout */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S9 */
+  { 0 }
+}},
+{ /* ARC_LDH_DI_AB_rs9 (455) - ARC_INS_LDH_DI_AB - ldh.di.ab	$A, [$B,$S9] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addrout */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S9 */
+  { 0 }
+}},
+{ /* ARC_LDH_DI_AW_rs9 (456) - ARC_INS_LDH_DI_AW - ldh.di.aw	$A, [$B,$S9] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addrout */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S9 */
+  { 0 }
+}},
+{ /* ARC_LDH_DI_limm (457) - ARC_INS_LDH_DI - ldh.di	$A, [$addr] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARC_LDH_DI_rlimm (458) - ARC_INS_LDH_DI - ldh.di	$A, [$addr] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR32 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARC_LDH_DI_rs9 (459) - ARC_INS_LDH_DI - ldh.di	$A, [$addr] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR32 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - anonymous_7198 */
+  { 0 }
+}},
+{ /* ARC_LDH_S_OFF (460) - ARC_INS_LDH_S - ldh_s	$c, [$b, $off] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off */
+  { 0 }
+}},
+{ /* ARC_LDH_S_X_OFF (461) - ARC_INS_LDH_S_X - ldh_s.x	$c, [$b, $off] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off */
+  { 0 }
+}},
+{ /* ARC_LDH_S_rrr (462) - ARC_INS_LDH_S - ldh_s	$a, [$b, $c] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* a */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { 0 }
+}},
+{ /* ARC_LDH_X_AB_rs9 (463) - ARC_INS_LDH_X_AB - ldh.x.ab	$A, [$B,$S9] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addrout */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S9 */
+  { 0 }
+}},
+{ /* ARC_LDH_X_AW_rs9 (464) - ARC_INS_LDH_X_AW - ldh.x.aw	$A, [$B,$S9] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addrout */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S9 */
+  { 0 }
+}},
+{ /* ARC_LDH_X_DI_AB_rs9 (465) - ARC_INS_LDH_X_DI_AB - ldh.x.di.ab	$A, [$B,$S9] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addrout */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S9 */
+  { 0 }
+}},
+{ /* ARC_LDH_X_DI_AW_rs9 (466) - ARC_INS_LDH_X_DI_AW - ldh.x.di.aw	$A, [$B,$S9] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addrout */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S9 */
+  { 0 }
+}},
+{ /* ARC_LDH_X_DI_limm (467) - ARC_INS_LDH_X_DI - ldh.x.di	$A, [$addr] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARC_LDH_X_DI_rlimm (468) - ARC_INS_LDH_X_DI - ldh.x.di	$A, [$addr] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR32 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARC_LDH_X_DI_rs9 (469) - ARC_INS_LDH_X_DI - ldh.x.di	$A, [$addr] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR32 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - anonymous_7198 */
+  { 0 }
+}},
+{ /* ARC_LDH_X_limm (470) - ARC_INS_LDH_X - ldh.x	$A, [$addr] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARC_LDH_X_rlimm (471) - ARC_INS_LDH_X - ldh.x	$A, [$addr] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR32 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARC_LDH_X_rs9 (472) - ARC_INS_LDH_X - ldh.x	$A, [$addr] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR32 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - anonymous_7198 */
+  { 0 }
+}},
+{ /* ARC_LDH_limm (473) - ARC_INS_LDH - ldh	$A, [$addr] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARC_LDH_rlimm (474) - ARC_INS_LDH - ldh	$A, [$addr] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR32 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARC_LDH_rs9 (475) - ARC_INS_LDH - ldh	$A, [$addr] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR32 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - anonymous_7198 */
+  { 0 }
+}},
+{ /* ARC_LDI_S_u7 (476) - ARC_INS_LDI_S - ldi_s	$b, [$u7] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u7 */
+  { 0 }
+}},
+{ /* ARC_LD_AB_rs9 (477) - ARC_INS_LD_AB - ld.ab	$A, [$B,$S9] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addrout */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S9 */
+  { 0 }
+}},
+{ /* ARC_LD_AW_rs9 (478) - ARC_INS_LD_AW - ld.aw	$A, [$B,$S9] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addrout */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S9 */
+  { 0 }
+}},
+{ /* ARC_LD_DI_AB_rs9 (479) - ARC_INS_LD_DI_AB - ld.di.ab	$A, [$B,$S9] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addrout */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S9 */
+  { 0 }
+}},
+{ /* ARC_LD_DI_AW_rs9 (480) - ARC_INS_LD_DI_AW - ld.di.aw	$A, [$B,$S9] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addrout */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S9 */
+  { 0 }
+}},
+{ /* ARC_LD_DI_limm (481) - ARC_INS_LD_DI - ld.di	$A, [$addr] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARC_LD_DI_rlimm (482) - ARC_INS_LD_DI - ld.di	$A, [$addr] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR32 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARC_LD_DI_rs9 (483) - ARC_INS_LD_DI - ld.di	$A, [$addr] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR32 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - anonymous_7198 */
+  { 0 }
+}},
+{ /* ARC_LD_S_AS_rrr (484) - ARC_INS_LD_S_AS - ld_s.as	$a, [$b, $c] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* a */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { 0 }
+}},
+{ /* ARC_LD_S_OFF (485) - ARC_INS_LD_S - ld_s	$c, [$b, $off] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off */
+  { 0 }
+}},
+{ /* ARC_LD_S_rrr (486) - ARC_INS_LD_S - ld_s	$a, [$b, $c] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* a */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { 0 }
+}},
+{ /* ARC_LD_S_s11 (487) - ARC_INS_LD_S - ld_s	%r1, [%gp, $s11] */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s11 */
+  { 0 }
+}},
+{ /* ARC_LD_limm (488) - ARC_INS_LD - ld	$A, [$addr] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARC_LD_rlimm (489) - ARC_INS_LD - ld	$A, [$addr] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR32 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARC_LD_rs9 (490) - ARC_INS_LD - ld	$A, [$addr] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR32 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - anonymous_7198 */
+  { 0 }
+}},
+{ /* ARC_LEAVE_S (491) - ARC_INS_LEAVE_S - leave_s	$u7 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u7 */
+  { 0 }
+}},
+{ /* ARC_LR_rs12 (492) - ARC_INS_LR - lr	$B, [$C] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_LR_ru6 (493) - ARC_INS_LR - lr	$B, [$C] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_LSR_S_ru5 (494) - ARC_INS_LSR_S - lsr_s	$b, $b, $u5 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u5 */
+  { 0 }
+}},
+{ /* ARC_LSR_cc_f_rru6 (495) - ARC_INS_LSR - lsr.${cc}.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_LSR_cc_rru6 (496) - ARC_INS_LSR - lsr.$cc	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_LSR_f_rrlimm (497) - ARC_INS_LSR_F - lsr.f	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_LSR_f_rrr (498) - ARC_INS_LSR_F - lsr.f	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_LSR_f_rrs12 (499) - ARC_INS_LSR_F - lsr.f	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_LSR_f_rru6 (500) - ARC_INS_LSR_F - lsr.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_LSR_rrlimm (501) - ARC_INS_LSR - lsr	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_LSR_rrr (502) - ARC_INS_LSR - lsr	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_LSR_rrs12 (503) - ARC_INS_LSR - lsr	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_LSR_rru6 (504) - ARC_INS_LSR - lsr	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_MAX_cc_f_rru6 (505) - ARC_INS_MAX - max.${cc}.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_MAX_cc_rru6 (506) - ARC_INS_MAX - max.$cc	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_MAX_f_rrlimm (507) - ARC_INS_MAX_F - max.f	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_MAX_f_rrr (508) - ARC_INS_MAX_F - max.f	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_MAX_f_rrs12 (509) - ARC_INS_MAX_F - max.f	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_MAX_f_rru6 (510) - ARC_INS_MAX_F - max.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_MAX_rrlimm (511) - ARC_INS_MAX - max	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_MAX_rrr (512) - ARC_INS_MAX - max	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_MAX_rrs12 (513) - ARC_INS_MAX - max	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_MAX_rru6 (514) - ARC_INS_MAX - max	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_MIN_cc_f_rru6 (515) - ARC_INS_MIN - min.${cc}.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_MIN_cc_rru6 (516) - ARC_INS_MIN - min.$cc	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_MIN_f_rrlimm (517) - ARC_INS_MIN_F - min.f	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_MIN_f_rrr (518) - ARC_INS_MIN_F - min.f	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_MIN_f_rrs12 (519) - ARC_INS_MIN_F - min.f	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_MIN_f_rru6 (520) - ARC_INS_MIN_F - min.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_MIN_rrlimm (521) - ARC_INS_MIN - min	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_MIN_rrr (522) - ARC_INS_MIN - min	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_MIN_rrs12 (523) - ARC_INS_MIN - min	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_MIN_rru6 (524) - ARC_INS_MIN - min	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_MOV_S_NE_rlimm (525) - ARC_INS_MOV_S_NE - mov_s.ne	$b_s3, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b_s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_MOV_S_NE_rr (526) - ARC_INS_MOV_S_NE - mov_s.ne	$b_s3, $h */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b_s3 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* h */
+  { 0 }
+}},
+{ /* ARC_MOV_S_rs3 (527) - ARC_INS_MOV_S - mov_s	$h, $b_s3 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* h */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b_s3 */
+  { 0 }
+}},
+{ /* ARC_MOV_S_s3 (528) - ARC_INS_MOV_S - mov_s	0, $b_s3 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b_s3 */
+  { 0 }
+}},
+{ /* ARC_MOV_S_u8 (529) - ARC_INS_MOV_S - mov_s	$b, $u8 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u8 */
+  { 0 }
+}},
+{ /* ARC_MOV_cc (530) - ARC_INS_MOV - mov.$cc	$B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { 0 }
+}},
+{ /* ARC_MOV_cc_f_ru6 (531) - ARC_INS_MOV - mov.${cc}.f	$B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B2 */
+  { 0 }
+}},
+{ /* ARC_MOV_cc_ru6 (532) - ARC_INS_MOV - mov.$cc	$B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B2 */
+  { 0 }
+}},
+{ /* ARC_MOV_f_ru6 (533) - ARC_INS_MOV_F - mov.f	$B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_MOV_rlimm (534) - ARC_INS_MOV - mov	$B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_MOV_rr (535) - ARC_INS_MOV - mov	$B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_MOV_rs12 (536) - ARC_INS_MOV - mov	$B, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_MOV_ru6 (537) - ARC_INS_MOV - mov	$B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_MPYMU_cc_f_rru6 (538) - ARC_INS_MPYMU - mpymu.${cc}.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_MPYMU_cc_rru6 (539) - ARC_INS_MPYMU - mpymu.$cc	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_MPYMU_f_rrlimm (540) - ARC_INS_MPYMU_F - mpymu.f	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_MPYMU_f_rrr (541) - ARC_INS_MPYMU_F - mpymu.f	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_MPYMU_f_rrs12 (542) - ARC_INS_MPYMU_F - mpymu.f	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_MPYMU_f_rru6 (543) - ARC_INS_MPYMU_F - mpymu.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_MPYMU_rrlimm (544) - ARC_INS_MPYMU - mpymu	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_MPYMU_rrr (545) - ARC_INS_MPYMU - mpymu	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_MPYMU_rrs12 (546) - ARC_INS_MPYMU - mpymu	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_MPYMU_rru6 (547) - ARC_INS_MPYMU - mpymu	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_MPYM_cc_f_rru6 (548) - ARC_INS_MPYM - mpym.${cc}.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_MPYM_cc_rru6 (549) - ARC_INS_MPYM - mpym.$cc	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_MPYM_f_rrlimm (550) - ARC_INS_MPYM_F - mpym.f	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_MPYM_f_rrr (551) - ARC_INS_MPYM_F - mpym.f	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_MPYM_f_rrs12 (552) - ARC_INS_MPYM_F - mpym.f	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_MPYM_f_rru6 (553) - ARC_INS_MPYM_F - mpym.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_MPYM_rrlimm (554) - ARC_INS_MPYM - mpym	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_MPYM_rrr (555) - ARC_INS_MPYM - mpym	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_MPYM_rrs12 (556) - ARC_INS_MPYM - mpym	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_MPYM_rru6 (557) - ARC_INS_MPYM - mpym	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_MPY_cc_f_rru6 (558) - ARC_INS_MPY - mpy.${cc}.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_MPY_cc_rru6 (559) - ARC_INS_MPY - mpy.$cc	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_MPY_f_rrlimm (560) - ARC_INS_MPY_F - mpy.f	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_MPY_f_rrr (561) - ARC_INS_MPY_F - mpy.f	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_MPY_f_rrs12 (562) - ARC_INS_MPY_F - mpy.f	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_MPY_f_rru6 (563) - ARC_INS_MPY_F - mpy.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_MPY_rrlimm (564) - ARC_INS_MPY - mpy	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_MPY_rrr (565) - ARC_INS_MPY - mpy	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_MPY_rrs12 (566) - ARC_INS_MPY - mpy	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_MPY_rru6 (567) - ARC_INS_MPY - mpy	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_NORMH_f_rr (568) - ARC_INS_NORMH_F - normh.f	$B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_NORMH_rr (569) - ARC_INS_NORMH - normh	$B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_NORM_f_rr (570) - ARC_INS_NORM_F - norm.f	$B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_NORM_rr (571) - ARC_INS_NORM - norm	$B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_OR_cc_f_rru6 (572) - ARC_INS_OR - or.${cc}.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_OR_cc_rru6 (573) - ARC_INS_OR - or.$cc	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_OR_f_rrlimm (574) - ARC_INS_OR_F - or.f	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_OR_f_rrr (575) - ARC_INS_OR_F - or.f	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_OR_f_rrs12 (576) - ARC_INS_OR_F - or.f	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_OR_f_rru6 (577) - ARC_INS_OR_F - or.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_OR_rrlimm (578) - ARC_INS_OR - or	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_OR_rrr (579) - ARC_INS_OR - or	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_OR_rrs12 (580) - ARC_INS_OR - or	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_OR_rru6 (581) - ARC_INS_OR - or	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_PCL_LD (582) - ARC_INS_LD_S - ld_s	$b, [%pcl, $u10] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u10 */
+  { 0 }
+}},
+{ /* ARC_POP_S_BLINK (583) - ARC_INS_POP_S - pop_s	%blink */
+{
+  { 0 }
+}},
+{ /* ARC_POP_S_r (584) - ARC_INS_POP_S - pop_s	$b3 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_iAny, CS_DATA_TYPE_LAST } }, /* b3 */
+  { 0 }
+}},
+{ /* ARC_PUSH_S_BLINK (585) - ARC_INS_PUSH_S - push_s	%blink */
+{
+  { 0 }
+}},
+{ /* ARC_PUSH_S_r (586) - ARC_INS_PUSH_S - push_s	$b3 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_iAny, CS_DATA_TYPE_LAST } }, /* b3 */
+  { 0 }
+}},
+{ /* ARC_ROR_cc_f_rru6 (587) - ARC_INS_ROR - ror.${cc}.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_ROR_cc_rru6 (588) - ARC_INS_ROR - ror.$cc	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_ROR_f_rrlimm (589) - ARC_INS_ROR_F - ror.f	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_ROR_f_rrr (590) - ARC_INS_ROR_F - ror.f	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_ROR_f_rrs12 (591) - ARC_INS_ROR_F - ror.f	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_ROR_f_rru6 (592) - ARC_INS_ROR_F - ror.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_ROR_rrlimm (593) - ARC_INS_ROR - ror	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_ROR_rrr (594) - ARC_INS_ROR - ror	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_ROR_rrs12 (595) - ARC_INS_ROR - ror	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_ROR_rru6 (596) - ARC_INS_ROR - ror	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_RSUB_cc_f_rru6 (597) - ARC_INS_RSUB - rsub.${cc}.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_RSUB_cc_rru6 (598) - ARC_INS_RSUB - rsub.$cc	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_RSUB_f_rrlimm (599) - ARC_INS_RSUB_F - rsub.f	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_RSUB_f_rrr (600) - ARC_INS_RSUB_F - rsub.f	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_RSUB_f_rrs12 (601) - ARC_INS_RSUB_F - rsub.f	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_RSUB_f_rru6 (602) - ARC_INS_RSUB_F - rsub.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_RSUB_rrlimm (603) - ARC_INS_RSUB - rsub	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_RSUB_rrr (604) - ARC_INS_RSUB - rsub	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_RSUB_rrs12 (605) - ARC_INS_RSUB - rsub	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_RSUB_rru6 (606) - ARC_INS_RSUB - rsub	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_SBC_cc_f_rru6 (607) - ARC_INS_SBC - sbc.${cc}.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_SBC_cc_rru6 (608) - ARC_INS_SBC - sbc.$cc	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_SBC_f_rrlimm (609) - ARC_INS_SBC_F - sbc.f	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_SBC_f_rrr (610) - ARC_INS_SBC_F - sbc.f	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_SBC_f_rrs12 (611) - ARC_INS_SBC_F - sbc.f	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_SBC_f_rru6 (612) - ARC_INS_SBC_F - sbc.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_SBC_rrlimm (613) - ARC_INS_SBC - sbc	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_SBC_rrr (614) - ARC_INS_SBC - sbc	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_SBC_rrs12 (615) - ARC_INS_SBC - sbc	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_SBC_rru6 (616) - ARC_INS_SBC - sbc	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_SETEQ_cc_f_rru6 (617) - ARC_INS_SETEQ - seteq.${cc}.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_SETEQ_cc_rru6 (618) - ARC_INS_SETEQ - seteq.$cc	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_SETEQ_f_rrlimm (619) - ARC_INS_SETEQ_F - seteq.f	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_SETEQ_f_rrr (620) - ARC_INS_SETEQ_F - seteq.f	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_SETEQ_f_rrs12 (621) - ARC_INS_SETEQ_F - seteq.f	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_SETEQ_f_rru6 (622) - ARC_INS_SETEQ_F - seteq.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_SETEQ_rrlimm (623) - ARC_INS_SETEQ - seteq	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_SETEQ_rrr (624) - ARC_INS_SETEQ - seteq	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_SETEQ_rrs12 (625) - ARC_INS_SETEQ - seteq	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_SETEQ_rru6 (626) - ARC_INS_SETEQ - seteq	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_SEXB_f_rr (627) - ARC_INS_SEXB_F - sexb.f	$B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_SEXB_rr (628) - ARC_INS_SEXB - sexb	$B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_SEXH_f_rr (629) - ARC_INS_SEXH_F - sexh.f	$B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_SEXH_rr (630) - ARC_INS_SEXH - sexh	$B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_SP_ADD_S (631) - ARC_INS_ADD_S - add_s	$b3, %sp, $u7 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_iAny, CS_DATA_TYPE_LAST } }, /* b3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u7 */
+  { 0 }
+}},
+{ /* ARC_SP_ADD_SP_S (632) - ARC_INS_ADD_S - add_s	%sp, %sp, $u7 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u7 */
+  { 0 }
+}},
+{ /* ARC_SP_LDB_S (633) - ARC_INS_LDB_S - ldb_s	$b3, [%sp, $u7] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_iAny, CS_DATA_TYPE_LAST } }, /* b3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u7 */
+  { 0 }
+}},
+{ /* ARC_SP_LD_S (634) - ARC_INS_LD_S - ld_s	$b3, [%sp, $u7] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_iAny, CS_DATA_TYPE_LAST } }, /* b3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u7 */
+  { 0 }
+}},
+{ /* ARC_SP_STB_S (635) - ARC_INS_STB_S - stb_s	$b3, [%sp, $u7] */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_iAny, CS_DATA_TYPE_LAST } }, /* b3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u7 */
+  { 0 }
+}},
+{ /* ARC_SP_ST_S (636) - ARC_INS_ST_S - st_s	$b3, [%sp, $u7] */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_iAny, CS_DATA_TYPE_LAST } }, /* b3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u7 */
+  { 0 }
+}},
+{ /* ARC_SP_SUB_SP_S (637) - ARC_INS_SUB_S - sub_s	%sp, %sp, $u7 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u7 */
+  { 0 }
+}},
+{ /* ARC_STB_AB_rs9 (638) - ARC_INS_STB_AB - stb.ab	$C, [$B,$S9] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addrout */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S9 */
+  { 0 }
+}},
+{ /* ARC_STB_AW_rs9 (639) - ARC_INS_STB_AW - stb.aw	$C, [$B,$S9] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addrout */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S9 */
+  { 0 }
+}},
+{ /* ARC_STB_DI_AB_rs9 (640) - ARC_INS_STB_DI_AB - stb.di.ab	$C, [$B,$S9] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addrout */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S9 */
+  { 0 }
+}},
+{ /* ARC_STB_DI_AW_rs9 (641) - ARC_INS_STB_DI_AW - stb.di.aw	$C, [$B,$S9] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addrout */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S9 */
+  { 0 }
+}},
+{ /* ARC_STB_DI_limm (642) - ARC_INS_STB_DI - stb.di	$C, [$addr] */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARC_STB_DI_rs9 (643) - ARC_INS_STB_DI - stb.di	$C, [$addr] */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR32 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - anonymous_7198 */
+  { 0 }
+}},
+{ /* ARC_STB_S_OFF (644) - ARC_INS_STB_S - stb_s	$c, [$b, $off] */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off */
+  { 0 }
+}},
+{ /* ARC_STB_limm (645) - ARC_INS_STB - stb	$C, [$addr] */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARC_STB_rs9 (646) - ARC_INS_STB - stb	$C, [$addr] */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR32 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - anonymous_7198 */
+  { 0 }
+}},
+{ /* ARC_STH_AB_rs9 (647) - ARC_INS_STH_AB - sth.ab	$C, [$B,$S9] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addrout */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S9 */
+  { 0 }
+}},
+{ /* ARC_STH_AW_rs9 (648) - ARC_INS_STH_AW - sth.aw	$C, [$B,$S9] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addrout */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S9 */
+  { 0 }
+}},
+{ /* ARC_STH_DI_AB_rs9 (649) - ARC_INS_STH_DI_AB - sth.di.ab	$C, [$B,$S9] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addrout */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S9 */
+  { 0 }
+}},
+{ /* ARC_STH_DI_AW_rs9 (650) - ARC_INS_STH_DI_AW - sth.di.aw	$C, [$B,$S9] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addrout */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S9 */
+  { 0 }
+}},
+{ /* ARC_STH_DI_limm (651) - ARC_INS_STH_DI - sth.di	$C, [$addr] */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARC_STH_DI_rs9 (652) - ARC_INS_STH_DI - sth.di	$C, [$addr] */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR32 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - anonymous_7198 */
+  { 0 }
+}},
+{ /* ARC_STH_S_OFF (653) - ARC_INS_STH_S - sth_s	$c, [$b, $off] */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off */
+  { 0 }
+}},
+{ /* ARC_STH_limm (654) - ARC_INS_STH - sth	$C, [$addr] */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARC_STH_rs9 (655) - ARC_INS_STH - sth	$C, [$addr] */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR32 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - anonymous_7198 */
+  { 0 }
+}},
+{ /* ARC_ST_AB_rs9 (656) - ARC_INS_ST_AB - st.ab	$C, [$B,$S9] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addrout */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S9 */
+  { 0 }
+}},
+{ /* ARC_ST_AW_rs9 (657) - ARC_INS_ST_AW - st.aw	$C, [$B,$S9] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addrout */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S9 */
+  { 0 }
+}},
+{ /* ARC_ST_DI_AB_rs9 (658) - ARC_INS_ST_DI_AB - st.di.ab	$C, [$B,$S9] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addrout */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S9 */
+  { 0 }
+}},
+{ /* ARC_ST_DI_AW_rs9 (659) - ARC_INS_ST_DI_AW - st.di.aw	$C, [$B,$S9] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addrout */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S9 */
+  { 0 }
+}},
+{ /* ARC_ST_DI_limm (660) - ARC_INS_ST_DI - st.di	$C, [$addr] */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARC_ST_DI_rs9 (661) - ARC_INS_ST_DI - st.di	$C, [$addr] */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR32 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - anonymous_7198 */
+  { 0 }
+}},
+{ /* ARC_ST_S_OFF (662) - ARC_INS_ST_S - st_s	$c, [$b, $off] */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off */
+  { 0 }
+}},
+{ /* ARC_ST_S_s11 (663) - ARC_INS_ST_S - st_s	%r0, [%gp, $s11] */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s11 */
+  { 0 }
+}},
+{ /* ARC_ST_limm (664) - ARC_INS_ST - st	$C, [$addr] */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARC_ST_rs9 (665) - ARC_INS_ST - st	$C, [$addr] */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR32 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - anonymous_7198 */
+  { 0 }
+}},
+{ /* ARC_SUB1_cc_f_rru6 (666) - ARC_INS_SUB1 - sub1.${cc}.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_SUB1_cc_rru6 (667) - ARC_INS_SUB1 - sub1.$cc	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_SUB1_f_rrlimm (668) - ARC_INS_SUB1_F - sub1.f	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_SUB1_f_rrr (669) - ARC_INS_SUB1_F - sub1.f	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_SUB1_f_rrs12 (670) - ARC_INS_SUB1_F - sub1.f	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_SUB1_f_rru6 (671) - ARC_INS_SUB1_F - sub1.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_SUB1_rrlimm (672) - ARC_INS_SUB1 - sub1	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_SUB1_rrr (673) - ARC_INS_SUB1 - sub1	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_SUB1_rrs12 (674) - ARC_INS_SUB1 - sub1	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_SUB1_rru6 (675) - ARC_INS_SUB1 - sub1	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_SUB2_cc_f_rru6 (676) - ARC_INS_SUB2 - sub2.${cc}.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_SUB2_cc_rru6 (677) - ARC_INS_SUB2 - sub2.$cc	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_SUB2_f_rrlimm (678) - ARC_INS_SUB2_F - sub2.f	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_SUB2_f_rrr (679) - ARC_INS_SUB2_F - sub2.f	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_SUB2_f_rrs12 (680) - ARC_INS_SUB2_F - sub2.f	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_SUB2_f_rru6 (681) - ARC_INS_SUB2_F - sub2.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_SUB2_rrlimm (682) - ARC_INS_SUB2 - sub2	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_SUB2_rrr (683) - ARC_INS_SUB2 - sub2	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_SUB2_rrs12 (684) - ARC_INS_SUB2 - sub2	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_SUB2_rru6 (685) - ARC_INS_SUB2 - sub2	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_SUB3_cc_f_rru6 (686) - ARC_INS_SUB3 - sub3.${cc}.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_SUB3_cc_rru6 (687) - ARC_INS_SUB3 - sub3.$cc	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_SUB3_f_rrlimm (688) - ARC_INS_SUB3_F - sub3.f	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_SUB3_f_rrr (689) - ARC_INS_SUB3_F - sub3.f	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_SUB3_f_rrs12 (690) - ARC_INS_SUB3_F - sub3.f	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_SUB3_f_rru6 (691) - ARC_INS_SUB3_F - sub3.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_SUB3_rrlimm (692) - ARC_INS_SUB3 - sub3	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_SUB3_rrr (693) - ARC_INS_SUB3 - sub3	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_SUB3_rrs12 (694) - ARC_INS_SUB3 - sub3	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_SUB3_rru6 (695) - ARC_INS_SUB3 - sub3	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_SUB_S_rrr (696) - ARC_INS_SUB_S - sub_s	$a, $b, $c */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* a */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { 0 }
+}},
+{ /* ARC_SUB_S_ru3 (697) - ARC_INS_SUB_S - sub_s	$c, $b, $u3 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u3 */
+  { 0 }
+}},
+{ /* ARC_SUB_S_ru5 (698) - ARC_INS_SUB_S - sub_s	$b, $b, $u5 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u5 */
+  { 0 }
+}},
+{ /* ARC_SUB_cc_f_rru6 (699) - ARC_INS_SUB - sub.${cc}.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_SUB_cc_rru6 (700) - ARC_INS_SUB - sub.$cc	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_SUB_f_rrlimm (701) - ARC_INS_SUB_F - sub.f	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_SUB_f_rrr (702) - ARC_INS_SUB_F - sub.f	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_SUB_f_rrs12 (703) - ARC_INS_SUB_F - sub.f	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_SUB_f_rru6 (704) - ARC_INS_SUB_F - sub.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_SUB_rrlimm (705) - ARC_INS_SUB - sub	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_SUB_rrr (706) - ARC_INS_SUB - sub	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_SUB_rrs12 (707) - ARC_INS_SUB - sub	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_SUB_rru6 (708) - ARC_INS_SUB - sub	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_XOR_cc_f_rru6 (709) - ARC_INS_XOR - xor.${cc}.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_XOR_cc_rru6 (710) - ARC_INS_XOR - xor.$cc	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { 0 }
+}},
+{ /* ARC_XOR_f_rrlimm (711) - ARC_INS_XOR_F - xor.f	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_XOR_f_rrr (712) - ARC_INS_XOR_F - xor.f	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_XOR_f_rrs12 (713) - ARC_INS_XOR_F - xor.f	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_XOR_f_rru6 (714) - ARC_INS_XOR_F - xor.f	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
+{ /* ARC_XOR_rrlimm (715) - ARC_INS_XOR - xor	$A, $B, $LImm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LImm */
+  { 0 }
+}},
+{ /* ARC_XOR_rrr (716) - ARC_INS_XOR - xor	$A, $B, $C */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* C */
+  { 0 }
+}},
+{ /* ARC_XOR_rrs12 (717) - ARC_INS_XOR - xor	$B, $in, $S12 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* S12 */
+  { 0 }
+}},
+{ /* ARC_XOR_rru6 (718) - ARC_INS_XOR - xor	$A, $B, $U6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* A */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* B */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* U6 */
+  { 0 }
+}},
diff --git a/arch/ARC/ARCGenCSOpGroup.inc b/arch/ARC/ARCGenCSOpGroup.inc
new file mode 100644
index 0000000000..797ceeb7f0
--- /dev/null
+++ b/arch/ARC/ARCGenCSOpGroup.inc
@@ -0,0 +1,19 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+  ARC_OP_GROUP_Operand = 0,
+  ARC_OP_GROUP_PredicateOperand = 1,
+  ARC_OP_GROUP_MemOperandRI = 2,
+  ARC_OP_GROUP_BRCCPredicateOperand = 3,
+  ARC_OP_GROUP_CCOperand = 4,
+  ARC_OP_GROUP_U6 = 5,
diff --git a/arch/ARC/ARCGenCSRegEnum.inc b/arch/ARC/ARCGenCSRegEnum.inc
new file mode 100644
index 0000000000..58bd15a4e0
--- /dev/null
+++ b/arch/ARC/ARCGenCSRegEnum.inc
@@ -0,0 +1,80 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+	ARC_REG_INVALID = 0,
+	ARC_REG_BLINK = 1,
+	ARC_REG_FP = 2,
+	ARC_REG_GP = 3,
+	ARC_REG_ILINK = 4,
+	ARC_REG_SP = 5,
+	ARC_REG_R0 = 6,
+	ARC_REG_R1 = 7,
+	ARC_REG_R2 = 8,
+	ARC_REG_R3 = 9,
+	ARC_REG_R4 = 10,
+	ARC_REG_R5 = 11,
+	ARC_REG_R6 = 12,
+	ARC_REG_R7 = 13,
+	ARC_REG_R8 = 14,
+	ARC_REG_R9 = 15,
+	ARC_REG_R10 = 16,
+	ARC_REG_R11 = 17,
+	ARC_REG_R12 = 18,
+	ARC_REG_R13 = 19,
+	ARC_REG_R14 = 20,
+	ARC_REG_R15 = 21,
+	ARC_REG_R16 = 22,
+	ARC_REG_R17 = 23,
+	ARC_REG_R18 = 24,
+	ARC_REG_R19 = 25,
+	ARC_REG_R20 = 26,
+	ARC_REG_R21 = 27,
+	ARC_REG_R22 = 28,
+	ARC_REG_R23 = 29,
+	ARC_REG_R24 = 30,
+	ARC_REG_R25 = 31,
+	ARC_REG_R30 = 32,
+	ARC_REG_R32 = 33,
+	ARC_REG_R33 = 34,
+	ARC_REG_R34 = 35,
+	ARC_REG_R35 = 36,
+	ARC_REG_R36 = 37,
+	ARC_REG_R37 = 38,
+	ARC_REG_R38 = 39,
+	ARC_REG_R39 = 40,
+	ARC_REG_R40 = 41,
+	ARC_REG_R41 = 42,
+	ARC_REG_R42 = 43,
+	ARC_REG_R43 = 44,
+	ARC_REG_R44 = 45,
+	ARC_REG_R45 = 46,
+	ARC_REG_R46 = 47,
+	ARC_REG_R47 = 48,
+	ARC_REG_R48 = 49,
+	ARC_REG_R49 = 50,
+	ARC_REG_R50 = 51,
+	ARC_REG_R51 = 52,
+	ARC_REG_R52 = 53,
+	ARC_REG_R53 = 54,
+	ARC_REG_R54 = 55,
+	ARC_REG_R55 = 56,
+	ARC_REG_R56 = 57,
+	ARC_REG_R57 = 58,
+	ARC_REG_R58 = 59,
+	ARC_REG_R59 = 60,
+	ARC_REG_R60 = 61,
+	ARC_REG_R61 = 62,
+	ARC_REG_R62 = 63,
+	ARC_REG_R63 = 64,
+	ARC_REG_STATUS32 = 65,
+	ARC_REG_ENDING, // 66
diff --git a/arch/ARC/ARCGenDisassemblerTables.inc b/arch/ARC/ARCGenDisassemblerTables.inc
new file mode 100644
index 0000000000..0ebb2b45a6
--- /dev/null
+++ b/arch/ARC/ARCGenDisassemblerTables.inc
@@ -0,0 +1,1803 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+#include "../../MCInst.h"
+#include "../../cs_priv.h"
+#include "../../LEB128.h"
+
+// Helper function for extracting fields from encoded instructions.
+#define FieldFromInstruction(fname, InsnType) \
+static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
+{ \
+  InsnType fieldMask; \
+  if (numBits == sizeof(InsnType) * 8) \
+    fieldMask = (InsnType)(-1LL); \
+  else \
+    fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \
+  return (insn & fieldMask) >> startBit; \
+}
+
+static bool Check(DecodeStatus *Out, const DecodeStatus In) {
+  *Out = (DecodeStatus) (*Out & In);
+  return *Out != MCDisassembler_Fail;
+}
+
+static const uint8_t DecoderTable16[] = {
+/* 0 */       MCD_OPC_ExtractField, 11, 5,  // Inst{15-11} ...
+/* 3 */       MCD_OPC_FilterValue, 8, 21, 0, 0, // Skip to: 29
+/* 8 */       MCD_OPC_ExtractField, 2, 1,  // Inst{2} ...
+/* 11 */      MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 20
+/* 16 */      MCD_OPC_Decode, 247, 2, 0, // Opcode: COMPACT_MOV_S_hreg
+/* 20 */      MCD_OPC_FilterValue, 1, 209, 4, 0, // Skip to: 1258
+/* 25 */      MCD_OPC_Decode, 246, 2, 1, // Opcode: COMPACT_LD_S
+/* 29 */      MCD_OPC_FilterValue, 9, 38, 0, 0, // Skip to: 72
+/* 34 */      MCD_OPC_ExtractField, 3, 1,  // Inst{3} ...
+/* 37 */      MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 63
+/* 42 */      MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 45 */      MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 54
+/* 50 */      MCD_OPC_Decode, 228, 3, 2, // Opcode: LD_S_AS_rrr
+/* 54 */      MCD_OPC_FilterValue, 1, 175, 4, 0, // Skip to: 1258
+/* 59 */      MCD_OPC_Decode, 184, 5, 2, // Opcode: SUB_S_rrr
+/* 63 */      MCD_OPC_FilterValue, 1, 166, 4, 0, // Skip to: 1258
+/* 68 */      MCD_OPC_Decode, 167, 2, 3, // Opcode: ADD_S_rru6
+/* 72 */      MCD_OPC_FilterValue, 10, 38, 0, 0, // Skip to: 115
+/* 77 */      MCD_OPC_ExtractField, 3, 1,  // Inst{3} ...
+/* 80 */      MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 106
+/* 85 */      MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 88 */      MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 97
+/* 93 */      MCD_OPC_Decode, 231, 3, 4, // Opcode: LD_S_s11
+/* 97 */      MCD_OPC_FilterValue, 1, 132, 4, 0, // Skip to: 1258
+/* 102 */     MCD_OPC_Decode, 151, 5, 4, // Opcode: ST_S_s11
+/* 106 */     MCD_OPC_FilterValue, 1, 123, 4, 0, // Skip to: 1258
+/* 111 */     MCD_OPC_Decode, 220, 3, 5, // Opcode: LDI_S_u7
+/* 115 */     MCD_OPC_FilterValue, 11, 21, 0, 0, // Skip to: 141
+/* 120 */     MCD_OPC_ExtractField, 10, 1,  // Inst{10} ...
+/* 123 */     MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 132
+/* 128 */     MCD_OPC_Decode, 171, 3, 6, // Opcode: JLI_S
+/* 132 */     MCD_OPC_FilterValue, 1, 97, 4, 0, // Skip to: 1258
+/* 137 */     MCD_OPC_Decode, 249, 2, 6, // Opcode: EI_S
+/* 141 */     MCD_OPC_FilterValue, 12, 39, 0, 0, // Skip to: 185
+/* 146 */     MCD_OPC_ExtractField, 3, 2,  // Inst{4-3} ...
+/* 149 */     MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 158
+/* 154 */     MCD_OPC_Decode, 230, 3, 2, // Opcode: LD_S_rrr
+/* 158 */     MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 167
+/* 163 */     MCD_OPC_Decode, 183, 3, 2, // Opcode: LDB_S_rrr
+/* 167 */     MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 176
+/* 172 */     MCD_OPC_Decode, 206, 3, 2, // Opcode: LDH_S_rrr
+/* 176 */     MCD_OPC_FilterValue, 3, 53, 4, 0, // Skip to: 1258
+/* 181 */     MCD_OPC_Decode, 166, 2, 2, // Opcode: ADD_S_rrr
+/* 185 */     MCD_OPC_FilterValue, 13, 39, 0, 0, // Skip to: 229
+/* 190 */     MCD_OPC_ExtractField, 3, 2,  // Inst{4-3} ...
+/* 193 */     MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 202
+/* 198 */     MCD_OPC_Decode, 169, 2, 7, // Opcode: ADD_S_ru3
+/* 202 */     MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 211
+/* 207 */     MCD_OPC_Decode, 185, 5, 7, // Opcode: SUB_S_ru3
+/* 211 */     MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 220
+/* 216 */     MCD_OPC_Decode, 191, 2, 7, // Opcode: ASL_S_ru3
+/* 220 */     MCD_OPC_FilterValue, 3, 9, 4, 0, // Skip to: 1258
+/* 225 */     MCD_OPC_Decode, 203, 2, 7, // Opcode: ASR_S_ru3
+/* 229 */     MCD_OPC_FilterValue, 14, 75, 0, 0, // Skip to: 309
+/* 234 */     MCD_OPC_ExtractField, 2, 3,  // Inst{4-2} ...
+/* 237 */     MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 246
+/* 242 */     MCD_OPC_Decode, 165, 2, 8, // Opcode: ADD_S_rr
+/* 246 */     MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 255
+/* 251 */     MCD_OPC_Decode, 168, 2, 9, // Opcode: ADD_S_rs3
+/* 255 */     MCD_OPC_FilterValue, 3, 22, 0, 0, // Skip to: 282
+/* 260 */     MCD_OPC_CheckField, 5, 3, 6, 11, 0, 0, // Skip to: 278
+/* 267 */     MCD_OPC_CheckField, 0, 2, 3, 4, 0, 0, // Skip to: 278
+/* 274 */     MCD_OPC_Decode, 144, 4, 10, // Opcode: MOV_S_s3
+/* 278 */     MCD_OPC_Decode, 143, 4, 9, // Opcode: MOV_S_rs3
+/* 282 */     MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 291
+/* 287 */     MCD_OPC_Decode, 240, 2, 8, // Opcode: CMP_S_rr
+/* 291 */     MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 300
+/* 296 */     MCD_OPC_Decode, 241, 2, 9, // Opcode: CMP_S_rs3
+/* 300 */     MCD_OPC_FilterValue, 7, 185, 3, 0, // Skip to: 1258
+/* 305 */     MCD_OPC_Decode, 142, 4, 8, // Opcode: MOV_S_NE_rr
+/* 309 */     MCD_OPC_FilterValue, 15, 121, 1, 0, // Skip to: 691
+/* 314 */     MCD_OPC_ExtractField, 0, 5,  // Inst{4-0} ...
+/* 317 */     MCD_OPC_FilterValue, 0, 119, 0, 0, // Skip to: 441
+/* 322 */     MCD_OPC_ExtractField, 5, 3,  // Inst{7-5} ...
+/* 325 */     MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 334
+/* 330 */     MCD_OPC_Decode, 144, 3, 11, // Opcode: GEN_J_S
+/* 334 */     MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 343
+/* 339 */     MCD_OPC_Decode, 145, 3, 11, // Opcode: GEN_J_S_D
+/* 343 */     MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 352
+/* 348 */     MCD_OPC_Decode, 141, 3, 11, // Opcode: GEN_JL_S
+/* 352 */     MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 361
+/* 357 */     MCD_OPC_Decode, 142, 3, 11, // Opcode: GEN_JL_S_D
+/* 361 */     MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 370
+/* 366 */     MCD_OPC_Decode, 159, 3, 11, // Opcode: GEN_SUB_S_NE
+/* 370 */     MCD_OPC_FilterValue, 7, 115, 3, 0, // Skip to: 1258
+/* 375 */     MCD_OPC_ExtractField, 8, 3,  // Inst{10-8} ...
+/* 378 */     MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 387
+/* 383 */     MCD_OPC_Decode, 153, 3, 12, // Opcode: GEN_NOP_S
+/* 387 */     MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 396
+/* 392 */     MCD_OPC_Decode, 163, 3, 12, // Opcode: GEN_UNIMP_S
+/* 396 */     MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 405
+/* 401 */     MCD_OPC_Decode, 160, 3, 12, // Opcode: GEN_SWI_S
+/* 405 */     MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 414
+/* 410 */     MCD_OPC_Decode, 140, 3, 12, // Opcode: GEN_JEQ_S
+/* 414 */     MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 423
+/* 419 */     MCD_OPC_Decode, 143, 3, 12, // Opcode: GEN_JNE_S
+/* 423 */     MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 432
+/* 428 */     MCD_OPC_Decode, 174, 3, 12, // Opcode: J_S_BLINK
+/* 432 */     MCD_OPC_FilterValue, 7, 53, 3, 0, // Skip to: 1258
+/* 437 */     MCD_OPC_Decode, 146, 3, 12, // Opcode: GEN_J_S_D_BLINK
+/* 441 */     MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 450
+/* 446 */     MCD_OPC_Decode, 158, 3, 13, // Opcode: GEN_SUB_S
+/* 450 */     MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 459
+/* 455 */     MCD_OPC_Decode, 131, 3, 13, // Opcode: GEN_AND_S
+/* 459 */     MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 468
+/* 464 */     MCD_OPC_Decode, 155, 3, 13, // Opcode: GEN_OR_S
+/* 468 */     MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 477
+/* 473 */     MCD_OPC_Decode, 136, 3, 13, // Opcode: GEN_BIC_S
+/* 477 */     MCD_OPC_FilterValue, 7, 4, 0, 0, // Skip to: 486
+/* 482 */     MCD_OPC_Decode, 164, 3, 13, // Opcode: GEN_XOR_S
+/* 486 */     MCD_OPC_FilterValue, 9, 4, 0, 0, // Skip to: 495
+/* 491 */     MCD_OPC_Decode, 150, 3, 13, // Opcode: GEN_MPYW_S
+/* 495 */     MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 504
+/* 500 */     MCD_OPC_Decode, 149, 3, 13, // Opcode: GEN_MPYUW_S
+/* 504 */     MCD_OPC_FilterValue, 11, 4, 0, 0, // Skip to: 513
+/* 509 */     MCD_OPC_Decode, 162, 3, 13, // Opcode: GEN_TST_S
+/* 513 */     MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 522
+/* 518 */     MCD_OPC_Decode, 151, 3, 13, // Opcode: GEN_MPY_S
+/* 522 */     MCD_OPC_FilterValue, 13, 4, 0, 0, // Skip to: 531
+/* 527 */     MCD_OPC_Decode, 156, 3, 13, // Opcode: GEN_SEXB_S
+/* 531 */     MCD_OPC_FilterValue, 14, 4, 0, 0, // Skip to: 540
+/* 536 */     MCD_OPC_Decode, 157, 3, 13, // Opcode: GEN_SEXH_S
+/* 540 */     MCD_OPC_FilterValue, 15, 4, 0, 0, // Skip to: 549
+/* 545 */     MCD_OPC_Decode, 138, 3, 13, // Opcode: GEN_EXTB_S
+/* 549 */     MCD_OPC_FilterValue, 16, 4, 0, 0, // Skip to: 558
+/* 554 */     MCD_OPC_Decode, 139, 3, 13, // Opcode: GEN_EXTH_S
+/* 558 */     MCD_OPC_FilterValue, 17, 4, 0, 0, // Skip to: 567
+/* 563 */     MCD_OPC_Decode, 255, 2, 13, // Opcode: GEN_ABS_S
+/* 567 */     MCD_OPC_FilterValue, 18, 4, 0, 0, // Skip to: 576
+/* 572 */     MCD_OPC_Decode, 154, 3, 13, // Opcode: GEN_NOT_S
+/* 576 */     MCD_OPC_FilterValue, 19, 4, 0, 0, // Skip to: 585
+/* 581 */     MCD_OPC_Decode, 152, 3, 13, // Opcode: GEN_NEG_S
+/* 585 */     MCD_OPC_FilterValue, 20, 4, 0, 0, // Skip to: 594
+/* 590 */     MCD_OPC_Decode, 128, 3, 13, // Opcode: GEN_ADD1_S
+/* 594 */     MCD_OPC_FilterValue, 21, 4, 0, 0, // Skip to: 603
+/* 599 */     MCD_OPC_Decode, 129, 3, 13, // Opcode: GEN_ADD2_S
+/* 603 */     MCD_OPC_FilterValue, 22, 4, 0, 0, // Skip to: 612
+/* 608 */     MCD_OPC_Decode, 130, 3, 13, // Opcode: GEN_ADD3_S
+/* 612 */     MCD_OPC_FilterValue, 24, 4, 0, 0, // Skip to: 621
+/* 617 */     MCD_OPC_Decode, 134, 3, 13, // Opcode: GEN_ASL_S
+/* 621 */     MCD_OPC_FilterValue, 25, 4, 0, 0, // Skip to: 630
+/* 626 */     MCD_OPC_Decode, 148, 3, 13, // Opcode: GEN_LSR_S
+/* 630 */     MCD_OPC_FilterValue, 26, 4, 0, 0, // Skip to: 639
+/* 635 */     MCD_OPC_Decode, 135, 3, 13, // Opcode: GEN_ASR_S
+/* 639 */     MCD_OPC_FilterValue, 27, 4, 0, 0, // Skip to: 648
+/* 644 */     MCD_OPC_Decode, 132, 3, 13, // Opcode: GEN_AS1L_S
+/* 648 */     MCD_OPC_FilterValue, 28, 4, 0, 0, // Skip to: 657
+/* 653 */     MCD_OPC_Decode, 133, 3, 13, // Opcode: GEN_AS1R_S
+/* 657 */     MCD_OPC_FilterValue, 29, 4, 0, 0, // Skip to: 666
+/* 662 */     MCD_OPC_Decode, 147, 3, 13, // Opcode: GEN_LS1R_S
+/* 666 */     MCD_OPC_FilterValue, 30, 4, 0, 0, // Skip to: 675
+/* 671 */     MCD_OPC_Decode, 161, 3, 14, // Opcode: GEN_TRAP_S
+/* 675 */     MCD_OPC_FilterValue, 31, 66, 2, 0, // Skip to: 1258
+/* 680 */     MCD_OPC_CheckField, 5, 6, 63, 59, 2, 0, // Skip to: 1258
+/* 687 */     MCD_OPC_Decode, 137, 3, 12, // Opcode: GEN_BRK_S
+/* 691 */     MCD_OPC_FilterValue, 16, 4, 0, 0, // Skip to: 700
+/* 696 */     MCD_OPC_Decode, 229, 3, 15, // Opcode: LD_S_OFF
+/* 700 */     MCD_OPC_FilterValue, 17, 4, 0, 0, // Skip to: 709
+/* 705 */     MCD_OPC_Decode, 182, 3, 16, // Opcode: LDB_S_OFF
+/* 709 */     MCD_OPC_FilterValue, 18, 4, 0, 0, // Skip to: 718
+/* 714 */     MCD_OPC_Decode, 204, 3, 17, // Opcode: LDH_S_OFF
+/* 718 */     MCD_OPC_FilterValue, 19, 4, 0, 0, // Skip to: 727
+/* 723 */     MCD_OPC_Decode, 205, 3, 17, // Opcode: LDH_S_X_OFF
+/* 727 */     MCD_OPC_FilterValue, 20, 4, 0, 0, // Skip to: 736
+/* 732 */     MCD_OPC_Decode, 150, 5, 15, // Opcode: ST_S_OFF
+/* 736 */     MCD_OPC_FilterValue, 21, 4, 0, 0, // Skip to: 745
+/* 741 */     MCD_OPC_Decode, 132, 5, 16, // Opcode: STB_S_OFF
+/* 745 */     MCD_OPC_FilterValue, 22, 4, 0, 0, // Skip to: 754
+/* 750 */     MCD_OPC_Decode, 141, 5, 17, // Opcode: STH_S_OFF
+/* 754 */     MCD_OPC_FilterValue, 23, 75, 0, 0, // Skip to: 834
+/* 759 */     MCD_OPC_ExtractField, 5, 3,  // Inst{7-5} ...
+/* 762 */     MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 771
+/* 767 */     MCD_OPC_Decode, 192, 2, 18, // Opcode: ASL_S_ru5
+/* 771 */     MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 780
+/* 776 */     MCD_OPC_Decode, 238, 3, 18, // Opcode: LSR_S_ru5
+/* 780 */     MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 789
+/* 785 */     MCD_OPC_Decode, 204, 2, 18, // Opcode: ASR_S_ru5
+/* 789 */     MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 798
+/* 794 */     MCD_OPC_Decode, 186, 5, 18, // Opcode: SUB_S_ru5
+/* 798 */     MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 807
+/* 803 */     MCD_OPC_Decode, 234, 2, 18, // Opcode: BSET_S_ru5
+/* 807 */     MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 816
+/* 812 */     MCD_OPC_Decode, 215, 2, 18, // Opcode: BCLR_S_ru5
+/* 816 */     MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 825
+/* 821 */     MCD_OPC_Decode, 227, 2, 18, // Opcode: BMSK_S_ru5
+/* 825 */     MCD_OPC_FilterValue, 7, 172, 1, 0, // Skip to: 1258
+/* 830 */     MCD_OPC_Decode, 235, 2, 18, // Opcode: BTST_S_ru5
+/* 834 */     MCD_OPC_FilterValue, 24, 181, 0, 0, // Skip to: 1020
+/* 839 */     MCD_OPC_ExtractField, 5, 3,  // Inst{7-5} ...
+/* 842 */     MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 851
+/* 847 */     MCD_OPC_Decode, 250, 4, 19, // Opcode: SP_LD_S
+/* 851 */     MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 860
+/* 856 */     MCD_OPC_Decode, 249, 4, 19, // Opcode: SP_LDB_S
+/* 860 */     MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 869
+/* 865 */     MCD_OPC_Decode, 252, 4, 19, // Opcode: SP_ST_S
+/* 869 */     MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 878
+/* 874 */     MCD_OPC_Decode, 251, 4, 19, // Opcode: SP_STB_S
+/* 878 */     MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 887
+/* 883 */     MCD_OPC_Decode, 247, 4, 19, // Opcode: SP_ADD_S
+/* 887 */     MCD_OPC_FilterValue, 5, 21, 0, 0, // Skip to: 913
+/* 892 */     MCD_OPC_ExtractField, 8, 3,  // Inst{10-8} ...
+/* 895 */     MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 904
+/* 900 */     MCD_OPC_Decode, 248, 4, 20, // Opcode: SP_ADD_SP_S
+/* 904 */     MCD_OPC_FilterValue, 1, 93, 1, 0, // Skip to: 1258
+/* 909 */     MCD_OPC_Decode, 253, 4, 20, // Opcode: SP_SUB_SP_S
+/* 913 */     MCD_OPC_FilterValue, 6, 45, 0, 0, // Skip to: 963
+/* 918 */     MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 921 */     MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 930
+/* 926 */     MCD_OPC_Decode, 235, 3, 21, // Opcode: LEAVE_S
+/* 930 */     MCD_OPC_FilterValue, 1, 67, 1, 0, // Skip to: 1258
+/* 935 */     MCD_OPC_ExtractField, 1, 4,  // Inst{4-1} ...
+/* 938 */     MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 947
+/* 943 */     MCD_OPC_Decode, 202, 4, 22, // Opcode: PUSH_S_r
+/* 947 */     MCD_OPC_FilterValue, 8, 50, 1, 0, // Skip to: 1258
+/* 952 */     MCD_OPC_CheckField, 8, 3, 0, 43, 1, 0, // Skip to: 1258
+/* 959 */     MCD_OPC_Decode, 199, 4, 12, // Opcode: POP_S_BLINK
+/* 963 */     MCD_OPC_FilterValue, 7, 34, 1, 0, // Skip to: 1258
+/* 968 */     MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 971 */     MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 987
+/* 976 */     MCD_OPC_CheckField, 10, 1, 0, 19, 1, 0, // Skip to: 1258
+/* 983 */     MCD_OPC_Decode, 250, 2, 23, // Opcode: ENTER_S
+/* 987 */     MCD_OPC_FilterValue, 1, 10, 1, 0, // Skip to: 1258
+/* 992 */     MCD_OPC_ExtractField, 1, 4,  // Inst{4-1} ...
+/* 995 */     MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1004
+/* 1000 */    MCD_OPC_Decode, 200, 4, 22, // Opcode: POP_S_r
+/* 1004 */    MCD_OPC_FilterValue, 8, 249, 0, 0, // Skip to: 1258
+/* 1009 */    MCD_OPC_CheckField, 8, 3, 0, 242, 0, 0, // Skip to: 1258
+/* 1016 */    MCD_OPC_Decode, 201, 4, 12, // Opcode: PUSH_S_BLINK
+/* 1020 */    MCD_OPC_FilterValue, 25, 39, 0, 0, // Skip to: 1064
+/* 1025 */    MCD_OPC_ExtractField, 9, 2,  // Inst{10-9} ...
+/* 1028 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1037
+/* 1033 */    MCD_OPC_Decode, 168, 3, 24, // Opcode: GP_LD_S
+/* 1037 */    MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 1046
+/* 1042 */    MCD_OPC_Decode, 166, 3, 25, // Opcode: GP_LDB_S
+/* 1046 */    MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 1055
+/* 1051 */    MCD_OPC_Decode, 167, 3, 26, // Opcode: GP_LDH_S
+/* 1055 */    MCD_OPC_FilterValue, 3, 198, 0, 0, // Skip to: 1258
+/* 1060 */    MCD_OPC_Decode, 165, 3, 24, // Opcode: GP_ADD_S
+/* 1064 */    MCD_OPC_FilterValue, 26, 4, 0, 0, // Skip to: 1073
+/* 1069 */    MCD_OPC_Decode, 198, 4, 27, // Opcode: PCL_LD
+/* 1073 */    MCD_OPC_FilterValue, 27, 4, 0, 0, // Skip to: 1082
+/* 1078 */    MCD_OPC_Decode, 145, 4, 28, // Opcode: MOV_S_u8
+/* 1082 */    MCD_OPC_FilterValue, 28, 21, 0, 0, // Skip to: 1108
+/* 1087 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1090 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1099
+/* 1095 */    MCD_OPC_Decode, 170, 2, 29, // Opcode: ADD_S_u7
+/* 1099 */    MCD_OPC_FilterValue, 1, 154, 0, 0, // Skip to: 1258
+/* 1104 */    MCD_OPC_Decode, 242, 2, 29, // Opcode: CMP_S_u7
+/* 1108 */    MCD_OPC_FilterValue, 29, 21, 0, 0, // Skip to: 1134
+/* 1113 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1116 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1125
+/* 1121 */    MCD_OPC_Decode, 230, 2, 30, // Opcode: BREQ_S
+/* 1125 */    MCD_OPC_FilterValue, 1, 128, 0, 0, // Skip to: 1258
+/* 1130 */    MCD_OPC_Decode, 231, 2, 30, // Opcode: BRNE_S
+/* 1134 */    MCD_OPC_FilterValue, 30, 110, 0, 0, // Skip to: 1249
+/* 1139 */    MCD_OPC_ExtractField, 9, 2,  // Inst{10-9} ...
+/* 1142 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1151
+/* 1147 */    MCD_OPC_Decode, 236, 2, 31, // Opcode: B_S
+/* 1151 */    MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 1160
+/* 1156 */    MCD_OPC_Decode, 216, 2, 31, // Opcode: BEQ_S
+/* 1160 */    MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 1169
+/* 1165 */    MCD_OPC_Decode, 228, 2, 31, // Opcode: BNE_S
+/* 1169 */    MCD_OPC_FilterValue, 3, 84, 0, 0, // Skip to: 1258
+/* 1174 */    MCD_OPC_ExtractField, 6, 3,  // Inst{8-6} ...
+/* 1177 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1186
+/* 1182 */    MCD_OPC_Decode, 218, 2, 32, // Opcode: BGT_S
+/* 1186 */    MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 1195
+/* 1191 */    MCD_OPC_Decode, 217, 2, 32, // Opcode: BGE_S
+/* 1195 */    MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 1204
+/* 1200 */    MCD_OPC_Decode, 225, 2, 32, // Opcode: BLT_S
+/* 1204 */    MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 1213
+/* 1209 */    MCD_OPC_Decode, 222, 2, 32, // Opcode: BLE_S
+/* 1213 */    MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 1222
+/* 1218 */    MCD_OPC_Decode, 219, 2, 32, // Opcode: BHI_S
+/* 1222 */    MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 1231
+/* 1227 */    MCD_OPC_Decode, 220, 2, 32, // Opcode: BHS_S
+/* 1231 */    MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 1240
+/* 1236 */    MCD_OPC_Decode, 223, 2, 32, // Opcode: BLO_S
+/* 1240 */    MCD_OPC_FilterValue, 7, 13, 0, 0, // Skip to: 1258
+/* 1245 */    MCD_OPC_Decode, 224, 2, 32, // Opcode: BLS_S
+/* 1249 */    MCD_OPC_FilterValue, 31, 4, 0, 0, // Skip to: 1258
+/* 1254 */    MCD_OPC_Decode, 226, 2, 33, // Opcode: BL_S
+/* 1258 */    MCD_OPC_Fail,
+  0
+};
+
+static const uint8_t DecoderTable32[] = {
+/* 0 */       MCD_OPC_ExtractField, 27, 5,  // Inst{31-27} ...
+/* 3 */       MCD_OPC_FilterValue, 0, 28, 0, 0, // Skip to: 36
+/* 8 */       MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 11 */      MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 20
+/* 16 */      MCD_OPC_Decode, 237, 2, 34, // Opcode: Bcc
+/* 20 */      MCD_OPC_FilterValue, 1, 205, 10, 0, // Skip to: 2790
+/* 25 */      MCD_OPC_CheckField, 4, 1, 0, 198, 10, 0, // Skip to: 2790
+/* 32 */      MCD_OPC_Decode, 229, 2, 35, // Opcode: BR
+/* 36 */      MCD_OPC_FilterValue, 1, 66, 0, 0, // Skip to: 107
+/* 41 */      MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 44 */      MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 84
+/* 49 */      MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 52 */      MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 68
+/* 57 */      MCD_OPC_CheckField, 17, 1, 1, 166, 10, 0, // Skip to: 2790
+/* 64 */      MCD_OPC_Decode, 221, 2, 36, // Opcode: BL
+/* 68 */      MCD_OPC_FilterValue, 1, 157, 10, 0, // Skip to: 2790
+/* 73 */      MCD_OPC_CheckField, 3, 1, 0, 150, 10, 0, // Skip to: 2790
+/* 80 */      MCD_OPC_Decode, 232, 2, 37, // Opcode: BRcc_rr
+/* 84 */      MCD_OPC_FilterValue, 1, 141, 10, 0, // Skip to: 2790
+/* 89 */      MCD_OPC_CheckField, 16, 1, 1, 134, 10, 0, // Skip to: 2790
+/* 96 */      MCD_OPC_CheckField, 3, 1, 0, 127, 10, 0, // Skip to: 2790
+/* 103 */     MCD_OPC_Decode, 233, 2, 38, // Opcode: BRcc_ru6
+/* 107 */     MCD_OPC_FilterValue, 2, 17, 1, 0, // Skip to: 385
+/* 112 */     MCD_OPC_ExtractField, 6, 6,  // Inst{11-6} ...
+/* 115 */     MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 124
+/* 120 */     MCD_OPC_Decode, 234, 3, 39, // Opcode: LD_rs9
+/* 124 */     MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 133
+/* 129 */     MCD_OPC_Decode, 196, 3, 39, // Opcode: LDB_rs9
+/* 133 */     MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 142
+/* 138 */     MCD_OPC_Decode, 193, 3, 39, // Opcode: LDB_X_rs9
+/* 142 */     MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 151
+/* 147 */     MCD_OPC_Decode, 219, 3, 39, // Opcode: LDH_rs9
+/* 151 */     MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 160
+/* 156 */     MCD_OPC_Decode, 216, 3, 39, // Opcode: LDH_X_rs9
+/* 160 */     MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 169
+/* 165 */     MCD_OPC_Decode, 222, 3, 40, // Opcode: LD_AW_rs9
+/* 169 */     MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 178
+/* 174 */     MCD_OPC_Decode, 176, 3, 40, // Opcode: LDB_AW_rs9
+/* 178 */     MCD_OPC_FilterValue, 11, 4, 0, 0, // Skip to: 187
+/* 183 */     MCD_OPC_Decode, 185, 3, 40, // Opcode: LDB_X_AW_rs9
+/* 187 */     MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 196
+/* 192 */     MCD_OPC_Decode, 198, 3, 40, // Opcode: LDH_AW_rs9
+/* 196 */     MCD_OPC_FilterValue, 13, 4, 0, 0, // Skip to: 205
+/* 201 */     MCD_OPC_Decode, 208, 3, 40, // Opcode: LDH_X_AW_rs9
+/* 205 */     MCD_OPC_FilterValue, 16, 4, 0, 0, // Skip to: 214
+/* 210 */     MCD_OPC_Decode, 221, 3, 40, // Opcode: LD_AB_rs9
+/* 214 */     MCD_OPC_FilterValue, 18, 4, 0, 0, // Skip to: 223
+/* 219 */     MCD_OPC_Decode, 175, 3, 40, // Opcode: LDB_AB_rs9
+/* 223 */     MCD_OPC_FilterValue, 19, 4, 0, 0, // Skip to: 232
+/* 228 */     MCD_OPC_Decode, 184, 3, 40, // Opcode: LDB_X_AB_rs9
+/* 232 */     MCD_OPC_FilterValue, 20, 4, 0, 0, // Skip to: 241
+/* 237 */     MCD_OPC_Decode, 197, 3, 40, // Opcode: LDH_AB_rs9
+/* 241 */     MCD_OPC_FilterValue, 21, 4, 0, 0, // Skip to: 250
+/* 246 */     MCD_OPC_Decode, 207, 3, 40, // Opcode: LDH_X_AB_rs9
+/* 250 */     MCD_OPC_FilterValue, 32, 4, 0, 0, // Skip to: 259
+/* 255 */     MCD_OPC_Decode, 227, 3, 39, // Opcode: LD_DI_rs9
+/* 259 */     MCD_OPC_FilterValue, 34, 4, 0, 0, // Skip to: 268
+/* 264 */     MCD_OPC_Decode, 181, 3, 39, // Opcode: LDB_DI_rs9
+/* 268 */     MCD_OPC_FilterValue, 35, 4, 0, 0, // Skip to: 277
+/* 273 */     MCD_OPC_Decode, 190, 3, 39, // Opcode: LDB_X_DI_rs9
+/* 277 */     MCD_OPC_FilterValue, 36, 4, 0, 0, // Skip to: 286
+/* 282 */     MCD_OPC_Decode, 203, 3, 39, // Opcode: LDH_DI_rs9
+/* 286 */     MCD_OPC_FilterValue, 37, 4, 0, 0, // Skip to: 295
+/* 291 */     MCD_OPC_Decode, 213, 3, 39, // Opcode: LDH_X_DI_rs9
+/* 295 */     MCD_OPC_FilterValue, 40, 4, 0, 0, // Skip to: 304
+/* 300 */     MCD_OPC_Decode, 224, 3, 40, // Opcode: LD_DI_AW_rs9
+/* 304 */     MCD_OPC_FilterValue, 42, 4, 0, 0, // Skip to: 313
+/* 309 */     MCD_OPC_Decode, 178, 3, 40, // Opcode: LDB_DI_AW_rs9
+/* 313 */     MCD_OPC_FilterValue, 43, 4, 0, 0, // Skip to: 322
+/* 318 */     MCD_OPC_Decode, 187, 3, 40, // Opcode: LDB_X_DI_AW_rs9
+/* 322 */     MCD_OPC_FilterValue, 44, 4, 0, 0, // Skip to: 331
+/* 327 */     MCD_OPC_Decode, 200, 3, 40, // Opcode: LDH_DI_AW_rs9
+/* 331 */     MCD_OPC_FilterValue, 45, 4, 0, 0, // Skip to: 340
+/* 336 */     MCD_OPC_Decode, 210, 3, 40, // Opcode: LDH_X_DI_AW_rs9
+/* 340 */     MCD_OPC_FilterValue, 48, 4, 0, 0, // Skip to: 349
+/* 345 */     MCD_OPC_Decode, 223, 3, 40, // Opcode: LD_DI_AB_rs9
+/* 349 */     MCD_OPC_FilterValue, 50, 4, 0, 0, // Skip to: 358
+/* 354 */     MCD_OPC_Decode, 177, 3, 40, // Opcode: LDB_DI_AB_rs9
+/* 358 */     MCD_OPC_FilterValue, 51, 4, 0, 0, // Skip to: 367
+/* 363 */     MCD_OPC_Decode, 186, 3, 40, // Opcode: LDB_X_DI_AB_rs9
+/* 367 */     MCD_OPC_FilterValue, 52, 4, 0, 0, // Skip to: 376
+/* 372 */     MCD_OPC_Decode, 199, 3, 40, // Opcode: LDH_DI_AB_rs9
+/* 376 */     MCD_OPC_FilterValue, 53, 105, 9, 0, // Skip to: 2790
+/* 381 */     MCD_OPC_Decode, 209, 3, 40, // Opcode: LDH_X_DI_AB_rs9
+/* 385 */     MCD_OPC_FilterValue, 3, 165, 0, 0, // Skip to: 555
+/* 390 */     MCD_OPC_ExtractField, 0, 6,  // Inst{5-0} ...
+/* 393 */     MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 402
+/* 398 */     MCD_OPC_Decode, 153, 5, 41, // Opcode: ST_rs9
+/* 402 */     MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 411
+/* 407 */     MCD_OPC_Decode, 134, 5, 41, // Opcode: STB_rs9
+/* 411 */     MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 420
+/* 416 */     MCD_OPC_Decode, 143, 5, 41, // Opcode: STH_rs9
+/* 420 */     MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 429
+/* 425 */     MCD_OPC_Decode, 145, 5, 42, // Opcode: ST_AW_rs9
+/* 429 */     MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 438
+/* 434 */     MCD_OPC_Decode, 255, 4, 42, // Opcode: STB_AW_rs9
+/* 438 */     MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 447
+/* 443 */     MCD_OPC_Decode, 136, 5, 42, // Opcode: STH_AW_rs9
+/* 447 */     MCD_OPC_FilterValue, 16, 4, 0, 0, // Skip to: 456
+/* 452 */     MCD_OPC_Decode, 144, 5, 42, // Opcode: ST_AB_rs9
+/* 456 */     MCD_OPC_FilterValue, 18, 4, 0, 0, // Skip to: 465
+/* 461 */     MCD_OPC_Decode, 254, 4, 42, // Opcode: STB_AB_rs9
+/* 465 */     MCD_OPC_FilterValue, 20, 4, 0, 0, // Skip to: 474
+/* 470 */     MCD_OPC_Decode, 135, 5, 42, // Opcode: STH_AB_rs9
+/* 474 */     MCD_OPC_FilterValue, 32, 4, 0, 0, // Skip to: 483
+/* 479 */     MCD_OPC_Decode, 149, 5, 41, // Opcode: ST_DI_rs9
+/* 483 */     MCD_OPC_FilterValue, 34, 4, 0, 0, // Skip to: 492
+/* 488 */     MCD_OPC_Decode, 131, 5, 41, // Opcode: STB_DI_rs9
+/* 492 */     MCD_OPC_FilterValue, 36, 4, 0, 0, // Skip to: 501
+/* 497 */     MCD_OPC_Decode, 140, 5, 41, // Opcode: STH_DI_rs9
+/* 501 */     MCD_OPC_FilterValue, 40, 4, 0, 0, // Skip to: 510
+/* 506 */     MCD_OPC_Decode, 147, 5, 42, // Opcode: ST_DI_AW_rs9
+/* 510 */     MCD_OPC_FilterValue, 42, 4, 0, 0, // Skip to: 519
+/* 515 */     MCD_OPC_Decode, 129, 5, 42, // Opcode: STB_DI_AW_rs9
+/* 519 */     MCD_OPC_FilterValue, 44, 4, 0, 0, // Skip to: 528
+/* 524 */     MCD_OPC_Decode, 138, 5, 42, // Opcode: STH_DI_AW_rs9
+/* 528 */     MCD_OPC_FilterValue, 48, 4, 0, 0, // Skip to: 537
+/* 533 */     MCD_OPC_Decode, 146, 5, 42, // Opcode: ST_DI_AB_rs9
+/* 537 */     MCD_OPC_FilterValue, 50, 4, 0, 0, // Skip to: 546
+/* 542 */     MCD_OPC_Decode, 128, 5, 42, // Opcode: STB_DI_AB_rs9
+/* 546 */     MCD_OPC_FilterValue, 52, 191, 8, 0, // Skip to: 2790
+/* 551 */     MCD_OPC_Decode, 137, 5, 42, // Opcode: STH_DI_AB_rs9
+/* 555 */     MCD_OPC_FilterValue, 4, 230, 6, 0, // Skip to: 2326
+/* 560 */     MCD_OPC_ExtractField, 15, 9,  // Inst{23-15} ...
+/* 563 */     MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 572
+/* 568 */     MCD_OPC_Decode, 178, 2, 43, // Opcode: ADD_rrr
+/* 572 */     MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 581
+/* 577 */     MCD_OPC_Decode, 174, 2, 43, // Opcode: ADD_f_rrr
+/* 581 */     MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 590
+/* 586 */     MCD_OPC_Decode, 160, 2, 43, // Opcode: ADC_rrr
+/* 590 */     MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 599
+/* 595 */     MCD_OPC_Decode, 156, 2, 43, // Opcode: ADC_f_rrr
+/* 599 */     MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 608
+/* 604 */     MCD_OPC_Decode, 194, 5, 43, // Opcode: SUB_rrr
+/* 608 */     MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 617
+/* 613 */     MCD_OPC_Decode, 190, 5, 43, // Opcode: SUB_f_rrr
+/* 617 */     MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 626
+/* 622 */     MCD_OPC_Decode, 230, 4, 43, // Opcode: SBC_rrr
+/* 626 */     MCD_OPC_FilterValue, 7, 4, 0, 0, // Skip to: 635
+/* 631 */     MCD_OPC_Decode, 226, 4, 43, // Opcode: SBC_f_rrr
+/* 635 */     MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 644
+/* 640 */     MCD_OPC_Decode, 188, 2, 43, // Opcode: AND_rrr
+/* 644 */     MCD_OPC_FilterValue, 9, 4, 0, 0, // Skip to: 653
+/* 649 */     MCD_OPC_Decode, 184, 2, 43, // Opcode: AND_f_rrr
+/* 653 */     MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 662
+/* 658 */     MCD_OPC_Decode, 195, 4, 43, // Opcode: OR_rrr
+/* 662 */     MCD_OPC_FilterValue, 11, 4, 0, 0, // Skip to: 671
+/* 667 */     MCD_OPC_Decode, 191, 4, 43, // Opcode: OR_f_rrr
+/* 671 */     MCD_OPC_FilterValue, 14, 4, 0, 0, // Skip to: 680
+/* 676 */     MCD_OPC_Decode, 204, 5, 43, // Opcode: XOR_rrr
+/* 680 */     MCD_OPC_FilterValue, 15, 4, 0, 0, // Skip to: 689
+/* 685 */     MCD_OPC_Decode, 200, 5, 43, // Opcode: XOR_f_rrr
+/* 689 */     MCD_OPC_FilterValue, 16, 4, 0, 0, // Skip to: 698
+/* 694 */     MCD_OPC_Decode, 128, 4, 43, // Opcode: MAX_rrr
+/* 698 */     MCD_OPC_FilterValue, 17, 4, 0, 0, // Skip to: 707
+/* 703 */     MCD_OPC_Decode, 252, 3, 43, // Opcode: MAX_f_rrr
+/* 707 */     MCD_OPC_FilterValue, 18, 4, 0, 0, // Skip to: 716
+/* 712 */     MCD_OPC_Decode, 138, 4, 43, // Opcode: MIN_rrr
+/* 716 */     MCD_OPC_FilterValue, 19, 4, 0, 0, // Skip to: 725
+/* 721 */     MCD_OPC_Decode, 134, 4, 43, // Opcode: MIN_f_rrr
+/* 725 */     MCD_OPC_FilterValue, 20, 4, 0, 0, // Skip to: 734
+/* 730 */     MCD_OPC_Decode, 151, 4, 44, // Opcode: MOV_rr
+/* 734 */     MCD_OPC_FilterValue, 25, 4, 0, 0, // Skip to: 743
+/* 739 */     MCD_OPC_Decode, 244, 2, 44, // Opcode: CMP_rr
+/* 743 */     MCD_OPC_FilterValue, 28, 4, 0, 0, // Skip to: 752
+/* 748 */     MCD_OPC_Decode, 220, 4, 43, // Opcode: RSUB_rrr
+/* 752 */     MCD_OPC_FilterValue, 29, 4, 0, 0, // Skip to: 761
+/* 757 */     MCD_OPC_Decode, 216, 4, 43, // Opcode: RSUB_f_rrr
+/* 761 */     MCD_OPC_FilterValue, 46, 4, 0, 0, // Skip to: 770
+/* 766 */     MCD_OPC_Decode, 161, 5, 43, // Opcode: SUB1_rrr
+/* 770 */     MCD_OPC_FilterValue, 47, 4, 0, 0, // Skip to: 779
+/* 775 */     MCD_OPC_Decode, 157, 5, 43, // Opcode: SUB1_f_rrr
+/* 779 */     MCD_OPC_FilterValue, 48, 4, 0, 0, // Skip to: 788
+/* 784 */     MCD_OPC_Decode, 171, 5, 43, // Opcode: SUB2_rrr
+/* 788 */     MCD_OPC_FilterValue, 49, 4, 0, 0, // Skip to: 797
+/* 793 */     MCD_OPC_Decode, 167, 5, 43, // Opcode: SUB2_f_rrr
+/* 797 */     MCD_OPC_FilterValue, 50, 4, 0, 0, // Skip to: 806
+/* 802 */     MCD_OPC_Decode, 181, 5, 43, // Opcode: SUB3_rrr
+/* 806 */     MCD_OPC_FilterValue, 51, 4, 0, 0, // Skip to: 815
+/* 811 */     MCD_OPC_Decode, 177, 5, 43, // Opcode: SUB3_f_rrr
+/* 815 */     MCD_OPC_FilterValue, 52, 4, 0, 0, // Skip to: 824
+/* 820 */     MCD_OPC_Decode, 181, 4, 43, // Opcode: MPY_rrr
+/* 824 */     MCD_OPC_FilterValue, 53, 4, 0, 0, // Skip to: 833
+/* 829 */     MCD_OPC_Decode, 177, 4, 43, // Opcode: MPY_f_rrr
+/* 833 */     MCD_OPC_FilterValue, 54, 4, 0, 0, // Skip to: 842
+/* 838 */     MCD_OPC_Decode, 171, 4, 43, // Opcode: MPYM_rrr
+/* 842 */     MCD_OPC_FilterValue, 55, 4, 0, 0, // Skip to: 851
+/* 847 */     MCD_OPC_Decode, 167, 4, 43, // Opcode: MPYM_f_rrr
+/* 851 */     MCD_OPC_FilterValue, 56, 4, 0, 0, // Skip to: 860
+/* 856 */     MCD_OPC_Decode, 161, 4, 43, // Opcode: MPYMU_rrr
+/* 860 */     MCD_OPC_FilterValue, 57, 4, 0, 0, // Skip to: 869
+/* 865 */     MCD_OPC_Decode, 157, 4, 43, // Opcode: MPYMU_f_rrr
+/* 869 */     MCD_OPC_FilterValue, 64, 4, 0, 0, // Skip to: 878
+/* 874 */     MCD_OPC_Decode, 169, 3, 45, // Opcode: J
+/* 878 */     MCD_OPC_FilterValue, 68, 4, 0, 0, // Skip to: 887
+/* 883 */     MCD_OPC_Decode, 170, 3, 45, // Opcode: JL
+/* 887 */     MCD_OPC_FilterValue, 94, 21, 0, 0, // Skip to: 913
+/* 892 */     MCD_OPC_ExtractField, 0, 6,  // Inst{5-0} ...
+/* 895 */     MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 904
+/* 900 */     MCD_OPC_Decode, 244, 4, 44, // Opcode: SEXB_rr
+/* 904 */     MCD_OPC_FilterValue, 6, 89, 7, 0, // Skip to: 2790
+/* 909 */     MCD_OPC_Decode, 246, 4, 44, // Opcode: SEXH_rr
+/* 913 */     MCD_OPC_FilterValue, 95, 21, 0, 0, // Skip to: 939
+/* 918 */     MCD_OPC_ExtractField, 0, 6,  // Inst{5-0} ...
+/* 921 */     MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 930
+/* 926 */     MCD_OPC_Decode, 243, 4, 44, // Opcode: SEXB_f_rr
+/* 930 */     MCD_OPC_FilterValue, 6, 63, 7, 0, // Skip to: 2790
+/* 935 */     MCD_OPC_Decode, 245, 4, 44, // Opcode: SEXH_f_rr
+/* 939 */     MCD_OPC_FilterValue, 112, 4, 0, 0, // Skip to: 948
+/* 944 */     MCD_OPC_Decode, 240, 4, 43, // Opcode: SETEQ_rrr
+/* 948 */     MCD_OPC_FilterValue, 113, 4, 0, 0, // Skip to: 957
+/* 953 */     MCD_OPC_Decode, 236, 4, 43, // Opcode: SETEQ_f_rrr
+/* 957 */     MCD_OPC_FilterValue, 128, 1, 4, 0, 0, // Skip to: 967
+/* 963 */     MCD_OPC_Decode, 180, 2, 46, // Opcode: ADD_rru6
+/* 967 */     MCD_OPC_FilterValue, 129, 1, 4, 0, 0, // Skip to: 977
+/* 973 */     MCD_OPC_Decode, 176, 2, 46, // Opcode: ADD_f_rru6
+/* 977 */     MCD_OPC_FilterValue, 130, 1, 4, 0, 0, // Skip to: 987
+/* 983 */     MCD_OPC_Decode, 162, 2, 46, // Opcode: ADC_rru6
+/* 987 */     MCD_OPC_FilterValue, 131, 1, 4, 0, 0, // Skip to: 997
+/* 993 */     MCD_OPC_Decode, 158, 2, 46, // Opcode: ADC_f_rru6
+/* 997 */     MCD_OPC_FilterValue, 132, 1, 4, 0, 0, // Skip to: 1007
+/* 1003 */    MCD_OPC_Decode, 196, 5, 46, // Opcode: SUB_rru6
+/* 1007 */    MCD_OPC_FilterValue, 133, 1, 4, 0, 0, // Skip to: 1017
+/* 1013 */    MCD_OPC_Decode, 192, 5, 46, // Opcode: SUB_f_rru6
+/* 1017 */    MCD_OPC_FilterValue, 134, 1, 4, 0, 0, // Skip to: 1027
+/* 1023 */    MCD_OPC_Decode, 232, 4, 46, // Opcode: SBC_rru6
+/* 1027 */    MCD_OPC_FilterValue, 135, 1, 4, 0, 0, // Skip to: 1037
+/* 1033 */    MCD_OPC_Decode, 228, 4, 46, // Opcode: SBC_f_rru6
+/* 1037 */    MCD_OPC_FilterValue, 136, 1, 4, 0, 0, // Skip to: 1047
+/* 1043 */    MCD_OPC_Decode, 190, 2, 46, // Opcode: AND_rru6
+/* 1047 */    MCD_OPC_FilterValue, 137, 1, 4, 0, 0, // Skip to: 1057
+/* 1053 */    MCD_OPC_Decode, 186, 2, 46, // Opcode: AND_f_rru6
+/* 1057 */    MCD_OPC_FilterValue, 138, 1, 4, 0, 0, // Skip to: 1067
+/* 1063 */    MCD_OPC_Decode, 197, 4, 46, // Opcode: OR_rru6
+/* 1067 */    MCD_OPC_FilterValue, 139, 1, 4, 0, 0, // Skip to: 1077
+/* 1073 */    MCD_OPC_Decode, 193, 4, 46, // Opcode: OR_f_rru6
+/* 1077 */    MCD_OPC_FilterValue, 142, 1, 4, 0, 0, // Skip to: 1087
+/* 1083 */    MCD_OPC_Decode, 206, 5, 46, // Opcode: XOR_rru6
+/* 1087 */    MCD_OPC_FilterValue, 143, 1, 4, 0, 0, // Skip to: 1097
+/* 1093 */    MCD_OPC_Decode, 202, 5, 46, // Opcode: XOR_f_rru6
+/* 1097 */    MCD_OPC_FilterValue, 144, 1, 4, 0, 0, // Skip to: 1107
+/* 1103 */    MCD_OPC_Decode, 130, 4, 46, // Opcode: MAX_rru6
+/* 1107 */    MCD_OPC_FilterValue, 145, 1, 4, 0, 0, // Skip to: 1117
+/* 1113 */    MCD_OPC_Decode, 254, 3, 46, // Opcode: MAX_f_rru6
+/* 1117 */    MCD_OPC_FilterValue, 146, 1, 4, 0, 0, // Skip to: 1127
+/* 1123 */    MCD_OPC_Decode, 140, 4, 46, // Opcode: MIN_rru6
+/* 1127 */    MCD_OPC_FilterValue, 147, 1, 4, 0, 0, // Skip to: 1137
+/* 1133 */    MCD_OPC_Decode, 136, 4, 46, // Opcode: MIN_f_rru6
+/* 1137 */    MCD_OPC_FilterValue, 148, 1, 4, 0, 0, // Skip to: 1147
+/* 1143 */    MCD_OPC_Decode, 153, 4, 47, // Opcode: MOV_ru6
+/* 1147 */    MCD_OPC_FilterValue, 149, 1, 4, 0, 0, // Skip to: 1157
+/* 1153 */    MCD_OPC_Decode, 149, 4, 47, // Opcode: MOV_f_ru6
+/* 1157 */    MCD_OPC_FilterValue, 153, 1, 4, 0, 0, // Skip to: 1167
+/* 1163 */    MCD_OPC_Decode, 245, 2, 47, // Opcode: CMP_ru6
+/* 1167 */    MCD_OPC_FilterValue, 156, 1, 4, 0, 0, // Skip to: 1177
+/* 1173 */    MCD_OPC_Decode, 222, 4, 46, // Opcode: RSUB_rru6
+/* 1177 */    MCD_OPC_FilterValue, 157, 1, 4, 0, 0, // Skip to: 1187
+/* 1183 */    MCD_OPC_Decode, 218, 4, 46, // Opcode: RSUB_f_rru6
+/* 1187 */    MCD_OPC_FilterValue, 174, 1, 4, 0, 0, // Skip to: 1197
+/* 1193 */    MCD_OPC_Decode, 163, 5, 46, // Opcode: SUB1_rru6
+/* 1197 */    MCD_OPC_FilterValue, 175, 1, 4, 0, 0, // Skip to: 1207
+/* 1203 */    MCD_OPC_Decode, 159, 5, 46, // Opcode: SUB1_f_rru6
+/* 1207 */    MCD_OPC_FilterValue, 176, 1, 4, 0, 0, // Skip to: 1217
+/* 1213 */    MCD_OPC_Decode, 173, 5, 46, // Opcode: SUB2_rru6
+/* 1217 */    MCD_OPC_FilterValue, 177, 1, 4, 0, 0, // Skip to: 1227
+/* 1223 */    MCD_OPC_Decode, 169, 5, 46, // Opcode: SUB2_f_rru6
+/* 1227 */    MCD_OPC_FilterValue, 178, 1, 4, 0, 0, // Skip to: 1237
+/* 1233 */    MCD_OPC_Decode, 183, 5, 46, // Opcode: SUB3_rru6
+/* 1237 */    MCD_OPC_FilterValue, 179, 1, 4, 0, 0, // Skip to: 1247
+/* 1243 */    MCD_OPC_Decode, 179, 5, 46, // Opcode: SUB3_f_rru6
+/* 1247 */    MCD_OPC_FilterValue, 180, 1, 4, 0, 0, // Skip to: 1257
+/* 1253 */    MCD_OPC_Decode, 183, 4, 46, // Opcode: MPY_rru6
+/* 1257 */    MCD_OPC_FilterValue, 181, 1, 4, 0, 0, // Skip to: 1267
+/* 1263 */    MCD_OPC_Decode, 179, 4, 46, // Opcode: MPY_f_rru6
+/* 1267 */    MCD_OPC_FilterValue, 182, 1, 4, 0, 0, // Skip to: 1277
+/* 1273 */    MCD_OPC_Decode, 173, 4, 46, // Opcode: MPYM_rru6
+/* 1277 */    MCD_OPC_FilterValue, 183, 1, 4, 0, 0, // Skip to: 1287
+/* 1283 */    MCD_OPC_Decode, 169, 4, 46, // Opcode: MPYM_f_rru6
+/* 1287 */    MCD_OPC_FilterValue, 184, 1, 4, 0, 0, // Skip to: 1297
+/* 1293 */    MCD_OPC_Decode, 163, 4, 46, // Opcode: MPYMU_rru6
+/* 1297 */    MCD_OPC_FilterValue, 185, 1, 4, 0, 0, // Skip to: 1307
+/* 1303 */    MCD_OPC_Decode, 159, 4, 46, // Opcode: MPYMU_f_rru6
+/* 1307 */    MCD_OPC_FilterValue, 212, 1, 11, 0, 0, // Skip to: 1324
+/* 1313 */    MCD_OPC_CheckField, 0, 6, 0, 190, 5, 0, // Skip to: 2790
+/* 1320 */    MCD_OPC_Decode, 237, 3, 48, // Opcode: LR_ru6
+/* 1324 */    MCD_OPC_FilterValue, 240, 1, 4, 0, 0, // Skip to: 1334
+/* 1330 */    MCD_OPC_Decode, 242, 4, 46, // Opcode: SETEQ_rru6
+/* 1334 */    MCD_OPC_FilterValue, 241, 1, 4, 0, 0, // Skip to: 1344
+/* 1340 */    MCD_OPC_Decode, 238, 4, 46, // Opcode: SETEQ_f_rru6
+/* 1344 */    MCD_OPC_FilterValue, 128, 2, 4, 0, 0, // Skip to: 1354
+/* 1350 */    MCD_OPC_Decode, 179, 2, 49, // Opcode: ADD_rrs12
+/* 1354 */    MCD_OPC_FilterValue, 129, 2, 4, 0, 0, // Skip to: 1364
+/* 1360 */    MCD_OPC_Decode, 175, 2, 49, // Opcode: ADD_f_rrs12
+/* 1364 */    MCD_OPC_FilterValue, 130, 2, 4, 0, 0, // Skip to: 1374
+/* 1370 */    MCD_OPC_Decode, 161, 2, 49, // Opcode: ADC_rrs12
+/* 1374 */    MCD_OPC_FilterValue, 131, 2, 4, 0, 0, // Skip to: 1384
+/* 1380 */    MCD_OPC_Decode, 157, 2, 49, // Opcode: ADC_f_rrs12
+/* 1384 */    MCD_OPC_FilterValue, 132, 2, 4, 0, 0, // Skip to: 1394
+/* 1390 */    MCD_OPC_Decode, 195, 5, 49, // Opcode: SUB_rrs12
+/* 1394 */    MCD_OPC_FilterValue, 133, 2, 4, 0, 0, // Skip to: 1404
+/* 1400 */    MCD_OPC_Decode, 191, 5, 49, // Opcode: SUB_f_rrs12
+/* 1404 */    MCD_OPC_FilterValue, 134, 2, 4, 0, 0, // Skip to: 1414
+/* 1410 */    MCD_OPC_Decode, 231, 4, 49, // Opcode: SBC_rrs12
+/* 1414 */    MCD_OPC_FilterValue, 135, 2, 4, 0, 0, // Skip to: 1424
+/* 1420 */    MCD_OPC_Decode, 227, 4, 49, // Opcode: SBC_f_rrs12
+/* 1424 */    MCD_OPC_FilterValue, 136, 2, 4, 0, 0, // Skip to: 1434
+/* 1430 */    MCD_OPC_Decode, 189, 2, 49, // Opcode: AND_rrs12
+/* 1434 */    MCD_OPC_FilterValue, 137, 2, 4, 0, 0, // Skip to: 1444
+/* 1440 */    MCD_OPC_Decode, 185, 2, 49, // Opcode: AND_f_rrs12
+/* 1444 */    MCD_OPC_FilterValue, 138, 2, 4, 0, 0, // Skip to: 1454
+/* 1450 */    MCD_OPC_Decode, 196, 4, 49, // Opcode: OR_rrs12
+/* 1454 */    MCD_OPC_FilterValue, 139, 2, 4, 0, 0, // Skip to: 1464
+/* 1460 */    MCD_OPC_Decode, 192, 4, 49, // Opcode: OR_f_rrs12
+/* 1464 */    MCD_OPC_FilterValue, 142, 2, 4, 0, 0, // Skip to: 1474
+/* 1470 */    MCD_OPC_Decode, 205, 5, 49, // Opcode: XOR_rrs12
+/* 1474 */    MCD_OPC_FilterValue, 143, 2, 4, 0, 0, // Skip to: 1484
+/* 1480 */    MCD_OPC_Decode, 201, 5, 49, // Opcode: XOR_f_rrs12
+/* 1484 */    MCD_OPC_FilterValue, 144, 2, 4, 0, 0, // Skip to: 1494
+/* 1490 */    MCD_OPC_Decode, 129, 4, 49, // Opcode: MAX_rrs12
+/* 1494 */    MCD_OPC_FilterValue, 145, 2, 4, 0, 0, // Skip to: 1504
+/* 1500 */    MCD_OPC_Decode, 253, 3, 49, // Opcode: MAX_f_rrs12
+/* 1504 */    MCD_OPC_FilterValue, 146, 2, 4, 0, 0, // Skip to: 1514
+/* 1510 */    MCD_OPC_Decode, 139, 4, 49, // Opcode: MIN_rrs12
+/* 1514 */    MCD_OPC_FilterValue, 147, 2, 4, 0, 0, // Skip to: 1524
+/* 1520 */    MCD_OPC_Decode, 135, 4, 49, // Opcode: MIN_f_rrs12
+/* 1524 */    MCD_OPC_FilterValue, 148, 2, 4, 0, 0, // Skip to: 1534
+/* 1530 */    MCD_OPC_Decode, 152, 4, 50, // Opcode: MOV_rs12
+/* 1534 */    MCD_OPC_FilterValue, 156, 2, 4, 0, 0, // Skip to: 1544
+/* 1540 */    MCD_OPC_Decode, 221, 4, 49, // Opcode: RSUB_rrs12
+/* 1544 */    MCD_OPC_FilterValue, 157, 2, 4, 0, 0, // Skip to: 1554
+/* 1550 */    MCD_OPC_Decode, 217, 4, 49, // Opcode: RSUB_f_rrs12
+/* 1554 */    MCD_OPC_FilterValue, 174, 2, 4, 0, 0, // Skip to: 1564
+/* 1560 */    MCD_OPC_Decode, 162, 5, 49, // Opcode: SUB1_rrs12
+/* 1564 */    MCD_OPC_FilterValue, 175, 2, 4, 0, 0, // Skip to: 1574
+/* 1570 */    MCD_OPC_Decode, 158, 5, 49, // Opcode: SUB1_f_rrs12
+/* 1574 */    MCD_OPC_FilterValue, 176, 2, 4, 0, 0, // Skip to: 1584
+/* 1580 */    MCD_OPC_Decode, 172, 5, 49, // Opcode: SUB2_rrs12
+/* 1584 */    MCD_OPC_FilterValue, 177, 2, 4, 0, 0, // Skip to: 1594
+/* 1590 */    MCD_OPC_Decode, 168, 5, 49, // Opcode: SUB2_f_rrs12
+/* 1594 */    MCD_OPC_FilterValue, 178, 2, 4, 0, 0, // Skip to: 1604
+/* 1600 */    MCD_OPC_Decode, 182, 5, 49, // Opcode: SUB3_rrs12
+/* 1604 */    MCD_OPC_FilterValue, 179, 2, 4, 0, 0, // Skip to: 1614
+/* 1610 */    MCD_OPC_Decode, 178, 5, 49, // Opcode: SUB3_f_rrs12
+/* 1614 */    MCD_OPC_FilterValue, 180, 2, 4, 0, 0, // Skip to: 1624
+/* 1620 */    MCD_OPC_Decode, 182, 4, 49, // Opcode: MPY_rrs12
+/* 1624 */    MCD_OPC_FilterValue, 181, 2, 4, 0, 0, // Skip to: 1634
+/* 1630 */    MCD_OPC_Decode, 178, 4, 49, // Opcode: MPY_f_rrs12
+/* 1634 */    MCD_OPC_FilterValue, 182, 2, 4, 0, 0, // Skip to: 1644
+/* 1640 */    MCD_OPC_Decode, 172, 4, 49, // Opcode: MPYM_rrs12
+/* 1644 */    MCD_OPC_FilterValue, 183, 2, 4, 0, 0, // Skip to: 1654
+/* 1650 */    MCD_OPC_Decode, 168, 4, 49, // Opcode: MPYM_f_rrs12
+/* 1654 */    MCD_OPC_FilterValue, 184, 2, 4, 0, 0, // Skip to: 1664
+/* 1660 */    MCD_OPC_Decode, 162, 4, 49, // Opcode: MPYMU_rrs12
+/* 1664 */    MCD_OPC_FilterValue, 185, 2, 4, 0, 0, // Skip to: 1674
+/* 1670 */    MCD_OPC_Decode, 158, 4, 49, // Opcode: MPYMU_f_rrs12
+/* 1674 */    MCD_OPC_FilterValue, 212, 2, 4, 0, 0, // Skip to: 1684
+/* 1680 */    MCD_OPC_Decode, 236, 3, 51, // Opcode: LR_rs12
+/* 1684 */    MCD_OPC_FilterValue, 240, 2, 4, 0, 0, // Skip to: 1694
+/* 1690 */    MCD_OPC_Decode, 241, 4, 49, // Opcode: SETEQ_rrs12
+/* 1694 */    MCD_OPC_FilterValue, 241, 2, 4, 0, 0, // Skip to: 1704
+/* 1700 */    MCD_OPC_Decode, 237, 4, 49, // Opcode: SETEQ_f_rrs12
+/* 1704 */    MCD_OPC_FilterValue, 128, 3, 11, 0, 0, // Skip to: 1721
+/* 1710 */    MCD_OPC_CheckField, 5, 1, 1, 49, 4, 0, // Skip to: 2790
+/* 1717 */    MCD_OPC_Decode, 172, 2, 52, // Opcode: ADD_cc_rru6
+/* 1721 */    MCD_OPC_FilterValue, 129, 3, 11, 0, 0, // Skip to: 1738
+/* 1727 */    MCD_OPC_CheckField, 5, 1, 1, 32, 4, 0, // Skip to: 2790
+/* 1734 */    MCD_OPC_Decode, 171, 2, 52, // Opcode: ADD_cc_f_rru6
+/* 1738 */    MCD_OPC_FilterValue, 130, 3, 11, 0, 0, // Skip to: 1755
+/* 1744 */    MCD_OPC_CheckField, 5, 1, 1, 15, 4, 0, // Skip to: 2790
+/* 1751 */    MCD_OPC_Decode, 154, 2, 52, // Opcode: ADC_cc_rru6
+/* 1755 */    MCD_OPC_FilterValue, 131, 3, 11, 0, 0, // Skip to: 1772
+/* 1761 */    MCD_OPC_CheckField, 5, 1, 1, 254, 3, 0, // Skip to: 2790
+/* 1768 */    MCD_OPC_Decode, 153, 2, 52, // Opcode: ADC_cc_f_rru6
+/* 1772 */    MCD_OPC_FilterValue, 132, 3, 11, 0, 0, // Skip to: 1789
+/* 1778 */    MCD_OPC_CheckField, 5, 1, 1, 237, 3, 0, // Skip to: 2790
+/* 1785 */    MCD_OPC_Decode, 188, 5, 52, // Opcode: SUB_cc_rru6
+/* 1789 */    MCD_OPC_FilterValue, 133, 3, 11, 0, 0, // Skip to: 1806
+/* 1795 */    MCD_OPC_CheckField, 5, 1, 1, 220, 3, 0, // Skip to: 2790
+/* 1802 */    MCD_OPC_Decode, 187, 5, 52, // Opcode: SUB_cc_f_rru6
+/* 1806 */    MCD_OPC_FilterValue, 134, 3, 11, 0, 0, // Skip to: 1823
+/* 1812 */    MCD_OPC_CheckField, 5, 1, 1, 203, 3, 0, // Skip to: 2790
+/* 1819 */    MCD_OPC_Decode, 224, 4, 52, // Opcode: SBC_cc_rru6
+/* 1823 */    MCD_OPC_FilterValue, 135, 3, 11, 0, 0, // Skip to: 1840
+/* 1829 */    MCD_OPC_CheckField, 5, 1, 1, 186, 3, 0, // Skip to: 2790
+/* 1836 */    MCD_OPC_Decode, 223, 4, 52, // Opcode: SBC_cc_f_rru6
+/* 1840 */    MCD_OPC_FilterValue, 136, 3, 11, 0, 0, // Skip to: 1857
+/* 1846 */    MCD_OPC_CheckField, 5, 1, 1, 169, 3, 0, // Skip to: 2790
+/* 1853 */    MCD_OPC_Decode, 182, 2, 52, // Opcode: AND_cc_rru6
+/* 1857 */    MCD_OPC_FilterValue, 137, 3, 11, 0, 0, // Skip to: 1874
+/* 1863 */    MCD_OPC_CheckField, 5, 1, 1, 152, 3, 0, // Skip to: 2790
+/* 1870 */    MCD_OPC_Decode, 181, 2, 52, // Opcode: AND_cc_f_rru6
+/* 1874 */    MCD_OPC_FilterValue, 138, 3, 11, 0, 0, // Skip to: 1891
+/* 1880 */    MCD_OPC_CheckField, 5, 1, 1, 135, 3, 0, // Skip to: 2790
+/* 1887 */    MCD_OPC_Decode, 189, 4, 52, // Opcode: OR_cc_rru6
+/* 1891 */    MCD_OPC_FilterValue, 139, 3, 11, 0, 0, // Skip to: 1908
+/* 1897 */    MCD_OPC_CheckField, 5, 1, 1, 118, 3, 0, // Skip to: 2790
+/* 1904 */    MCD_OPC_Decode, 188, 4, 52, // Opcode: OR_cc_f_rru6
+/* 1908 */    MCD_OPC_FilterValue, 142, 3, 11, 0, 0, // Skip to: 1925
+/* 1914 */    MCD_OPC_CheckField, 5, 1, 1, 101, 3, 0, // Skip to: 2790
+/* 1921 */    MCD_OPC_Decode, 198, 5, 52, // Opcode: XOR_cc_rru6
+/* 1925 */    MCD_OPC_FilterValue, 143, 3, 11, 0, 0, // Skip to: 1942
+/* 1931 */    MCD_OPC_CheckField, 5, 1, 1, 84, 3, 0, // Skip to: 2790
+/* 1938 */    MCD_OPC_Decode, 197, 5, 52, // Opcode: XOR_cc_f_rru6
+/* 1942 */    MCD_OPC_FilterValue, 144, 3, 11, 0, 0, // Skip to: 1959
+/* 1948 */    MCD_OPC_CheckField, 5, 1, 1, 67, 3, 0, // Skip to: 2790
+/* 1955 */    MCD_OPC_Decode, 250, 3, 52, // Opcode: MAX_cc_rru6
+/* 1959 */    MCD_OPC_FilterValue, 145, 3, 11, 0, 0, // Skip to: 1976
+/* 1965 */    MCD_OPC_CheckField, 5, 1, 1, 50, 3, 0, // Skip to: 2790
+/* 1972 */    MCD_OPC_Decode, 249, 3, 52, // Opcode: MAX_cc_f_rru6
+/* 1976 */    MCD_OPC_FilterValue, 146, 3, 11, 0, 0, // Skip to: 1993
+/* 1982 */    MCD_OPC_CheckField, 5, 1, 1, 33, 3, 0, // Skip to: 2790
+/* 1989 */    MCD_OPC_Decode, 132, 4, 52, // Opcode: MIN_cc_rru6
+/* 1993 */    MCD_OPC_FilterValue, 147, 3, 11, 0, 0, // Skip to: 2010
+/* 1999 */    MCD_OPC_CheckField, 5, 1, 1, 16, 3, 0, // Skip to: 2790
+/* 2006 */    MCD_OPC_Decode, 131, 4, 52, // Opcode: MIN_cc_f_rru6
+/* 2010 */    MCD_OPC_FilterValue, 148, 3, 21, 0, 0, // Skip to: 2037
+/* 2016 */    MCD_OPC_ExtractField, 5, 1,  // Inst{5} ...
+/* 2019 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2028
+/* 2024 */    MCD_OPC_Decode, 146, 4, 53, // Opcode: MOV_cc
+/* 2028 */    MCD_OPC_FilterValue, 1, 245, 2, 0, // Skip to: 2790
+/* 2033 */    MCD_OPC_Decode, 148, 4, 54, // Opcode: MOV_cc_ru6
+/* 2037 */    MCD_OPC_FilterValue, 149, 3, 11, 0, 0, // Skip to: 2054
+/* 2043 */    MCD_OPC_CheckField, 5, 1, 1, 228, 2, 0, // Skip to: 2790
+/* 2050 */    MCD_OPC_Decode, 147, 4, 54, // Opcode: MOV_cc_f_ru6
+/* 2054 */    MCD_OPC_FilterValue, 156, 3, 11, 0, 0, // Skip to: 2071
+/* 2060 */    MCD_OPC_CheckField, 5, 1, 1, 211, 2, 0, // Skip to: 2790
+/* 2067 */    MCD_OPC_Decode, 214, 4, 52, // Opcode: RSUB_cc_rru6
+/* 2071 */    MCD_OPC_FilterValue, 157, 3, 11, 0, 0, // Skip to: 2088
+/* 2077 */    MCD_OPC_CheckField, 5, 1, 1, 194, 2, 0, // Skip to: 2790
+/* 2084 */    MCD_OPC_Decode, 213, 4, 52, // Opcode: RSUB_cc_f_rru6
+/* 2088 */    MCD_OPC_FilterValue, 174, 3, 11, 0, 0, // Skip to: 2105
+/* 2094 */    MCD_OPC_CheckField, 5, 1, 1, 177, 2, 0, // Skip to: 2790
+/* 2101 */    MCD_OPC_Decode, 155, 5, 52, // Opcode: SUB1_cc_rru6
+/* 2105 */    MCD_OPC_FilterValue, 175, 3, 11, 0, 0, // Skip to: 2122
+/* 2111 */    MCD_OPC_CheckField, 5, 1, 1, 160, 2, 0, // Skip to: 2790
+/* 2118 */    MCD_OPC_Decode, 154, 5, 52, // Opcode: SUB1_cc_f_rru6
+/* 2122 */    MCD_OPC_FilterValue, 176, 3, 11, 0, 0, // Skip to: 2139
+/* 2128 */    MCD_OPC_CheckField, 5, 1, 1, 143, 2, 0, // Skip to: 2790
+/* 2135 */    MCD_OPC_Decode, 165, 5, 52, // Opcode: SUB2_cc_rru6
+/* 2139 */    MCD_OPC_FilterValue, 177, 3, 11, 0, 0, // Skip to: 2156
+/* 2145 */    MCD_OPC_CheckField, 5, 1, 1, 126, 2, 0, // Skip to: 2790
+/* 2152 */    MCD_OPC_Decode, 164, 5, 52, // Opcode: SUB2_cc_f_rru6
+/* 2156 */    MCD_OPC_FilterValue, 178, 3, 11, 0, 0, // Skip to: 2173
+/* 2162 */    MCD_OPC_CheckField, 5, 1, 1, 109, 2, 0, // Skip to: 2790
+/* 2169 */    MCD_OPC_Decode, 175, 5, 52, // Opcode: SUB3_cc_rru6
+/* 2173 */    MCD_OPC_FilterValue, 179, 3, 11, 0, 0, // Skip to: 2190
+/* 2179 */    MCD_OPC_CheckField, 5, 1, 1, 92, 2, 0, // Skip to: 2790
+/* 2186 */    MCD_OPC_Decode, 174, 5, 52, // Opcode: SUB3_cc_f_rru6
+/* 2190 */    MCD_OPC_FilterValue, 180, 3, 11, 0, 0, // Skip to: 2207
+/* 2196 */    MCD_OPC_CheckField, 5, 1, 1, 75, 2, 0, // Skip to: 2790
+/* 2203 */    MCD_OPC_Decode, 175, 4, 52, // Opcode: MPY_cc_rru6
+/* 2207 */    MCD_OPC_FilterValue, 181, 3, 11, 0, 0, // Skip to: 2224
+/* 2213 */    MCD_OPC_CheckField, 5, 1, 1, 58, 2, 0, // Skip to: 2790
+/* 2220 */    MCD_OPC_Decode, 174, 4, 52, // Opcode: MPY_cc_f_rru6
+/* 2224 */    MCD_OPC_FilterValue, 182, 3, 11, 0, 0, // Skip to: 2241
+/* 2230 */    MCD_OPC_CheckField, 5, 1, 1, 41, 2, 0, // Skip to: 2790
+/* 2237 */    MCD_OPC_Decode, 165, 4, 52, // Opcode: MPYM_cc_rru6
+/* 2241 */    MCD_OPC_FilterValue, 183, 3, 11, 0, 0, // Skip to: 2258
+/* 2247 */    MCD_OPC_CheckField, 5, 1, 1, 24, 2, 0, // Skip to: 2790
+/* 2254 */    MCD_OPC_Decode, 164, 4, 52, // Opcode: MPYM_cc_f_rru6
+/* 2258 */    MCD_OPC_FilterValue, 184, 3, 11, 0, 0, // Skip to: 2275
+/* 2264 */    MCD_OPC_CheckField, 5, 1, 1, 7, 2, 0, // Skip to: 2790
+/* 2271 */    MCD_OPC_Decode, 155, 4, 52, // Opcode: MPYMU_cc_rru6
+/* 2275 */    MCD_OPC_FilterValue, 185, 3, 11, 0, 0, // Skip to: 2292
+/* 2281 */    MCD_OPC_CheckField, 5, 1, 1, 246, 1, 0, // Skip to: 2790
+/* 2288 */    MCD_OPC_Decode, 154, 4, 52, // Opcode: MPYMU_cc_f_rru6
+/* 2292 */    MCD_OPC_FilterValue, 240, 3, 11, 0, 0, // Skip to: 2309
+/* 2298 */    MCD_OPC_CheckField, 5, 1, 1, 229, 1, 0, // Skip to: 2790
+/* 2305 */    MCD_OPC_Decode, 234, 4, 52, // Opcode: SETEQ_cc_rru6
+/* 2309 */    MCD_OPC_FilterValue, 241, 3, 219, 1, 0, // Skip to: 2790
+/* 2315 */    MCD_OPC_CheckField, 5, 1, 1, 212, 1, 0, // Skip to: 2790
+/* 2322 */    MCD_OPC_Decode, 233, 4, 52, // Opcode: SETEQ_cc_f_rru6
+/* 2326 */    MCD_OPC_FilterValue, 5, 203, 1, 0, // Skip to: 2790
+/* 2331 */    MCD_OPC_ExtractField, 15, 9,  // Inst{23-15} ...
+/* 2334 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2343
+/* 2339 */    MCD_OPC_Decode, 200, 2, 43, // Opcode: ASL_rrr
+/* 2343 */    MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 2352
+/* 2348 */    MCD_OPC_Decode, 196, 2, 43, // Opcode: ASL_f_rrr
+/* 2352 */    MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 2361
+/* 2357 */    MCD_OPC_Decode, 246, 3, 43, // Opcode: LSR_rrr
+/* 2361 */    MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 2370
+/* 2366 */    MCD_OPC_Decode, 242, 3, 43, // Opcode: LSR_f_rrr
+/* 2370 */    MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 2379
+/* 2375 */    MCD_OPC_Decode, 212, 2, 43, // Opcode: ASR_rrr
+/* 2379 */    MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 2388
+/* 2384 */    MCD_OPC_Decode, 208, 2, 43, // Opcode: ASR_f_rrr
+/* 2388 */    MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 2397
+/* 2393 */    MCD_OPC_Decode, 210, 4, 43, // Opcode: ROR_rrr
+/* 2397 */    MCD_OPC_FilterValue, 7, 4, 0, 0, // Skip to: 2406
+/* 2402 */    MCD_OPC_Decode, 206, 4, 43, // Opcode: ROR_f_rrr
+/* 2406 */    MCD_OPC_FilterValue, 94, 39, 0, 0, // Skip to: 2450
+/* 2411 */    MCD_OPC_ExtractField, 0, 6,  // Inst{5-0} ...
+/* 2414 */    MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 2423
+/* 2419 */    MCD_OPC_Decode, 187, 4, 44, // Opcode: NORM_rr
+/* 2423 */    MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 2432
+/* 2428 */    MCD_OPC_Decode, 185, 4, 44, // Opcode: NORMH_rr
+/* 2432 */    MCD_OPC_FilterValue, 18, 4, 0, 0, // Skip to: 2441
+/* 2437 */    MCD_OPC_Decode, 252, 2, 44, // Opcode: FFS_rr
+/* 2441 */    MCD_OPC_FilterValue, 19, 88, 1, 0, // Skip to: 2790
+/* 2446 */    MCD_OPC_Decode, 254, 2, 44, // Opcode: FLS_rr
+/* 2450 */    MCD_OPC_FilterValue, 95, 39, 0, 0, // Skip to: 2494
+/* 2455 */    MCD_OPC_ExtractField, 0, 6,  // Inst{5-0} ...
+/* 2458 */    MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 2467
+/* 2463 */    MCD_OPC_Decode, 186, 4, 44, // Opcode: NORM_f_rr
+/* 2467 */    MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 2476
+/* 2472 */    MCD_OPC_Decode, 184, 4, 44, // Opcode: NORMH_f_rr
+/* 2476 */    MCD_OPC_FilterValue, 18, 4, 0, 0, // Skip to: 2485
+/* 2481 */    MCD_OPC_Decode, 251, 2, 44, // Opcode: FFS_f_rr
+/* 2485 */    MCD_OPC_FilterValue, 19, 44, 1, 0, // Skip to: 2790
+/* 2490 */    MCD_OPC_Decode, 253, 2, 44, // Opcode: FLS_f_rr
+/* 2494 */    MCD_OPC_FilterValue, 128, 1, 4, 0, 0, // Skip to: 2504
+/* 2500 */    MCD_OPC_Decode, 202, 2, 46, // Opcode: ASL_rru6
+/* 2504 */    MCD_OPC_FilterValue, 129, 1, 4, 0, 0, // Skip to: 2514
+/* 2510 */    MCD_OPC_Decode, 198, 2, 46, // Opcode: ASL_f_rru6
+/* 2514 */    MCD_OPC_FilterValue, 130, 1, 4, 0, 0, // Skip to: 2524
+/* 2520 */    MCD_OPC_Decode, 248, 3, 46, // Opcode: LSR_rru6
+/* 2524 */    MCD_OPC_FilterValue, 131, 1, 4, 0, 0, // Skip to: 2534
+/* 2530 */    MCD_OPC_Decode, 244, 3, 46, // Opcode: LSR_f_rru6
+/* 2534 */    MCD_OPC_FilterValue, 132, 1, 4, 0, 0, // Skip to: 2544
+/* 2540 */    MCD_OPC_Decode, 214, 2, 46, // Opcode: ASR_rru6
+/* 2544 */    MCD_OPC_FilterValue, 133, 1, 4, 0, 0, // Skip to: 2554
+/* 2550 */    MCD_OPC_Decode, 210, 2, 46, // Opcode: ASR_f_rru6
+/* 2554 */    MCD_OPC_FilterValue, 134, 1, 4, 0, 0, // Skip to: 2564
+/* 2560 */    MCD_OPC_Decode, 212, 4, 46, // Opcode: ROR_rru6
+/* 2564 */    MCD_OPC_FilterValue, 135, 1, 4, 0, 0, // Skip to: 2574
+/* 2570 */    MCD_OPC_Decode, 208, 4, 46, // Opcode: ROR_f_rru6
+/* 2574 */    MCD_OPC_FilterValue, 128, 2, 4, 0, 0, // Skip to: 2584
+/* 2580 */    MCD_OPC_Decode, 201, 2, 49, // Opcode: ASL_rrs12
+/* 2584 */    MCD_OPC_FilterValue, 129, 2, 4, 0, 0, // Skip to: 2594
+/* 2590 */    MCD_OPC_Decode, 197, 2, 49, // Opcode: ASL_f_rrs12
+/* 2594 */    MCD_OPC_FilterValue, 130, 2, 4, 0, 0, // Skip to: 2604
+/* 2600 */    MCD_OPC_Decode, 247, 3, 49, // Opcode: LSR_rrs12
+/* 2604 */    MCD_OPC_FilterValue, 131, 2, 4, 0, 0, // Skip to: 2614
+/* 2610 */    MCD_OPC_Decode, 243, 3, 49, // Opcode: LSR_f_rrs12
+/* 2614 */    MCD_OPC_FilterValue, 132, 2, 4, 0, 0, // Skip to: 2624
+/* 2620 */    MCD_OPC_Decode, 213, 2, 49, // Opcode: ASR_rrs12
+/* 2624 */    MCD_OPC_FilterValue, 133, 2, 4, 0, 0, // Skip to: 2634
+/* 2630 */    MCD_OPC_Decode, 209, 2, 49, // Opcode: ASR_f_rrs12
+/* 2634 */    MCD_OPC_FilterValue, 134, 2, 4, 0, 0, // Skip to: 2644
+/* 2640 */    MCD_OPC_Decode, 211, 4, 49, // Opcode: ROR_rrs12
+/* 2644 */    MCD_OPC_FilterValue, 135, 2, 4, 0, 0, // Skip to: 2654
+/* 2650 */    MCD_OPC_Decode, 207, 4, 49, // Opcode: ROR_f_rrs12
+/* 2654 */    MCD_OPC_FilterValue, 128, 3, 11, 0, 0, // Skip to: 2671
+/* 2660 */    MCD_OPC_CheckField, 5, 1, 1, 123, 0, 0, // Skip to: 2790
+/* 2667 */    MCD_OPC_Decode, 194, 2, 52, // Opcode: ASL_cc_rru6
+/* 2671 */    MCD_OPC_FilterValue, 129, 3, 11, 0, 0, // Skip to: 2688
+/* 2677 */    MCD_OPC_CheckField, 5, 1, 1, 106, 0, 0, // Skip to: 2790
+/* 2684 */    MCD_OPC_Decode, 193, 2, 52, // Opcode: ASL_cc_f_rru6
+/* 2688 */    MCD_OPC_FilterValue, 130, 3, 11, 0, 0, // Skip to: 2705
+/* 2694 */    MCD_OPC_CheckField, 5, 1, 1, 89, 0, 0, // Skip to: 2790
+/* 2701 */    MCD_OPC_Decode, 240, 3, 52, // Opcode: LSR_cc_rru6
+/* 2705 */    MCD_OPC_FilterValue, 131, 3, 11, 0, 0, // Skip to: 2722
+/* 2711 */    MCD_OPC_CheckField, 5, 1, 1, 72, 0, 0, // Skip to: 2790
+/* 2718 */    MCD_OPC_Decode, 239, 3, 52, // Opcode: LSR_cc_f_rru6
+/* 2722 */    MCD_OPC_FilterValue, 132, 3, 11, 0, 0, // Skip to: 2739
+/* 2728 */    MCD_OPC_CheckField, 5, 1, 1, 55, 0, 0, // Skip to: 2790
+/* 2735 */    MCD_OPC_Decode, 206, 2, 52, // Opcode: ASR_cc_rru6
+/* 2739 */    MCD_OPC_FilterValue, 133, 3, 11, 0, 0, // Skip to: 2756
+/* 2745 */    MCD_OPC_CheckField, 5, 1, 1, 38, 0, 0, // Skip to: 2790
+/* 2752 */    MCD_OPC_Decode, 205, 2, 52, // Opcode: ASR_cc_f_rru6
+/* 2756 */    MCD_OPC_FilterValue, 134, 3, 11, 0, 0, // Skip to: 2773
+/* 2762 */    MCD_OPC_CheckField, 5, 1, 1, 21, 0, 0, // Skip to: 2790
+/* 2769 */    MCD_OPC_Decode, 204, 4, 52, // Opcode: ROR_cc_rru6
+/* 2773 */    MCD_OPC_FilterValue, 135, 3, 11, 0, 0, // Skip to: 2790
+/* 2779 */    MCD_OPC_CheckField, 5, 1, 1, 4, 0, 0, // Skip to: 2790
+/* 2786 */    MCD_OPC_Decode, 203, 4, 52, // Opcode: ROR_cc_f_rru6
+/* 2790 */    MCD_OPC_Fail,
+  0
+};
+
+static const uint8_t DecoderTable48[] = {
+/* 0 */       MCD_OPC_ExtractField, 0, 3,  // Inst{2-0} ...
+/* 3 */       MCD_OPC_FilterValue, 3, 45, 0, 0, // Skip to: 53
+/* 8 */       MCD_OPC_ExtractField, 11, 5,  // Inst{15-11} ...
+/* 11 */      MCD_OPC_FilterValue, 8, 11, 0, 0, // Skip to: 27
+/* 16 */      MCD_OPC_CheckField, 5, 3, 6, 86, 0, 0, // Skip to: 109
+/* 23 */      MCD_OPC_Decode, 248, 2, 0, // Opcode: COMPACT_MOV_S_limm
+/* 27 */      MCD_OPC_FilterValue, 14, 77, 0, 0, // Skip to: 109
+/* 32 */      MCD_OPC_ExtractField, 3, 5,  // Inst{7-3} ...
+/* 35 */      MCD_OPC_FilterValue, 24, 4, 0, 0, // Skip to: 44
+/* 40 */      MCD_OPC_Decode, 164, 2, 55, // Opcode: ADD_S_rlimm
+/* 44 */      MCD_OPC_FilterValue, 26, 60, 0, 0, // Skip to: 109
+/* 49 */      MCD_OPC_Decode, 239, 2, 55, // Opcode: CMP_S_rlimm
+/* 53 */      MCD_OPC_FilterValue, 7, 51, 0, 0, // Skip to: 109
+/* 58 */      MCD_OPC_ExtractField, 3, 5,  // Inst{7-3} ...
+/* 61 */      MCD_OPC_FilterValue, 24, 11, 0, 0, // Skip to: 77
+/* 66 */      MCD_OPC_CheckField, 11, 5, 14, 36, 0, 0, // Skip to: 109
+/* 73 */      MCD_OPC_Decode, 163, 2, 56, // Opcode: ADD_S_limms3
+/* 77 */      MCD_OPC_FilterValue, 26, 11, 0, 0, // Skip to: 93
+/* 82 */      MCD_OPC_CheckField, 11, 5, 14, 20, 0, 0, // Skip to: 109
+/* 89 */      MCD_OPC_Decode, 238, 2, 56, // Opcode: CMP_S_limms3
+/* 93 */      MCD_OPC_FilterValue, 27, 11, 0, 0, // Skip to: 109
+/* 98 */      MCD_OPC_CheckField, 11, 5, 14, 4, 0, 0, // Skip to: 109
+/* 105 */     MCD_OPC_Decode, 141, 4, 55, // Opcode: MOV_S_NE_rlimm
+/* 109 */     MCD_OPC_Fail,
+  0
+};
+
+static const uint8_t DecoderTable64[] = {
+/* 0 */       MCD_OPC_ExtractField, 15, 9,  // Inst{23-15} ...
+/* 3 */       MCD_OPC_FilterValue, 0, 103, 1, 0, // Skip to: 367
+/* 8 */       MCD_OPC_ExtractField, 27, 5,  // Inst{31-27} ...
+/* 11 */      MCD_OPC_FilterValue, 2, 173, 0, 0, // Skip to: 189
+/* 16 */      MCD_OPC_ExtractField, 6, 9,  // Inst{14-6} ...
+/* 19 */      MCD_OPC_FilterValue, 192, 3, 11, 0, 0, // Skip to: 36
+/* 25 */      MCD_OPC_CheckField, 24, 3, 6, 255, 5, 0, // Skip to: 1567
+/* 32 */      MCD_OPC_Decode, 232, 3, 57, // Opcode: LD_limm
+/* 36 */      MCD_OPC_FilterValue, 194, 3, 11, 0, 0, // Skip to: 53
+/* 42 */      MCD_OPC_CheckField, 24, 3, 6, 238, 5, 0, // Skip to: 1567
+/* 49 */      MCD_OPC_Decode, 194, 3, 57, // Opcode: LDB_limm
+/* 53 */      MCD_OPC_FilterValue, 195, 3, 11, 0, 0, // Skip to: 70
+/* 59 */      MCD_OPC_CheckField, 24, 3, 6, 221, 5, 0, // Skip to: 1567
+/* 66 */      MCD_OPC_Decode, 191, 3, 57, // Opcode: LDB_X_limm
+/* 70 */      MCD_OPC_FilterValue, 196, 3, 11, 0, 0, // Skip to: 87
+/* 76 */      MCD_OPC_CheckField, 24, 3, 6, 204, 5, 0, // Skip to: 1567
+/* 83 */      MCD_OPC_Decode, 217, 3, 57, // Opcode: LDH_limm
+/* 87 */      MCD_OPC_FilterValue, 197, 3, 11, 0, 0, // Skip to: 104
+/* 93 */      MCD_OPC_CheckField, 24, 3, 6, 187, 5, 0, // Skip to: 1567
+/* 100 */     MCD_OPC_Decode, 214, 3, 57, // Opcode: LDH_X_limm
+/* 104 */     MCD_OPC_FilterValue, 224, 3, 11, 0, 0, // Skip to: 121
+/* 110 */     MCD_OPC_CheckField, 24, 3, 6, 170, 5, 0, // Skip to: 1567
+/* 117 */     MCD_OPC_Decode, 225, 3, 57, // Opcode: LD_DI_limm
+/* 121 */     MCD_OPC_FilterValue, 226, 3, 11, 0, 0, // Skip to: 138
+/* 127 */     MCD_OPC_CheckField, 24, 3, 6, 153, 5, 0, // Skip to: 1567
+/* 134 */     MCD_OPC_Decode, 179, 3, 57, // Opcode: LDB_DI_limm
+/* 138 */     MCD_OPC_FilterValue, 227, 3, 11, 0, 0, // Skip to: 155
+/* 144 */     MCD_OPC_CheckField, 24, 3, 6, 136, 5, 0, // Skip to: 1567
+/* 151 */     MCD_OPC_Decode, 188, 3, 57, // Opcode: LDB_X_DI_limm
+/* 155 */     MCD_OPC_FilterValue, 228, 3, 11, 0, 0, // Skip to: 172
+/* 161 */     MCD_OPC_CheckField, 24, 3, 6, 119, 5, 0, // Skip to: 1567
+/* 168 */     MCD_OPC_Decode, 201, 3, 57, // Opcode: LDH_DI_limm
+/* 172 */     MCD_OPC_FilterValue, 229, 3, 109, 5, 0, // Skip to: 1567
+/* 178 */     MCD_OPC_CheckField, 24, 3, 6, 102, 5, 0, // Skip to: 1567
+/* 185 */     MCD_OPC_Decode, 211, 3, 57, // Opcode: LDH_X_DI_limm
+/* 189 */     MCD_OPC_FilterValue, 3, 141, 0, 0, // Skip to: 335
+/* 194 */     MCD_OPC_ExtractField, 0, 6,  // Inst{5-0} ...
+/* 197 */     MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 220
+/* 202 */     MCD_OPC_CheckField, 24, 3, 6, 78, 5, 0, // Skip to: 1567
+/* 209 */     MCD_OPC_CheckField, 12, 3, 7, 71, 5, 0, // Skip to: 1567
+/* 216 */     MCD_OPC_Decode, 152, 5, 58, // Opcode: ST_limm
+/* 220 */     MCD_OPC_FilterValue, 2, 18, 0, 0, // Skip to: 243
+/* 225 */     MCD_OPC_CheckField, 24, 3, 6, 55, 5, 0, // Skip to: 1567
+/* 232 */     MCD_OPC_CheckField, 12, 3, 7, 48, 5, 0, // Skip to: 1567
+/* 239 */     MCD_OPC_Decode, 133, 5, 58, // Opcode: STB_limm
+/* 243 */     MCD_OPC_FilterValue, 4, 18, 0, 0, // Skip to: 266
+/* 248 */     MCD_OPC_CheckField, 24, 3, 6, 32, 5, 0, // Skip to: 1567
+/* 255 */     MCD_OPC_CheckField, 12, 3, 7, 25, 5, 0, // Skip to: 1567
+/* 262 */     MCD_OPC_Decode, 142, 5, 58, // Opcode: STH_limm
+/* 266 */     MCD_OPC_FilterValue, 32, 18, 0, 0, // Skip to: 289
+/* 271 */     MCD_OPC_CheckField, 24, 3, 6, 9, 5, 0, // Skip to: 1567
+/* 278 */     MCD_OPC_CheckField, 12, 3, 7, 2, 5, 0, // Skip to: 1567
+/* 285 */     MCD_OPC_Decode, 148, 5, 58, // Opcode: ST_DI_limm
+/* 289 */     MCD_OPC_FilterValue, 34, 18, 0, 0, // Skip to: 312
+/* 294 */     MCD_OPC_CheckField, 24, 3, 6, 242, 4, 0, // Skip to: 1567
+/* 301 */     MCD_OPC_CheckField, 12, 3, 7, 235, 4, 0, // Skip to: 1567
+/* 308 */     MCD_OPC_Decode, 130, 5, 58, // Opcode: STB_DI_limm
+/* 312 */     MCD_OPC_FilterValue, 36, 226, 4, 0, // Skip to: 1567
+/* 317 */     MCD_OPC_CheckField, 24, 3, 6, 219, 4, 0, // Skip to: 1567
+/* 324 */     MCD_OPC_CheckField, 12, 3, 7, 212, 4, 0, // Skip to: 1567
+/* 331 */     MCD_OPC_Decode, 139, 5, 58, // Opcode: STH_DI_limm
+/* 335 */     MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 351
+/* 340 */     MCD_OPC_CheckField, 6, 6, 62, 196, 4, 0, // Skip to: 1567
+/* 347 */     MCD_OPC_Decode, 177, 2, 59, // Opcode: ADD_rrlimm
+/* 351 */     MCD_OPC_FilterValue, 5, 187, 4, 0, // Skip to: 1567
+/* 356 */     MCD_OPC_CheckField, 6, 6, 62, 180, 4, 0, // Skip to: 1567
+/* 363 */     MCD_OPC_Decode, 199, 2, 59, // Opcode: ASL_rrlimm
+/* 367 */     MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 407
+/* 372 */     MCD_OPC_ExtractField, 27, 5,  // Inst{31-27} ...
+/* 375 */     MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 391
+/* 380 */     MCD_OPC_CheckField, 6, 6, 62, 156, 4, 0, // Skip to: 1567
+/* 387 */     MCD_OPC_Decode, 173, 2, 59, // Opcode: ADD_f_rrlimm
+/* 391 */     MCD_OPC_FilterValue, 5, 147, 4, 0, // Skip to: 1567
+/* 396 */     MCD_OPC_CheckField, 6, 6, 62, 140, 4, 0, // Skip to: 1567
+/* 403 */     MCD_OPC_Decode, 195, 2, 59, // Opcode: ASL_f_rrlimm
+/* 407 */     MCD_OPC_FilterValue, 2, 35, 0, 0, // Skip to: 447
+/* 412 */     MCD_OPC_ExtractField, 27, 5,  // Inst{31-27} ...
+/* 415 */     MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 431
+/* 420 */     MCD_OPC_CheckField, 6, 6, 62, 116, 4, 0, // Skip to: 1567
+/* 427 */     MCD_OPC_Decode, 159, 2, 59, // Opcode: ADC_rrlimm
+/* 431 */     MCD_OPC_FilterValue, 5, 107, 4, 0, // Skip to: 1567
+/* 436 */     MCD_OPC_CheckField, 6, 6, 62, 100, 4, 0, // Skip to: 1567
+/* 443 */     MCD_OPC_Decode, 245, 3, 59, // Opcode: LSR_rrlimm
+/* 447 */     MCD_OPC_FilterValue, 3, 35, 0, 0, // Skip to: 487
+/* 452 */     MCD_OPC_ExtractField, 27, 5,  // Inst{31-27} ...
+/* 455 */     MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 471
+/* 460 */     MCD_OPC_CheckField, 6, 6, 62, 76, 4, 0, // Skip to: 1567
+/* 467 */     MCD_OPC_Decode, 155, 2, 59, // Opcode: ADC_f_rrlimm
+/* 471 */     MCD_OPC_FilterValue, 5, 67, 4, 0, // Skip to: 1567
+/* 476 */     MCD_OPC_CheckField, 6, 6, 62, 60, 4, 0, // Skip to: 1567
+/* 483 */     MCD_OPC_Decode, 241, 3, 59, // Opcode: LSR_f_rrlimm
+/* 487 */     MCD_OPC_FilterValue, 4, 35, 0, 0, // Skip to: 527
+/* 492 */     MCD_OPC_ExtractField, 27, 5,  // Inst{31-27} ...
+/* 495 */     MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 511
+/* 500 */     MCD_OPC_CheckField, 6, 6, 62, 36, 4, 0, // Skip to: 1567
+/* 507 */     MCD_OPC_Decode, 193, 5, 59, // Opcode: SUB_rrlimm
+/* 511 */     MCD_OPC_FilterValue, 5, 27, 4, 0, // Skip to: 1567
+/* 516 */     MCD_OPC_CheckField, 6, 6, 62, 20, 4, 0, // Skip to: 1567
+/* 523 */     MCD_OPC_Decode, 211, 2, 59, // Opcode: ASR_rrlimm
+/* 527 */     MCD_OPC_FilterValue, 5, 35, 0, 0, // Skip to: 567
+/* 532 */     MCD_OPC_ExtractField, 27, 5,  // Inst{31-27} ...
+/* 535 */     MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 551
+/* 540 */     MCD_OPC_CheckField, 6, 6, 62, 252, 3, 0, // Skip to: 1567
+/* 547 */     MCD_OPC_Decode, 189, 5, 59, // Opcode: SUB_f_rrlimm
+/* 551 */     MCD_OPC_FilterValue, 5, 243, 3, 0, // Skip to: 1567
+/* 556 */     MCD_OPC_CheckField, 6, 6, 62, 236, 3, 0, // Skip to: 1567
+/* 563 */     MCD_OPC_Decode, 207, 2, 59, // Opcode: ASR_f_rrlimm
+/* 567 */     MCD_OPC_FilterValue, 6, 35, 0, 0, // Skip to: 607
+/* 572 */     MCD_OPC_ExtractField, 27, 5,  // Inst{31-27} ...
+/* 575 */     MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 591
+/* 580 */     MCD_OPC_CheckField, 6, 6, 62, 212, 3, 0, // Skip to: 1567
+/* 587 */     MCD_OPC_Decode, 229, 4, 59, // Opcode: SBC_rrlimm
+/* 591 */     MCD_OPC_FilterValue, 5, 203, 3, 0, // Skip to: 1567
+/* 596 */     MCD_OPC_CheckField, 6, 6, 62, 196, 3, 0, // Skip to: 1567
+/* 603 */     MCD_OPC_Decode, 209, 4, 59, // Opcode: ROR_rrlimm
+/* 607 */     MCD_OPC_FilterValue, 7, 35, 0, 0, // Skip to: 647
+/* 612 */     MCD_OPC_ExtractField, 27, 5,  // Inst{31-27} ...
+/* 615 */     MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 631
+/* 620 */     MCD_OPC_CheckField, 6, 6, 62, 172, 3, 0, // Skip to: 1567
+/* 627 */     MCD_OPC_Decode, 225, 4, 59, // Opcode: SBC_f_rrlimm
+/* 631 */     MCD_OPC_FilterValue, 5, 163, 3, 0, // Skip to: 1567
+/* 636 */     MCD_OPC_CheckField, 6, 6, 62, 156, 3, 0, // Skip to: 1567
+/* 643 */     MCD_OPC_Decode, 205, 4, 59, // Opcode: ROR_f_rrlimm
+/* 647 */     MCD_OPC_FilterValue, 8, 18, 0, 0, // Skip to: 670
+/* 652 */     MCD_OPC_CheckField, 27, 5, 4, 140, 3, 0, // Skip to: 1567
+/* 659 */     MCD_OPC_CheckField, 6, 6, 62, 133, 3, 0, // Skip to: 1567
+/* 666 */     MCD_OPC_Decode, 187, 2, 59, // Opcode: AND_rrlimm
+/* 670 */     MCD_OPC_FilterValue, 9, 18, 0, 0, // Skip to: 693
+/* 675 */     MCD_OPC_CheckField, 27, 5, 4, 117, 3, 0, // Skip to: 1567
+/* 682 */     MCD_OPC_CheckField, 6, 6, 62, 110, 3, 0, // Skip to: 1567
+/* 689 */     MCD_OPC_Decode, 183, 2, 59, // Opcode: AND_f_rrlimm
+/* 693 */     MCD_OPC_FilterValue, 10, 18, 0, 0, // Skip to: 716
+/* 698 */     MCD_OPC_CheckField, 27, 5, 4, 94, 3, 0, // Skip to: 1567
+/* 705 */     MCD_OPC_CheckField, 6, 6, 62, 87, 3, 0, // Skip to: 1567
+/* 712 */     MCD_OPC_Decode, 194, 4, 59, // Opcode: OR_rrlimm
+/* 716 */     MCD_OPC_FilterValue, 11, 18, 0, 0, // Skip to: 739
+/* 721 */     MCD_OPC_CheckField, 27, 5, 4, 71, 3, 0, // Skip to: 1567
+/* 728 */     MCD_OPC_CheckField, 6, 6, 62, 64, 3, 0, // Skip to: 1567
+/* 735 */     MCD_OPC_Decode, 190, 4, 59, // Opcode: OR_f_rrlimm
+/* 739 */     MCD_OPC_FilterValue, 14, 18, 0, 0, // Skip to: 762
+/* 744 */     MCD_OPC_CheckField, 27, 5, 4, 48, 3, 0, // Skip to: 1567
+/* 751 */     MCD_OPC_CheckField, 6, 6, 62, 41, 3, 0, // Skip to: 1567
+/* 758 */     MCD_OPC_Decode, 203, 5, 59, // Opcode: XOR_rrlimm
+/* 762 */     MCD_OPC_FilterValue, 15, 18, 0, 0, // Skip to: 785
+/* 767 */     MCD_OPC_CheckField, 27, 5, 4, 25, 3, 0, // Skip to: 1567
+/* 774 */     MCD_OPC_CheckField, 6, 6, 62, 18, 3, 0, // Skip to: 1567
+/* 781 */     MCD_OPC_Decode, 199, 5, 59, // Opcode: XOR_f_rrlimm
+/* 785 */     MCD_OPC_FilterValue, 16, 18, 0, 0, // Skip to: 808
+/* 790 */     MCD_OPC_CheckField, 27, 5, 4, 2, 3, 0, // Skip to: 1567
+/* 797 */     MCD_OPC_CheckField, 6, 6, 62, 251, 2, 0, // Skip to: 1567
+/* 804 */     MCD_OPC_Decode, 255, 3, 59, // Opcode: MAX_rrlimm
+/* 808 */     MCD_OPC_FilterValue, 17, 18, 0, 0, // Skip to: 831
+/* 813 */     MCD_OPC_CheckField, 27, 5, 4, 235, 2, 0, // Skip to: 1567
+/* 820 */     MCD_OPC_CheckField, 6, 6, 62, 228, 2, 0, // Skip to: 1567
+/* 827 */     MCD_OPC_Decode, 251, 3, 59, // Opcode: MAX_f_rrlimm
+/* 831 */     MCD_OPC_FilterValue, 18, 18, 0, 0, // Skip to: 854
+/* 836 */     MCD_OPC_CheckField, 27, 5, 4, 212, 2, 0, // Skip to: 1567
+/* 843 */     MCD_OPC_CheckField, 6, 6, 62, 205, 2, 0, // Skip to: 1567
+/* 850 */     MCD_OPC_Decode, 137, 4, 59, // Opcode: MIN_rrlimm
+/* 854 */     MCD_OPC_FilterValue, 19, 18, 0, 0, // Skip to: 877
+/* 859 */     MCD_OPC_CheckField, 27, 5, 4, 189, 2, 0, // Skip to: 1567
+/* 866 */     MCD_OPC_CheckField, 6, 6, 62, 182, 2, 0, // Skip to: 1567
+/* 873 */     MCD_OPC_Decode, 133, 4, 59, // Opcode: MIN_f_rrlimm
+/* 877 */     MCD_OPC_FilterValue, 20, 18, 0, 0, // Skip to: 900
+/* 882 */     MCD_OPC_CheckField, 27, 5, 4, 166, 2, 0, // Skip to: 1567
+/* 889 */     MCD_OPC_CheckField, 6, 6, 62, 159, 2, 0, // Skip to: 1567
+/* 896 */     MCD_OPC_Decode, 150, 4, 60, // Opcode: MOV_rlimm
+/* 900 */     MCD_OPC_FilterValue, 25, 18, 0, 0, // Skip to: 923
+/* 905 */     MCD_OPC_CheckField, 27, 5, 4, 143, 2, 0, // Skip to: 1567
+/* 912 */     MCD_OPC_CheckField, 6, 6, 62, 136, 2, 0, // Skip to: 1567
+/* 919 */     MCD_OPC_Decode, 243, 2, 60, // Opcode: CMP_rlimm
+/* 923 */     MCD_OPC_FilterValue, 28, 18, 0, 0, // Skip to: 946
+/* 928 */     MCD_OPC_CheckField, 27, 5, 4, 120, 2, 0, // Skip to: 1567
+/* 935 */     MCD_OPC_CheckField, 6, 6, 62, 113, 2, 0, // Skip to: 1567
+/* 942 */     MCD_OPC_Decode, 219, 4, 59, // Opcode: RSUB_rrlimm
+/* 946 */     MCD_OPC_FilterValue, 29, 18, 0, 0, // Skip to: 969
+/* 951 */     MCD_OPC_CheckField, 27, 5, 4, 97, 2, 0, // Skip to: 1567
+/* 958 */     MCD_OPC_CheckField, 6, 6, 62, 90, 2, 0, // Skip to: 1567
+/* 965 */     MCD_OPC_Decode, 215, 4, 59, // Opcode: RSUB_f_rrlimm
+/* 969 */     MCD_OPC_FilterValue, 46, 18, 0, 0, // Skip to: 992
+/* 974 */     MCD_OPC_CheckField, 27, 5, 4, 74, 2, 0, // Skip to: 1567
+/* 981 */     MCD_OPC_CheckField, 6, 6, 62, 67, 2, 0, // Skip to: 1567
+/* 988 */     MCD_OPC_Decode, 160, 5, 59, // Opcode: SUB1_rrlimm
+/* 992 */     MCD_OPC_FilterValue, 47, 18, 0, 0, // Skip to: 1015
+/* 997 */     MCD_OPC_CheckField, 27, 5, 4, 51, 2, 0, // Skip to: 1567
+/* 1004 */    MCD_OPC_CheckField, 6, 6, 62, 44, 2, 0, // Skip to: 1567
+/* 1011 */    MCD_OPC_Decode, 156, 5, 59, // Opcode: SUB1_f_rrlimm
+/* 1015 */    MCD_OPC_FilterValue, 48, 18, 0, 0, // Skip to: 1038
+/* 1020 */    MCD_OPC_CheckField, 27, 5, 4, 28, 2, 0, // Skip to: 1567
+/* 1027 */    MCD_OPC_CheckField, 6, 6, 62, 21, 2, 0, // Skip to: 1567
+/* 1034 */    MCD_OPC_Decode, 170, 5, 59, // Opcode: SUB2_rrlimm
+/* 1038 */    MCD_OPC_FilterValue, 49, 18, 0, 0, // Skip to: 1061
+/* 1043 */    MCD_OPC_CheckField, 27, 5, 4, 5, 2, 0, // Skip to: 1567
+/* 1050 */    MCD_OPC_CheckField, 6, 6, 62, 254, 1, 0, // Skip to: 1567
+/* 1057 */    MCD_OPC_Decode, 166, 5, 59, // Opcode: SUB2_f_rrlimm
+/* 1061 */    MCD_OPC_FilterValue, 50, 18, 0, 0, // Skip to: 1084
+/* 1066 */    MCD_OPC_CheckField, 27, 5, 4, 238, 1, 0, // Skip to: 1567
+/* 1073 */    MCD_OPC_CheckField, 6, 6, 62, 231, 1, 0, // Skip to: 1567
+/* 1080 */    MCD_OPC_Decode, 180, 5, 59, // Opcode: SUB3_rrlimm
+/* 1084 */    MCD_OPC_FilterValue, 51, 18, 0, 0, // Skip to: 1107
+/* 1089 */    MCD_OPC_CheckField, 27, 5, 4, 215, 1, 0, // Skip to: 1567
+/* 1096 */    MCD_OPC_CheckField, 6, 6, 62, 208, 1, 0, // Skip to: 1567
+/* 1103 */    MCD_OPC_Decode, 176, 5, 59, // Opcode: SUB3_f_rrlimm
+/* 1107 */    MCD_OPC_FilterValue, 52, 18, 0, 0, // Skip to: 1130
+/* 1112 */    MCD_OPC_CheckField, 27, 5, 4, 192, 1, 0, // Skip to: 1567
+/* 1119 */    MCD_OPC_CheckField, 6, 6, 62, 185, 1, 0, // Skip to: 1567
+/* 1126 */    MCD_OPC_Decode, 180, 4, 59, // Opcode: MPY_rrlimm
+/* 1130 */    MCD_OPC_FilterValue, 53, 18, 0, 0, // Skip to: 1153
+/* 1135 */    MCD_OPC_CheckField, 27, 5, 4, 169, 1, 0, // Skip to: 1567
+/* 1142 */    MCD_OPC_CheckField, 6, 6, 62, 162, 1, 0, // Skip to: 1567
+/* 1149 */    MCD_OPC_Decode, 176, 4, 59, // Opcode: MPY_f_rrlimm
+/* 1153 */    MCD_OPC_FilterValue, 54, 18, 0, 0, // Skip to: 1176
+/* 1158 */    MCD_OPC_CheckField, 27, 5, 4, 146, 1, 0, // Skip to: 1567
+/* 1165 */    MCD_OPC_CheckField, 6, 6, 62, 139, 1, 0, // Skip to: 1567
+/* 1172 */    MCD_OPC_Decode, 170, 4, 59, // Opcode: MPYM_rrlimm
+/* 1176 */    MCD_OPC_FilterValue, 55, 18, 0, 0, // Skip to: 1199
+/* 1181 */    MCD_OPC_CheckField, 27, 5, 4, 123, 1, 0, // Skip to: 1567
+/* 1188 */    MCD_OPC_CheckField, 6, 6, 62, 116, 1, 0, // Skip to: 1567
+/* 1195 */    MCD_OPC_Decode, 166, 4, 59, // Opcode: MPYM_f_rrlimm
+/* 1199 */    MCD_OPC_FilterValue, 56, 18, 0, 0, // Skip to: 1222
+/* 1204 */    MCD_OPC_CheckField, 27, 5, 4, 100, 1, 0, // Skip to: 1567
+/* 1211 */    MCD_OPC_CheckField, 6, 6, 62, 93, 1, 0, // Skip to: 1567
+/* 1218 */    MCD_OPC_Decode, 160, 4, 59, // Opcode: MPYMU_rrlimm
+/* 1222 */    MCD_OPC_FilterValue, 57, 18, 0, 0, // Skip to: 1245
+/* 1227 */    MCD_OPC_CheckField, 27, 5, 4, 77, 1, 0, // Skip to: 1567
+/* 1234 */    MCD_OPC_CheckField, 6, 6, 62, 70, 1, 0, // Skip to: 1567
+/* 1241 */    MCD_OPC_Decode, 156, 4, 59, // Opcode: MPYMU_f_rrlimm
+/* 1245 */    MCD_OPC_FilterValue, 64, 18, 0, 0, // Skip to: 1268
+/* 1250 */    MCD_OPC_CheckField, 27, 5, 4, 54, 1, 0, // Skip to: 1567
+/* 1257 */    MCD_OPC_CheckField, 6, 6, 62, 47, 1, 0, // Skip to: 1567
+/* 1264 */    MCD_OPC_Decode, 173, 3, 61, // Opcode: J_LImm
+/* 1268 */    MCD_OPC_FilterValue, 68, 18, 0, 0, // Skip to: 1291
+/* 1273 */    MCD_OPC_CheckField, 27, 5, 4, 31, 1, 0, // Skip to: 1567
+/* 1280 */    MCD_OPC_CheckField, 6, 6, 62, 24, 1, 0, // Skip to: 1567
+/* 1287 */    MCD_OPC_Decode, 172, 3, 61, // Opcode: JL_LImm
+/* 1291 */    MCD_OPC_FilterValue, 96, 18, 0, 0, // Skip to: 1314
+/* 1296 */    MCD_OPC_CheckField, 27, 5, 4, 8, 1, 0, // Skip to: 1567
+/* 1303 */    MCD_OPC_CheckField, 6, 6, 62, 1, 1, 0, // Skip to: 1567
+/* 1310 */    MCD_OPC_Decode, 233, 3, 62, // Opcode: LD_rlimm
+/* 1314 */    MCD_OPC_FilterValue, 97, 18, 0, 0, // Skip to: 1337
+/* 1319 */    MCD_OPC_CheckField, 27, 5, 4, 241, 0, 0, // Skip to: 1567
+/* 1326 */    MCD_OPC_CheckField, 6, 6, 62, 234, 0, 0, // Skip to: 1567
+/* 1333 */    MCD_OPC_Decode, 226, 3, 62, // Opcode: LD_DI_rlimm
+/* 1337 */    MCD_OPC_FilterValue, 100, 18, 0, 0, // Skip to: 1360
+/* 1342 */    MCD_OPC_CheckField, 27, 5, 4, 218, 0, 0, // Skip to: 1567
+/* 1349 */    MCD_OPC_CheckField, 6, 6, 62, 211, 0, 0, // Skip to: 1567
+/* 1356 */    MCD_OPC_Decode, 195, 3, 62, // Opcode: LDB_rlimm
+/* 1360 */    MCD_OPC_FilterValue, 101, 18, 0, 0, // Skip to: 1383
+/* 1365 */    MCD_OPC_CheckField, 27, 5, 4, 195, 0, 0, // Skip to: 1567
+/* 1372 */    MCD_OPC_CheckField, 6, 6, 62, 188, 0, 0, // Skip to: 1567
+/* 1379 */    MCD_OPC_Decode, 180, 3, 62, // Opcode: LDB_DI_rlimm
+/* 1383 */    MCD_OPC_FilterValue, 102, 18, 0, 0, // Skip to: 1406
+/* 1388 */    MCD_OPC_CheckField, 27, 5, 4, 172, 0, 0, // Skip to: 1567
+/* 1395 */    MCD_OPC_CheckField, 6, 6, 62, 165, 0, 0, // Skip to: 1567
+/* 1402 */    MCD_OPC_Decode, 192, 3, 62, // Opcode: LDB_X_rlimm
+/* 1406 */    MCD_OPC_FilterValue, 103, 18, 0, 0, // Skip to: 1429
+/* 1411 */    MCD_OPC_CheckField, 27, 5, 4, 149, 0, 0, // Skip to: 1567
+/* 1418 */    MCD_OPC_CheckField, 6, 6, 62, 142, 0, 0, // Skip to: 1567
+/* 1425 */    MCD_OPC_Decode, 189, 3, 62, // Opcode: LDB_X_DI_rlimm
+/* 1429 */    MCD_OPC_FilterValue, 104, 18, 0, 0, // Skip to: 1452
+/* 1434 */    MCD_OPC_CheckField, 27, 5, 4, 126, 0, 0, // Skip to: 1567
+/* 1441 */    MCD_OPC_CheckField, 6, 6, 62, 119, 0, 0, // Skip to: 1567
+/* 1448 */    MCD_OPC_Decode, 218, 3, 62, // Opcode: LDH_rlimm
+/* 1452 */    MCD_OPC_FilterValue, 105, 18, 0, 0, // Skip to: 1475
+/* 1457 */    MCD_OPC_CheckField, 27, 5, 4, 103, 0, 0, // Skip to: 1567
+/* 1464 */    MCD_OPC_CheckField, 6, 6, 62, 96, 0, 0, // Skip to: 1567
+/* 1471 */    MCD_OPC_Decode, 202, 3, 62, // Opcode: LDH_DI_rlimm
+/* 1475 */    MCD_OPC_FilterValue, 106, 18, 0, 0, // Skip to: 1498
+/* 1480 */    MCD_OPC_CheckField, 27, 5, 4, 80, 0, 0, // Skip to: 1567
+/* 1487 */    MCD_OPC_CheckField, 6, 6, 62, 73, 0, 0, // Skip to: 1567
+/* 1494 */    MCD_OPC_Decode, 215, 3, 62, // Opcode: LDH_X_rlimm
+/* 1498 */    MCD_OPC_FilterValue, 107, 18, 0, 0, // Skip to: 1521
+/* 1503 */    MCD_OPC_CheckField, 27, 5, 4, 57, 0, 0, // Skip to: 1567
+/* 1510 */    MCD_OPC_CheckField, 6, 6, 62, 50, 0, 0, // Skip to: 1567
+/* 1517 */    MCD_OPC_Decode, 212, 3, 62, // Opcode: LDH_X_DI_rlimm
+/* 1521 */    MCD_OPC_FilterValue, 112, 18, 0, 0, // Skip to: 1544
+/* 1526 */    MCD_OPC_CheckField, 27, 5, 4, 34, 0, 0, // Skip to: 1567
+/* 1533 */    MCD_OPC_CheckField, 6, 6, 62, 27, 0, 0, // Skip to: 1567
+/* 1540 */    MCD_OPC_Decode, 239, 4, 59, // Opcode: SETEQ_rrlimm
+/* 1544 */    MCD_OPC_FilterValue, 113, 18, 0, 0, // Skip to: 1567
+/* 1549 */    MCD_OPC_CheckField, 27, 5, 4, 11, 0, 0, // Skip to: 1567
+/* 1556 */    MCD_OPC_CheckField, 6, 6, 62, 4, 0, 0, // Skip to: 1567
+/* 1563 */    MCD_OPC_Decode, 235, 4, 59, // Opcode: SETEQ_f_rrlimm
+/* 1567 */    MCD_OPC_Fail,
+  0
+};
+
+static bool checkDecoderPredicate(MCInst *Inst, unsigned Idx) {
+  CS_ASSERT_RET_VAL(0 && "Invalid index!", false);
+}
+
+#define DecodeToMCInst(fname, fieldname, InsnType) \
+static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \
+		uint64_t Address, const void *Decoder, bool *DecodeComplete) \
+{ \
+  *DecodeComplete = true; \
+  InsnType tmp; \
+  switch (Idx) { \
+  default: CS_ASSERT_RET_VAL(0 && "Invalid index!", MCDisassembler_Fail); \
+  case 0: \
+    if (!Check(&S, DecodeMoveHRegInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 1: \
+    tmp = fieldname(insn, 8, 2); \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 2) << 3; \
+    tmp |= fieldname(insn, 5, 3) << 0; \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 3, 2) << 2; \
+    tmp |= fieldname(insn, 10, 1) << 4; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 2: \
+    tmp = fieldname(insn, 0, 3); \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 5, 3); \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 3: \
+    tmp = fieldname(insn, 7, 1); \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 3) << 0; \
+    tmp |= fieldname(insn, 4, 3) << 3; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 4: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 3) << 2; \
+    tmp |= fieldname(insn, 5, 6) << 5; \
+    if (!Check(&S, DecodeSignedOperand_11(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 5: \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 3) << 0; \
+    tmp |= fieldname(insn, 4, 4) << 3; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 6: \
+    tmp = fieldname(insn, 0, 10); \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 7: \
+    tmp = fieldname(insn, 5, 3); \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 0, 3); \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 8: \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 2) << 3; \
+    tmp |= fieldname(insn, 5, 3) << 0; \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 9: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 2) << 3; \
+    tmp |= fieldname(insn, 5, 3) << 0; \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeFromCyclicRange_3(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 10: \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeFromCyclicRange_3(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 11: \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 12: \
+    return S; \
+  case 13: \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 5, 3); \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 14: \
+    tmp = fieldname(insn, 5, 6); \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 15: \
+    tmp = fieldname(insn, 5, 3); \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 0, 5) << 2; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 16: \
+    tmp = fieldname(insn, 5, 3); \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 0, 5); \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 17: \
+    tmp = fieldname(insn, 5, 3); \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 0, 5) << 1; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 18: \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 0, 5); \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 19: \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeGBR32ShortRegister(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 0, 5) << 2; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 20: \
+    tmp = fieldname(insn, 0, 5) << 2; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 21: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 1, 4) << 0; \
+    tmp |= fieldname(insn, 8, 3) << 4; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 22: \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeGBR32ShortRegister(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 23: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 1, 4) << 0; \
+    tmp |= fieldname(insn, 8, 2) << 4; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 24: \
+    tmp = fieldname(insn, 0, 9) << 2; \
+    if (!Check(&S, DecodeSignedOperand_11(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 25: \
+    tmp = fieldname(insn, 0, 9); \
+    if (!Check(&S, DecodeSignedOperand_9(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 26: \
+    tmp = fieldname(insn, 0, 9) << 1; \
+    if (!Check(&S, DecodeSignedOperand_10(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 27: \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 0, 8) << 2; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 28: \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 0, 8); \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 29: \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 0, 7); \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 30: \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 0, 7) << 1; \
+    if (!Check(&S, DecodeBranchTargetS_8(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 31: \
+    tmp = fieldname(insn, 0, 9) << 1; \
+    if (!Check(&S, DecodeBranchTargetS_10(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 32: \
+    tmp = fieldname(insn, 0, 6) << 1; \
+    if (!Check(&S, DecodeBranchTargetS_7(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 33: \
+    tmp = fieldname(insn, 0, 11) << 2; \
+    if (!Check(&S, DecodeBranchTargetS_13(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 34: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 6, 10) << 11; \
+    tmp |= fieldname(insn, 17, 10) << 1; \
+    if (!Check(&S, DecodeBranchTargetS_21(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 0, 5); \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 35: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 21; \
+    tmp |= fieldname(insn, 6, 10) << 11; \
+    tmp |= fieldname(insn, 17, 10) << 1; \
+    if (!Check(&S, DecodeBranchTargetS_25(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 36: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 21; \
+    tmp |= fieldname(insn, 6, 10) << 11; \
+    tmp |= fieldname(insn, 18, 9) << 2; \
+    if (!Check(&S, DecodeBranchTargetS_25(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 37: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 15, 1) << 8; \
+    tmp |= fieldname(insn, 17, 7) << 1; \
+    if (!Check(&S, DecodeBranchTargetS_9(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 3) << 3; \
+    tmp |= fieldname(insn, 24, 3) << 0; \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 6, 6); \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 0, 3); \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 38: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 15, 1) << 8; \
+    tmp |= fieldname(insn, 17, 7) << 1; \
+    if (!Check(&S, DecodeBranchTargetS_9(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 3) << 3; \
+    tmp |= fieldname(insn, 24, 3) << 0; \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 6, 6); \
+    MCOperand_CreateImm0(MI, tmp); \
+    tmp = fieldname(insn, 0, 3); \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 39: \
+    tmp = fieldname(insn, 0, 6); \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 3) << 12; \
+    tmp |= fieldname(insn, 15, 1) << 8; \
+    tmp |= fieldname(insn, 16, 8) << 0; \
+    tmp |= fieldname(insn, 24, 3) << 9; \
+    if (!Check(&S, DecodeMEMrs9(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 40: \
+    tmp = fieldname(insn, 0, 6); \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 3) << 3; \
+    tmp |= fieldname(insn, 24, 3) << 0; \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 3) << 3; \
+    tmp |= fieldname(insn, 24, 3) << 0; \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 15, 1) << 8; \
+    tmp |= fieldname(insn, 16, 8) << 0; \
+    if (!Check(&S, DecodeSignedOperand_9(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 41: \
+    tmp = fieldname(insn, 6, 6); \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 3) << 12; \
+    tmp |= fieldname(insn, 15, 1) << 8; \
+    tmp |= fieldname(insn, 16, 8) << 0; \
+    tmp |= fieldname(insn, 24, 3) << 9; \
+    if (!Check(&S, DecodeMEMrs9(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 42: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 3) << 3; \
+    tmp |= fieldname(insn, 24, 3) << 0; \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 6, 6); \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 3) << 3; \
+    tmp |= fieldname(insn, 24, 3) << 0; \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 15, 1) << 8; \
+    tmp |= fieldname(insn, 16, 8) << 0; \
+    if (!Check(&S, DecodeSignedOperand_9(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 43: \
+    tmp = fieldname(insn, 0, 6); \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 3) << 3; \
+    tmp |= fieldname(insn, 24, 3) << 0; \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 6, 6); \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 44: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 3) << 3; \
+    tmp |= fieldname(insn, 24, 3) << 0; \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 6, 6); \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 45: \
+    tmp = fieldname(insn, 6, 6); \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 46: \
+    tmp = fieldname(insn, 0, 6); \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 3) << 3; \
+    tmp |= fieldname(insn, 24, 3) << 0; \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 6, 6); \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 47: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 3) << 3; \
+    tmp |= fieldname(insn, 24, 3) << 0; \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 6, 6); \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 48: \
+    if (!Check(&S, DecodeSOPwithRU6(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 49: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 3) << 3; \
+    tmp |= fieldname(insn, 24, 3) << 0; \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 3) << 3; \
+    tmp |= fieldname(insn, 24, 3) << 0; \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 6) << 6; \
+    tmp |= fieldname(insn, 6, 6) << 0; \
+    if (!Check(&S, DecodeSignedOperand_12(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 50: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 3) << 3; \
+    tmp |= fieldname(insn, 24, 3) << 0; \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 6) << 6; \
+    tmp |= fieldname(insn, 6, 6) << 0; \
+    if (!Check(&S, DecodeSignedOperand_12(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 51: \
+    if (!Check(&S, DecodeSOPwithRS12(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 52: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 3) << 3; \
+    tmp |= fieldname(insn, 24, 3) << 0; \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 6, 6); \
+    MCOperand_CreateImm0(MI, tmp); \
+    tmp = fieldname(insn, 0, 5); \
+    MCOperand_CreateImm0(MI, tmp); \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 3) << 3; \
+    tmp |= fieldname(insn, 24, 3) << 0; \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 53: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 3) << 3; \
+    tmp |= fieldname(insn, 24, 3) << 0; \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 6, 6); \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 3) << 3; \
+    tmp |= fieldname(insn, 24, 3) << 0; \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 0, 5); \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 54: \
+    if (!Check(&S, DecodeCCRU6Instruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 55: \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 32); \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 56: \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeFromCyclicRange_3(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 32); \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 57: \
+    if (!Check(&S, DecodeLdLImmInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 58: \
+    if (!Check(&S, DecodeStLImmInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 59: \
+    tmp = fieldname(insn, 0, 6); \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 3) << 3; \
+    tmp |= fieldname(insn, 24, 3) << 0; \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 32, 32); \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 60: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 3) << 3; \
+    tmp |= fieldname(insn, 24, 3) << 0; \
+    if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 32, 32); \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 61: \
+    tmp = fieldname(insn, 32, 32); \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 62: \
+    if (!Check(&S, DecodeLdRLImmInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  } \
+}
+
+#define DecodeInstruction(fname, fieldname, decoder, InsnType) \
+static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \
+                                      InsnType insn, uint64_t Address, const void *Decoder) { \
+  const uint8_t *Ptr = DecodeTable; \
+  uint64_t CurFieldValue = 0; \
+  DecodeStatus S = MCDisassembler_Success; \
+  while (true) { \
+    switch (*Ptr) { \
+    default: \
+      return MCDisassembler_Fail; \
+    case MCD_OPC_ExtractField: { \
+      unsigned Start = *++Ptr; \
+      unsigned Len = *++Ptr; \
+      ++Ptr; \
+      CurFieldValue = fieldname(insn, Start, Len); \
+      break; \
+    } \
+    case MCD_OPC_FilterValue: { \
+      /* Decode the field value. */ \
+      unsigned Len; \
+      uint64_t Val = decodeULEB128(++Ptr, &Len); \
+      Ptr += Len; \
+      /* NumToSkip is a plain 24-bit integer. */ \
+      unsigned NumToSkip = *Ptr++; \
+      NumToSkip |= (*Ptr++) << 8; \
+      NumToSkip |= (*Ptr++) << 16; \
+      /* Perform the filter operation. */ \
+      if (Val != CurFieldValue) \
+        Ptr += NumToSkip; \
+      break; \
+    } \
+    case MCD_OPC_CheckField: { \
+      unsigned Start = *++Ptr; \
+      unsigned Len = *++Ptr; \
+      uint64_t FieldValue = fieldname(insn, Start, Len); \
+      /* Decode the field value. */ \
+      unsigned PtrLen = 0; \
+      uint64_t ExpectedValue = decodeULEB128(++Ptr, &PtrLen); \
+      Ptr += PtrLen; \
+      /* NumToSkip is a plain 24-bit integer. */ \
+      unsigned NumToSkip = *Ptr++; \
+      NumToSkip |= (*Ptr++) << 8; \
+      NumToSkip |= (*Ptr++) << 16; \
+      /* If the actual and expected values don't match, skip. */ \
+      if (ExpectedValue != FieldValue) \
+        Ptr += NumToSkip; \
+      break; \
+    } \
+    case MCD_OPC_CheckPredicate: { \
+      unsigned Len; \
+      /* Decode the Predicate Index value. */ \
+      unsigned PIdx = decodeULEB128(++Ptr, &Len); \
+      Ptr += Len; \
+      /* NumToSkip is a plain 24-bit integer. */ \
+      unsigned NumToSkip = *Ptr++; \
+      NumToSkip |= (*Ptr++) << 8; \
+      NumToSkip |= (*Ptr++) << 16; \
+      /* Check the predicate. */ \
+      bool Pred = checkDecoderPredicate(MI, PIdx); \
+      if (!Pred) \
+        Ptr += NumToSkip; \
+      break; \
+    } \
+    case MCD_OPC_Decode: { \
+      unsigned Len; \
+      /* Decode the Opcode value. */ \
+      unsigned Opc = decodeULEB128(++Ptr, &Len); \
+      Ptr += Len; \
+      unsigned DecodeIdx = decodeULEB128(Ptr, &Len); \
+      Ptr += Len; \
+      MCInst_clear(MI); \
+      MCInst_setOpcode(MI, Opc); \
+      bool DecodeComplete; \
+      S = decoder(S, DecodeIdx, insn, MI, Address, Decoder, &DecodeComplete); \
+      return S; \
+    } \
+    case MCD_OPC_TryDecode: { \
+      unsigned Len; \
+      /* Decode the Opcode value. */ \
+      unsigned Opc = decodeULEB128(++Ptr, &Len); \
+      Ptr += Len; \
+      unsigned DecodeIdx = decodeULEB128(Ptr, &Len); \
+      Ptr += Len; \
+      /* NumToSkip is a plain 24-bit integer. */ \
+      unsigned NumToSkip = *Ptr++; \
+      NumToSkip |= (*Ptr++) << 8; \
+      NumToSkip |= (*Ptr++) << 16; \
+      /* Perform the decode operation. */ \
+      MCInst_setOpcode(MI, Opc); \
+      bool DecodeComplete; \
+      S = decoder(S, DecodeIdx, insn, MI, Address, Decoder, &DecodeComplete); \
+      if (DecodeComplete) { \
+        /* Decoding complete. */ \
+        return S; \
+      } else { \
+        /* LLVM uses a MCInst on the stack, but for our use case, */ \
+        /* it is enough for now to reset the op counter. */ \
+        MCInst_clear(MI); \
+        /* If the decoding was incomplete, skip. */ \
+        Ptr += NumToSkip; \
+        /* Reset decode status. This also drops a SoftFail status that could be */ \
+        /* set before the decode attempt. */ \
+        S = MCDisassembler_Success; \
+      } \
+      break; \
+    } \
+    case MCD_OPC_SoftFail: { \
+      /* Decode the mask values. */ \
+      unsigned Len; \
+      uint64_t PositiveMask = decodeULEB128(++Ptr, &Len); \
+      Ptr += Len; \
+      uint64_t NegativeMask = decodeULEB128(Ptr, &Len); \
+      Ptr += Len; \
+      bool Fail = (insn & PositiveMask) != 0 || (~insn & NegativeMask) != 0; \
+      if (Fail) \
+        S = MCDisassembler_SoftFail; \
+      break; \
+    } \
+    case MCD_OPC_Fail: { \
+      return MCDisassembler_Fail; \
+    } \
+    } \
+  } \
+  /* Bogisity detected in disassembler state machine! */ \
+}
+
+FieldFromInstruction(fieldFromInstruction_2, uint16_t)
+DecodeToMCInst(decodeToMCInst_2, fieldFromInstruction_2, uint16_t)
+DecodeInstruction(decodeInstruction_2, fieldFromInstruction_2, decodeToMCInst_2, uint16_t)
+FieldFromInstruction(fieldFromInstruction_4, uint32_t)
+DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint32_t)
+DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4, uint32_t)
+FieldFromInstruction(fieldFromInstruction_8, uint64_t)
+DecodeToMCInst(decodeToMCInst_8, fieldFromInstruction_8, uint64_t)
+DecodeInstruction(decodeInstruction_8, fieldFromInstruction_8, decodeToMCInst_8, uint64_t)
diff --git a/arch/ARC/ARCGenInstrInfo.inc b/arch/ARC/ARCGenInstrInfo.inc
new file mode 100644
index 0000000000..9c593f45cb
--- /dev/null
+++ b/arch/ARC/ARCGenInstrInfo.inc
@@ -0,0 +1,1616 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+#ifdef GET_INSTRINFO_ENUM
+#undef GET_INSTRINFO_ENUM
+
+  enum {
+    ARC_PHI	= 0,
+    ARC_INLINEASM	= 1,
+    ARC_INLINEASM_BR	= 2,
+    ARC_CFI_INSTRUCTION	= 3,
+    ARC_EH_LABEL	= 4,
+    ARC_GC_LABEL	= 5,
+    ARC_ANNOTATION_LABEL	= 6,
+    ARC_KILL	= 7,
+    ARC_EXTRACT_SUBREG	= 8,
+    ARC_INSERT_SUBREG	= 9,
+    ARC_IMPLICIT_DEF	= 10,
+    ARC_SUBREG_TO_REG	= 11,
+    ARC_COPY_TO_REGCLASS	= 12,
+    ARC_DBG_VALUE	= 13,
+    ARC_DBG_VALUE_LIST	= 14,
+    ARC_DBG_INSTR_REF	= 15,
+    ARC_DBG_PHI	= 16,
+    ARC_DBG_LABEL	= 17,
+    ARC_REG_SEQUENCE	= 18,
+    ARC_COPY	= 19,
+    ARC_BUNDLE	= 20,
+    ARC_LIFETIME_START	= 21,
+    ARC_LIFETIME_END	= 22,
+    ARC_PSEUDO_PROBE	= 23,
+    ARC_ARITH_FENCE	= 24,
+    ARC_STACKMAP	= 25,
+    ARC_FENTRY_CALL	= 26,
+    ARC_PATCHPOINT	= 27,
+    ARC_LOAD_STACK_GUARD	= 28,
+    ARC_PREALLOCATED_SETUP	= 29,
+    ARC_PREALLOCATED_ARG	= 30,
+    ARC_STATEPOINT	= 31,
+    ARC_LOCAL_ESCAPE	= 32,
+    ARC_FAULTING_OP	= 33,
+    ARC_PATCHABLE_OP	= 34,
+    ARC_PATCHABLE_FUNCTION_ENTER	= 35,
+    ARC_PATCHABLE_RET	= 36,
+    ARC_PATCHABLE_FUNCTION_EXIT	= 37,
+    ARC_PATCHABLE_TAIL_CALL	= 38,
+    ARC_PATCHABLE_EVENT_CALL	= 39,
+    ARC_PATCHABLE_TYPED_EVENT_CALL	= 40,
+    ARC_ICALL_BRANCH_FUNNEL	= 41,
+    ARC_MEMBARRIER	= 42,
+    ARC_JUMP_TABLE_DEBUG_INFO	= 43,
+    ARC_G_ASSERT_SEXT	= 44,
+    ARC_G_ASSERT_ZEXT	= 45,
+    ARC_G_ASSERT_ALIGN	= 46,
+    ARC_G_ADD	= 47,
+    ARC_G_SUB	= 48,
+    ARC_G_MUL	= 49,
+    ARC_G_SDIV	= 50,
+    ARC_G_UDIV	= 51,
+    ARC_G_SREM	= 52,
+    ARC_G_UREM	= 53,
+    ARC_G_SDIVREM	= 54,
+    ARC_G_UDIVREM	= 55,
+    ARC_G_AND	= 56,
+    ARC_G_OR	= 57,
+    ARC_G_XOR	= 58,
+    ARC_G_IMPLICIT_DEF	= 59,
+    ARC_G_PHI	= 60,
+    ARC_G_FRAME_INDEX	= 61,
+    ARC_G_GLOBAL_VALUE	= 62,
+    ARC_G_CONSTANT_POOL	= 63,
+    ARC_G_EXTRACT	= 64,
+    ARC_G_UNMERGE_VALUES	= 65,
+    ARC_G_INSERT	= 66,
+    ARC_G_MERGE_VALUES	= 67,
+    ARC_G_BUILD_VECTOR	= 68,
+    ARC_G_BUILD_VECTOR_TRUNC	= 69,
+    ARC_G_CONCAT_VECTORS	= 70,
+    ARC_G_PTRTOINT	= 71,
+    ARC_G_INTTOPTR	= 72,
+    ARC_G_BITCAST	= 73,
+    ARC_G_FREEZE	= 74,
+    ARC_G_CONSTANT_FOLD_BARRIER	= 75,
+    ARC_G_INTRINSIC_FPTRUNC_ROUND	= 76,
+    ARC_G_INTRINSIC_TRUNC	= 77,
+    ARC_G_INTRINSIC_ROUND	= 78,
+    ARC_G_INTRINSIC_LRINT	= 79,
+    ARC_G_INTRINSIC_ROUNDEVEN	= 80,
+    ARC_G_READCYCLECOUNTER	= 81,
+    ARC_G_LOAD	= 82,
+    ARC_G_SEXTLOAD	= 83,
+    ARC_G_ZEXTLOAD	= 84,
+    ARC_G_INDEXED_LOAD	= 85,
+    ARC_G_INDEXED_SEXTLOAD	= 86,
+    ARC_G_INDEXED_ZEXTLOAD	= 87,
+    ARC_G_STORE	= 88,
+    ARC_G_INDEXED_STORE	= 89,
+    ARC_G_ATOMIC_CMPXCHG_WITH_SUCCESS	= 90,
+    ARC_G_ATOMIC_CMPXCHG	= 91,
+    ARC_G_ATOMICRMW_XCHG	= 92,
+    ARC_G_ATOMICRMW_ADD	= 93,
+    ARC_G_ATOMICRMW_SUB	= 94,
+    ARC_G_ATOMICRMW_AND	= 95,
+    ARC_G_ATOMICRMW_NAND	= 96,
+    ARC_G_ATOMICRMW_OR	= 97,
+    ARC_G_ATOMICRMW_XOR	= 98,
+    ARC_G_ATOMICRMW_MAX	= 99,
+    ARC_G_ATOMICRMW_MIN	= 100,
+    ARC_G_ATOMICRMW_UMAX	= 101,
+    ARC_G_ATOMICRMW_UMIN	= 102,
+    ARC_G_ATOMICRMW_FADD	= 103,
+    ARC_G_ATOMICRMW_FSUB	= 104,
+    ARC_G_ATOMICRMW_FMAX	= 105,
+    ARC_G_ATOMICRMW_FMIN	= 106,
+    ARC_G_ATOMICRMW_UINC_WRAP	= 107,
+    ARC_G_ATOMICRMW_UDEC_WRAP	= 108,
+    ARC_G_FENCE	= 109,
+    ARC_G_PREFETCH	= 110,
+    ARC_G_BRCOND	= 111,
+    ARC_G_BRINDIRECT	= 112,
+    ARC_G_INVOKE_REGION_START	= 113,
+    ARC_G_INTRINSIC	= 114,
+    ARC_G_INTRINSIC_W_SIDE_EFFECTS	= 115,
+    ARC_G_INTRINSIC_CONVERGENT	= 116,
+    ARC_G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS	= 117,
+    ARC_G_ANYEXT	= 118,
+    ARC_G_TRUNC	= 119,
+    ARC_G_CONSTANT	= 120,
+    ARC_G_FCONSTANT	= 121,
+    ARC_G_VASTART	= 122,
+    ARC_G_VAARG	= 123,
+    ARC_G_SEXT	= 124,
+    ARC_G_SEXT_INREG	= 125,
+    ARC_G_ZEXT	= 126,
+    ARC_G_SHL	= 127,
+    ARC_G_LSHR	= 128,
+    ARC_G_ASHR	= 129,
+    ARC_G_FSHL	= 130,
+    ARC_G_FSHR	= 131,
+    ARC_G_ROTR	= 132,
+    ARC_G_ROTL	= 133,
+    ARC_G_ICMP	= 134,
+    ARC_G_FCMP	= 135,
+    ARC_G_SELECT	= 136,
+    ARC_G_UADDO	= 137,
+    ARC_G_UADDE	= 138,
+    ARC_G_USUBO	= 139,
+    ARC_G_USUBE	= 140,
+    ARC_G_SADDO	= 141,
+    ARC_G_SADDE	= 142,
+    ARC_G_SSUBO	= 143,
+    ARC_G_SSUBE	= 144,
+    ARC_G_UMULO	= 145,
+    ARC_G_SMULO	= 146,
+    ARC_G_UMULH	= 147,
+    ARC_G_SMULH	= 148,
+    ARC_G_UADDSAT	= 149,
+    ARC_G_SADDSAT	= 150,
+    ARC_G_USUBSAT	= 151,
+    ARC_G_SSUBSAT	= 152,
+    ARC_G_USHLSAT	= 153,
+    ARC_G_SSHLSAT	= 154,
+    ARC_G_SMULFIX	= 155,
+    ARC_G_UMULFIX	= 156,
+    ARC_G_SMULFIXSAT	= 157,
+    ARC_G_UMULFIXSAT	= 158,
+    ARC_G_SDIVFIX	= 159,
+    ARC_G_UDIVFIX	= 160,
+    ARC_G_SDIVFIXSAT	= 161,
+    ARC_G_UDIVFIXSAT	= 162,
+    ARC_G_FADD	= 163,
+    ARC_G_FSUB	= 164,
+    ARC_G_FMUL	= 165,
+    ARC_G_FMA	= 166,
+    ARC_G_FMAD	= 167,
+    ARC_G_FDIV	= 168,
+    ARC_G_FREM	= 169,
+    ARC_G_FPOW	= 170,
+    ARC_G_FPOWI	= 171,
+    ARC_G_FEXP	= 172,
+    ARC_G_FEXP2	= 173,
+    ARC_G_FEXP10	= 174,
+    ARC_G_FLOG	= 175,
+    ARC_G_FLOG2	= 176,
+    ARC_G_FLOG10	= 177,
+    ARC_G_FLDEXP	= 178,
+    ARC_G_FFREXP	= 179,
+    ARC_G_FNEG	= 180,
+    ARC_G_FPEXT	= 181,
+    ARC_G_FPTRUNC	= 182,
+    ARC_G_FPTOSI	= 183,
+    ARC_G_FPTOUI	= 184,
+    ARC_G_SITOFP	= 185,
+    ARC_G_UITOFP	= 186,
+    ARC_G_FABS	= 187,
+    ARC_G_FCOPYSIGN	= 188,
+    ARC_G_IS_FPCLASS	= 189,
+    ARC_G_FCANONICALIZE	= 190,
+    ARC_G_FMINNUM	= 191,
+    ARC_G_FMAXNUM	= 192,
+    ARC_G_FMINNUM_IEEE	= 193,
+    ARC_G_FMAXNUM_IEEE	= 194,
+    ARC_G_FMINIMUM	= 195,
+    ARC_G_FMAXIMUM	= 196,
+    ARC_G_GET_FPENV	= 197,
+    ARC_G_SET_FPENV	= 198,
+    ARC_G_RESET_FPENV	= 199,
+    ARC_G_GET_FPMODE	= 200,
+    ARC_G_SET_FPMODE	= 201,
+    ARC_G_RESET_FPMODE	= 202,
+    ARC_G_PTR_ADD	= 203,
+    ARC_G_PTRMASK	= 204,
+    ARC_G_SMIN	= 205,
+    ARC_G_SMAX	= 206,
+    ARC_G_UMIN	= 207,
+    ARC_G_UMAX	= 208,
+    ARC_G_ABS	= 209,
+    ARC_G_LROUND	= 210,
+    ARC_G_LLROUND	= 211,
+    ARC_G_BR	= 212,
+    ARC_G_BRJT	= 213,
+    ARC_G_INSERT_VECTOR_ELT	= 214,
+    ARC_G_EXTRACT_VECTOR_ELT	= 215,
+    ARC_G_SHUFFLE_VECTOR	= 216,
+    ARC_G_CTTZ	= 217,
+    ARC_G_CTTZ_ZERO_UNDEF	= 218,
+    ARC_G_CTLZ	= 219,
+    ARC_G_CTLZ_ZERO_UNDEF	= 220,
+    ARC_G_CTPOP	= 221,
+    ARC_G_BSWAP	= 222,
+    ARC_G_BITREVERSE	= 223,
+    ARC_G_FCEIL	= 224,
+    ARC_G_FCOS	= 225,
+    ARC_G_FSIN	= 226,
+    ARC_G_FSQRT	= 227,
+    ARC_G_FFLOOR	= 228,
+    ARC_G_FRINT	= 229,
+    ARC_G_FNEARBYINT	= 230,
+    ARC_G_ADDRSPACE_CAST	= 231,
+    ARC_G_BLOCK_ADDR	= 232,
+    ARC_G_JUMP_TABLE	= 233,
+    ARC_G_DYN_STACKALLOC	= 234,
+    ARC_G_STACKSAVE	= 235,
+    ARC_G_STACKRESTORE	= 236,
+    ARC_G_STRICT_FADD	= 237,
+    ARC_G_STRICT_FSUB	= 238,
+    ARC_G_STRICT_FMUL	= 239,
+    ARC_G_STRICT_FDIV	= 240,
+    ARC_G_STRICT_FREM	= 241,
+    ARC_G_STRICT_FMA	= 242,
+    ARC_G_STRICT_FSQRT	= 243,
+    ARC_G_STRICT_FLDEXP	= 244,
+    ARC_G_READ_REGISTER	= 245,
+    ARC_G_WRITE_REGISTER	= 246,
+    ARC_G_MEMCPY	= 247,
+    ARC_G_MEMCPY_INLINE	= 248,
+    ARC_G_MEMMOVE	= 249,
+    ARC_G_MEMSET	= 250,
+    ARC_G_BZERO	= 251,
+    ARC_G_VECREDUCE_SEQ_FADD	= 252,
+    ARC_G_VECREDUCE_SEQ_FMUL	= 253,
+    ARC_G_VECREDUCE_FADD	= 254,
+    ARC_G_VECREDUCE_FMUL	= 255,
+    ARC_G_VECREDUCE_FMAX	= 256,
+    ARC_G_VECREDUCE_FMIN	= 257,
+    ARC_G_VECREDUCE_FMAXIMUM	= 258,
+    ARC_G_VECREDUCE_FMINIMUM	= 259,
+    ARC_G_VECREDUCE_ADD	= 260,
+    ARC_G_VECREDUCE_MUL	= 261,
+    ARC_G_VECREDUCE_AND	= 262,
+    ARC_G_VECREDUCE_OR	= 263,
+    ARC_G_VECREDUCE_XOR	= 264,
+    ARC_G_VECREDUCE_SMAX	= 265,
+    ARC_G_VECREDUCE_SMIN	= 266,
+    ARC_G_VECREDUCE_UMAX	= 267,
+    ARC_G_VECREDUCE_UMIN	= 268,
+    ARC_G_SBFX	= 269,
+    ARC_G_UBFX	= 270,
+    ARC_ADJCALLSTACKDOWN	= 271,
+    ARC_ADJCALLSTACKUP	= 272,
+    ARC_BRcc_rr_p	= 273,
+    ARC_BRcc_ru6_p	= 274,
+    ARC_CTLZ	= 275,
+    ARC_CTTZ	= 276,
+    ARC_GETFI	= 277,
+    ARC_STB_FAR	= 278,
+    ARC_STH_FAR	= 279,
+    ARC_ST_FAR	= 280,
+    ARC_ADC_cc_f_rru6	= 281,
+    ARC_ADC_cc_rru6	= 282,
+    ARC_ADC_f_rrlimm	= 283,
+    ARC_ADC_f_rrr	= 284,
+    ARC_ADC_f_rrs12	= 285,
+    ARC_ADC_f_rru6	= 286,
+    ARC_ADC_rrlimm	= 287,
+    ARC_ADC_rrr	= 288,
+    ARC_ADC_rrs12	= 289,
+    ARC_ADC_rru6	= 290,
+    ARC_ADD_S_limms3	= 291,
+    ARC_ADD_S_rlimm	= 292,
+    ARC_ADD_S_rr	= 293,
+    ARC_ADD_S_rrr	= 294,
+    ARC_ADD_S_rru6	= 295,
+    ARC_ADD_S_rs3	= 296,
+    ARC_ADD_S_ru3	= 297,
+    ARC_ADD_S_u7	= 298,
+    ARC_ADD_cc_f_rru6	= 299,
+    ARC_ADD_cc_rru6	= 300,
+    ARC_ADD_f_rrlimm	= 301,
+    ARC_ADD_f_rrr	= 302,
+    ARC_ADD_f_rrs12	= 303,
+    ARC_ADD_f_rru6	= 304,
+    ARC_ADD_rrlimm	= 305,
+    ARC_ADD_rrr	= 306,
+    ARC_ADD_rrs12	= 307,
+    ARC_ADD_rru6	= 308,
+    ARC_AND_cc_f_rru6	= 309,
+    ARC_AND_cc_rru6	= 310,
+    ARC_AND_f_rrlimm	= 311,
+    ARC_AND_f_rrr	= 312,
+    ARC_AND_f_rrs12	= 313,
+    ARC_AND_f_rru6	= 314,
+    ARC_AND_rrlimm	= 315,
+    ARC_AND_rrr	= 316,
+    ARC_AND_rrs12	= 317,
+    ARC_AND_rru6	= 318,
+    ARC_ASL_S_ru3	= 319,
+    ARC_ASL_S_ru5	= 320,
+    ARC_ASL_cc_f_rru6	= 321,
+    ARC_ASL_cc_rru6	= 322,
+    ARC_ASL_f_rrlimm	= 323,
+    ARC_ASL_f_rrr	= 324,
+    ARC_ASL_f_rrs12	= 325,
+    ARC_ASL_f_rru6	= 326,
+    ARC_ASL_rrlimm	= 327,
+    ARC_ASL_rrr	= 328,
+    ARC_ASL_rrs12	= 329,
+    ARC_ASL_rru6	= 330,
+    ARC_ASR_S_ru3	= 331,
+    ARC_ASR_S_ru5	= 332,
+    ARC_ASR_cc_f_rru6	= 333,
+    ARC_ASR_cc_rru6	= 334,
+    ARC_ASR_f_rrlimm	= 335,
+    ARC_ASR_f_rrr	= 336,
+    ARC_ASR_f_rrs12	= 337,
+    ARC_ASR_f_rru6	= 338,
+    ARC_ASR_rrlimm	= 339,
+    ARC_ASR_rrr	= 340,
+    ARC_ASR_rrs12	= 341,
+    ARC_ASR_rru6	= 342,
+    ARC_BCLR_S_ru5	= 343,
+    ARC_BEQ_S	= 344,
+    ARC_BGE_S	= 345,
+    ARC_BGT_S	= 346,
+    ARC_BHI_S	= 347,
+    ARC_BHS_S	= 348,
+    ARC_BL	= 349,
+    ARC_BLE_S	= 350,
+    ARC_BLO_S	= 351,
+    ARC_BLS_S	= 352,
+    ARC_BLT_S	= 353,
+    ARC_BL_S	= 354,
+    ARC_BMSK_S_ru5	= 355,
+    ARC_BNE_S	= 356,
+    ARC_BR	= 357,
+    ARC_BREQ_S	= 358,
+    ARC_BRNE_S	= 359,
+    ARC_BRcc_rr	= 360,
+    ARC_BRcc_ru6	= 361,
+    ARC_BSET_S_ru5	= 362,
+    ARC_BTST_S_ru5	= 363,
+    ARC_B_S	= 364,
+    ARC_Bcc	= 365,
+    ARC_CMP_S_limms3	= 366,
+    ARC_CMP_S_rlimm	= 367,
+    ARC_CMP_S_rr	= 368,
+    ARC_CMP_S_rs3	= 369,
+    ARC_CMP_S_u7	= 370,
+    ARC_CMP_rlimm	= 371,
+    ARC_CMP_rr	= 372,
+    ARC_CMP_ru6	= 373,
+    ARC_COMPACT_LD_S	= 374,
+    ARC_COMPACT_MOV_S_hreg	= 375,
+    ARC_COMPACT_MOV_S_limm	= 376,
+    ARC_EI_S	= 377,
+    ARC_ENTER_S	= 378,
+    ARC_FFS_f_rr	= 379,
+    ARC_FFS_rr	= 380,
+    ARC_FLS_f_rr	= 381,
+    ARC_FLS_rr	= 382,
+    ARC_GEN_ABS_S	= 383,
+    ARC_GEN_ADD1_S	= 384,
+    ARC_GEN_ADD2_S	= 385,
+    ARC_GEN_ADD3_S	= 386,
+    ARC_GEN_AND_S	= 387,
+    ARC_GEN_AS1L_S	= 388,
+    ARC_GEN_AS1R_S	= 389,
+    ARC_GEN_ASL_S	= 390,
+    ARC_GEN_ASR_S	= 391,
+    ARC_GEN_BIC_S	= 392,
+    ARC_GEN_BRK_S	= 393,
+    ARC_GEN_EXTB_S	= 394,
+    ARC_GEN_EXTH_S	= 395,
+    ARC_GEN_JEQ_S	= 396,
+    ARC_GEN_JL_S	= 397,
+    ARC_GEN_JL_S_D	= 398,
+    ARC_GEN_JNE_S	= 399,
+    ARC_GEN_J_S	= 400,
+    ARC_GEN_J_S_D	= 401,
+    ARC_GEN_J_S_D_BLINK	= 402,
+    ARC_GEN_LS1R_S	= 403,
+    ARC_GEN_LSR_S	= 404,
+    ARC_GEN_MPYUW_S	= 405,
+    ARC_GEN_MPYW_S	= 406,
+    ARC_GEN_MPY_S	= 407,
+    ARC_GEN_NEG_S	= 408,
+    ARC_GEN_NOP_S	= 409,
+    ARC_GEN_NOT_S	= 410,
+    ARC_GEN_OR_S	= 411,
+    ARC_GEN_SEXB_S	= 412,
+    ARC_GEN_SEXH_S	= 413,
+    ARC_GEN_SUB_S	= 414,
+    ARC_GEN_SUB_S_NE	= 415,
+    ARC_GEN_SWI_S	= 416,
+    ARC_GEN_TRAP_S	= 417,
+    ARC_GEN_TST_S	= 418,
+    ARC_GEN_UNIMP_S	= 419,
+    ARC_GEN_XOR_S	= 420,
+    ARC_GP_ADD_S	= 421,
+    ARC_GP_LDB_S	= 422,
+    ARC_GP_LDH_S	= 423,
+    ARC_GP_LD_S	= 424,
+    ARC_J	= 425,
+    ARC_JL	= 426,
+    ARC_JLI_S	= 427,
+    ARC_JL_LImm	= 428,
+    ARC_J_LImm	= 429,
+    ARC_J_S_BLINK	= 430,
+    ARC_LDB_AB_rs9	= 431,
+    ARC_LDB_AW_rs9	= 432,
+    ARC_LDB_DI_AB_rs9	= 433,
+    ARC_LDB_DI_AW_rs9	= 434,
+    ARC_LDB_DI_limm	= 435,
+    ARC_LDB_DI_rlimm	= 436,
+    ARC_LDB_DI_rs9	= 437,
+    ARC_LDB_S_OFF	= 438,
+    ARC_LDB_S_rrr	= 439,
+    ARC_LDB_X_AB_rs9	= 440,
+    ARC_LDB_X_AW_rs9	= 441,
+    ARC_LDB_X_DI_AB_rs9	= 442,
+    ARC_LDB_X_DI_AW_rs9	= 443,
+    ARC_LDB_X_DI_limm	= 444,
+    ARC_LDB_X_DI_rlimm	= 445,
+    ARC_LDB_X_DI_rs9	= 446,
+    ARC_LDB_X_limm	= 447,
+    ARC_LDB_X_rlimm	= 448,
+    ARC_LDB_X_rs9	= 449,
+    ARC_LDB_limm	= 450,
+    ARC_LDB_rlimm	= 451,
+    ARC_LDB_rs9	= 452,
+    ARC_LDH_AB_rs9	= 453,
+    ARC_LDH_AW_rs9	= 454,
+    ARC_LDH_DI_AB_rs9	= 455,
+    ARC_LDH_DI_AW_rs9	= 456,
+    ARC_LDH_DI_limm	= 457,
+    ARC_LDH_DI_rlimm	= 458,
+    ARC_LDH_DI_rs9	= 459,
+    ARC_LDH_S_OFF	= 460,
+    ARC_LDH_S_X_OFF	= 461,
+    ARC_LDH_S_rrr	= 462,
+    ARC_LDH_X_AB_rs9	= 463,
+    ARC_LDH_X_AW_rs9	= 464,
+    ARC_LDH_X_DI_AB_rs9	= 465,
+    ARC_LDH_X_DI_AW_rs9	= 466,
+    ARC_LDH_X_DI_limm	= 467,
+    ARC_LDH_X_DI_rlimm	= 468,
+    ARC_LDH_X_DI_rs9	= 469,
+    ARC_LDH_X_limm	= 470,
+    ARC_LDH_X_rlimm	= 471,
+    ARC_LDH_X_rs9	= 472,
+    ARC_LDH_limm	= 473,
+    ARC_LDH_rlimm	= 474,
+    ARC_LDH_rs9	= 475,
+    ARC_LDI_S_u7	= 476,
+    ARC_LD_AB_rs9	= 477,
+    ARC_LD_AW_rs9	= 478,
+    ARC_LD_DI_AB_rs9	= 479,
+    ARC_LD_DI_AW_rs9	= 480,
+    ARC_LD_DI_limm	= 481,
+    ARC_LD_DI_rlimm	= 482,
+    ARC_LD_DI_rs9	= 483,
+    ARC_LD_S_AS_rrr	= 484,
+    ARC_LD_S_OFF	= 485,
+    ARC_LD_S_rrr	= 486,
+    ARC_LD_S_s11	= 487,
+    ARC_LD_limm	= 488,
+    ARC_LD_rlimm	= 489,
+    ARC_LD_rs9	= 490,
+    ARC_LEAVE_S	= 491,
+    ARC_LR_rs12	= 492,
+    ARC_LR_ru6	= 493,
+    ARC_LSR_S_ru5	= 494,
+    ARC_LSR_cc_f_rru6	= 495,
+    ARC_LSR_cc_rru6	= 496,
+    ARC_LSR_f_rrlimm	= 497,
+    ARC_LSR_f_rrr	= 498,
+    ARC_LSR_f_rrs12	= 499,
+    ARC_LSR_f_rru6	= 500,
+    ARC_LSR_rrlimm	= 501,
+    ARC_LSR_rrr	= 502,
+    ARC_LSR_rrs12	= 503,
+    ARC_LSR_rru6	= 504,
+    ARC_MAX_cc_f_rru6	= 505,
+    ARC_MAX_cc_rru6	= 506,
+    ARC_MAX_f_rrlimm	= 507,
+    ARC_MAX_f_rrr	= 508,
+    ARC_MAX_f_rrs12	= 509,
+    ARC_MAX_f_rru6	= 510,
+    ARC_MAX_rrlimm	= 511,
+    ARC_MAX_rrr	= 512,
+    ARC_MAX_rrs12	= 513,
+    ARC_MAX_rru6	= 514,
+    ARC_MIN_cc_f_rru6	= 515,
+    ARC_MIN_cc_rru6	= 516,
+    ARC_MIN_f_rrlimm	= 517,
+    ARC_MIN_f_rrr	= 518,
+    ARC_MIN_f_rrs12	= 519,
+    ARC_MIN_f_rru6	= 520,
+    ARC_MIN_rrlimm	= 521,
+    ARC_MIN_rrr	= 522,
+    ARC_MIN_rrs12	= 523,
+    ARC_MIN_rru6	= 524,
+    ARC_MOV_S_NE_rlimm	= 525,
+    ARC_MOV_S_NE_rr	= 526,
+    ARC_MOV_S_rs3	= 527,
+    ARC_MOV_S_s3	= 528,
+    ARC_MOV_S_u8	= 529,
+    ARC_MOV_cc	= 530,
+    ARC_MOV_cc_f_ru6	= 531,
+    ARC_MOV_cc_ru6	= 532,
+    ARC_MOV_f_ru6	= 533,
+    ARC_MOV_rlimm	= 534,
+    ARC_MOV_rr	= 535,
+    ARC_MOV_rs12	= 536,
+    ARC_MOV_ru6	= 537,
+    ARC_MPYMU_cc_f_rru6	= 538,
+    ARC_MPYMU_cc_rru6	= 539,
+    ARC_MPYMU_f_rrlimm	= 540,
+    ARC_MPYMU_f_rrr	= 541,
+    ARC_MPYMU_f_rrs12	= 542,
+    ARC_MPYMU_f_rru6	= 543,
+    ARC_MPYMU_rrlimm	= 544,
+    ARC_MPYMU_rrr	= 545,
+    ARC_MPYMU_rrs12	= 546,
+    ARC_MPYMU_rru6	= 547,
+    ARC_MPYM_cc_f_rru6	= 548,
+    ARC_MPYM_cc_rru6	= 549,
+    ARC_MPYM_f_rrlimm	= 550,
+    ARC_MPYM_f_rrr	= 551,
+    ARC_MPYM_f_rrs12	= 552,
+    ARC_MPYM_f_rru6	= 553,
+    ARC_MPYM_rrlimm	= 554,
+    ARC_MPYM_rrr	= 555,
+    ARC_MPYM_rrs12	= 556,
+    ARC_MPYM_rru6	= 557,
+    ARC_MPY_cc_f_rru6	= 558,
+    ARC_MPY_cc_rru6	= 559,
+    ARC_MPY_f_rrlimm	= 560,
+    ARC_MPY_f_rrr	= 561,
+    ARC_MPY_f_rrs12	= 562,
+    ARC_MPY_f_rru6	= 563,
+    ARC_MPY_rrlimm	= 564,
+    ARC_MPY_rrr	= 565,
+    ARC_MPY_rrs12	= 566,
+    ARC_MPY_rru6	= 567,
+    ARC_NORMH_f_rr	= 568,
+    ARC_NORMH_rr	= 569,
+    ARC_NORM_f_rr	= 570,
+    ARC_NORM_rr	= 571,
+    ARC_OR_cc_f_rru6	= 572,
+    ARC_OR_cc_rru6	= 573,
+    ARC_OR_f_rrlimm	= 574,
+    ARC_OR_f_rrr	= 575,
+    ARC_OR_f_rrs12	= 576,
+    ARC_OR_f_rru6	= 577,
+    ARC_OR_rrlimm	= 578,
+    ARC_OR_rrr	= 579,
+    ARC_OR_rrs12	= 580,
+    ARC_OR_rru6	= 581,
+    ARC_PCL_LD	= 582,
+    ARC_POP_S_BLINK	= 583,
+    ARC_POP_S_r	= 584,
+    ARC_PUSH_S_BLINK	= 585,
+    ARC_PUSH_S_r	= 586,
+    ARC_ROR_cc_f_rru6	= 587,
+    ARC_ROR_cc_rru6	= 588,
+    ARC_ROR_f_rrlimm	= 589,
+    ARC_ROR_f_rrr	= 590,
+    ARC_ROR_f_rrs12	= 591,
+    ARC_ROR_f_rru6	= 592,
+    ARC_ROR_rrlimm	= 593,
+    ARC_ROR_rrr	= 594,
+    ARC_ROR_rrs12	= 595,
+    ARC_ROR_rru6	= 596,
+    ARC_RSUB_cc_f_rru6	= 597,
+    ARC_RSUB_cc_rru6	= 598,
+    ARC_RSUB_f_rrlimm	= 599,
+    ARC_RSUB_f_rrr	= 600,
+    ARC_RSUB_f_rrs12	= 601,
+    ARC_RSUB_f_rru6	= 602,
+    ARC_RSUB_rrlimm	= 603,
+    ARC_RSUB_rrr	= 604,
+    ARC_RSUB_rrs12	= 605,
+    ARC_RSUB_rru6	= 606,
+    ARC_SBC_cc_f_rru6	= 607,
+    ARC_SBC_cc_rru6	= 608,
+    ARC_SBC_f_rrlimm	= 609,
+    ARC_SBC_f_rrr	= 610,
+    ARC_SBC_f_rrs12	= 611,
+    ARC_SBC_f_rru6	= 612,
+    ARC_SBC_rrlimm	= 613,
+    ARC_SBC_rrr	= 614,
+    ARC_SBC_rrs12	= 615,
+    ARC_SBC_rru6	= 616,
+    ARC_SETEQ_cc_f_rru6	= 617,
+    ARC_SETEQ_cc_rru6	= 618,
+    ARC_SETEQ_f_rrlimm	= 619,
+    ARC_SETEQ_f_rrr	= 620,
+    ARC_SETEQ_f_rrs12	= 621,
+    ARC_SETEQ_f_rru6	= 622,
+    ARC_SETEQ_rrlimm	= 623,
+    ARC_SETEQ_rrr	= 624,
+    ARC_SETEQ_rrs12	= 625,
+    ARC_SETEQ_rru6	= 626,
+    ARC_SEXB_f_rr	= 627,
+    ARC_SEXB_rr	= 628,
+    ARC_SEXH_f_rr	= 629,
+    ARC_SEXH_rr	= 630,
+    ARC_SP_ADD_S	= 631,
+    ARC_SP_ADD_SP_S	= 632,
+    ARC_SP_LDB_S	= 633,
+    ARC_SP_LD_S	= 634,
+    ARC_SP_STB_S	= 635,
+    ARC_SP_ST_S	= 636,
+    ARC_SP_SUB_SP_S	= 637,
+    ARC_STB_AB_rs9	= 638,
+    ARC_STB_AW_rs9	= 639,
+    ARC_STB_DI_AB_rs9	= 640,
+    ARC_STB_DI_AW_rs9	= 641,
+    ARC_STB_DI_limm	= 642,
+    ARC_STB_DI_rs9	= 643,
+    ARC_STB_S_OFF	= 644,
+    ARC_STB_limm	= 645,
+    ARC_STB_rs9	= 646,
+    ARC_STH_AB_rs9	= 647,
+    ARC_STH_AW_rs9	= 648,
+    ARC_STH_DI_AB_rs9	= 649,
+    ARC_STH_DI_AW_rs9	= 650,
+    ARC_STH_DI_limm	= 651,
+    ARC_STH_DI_rs9	= 652,
+    ARC_STH_S_OFF	= 653,
+    ARC_STH_limm	= 654,
+    ARC_STH_rs9	= 655,
+    ARC_ST_AB_rs9	= 656,
+    ARC_ST_AW_rs9	= 657,
+    ARC_ST_DI_AB_rs9	= 658,
+    ARC_ST_DI_AW_rs9	= 659,
+    ARC_ST_DI_limm	= 660,
+    ARC_ST_DI_rs9	= 661,
+    ARC_ST_S_OFF	= 662,
+    ARC_ST_S_s11	= 663,
+    ARC_ST_limm	= 664,
+    ARC_ST_rs9	= 665,
+    ARC_SUB1_cc_f_rru6	= 666,
+    ARC_SUB1_cc_rru6	= 667,
+    ARC_SUB1_f_rrlimm	= 668,
+    ARC_SUB1_f_rrr	= 669,
+    ARC_SUB1_f_rrs12	= 670,
+    ARC_SUB1_f_rru6	= 671,
+    ARC_SUB1_rrlimm	= 672,
+    ARC_SUB1_rrr	= 673,
+    ARC_SUB1_rrs12	= 674,
+    ARC_SUB1_rru6	= 675,
+    ARC_SUB2_cc_f_rru6	= 676,
+    ARC_SUB2_cc_rru6	= 677,
+    ARC_SUB2_f_rrlimm	= 678,
+    ARC_SUB2_f_rrr	= 679,
+    ARC_SUB2_f_rrs12	= 680,
+    ARC_SUB2_f_rru6	= 681,
+    ARC_SUB2_rrlimm	= 682,
+    ARC_SUB2_rrr	= 683,
+    ARC_SUB2_rrs12	= 684,
+    ARC_SUB2_rru6	= 685,
+    ARC_SUB3_cc_f_rru6	= 686,
+    ARC_SUB3_cc_rru6	= 687,
+    ARC_SUB3_f_rrlimm	= 688,
+    ARC_SUB3_f_rrr	= 689,
+    ARC_SUB3_f_rrs12	= 690,
+    ARC_SUB3_f_rru6	= 691,
+    ARC_SUB3_rrlimm	= 692,
+    ARC_SUB3_rrr	= 693,
+    ARC_SUB3_rrs12	= 694,
+    ARC_SUB3_rru6	= 695,
+    ARC_SUB_S_rrr	= 696,
+    ARC_SUB_S_ru3	= 697,
+    ARC_SUB_S_ru5	= 698,
+    ARC_SUB_cc_f_rru6	= 699,
+    ARC_SUB_cc_rru6	= 700,
+    ARC_SUB_f_rrlimm	= 701,
+    ARC_SUB_f_rrr	= 702,
+    ARC_SUB_f_rrs12	= 703,
+    ARC_SUB_f_rru6	= 704,
+    ARC_SUB_rrlimm	= 705,
+    ARC_SUB_rrr	= 706,
+    ARC_SUB_rrs12	= 707,
+    ARC_SUB_rru6	= 708,
+    ARC_XOR_cc_f_rru6	= 709,
+    ARC_XOR_cc_rru6	= 710,
+    ARC_XOR_f_rrlimm	= 711,
+    ARC_XOR_f_rrr	= 712,
+    ARC_XOR_f_rrs12	= 713,
+    ARC_XOR_f_rru6	= 714,
+    ARC_XOR_rrlimm	= 715,
+    ARC_XOR_rrr	= 716,
+    ARC_XOR_rrs12	= 717,
+    ARC_XOR_rru6	= 718,
+    INSTRUCTION_LIST_END = 719
+  };
+
+#endif // GET_INSTRINFO_ENUM
+
+#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
+typedef struct ARCInstrTable {
+  MCInstrDesc Insts[719];
+  MCOperandInfo OperandInfo[207];
+  MCPhysReg ImplicitOps[9];
+} ARCInstrTable;
+
+#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
+
+#ifdef GET_INSTRINFO_MC_DESC
+#undef GET_INSTRINFO_MC_DESC
+
+static const unsigned ARCImpOpBase = sizeof(MCOperandInfo) / (sizeof(MCPhysReg));
+
+static const ARCInstrTable ARCDescs = {
+  {
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #718 = XOR_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #717 = XOR_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #716 = XOR_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #715 = XOR_rrlimm
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #714 = XOR_f_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #713 = XOR_f_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #712 = XOR_f_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #711 = XOR_f_rrlimm
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #710 = XOR_cc_rru6
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #709 = XOR_cc_f_rru6
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #708 = SUB_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #707 = SUB_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #706 = SUB_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #705 = SUB_rrlimm
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #704 = SUB_f_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #703 = SUB_f_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #702 = SUB_f_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #701 = SUB_f_rrlimm
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #700 = SUB_cc_rru6
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #699 = SUB_cc_f_rru6
+  { 2, &ARCDescs.OperandInfo[176] },  // Inst #698 = SUB_S_ru5
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #697 = SUB_S_ru3
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #696 = SUB_S_rrr
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #695 = SUB3_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #694 = SUB3_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #693 = SUB3_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #692 = SUB3_rrlimm
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #691 = SUB3_f_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #690 = SUB3_f_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #689 = SUB3_f_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #688 = SUB3_f_rrlimm
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #687 = SUB3_cc_rru6
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #686 = SUB3_cc_f_rru6
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #685 = SUB2_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #684 = SUB2_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #683 = SUB2_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #682 = SUB2_rrlimm
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #681 = SUB2_f_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #680 = SUB2_f_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #679 = SUB2_f_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #678 = SUB2_f_rrlimm
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #677 = SUB2_cc_rru6
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #676 = SUB2_cc_f_rru6
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #675 = SUB1_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #674 = SUB1_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #673 = SUB1_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #672 = SUB1_rrlimm
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #671 = SUB1_f_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #670 = SUB1_f_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #669 = SUB1_f_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #668 = SUB1_f_rrlimm
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #667 = SUB1_cc_rru6
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #666 = SUB1_cc_f_rru6
+  { 3, &ARCDescs.OperandInfo[153] },  // Inst #665 = ST_rs9
+  { 3, &ARCDescs.OperandInfo[150] },  // Inst #664 = ST_limm
+  { 1, &ARCDescs.OperandInfo[0] },  // Inst #663 = ST_S_s11
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #662 = ST_S_OFF
+  { 3, &ARCDescs.OperandInfo[153] },  // Inst #661 = ST_DI_rs9
+  { 3, &ARCDescs.OperandInfo[150] },  // Inst #660 = ST_DI_limm
+  { 4, &ARCDescs.OperandInfo[203] },  // Inst #659 = ST_DI_AW_rs9
+  { 4, &ARCDescs.OperandInfo[203] },  // Inst #658 = ST_DI_AB_rs9
+  { 4, &ARCDescs.OperandInfo[203] },  // Inst #657 = ST_AW_rs9
+  { 4, &ARCDescs.OperandInfo[203] },  // Inst #656 = ST_AB_rs9
+  { 3, &ARCDescs.OperandInfo[153] },  // Inst #655 = STH_rs9
+  { 3, &ARCDescs.OperandInfo[150] },  // Inst #654 = STH_limm
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #653 = STH_S_OFF
+  { 3, &ARCDescs.OperandInfo[153] },  // Inst #652 = STH_DI_rs9
+  { 3, &ARCDescs.OperandInfo[150] },  // Inst #651 = STH_DI_limm
+  { 4, &ARCDescs.OperandInfo[203] },  // Inst #650 = STH_DI_AW_rs9
+  { 4, &ARCDescs.OperandInfo[203] },  // Inst #649 = STH_DI_AB_rs9
+  { 4, &ARCDescs.OperandInfo[203] },  // Inst #648 = STH_AW_rs9
+  { 4, &ARCDescs.OperandInfo[203] },  // Inst #647 = STH_AB_rs9
+  { 3, &ARCDescs.OperandInfo[153] },  // Inst #646 = STB_rs9
+  { 3, &ARCDescs.OperandInfo[150] },  // Inst #645 = STB_limm
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #644 = STB_S_OFF
+  { 3, &ARCDescs.OperandInfo[153] },  // Inst #643 = STB_DI_rs9
+  { 3, &ARCDescs.OperandInfo[150] },  // Inst #642 = STB_DI_limm
+  { 4, &ARCDescs.OperandInfo[203] },  // Inst #641 = STB_DI_AW_rs9
+  { 4, &ARCDescs.OperandInfo[203] },  // Inst #640 = STB_DI_AB_rs9
+  { 4, &ARCDescs.OperandInfo[203] },  // Inst #639 = STB_AW_rs9
+  { 4, &ARCDescs.OperandInfo[203] },  // Inst #638 = STB_AB_rs9
+  { 1, &ARCDescs.OperandInfo[0] },  // Inst #637 = SP_SUB_SP_S
+  { 2, &ARCDescs.OperandInfo[201] },  // Inst #636 = SP_ST_S
+  { 2, &ARCDescs.OperandInfo[201] },  // Inst #635 = SP_STB_S
+  { 2, &ARCDescs.OperandInfo[201] },  // Inst #634 = SP_LD_S
+  { 2, &ARCDescs.OperandInfo[201] },  // Inst #633 = SP_LDB_S
+  { 1, &ARCDescs.OperandInfo[0] },  // Inst #632 = SP_ADD_SP_S
+  { 2, &ARCDescs.OperandInfo[201] },  // Inst #631 = SP_ADD_S
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #630 = SEXH_rr
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #629 = SEXH_f_rr
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #628 = SEXB_rr
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #627 = SEXB_f_rr
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #626 = SETEQ_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #625 = SETEQ_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #624 = SETEQ_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #623 = SETEQ_rrlimm
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #622 = SETEQ_f_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #621 = SETEQ_f_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #620 = SETEQ_f_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #619 = SETEQ_f_rrlimm
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #618 = SETEQ_cc_rru6
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #617 = SETEQ_cc_f_rru6
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #616 = SBC_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #615 = SBC_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #614 = SBC_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #613 = SBC_rrlimm
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #612 = SBC_f_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #611 = SBC_f_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #610 = SBC_f_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #609 = SBC_f_rrlimm
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #608 = SBC_cc_rru6
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #607 = SBC_cc_f_rru6
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #606 = RSUB_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #605 = RSUB_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #604 = RSUB_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #603 = RSUB_rrlimm
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #602 = RSUB_f_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #601 = RSUB_f_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #600 = RSUB_f_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #599 = RSUB_f_rrlimm
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #598 = RSUB_cc_rru6
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #597 = RSUB_cc_f_rru6
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #596 = ROR_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #595 = ROR_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #594 = ROR_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #593 = ROR_rrlimm
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #592 = ROR_f_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #591 = ROR_f_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #590 = ROR_f_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #589 = ROR_f_rrlimm
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #588 = ROR_cc_rru6
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #587 = ROR_cc_f_rru6
+  { 1, &ARCDescs.OperandInfo[200] },  // Inst #586 = PUSH_S_r
+  { 0, &ARCDescs.OperandInfo[1] },  // Inst #585 = PUSH_S_BLINK
+  { 1, &ARCDescs.OperandInfo[200] },  // Inst #584 = POP_S_r
+  { 0, &ARCDescs.OperandInfo[1] },  // Inst #583 = POP_S_BLINK
+  { 2, &ARCDescs.OperandInfo[176] },  // Inst #582 = PCL_LD
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #581 = OR_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #580 = OR_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #579 = OR_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #578 = OR_rrlimm
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #577 = OR_f_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #576 = OR_f_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #575 = OR_f_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #574 = OR_f_rrlimm
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #573 = OR_cc_rru6
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #572 = OR_cc_f_rru6
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #571 = NORM_rr
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #570 = NORM_f_rr
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #569 = NORMH_rr
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #568 = NORMH_f_rr
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #567 = MPY_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #566 = MPY_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #565 = MPY_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #564 = MPY_rrlimm
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #563 = MPY_f_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #562 = MPY_f_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #561 = MPY_f_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #560 = MPY_f_rrlimm
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #559 = MPY_cc_rru6
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #558 = MPY_cc_f_rru6
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #557 = MPYM_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #556 = MPYM_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #555 = MPYM_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #554 = MPYM_rrlimm
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #553 = MPYM_f_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #552 = MPYM_f_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #551 = MPYM_f_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #550 = MPYM_f_rrlimm
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #549 = MPYM_cc_rru6
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #548 = MPYM_cc_f_rru6
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #547 = MPYMU_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #546 = MPYMU_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #545 = MPYMU_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #544 = MPYMU_rrlimm
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #543 = MPYMU_f_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #542 = MPYMU_f_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #541 = MPYMU_f_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #540 = MPYMU_f_rrlimm
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #539 = MPYMU_cc_rru6
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #538 = MPYMU_cc_f_rru6
+  { 2, &ARCDescs.OperandInfo[176] },  // Inst #537 = MOV_ru6
+  { 2, &ARCDescs.OperandInfo[176] },  // Inst #536 = MOV_rs12
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #535 = MOV_rr
+  { 2, &ARCDescs.OperandInfo[174] },  // Inst #534 = MOV_rlimm
+  { 2, &ARCDescs.OperandInfo[176] },  // Inst #533 = MOV_f_ru6
+  { 4, &ARCDescs.OperandInfo[196] },  // Inst #532 = MOV_cc_ru6
+  { 4, &ARCDescs.OperandInfo[196] },  // Inst #531 = MOV_cc_f_ru6
+  { 4, &ARCDescs.OperandInfo[192] },  // Inst #530 = MOV_cc
+  { 2, &ARCDescs.OperandInfo[176] },  // Inst #529 = MOV_S_u8
+  { 1, &ARCDescs.OperandInfo[0] },  // Inst #528 = MOV_S_s3
+  { 2, &ARCDescs.OperandInfo[176] },  // Inst #527 = MOV_S_rs3
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #526 = MOV_S_NE_rr
+  { 2, &ARCDescs.OperandInfo[174] },  // Inst #525 = MOV_S_NE_rlimm
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #524 = MIN_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #523 = MIN_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #522 = MIN_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #521 = MIN_rrlimm
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #520 = MIN_f_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #519 = MIN_f_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #518 = MIN_f_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #517 = MIN_f_rrlimm
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #516 = MIN_cc_rru6
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #515 = MIN_cc_f_rru6
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #514 = MAX_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #513 = MAX_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #512 = MAX_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #511 = MAX_rrlimm
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #510 = MAX_f_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #509 = MAX_f_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #508 = MAX_f_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #507 = MAX_f_rrlimm
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #506 = MAX_cc_rru6
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #505 = MAX_cc_f_rru6
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #504 = LSR_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #503 = LSR_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #502 = LSR_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #501 = LSR_rrlimm
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #500 = LSR_f_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #499 = LSR_f_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #498 = LSR_f_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #497 = LSR_f_rrlimm
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #496 = LSR_cc_rru6
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #495 = LSR_cc_f_rru6
+  { 2, &ARCDescs.OperandInfo[176] },  // Inst #494 = LSR_S_ru5
+  { 2, &ARCDescs.OperandInfo[176] },  // Inst #493 = LR_ru6
+  { 2, &ARCDescs.OperandInfo[176] },  // Inst #492 = LR_rs12
+  { 1, &ARCDescs.OperandInfo[0] },  // Inst #491 = LEAVE_S
+  { 3, &ARCDescs.OperandInfo[153] },  // Inst #490 = LD_rs9
+  { 3, &ARCDescs.OperandInfo[153] },  // Inst #489 = LD_rlimm
+  { 3, &ARCDescs.OperandInfo[150] },  // Inst #488 = LD_limm
+  { 1, &ARCDescs.OperandInfo[0] },  // Inst #487 = LD_S_s11
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #486 = LD_S_rrr
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #485 = LD_S_OFF
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #484 = LD_S_AS_rrr
+  { 3, &ARCDescs.OperandInfo[153] },  // Inst #483 = LD_DI_rs9
+  { 3, &ARCDescs.OperandInfo[153] },  // Inst #482 = LD_DI_rlimm
+  { 3, &ARCDescs.OperandInfo[150] },  // Inst #481 = LD_DI_limm
+  { 4, &ARCDescs.OperandInfo[188] },  // Inst #480 = LD_DI_AW_rs9
+  { 4, &ARCDescs.OperandInfo[188] },  // Inst #479 = LD_DI_AB_rs9
+  { 4, &ARCDescs.OperandInfo[188] },  // Inst #478 = LD_AW_rs9
+  { 4, &ARCDescs.OperandInfo[188] },  // Inst #477 = LD_AB_rs9
+  { 2, &ARCDescs.OperandInfo[176] },  // Inst #476 = LDI_S_u7
+  { 3, &ARCDescs.OperandInfo[153] },  // Inst #475 = LDH_rs9
+  { 3, &ARCDescs.OperandInfo[153] },  // Inst #474 = LDH_rlimm
+  { 3, &ARCDescs.OperandInfo[150] },  // Inst #473 = LDH_limm
+  { 3, &ARCDescs.OperandInfo[153] },  // Inst #472 = LDH_X_rs9
+  { 3, &ARCDescs.OperandInfo[153] },  // Inst #471 = LDH_X_rlimm
+  { 3, &ARCDescs.OperandInfo[150] },  // Inst #470 = LDH_X_limm
+  { 3, &ARCDescs.OperandInfo[153] },  // Inst #469 = LDH_X_DI_rs9
+  { 3, &ARCDescs.OperandInfo[153] },  // Inst #468 = LDH_X_DI_rlimm
+  { 3, &ARCDescs.OperandInfo[150] },  // Inst #467 = LDH_X_DI_limm
+  { 4, &ARCDescs.OperandInfo[188] },  // Inst #466 = LDH_X_DI_AW_rs9
+  { 4, &ARCDescs.OperandInfo[188] },  // Inst #465 = LDH_X_DI_AB_rs9
+  { 4, &ARCDescs.OperandInfo[188] },  // Inst #464 = LDH_X_AW_rs9
+  { 4, &ARCDescs.OperandInfo[188] },  // Inst #463 = LDH_X_AB_rs9
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #462 = LDH_S_rrr
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #461 = LDH_S_X_OFF
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #460 = LDH_S_OFF
+  { 3, &ARCDescs.OperandInfo[153] },  // Inst #459 = LDH_DI_rs9
+  { 3, &ARCDescs.OperandInfo[153] },  // Inst #458 = LDH_DI_rlimm
+  { 3, &ARCDescs.OperandInfo[150] },  // Inst #457 = LDH_DI_limm
+  { 4, &ARCDescs.OperandInfo[188] },  // Inst #456 = LDH_DI_AW_rs9
+  { 4, &ARCDescs.OperandInfo[188] },  // Inst #455 = LDH_DI_AB_rs9
+  { 4, &ARCDescs.OperandInfo[188] },  // Inst #454 = LDH_AW_rs9
+  { 4, &ARCDescs.OperandInfo[188] },  // Inst #453 = LDH_AB_rs9
+  { 3, &ARCDescs.OperandInfo[153] },  // Inst #452 = LDB_rs9
+  { 3, &ARCDescs.OperandInfo[153] },  // Inst #451 = LDB_rlimm
+  { 3, &ARCDescs.OperandInfo[150] },  // Inst #450 = LDB_limm
+  { 3, &ARCDescs.OperandInfo[153] },  // Inst #449 = LDB_X_rs9
+  { 3, &ARCDescs.OperandInfo[153] },  // Inst #448 = LDB_X_rlimm
+  { 3, &ARCDescs.OperandInfo[150] },  // Inst #447 = LDB_X_limm
+  { 3, &ARCDescs.OperandInfo[153] },  // Inst #446 = LDB_X_DI_rs9
+  { 3, &ARCDescs.OperandInfo[153] },  // Inst #445 = LDB_X_DI_rlimm
+  { 3, &ARCDescs.OperandInfo[150] },  // Inst #444 = LDB_X_DI_limm
+  { 4, &ARCDescs.OperandInfo[188] },  // Inst #443 = LDB_X_DI_AW_rs9
+  { 4, &ARCDescs.OperandInfo[188] },  // Inst #442 = LDB_X_DI_AB_rs9
+  { 4, &ARCDescs.OperandInfo[188] },  // Inst #441 = LDB_X_AW_rs9
+  { 4, &ARCDescs.OperandInfo[188] },  // Inst #440 = LDB_X_AB_rs9
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #439 = LDB_S_rrr
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #438 = LDB_S_OFF
+  { 3, &ARCDescs.OperandInfo[153] },  // Inst #437 = LDB_DI_rs9
+  { 3, &ARCDescs.OperandInfo[153] },  // Inst #436 = LDB_DI_rlimm
+  { 3, &ARCDescs.OperandInfo[150] },  // Inst #435 = LDB_DI_limm
+  { 4, &ARCDescs.OperandInfo[188] },  // Inst #434 = LDB_DI_AW_rs9
+  { 4, &ARCDescs.OperandInfo[188] },  // Inst #433 = LDB_DI_AB_rs9
+  { 4, &ARCDescs.OperandInfo[188] },  // Inst #432 = LDB_AW_rs9
+  { 4, &ARCDescs.OperandInfo[188] },  // Inst #431 = LDB_AB_rs9
+  { 0, &ARCDescs.OperandInfo[1] },  // Inst #430 = J_S_BLINK
+  { 1, &ARCDescs.OperandInfo[1] },  // Inst #429 = J_LImm
+  { 1, &ARCDescs.OperandInfo[1] },  // Inst #428 = JL_LImm
+  { 1, &ARCDescs.OperandInfo[0] },  // Inst #427 = JLI_S
+  { 1, &ARCDescs.OperandInfo[187] },  // Inst #426 = JL
+  { 1, &ARCDescs.OperandInfo[187] },  // Inst #425 = J
+  { 1, &ARCDescs.OperandInfo[0] },  // Inst #424 = GP_LD_S
+  { 1, &ARCDescs.OperandInfo[0] },  // Inst #423 = GP_LDH_S
+  { 1, &ARCDescs.OperandInfo[0] },  // Inst #422 = GP_LDB_S
+  { 1, &ARCDescs.OperandInfo[0] },  // Inst #421 = GP_ADD_S
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #420 = GEN_XOR_S
+  { 0, &ARCDescs.OperandInfo[1] },  // Inst #419 = GEN_UNIMP_S
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #418 = GEN_TST_S
+  { 1, &ARCDescs.OperandInfo[0] },  // Inst #417 = GEN_TRAP_S
+  { 0, &ARCDescs.OperandInfo[1] },  // Inst #416 = GEN_SWI_S
+  { 1, &ARCDescs.OperandInfo[187] },  // Inst #415 = GEN_SUB_S_NE
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #414 = GEN_SUB_S
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #413 = GEN_SEXH_S
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #412 = GEN_SEXB_S
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #411 = GEN_OR_S
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #410 = GEN_NOT_S
+  { 0, &ARCDescs.OperandInfo[1] },  // Inst #409 = GEN_NOP_S
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #408 = GEN_NEG_S
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #407 = GEN_MPY_S
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #406 = GEN_MPYW_S
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #405 = GEN_MPYUW_S
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #404 = GEN_LSR_S
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #403 = GEN_LS1R_S
+  { 0, &ARCDescs.OperandInfo[1] },  // Inst #402 = GEN_J_S_D_BLINK
+  { 1, &ARCDescs.OperandInfo[187] },  // Inst #401 = GEN_J_S_D
+  { 1, &ARCDescs.OperandInfo[187] },  // Inst #400 = GEN_J_S
+  { 0, &ARCDescs.OperandInfo[1] },  // Inst #399 = GEN_JNE_S
+  { 1, &ARCDescs.OperandInfo[187] },  // Inst #398 = GEN_JL_S_D
+  { 1, &ARCDescs.OperandInfo[187] },  // Inst #397 = GEN_JL_S
+  { 0, &ARCDescs.OperandInfo[1] },  // Inst #396 = GEN_JEQ_S
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #395 = GEN_EXTH_S
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #394 = GEN_EXTB_S
+  { 0, &ARCDescs.OperandInfo[1] },  // Inst #393 = GEN_BRK_S
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #392 = GEN_BIC_S
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #391 = GEN_ASR_S
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #390 = GEN_ASL_S
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #389 = GEN_AS1R_S
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #388 = GEN_AS1L_S
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #387 = GEN_AND_S
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #386 = GEN_ADD3_S
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #385 = GEN_ADD2_S
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #384 = GEN_ADD1_S
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #383 = GEN_ABS_S
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #382 = FLS_rr
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #381 = FLS_f_rr
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #380 = FFS_rr
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #379 = FFS_f_rr
+  { 1, &ARCDescs.OperandInfo[0] },  // Inst #378 = ENTER_S
+  { 1, &ARCDescs.OperandInfo[0] },  // Inst #377 = EI_S
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #376 = COMPACT_MOV_S_limm
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #375 = COMPACT_MOV_S_hreg
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #374 = COMPACT_LD_S
+  { 2, &ARCDescs.OperandInfo[174] },  // Inst #373 = CMP_ru6
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #372 = CMP_rr
+  { 2, &ARCDescs.OperandInfo[174] },  // Inst #371 = CMP_rlimm
+  { 2, &ARCDescs.OperandInfo[176] },  // Inst #370 = CMP_S_u7
+  { 2, &ARCDescs.OperandInfo[176] },  // Inst #369 = CMP_S_rs3
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #368 = CMP_S_rr
+  { 2, &ARCDescs.OperandInfo[174] },  // Inst #367 = CMP_S_rlimm
+  { 2, &ARCDescs.OperandInfo[172] },  // Inst #366 = CMP_S_limms3
+  { 2, &ARCDescs.OperandInfo[185] },  // Inst #365 = Bcc
+  { 1, &ARCDescs.OperandInfo[178] },  // Inst #364 = B_S
+  { 2, &ARCDescs.OperandInfo[176] },  // Inst #363 = BTST_S_ru5
+  { 2, &ARCDescs.OperandInfo[176] },  // Inst #362 = BSET_S_ru5
+  { 4, &ARCDescs.OperandInfo[181] },  // Inst #361 = BRcc_ru6
+  { 4, &ARCDescs.OperandInfo[140] },  // Inst #360 = BRcc_rr
+  { 2, &ARCDescs.OperandInfo[179] },  // Inst #359 = BRNE_S
+  { 2, &ARCDescs.OperandInfo[179] },  // Inst #358 = BREQ_S
+  { 1, &ARCDescs.OperandInfo[178] },  // Inst #357 = BR
+  { 1, &ARCDescs.OperandInfo[178] },  // Inst #356 = BNE_S
+  { 2, &ARCDescs.OperandInfo[176] },  // Inst #355 = BMSK_S_ru5
+  { 1, &ARCDescs.OperandInfo[178] },  // Inst #354 = BL_S
+  { 1, &ARCDescs.OperandInfo[178] },  // Inst #353 = BLT_S
+  { 1, &ARCDescs.OperandInfo[178] },  // Inst #352 = BLS_S
+  { 1, &ARCDescs.OperandInfo[178] },  // Inst #351 = BLO_S
+  { 1, &ARCDescs.OperandInfo[178] },  // Inst #350 = BLE_S
+  { 1, &ARCDescs.OperandInfo[178] },  // Inst #349 = BL
+  { 1, &ARCDescs.OperandInfo[178] },  // Inst #348 = BHS_S
+  { 1, &ARCDescs.OperandInfo[178] },  // Inst #347 = BHI_S
+  { 1, &ARCDescs.OperandInfo[178] },  // Inst #346 = BGT_S
+  { 1, &ARCDescs.OperandInfo[178] },  // Inst #345 = BGE_S
+  { 1, &ARCDescs.OperandInfo[178] },  // Inst #344 = BEQ_S
+  { 2, &ARCDescs.OperandInfo[176] },  // Inst #343 = BCLR_S_ru5
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #342 = ASR_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #341 = ASR_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #340 = ASR_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #339 = ASR_rrlimm
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #338 = ASR_f_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #337 = ASR_f_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #336 = ASR_f_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #335 = ASR_f_rrlimm
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #334 = ASR_cc_rru6
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #333 = ASR_cc_f_rru6
+  { 2, &ARCDescs.OperandInfo[176] },  // Inst #332 = ASR_S_ru5
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #331 = ASR_S_ru3
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #330 = ASL_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #329 = ASL_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #328 = ASL_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #327 = ASL_rrlimm
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #326 = ASL_f_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #325 = ASL_f_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #324 = ASL_f_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #323 = ASL_f_rrlimm
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #322 = ASL_cc_rru6
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #321 = ASL_cc_f_rru6
+  { 2, &ARCDescs.OperandInfo[176] },  // Inst #320 = ASL_S_ru5
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #319 = ASL_S_ru3
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #318 = AND_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #317 = AND_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #316 = AND_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #315 = AND_rrlimm
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #314 = AND_f_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #313 = AND_f_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #312 = AND_f_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #311 = AND_f_rrlimm
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #310 = AND_cc_rru6
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #309 = AND_cc_f_rru6
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #308 = ADD_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #307 = ADD_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #306 = ADD_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #305 = ADD_rrlimm
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #304 = ADD_f_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #303 = ADD_f_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #302 = ADD_f_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #301 = ADD_f_rrlimm
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #300 = ADD_cc_rru6
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #299 = ADD_cc_f_rru6
+  { 2, &ARCDescs.OperandInfo[176] },  // Inst #298 = ADD_S_u7
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #297 = ADD_S_ru3
+  { 2, &ARCDescs.OperandInfo[176] },  // Inst #296 = ADD_S_rs3
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #295 = ADD_S_rru6
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #294 = ADD_S_rrr
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #293 = ADD_S_rr
+  { 2, &ARCDescs.OperandInfo[174] },  // Inst #292 = ADD_S_rlimm
+  { 2, &ARCDescs.OperandInfo[172] },  // Inst #291 = ADD_S_limms3
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #290 = ADC_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #289 = ADC_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #288 = ADC_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #287 = ADC_rrlimm
+  { 3, &ARCDescs.OperandInfo[169] },  // Inst #286 = ADC_f_rru6
+  { 3, &ARCDescs.OperandInfo[166] },  // Inst #285 = ADC_f_rrs12
+  { 3, &ARCDescs.OperandInfo[163] },  // Inst #284 = ADC_f_rrr
+  { 3, &ARCDescs.OperandInfo[160] },  // Inst #283 = ADC_f_rrlimm
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #282 = ADC_cc_rru6
+  { 4, &ARCDescs.OperandInfo[156] },  // Inst #281 = ADC_cc_f_rru6
+  { 3, &ARCDescs.OperandInfo[153] },  // Inst #280 = ST_FAR
+  { 3, &ARCDescs.OperandInfo[153] },  // Inst #279 = STH_FAR
+  { 3, &ARCDescs.OperandInfo[153] },  // Inst #278 = STB_FAR
+  { 3, &ARCDescs.OperandInfo[150] },  // Inst #277 = GETFI
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #276 = CTTZ
+  { 2, &ARCDescs.OperandInfo[148] },  // Inst #275 = CTLZ
+  { 4, &ARCDescs.OperandInfo[144] },  // Inst #274 = BRcc_ru6_p
+  { 4, &ARCDescs.OperandInfo[140] },  // Inst #273 = BRcc_rr_p
+  { 2, &ARCDescs.OperandInfo[21] },  // Inst #272 = ADJCALLSTACKUP
+  { 2, &ARCDescs.OperandInfo[21] },  // Inst #271 = ADJCALLSTACKDOWN
+  { 4, &ARCDescs.OperandInfo[136] },  // Inst #270 = G_UBFX
+  { 4, &ARCDescs.OperandInfo[136] },  // Inst #269 = G_SBFX
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #268 = G_VECREDUCE_UMIN
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #267 = G_VECREDUCE_UMAX
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #266 = G_VECREDUCE_SMIN
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #265 = G_VECREDUCE_SMAX
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #264 = G_VECREDUCE_XOR
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #263 = G_VECREDUCE_OR
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #262 = G_VECREDUCE_AND
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #261 = G_VECREDUCE_MUL
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #260 = G_VECREDUCE_ADD
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #259 = G_VECREDUCE_FMINIMUM
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #258 = G_VECREDUCE_FMAXIMUM
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #257 = G_VECREDUCE_FMIN
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #256 = G_VECREDUCE_FMAX
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #255 = G_VECREDUCE_FMUL
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #254 = G_VECREDUCE_FADD
+  { 3, &ARCDescs.OperandInfo[123] },  // Inst #253 = G_VECREDUCE_SEQ_FMUL
+  { 3, &ARCDescs.OperandInfo[123] },  // Inst #252 = G_VECREDUCE_SEQ_FADD
+  { 3, &ARCDescs.OperandInfo[53] },  // Inst #251 = G_BZERO
+  { 4, &ARCDescs.OperandInfo[132] },  // Inst #250 = G_MEMSET
+  { 4, &ARCDescs.OperandInfo[132] },  // Inst #249 = G_MEMMOVE
+  { 3, &ARCDescs.OperandInfo[123] },  // Inst #248 = G_MEMCPY_INLINE
+  { 4, &ARCDescs.OperandInfo[132] },  // Inst #247 = G_MEMCPY
+  { 2, &ARCDescs.OperandInfo[130] },  // Inst #246 = G_WRITE_REGISTER
+  { 2, &ARCDescs.OperandInfo[51] },  // Inst #245 = G_READ_REGISTER
+  { 3, &ARCDescs.OperandInfo[96] },  // Inst #244 = G_STRICT_FLDEXP
+  { 2, &ARCDescs.OperandInfo[62] },  // Inst #243 = G_STRICT_FSQRT
+  { 4, &ARCDescs.OperandInfo[46] },  // Inst #242 = G_STRICT_FMA
+  { 3, &ARCDescs.OperandInfo[43] },  // Inst #241 = G_STRICT_FREM
+  { 3, &ARCDescs.OperandInfo[43] },  // Inst #240 = G_STRICT_FDIV
+  { 3, &ARCDescs.OperandInfo[43] },  // Inst #239 = G_STRICT_FMUL
+  { 3, &ARCDescs.OperandInfo[43] },  // Inst #238 = G_STRICT_FSUB
+  { 3, &ARCDescs.OperandInfo[43] },  // Inst #237 = G_STRICT_FADD
+  { 1, &ARCDescs.OperandInfo[50] },  // Inst #236 = G_STACKRESTORE
+  { 1, &ARCDescs.OperandInfo[50] },  // Inst #235 = G_STACKSAVE
+  { 3, &ARCDescs.OperandInfo[64] },  // Inst #234 = G_DYN_STACKALLOC
+  { 2, &ARCDescs.OperandInfo[51] },  // Inst #233 = G_JUMP_TABLE
+  { 2, &ARCDescs.OperandInfo[51] },  // Inst #232 = G_BLOCK_ADDR
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #231 = G_ADDRSPACE_CAST
+  { 2, &ARCDescs.OperandInfo[62] },  // Inst #230 = G_FNEARBYINT
+  { 2, &ARCDescs.OperandInfo[62] },  // Inst #229 = G_FRINT
+  { 2, &ARCDescs.OperandInfo[62] },  // Inst #228 = G_FFLOOR
+  { 2, &ARCDescs.OperandInfo[62] },  // Inst #227 = G_FSQRT
+  { 2, &ARCDescs.OperandInfo[62] },  // Inst #226 = G_FSIN
+  { 2, &ARCDescs.OperandInfo[62] },  // Inst #225 = G_FCOS
+  { 2, &ARCDescs.OperandInfo[62] },  // Inst #224 = G_FCEIL
+  { 2, &ARCDescs.OperandInfo[62] },  // Inst #223 = G_BITREVERSE
+  { 2, &ARCDescs.OperandInfo[62] },  // Inst #222 = G_BSWAP
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #221 = G_CTPOP
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #220 = G_CTLZ_ZERO_UNDEF
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #219 = G_CTLZ
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #218 = G_CTTZ_ZERO_UNDEF
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #217 = G_CTTZ
+  { 4, &ARCDescs.OperandInfo[126] },  // Inst #216 = G_SHUFFLE_VECTOR
+  { 3, &ARCDescs.OperandInfo[123] },  // Inst #215 = G_EXTRACT_VECTOR_ELT
+  { 4, &ARCDescs.OperandInfo[119] },  // Inst #214 = G_INSERT_VECTOR_ELT
+  { 3, &ARCDescs.OperandInfo[116] },  // Inst #213 = G_BRJT
+  { 1, &ARCDescs.OperandInfo[0] },  // Inst #212 = G_BR
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #211 = G_LLROUND
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #210 = G_LROUND
+  { 2, &ARCDescs.OperandInfo[62] },  // Inst #209 = G_ABS
+  { 3, &ARCDescs.OperandInfo[43] },  // Inst #208 = G_UMAX
+  { 3, &ARCDescs.OperandInfo[43] },  // Inst #207 = G_UMIN
+  { 3, &ARCDescs.OperandInfo[43] },  // Inst #206 = G_SMAX
+  { 3, &ARCDescs.OperandInfo[43] },  // Inst #205 = G_SMIN
+  { 3, &ARCDescs.OperandInfo[96] },  // Inst #204 = G_PTRMASK
+  { 3, &ARCDescs.OperandInfo[96] },  // Inst #203 = G_PTR_ADD
+  { 0, &ARCDescs.OperandInfo[1] },  // Inst #202 = G_RESET_FPMODE
+  { 1, &ARCDescs.OperandInfo[50] },  // Inst #201 = G_SET_FPMODE
+  { 1, &ARCDescs.OperandInfo[50] },  // Inst #200 = G_GET_FPMODE
+  { 0, &ARCDescs.OperandInfo[1] },  // Inst #199 = G_RESET_FPENV
+  { 1, &ARCDescs.OperandInfo[50] },  // Inst #198 = G_SET_FPENV
+  { 1, &ARCDescs.OperandInfo[50] },  // Inst #197 = G_GET_FPENV
+  { 3, &ARCDescs.OperandInfo[43] },  // Inst #196 = G_FMAXIMUM
+  { 3, &ARCDescs.OperandInfo[43] },  // Inst #195 = G_FMINIMUM
+  { 3, &ARCDescs.OperandInfo[43] },  // Inst #194 = G_FMAXNUM_IEEE
+  { 3, &ARCDescs.OperandInfo[43] },  // Inst #193 = G_FMINNUM_IEEE
+  { 3, &ARCDescs.OperandInfo[43] },  // Inst #192 = G_FMAXNUM
+  { 3, &ARCDescs.OperandInfo[43] },  // Inst #191 = G_FMINNUM
+  { 2, &ARCDescs.OperandInfo[62] },  // Inst #190 = G_FCANONICALIZE
+  { 3, &ARCDescs.OperandInfo[93] },  // Inst #189 = G_IS_FPCLASS
+  { 3, &ARCDescs.OperandInfo[96] },  // Inst #188 = G_FCOPYSIGN
+  { 2, &ARCDescs.OperandInfo[62] },  // Inst #187 = G_FABS
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #186 = G_UITOFP
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #185 = G_SITOFP
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #184 = G_FPTOUI
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #183 = G_FPTOSI
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #182 = G_FPTRUNC
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #181 = G_FPEXT
+  { 2, &ARCDescs.OperandInfo[62] },  // Inst #180 = G_FNEG
+  { 3, &ARCDescs.OperandInfo[86] },  // Inst #179 = G_FFREXP
+  { 3, &ARCDescs.OperandInfo[96] },  // Inst #178 = G_FLDEXP
+  { 2, &ARCDescs.OperandInfo[62] },  // Inst #177 = G_FLOG10
+  { 2, &ARCDescs.OperandInfo[62] },  // Inst #176 = G_FLOG2
+  { 2, &ARCDescs.OperandInfo[62] },  // Inst #175 = G_FLOG
+  { 2, &ARCDescs.OperandInfo[62] },  // Inst #174 = G_FEXP10
+  { 2, &ARCDescs.OperandInfo[62] },  // Inst #173 = G_FEXP2
+  { 2, &ARCDescs.OperandInfo[62] },  // Inst #172 = G_FEXP
+  { 3, &ARCDescs.OperandInfo[96] },  // Inst #171 = G_FPOWI
+  { 3, &ARCDescs.OperandInfo[43] },  // Inst #170 = G_FPOW
+  { 3, &ARCDescs.OperandInfo[43] },  // Inst #169 = G_FREM
+  { 3, &ARCDescs.OperandInfo[43] },  // Inst #168 = G_FDIV
+  { 4, &ARCDescs.OperandInfo[46] },  // Inst #167 = G_FMAD
+  { 4, &ARCDescs.OperandInfo[46] },  // Inst #166 = G_FMA
+  { 3, &ARCDescs.OperandInfo[43] },  // Inst #165 = G_FMUL
+  { 3, &ARCDescs.OperandInfo[43] },  // Inst #164 = G_FSUB
+  { 3, &ARCDescs.OperandInfo[43] },  // Inst #163 = G_FADD
+  { 4, &ARCDescs.OperandInfo[112] },  // Inst #162 = G_UDIVFIXSAT
+  { 4, &ARCDescs.OperandInfo[112] },  // Inst #161 = G_SDIVFIXSAT
+  { 4, &ARCDescs.OperandInfo[112] },  // Inst #160 = G_UDIVFIX
+  { 4, &ARCDescs.OperandInfo[112] },  // Inst #159 = G_SDIVFIX
+  { 4, &ARCDescs.OperandInfo[112] },  // Inst #158 = G_UMULFIXSAT
+  { 4, &ARCDescs.OperandInfo[112] },  // Inst #157 = G_SMULFIXSAT
+  { 4, &ARCDescs.OperandInfo[112] },  // Inst #156 = G_UMULFIX
+  { 4, &ARCDescs.OperandInfo[112] },  // Inst #155 = G_SMULFIX
+  { 3, &ARCDescs.OperandInfo[96] },  // Inst #154 = G_SSHLSAT
+  { 3, &ARCDescs.OperandInfo[96] },  // Inst #153 = G_USHLSAT
+  { 3, &ARCDescs.OperandInfo[43] },  // Inst #152 = G_SSUBSAT
+  { 3, &ARCDescs.OperandInfo[43] },  // Inst #151 = G_USUBSAT
+  { 3, &ARCDescs.OperandInfo[43] },  // Inst #150 = G_SADDSAT
+  { 3, &ARCDescs.OperandInfo[43] },  // Inst #149 = G_UADDSAT
+  { 3, &ARCDescs.OperandInfo[43] },  // Inst #148 = G_SMULH
+  { 3, &ARCDescs.OperandInfo[43] },  // Inst #147 = G_UMULH
+  { 4, &ARCDescs.OperandInfo[82] },  // Inst #146 = G_SMULO
+  { 4, &ARCDescs.OperandInfo[82] },  // Inst #145 = G_UMULO
+  { 5, &ARCDescs.OperandInfo[107] },  // Inst #144 = G_SSUBE
+  { 4, &ARCDescs.OperandInfo[82] },  // Inst #143 = G_SSUBO
+  { 5, &ARCDescs.OperandInfo[107] },  // Inst #142 = G_SADDE
+  { 4, &ARCDescs.OperandInfo[82] },  // Inst #141 = G_SADDO
+  { 5, &ARCDescs.OperandInfo[107] },  // Inst #140 = G_USUBE
+  { 4, &ARCDescs.OperandInfo[82] },  // Inst #139 = G_USUBO
+  { 5, &ARCDescs.OperandInfo[107] },  // Inst #138 = G_UADDE
+  { 4, &ARCDescs.OperandInfo[82] },  // Inst #137 = G_UADDO
+  { 4, &ARCDescs.OperandInfo[82] },  // Inst #136 = G_SELECT
+  { 4, &ARCDescs.OperandInfo[103] },  // Inst #135 = G_FCMP
+  { 4, &ARCDescs.OperandInfo[103] },  // Inst #134 = G_ICMP
+  { 3, &ARCDescs.OperandInfo[96] },  // Inst #133 = G_ROTL
+  { 3, &ARCDescs.OperandInfo[96] },  // Inst #132 = G_ROTR
+  { 4, &ARCDescs.OperandInfo[99] },  // Inst #131 = G_FSHR
+  { 4, &ARCDescs.OperandInfo[99] },  // Inst #130 = G_FSHL
+  { 3, &ARCDescs.OperandInfo[96] },  // Inst #129 = G_ASHR
+  { 3, &ARCDescs.OperandInfo[96] },  // Inst #128 = G_LSHR
+  { 3, &ARCDescs.OperandInfo[96] },  // Inst #127 = G_SHL
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #126 = G_ZEXT
+  { 3, &ARCDescs.OperandInfo[40] },  // Inst #125 = G_SEXT_INREG
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #124 = G_SEXT
+  { 3, &ARCDescs.OperandInfo[93] },  // Inst #123 = G_VAARG
+  { 1, &ARCDescs.OperandInfo[50] },  // Inst #122 = G_VASTART
+  { 2, &ARCDescs.OperandInfo[51] },  // Inst #121 = G_FCONSTANT
+  { 2, &ARCDescs.OperandInfo[51] },  // Inst #120 = G_CONSTANT
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #119 = G_TRUNC
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #118 = G_ANYEXT
+  { 1, &ARCDescs.OperandInfo[0] },  // Inst #117 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
+  { 1, &ARCDescs.OperandInfo[0] },  // Inst #116 = G_INTRINSIC_CONVERGENT
+  { 1, &ARCDescs.OperandInfo[0] },  // Inst #115 = G_INTRINSIC_W_SIDE_EFFECTS
+  { 1, &ARCDescs.OperandInfo[0] },  // Inst #114 = G_INTRINSIC
+  { 0, &ARCDescs.OperandInfo[1] },  // Inst #113 = G_INVOKE_REGION_START
+  { 1, &ARCDescs.OperandInfo[50] },  // Inst #112 = G_BRINDIRECT
+  { 2, &ARCDescs.OperandInfo[51] },  // Inst #111 = G_BRCOND
+  { 4, &ARCDescs.OperandInfo[89] },  // Inst #110 = G_PREFETCH
+  { 2, &ARCDescs.OperandInfo[21] },  // Inst #109 = G_FENCE
+  { 3, &ARCDescs.OperandInfo[86] },  // Inst #108 = G_ATOMICRMW_UDEC_WRAP
+  { 3, &ARCDescs.OperandInfo[86] },  // Inst #107 = G_ATOMICRMW_UINC_WRAP
+  { 3, &ARCDescs.OperandInfo[86] },  // Inst #106 = G_ATOMICRMW_FMIN
+  { 3, &ARCDescs.OperandInfo[86] },  // Inst #105 = G_ATOMICRMW_FMAX
+  { 3, &ARCDescs.OperandInfo[86] },  // Inst #104 = G_ATOMICRMW_FSUB
+  { 3, &ARCDescs.OperandInfo[86] },  // Inst #103 = G_ATOMICRMW_FADD
+  { 3, &ARCDescs.OperandInfo[86] },  // Inst #102 = G_ATOMICRMW_UMIN
+  { 3, &ARCDescs.OperandInfo[86] },  // Inst #101 = G_ATOMICRMW_UMAX
+  { 3, &ARCDescs.OperandInfo[86] },  // Inst #100 = G_ATOMICRMW_MIN
+  { 3, &ARCDescs.OperandInfo[86] },  // Inst #99 = G_ATOMICRMW_MAX
+  { 3, &ARCDescs.OperandInfo[86] },  // Inst #98 = G_ATOMICRMW_XOR
+  { 3, &ARCDescs.OperandInfo[86] },  // Inst #97 = G_ATOMICRMW_OR
+  { 3, &ARCDescs.OperandInfo[86] },  // Inst #96 = G_ATOMICRMW_NAND
+  { 3, &ARCDescs.OperandInfo[86] },  // Inst #95 = G_ATOMICRMW_AND
+  { 3, &ARCDescs.OperandInfo[86] },  // Inst #94 = G_ATOMICRMW_SUB
+  { 3, &ARCDescs.OperandInfo[86] },  // Inst #93 = G_ATOMICRMW_ADD
+  { 3, &ARCDescs.OperandInfo[86] },  // Inst #92 = G_ATOMICRMW_XCHG
+  { 4, &ARCDescs.OperandInfo[82] },  // Inst #91 = G_ATOMIC_CMPXCHG
+  { 5, &ARCDescs.OperandInfo[77] },  // Inst #90 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
+  { 5, &ARCDescs.OperandInfo[72] },  // Inst #89 = G_INDEXED_STORE
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #88 = G_STORE
+  { 5, &ARCDescs.OperandInfo[67] },  // Inst #87 = G_INDEXED_ZEXTLOAD
+  { 5, &ARCDescs.OperandInfo[67] },  // Inst #86 = G_INDEXED_SEXTLOAD
+  { 5, &ARCDescs.OperandInfo[67] },  // Inst #85 = G_INDEXED_LOAD
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #84 = G_ZEXTLOAD
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #83 = G_SEXTLOAD
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #82 = G_LOAD
+  { 1, &ARCDescs.OperandInfo[50] },  // Inst #81 = G_READCYCLECOUNTER
+  { 2, &ARCDescs.OperandInfo[62] },  // Inst #80 = G_INTRINSIC_ROUNDEVEN
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #79 = G_INTRINSIC_LRINT
+  { 2, &ARCDescs.OperandInfo[62] },  // Inst #78 = G_INTRINSIC_ROUND
+  { 2, &ARCDescs.OperandInfo[62] },  // Inst #77 = G_INTRINSIC_TRUNC
+  { 3, &ARCDescs.OperandInfo[64] },  // Inst #76 = G_INTRINSIC_FPTRUNC_ROUND
+  { 2, &ARCDescs.OperandInfo[62] },  // Inst #75 = G_CONSTANT_FOLD_BARRIER
+  { 2, &ARCDescs.OperandInfo[62] },  // Inst #74 = G_FREEZE
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #73 = G_BITCAST
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #72 = G_INTTOPTR
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #71 = G_PTRTOINT
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #70 = G_CONCAT_VECTORS
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #69 = G_BUILD_VECTOR_TRUNC
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #68 = G_BUILD_VECTOR
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #67 = G_MERGE_VALUES
+  { 4, &ARCDescs.OperandInfo[58] },  // Inst #66 = G_INSERT
+  { 2, &ARCDescs.OperandInfo[56] },  // Inst #65 = G_UNMERGE_VALUES
+  { 3, &ARCDescs.OperandInfo[53] },  // Inst #64 = G_EXTRACT
+  { 2, &ARCDescs.OperandInfo[51] },  // Inst #63 = G_CONSTANT_POOL
+  { 2, &ARCDescs.OperandInfo[51] },  // Inst #62 = G_GLOBAL_VALUE
+  { 2, &ARCDescs.OperandInfo[51] },  // Inst #61 = G_FRAME_INDEX
+  { 1, &ARCDescs.OperandInfo[50] },  // Inst #60 = G_PHI
+  { 1, &ARCDescs.OperandInfo[50] },  // Inst #59 = G_IMPLICIT_DEF
+  { 3, &ARCDescs.OperandInfo[43] },  // Inst #58 = G_XOR
+  { 3, &ARCDescs.OperandInfo[43] },  // Inst #57 = G_OR
+  { 3, &ARCDescs.OperandInfo[43] },  // Inst #56 = G_AND
+  { 4, &ARCDescs.OperandInfo[46] },  // Inst #55 = G_UDIVREM
+  { 4, &ARCDescs.OperandInfo[46] },  // Inst #54 = G_SDIVREM
+  { 3, &ARCDescs.OperandInfo[43] },  // Inst #53 = G_UREM
+  { 3, &ARCDescs.OperandInfo[43] },  // Inst #52 = G_SREM
+  { 3, &ARCDescs.OperandInfo[43] },  // Inst #51 = G_UDIV
+  { 3, &ARCDescs.OperandInfo[43] },  // Inst #50 = G_SDIV
+  { 3, &ARCDescs.OperandInfo[43] },  // Inst #49 = G_MUL
+  { 3, &ARCDescs.OperandInfo[43] },  // Inst #48 = G_SUB
+  { 3, &ARCDescs.OperandInfo[43] },  // Inst #47 = G_ADD
+  { 3, &ARCDescs.OperandInfo[40] },  // Inst #46 = G_ASSERT_ALIGN
+  { 3, &ARCDescs.OperandInfo[40] },  // Inst #45 = G_ASSERT_ZEXT
+  { 3, &ARCDescs.OperandInfo[40] },  // Inst #44 = G_ASSERT_SEXT
+  { 1, &ARCDescs.OperandInfo[1] },  // Inst #43 = JUMP_TABLE_DEBUG_INFO
+  { 0, &ARCDescs.OperandInfo[1] },  // Inst #42 = MEMBARRIER
+  { 0, &ARCDescs.OperandInfo[1] },  // Inst #41 = ICALL_BRANCH_FUNNEL
+  { 3, &ARCDescs.OperandInfo[37] },  // Inst #40 = PATCHABLE_TYPED_EVENT_CALL
+  { 2, &ARCDescs.OperandInfo[35] },  // Inst #39 = PATCHABLE_EVENT_CALL
+  { 0, &ARCDescs.OperandInfo[1] },  // Inst #38 = PATCHABLE_TAIL_CALL
+  { 0, &ARCDescs.OperandInfo[1] },  // Inst #37 = PATCHABLE_FUNCTION_EXIT
+  { 0, &ARCDescs.OperandInfo[1] },  // Inst #36 = PATCHABLE_RET
+  { 0, &ARCDescs.OperandInfo[1] },  // Inst #35 = PATCHABLE_FUNCTION_ENTER
+  { 0, &ARCDescs.OperandInfo[1] },  // Inst #34 = PATCHABLE_OP
+  { 1, &ARCDescs.OperandInfo[0] },  // Inst #33 = FAULTING_OP
+  { 2, &ARCDescs.OperandInfo[33] },  // Inst #32 = LOCAL_ESCAPE
+  { 0, &ARCDescs.OperandInfo[1] },  // Inst #31 = STATEPOINT
+  { 3, &ARCDescs.OperandInfo[30] },  // Inst #30 = PREALLOCATED_ARG
+  { 1, &ARCDescs.OperandInfo[1] },  // Inst #29 = PREALLOCATED_SETUP
+  { 1, &ARCDescs.OperandInfo[29] },  // Inst #28 = LOAD_STACK_GUARD
+  { 6, &ARCDescs.OperandInfo[23] },  // Inst #27 = PATCHPOINT
+  { 0, &ARCDescs.OperandInfo[1] },  // Inst #26 = FENTRY_CALL
+  { 2, &ARCDescs.OperandInfo[21] },  // Inst #25 = STACKMAP
+  { 2, &ARCDescs.OperandInfo[19] },  // Inst #24 = ARITH_FENCE
+  { 4, &ARCDescs.OperandInfo[15] },  // Inst #23 = PSEUDO_PROBE
+  { 1, &ARCDescs.OperandInfo[1] },  // Inst #22 = LIFETIME_END
+  { 1, &ARCDescs.OperandInfo[1] },  // Inst #21 = LIFETIME_START
+  { 0, &ARCDescs.OperandInfo[1] },  // Inst #20 = BUNDLE
+  { 2, &ARCDescs.OperandInfo[13] },  // Inst #19 = COPY
+  { 2, &ARCDescs.OperandInfo[13] },  // Inst #18 = REG_SEQUENCE
+  { 1, &ARCDescs.OperandInfo[0] },  // Inst #17 = DBG_LABEL
+  { 0, &ARCDescs.OperandInfo[1] },  // Inst #16 = DBG_PHI
+  { 0, &ARCDescs.OperandInfo[1] },  // Inst #15 = DBG_INSTR_REF
+  { 0, &ARCDescs.OperandInfo[1] },  // Inst #14 = DBG_VALUE_LIST
+  { 0, &ARCDescs.OperandInfo[1] },  // Inst #13 = DBG_VALUE
+  { 3, &ARCDescs.OperandInfo[2] },  // Inst #12 = COPY_TO_REGCLASS
+  { 4, &ARCDescs.OperandInfo[9] },  // Inst #11 = SUBREG_TO_REG
+  { 1, &ARCDescs.OperandInfo[0] },  // Inst #10 = IMPLICIT_DEF
+  { 4, &ARCDescs.OperandInfo[5] },  // Inst #9 = INSERT_SUBREG
+  { 3, &ARCDescs.OperandInfo[2] },  // Inst #8 = EXTRACT_SUBREG
+  { 0, &ARCDescs.OperandInfo[1] },  // Inst #7 = KILL
+  { 1, &ARCDescs.OperandInfo[1] },  // Inst #6 = ANNOTATION_LABEL
+  { 1, &ARCDescs.OperandInfo[1] },  // Inst #5 = GC_LABEL
+  { 1, &ARCDescs.OperandInfo[1] },  // Inst #4 = EH_LABEL
+  { 1, &ARCDescs.OperandInfo[1] },  // Inst #3 = CFI_INSTRUCTION
+  { 0, &ARCDescs.OperandInfo[1] },  // Inst #2 = INLINEASM_BR
+  { 0, &ARCDescs.OperandInfo[1] },  // Inst #1 = INLINEASM
+  { 1, &ARCDescs.OperandInfo[0] },  // Inst #0 = PHI
+  }, {
+    /* 0 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
+    /* 1 */
+    /* 1 */ { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
+    /* 2 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
+    /* 5 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
+    /* 9 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
+    /* 13 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
+    /* 15 */ { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
+    /* 19 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, CONSTRAINT_MCOI_TIED_TO(0) },
+    /* 21 */ { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
+    /* 23 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
+    /* 29 */ { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 },
+    /* 30 */ { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
+    /* 33 */ { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
+    /* 35 */ { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
+    /* 37 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
+    /* 40 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_IMM_0, 0 },
+    /* 43 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
+    /* 46 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
+    /* 50 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
+    /* 51 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
+    /* 53 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_IMM_0, 0 },
+    /* 56 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 },
+    /* 58 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_IMM_0, 0 },
+    /* 62 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
+    /* 64 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
+    /* 67 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
+    /* 72 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
+    /* 77 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
+    /* 82 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
+    /* 86 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
+    /* 89 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
+    /* 93 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
+    /* 96 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 },
+    /* 99 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 },
+    /* 103 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 },
+    /* 107 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 },
+    /* 112 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_IMM_0, 0 },
+    /* 116 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 },
+    /* 119 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 },
+    /* 123 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 },
+    /* 126 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
+    /* 130 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
+    /* 132 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_IMM_0, 0 },
+    /* 136 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 },
+    /* 140 */ { -1, 0, MCOI_OPERAND_PCREL, 0 }, { ARC_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARC_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
+    /* 144 */ { -1, 0, MCOI_OPERAND_PCREL, 0 }, { ARC_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
+    /* 148 */ { ARC_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARC_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
+    /* 150 */ { ARC_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
+    /* 153 */ { ARC_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARC_GPR32RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
+    /* 156 */ { ARC_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARC_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) },
+    /* 160 */ { ARC_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARC_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
+    /* 163 */ { ARC_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARC_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARC_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
+    /* 166 */ { ARC_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARC_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
+    /* 169 */ { ARC_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARC_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
+    /* 172 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
+    /* 174 */ { ARC_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
+    /* 176 */ { ARC_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
+    /* 178 */ { -1, 0, MCOI_OPERAND_PCREL, 0 },
+    /* 179 */ { ARC_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 },
+    /* 181 */ { -1, 0, MCOI_OPERAND_PCREL, 0 }, { ARC_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
+    /* 185 */ { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
+    /* 187 */ { ARC_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
+    /* 188 */ { ARC_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARC_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARC_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
+    /* 192 */ { ARC_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARC_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARC_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
+    /* 196 */ { ARC_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARC_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) },
+    /* 200 */ { -1, 0, MCOI_OPERAND_REGISTER, 0 },
+    /* 201 */ { -1, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
+    /* 203 */ { ARC_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARC_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARC_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
+  }, {
+    /* 0 */
+    /* 0 */ ARC_SP, ARC_SP,
+    /* 2 */ ARC_STATUS32,
+    /* 3 */ ARC_STATUS32, ARC_STATUS32,
+    /* 5 */ ARC_SP, ARC_BLINK,
+    /* 7 */ ARC_BLINK, ARC_SP,
+  }
+};
+
+#endif // GET_INSTRINFO_MC_DESC
+
+#ifdef GET_COMPUTE_FEATURES
+#undef GET_COMPUTE_FEATURES
+
+#endif // GET_COMPUTE_FEATURES
+
+#ifdef GET_AVAILABLE_OPCODE_CHECKER
+#undef GET_AVAILABLE_OPCODE_CHECKER
+
+#endif // GET_AVAILABLE_OPCODE_CHECKER
+
+#ifdef GET_INSTRMAP_INFO
+#undef GET_INSTRMAP_INFO
+enum AA {
+	AA_PostIncAM
+};
+
+// getPostIncOpcode
+int getPostIncOpcode(uint16_t Opcode) {
+static const uint16_t getPostIncOpcodeTable[][2] = {
+  { ARC_LDB_DI_rs9, ARC_LDB_DI_AB_rs9 },
+  { ARC_LDB_X_DI_rs9, ARC_LDB_X_DI_AB_rs9 },
+  { ARC_LDB_X_rs9, ARC_LDB_X_AB_rs9 },
+  { ARC_LDB_rs9, ARC_LDB_AB_rs9 },
+  { ARC_LDH_DI_rs9, ARC_LDH_DI_AB_rs9 },
+  { ARC_LDH_X_DI_rs9, ARC_LDH_X_DI_AB_rs9 },
+  { ARC_LDH_X_rs9, ARC_LDH_X_AB_rs9 },
+  { ARC_LDH_rs9, ARC_LDH_AB_rs9 },
+  { ARC_LD_DI_rs9, ARC_LD_DI_AB_rs9 },
+  { ARC_LD_rs9, ARC_LD_AB_rs9 },
+  { ARC_STB_DI_rs9, ARC_STB_DI_AB_rs9 },
+  { ARC_STB_rs9, ARC_STB_AB_rs9 },
+  { ARC_STH_DI_rs9, ARC_STH_DI_AB_rs9 },
+  { ARC_STH_rs9, ARC_STH_AB_rs9 },
+  { ARC_ST_DI_rs9, ARC_ST_DI_AB_rs9 },
+  { ARC_ST_rs9, ARC_ST_AB_rs9 },
+}; // End of getPostIncOpcodeTable
+
+  unsigned mid;
+  unsigned start = 0;
+  unsigned end = 16;
+  while (start < end) {
+    mid = start + (end - start) / 2;
+    if (Opcode == getPostIncOpcodeTable[mid][0]) {
+      break;
+    }
+    if (Opcode < getPostIncOpcodeTable[mid][0])
+      end = mid;
+    else
+      start = mid + 1;
+  }
+  if (start == end)
+    return -1; // Instruction doesn't exist in this table.
+
+  return getPostIncOpcodeTable[mid][1];
+}
+
+#endif // GET_INSTRMAP_INFO
+
diff --git a/arch/ARC/ARCGenRegisterInfo.inc b/arch/ARC/ARCGenRegisterInfo.inc
new file mode 100644
index 0000000000..6d1cdc5f30
--- /dev/null
+++ b/arch/ARC/ARCGenRegisterInfo.inc
@@ -0,0 +1,296 @@
+#ifdef GET_REGINFO_ENUM
+#undef GET_REGINFO_ENUM
+
+enum {
+  ARC_NoRegister,
+  ARC_BLINK = 1,
+  ARC_FP = 2,
+  ARC_GP = 3,
+  ARC_ILINK = 4,
+  ARC_SP = 5,
+  ARC_R0 = 6,
+  ARC_R1 = 7,
+  ARC_R2 = 8,
+  ARC_R3 = 9,
+  ARC_R4 = 10,
+  ARC_R5 = 11,
+  ARC_R6 = 12,
+  ARC_R7 = 13,
+  ARC_R8 = 14,
+  ARC_R9 = 15,
+  ARC_R10 = 16,
+  ARC_R11 = 17,
+  ARC_R12 = 18,
+  ARC_R13 = 19,
+  ARC_R14 = 20,
+  ARC_R15 = 21,
+  ARC_R16 = 22,
+  ARC_R17 = 23,
+  ARC_R18 = 24,
+  ARC_R19 = 25,
+  ARC_R20 = 26,
+  ARC_R21 = 27,
+  ARC_R22 = 28,
+  ARC_R23 = 29,
+  ARC_R24 = 30,
+  ARC_R25 = 31,
+  ARC_R30 = 32,
+  ARC_R32 = 33,
+  ARC_R33 = 34,
+  ARC_R34 = 35,
+  ARC_R35 = 36,
+  ARC_R36 = 37,
+  ARC_R37 = 38,
+  ARC_R38 = 39,
+  ARC_R39 = 40,
+  ARC_R40 = 41,
+  ARC_R41 = 42,
+  ARC_R42 = 43,
+  ARC_R43 = 44,
+  ARC_R44 = 45,
+  ARC_R45 = 46,
+  ARC_R46 = 47,
+  ARC_R47 = 48,
+  ARC_R48 = 49,
+  ARC_R49 = 50,
+  ARC_R50 = 51,
+  ARC_R51 = 52,
+  ARC_R52 = 53,
+  ARC_R53 = 54,
+  ARC_R54 = 55,
+  ARC_R55 = 56,
+  ARC_R56 = 57,
+  ARC_R57 = 58,
+  ARC_R58 = 59,
+  ARC_R59 = 60,
+  ARC_R60 = 61,
+  ARC_R61 = 62,
+  ARC_R62 = 63,
+  ARC_R63 = 64,
+  ARC_STATUS32 = 65,
+  NUM_TARGET_REGS // 66
+};
+
+// Register classes
+
+enum {
+  ARC_SREGRegClassID = 0,
+  ARC_GPR_SRegClassID = 1,
+  ARC_GPR32RegClassID = 2,
+  ARC_GPR32_and_GPR_SRegClassID = 3,
+
+};
+#endif // GET_REGINFO_ENUM
+
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+#ifdef GET_REGINFO_MC_DESC
+#undef GET_REGINFO_MC_DESC
+
+static const MCPhysReg ARCRegDiffLists[] = {
+  /* 0 */ 0,
+};
+
+static const uint16_t ARCSubRegIdxLists[] = {
+  /* 0 */ 0,
+};
+
+static const MCRegisterDesc ARCRegDesc[] = { // Descriptors
+  { 3, 0, 0, 0, 0, 0 },
+  { 235, 0, 0, 0, 0, 0 },
+  { 247, 0, 0, 0, 1, 0 },
+  { 250, 0, 0, 0, 2, 0 },
+  { 241, 0, 0, 0, 3, 0 },
+  { 253, 0, 0, 0, 4, 0 },
+  { 24, 0, 0, 0, 5, 0 },
+  { 47, 0, 0, 0, 6, 0 },
+  { 83, 0, 0, 0, 7, 0 },
+  { 110, 0, 0, 0, 8, 0 },
+  { 133, 0, 0, 0, 9, 0 },
+  { 156, 0, 0, 0, 10, 0 },
+  { 175, 0, 0, 0, 11, 0 },
+  { 194, 0, 0, 0, 12, 0 },
+  { 213, 0, 0, 0, 13, 0 },
+  { 232, 0, 0, 0, 14, 0 },
+  { 0, 0, 0, 0, 15, 0 },
+  { 27, 0, 0, 0, 16, 0 },
+  { 50, 0, 0, 0, 17, 0 },
+  { 86, 0, 0, 0, 18, 0 },
+  { 113, 0, 0, 0, 19, 0 },
+  { 136, 0, 0, 0, 20, 0 },
+  { 159, 0, 0, 0, 21, 0 },
+  { 178, 0, 0, 0, 22, 0 },
+  { 197, 0, 0, 0, 23, 0 },
+  { 216, 0, 0, 0, 24, 0 },
+  { 4, 0, 0, 0, 25, 0 },
+  { 31, 0, 0, 0, 26, 0 },
+  { 54, 0, 0, 0, 27, 0 },
+  { 90, 0, 0, 0, 28, 0 },
+  { 117, 0, 0, 0, 29, 0 },
+  { 140, 0, 0, 0, 30, 0 },
+  { 8, 0, 0, 0, 31, 0 },
+  { 58, 0, 0, 0, 32, 0 },
+  { 94, 0, 0, 0, 33, 0 },
+  { 121, 0, 0, 0, 34, 0 },
+  { 144, 0, 0, 0, 35, 0 },
+  { 163, 0, 0, 0, 36, 0 },
+  { 182, 0, 0, 0, 37, 0 },
+  { 201, 0, 0, 0, 38, 0 },
+  { 220, 0, 0, 0, 39, 0 },
+  { 12, 0, 0, 0, 40, 0 },
+  { 35, 0, 0, 0, 41, 0 },
+  { 71, 0, 0, 0, 42, 0 },
+  { 98, 0, 0, 0, 43, 0 },
+  { 125, 0, 0, 0, 44, 0 },
+  { 148, 0, 0, 0, 45, 0 },
+  { 167, 0, 0, 0, 46, 0 },
+  { 186, 0, 0, 0, 47, 0 },
+  { 205, 0, 0, 0, 48, 0 },
+  { 224, 0, 0, 0, 49, 0 },
+  { 16, 0, 0, 0, 50, 0 },
+  { 39, 0, 0, 0, 51, 0 },
+  { 75, 0, 0, 0, 52, 0 },
+  { 102, 0, 0, 0, 53, 0 },
+  { 129, 0, 0, 0, 54, 0 },
+  { 152, 0, 0, 0, 55, 0 },
+  { 171, 0, 0, 0, 56, 0 },
+  { 190, 0, 0, 0, 57, 0 },
+  { 209, 0, 0, 0, 58, 0 },
+  { 228, 0, 0, 0, 59, 0 },
+  { 20, 0, 0, 0, 60, 0 },
+  { 43, 0, 0, 0, 61, 0 },
+  { 79, 0, 0, 0, 62, 0 },
+  { 106, 0, 0, 0, 63, 0 },
+  { 62, 0, 0, 0, 64, 0 },
+};
+
+  // SREG Register Class...
+  static const MCPhysReg SREG[] = {
+    ARC_STATUS32, 
+  };
+
+  // SREG Bit set.
+  static const uint8_t SREGBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 
+  };
+
+  // GPR_S Register Class...
+  static const MCPhysReg GPR_S[] = {
+    ARC_R0, ARC_R1, ARC_R2, ARC_R3, ARC_R12, ARC_R13, ARC_R14, ARC_R15, 
+  };
+
+  // GPR_S Bit set.
+  static const uint8_t GPR_SBits[] = {
+    0xc0, 0x03, 0x3c, 
+  };
+
+  // GPR32 Register Class...
+  static const MCPhysReg GPR32[] = {
+    ARC_R0, ARC_R1, ARC_R2, ARC_R3, ARC_R4, ARC_R5, ARC_R6, ARC_R7, ARC_R8, ARC_R9, ARC_R10, ARC_R11, ARC_R12, ARC_R13, ARC_R14, ARC_R15, ARC_R16, ARC_R17, ARC_R18, ARC_R19, ARC_R20, ARC_R21, ARC_R22, ARC_R23, ARC_R24, ARC_R25, ARC_GP, ARC_FP, ARC_SP, ARC_ILINK, ARC_R30, ARC_BLINK, ARC_R32, ARC_R33, ARC_R34, ARC_R35, ARC_R36, ARC_R37, ARC_R38, ARC_R39, ARC_R40, ARC_R41, ARC_R42, ARC_R43, ARC_R44, ARC_R45, ARC_R46, ARC_R47, ARC_R48, ARC_R49, ARC_R50, ARC_R51, ARC_R52, ARC_R53, ARC_R54, ARC_R55, ARC_R56, ARC_R57, ARC_R58, ARC_R59, ARC_R60, ARC_R61, ARC_R62, ARC_R63, 
+  };
+
+  // GPR32 Bit set.
+  static const uint8_t GPR32Bits[] = {
+    0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01, 
+  };
+
+  // GPR32_and_GPR_S Register Class...
+  static const MCPhysReg GPR32_and_GPR_S[] = {
+    ARC_R0, ARC_R1, ARC_R2, ARC_R3, ARC_R12, ARC_R13, ARC_R14, ARC_R15, 
+  };
+
+  // GPR32_and_GPR_S Bit set.
+  static const uint8_t GPR32_and_GPR_SBits[] = {
+    0xc0, 0x03, 0x3c, 
+  };
+
+static const MCRegisterClass ARCMCRegisterClasses[] = {
+  { SREG, SREGBits, sizeof(SREGBits) },
+  { GPR_S, GPR_SBits, sizeof(GPR_SBits) },
+  { GPR32, GPR32Bits, sizeof(GPR32Bits) },
+  { GPR32_and_GPR_S, GPR32_and_GPR_SBits, sizeof(GPR32_and_GPR_SBits) },
+};
+
+static const uint16_t ARCRegEncodingTable[] = {
+  0,
+  31,
+  27,
+  26,
+  29,
+  28,
+  0,
+  1,
+  2,
+  3,
+  4,
+  5,
+  6,
+  7,
+  8,
+  9,
+  10,
+  11,
+  12,
+  13,
+  14,
+  15,
+  16,
+  17,
+  18,
+  19,
+  20,
+  21,
+  22,
+  23,
+  24,
+  25,
+  30,
+  32,
+  33,
+  34,
+  35,
+  36,
+  37,
+  38,
+  39,
+  40,
+  41,
+  42,
+  43,
+  44,
+  45,
+  46,
+  47,
+  48,
+  49,
+  50,
+  51,
+  52,
+  53,
+  54,
+  55,
+  56,
+  57,
+  58,
+  59,
+  60,
+  61,
+  62,
+  63,
+  10,
+};
+#endif // GET_REGINFO_MC_DESC
+
+
+
diff --git a/arch/ARC/ARCGenSubtargetInfo.inc b/arch/ARC/ARCGenSubtargetInfo.inc
new file mode 100644
index 0000000000..be2c157f00
--- /dev/null
+++ b/arch/ARC/ARCGenSubtargetInfo.inc
@@ -0,0 +1,24 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+#ifdef GET_SUBTARGETINFO_ENUM
+#undef GET_SUBTARGETINFO_ENUM
+
+enum {
+  ARC_FeatureNORM = 0,
+  ARC_NumSubtargetFeatures = 1
+};
+#endif // GET_SUBTARGETINFO_ENUM
+
+
+
diff --git a/arch/ARC/ARCInfo.h b/arch/ARC/ARCInfo.h
new file mode 100644
index 0000000000..715a868816
--- /dev/null
+++ b/arch/ARC/ARCInfo.h
@@ -0,0 +1,72 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Only small edits allowed. */
+/* For multiple similar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+//===- ARCInfo.h - Additional ARC Info --------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains small standalone helper functions and enum definitions for
+// the ARC target useful for the compiler back-end and the MC libraries.
+// As such, it deliberately does not include references to LLVM core
+// code gen types, passes, etc..
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_ARC_MCTARGETDESC_ARCINFO_H
+#define LLVM_LIB_TARGET_ARC_MCTARGETDESC_ARCINFO_H
+
+// Enums corresponding to ARC condition codes
+// CS namespace begin: ARCCC
+
+typedef enum ARCCondCode {
+	ARCCC_AL = 0x0,
+	ARCCC_EQ = 0x1,
+	ARCCC_NE = 0x2,
+	ARCCC_P = 0x3,
+	ARCCC_N = 0x4,
+	ARCCC_LO = 0x5,
+	ARCCC_HS = 0x6,
+	ARCCC_VS = 0x7,
+	ARCCC_VC = 0x8,
+	ARCCC_GT = 0x9,
+	ARCCC_GE = 0xa,
+	ARCCC_LT = 0xb,
+	ARCCC_LE = 0xc,
+	ARCCC_HI = 0xd,
+	ARCCC_LS = 0xe,
+	ARCCC_PNZ = 0xf,
+	ARCCC_Z = 0x11, // Low 4-bits = EQ
+	ARCCC_NZ = 0x12 // Low 4-bits = NE
+} ARCCC_CondCode;
+
+typedef enum BRCondCode {
+	ARCCC_BREQ = 0x0,
+	ARCCC_BRNE = 0x1,
+	ARCCC_BRLT = 0x2,
+	ARCCC_BRGE = 0x3,
+	ARCCC_BRLO = 0x4,
+	ARCCC_BRHS = 0x5
+} ARCCC_BRCondCode;
+
+// CS namespace end: ARCCC
+
+// end namespace ARCCC
+
+// end namespace llvm
+
+#endif
diff --git a/arch/ARC/ARCInstPrinter.c b/arch/ARC/ARCInstPrinter.c
new file mode 100644
index 0000000000..deb02600ba
--- /dev/null
+++ b/arch/ARC/ARCInstPrinter.c
@@ -0,0 +1,210 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Only small edits allowed. */
+/* For multiple similar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+//===- ARCInstPrinter.cpp - ARC MCInst to assembly syntax -------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This class prints an ARC MCInst to a .s file.
+//
+//===----------------------------------------------------------------------===//
+
+#ifdef CAPSTONE_HAS_ARC
+
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include <capstone/platform.h>
+
+#include "../../SStream.h"
+#include "../../MCInst.h"
+#include "../../MCInstPrinter.h"
+
+#include "ARCInfo.h"
+#include "ARCInstPrinter.h"
+#include "ARCLinkage.h"
+#include "ARCMapping.h"
+
+#define CONCAT(a, b) CONCAT_(a, b)
+#define CONCAT_(a, b) a##_##b
+
+#define DEBUG_TYPE "asm-printer"
+
+#include "ARCGenAsmWriter.inc"
+
+static const char *ARCBRCondCodeToString(ARCCC_BRCondCode BRCC)
+{
+	switch (BRCC) {
+	case ARCCC_BREQ:
+		return "eq";
+	case ARCCC_BRNE:
+		return "ne";
+	case ARCCC_BRLT:
+		return "lt";
+	case ARCCC_BRGE:
+		return "ge";
+	case ARCCC_BRLO:
+		return "lo";
+	case ARCCC_BRHS:
+		return "hs";
+	}
+	// CS_ASSERT(0 && "Unknown condition code passed");
+	return "";
+}
+
+static const char *ARCCondCodeToString(ARCCC_CondCode CC)
+{
+	switch (CC) {
+	case ARCCC_EQ:
+		return "eq";
+	case ARCCC_NE:
+		return "ne";
+	case ARCCC_P:
+		return "p";
+	case ARCCC_N:
+		return "n";
+	case ARCCC_HS:
+		return "hs";
+	case ARCCC_LO:
+		return "lo";
+	case ARCCC_GT:
+		return "gt";
+	case ARCCC_GE:
+		return "ge";
+	case ARCCC_VS:
+		return "vs";
+	case ARCCC_VC:
+		return "vc";
+	case ARCCC_LT:
+		return "lt";
+	case ARCCC_LE:
+		return "le";
+	case ARCCC_HI:
+		return "hi";
+	case ARCCC_LS:
+		return "ls";
+	case ARCCC_PNZ:
+		return "pnz";
+	case ARCCC_AL:
+		return "al";
+	case ARCCC_NZ:
+		return "nz";
+	case ARCCC_Z:
+		return "z";
+	}
+	// CS_ASSERT(0 && "Unknown condition code passed");
+	return "";
+}
+
+static void printRegName(SStream *OS, MCRegister Reg)
+{
+	SStream_concat0(OS, getRegisterName(Reg));
+}
+
+static void printInst(MCInst *MI, uint64_t Address, const char *Annot, SStream *O)
+{
+	printInstruction(MI, Address, O);
+}
+
+static void printOperand(MCInst *MI, unsigned OpNum, SStream *O)
+{
+	add_cs_detail(MI, ARC_OP_GROUP_Operand, OpNum);
+	MCOperand *Op = MCInst_getOperand(MI, (OpNum));
+	if (MCOperand_isReg(Op)) {
+		printRegName(O, MCOperand_getReg(Op));
+	} else if (MCOperand_isImm(Op)) {
+		SStream_concat(O, "%" PRId64, MCOperand_getImm(Op));
+	} else if (MCOperand_isExpr(Op)) {
+		printExpr(O, MCOperand_getExpr(Op));
+	}
+}
+
+static void printOperandAddr(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O)
+{
+	printOperand(MI, OpNum, O);
+}
+
+static void printMemOperandRI(MCInst *MI, unsigned OpNum, SStream *O)
+{
+	add_cs_detail(MI, ARC_OP_GROUP_MemOperandRI, OpNum);
+	MCOperand *base = MCInst_getOperand(MI, (OpNum));
+	MCOperand *offset = MCInst_getOperand(MI, (OpNum + 1));
+	CS_ASSERT((MCOperand_isReg(base) && "Base should be register."));
+	CS_ASSERT((MCOperand_isImm(offset) && "Offset should be immediate."));
+	printRegName(O, MCOperand_getReg(base));
+	SStream_concat(O, "%s", ",");
+	printInt64(O, MCOperand_getImm(offset));
+}
+
+static void printPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O)
+{
+	add_cs_detail(MI, ARC_OP_GROUP_PredicateOperand, OpNum);
+
+	MCOperand *Op = MCInst_getOperand(MI, (OpNum));
+	CS_ASSERT((MCOperand_isImm(Op) && "Predicate operand is immediate."));
+	SStream_concat0(
+		O, ARCCondCodeToString((ARCCC_CondCode)MCOperand_getImm(Op)));
+}
+
+static void printBRCCPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O)
+{
+	add_cs_detail(MI, ARC_OP_GROUP_BRCCPredicateOperand, OpNum);
+	MCOperand *Op = MCInst_getOperand(MI, (OpNum));
+	CS_ASSERT((MCOperand_isImm(Op) && "Predicate operand is immediate."));
+	SStream_concat0(O, ARCBRCondCodeToString(
+				   (ARCCC_BRCondCode)MCOperand_getImm(Op)));
+}
+
+static void printCCOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	add_cs_detail(MI, ARC_OP_GROUP_CCOperand, OpNum);
+	SStream_concat0(O, ARCCondCodeToString((ARCCC_CondCode)MCOperand_getImm(
+				   MCInst_getOperand(MI, (OpNum)))));
+}
+
+static void printU6ShiftedBy(unsigned ShiftBy, MCInst *MI, int OpNum, SStream *O)
+{
+	MCOperand *MO = MCInst_getOperand(MI, (OpNum));
+	if (MCOperand_isImm(MO)) {
+		unsigned Value = MCOperand_getImm(MO);
+		unsigned Value2 = Value >> ShiftBy;
+		if (Value2 > 0x3F || (Value2 << ShiftBy != Value)) {
+			CS_ASSERT((false && "instruction has wrong format"));
+		}
+	}
+	printOperand(MI, OpNum, O);
+}
+
+static void printU6(MCInst *MI, int OpNum, SStream *O)
+{
+	add_cs_detail(MI, ARC_OP_GROUP_U6, OpNum);
+	printU6ShiftedBy(0, MI, OpNum, O);
+}
+
+void ARC_LLVM_printInst(MCInst *MI, uint64_t Address, const char *Annot,
+			      SStream *O)
+{
+	printInst(MI, Address, Annot, O);
+}
+
+const char *ARC_LLVM_getRegisterName(unsigned RegNo)
+{
+	return getRegisterName(RegNo);
+}
+
+#endif
\ No newline at end of file
diff --git a/arch/ARC/ARCInstPrinter.h b/arch/ARC/ARCInstPrinter.h
new file mode 100644
index 0000000000..6ae840b9da
--- /dev/null
+++ b/arch/ARC/ARCInstPrinter.h
@@ -0,0 +1,58 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Only small edits allowed. */
+/* For multiple similar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+//===- ARCInstPrinter.h - Convert ARC MCInst to assembly syntax -*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// \file
+/// This file contains the declaration of the ARCInstPrinter class,
+/// which is used to print ARC MCInst to a .s file.
+///
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_ARC_INSTPRINTER_ARCINSTPRINTER_H
+#define LLVM_LIB_TARGET_ARC_INSTPRINTER_ARCINSTPRINTER_H
+
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include <capstone/platform.h>
+
+#include "../../SStream.h"
+#include "../../MCInst.h"
+
+#define CONCAT(a, b) CONCAT_(a, b)
+#define CONCAT_(a, b) a##_##b
+
+// Autogenerated by tblgen.
+static void printInstruction(MCInst *MI, uint64_t Address, SStream *O);
+static void printRegName(SStream *OS, MCRegister Reg);
+static void printInst(MCInst *MI, uint64_t Address, const char *Annot, SStream *O);
+static void printCCOperand(MCInst *MI, int OpNum, SStream *O);
+static void printU6(MCInst *MI, int OpNum, SStream *O);
+static void printMemOperandRI(MCInst *MI, unsigned OpNum, SStream *O);
+static void printOperand(MCInst *MI, unsigned OpNum, SStream *O);
+static void printOperandAddr(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O);
+static void printPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O);
+static void printBRCCPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O);
+static void printU6ShiftedBy(unsigned ShiftBy, MCInst *MI, int OpNum, SStream *O);
+;
+// end namespace llvm
+
+#endif // LLVM_LIB_TARGET_ARC_INSTPRINTER_ARCINSTPRINTER_H
diff --git a/arch/ARC/ARCLinkage.h b/arch/ARC/ARCLinkage.h
new file mode 100644
index 0000000000..d0c2f6240e
--- /dev/null
+++ b/arch/ARC/ARCLinkage.h
@@ -0,0 +1,23 @@
+/* Capstone Disassembly Engine */
+/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2024 */
+
+#ifndef CS_ARC_LINKAGE_H
+#define CS_ARC_LINKAGE_H
+
+// Function definitions to call static LLVM functions.
+
+#include "../../MCDisassembler.h"
+#include "../../MCInst.h"
+#include "../../MCRegisterInfo.h"
+#include "../../SStream.h"
+#include "capstone/capstone.h"
+
+const char *ARC_LLVM_getRegisterName(unsigned RegNo);
+void ARC_LLVM_printInst(MCInst *MI, uint64_t Address, const char *Annot,
+			      SStream *O);
+DecodeStatus ARC_LLVM_getInstruction(MCInst *MI, uint64_t *Size,
+					   const uint8_t *Bytes,
+					   size_t BytesLen, uint64_t Address,
+					   SStream *CS);
+
+#endif // CS_ARC_LINKAGE_H
diff --git a/arch/ARC/ARCMapping.c b/arch/ARC/ARCMapping.c
new file mode 100644
index 0000000000..996d71866b
--- /dev/null
+++ b/arch/ARC/ARCMapping.c
@@ -0,0 +1,288 @@
+/* Capstone Disassembly Engine */
+/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2024 */
+
+#ifdef CAPSTONE_HAS_ARC
+
+#include <stdio.h>
+#include <string.h>
+
+#include <capstone/capstone.h>
+#include <capstone/arc.h>
+
+#include "../../Mapping.h"
+#include "../../MCDisassembler.h"
+#include "../../cs_priv.h"
+#include "../../cs_simple_types.h"
+
+#include "ARCMapping.h"
+#include "ARCLinkage.h"
+
+#define GET_REGINFO_ENUM
+#define GET_REGINFO_MC_DESC
+#include "ARCGenRegisterInfo.inc"
+
+#define GET_INSTRINFO_ENUM
+#include "ARCGenInstrInfo.inc"
+
+void ARC_init_mri(MCRegisterInfo *MRI)
+{
+	MCRegisterInfo_InitMCRegisterInfo(MRI, ARCRegDesc,
+					  sizeof(ARCRegDesc), 0, 0,
+					  ARCMCRegisterClasses,
+					  ARR_SIZE(ARCMCRegisterClasses),
+					  0, 0, ARCRegDiffLists, 0,
+					  ARCSubRegIdxLists,
+					  ARR_SIZE(ARCSubRegIdxLists), 0);
+}
+
+const char *ARC_reg_name(csh handle, unsigned int reg)
+{
+	return ARC_LLVM_getRegisterName(reg);
+}
+
+void ARC_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
+{
+	// Not used by ARC. Information is set after disassembly.
+}
+
+static const char *const insn_name_maps[] = {
+#include "ARCGenCSMappingInsnName.inc"
+};
+
+const char *ARC_insn_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	if (id < ARR_SIZE(insn_name_maps))
+		return insn_name_maps[id];
+	// not found
+	return NULL;
+#else
+	return NULL;
+#endif
+}
+
+#ifndef CAPSTONE_DIET
+static const name_map group_name_maps[] = {
+	{ ARC_GRP_INVALID, NULL },
+
+	{ ARC_GRP_JUMP, "jump" },
+	{ ARC_GRP_CALL, "call" },
+	{ ARC_GRP_RET, "return" },
+	{ ARC_GRP_BRANCH_RELATIVE, "branch_relative" },
+
+};
+#endif
+
+const char *ARC_group_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
+#else
+	return NULL;
+#endif
+}
+
+void ARC_reg_access(const cs_insn *insn, cs_regs regs_read,
+			  uint8_t *regs_read_count, cs_regs regs_write,
+			  uint8_t *regs_write_count)
+{
+	uint8_t i;
+	uint8_t read_count, write_count;
+	cs_arc *arc = &(insn->detail->arc);
+
+	read_count = insn->detail->regs_read_count;
+	write_count = insn->detail->regs_write_count;
+
+	// implicit registers
+	memcpy(regs_read, insn->detail->regs_read,
+	       read_count * sizeof(insn->detail->regs_read[0]));
+	memcpy(regs_write, insn->detail->regs_write,
+	       write_count * sizeof(insn->detail->regs_write[0]));
+
+	// explicit registers
+	for (i = 0; i < arc->op_count; i++) {
+		cs_arc_op *op = &(arc->operands[i]);
+		switch ((int)op->type) {
+		case ARC_OP_REG:
+			if ((op->access & CS_AC_READ) &&
+			    !arr_exist(regs_read, read_count, op->reg)) {
+				regs_read[read_count] = (uint16_t)op->reg;
+				read_count++;
+			}
+			if ((op->access & CS_AC_WRITE) &&
+			    !arr_exist(regs_write, write_count, op->reg)) {
+				regs_write[write_count] = (uint16_t)op->reg;
+				write_count++;
+			}
+			break;
+		default:
+			break;
+		}
+	}
+
+	*regs_read_count = read_count;
+	*regs_write_count = write_count;
+}
+
+const insn_map arc_insns[] = {
+#include "ARCGenCSMappingInsn.inc"
+};
+
+void ARC_set_instr_map_data(MCInst *MI)
+{
+	map_cs_id(MI, arc_insns, ARR_SIZE(arc_insns));
+	map_implicit_reads(MI, arc_insns);
+	map_implicit_writes(MI, arc_insns);
+	map_groups(MI, arc_insns);
+}
+
+bool ARC_getInstruction(csh handle, const uint8_t *code, size_t code_len,
+			      MCInst *instr, uint16_t *size, uint64_t address,
+			      void *info)
+{
+	uint64_t temp_size;
+	ARC_init_cs_detail(instr);
+	bool Result = ARC_LLVM_getInstruction(instr, &temp_size, code,
+						    code_len, address, info) !=
+		      MCDisassembler_Fail;
+	ARC_set_instr_map_data(instr);
+	*size = temp_size;
+	return Result;
+}
+
+void ARC_printer(MCInst *MI, SStream *O,
+		       void * /* MCRegisterInfo* */ info)
+{
+	MCRegisterInfo *MRI = (MCRegisterInfo *)info;
+	MI->MRI = MRI;
+
+	ARC_LLVM_printInst(MI, MI->address, "", O);
+}
+
+void ARC_setup_op(cs_arc_op *op)
+{
+	memset(op, 0, sizeof(cs_arc_op));
+	op->type = ARC_OP_INVALID;
+}
+
+void ARC_init_cs_detail(MCInst *MI)
+{
+	if (!detail_is_set(MI)) {
+		return;
+	}
+	unsigned int i;
+
+	memset(get_detail(MI), 0,
+			offsetof(cs_detail, arc) + sizeof(cs_arc));
+
+	for (i = 0; i < ARR_SIZE(ARC_get_detail(MI)->operands);
+			i++)
+		ARC_setup_op(
+			&ARC_get_detail(MI)->operands[i]);
+}
+
+static const map_insn_ops insn_operands[] = {
+#include "ARCGenCSMappingInsnOp.inc"
+};
+
+void ARC_set_detail_op_imm(MCInst *MI, unsigned OpNum,
+				 arc_op_type ImmType, int64_t Imm)
+{
+	if (!detail_is_set(MI))
+		return;
+	ARC_check_safe_inc(MI);
+	CS_ASSERT((map_get_op_type(MI, OpNum) & ~CS_OP_MEM) == CS_OP_IMM);
+	CS_ASSERT(ImmType == ARC_OP_IMM);
+
+	ARC_get_detail_op(MI, 0)->type = ImmType;
+	ARC_get_detail_op(MI, 0)->imm = Imm;
+	ARC_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
+	ARC_inc_op_count(MI);
+}
+
+void ARC_set_detail_op_reg(MCInst *MI, unsigned OpNum, arc_reg Reg)
+{
+	if (!detail_is_set(MI))
+		return;
+	ARC_check_safe_inc(MI);
+	CS_ASSERT((map_get_op_type(MI, OpNum) & ~CS_OP_MEM) == CS_OP_REG);
+
+	ARC_get_detail_op(MI, 0)->type = ARC_OP_REG;
+	ARC_get_detail_op(MI, 0)->reg = Reg;
+	ARC_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
+	ARC_inc_op_count(MI);
+}
+
+void ARC_add_cs_detail(MCInst *MI, int op_group,
+			     va_list args)
+{
+	if (!detail_is_set(MI))
+		return;
+
+	unsigned OpNum = va_arg(args, unsigned);
+	cs_op_type op_type = map_get_op_type(MI, OpNum);
+	cs_op_type base_op_type = op_type;
+	cs_op_type offset_op_type;
+	// Fill cs_detail
+	switch (op_group) {
+	default:
+		printf("ERROR: Operand group %d not handled!\n", op_group);
+		CS_ASSERT_RET(0);
+	case ARC_OP_GROUP_Operand:
+		if (op_type == CS_OP_IMM) {
+			ARC_set_detail_op_imm(MI, OpNum, ARC_OP_IMM,
+						    MCInst_getOpVal(MI, OpNum));
+		} else if (op_type == CS_OP_REG) {
+			ARC_set_detail_op_reg(MI, OpNum,
+						    MCInst_getOpVal(MI, OpNum));
+		} else {
+			// Expression
+			ARC_set_detail_op_imm(MI, OpNum, ARC_OP_IMM,
+						    MCOperand_getImm(MCInst_getOperand(MI, OpNum)));
+		}
+		break;
+	case ARC_OP_GROUP_PredicateOperand:
+		if (op_type == CS_OP_IMM) {
+			ARC_set_detail_op_imm(MI, OpNum, ARC_OP_IMM,
+						    MCInst_getOpVal(MI, OpNum));
+		} else
+			CS_ASSERT(0 && "Op type not handled.");
+		break;
+	case ARC_OP_GROUP_MemOperandRI:
+		if (base_op_type == CS_OP_REG) {
+			ARC_set_detail_op_reg(MI, OpNum,
+						    MCInst_getOpVal(MI, OpNum));
+		} else
+			CS_ASSERT(0 && "Op type not handled.");
+		offset_op_type = map_get_op_type(MI, OpNum+1);
+		if (offset_op_type == CS_OP_IMM) {
+			ARC_set_detail_op_imm(MI, OpNum+1, ARC_OP_IMM,
+						    MCInst_getOpVal(MI, OpNum+1));
+		} else
+			CS_ASSERT(0 && "Op type not handled.");
+		break;
+	case ARC_OP_GROUP_BRCCPredicateOperand:
+		if (op_type == CS_OP_IMM) {
+			ARC_set_detail_op_imm(MI, OpNum, ARC_OP_IMM,
+						    MCInst_getOpVal(MI, OpNum));
+		} else
+			CS_ASSERT(0 && "Op type not handled.");
+		break;
+	case ARC_OP_GROUP_CCOperand:
+		if (op_type == CS_OP_IMM) {
+			ARC_set_detail_op_imm(MI, OpNum, ARC_OP_IMM,
+						    MCInst_getOpVal(MI, OpNum));
+		} else
+			CS_ASSERT(0 && "Op type not handled.");
+		break;
+	case ARC_OP_GROUP_U6:
+		if (op_type == CS_OP_IMM) {
+			ARC_set_detail_op_imm(MI, OpNum, ARC_OP_IMM,
+						    MCInst_getOpVal(MI, OpNum));
+		} else
+			CS_ASSERT(0 && "Op type not handled.");
+		break;		
+	}
+}
+
+#endif
\ No newline at end of file
diff --git a/arch/ARC/ARCMapping.h b/arch/ARC/ARCMapping.h
new file mode 100644
index 0000000000..ff48f83aa0
--- /dev/null
+++ b/arch/ARC/ARCMapping.h
@@ -0,0 +1,55 @@
+/* Capstone Disassembly Engine */
+/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2024 */
+
+#ifndef CS_ARC_MAP_H
+#define CS_ARC_MAP_H
+
+#include "../../Mapping.h"
+#include "../../include/capstone/capstone.h"
+#include "../../utils.h"
+
+typedef enum {
+#include "ARCGenCSOpGroup.inc"
+} arc_op_group;
+
+void ARC_init_mri(MCRegisterInfo *MRI);
+
+// return name of register in friendly string
+const char *ARC_reg_name(csh handle, unsigned int reg);
+
+void ARC_printer(MCInst *MI, SStream *O,
+		       void * /* MCRegisterInfo* */ info);
+
+// given internal insn id, return public instruction ID
+void ARC_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
+
+const char *ARC_insn_name(csh handle, unsigned int id);
+
+const char *ARC_group_name(csh handle, unsigned int id);
+
+void ARC_reg_access(const cs_insn *insn, cs_regs regs_read,
+			  uint8_t *regs_read_count, cs_regs regs_write,
+			  uint8_t *regs_write_count);
+
+bool ARC_getInstruction(csh handle, const uint8_t *code, size_t code_len,
+			      MCInst *instr, uint16_t *size, uint64_t address,
+			      void *info);
+
+// cs_detail related functions
+void ARC_init_cs_detail(MCInst *MI);
+void ARC_set_detail_op_imm(MCInst *MI, unsigned OpNum,
+				 arc_op_type ImmType, int64_t Imm);
+void ARC_add_cs_detail(MCInst *MI, int /* arc_op_group */ op_group,
+			     va_list args);
+static inline void add_cs_detail(MCInst *MI,
+				 int /* arc_op_group */ op_group, ...)
+{
+	if (!detail_is_set(MI))
+		return;
+	va_list args;
+	va_start(args, op_group);
+	ARC_add_cs_detail(MI, op_group, args);
+	va_end(args);
+}
+
+#endif
\ No newline at end of file
diff --git a/arch/ARC/ARCModule.c b/arch/ARC/ARCModule.c
new file mode 100644
index 0000000000..f42b613489
--- /dev/null
+++ b/arch/ARC/ARCModule.c
@@ -0,0 +1,52 @@
+/* Capstone Disassembly Engine */
+/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2024 */
+
+#ifdef CAPSTONE_HAS_ARC
+
+#include <capstone/capstone.h>
+
+#include "ARCModule.h"
+#include "../../MCRegisterInfo.h"
+#include "../../cs_priv.h"
+#include "ARCMapping.h"
+
+cs_err ARC_global_init(cs_struct *ud)
+{
+	MCRegisterInfo *mri;
+	mri = cs_mem_malloc(sizeof(*mri));
+
+	ARC_init_mri(mri);
+
+	ud->printer = ARC_printer;
+	ud->printer_info = mri;
+	ud->reg_name = ARC_reg_name;
+	ud->insn_id = ARC_get_insn_id;
+	ud->insn_name = ARC_insn_name;
+	ud->group_name = ARC_group_name;
+	ud->post_printer = NULL;
+#ifndef CAPSTONE_DIET
+	ud->reg_access = ARC_reg_access;
+#endif
+
+	ud->disasm = ARC_getInstruction;
+
+	return CS_ERR_OK;
+}
+
+cs_err ARC_option(cs_struct *handle, cs_opt_type type, size_t value)
+{
+	switch (type) {
+	case CS_OPT_MODE:
+		handle->mode = (cs_mode)value;
+		break;
+	case CS_OPT_SYNTAX:
+		handle->syntax |= (int)value;
+		break;
+	default:
+		break;
+	}
+
+	return CS_ERR_OK;
+}
+
+#endif
\ No newline at end of file
diff --git a/arch/ARC/ARCModule.h b/arch/ARC/ARCModule.h
new file mode 100644
index 0000000000..5dce75b2bf
--- /dev/null
+++ b/arch/ARC/ARCModule.h
@@ -0,0 +1,12 @@
+/* Capstone Disassembly Engine */
+/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2024 */
+
+#ifndef CS_ARC_MODULE_H
+#define CS_ARC_MODULE_H
+
+#include "../../utils.h"
+
+cs_err ARC_global_init(cs_struct *ud);
+cs_err ARC_option(cs_struct *handle, cs_opt_type type, size_t value);
+
+#endif
\ No newline at end of file
diff --git a/bindings/const_generator.py b/bindings/const_generator.py
index f81c02dc03..b2f9cefebc 100644
--- a/bindings/const_generator.py
+++ b/bindings/const_generator.py
@@ -8,7 +8,7 @@
 
 include = ['arm.h', 'aarch64.h', 'm68k.h', 'mips.h', 'x86.h', 'ppc.h', 'sparc.h', 'systemz.h', 'xcore.h',
            'tms320c64x.h', 'm680x.h', 'evm.h', 'mos65xx.h', 'wasm.h', 'bpf.h', 'riscv.h', 'sh.h', 'tricore.h',
-           'alpha.h', 'hppa.h', 'loongarch.h', 'xtensa.h']
+           'alpha.h', 'hppa.h', 'loongarch.h', 'arc.h', 'xtensa.h']
 
 template = {
     'java': {
@@ -63,6 +63,7 @@
             'hppa.h': 'hppa',
             'loongarch.h': 'loongarch',
             'xtensa.h': 'xtensa',
+            'arc.h': 'arc',
             'comment_open': '#',
             'comment_close': '',
         },
diff --git a/bindings/python/capstone/__init__.py b/bindings/python/capstone/__init__.py
index 0e88de7134..843b834dd5 100755
--- a/bindings/python/capstone/__init__.py
+++ b/bindings/python/capstone/__init__.py
@@ -42,6 +42,7 @@
     'CS_ARCH_HPPA',
     'CS_ARCH_LOONGARCH',
     'CS_ARCH_XTENSA',
+    'CS_ARCH_ARC',
     'CS_ARCH_ALL',
 
     'CS_MODE_LITTLE_ENDIAN',
@@ -269,7 +270,8 @@
 CS_ARCH_HPPA = 19
 CS_ARCH_LOONGARCH = 20
 CS_ARCH_XTENSA = 21
-CS_ARCH_MAX = 21
+CS_ARCH_ARC = 22
+CS_ARCH_MAX = 22
 CS_ARCH_ALL = 0xFFFF
 
 # disasm mode
@@ -561,7 +563,7 @@ def copy_ctypes_list(src):
 
 # Weird import placement because these modules are needed by the below code but need the above functions
 from . import arm, aarch64, m68k, mips, ppc, sparc, systemz, x86, xcore, tms320c64x, m680x, evm, mos65xx, wasm, bpf, \
-    riscv, sh, tricore, alpha, hppa, loongarch, xtensa
+    riscv, sh, tricore, alpha, hppa, loongarch, arc, xtensa
 
 
 class _cs_arch(ctypes.Union):
@@ -588,6 +590,7 @@ class _cs_arch(ctypes.Union):
         ('hppa', hppa.CsHPPA),
         ('loongarch', loongarch.CsLoongArch),
         ('xtensa', xtensa.CsXtensa),
+        ('arc', arc.CsARC),
     )
 
 
@@ -964,6 +967,8 @@ def __gen_detail(self):
             (self.operands) = hppa.get_arch_info(self._raw.detail.contents.arch.hppa)
         elif arch == CS_ARCH_LOONGARCH:
             (self.format, self.operands) = loongarch.get_arch_info(self._raw.detail.contents.arch.loongarch)
+        elif arch == CS_ARCH_ARC:
+            (self.operands) = arc.get_arch_info(self._raw.detail.contents.arch.arc)
         elif arch == CS_ARCH_XTENSA:
             (self.operands) = xtensa.get_arch_info(self._raw.detail.contents.arch.xtensa)
 
@@ -1440,7 +1445,8 @@ def debug():
         "m680x": CS_ARCH_M680X, 'evm': CS_ARCH_EVM, 'mos65xx': CS_ARCH_MOS65XX,
         'bpf': CS_ARCH_BPF, 'riscv': CS_ARCH_RISCV, 'tricore': CS_ARCH_TRICORE,
         'wasm': CS_ARCH_WASM, 'sh': CS_ARCH_SH, 'alpha': CS_ARCH_ALPHA,
-        'hppa': CS_ARCH_HPPA, 'loongarch': CS_ARCH_LOONGARCH, 'xtensa': CS_ARCH_XTENSA
+        'hppa': CS_ARCH_HPPA, 'loongarch': CS_ARCH_LOONGARCH, 'xtensa': CS_ARCH_XTENSA, 
+        'arc': CS_ARCH_ARC
     }
 
     all_archs = ""
diff --git a/bindings/python/capstone/arc.py b/bindings/python/capstone/arc.py
new file mode 100644
index 0000000000..ec30d5d5c2
--- /dev/null
+++ b/bindings/python/capstone/arc.py
@@ -0,0 +1,39 @@
+# Capstone Python bindings, by R33v0LT <sibirtsevdl@gmail.com>
+
+import ctypes
+from . import copy_ctypes_list
+from .arc_const import *
+
+
+class ARCOpValue(ctypes.Union):
+    _fields_ = (
+        ('reg', ctypes.c_uint),
+        ('imm', ctypes.c_int64)
+    )
+
+
+class ARCOp(ctypes.Structure):
+    _fields_ = (
+        ('type', ctypes.c_int),
+        ('value', ARCOpValue),
+        ('access', ctypes.c_uint)
+    )
+
+    @property
+    def imm(self):
+        return self.value.imm
+
+    @property
+    def reg(self):
+        return self.value.reg
+
+
+# Instruction structure
+class CsARC(ctypes.Structure):
+    _fields_ = (
+        ('op_count', ctypes.c_uint8),
+        ('operands', ARCOp * 8),
+    )
+
+def get_arch_info(a):
+    return (copy_ctypes_list(a.operands[:a.op_count]))
diff --git a/bindings/python/capstone/arc_const.py b/bindings/python/capstone/arc_const.py
new file mode 100644
index 0000000000..3297e43bdd
--- /dev/null
+++ b/bindings/python/capstone/arc_const.py
@@ -0,0 +1,274 @@
+from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX, UINT8_MAX
+# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [arc_const.py]
+ARC_OP_INVALID = CS_OP_INVALID
+ARC_OP_REG = CS_OP_REG
+ARC_OP_IMM = CS_OP_IMM
+
+ARC_REG_INVALID = 0
+ARC_REG_BLINK = 1
+ARC_REG_FP = 2
+ARC_REG_GP = 3
+ARC_REG_ILINK = 4
+ARC_REG_SP = 5
+ARC_REG_R0 = 6
+ARC_REG_R1 = 7
+ARC_REG_R2 = 8
+ARC_REG_R3 = 9
+ARC_REG_R4 = 10
+ARC_REG_R5 = 11
+ARC_REG_R6 = 12
+ARC_REG_R7 = 13
+ARC_REG_R8 = 14
+ARC_REG_R9 = 15
+ARC_REG_R10 = 16
+ARC_REG_R11 = 17
+ARC_REG_R12 = 18
+ARC_REG_R13 = 19
+ARC_REG_R14 = 20
+ARC_REG_R15 = 21
+ARC_REG_R16 = 22
+ARC_REG_R17 = 23
+ARC_REG_R18 = 24
+ARC_REG_R19 = 25
+ARC_REG_R20 = 26
+ARC_REG_R21 = 27
+ARC_REG_R22 = 28
+ARC_REG_R23 = 29
+ARC_REG_R24 = 30
+ARC_REG_R25 = 31
+ARC_REG_R30 = 32
+ARC_REG_R32 = 33
+ARC_REG_R33 = 34
+ARC_REG_R34 = 35
+ARC_REG_R35 = 36
+ARC_REG_R36 = 37
+ARC_REG_R37 = 38
+ARC_REG_R38 = 39
+ARC_REG_R39 = 40
+ARC_REG_R40 = 41
+ARC_REG_R41 = 42
+ARC_REG_R42 = 43
+ARC_REG_R43 = 44
+ARC_REG_R44 = 45
+ARC_REG_R45 = 46
+ARC_REG_R46 = 47
+ARC_REG_R47 = 48
+ARC_REG_R48 = 49
+ARC_REG_R49 = 50
+ARC_REG_R50 = 51
+ARC_REG_R51 = 52
+ARC_REG_R52 = 53
+ARC_REG_R53 = 54
+ARC_REG_R54 = 55
+ARC_REG_R55 = 56
+ARC_REG_R56 = 57
+ARC_REG_R57 = 58
+ARC_REG_R58 = 59
+ARC_REG_R59 = 60
+ARC_REG_R60 = 61
+ARC_REG_R61 = 62
+ARC_REG_R62 = 63
+ARC_REG_R63 = 64
+ARC_REG_STATUS32 = 65
+ARC_REG_ENDING = 66
+
+ARC_INS_INVALID = 0
+ARC_INS_h = 1
+ARC_INS_PBR = 2
+ARC_INS_ERROR_FLS = 3
+ARC_INS_ERROR_FFS = 4
+ARC_INS_PLDFI = 5
+ARC_INS_STB_FAR = 6
+ARC_INS_STH_FAR = 7
+ARC_INS_ST_FAR = 8
+ARC_INS_ADC = 9
+ARC_INS_ADC_F = 10
+ARC_INS_ADD_S = 11
+ARC_INS_ADD = 12
+ARC_INS_ADD_F = 13
+ARC_INS_AND = 14
+ARC_INS_AND_F = 15
+ARC_INS_ASL_S = 16
+ARC_INS_ASL = 17
+ARC_INS_ASL_F = 18
+ARC_INS_ASR_S = 19
+ARC_INS_ASR = 20
+ARC_INS_ASR_F = 21
+ARC_INS_BCLR_S = 22
+ARC_INS_BEQ_S = 23
+ARC_INS_BGE_S = 24
+ARC_INS_BGT_S = 25
+ARC_INS_BHI_S = 26
+ARC_INS_BHS_S = 27
+ARC_INS_BL = 28
+ARC_INS_BLE_S = 29
+ARC_INS_BLO_S = 30
+ARC_INS_BLS_S = 31
+ARC_INS_BLT_S = 32
+ARC_INS_BL_S = 33
+ARC_INS_BMSK_S = 34
+ARC_INS_BNE_S = 35
+ARC_INS_B = 36
+ARC_INS_BREQ_S = 37
+ARC_INS_BRNE_S = 38
+ARC_INS_BR = 39
+ARC_INS_BSET_S = 40
+ARC_INS_BTST_S = 41
+ARC_INS_B_S = 42
+ARC_INS_CMP_S = 43
+ARC_INS_CMP = 44
+ARC_INS_LD_S = 45
+ARC_INS_MOV_S = 46
+ARC_INS_EI_S = 47
+ARC_INS_ENTER_S = 48
+ARC_INS_FFS_F = 49
+ARC_INS_FFS = 50
+ARC_INS_FLS_F = 51
+ARC_INS_FLS = 52
+ARC_INS_ABS_S = 53
+ARC_INS_ADD1_S = 54
+ARC_INS_ADD2_S = 55
+ARC_INS_ADD3_S = 56
+ARC_INS_AND_S = 57
+ARC_INS_BIC_S = 58
+ARC_INS_BRK_S = 59
+ARC_INS_EXTB_S = 60
+ARC_INS_EXTH_S = 61
+ARC_INS_JEQ_S = 62
+ARC_INS_JL_S = 63
+ARC_INS_JL_S_D = 64
+ARC_INS_JNE_S = 65
+ARC_INS_J_S = 66
+ARC_INS_J_S_D = 67
+ARC_INS_LSR_S = 68
+ARC_INS_MPYUW_S = 69
+ARC_INS_MPYW_S = 70
+ARC_INS_MPY_S = 71
+ARC_INS_NEG_S = 72
+ARC_INS_NOP_S = 73
+ARC_INS_NOT_S = 74
+ARC_INS_OR_S = 75
+ARC_INS_SEXB_S = 76
+ARC_INS_SEXH_S = 77
+ARC_INS_SUB_S = 78
+ARC_INS_SUB_S_NE = 79
+ARC_INS_SWI_S = 80
+ARC_INS_TRAP_S = 81
+ARC_INS_TST_S = 82
+ARC_INS_UNIMP_S = 83
+ARC_INS_XOR_S = 84
+ARC_INS_LDB_S = 85
+ARC_INS_LDH_S = 86
+ARC_INS_J = 87
+ARC_INS_JL = 88
+ARC_INS_JLI_S = 89
+ARC_INS_LDB_AB = 90
+ARC_INS_LDB_AW = 91
+ARC_INS_LDB_DI_AB = 92
+ARC_INS_LDB_DI_AW = 93
+ARC_INS_LDB_DI = 94
+ARC_INS_LDB_X_AB = 95
+ARC_INS_LDB_X_AW = 96
+ARC_INS_LDB_X_DI_AB = 97
+ARC_INS_LDB_X_DI_AW = 98
+ARC_INS_LDB_X_DI = 99
+ARC_INS_LDB_X = 100
+ARC_INS_LDB = 101
+ARC_INS_LDH_AB = 102
+ARC_INS_LDH_AW = 103
+ARC_INS_LDH_DI_AB = 104
+ARC_INS_LDH_DI_AW = 105
+ARC_INS_LDH_DI = 106
+ARC_INS_LDH_S_X = 107
+ARC_INS_LDH_X_AB = 108
+ARC_INS_LDH_X_AW = 109
+ARC_INS_LDH_X_DI_AB = 110
+ARC_INS_LDH_X_DI_AW = 111
+ARC_INS_LDH_X_DI = 112
+ARC_INS_LDH_X = 113
+ARC_INS_LDH = 114
+ARC_INS_LDI_S = 115
+ARC_INS_LD_AB = 116
+ARC_INS_LD_AW = 117
+ARC_INS_LD_DI_AB = 118
+ARC_INS_LD_DI_AW = 119
+ARC_INS_LD_DI = 120
+ARC_INS_LD_S_AS = 121
+ARC_INS_LD = 122
+ARC_INS_LEAVE_S = 123
+ARC_INS_LR = 124
+ARC_INS_LSR = 125
+ARC_INS_LSR_F = 126
+ARC_INS_MAX = 127
+ARC_INS_MAX_F = 128
+ARC_INS_MIN = 129
+ARC_INS_MIN_F = 130
+ARC_INS_MOV_S_NE = 131
+ARC_INS_MOV = 132
+ARC_INS_MOV_F = 133
+ARC_INS_MPYMU = 134
+ARC_INS_MPYMU_F = 135
+ARC_INS_MPYM = 136
+ARC_INS_MPYM_F = 137
+ARC_INS_MPY = 138
+ARC_INS_MPY_F = 139
+ARC_INS_NORMH_F = 140
+ARC_INS_NORMH = 141
+ARC_INS_NORM_F = 142
+ARC_INS_NORM = 143
+ARC_INS_OR = 144
+ARC_INS_OR_F = 145
+ARC_INS_POP_S = 146
+ARC_INS_PUSH_S = 147
+ARC_INS_ROR = 148
+ARC_INS_ROR_F = 149
+ARC_INS_RSUB = 150
+ARC_INS_RSUB_F = 151
+ARC_INS_SBC = 152
+ARC_INS_SBC_F = 153
+ARC_INS_SETEQ = 154
+ARC_INS_SETEQ_F = 155
+ARC_INS_SEXB_F = 156
+ARC_INS_SEXB = 157
+ARC_INS_SEXH_F = 158
+ARC_INS_SEXH = 159
+ARC_INS_STB_S = 160
+ARC_INS_ST_S = 161
+ARC_INS_STB_AB = 162
+ARC_INS_STB_AW = 163
+ARC_INS_STB_DI_AB = 164
+ARC_INS_STB_DI_AW = 165
+ARC_INS_STB_DI = 166
+ARC_INS_STB = 167
+ARC_INS_STH_AB = 168
+ARC_INS_STH_AW = 169
+ARC_INS_STH_DI_AB = 170
+ARC_INS_STH_DI_AW = 171
+ARC_INS_STH_DI = 172
+ARC_INS_STH_S = 173
+ARC_INS_STH = 174
+ARC_INS_ST_AB = 175
+ARC_INS_ST_AW = 176
+ARC_INS_ST_DI_AB = 177
+ARC_INS_ST_DI_AW = 178
+ARC_INS_ST_DI = 179
+ARC_INS_ST = 180
+ARC_INS_SUB1 = 181
+ARC_INS_SUB1_F = 182
+ARC_INS_SUB2 = 183
+ARC_INS_SUB2_F = 184
+ARC_INS_SUB3 = 185
+ARC_INS_SUB3_F = 186
+ARC_INS_SUB = 187
+ARC_INS_SUB_F = 188
+ARC_INS_XOR = 189
+ARC_INS_XOR_F = 190
+
+# Group of ARC instructions
+
+ARC_GRP_INVALID = 0
+ARC_GRP_JUMP = 1
+ARC_GRP_CALL = 2
+ARC_GRP_RET = 3
+ARC_GRP_BRANCH_RELATIVE = 4
+ARC_GRP_ENDING = 5
diff --git a/bindings/python/cstest_py/src/cstest_py/compare.py b/bindings/python/cstest_py/src/cstest_py/compare.py
index 6200463e34..c013c2d734 100644
--- a/bindings/python/cstest_py/src/cstest_py/compare.py
+++ b/bindings/python/cstest_py/src/cstest_py/compare.py
@@ -28,6 +28,7 @@
 from capstone import alpha_const
 from capstone import hppa_const
 from capstone import loongarch_const
+from capstone import arc_const
 
 
 def cs_const_getattr(identifier: str):
@@ -95,6 +96,9 @@ def cs_const_getattr(identifier: str):
     if attr is not None:
         return attr
     attr = getattr(loongarch_const, identifier, None)
+    if attr is not None:
+        return attr
+    attr = getattr(arc_const, identifier, None)
     if attr is not None:
         return attr
     raise ValueError(f"Python capstone doesn't have the constant: {identifier}")
diff --git a/bindings/python/cstest_py/src/cstest_py/details.py b/bindings/python/cstest_py/src/cstest_py/details.py
index 18e635eda1..5da738c468 100644
--- a/bindings/python/cstest_py/src/cstest_py/details.py
+++ b/bindings/python/cstest_py/src/cstest_py/details.py
@@ -32,6 +32,11 @@
     LOONGARCH_OP_MEM,
 )
 
+from capstone.arc_const import (
+    ARC_OP_REG,
+    ARC_OP_IMM,
+)
+
 from capstone.m680x_const import (
     M680X_OP_REGISTER,
     M680X_OP_IMMEDIATE,
@@ -270,6 +275,8 @@ def compare_details(insn: CsInsn, expected: dict) -> bool:
         return test_expected_x86(actual, expected["x86"])
     elif "m68k" in expected:
         return test_expected_m68k(actual, expected["m68k"])
+    elif "arc" in expected:
+        return test_expected_arc(actual, expected["arc"])
 
     return True
 
@@ -1528,3 +1535,27 @@ def test_expected_wasm(actual: CsInsn, expected: dict) -> bool:
         else:
             raise ValueError("Operand type not handled.")
     return True
+
+def test_expected_arc(actual: CsInsn, expected: dict) -> bool:
+    if "operands" not in expected:
+        return True
+    elif not compare_uint32(
+        len(actual.operands), len(expected.get("operands")), "operands_count"
+    ):
+        return False
+
+    for aop, eop in zip(actual.operands, expected["operands"]):
+        if not compare_enum(aop.type, eop.get("type"), "type"):
+            return False
+        if not compare_enum(aop.access, eop.get("access"), "access"):
+            return False
+
+        if aop.type == ARC_OP_REG:
+            if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"):
+                return False
+        elif aop.type == ARC_OP_IMM:
+            if not compare_int32(aop.imm, eop.get("imm"), "imm"):
+                return False
+        else:
+            raise ValueError("Operand type not handled.")
+    return True
\ No newline at end of file
diff --git a/bindings/python/tests/test_iter.py b/bindings/python/tests/test_iter.py
index fd83a70bc8..52f59d47e2 100755
--- a/bindings/python/tests/test_iter.py
+++ b/bindings/python/tests/test_iter.py
@@ -33,6 +33,7 @@
 HPPA_20_CODE =    b'\xa2\x50\x20\x00\x20\x58\x01\x00\xa1\x44\x00\x00\x40\x18\x41\x00\xa2\x08\x20\x00\xa1\x48\x60\x01\xc0\x18\x61\x01\xa1\x14\x00\x00\x61\x0d\x0f\x00\x61\x0e\x0f\x00\x60\x18\x01\x00\x00\x0c\x00\x00\xa0\x0c\x00\x00\x1f\xc0\xff\x03\x00\x04\x00\x00\x00\x04\x10\x00\x83\x51\x22\x04\xc3\x51\x22\x04\x83\x51\x22\x04\x83\x71\x2f\x04\xc3\x71\x2f\x04\x83\x71\x2f\x04\x43\x53\x41\x04\x63\x53\x41\x04\x03\x53\x41\x04\x00\x12\x41\x04\x00\x16\x41\x04\x20\x16\x41\x04\x00\x42\x41\x04\x00\x46\x41\x04\x20\x46\x41\x04\x40\x12\x41\x04\x60\x12\x41\x04\x40\x42\x41\x04\x60\x42\x41\x04\x00\x18\x41\x04\x00\x08\x41\x04\x80\x13\x41\x04\xa0\x13\x41\x04\x80\x52\x41\x04\xa0\x52\x41\x04\x80\x72\x5e\x04\x80\x42\x41\x04\xc0\x52\x41\x04\xe0\x52\x41\x04\xc0\x42\x41\x04\xe0\x42\x41\x04\xad\xde\x00\x14'
 HPPA_11_CODE_BE = b'\x24\x41\x40\xc3\x24\x41\x60\xc3\x24\x41\x40\xe3\x24\x41\x60\xe3\x24\x41\x68\xe3\x2c\x41\x40\xc3\x2c\x41\x60\xc3\x2c\x41\x40\xe3\x2c\x41\x60\xe3\x2c\x41\x68\xe3\x24\x62\x42\xc1\x24\x62\x62\xc1\x24\x62\x42\xe1\x24\x62\x46\xe1\x24\x62\x62\xe1\x24\x62\x6a\xe1\x2c\x62\x42\xc1\x2c\x62\x62\xc1\x2c\x62\x42\xe1\x2c\x62\x46\xe1\x2c\x62\x62\xe1\x2c\x62\x6a\xe1\x24\x3e\x50\xc2\x24\x3e\x50\xe2\x24\x3e\x70\xe2\x24\x3e\x78\xe2\x2c\x3e\x50\xc2\x2c\x3e\x50\xe2\x2c\x3e\x70\xe2\x2c\x3e\x78\xe2\x24\x5e\x52\xc1\x24\x5e\x52\xe1\x24\x5e\x56\xe1\x24\x5e\x72\xe1\x24\x5e\x7a\xe1\x2c\x5e\x52\xc1\x2c\x5e\x52\xe1\x2c\x5e\x56\xe1\x2c\x5e\x72\xe1\x2c\x5e\x7a\xe1'
 HPPA_11_CODE =    b'\xc3\x40\x41\x24\xc3\x60\x41\x24\xe3\x40\x41\x24\xe3\x60\x41\x24\xe3\x68\x41\x24\xc3\x40\x41\x2c\xc3\x60\x41\x2c\xe3\x40\x41\x2c\xe3\x60\x41\x2c\xe3\x68\x41\x2c\xc1\x42\x62\x24\xc1\x62\x62\x24\xe1\x42\x62\x24\xe1\x46\x62\x24\xe1\x62\x62\x24\xe1\x6a\x62\x24\xc1\x42\x62\x2c\xc1\x62\x62\x2c\xe1\x42\x62\x2c\xe1\x46\x62\x2c\xe1\x62\x62\x2c\xe1\x6a\x62\x2c\xc2\x50\x3e\x24\xe2\x50\x3e\x24\xe2\x70\x3e\x24\xe2\x78\x3e\x24\xc2\x50\x3e\x2c\xe2\x50\x3e\x2c\xe2\x70\x3e\x2c\xe2\x78\x3e\x2c\xc1\x52\x5e\x24\xe1\x52\x5e\x24\xe1\x56\x5e\x24\xe1\x72\x5e\x24\xe1\x7a\x5e\x24\xc1\x52\x5e\x2c\xe1\x52\x5e\x2c\xe1\x56\x5e\x2c\xe1\x72\x5e\x2c\xe1\x7a\x5e\x2c'
+ARC_CODE = b"\x04\x11\x00\x00\x04\x11\x00\x02\x04\x11\x00\x04\x04\x11\x00\x01\x04\x11\x00\x03\x04\x11\x00\x05\x04\x11\x80\x00\x04\x11\x80\x02\x04\x11\x80\x04"
 
 all_tests = (
         (CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", None),
@@ -66,6 +67,7 @@
         (CS_ARCH_HPPA, CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_20, HPPA_20_CODE, "HPPA 2.0 (Little-endian)", None),
         (CS_ARCH_HPPA, CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_11, HPPA_11_CODE_BE, "HPPA 1.1 (Big-endian)", None),
         (CS_ARCH_HPPA, CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_11, HPPA_11_CODE, "HPPA 1.1 (Little-endian)", None),
+        (CS_ARCH_ARC, CS_MODE_LITTLE_ENDIAN, ARC_CODE, "ARC", None),
         )
 
 # ## Test class Cs
diff --git a/bindings/python/tests/test_lite.py b/bindings/python/tests/test_lite.py
index 979c9cf4bd..7ff4f86f43 100755
--- a/bindings/python/tests/test_lite.py
+++ b/bindings/python/tests/test_lite.py
@@ -27,6 +27,8 @@
 XCORE_CODE = b"\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10"
 M68K_CODE = b"\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28\x4E\xB9\x00\x00\x00\x12\x4E\x75"
 M680X_CODE = b"\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39"
+ARC_CODE = b"\x04\x11\x00\x00\x04\x11\x00\x02\x04\x11\x00\x04\x04\x11\x00\x01\x04\x11\x00\x03\x04\x11\x00\x05\x04\x11\x80\x00\x04\x11\x80\x02\x04\x11\x80\x04"
+
 
 all_tests = (
         (CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", None),
@@ -54,6 +56,7 @@
         (CS_ARCH_XCORE, 0, XCORE_CODE, "XCore", None),
         (CS_ARCH_M68K, CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040, M68K_CODE, "M68K (68040)", None),
         (CS_ARCH_M680X, CS_MODE_M680X_6809, M680X_CODE, "M680X_M6809", None),
+        (CS_ARCH_ARC, CS_MODE_LITTLE_ENDIAN, ARC_CODE, "ARC", None),
         )
 
 
diff --git a/cmake.sh b/cmake.sh
index 819d708dae..164d70d625 100755
--- a/cmake.sh
+++ b/cmake.sh
@@ -66,6 +66,9 @@ case $1 in
   LOONGARCH)
     ARCH=LOONGARCH
     ;;
+  ARC)
+    ARCH=ARC
+    ;;
   *)
     ;;
 esac
diff --git a/config.mk b/config.mk
index 42f064b551..568f757986 100644
--- a/config.mk
+++ b/config.mk
@@ -4,7 +4,7 @@
 ################################################################################
 # Specify which archs you want to compile in. By default, we build all archs.
 
-CAPSTONE_ARCHS ?= arm aarch64 m68k mips powerpc sparc systemz x86 xcore tms320c64x m680x evm riscv mos65xx wasm bpf sh tricore alpha hppa loongarch xtensa
+CAPSTONE_ARCHS ?= arm aarch64 m68k mips powerpc sparc systemz x86 xcore tms320c64x m680x evm riscv mos65xx wasm bpf sh tricore alpha hppa loongarch xtensa arc
 
 
 ################################################################################
diff --git a/cs.c b/cs.c
index d87f227284..eb2966fa9c 100644
--- a/cs.c
+++ b/cs.c
@@ -72,6 +72,7 @@
 #include "arch/HPPA/HPPAModule.h"
 #include "arch/LoongArch/LoongArchModule.h"
 #include "arch/Xtensa/XtensaModule.h"
+#include "arch/ARC/ARCModule.h"
 
 typedef struct cs_arch_config {
 	// constructor initialization
@@ -266,6 +267,13 @@ typedef struct cs_arch_config {
 		  CS_MODE_XTENSA_ESP8266), \
 	}
 
+#define CS_ARCH_CONFIG_ARC \
+	{ \
+		ARC_global_init, \
+		ARC_option, \
+		~(CS_MODE_LITTLE_ENDIAN), \
+	}
+
 #ifdef CAPSTONE_USE_ARCH_REGISTRATION
 static cs_arch_config arch_configs[MAX_ARCH];
 static uint32_t all_arch;
@@ -382,7 +390,12 @@ static const cs_arch_config arch_configs[MAX_ARCH] = {
 	{ NULL, NULL, 0 },
 #endif
 #ifdef CAPSTONE_HAS_XTENSA
-	CS_ARCH_CONFIG_XTENSA
+	CS_ARCH_CONFIG_XTENSA,
+#else
+	{ NULL, NULL, 0 },
+#endif
+#ifdef CAPSTONE_HAS_ARC
+	CS_ARCH_CONFIG_ARC,
 #else
 	{ NULL, NULL, 0 },
 #endif
@@ -456,7 +469,10 @@ static const uint32_t all_arch = 0
 #ifdef CAPSTONE_HAS_XTENSA
 				 | (1 << CS_ARCH_XTENSA)
 #endif
-	;
+#ifdef CAPSTONE_HAS_ARC
+				 | (1 << CS_ARCH_ARC)
+#endif
+;
 #endif
 
 
@@ -683,12 +699,21 @@ void CAPSTONE_API cs_arch_register_loongarch(void)
 #endif
 }
 
+CAPSTONE_EXPORT
+void CAPSTONE_API cs_arch_register_arc(void)
+{
+#if defined(CAPSTONE_USE_ARCH_REGISTRATION) && defined(CAPSTONE_HAS_ARC)
+	CS_ARCH_REGISTER(ARC);
+#endif
+}
+
+
 CAPSTONE_EXPORT
 bool CAPSTONE_API cs_support(int query)
 {
 	if (query == CS_ARCH_ALL)
 		return all_arch ==
-		       ((1 << CS_ARCH_ARM) | (1 << CS_ARCH_AARCH64) |
+		    ((1 << CS_ARCH_ARM) | (1 << CS_ARCH_AARCH64) |
 			(1 << CS_ARCH_MIPS) | (1 << CS_ARCH_X86) |
 			(1 << CS_ARCH_PPC) | (1 << CS_ARCH_SPARC) |
 			(1 << CS_ARCH_SYSTEMZ) | (1 << CS_ARCH_XCORE) |
@@ -698,7 +723,8 @@ bool CAPSTONE_API cs_support(int query)
 			(1 << CS_ARCH_WASM) | (1 << CS_ARCH_BPF) |
 			(1 << CS_ARCH_SH) | (1 << CS_ARCH_TRICORE) |
 			(1 << CS_ARCH_ALPHA) | (1 << CS_ARCH_HPPA) |
-			(1 << CS_ARCH_LOONGARCH) | (1 << CS_ARCH_XTENSA));
+			(1 << CS_ARCH_LOONGARCH) | (1 << CS_ARCH_XTENSA) | 
+			(1 << CS_ARCH_ARC));
 
 	if ((unsigned int)query < CS_ARCH_MAX)
 		return all_arch & (1 << query);
@@ -1010,6 +1036,10 @@ static uint8_t skipdata_size(cs_struct *handle)
 		case CS_ARCH_LOONGARCH:
 			// LoongArch alignment is 4.
 			return 4;
+		case CS_ARCH_ARC:
+			// ARC instruction's length can be 2, 4, 6 or 8 bytes,
+			// therefore, skip 2 bytes
+			return 2;
 	}
 }
 
@@ -1764,6 +1794,11 @@ int CAPSTONE_API cs_op_count(csh ud, const cs_insn *insn, unsigned int op_type)
 				if (insn->detail->loongarch.operands[i].type == (loongarch_op_type)op_type)
 					count++;
 			break;
+		case CS_ARCH_ARC:
+			for (i = 0; i < insn->detail->arc.op_count; i++)
+				if (insn->detail->arc.operands[i].type == (arc_op_type)op_type)
+					count++;
+			break;
 	}
 
 	return count;
@@ -1971,6 +2006,14 @@ int CAPSTONE_API cs_op_index(csh ud, const cs_insn *insn, unsigned int op_type,
 					return i;
 			}
 			break;
+		case CS_ARCH_ARC:
+			for (i = 0; i < insn->detail->arc.op_count; i++) {
+				if (insn->detail->arc.operands[i].type == (arc_op_type)op_type)
+					count++;
+				if (count == post)
+					return i;
+			}
+			break;
 	}
 
 	return -1;
diff --git a/cstool/cstool.c b/cstool/cstool.c
index 8bbdf0a86a..0974185deb 100644
--- a/cstool/cstool.c
+++ b/cstool/cstool.c
@@ -239,6 +239,9 @@ static struct {
 	{ "esp32", "Xtensa ESP32", CS_ARCH_XTENSA, CS_MODE_XTENSA_ESP32 },
 	{ "esp32s2", "Xtensa ESP32S2", CS_ARCH_XTENSA, CS_MODE_XTENSA_ESP32S2 },
 	{ "esp8266", "Xtensa ESP8266", CS_ARCH_XTENSA, CS_MODE_XTENSA_ESP8266 },
+
+	{ "arc", "ARC Little-Endian", CS_ARCH_ARC, CS_MODE_LITTLE_ENDIAN },
+
 	{ NULL }
 };
 
@@ -324,6 +327,7 @@ static const char *get_arch_name(cs_arch arch)
 	case CS_ARCH_ALPHA: return "Alpha";
 	case CS_ARCH_HPPA: return "HPPA";
 	case CS_ARCH_LOONGARCH: return "LoongArch";
+	case CS_ARCH_ARC: return "ARC";
 	default: return NULL;
 	}
 }
@@ -443,6 +447,9 @@ static void print_details(csh handle, cs_arch arch, cs_mode md, cs_insn *ins)
 		case CS_ARCH_XTENSA:
 			print_insn_detail_xtensa(handle, ins);
 			break;
+		case CS_ARCH_ARC:
+			print_insn_detail_arc(handle, ins);
+			break;
 		default: break;
 	}
 
@@ -633,6 +640,10 @@ int main(int argc, char **argv)
 					printf("xtensa=1 ");
 				}
 
+				if (cs_support(CS_ARCH_ARC)) {
+					printf("arc=1 ");
+				}
+
 				printf("\n");
 				return 0;
 			case 'h':
diff --git a/cstool/cstool.h b/cstool/cstool.h
index b55cf70cc8..2d005bc9a0 100644
--- a/cstool/cstool.h
+++ b/cstool/cstool.h
@@ -23,5 +23,6 @@ void print_insn_detail_alpha(csh handle, cs_insn *ins);
 void print_insn_detail_hppa(csh handle, cs_insn *ins);
 void print_insn_detail_loongarch(csh handle, cs_insn *ins);
 void print_insn_detail_xtensa(csh handle, cs_insn *ins);
+void print_insn_detail_arc(csh handle, cs_insn *ins);
 
 #endif //CAPSTONE_CSTOOL_CSTOOL_H_
diff --git a/cstool/cstool_arc.c b/cstool/cstool_arc.c
new file mode 100644
index 0000000000..ef859e52fe
--- /dev/null
+++ b/cstool/cstool_arc.c
@@ -0,0 +1,74 @@
+#include <stdio.h>
+#include <capstone/capstone.h>
+#include "cstool.h"
+
+void print_insn_detail_arc(csh handle, cs_insn *ins)
+{
+	cs_arc *arc;
+	int i;
+	cs_regs regs_read, regs_write;
+	uint8_t regs_read_count, regs_write_count;
+	uint8_t access;
+
+	// detail can be NULL on "data" instruction if SKIPDATA option is turned ON
+	if (ins->detail == NULL)
+		return;
+
+	arc = &(ins->detail->arc);
+	if (arc->op_count)
+		printf("\top_count: %u\n", arc->op_count);
+
+	for (i = 0; i < arc->op_count; i++) {
+		cs_arc_op *op = &(arc->operands[i]);
+		switch ((int)op->type) {
+		default:
+			break;
+		case ARC_OP_REG:
+			printf("\t\toperands[%u].type: REG = %s\n", i,
+			       cs_reg_name(handle, op->reg));
+			break;
+		case ARC_OP_IMM:
+			printf("\t\toperands[%u].type: IMM = 0x%lx\n", i,
+			       (long)op->imm);
+			break;
+		}
+
+		access = op->access;
+		switch (access) {
+		default:
+			break;
+		case CS_AC_READ:
+			printf("\t\toperands[%u].access: READ\n", i);
+			break;
+		case CS_AC_WRITE:
+			printf("\t\toperands[%u].access: WRITE\n", i);
+			break;
+		case CS_AC_READ | CS_AC_WRITE:
+			printf("\t\toperands[%u].access: READ | WRITE\n", i);
+			break;
+		}
+	}
+
+	if (ins->detail->writeback)
+		printf("\tWrite-back: True\n");
+
+	/* print all registers that are involved in this instruction */
+	if (!cs_regs_access(handle, ins, regs_read, &regs_read_count,
+			    regs_write, &regs_write_count)) {
+		if (regs_read_count) {
+			printf("\tRegisters read:");
+			for (i = 0; i < regs_read_count; i++)
+				printf(" %s",
+				       cs_reg_name(handle, regs_read[i]));
+			printf("\n");
+		}
+
+		if (regs_write_count) {
+			printf("\tRegisters modified:");
+			for (i = 0; i < regs_write_count; i++)
+				printf(" %s",
+				       cs_reg_name(handle, regs_write[i]));
+			printf("\n");
+		}
+	}
+}
diff --git a/include/capstone/arc.h b/include/capstone/arc.h
new file mode 100644
index 0000000000..f89a12ad31
--- /dev/null
+++ b/include/capstone/arc.h
@@ -0,0 +1,344 @@
+#ifndef CAPSTONE_ARC_H
+#define CAPSTONE_ARC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
+#include <stdint.h>
+#endif
+
+#include "platform.h"
+#include "cs_operand.h"
+
+/// Operand type for instruction's operands
+typedef enum arc_op_type {
+	ARC_OP_INVALID = CS_OP_INVALID, ///< Invalid
+	ARC_OP_REG = CS_OP_REG,	      ///< Register operand
+	ARC_OP_IMM = CS_OP_IMM,	      ///< Immediate operand
+} arc_op_type;
+
+/// Instruction operand
+typedef struct cs_arc_op {
+	arc_op_type type;	      //< operand type
+	union {
+		unsigned int reg;     /// register value for REG operand
+		int64_t imm;	      /// immediate value for IMM operand
+	};
+
+	/// How is this operand accessed? (READ, WRITE or READ|WRITE)
+	/// NOTE: this field is irrelevant if engine is compiled in DIET mode.
+	enum cs_ac_type access;
+} cs_arc_op;
+
+#define NUM_ARC_OPS 8
+
+/// Instruction structure
+typedef struct cs_arc {
+	/// Number of operands of this instruction,
+	/// or 0 when instruction has no operand.
+	uint8_t op_count;
+	cs_arc_op operands[NUM_ARC_OPS]; ///< operands for this instruction.
+} cs_arc;
+
+/// ARC registers
+typedef enum arc_reg {
+	// generated content <ARCGenCSRegEnum.inc> begin
+	// clang-format off
+
+	ARC_REG_INVALID = 0,
+	ARC_REG_BLINK = 1,
+	ARC_REG_FP = 2,
+	ARC_REG_GP = 3,
+	ARC_REG_ILINK = 4,
+	ARC_REG_SP = 5,
+	ARC_REG_R0 = 6,
+	ARC_REG_R1 = 7,
+	ARC_REG_R2 = 8,
+	ARC_REG_R3 = 9,
+	ARC_REG_R4 = 10,
+	ARC_REG_R5 = 11,
+	ARC_REG_R6 = 12,
+	ARC_REG_R7 = 13,
+	ARC_REG_R8 = 14,
+	ARC_REG_R9 = 15,
+	ARC_REG_R10 = 16,
+	ARC_REG_R11 = 17,
+	ARC_REG_R12 = 18,
+	ARC_REG_R13 = 19,
+	ARC_REG_R14 = 20,
+	ARC_REG_R15 = 21,
+	ARC_REG_R16 = 22,
+	ARC_REG_R17 = 23,
+	ARC_REG_R18 = 24,
+	ARC_REG_R19 = 25,
+	ARC_REG_R20 = 26,
+	ARC_REG_R21 = 27,
+	ARC_REG_R22 = 28,
+	ARC_REG_R23 = 29,
+	ARC_REG_R24 = 30,
+	ARC_REG_R25 = 31,
+	ARC_REG_R30 = 32,
+	ARC_REG_R32 = 33,
+	ARC_REG_R33 = 34,
+	ARC_REG_R34 = 35,
+	ARC_REG_R35 = 36,
+	ARC_REG_R36 = 37,
+	ARC_REG_R37 = 38,
+	ARC_REG_R38 = 39,
+	ARC_REG_R39 = 40,
+	ARC_REG_R40 = 41,
+	ARC_REG_R41 = 42,
+	ARC_REG_R42 = 43,
+	ARC_REG_R43 = 44,
+	ARC_REG_R44 = 45,
+	ARC_REG_R45 = 46,
+	ARC_REG_R46 = 47,
+	ARC_REG_R47 = 48,
+	ARC_REG_R48 = 49,
+	ARC_REG_R49 = 50,
+	ARC_REG_R50 = 51,
+	ARC_REG_R51 = 52,
+	ARC_REG_R52 = 53,
+	ARC_REG_R53 = 54,
+	ARC_REG_R54 = 55,
+	ARC_REG_R55 = 56,
+	ARC_REG_R56 = 57,
+	ARC_REG_R57 = 58,
+	ARC_REG_R58 = 59,
+	ARC_REG_R59 = 60,
+	ARC_REG_R60 = 61,
+	ARC_REG_R61 = 62,
+	ARC_REG_R62 = 63,
+	ARC_REG_R63 = 64,
+	ARC_REG_STATUS32 = 65,
+	ARC_REG_ENDING, // 66
+
+	// clang-format on
+	// generated content <ARCGenCSRegEnum.inc> end
+} arc_reg;
+
+/// ARC instruction
+typedef enum arc_insn {
+	// generated content <ARCGenCSInsnEnum.inc> begin
+	// clang-format off
+
+	ARC_INS_INVALID,
+	ARC_INS_h,
+	ARC_INS_PBR,
+	ARC_INS_ERROR_FLS,
+	ARC_INS_ERROR_FFS,
+	ARC_INS_PLDFI,
+	ARC_INS_STB_FAR,
+	ARC_INS_STH_FAR,
+	ARC_INS_ST_FAR,
+	ARC_INS_ADC,
+	ARC_INS_ADC_F,
+	ARC_INS_ADD_S,
+	ARC_INS_ADD,
+	ARC_INS_ADD_F,
+	ARC_INS_AND,
+	ARC_INS_AND_F,
+	ARC_INS_ASL_S,
+	ARC_INS_ASL,
+	ARC_INS_ASL_F,
+	ARC_INS_ASR_S,
+	ARC_INS_ASR,
+	ARC_INS_ASR_F,
+	ARC_INS_BCLR_S,
+	ARC_INS_BEQ_S,
+	ARC_INS_BGE_S,
+	ARC_INS_BGT_S,
+	ARC_INS_BHI_S,
+	ARC_INS_BHS_S,
+	ARC_INS_BL,
+	ARC_INS_BLE_S,
+	ARC_INS_BLO_S,
+	ARC_INS_BLS_S,
+	ARC_INS_BLT_S,
+	ARC_INS_BL_S,
+	ARC_INS_BMSK_S,
+	ARC_INS_BNE_S,
+	ARC_INS_B,
+	ARC_INS_BREQ_S,
+	ARC_INS_BRNE_S,
+	ARC_INS_BR,
+	ARC_INS_BSET_S,
+	ARC_INS_BTST_S,
+	ARC_INS_B_S,
+	ARC_INS_CMP_S,
+	ARC_INS_CMP,
+	ARC_INS_LD_S,
+	ARC_INS_MOV_S,
+	ARC_INS_EI_S,
+	ARC_INS_ENTER_S,
+	ARC_INS_FFS_F,
+	ARC_INS_FFS,
+	ARC_INS_FLS_F,
+	ARC_INS_FLS,
+	ARC_INS_ABS_S,
+	ARC_INS_ADD1_S,
+	ARC_INS_ADD2_S,
+	ARC_INS_ADD3_S,
+	ARC_INS_AND_S,
+	ARC_INS_BIC_S,
+	ARC_INS_BRK_S,
+	ARC_INS_EXTB_S,
+	ARC_INS_EXTH_S,
+	ARC_INS_JEQ_S,
+	ARC_INS_JL_S,
+	ARC_INS_JL_S_D,
+	ARC_INS_JNE_S,
+	ARC_INS_J_S,
+	ARC_INS_J_S_D,
+	ARC_INS_LSR_S,
+	ARC_INS_MPYUW_S,
+	ARC_INS_MPYW_S,
+	ARC_INS_MPY_S,
+	ARC_INS_NEG_S,
+	ARC_INS_NOP_S,
+	ARC_INS_NOT_S,
+	ARC_INS_OR_S,
+	ARC_INS_SEXB_S,
+	ARC_INS_SEXH_S,
+	ARC_INS_SUB_S,
+	ARC_INS_SUB_S_NE,
+	ARC_INS_SWI_S,
+	ARC_INS_TRAP_S,
+	ARC_INS_TST_S,
+	ARC_INS_UNIMP_S,
+	ARC_INS_XOR_S,
+	ARC_INS_LDB_S,
+	ARC_INS_LDH_S,
+	ARC_INS_J,
+	ARC_INS_JL,
+	ARC_INS_JLI_S,
+	ARC_INS_LDB_AB,
+	ARC_INS_LDB_AW,
+	ARC_INS_LDB_DI_AB,
+	ARC_INS_LDB_DI_AW,
+	ARC_INS_LDB_DI,
+	ARC_INS_LDB_X_AB,
+	ARC_INS_LDB_X_AW,
+	ARC_INS_LDB_X_DI_AB,
+	ARC_INS_LDB_X_DI_AW,
+	ARC_INS_LDB_X_DI,
+	ARC_INS_LDB_X,
+	ARC_INS_LDB,
+	ARC_INS_LDH_AB,
+	ARC_INS_LDH_AW,
+	ARC_INS_LDH_DI_AB,
+	ARC_INS_LDH_DI_AW,
+	ARC_INS_LDH_DI,
+	ARC_INS_LDH_S_X,
+	ARC_INS_LDH_X_AB,
+	ARC_INS_LDH_X_AW,
+	ARC_INS_LDH_X_DI_AB,
+	ARC_INS_LDH_X_DI_AW,
+	ARC_INS_LDH_X_DI,
+	ARC_INS_LDH_X,
+	ARC_INS_LDH,
+	ARC_INS_LDI_S,
+	ARC_INS_LD_AB,
+	ARC_INS_LD_AW,
+	ARC_INS_LD_DI_AB,
+	ARC_INS_LD_DI_AW,
+	ARC_INS_LD_DI,
+	ARC_INS_LD_S_AS,
+	ARC_INS_LD,
+	ARC_INS_LEAVE_S,
+	ARC_INS_LR,
+	ARC_INS_LSR,
+	ARC_INS_LSR_F,
+	ARC_INS_MAX,
+	ARC_INS_MAX_F,
+	ARC_INS_MIN,
+	ARC_INS_MIN_F,
+	ARC_INS_MOV_S_NE,
+	ARC_INS_MOV,
+	ARC_INS_MOV_F,
+	ARC_INS_MPYMU,
+	ARC_INS_MPYMU_F,
+	ARC_INS_MPYM,
+	ARC_INS_MPYM_F,
+	ARC_INS_MPY,
+	ARC_INS_MPY_F,
+	ARC_INS_NORMH_F,
+	ARC_INS_NORMH,
+	ARC_INS_NORM_F,
+	ARC_INS_NORM,
+	ARC_INS_OR,
+	ARC_INS_OR_F,
+	ARC_INS_POP_S,
+	ARC_INS_PUSH_S,
+	ARC_INS_ROR,
+	ARC_INS_ROR_F,
+	ARC_INS_RSUB,
+	ARC_INS_RSUB_F,
+	ARC_INS_SBC,
+	ARC_INS_SBC_F,
+	ARC_INS_SETEQ,
+	ARC_INS_SETEQ_F,
+	ARC_INS_SEXB_F,
+	ARC_INS_SEXB,
+	ARC_INS_SEXH_F,
+	ARC_INS_SEXH,
+	ARC_INS_STB_S,
+	ARC_INS_ST_S,
+	ARC_INS_STB_AB,
+	ARC_INS_STB_AW,
+	ARC_INS_STB_DI_AB,
+	ARC_INS_STB_DI_AW,
+	ARC_INS_STB_DI,
+	ARC_INS_STB,
+	ARC_INS_STH_AB,
+	ARC_INS_STH_AW,
+	ARC_INS_STH_DI_AB,
+	ARC_INS_STH_DI_AW,
+	ARC_INS_STH_DI,
+	ARC_INS_STH_S,
+	ARC_INS_STH,
+	ARC_INS_ST_AB,
+	ARC_INS_ST_AW,
+	ARC_INS_ST_DI_AB,
+	ARC_INS_ST_DI_AW,
+	ARC_INS_ST_DI,
+	ARC_INS_ST,
+	ARC_INS_SUB1,
+	ARC_INS_SUB1_F,
+	ARC_INS_SUB2,
+	ARC_INS_SUB2_F,
+	ARC_INS_SUB3,
+	ARC_INS_SUB3_F,
+	ARC_INS_SUB,
+	ARC_INS_SUB_F,
+	ARC_INS_XOR,
+	ARC_INS_XOR_F,
+
+	// clang-format on
+	// generated content <ARCGenCSInsnEnum.inc> end
+} arc_insn;
+
+//> Group of ARC instructions
+typedef enum arc_insn_group {
+	ARC_GRP_INVALID = 0, ///< = CS_GRP_INVALID
+
+	/// Generic groups
+	/// all jump instructions (conditional+direct+indirect jumps)
+	ARC_GRP_JUMP, ///< = CS_GRP_JUMP
+	/// all call instructions
+	ARC_GRP_CALL, ///< = CS_GRP_CALL
+	/// all return instructions
+	ARC_GRP_RET, ///< = CS_GRP_RET
+	/// all relative branching instructions
+	ARC_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE
+
+	ARC_GRP_ENDING,
+} arc_insn_group;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
\ No newline at end of file
diff --git a/include/capstone/capstone.h b/include/capstone/capstone.h
index 46b8c58de3..436198b92e 100644
--- a/include/capstone/capstone.h
+++ b/include/capstone/capstone.h
@@ -103,6 +103,7 @@ typedef enum cs_arch {
 	CS_ARCH_HPPA, 		///< HPPA architecture
 	CS_ARCH_LOONGARCH, 	///< LoongArch architecture
 	CS_ARCH_XTENSA, 	///< Xtensa architecture
+	CS_ARCH_ARC, 	    ///< ARC architecture
 	CS_ARCH_MAX,
 	CS_ARCH_ALL = 0xFFFF, // All architectures - for cs_support()
 } cs_arch;
@@ -358,6 +359,7 @@ typedef struct cs_opt_skipdata {
 	/// BPF:       8 bytes.
 	/// TriCore:   2 bytes.
 	/// LoongArch: 4 bytes.
+	/// ARC: 	   2 bytes.
 	cs_skipdata_cb_t callback; 	// default value is NULL
 
 	/// User-defined data to be passed to @callback function pointer.
@@ -391,6 +393,7 @@ typedef struct cs_opt_skipdata {
 #include "hppa.h"
 #include "loongarch.h"
 #include "xtensa.h"
+#include "arc.h"
 
 #define MAX_IMPL_W_REGS 47
 #define MAX_IMPL_R_REGS 20
@@ -448,6 +451,7 @@ typedef struct cs_detail {
 		cs_hppa hppa; ///< HPPA architecture
 		cs_loongarch loongarch; ///< LoongArch architecture
 		cs_xtensa xtensa; ///< Xtensa architecture
+		cs_arc arc; ///< ARC architecture
 	};
 } cs_detail;
 
@@ -599,6 +603,8 @@ CAPSTONE_EXPORT
 void CAPSTONE_API cs_arch_register_alpha(void);
 CAPSTONE_EXPORT
 void CAPSTONE_API cs_arch_register_loongarch(void);
+CAPSTONE_EXPORT
+void CAPSTONE_API cs_arch_register_arc(void);
 
 /**
  This API can be used to either ask for archs supported by this library,
diff --git a/packages/deb/control b/packages/deb/control
index 440f21547c..87d87bf877 100644
--- a/packages/deb/control
+++ b/packages/deb/control
@@ -14,7 +14,7 @@ Description: lightweight multi-architecture disassembly framework - devel files
  Capstone is a lightweight multi-platform, multi-architecture disassembly
  framework. These are the development headers and libraries.
  Features:
- - Support hardware architectures: AArch64, ARM, Alpha, BPF, EVM, HPPA, LongArch, M680X, M68K, MOS65XX, Mips, PowerPC, RISCV, SH, Sparc, SystemZ, TMS320C64x, TriCore, WASM, x86, XCore, Xtensa.
+ - Support hardware architectures: AArch64, ARM, Alpha, ARC, BPF, EVM, HPPA, LongArch, M680X, M68K, MOS65XX, Mips, PowerPC, RISCV, SH, Sparc, SystemZ, TMS320C64x, TriCore, WASM, x86, XCore, Xtensa.
  - Clean/simple/lightweight/intuitive architecture-neutral API.
  - Provide details on disassembled instructions (called "decomposer" by some
  others).
diff --git a/suite/MC/ARC/alu_arc.s.cs b/suite/MC/ARC/alu_arc.s.cs
new file mode 100644
index 0000000000..4a68065a87
--- /dev/null
+++ b/suite/MC/ARC/alu_arc.s.cs
@@ -0,0 +1,141 @@
+# CS_ARCH_ARC, CS_MODE_LITTLE_ENDIAN, None
+
+0x0,0x20,0x0,0x0 = add %r0, %r0, %r0
+0x0,0x20,0x4,0x0 = add %r4, %r0, %r0
+0x0,0x20,0x4,0x80 = add.f %r4, %r0, %r0
+0x0,0x20,0xc2,0x0 = add %r2, %r0, %r3
+0x0,0x20,0x2,0x1 = add %r2, %r0, %r4
+0x0,0x27,0x2,0x1 = add %r2, %r7, %r4
+0xc0,0x20,0x61,0x0 = add.eq %r0, %r0, 1
+0xc0,0x26,0x2b,0x4 = add.lt %r6, %r6, 16
+0xc0,0x27,0xec,0x17 = add.le %r15, %r15, 31
+0xc0,0x20,0x69,0x0 = add.gt %r0, %r0, 1
+0xc0,0x26,0x2a,0x4 = add.ge %r6, %r6, 16
+0xc0,0x27,0xe3,0x17 = add.p %r15, %r15, 31
+0xc0,0x20,0x64,0x0 = add.n %r0, %r0, 1
+0xc0,0x26,0x27,0x4 = add.vs %r6, %r6, 16
+0xc0,0x27,0xef,0x17 = add.pnz %r15, %r15, 31
+0xc0,0x20,0x61,0x80 = add.eq.f %r0, %r0, 1
+0xc0,0x26,0x2b,0x84 = add.lt.f %r6, %r6, 16
+0xc0,0x27,0xec,0x97 = add.le.f %r15, %r15, 31
+0xc0,0x20,0x69,0x80 = add.gt.f %r0, %r0, 1
+0xc0,0x26,0x2a,0x84 = add.ge.f %r6, %r6, 16
+0xc0,0x27,0xe3,0x97 = add.p.f %r15, %r15, 31
+0xc0,0x20,0x64,0x80 = add.n.f %r0, %r0, 1
+0xc0,0x26,0x27,0x84 = add.vs.f %r6, %r6, 16
+0xc0,0x27,0xef,0x97 = add.pnz.f %r15, %r15, 31
+0x4,0x27,0x2,0x1 = and %r2, %r7, %r4
+0x4,0x27,0x2,0x81 = and.f %r2, %r7, %r4
+0x44,0x27,0x2,0x1 = and %r2, %r7, 4
+0x84,0x21,0xc3,0xf = and %r1, %r1, 255
+0x84,0x21,0xc3,0x8f = and.f %r1, %r1, 255
+0xc4,0x20,0x21,0x0 = and.eq %r0, %r0, 0
+0xc4,0x26,0x2b,0x4 = and.lt %r6, %r6, 16
+0xc4,0x27,0xec,0x17 = and.le %r15, %r15, 31
+0xc4,0x20,0x29,0x0 = and.gt %r0, %r0, 0
+0xc4,0x26,0x2a,0x4 = and.ge %r6, %r6, 16
+0xc4,0x27,0xe3,0x17 = and.p %r15, %r15, 31
+0xc4,0x20,0x24,0x0 = and.n %r0, %r0, 0
+0xc4,0x26,0x27,0x4 = and.vs %r6, %r6, 16
+0xc4,0x27,0xef,0x17 = and.pnz %r15, %r15, 31
+0xc4,0x20,0x21,0x80 = and.eq.f %r0, %r0, 0
+0xc4,0x26,0x2b,0x84 = and.lt.f %r6, %r6, 16
+0xc4,0x27,0xec,0x97 = and.le.f %r15, %r15, 31
+0xc4,0x20,0x29,0x80 = and.gt.f %r0, %r0, 0
+0xc4,0x26,0x2a,0x84 = and.ge.f %r6, %r6, 16
+0xc4,0x27,0xe3,0x97 = and.p.f %r15, %r15, 31
+0xc4,0x20,0x24,0x80 = and.n.f %r0, %r0, 0
+0xc4,0x26,0x27,0x84 = and.vs.f %r6, %r6, 16
+0xc4,0x27,0xef,0x97 = and.pnz.f %r15, %r15, 31
+0x40,0x29,0x81,0x0 = asl %r1, %r1, 2
+0x0,0x28,0x0,0x0 = asl %r0, %r0, %r0
+0x0,0x28,0x0,0x80 = asl.f %r0, %r0, %r0
+0x42,0x2a,0xc1,0x7 = asr %r1, %r2, 31
+0x42,0x2a,0xc1,0x87 = asr.f %r1, %r2, 31
+0x42,0x2b,0xc1,0x1 = asr %r1, %r3, 7
+0x2,0x29,0x81,0x0 = asr %r1, %r1, %r2
+0x8,0x22,0x40,0x0 = max %r0, %r2, %r1
+0x48,0x21,0xc0,0x3 = max %r0, %r1, 15
+0x8,0x22,0x80,0xf,0x0,0x0,0xa0,0xf = max %r0, %r2, 4000
+0x88,0x22,0xc3,0xf = max %r2, %r2, 255
+0x5,0x20,0x92,0x2f,0x0,0x0,0x0,0xf0 = or %r18, %r16, 61440
+0x5,0x20,0x92,0xaf,0x0,0x0,0x0,0xf0 = or.f %r18, %r16, 61440
+0x5,0x21,0x81,0x3 = or %r1, %r1, %r14
+0x5,0x26,0x41,0x10 = or %r1, %r14, %r1
+0x85,0x21,0x2,0x0 = or %r1, %r1, 128
+0x2,0x23,0x9c,0x3f,0x0,0x0,0x5c,0x0 = sub %sp, %fp, 92
+0x2,0x27,0x2,0x1 = sub %r2, %r7, %r4
+0x2,0x27,0x2,0x81 = sub.f %r2, %r7, %r4
+0x2,0x26,0x0,0x20 = sub %r0, %r22, %r0
+0x17,0x23,0x43,0x30 = sub1 %r3, %fp, %r1
+0x58,0x23,0x43,0x34 = sub2 %r3, %fp, 17
+0x99,0x23,0xff,0x3f = sub3 %fp, %fp, -1
+0x99,0x23,0xff,0xbf = sub3.f %fp, %fp, -1
+0xce,0x20,0xe2,0x7 = rsub.ne %r0, %r0, 31
+0xce,0x20,0x61,0x0 = rsub.eq %r0, %r0, 1
+0xce,0x26,0x2b,0x4 = rsub.lt %r6, %r6, 16
+0xce,0x27,0xec,0x17 = rsub.le %r15, %r15, 31
+0xce,0x20,0x69,0x0 = rsub.gt %r0, %r0, 1
+0xce,0x26,0x2a,0x4 = rsub.ge %r6, %r6, 16
+0xce,0x27,0xe3,0x17 = rsub.p %r15, %r15, 31
+0xce,0x20,0x64,0x0 = rsub.n %r0, %r0, 1
+0xce,0x26,0x27,0x4 = rsub.vs %r6, %r6, 16
+0xce,0x27,0xef,0x17 = rsub.pnz %r15, %r15, 31
+0xce,0x20,0xe2,0x87 = rsub.ne.f %r0, %r0, 31
+0xce,0x20,0x61,0x80 = rsub.eq.f %r0, %r0, 1
+0xce,0x26,0x2b,0x84 = rsub.lt.f %r6, %r6, 16
+0xce,0x27,0xec,0x97 = rsub.le.f %r15, %r15, 31
+0xce,0x20,0x69,0x80 = rsub.gt.f %r0, %r0, 1
+0xce,0x26,0x2a,0x84 = rsub.ge.f %r6, %r6, 16
+0xce,0x27,0xe3,0x97 = rsub.p.f %r15, %r15, 31
+0xce,0x20,0x64,0x80 = rsub.n.f %r0, %r0, 1
+0xce,0x26,0x27,0x84 = rsub.vs.f %r6, %r6, 16
+0xce,0x27,0xef,0x97 = rsub.pnz.f %r15, %r15, 31
+0x1,0x20,0x0,0x0 = adc %r0, %r0, %r0
+0x1,0x20,0x4,0x0 = adc %r4, %r0, %r0
+0x1,0x20,0x4,0x80 = adc.f %r4, %r0, %r0
+0x1,0x20,0xc2,0x0 = adc %r2, %r0, %r3
+0x1,0x20,0x2,0x1 = adc %r2, %r0, %r4
+0x1,0x27,0x2,0x1 = adc %r2, %r7, %r4
+0xc1,0x20,0x61,0x0 = adc.eq %r0, %r0, 1
+0xc1,0x26,0x2b,0x4 = adc.lt %r6, %r6, 16
+0xc1,0x27,0xec,0x17 = adc.le %r15, %r15, 31
+0xc1,0x20,0x69,0x0 = adc.gt %r0, %r0, 1
+0xc1,0x26,0x2a,0x4 = adc.ge %r6, %r6, 16
+0xc1,0x27,0xe3,0x17 = adc.p %r15, %r15, 31
+0xc1,0x20,0x64,0x0 = adc.n %r0, %r0, 1
+0xc1,0x26,0x27,0x4 = adc.vs %r6, %r6, 16
+0xc1,0x27,0xef,0x17 = adc.pnz %r15, %r15, 31
+0xc1,0x20,0x61,0x80 = adc.eq.f %r0, %r0, 1
+0xc1,0x26,0x2b,0x84 = adc.lt.f %r6, %r6, 16
+0xc1,0x27,0xec,0x97 = adc.le.f %r15, %r15, 31
+0xc1,0x20,0x69,0x80 = adc.gt.f %r0, %r0, 1
+0xc1,0x26,0x2a,0x84 = adc.ge.f %r6, %r6, 16
+0xc1,0x27,0xe3,0x97 = adc.p.f %r15, %r15, 31
+0xc1,0x20,0x64,0x80 = adc.n.f %r0, %r0, 1
+0xc1,0x26,0x27,0x84 = adc.vs.f %r6, %r6, 16
+0xc1,0x27,0xef,0x97 = adc.pnz.f %r15, %r15, 31
+0x3,0x20,0x0,0x0 = sbc %r0, %r0, %r0
+0x3,0x20,0x4,0x0 = sbc %r4, %r0, %r0
+0x3,0x20,0x4,0x80 = sbc.f %r4, %r0, %r0
+0x3,0x20,0xc2,0x0 = sbc %r2, %r0, %r3
+0x3,0x20,0x2,0x1 = sbc %r2, %r0, %r4
+0x3,0x27,0x2,0x1 = sbc %r2, %r7, %r4
+0xc3,0x20,0x61,0x0 = sbc.eq %r0, %r0, 1
+0xc3,0x26,0x2b,0x4 = sbc.lt %r6, %r6, 16
+0xc3,0x27,0xec,0x17 = sbc.le %r15, %r15, 31
+0xc3,0x20,0x69,0x0 = sbc.gt %r0, %r0, 1
+0xc3,0x26,0x2a,0x4 = sbc.ge %r6, %r6, 16
+0xc3,0x27,0xe3,0x17 = sbc.p %r15, %r15, 31
+0xc3,0x20,0x64,0x0 = sbc.n %r0, %r0, 1
+0xc3,0x26,0x27,0x4 = sbc.vs %r6, %r6, 16
+0xc3,0x27,0xef,0x17 = sbc.pnz %r15, %r15, 31
+0xc3,0x20,0x61,0x80 = sbc.eq.f %r0, %r0, 1
+0xc3,0x26,0x2b,0x84 = sbc.lt.f %r6, %r6, 16
+0xc3,0x27,0xec,0x97 = sbc.le.f %r15, %r15, 31
+0xc3,0x20,0x69,0x80 = sbc.gt.f %r0, %r0, 1
+0xc3,0x26,0x2a,0x84 = sbc.ge.f %r6, %r6, 16
+0xc3,0x27,0xe3,0x97 = sbc.p.f %r15, %r15, 31
+0xc3,0x20,0x64,0x80 = sbc.n.f %r0, %r0, 1
+0xc3,0x26,0x27,0x84 = sbc.vs.f %r6, %r6, 16
+0xc3,0x27,0xef,0x97 = sbc.pnz.f %r15, %r15, 31
diff --git a/suite/MC/ARC/br_arc.s.cs b/suite/MC/ARC/br_arc.s.cs
new file mode 100644
index 0000000000..d27d1c08e9
--- /dev/null
+++ b/suite/MC/ARC/br_arc.s.cs
@@ -0,0 +1,12 @@
+# CS_ARCH_ARC, CS_MODE_LITTLE_ENDIAN, None
+
+0x3d,0xa,0x12,0x0 = brlt %r2, 0, 60
+0x91,0xa,0x4,0x91 = brlo %r10, %r4, -112
+0x2d,0xa,0x40,0x0 = breq %r2, %r1, 44
+0xf1,0x8,0x11,0x80 = brne %r0, 0, -16
+0x27,0xa,0x5,0x2 = brhs %r2, %r8, 38
+0x30,0x1,0x2,0x0 = bne 304
+0xc,0x1,0x1,0x0 = beq 268
+0xa0,0x1,0xd,0x0 = bhi 416
+0xbd,0x7,0xcf,0xff = b -68
+0x0,0x0,0x9e,0x0 = b 4096
diff --git a/suite/MC/ARC/compact_arc.s.cs b/suite/MC/ARC/compact_arc.s.cs
new file mode 100644
index 0000000000..ea6b46e299
--- /dev/null
+++ b/suite/MC/ARC/compact_arc.s.cs
@@ -0,0 +1,128 @@
+# CS_ARCH_ARC, CS_MODE_LITTLE_ENDIAN, None
+
+0x31,0x78 = abs_s %r0, %r1
+0x58,0x61 = add_s %r0, %r1, %r2
+0x63,0x70 = add_s %r0, %r0, %fp
+0x67,0x77 = add_s %fp, %fp, -1
+0x67,0x76 = add_s %fp, %fp, 6
+0xc3,0x70,0x22,0x11,0x44,0x33 = add_s %r0, %r0, 287454020
+0xc7,0x74,0x22,0x11,0x44,0x33 = add_s 0, 287454020, 4
+0x90,0xc0 = add_s %r0, %sp, 64
+0x40,0xe0 = add_s %r0, %r0, 64
+0x7,0x69 = add_s %r0, %r1, 7
+0xb0,0xc0 = add_s %sp, %sp, 64
+0xff,0xcf = add_s %r0, %gp, -4
+0xc,0x49 = add_s %r0, %r1, 4
+0x8c,0x48 = add_s %r1, %r0, 4
+0x34,0x78 = add1_s %r0, %r0, %r1
+0x35,0x78 = add2_s %r0, %r0, %r1
+0x36,0x78 = add3_s %r0, %r0, %r1
+0x24,0x78 = and_s %r0, %r0, %r1
+0x3b,0x78 = asl_s %r0, %r1
+0x34,0x68 = asl_s %r1, %r0, 4
+0x38,0x78 = asl_s %r0, %r0, %r1
+0x10,0xb8 = asl_s %r0, %r0, 16
+0x3c,0x78 = asr_s %r0, %r1
+0x3c,0x68 = asr_s %r1, %r0, 4
+0x3a,0x78 = asr_s %r0, %r0, %r1
+0x50,0xb8 = asr_s %r0, %r0, 16
+0x80,0xf0 = b_s 256
+0xfe,0xf1 = b_s -4
+0xfe,0xf3 = beq_s -4
+0xfe,0xf5 = bne_s -4
+0x3e,0xf6 = bgt_s -4
+0x7e,0xf6 = bge_s -4
+0xbe,0xf6 = blt_s -4
+0xfe,0xf6 = ble_s -4
+0x3e,0xf7 = bhi_s -4
+0x7e,0xf7 = bhs_s -4
+0xbe,0xf7 = blo_s -4
+0xfe,0xf7 = bls_s -4
+0xb8,0xb8 = bclr_s %r0, %r0, 24
+0x26,0x78 = bic_s %r0, %r0, %r1
+0xc0,0xff = bl_s -256
+0xd8,0xb8 = bmsk_s %r0, %r0, 24
+0xc0,0xe8 = brne_s %r0, 0, -128
+0x40,0xe8 = breq_s %r0, 0, -128
+0xff,0x7f = brk_s
+0x98,0xb8 = bset_s %r0, %r0, 24
+0xf8,0xb8 = btst_s %r0, 24
+0x93,0x70 = cmp_s %r0, %sp
+0x97,0x77 = cmp_s %sp, -1
+0xc0,0xe2 = cmp_s %r2, 64
+0x0,0x5e = ei_s 512
+0xe0,0xc1 = enter_s 16
+0x2f,0x78 = extb_s %r0, %r1
+0x30,0x78 = exth_s %r0, %r1
+0x0,0x78 = j_s [%r0]
+0xe0,0x7e = j_s [%blink]
+0x20,0x78 = j_s.d [%r0]
+0xe0,0x7f = j_s.d [%blink]
+0xe0,0x7c = jeq_s [%blink]
+0xe0,0x7d = jne_s [%blink]
+0x40,0x78 = jl_s [%r0]
+0x60,0x78 = jl_s.d [%r0]
+0x0,0x5a = jli_s 512
+0x40,0x61 = ld_s %r0, [%r1, %r2]
+0x10,0xc0 = ld_s %r0, [%sp, 64]
+0x80,0xd0 = ld_s %r0, [%pcl, 512]
+0x30,0x80 = ld_s %r1, [%r0, 64]
+0x0,0xc9 = ld_s %r0, [%gp, -1024]
+0x48,0x61 = ldb_s %r0, [%r1, %r2]
+0x30,0xc0 = ldb_s %r0, [%sp, 64]
+0x30,0x88 = ldb_s %r1, [%r0, 16]
+0x0,0xcb = ldb_s %r0, [%gp, -256]
+0x50,0x61 = ldh_s %r0, [%r1, %r2]
+0x30,0x90 = ldh_s %r1, [%r0, 32]
+0x0,0xcd = ldh_s %r0, [%gp, -512]
+0x30,0x98 = ldh_s.x %r1, [%r0, 32]
+0x36,0x40 = ld_s %r0, [%r17, 8]
+0x36,0x41 = ld_s %r1, [%r17, 8]
+0x36,0x42 = ld_s %r2, [%r17, 8]
+0x36,0x43 = ld_s %r3, [%r17, 8]
+0x40,0x49 = ld_s.as %r0, [%r1, %r2]
+0x0,0x54 = ld_s %r1, [%gp, -1024]
+0x88,0x50 = ldi_s %r0, [64]
+0xc0,0xc1 = leave_s 16
+0x3d,0x78 = lsr_s %r0, %r1
+0x39,0x78 = lsr_s %r0, %r0, %r1
+0x30,0xb8 = lsr_s %r0, %r0, 16
+0x2e,0x77 = mov_s %r17, -1
+0xcf,0x75 = mov_s 0, 5
+0x3e,0x70 = mov_s.ne %r0, %r17
+0xdf,0x70,0x0,0x0,0x0,0x4 = mov_s.ne %r0, 1024
+0x80,0xd8 = mov_s %r0, 128
+0x32,0x40 = mov_s %r16, %r17
+0xd3,0x40,0x0,0x0,0x0,0x4 = mov_s %r16, 1024
+0x3a,0x46 = mov_s 0, %r17
+0xdb,0x46,0x0,0x0,0x0,0x4 = mov_s 0, 1024
+0x2c,0x78 = mpy_s %r0, %r0, %r1
+0x2a,0x78 = mpyuw_s %r0, %r0, %r1
+0x29,0x78 = mpyw_s %r0, %r0, %r1
+0x33,0x78 = neg_s %r0, %r1
+0xe0,0x78 = nop_s
+0x32,0x78 = not_s %r0, %r1
+0x25,0x78 = or_s %r0, %r0, %r1
+0xe1,0xc0 = pop_s %r0
+0xd1,0xc0 = pop_s %blink
+0xc1,0xc0 = push_s %r0
+0xf1,0xc0 = push_s %blink
+0x2d,0x78 = sexb_s %r0, %r1
+0x2e,0x78 = sexh_s %r0, %r1
+0x50,0xc0 = st_s %r0, [%sp, 64]
+0x30,0xa0 = st_s %r1, [%r0, 64]
+0x10,0x54 = st_s %r0, [%gp, -1024]
+0x70,0xc0 = stb_s %r0, [%sp, 64]
+0x30,0xa8 = stb_s %r1, [%r0, 16]
+0x30,0xb0 = sth_s %r1, [%r0, 32]
+0x2c,0x68 = sub_s %r1, %r0, 4
+0xc0,0x78 = sub_s.ne %r0, %r0, %r0
+0x22,0x78 = sub_s %r0, %r0, %r1
+0x70,0xb8 = sub_s %r0, %r0, 16
+0xb0,0xc1 = sub_s %sp, %sp, 64
+0x50,0x49 = sub_s %r0, %r1, %r2
+0xe0,0x7a = swi_s
+0x1e,0x7c = trap_s 32
+0x2b,0x78 = tst_s %r0, %r1
+0xe0,0x79 = unimp_s
+0x27,0x78 = xor_s %r0, %r0, %r1
diff --git a/suite/MC/ARC/ldst_arc.s.cs b/suite/MC/ARC/ldst_arc.s.cs
new file mode 100644
index 0000000000..0a7ed9bf7e
--- /dev/null
+++ b/suite/MC/ARC/ldst_arc.s.cs
@@ -0,0 +1,38 @@
+# CS_ARCH_ARC, CS_MODE_LITTLE_ENDIAN, None
+
+0x0,0x10,0x0,0x0 = ld %r0, [%r0,0]
+0x0,0x10,0x0,0x1 = ldh %r0, [%r0,0]
+0x0,0x10,0x80,0x0 = ldb %r0, [%r0,0]
+0xc,0x10,0x1,0x0 = ld %r1, [%r0,12]
+0xf4,0x13,0xe,0xb0 = ld %r14, [%fp,-12]
+0xf4,0x10,0x3,0x80 = ld %r3, [%r0,-12]
+0xf4,0x10,0x0,0x0 = ld %r0, [%r0,244]
+0xf4,0x10,0x0,0x80 = ld %r0, [%r0,-12]
+0x0,0x11,0x43,0x1 = ldh.x %r3, [%r1,0]
+0x2,0x11,0x42,0x1 = ldh.x %r2, [%r1,2]
+0x7c,0x13,0x42,0xb1 = ldh.x %r2, [%fp,-132]
+0x30,0x20,0x80,0xf,0x0,0x0,0x0,0xfa = ld %r0, [%r0,64000]
+0x0,0x16,0x6,0x70,0x0,0x0,0xb0,0xf9 = ld %r6, [63920]
+0x23,0x1c,0x82,0x30 = stb %r2, [%sp,35]
+0x0,0x1e,0xc0,0x71,0x0,0x0,0xb0,0xf9 = st %r7, [63920]
+0x1,0x10,0x81,0x4 = ldb.ab %r1, [%r0,1]
+0x1,0x18,0x92,0x0 = stb.ab %r2, [%r0,1]
+0xc,0x10,0x3,0x5 = ldh.ab %r3, [%r0,12]
+0x12,0x18,0x14,0x1 = sth.ab %r4, [%r0,18]
+0x80,0x12,0x5,0x4 = ld.ab %r5, [%r2,128]
+0x40,0x1a,0x90,0x1 = st.ab %r6, [%r2,64]
+0x1,0x10,0x87,0x2 = ldb.aw %r7, [%r0,1]
+0x1,0x18,0xa,0x2 = stb.aw %r8, [%r0,1]
+0xc,0x10,0x3,0x3 = ldh.aw %r3, [%r0,12]
+0x12,0x18,0xcc,0x0 = sth.aw %r3, [%r0,18]
+0x80,0x12,0x6,0x2 = ld.aw %r6, [%r2,128]
+0x40,0x1a,0x88,0x1 = st.aw %r6, [%r2,64]
+0x8,0x10,0xc0,0x1a = ldb.x.di.aw %r0, [%r8,8]
+0x40,0x19,0x32,0x10 = stb.di.ab %r0, [%r9,64]
+0x6a,0x20,0x40,0x8 = lr %r0, [33]
+0x6a,0x27,0x40,0x8 = lr %r7, [33]
+0x6a,0x27,0x40,0x18 = lr %r15, [33]
+0x6a,0x26,0x40,0x28 = lr %r22, [33]
+0xaa,0x20,0x60,0x8 = lr %r0, [-33]
+0xaa,0x20,0x41,0x8 = lr %r0, [97]
+0xaa,0x20,0x61,0x8 = lr %r0, [-97]
diff --git a/suite/MC/ARC/misc_arc.c.cs b/suite/MC/ARC/misc_arc.c.cs
new file mode 100644
index 0000000000..abb93a4768
--- /dev/null
+++ b/suite/MC/ARC/misc_arc.c.cs
@@ -0,0 +1,51 @@
+# CS_ARCH_ARC, CS_MODE_LITTLE_ENDIAN, None
+
+0x8a,0x20,0xff,0xf = mov %r0, -1
+0xa,0x24,0x80,0xf,0x0,0x0,0xff,0x7f = mov %r4, 32767
+0xca,0x22,0x81,0x1 = mov.eq %r2, %r6
+0xa,0x25,0x80,0x10 = mov %r13, %r2
+0x4a,0x21,0x0,0x5 = mov %r1, 20
+0xca,0x20,0x21,0x8 = mov.eq %r0, 32
+0xca,0x20,0x22,0x0 = mov.ne %r0, 0
+0xca,0x20,0x21,0x0 = mov.eq %r0, 0
+0xca,0x26,0x2b,0x4 = mov.lt %r6, 16
+0xca,0x27,0xec,0x17 = mov.le %r15, 31
+0xca,0x20,0x29,0x0 = mov.gt %r0, 0
+0xca,0x26,0x2a,0x4 = mov.ge %r6, 16
+0xca,0x27,0xe3,0x17 = mov.p %r15, 31
+0xca,0x20,0x24,0x0 = mov.n %r0, 0
+0xca,0x26,0x27,0x4 = mov.vs %r6, 16
+0xca,0x27,0xef,0x17 = mov.pnz %r15, 31
+0x4a,0x20,0x0,0x80 = mov.f %r0, 0
+0x4a,0x26,0x0,0x84 = mov.f %r6, 16
+0x4a,0x27,0xc0,0x97 = mov.f %r15, 31
+0xca,0x20,0x21,0x80 = mov.eq.f %r0, 0
+0xca,0x26,0x2b,0x84 = mov.lt.f %r6, 16
+0xca,0x27,0xec,0x97 = mov.le.f %r15, 31
+0xca,0x20,0x29,0x80 = mov.gt.f %r0, 0
+0xca,0x26,0x2a,0x84 = mov.ge.f %r6, 16
+0xca,0x27,0xe3,0x97 = mov.p.f %r15, 31
+0xca,0x20,0x24,0x80 = mov.n.f %r0, 0
+0xca,0x26,0x27,0x84 = mov.vs.f %r6, 16
+0xca,0x27,0xef,0x97 = mov.pnz.f %r15, 31
+0xfc,0x1c,0xc8,0xb6 = st.aw %fp, [%sp,-4]
+0x4,0x14,0x1b,0x34 = ld.ab %fp, [%sp,4]
+0x16,0x8,0xcf,0xff = bl -2028
+0xc,0x25,0x80,0x92 = cmp %r13, %r10
+0x4c,0x26,0x0,0x90 = cmp %r14, 0
+0x4c,0x27,0x40,0xa0 = cmp %r23, 1
+0x22,0x20,0x40,0x5 = jl [%r21]
+0x22,0x20,0x80,0xf,0x0,0x0,0x39,0x30 = jl 12345
+0x20,0x20,0xc0,0x0 = j [%r3]
+0x20,0x20,0x80,0xf,0x0,0x0,0x39,0x30 = j 12345
+0x38,0x23,0x43,0x30 = seteq %r3, %fp, %r1
+0x78,0x23,0x43,0x34 = seteq %r3, %fp, 17
+0xb8,0x23,0xff,0x3f = seteq %fp, %fp, -1
+0x2f,0x28,0x13,0x0 = fls %r0, %r0
+0x2f,0x28,0x13,0x80 = fls.f %r0, %r0
+0x2f,0x28,0x12,0x0 = ffs %r0, %r0
+0x2f,0x28,0x12,0x80 = ffs.f %r0, %r0
+0x2f,0x2f,0xd2,0x13 = ffs %r15, %r15
+0x2f,0x2f,0xd2,0x93 = ffs.f %r15, %r15
+0x2f,0x2e,0xc1,0x27 = norm %r22, %blink
+0x2f,0x2f,0x88,0x4 = normh %r7, %r18
diff --git a/suite/auto-sync/src/autosync/Targets.py b/suite/auto-sync/src/autosync/Targets.py
index daa27125a6..cb2193206f 100644
--- a/suite/auto-sync/src/autosync/Targets.py
+++ b/suite/auto-sync/src/autosync/Targets.py
@@ -12,6 +12,7 @@
     "Mips",
     "Xtensa",
     "TriCore",
+    "ARC",
 ]
 
 # Names of the target architecture as they are used in code and pretty much everywhere else.
@@ -25,6 +26,7 @@
     "Mips",
     "Xtensa",
     "TriCore",
+    "ARC",
 ]
 
 # Maps the target full name to the name used in code (and pretty much everywhere else).
@@ -38,6 +40,7 @@
     "Mips": "Mips",
     "Xtensa": "Xtensa",
     "TriCore": "TriCore",
+    "ARC": "ARC",
     "ARCH": "ARCH",  # For testing
 }
 
@@ -52,5 +55,6 @@
     "Mips": "Mips",
     "Xtensa": "Xtensa",
     "TriCore": "TriCore",
+    "ARC": "ARC",
     "ARCH": "ARCH",  # For testing
 }
diff --git a/suite/auto-sync/src/autosync/cpptranslator/CppTranslator.py b/suite/auto-sync/src/autosync/cpptranslator/CppTranslator.py
index a5ae11e5c8..d98f8631a5 100755
--- a/suite/auto-sync/src/autosync/cpptranslator/CppTranslator.py
+++ b/suite/auto-sync/src/autosync/cpptranslator/CppTranslator.py
@@ -50,6 +50,7 @@
 from autosync.cpptranslator.patches.IsRegImm import IsOperandRegImm
 from autosync.cpptranslator.patches.LLVMFallThrough import LLVMFallThrough
 from autosync.cpptranslator.patches.LLVMunreachable import LLVMUnreachable
+from autosync.cpptranslator.patches.BadConditionCode import BadConditionCode
 from autosync.cpptranslator.patches.LLVM_DEBUG import LLVM_DEBUG
 from autosync.cpptranslator.patches.MethodToFunctions import MethodToFunction
 from autosync.cpptranslator.patches.MethodTypeQualifier import MethodTypeQualifier
@@ -154,6 +155,7 @@ class Translator:
         Assert.__name__: 0,  # ◁─────────┐ The llvm_unreachable calls are replaced with asserts.
         LLVMUnreachable.__name__: 1,  # ─┘ Those assert should stay.
         LLVMFallThrough.__name__: 0,
+        BadConditionCode.__name__: 0,
         LLVM_DEBUG.__name__: 0,
         DeclarationInConditionalClause.__name__: 0,
         StreamOperations.__name__: 0,
@@ -289,6 +291,8 @@ def init_patches(self):
                     patch = Assert(p)
                 case LLVMFallThrough.__name__:
                     patch = LLVMFallThrough(p)
+                case BadConditionCode.__name__:
+                    patch = BadConditionCode(p)
                 case DeclarationInConditionalClause.__name__:
                     patch = DeclarationInConditionalClause(p)
                 case OutStreamParam.__name__:
diff --git a/suite/auto-sync/src/autosync/cpptranslator/Tests/test_patches.py b/suite/auto-sync/src/autosync/cpptranslator/Tests/test_patches.py
index 0c5ea484db..9deeb99f9f 100644
--- a/suite/auto-sync/src/autosync/cpptranslator/Tests/test_patches.py
+++ b/suite/auto-sync/src/autosync/cpptranslator/Tests/test_patches.py
@@ -78,6 +78,7 @@
 from autosync.cpptranslator.patches.UseMarkup import UseMarkup
 from autosync.cpptranslator.patches.UsingDeclaration import UsingDeclaration
 from autosync.cpptranslator.TemplateCollector import TemplateCollector
+from autosync.cpptranslator.patches.BadConditionCode import BadConditionCode
 from autosync.Helper import get_path
 from autosync.cpptranslator.patches.isUInt import IsUInt
 
@@ -296,6 +297,13 @@ def test_fieldfrominstr(self):
             b"fieldFromInstruction_4(Val, 0, 4)",
         )
 
+        syntax = b"static unsigned function(unsigned Insn) { return fieldFromInstruction(Insn, 6, 6); }"
+        self.check_patching_result(
+            patch,
+            syntax,
+            b"fieldFromInstruction_4(Insn, 6, 6)",
+        )
+
     def test_getnumoperands(self):
         patch = GetNumOperands(0)
         syntax = b"MI.getNumOperands();"
@@ -612,3 +620,10 @@ def test_isuintn(self):
         patch = IsUInt(0)
         syntax = b"isUInt<RegUnitBits>(FirstRU);"
         self.check_patching_result(patch, syntax, b"isUIntN(RegUnitBits, FirstRU)")
+
+    def test_badconditioncode(self):
+        patch = BadConditionCode(0)
+        syntax = b"return BadConditionCode(BRCC)"
+        self.check_patching_result(
+            patch, syntax, b'CS_ASSERT(0 && "Unknown condition code passed");'
+        )
diff --git a/suite/auto-sync/src/autosync/cpptranslator/arch_config.json b/suite/auto-sync/src/autosync/cpptranslator/arch_config.json
index 4d295bb1b6..c0ae74d4ec 100644
--- a/suite/auto-sync/src/autosync/cpptranslator/arch_config.json
+++ b/suite/auto-sync/src/autosync/cpptranslator/arch_config.json
@@ -264,5 +264,31 @@
     "files_for_template_search": [],
     "templates_with_arg_deduction": [],
     "manually_edited_files": []
+  },
+  "ARC": {
+    "files_to_translate": [
+      {
+        "in": "{LLVM_ROOT}/llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp",
+        "out": "ARCDisassembler.c"
+      },{
+        "in": "{LLVM_ROOT}/llvm/lib/Target/ARC/MCTargetDesc/ARCInstPrinter.cpp",
+        "out": "ARCInstPrinter.c"
+      },{
+        "in": "{LLVM_ROOT}/llvm/lib/Target/ARC/MCTargetDesc/ARCInstPrinter.h",
+        "out": "ARCInstPrinter.h"
+      },
+      {
+        "in": "{LLVM_ROOT}/llvm/lib/Target/ARC/MCTargetDesc/ARCInfo.h",
+        "out": "ARCInfo.h"
+      }
+    ],
+    "files_for_template_search": [
+      "{CPP_INC_OUT_DIR}/ARCGenDisassemblerTables.inc",
+      "{CPP_INC_OUT_DIR}/ARCGenAsmWriter.inc",
+      "{LLVM_ROOT}/llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp",
+      "{LLVM_ROOT}/llvm/lib/Target/ARC/MCTargetDesc/ARCInstPrinter.cpp"
+    ],
+    "templates_with_arg_deduction": [],
+    "manually_edited_files": []
   }
 }
diff --git a/suite/auto-sync/src/autosync/cpptranslator/patches/BadConditionCode.py b/suite/auto-sync/src/autosync/cpptranslator/patches/BadConditionCode.py
new file mode 100644
index 0000000000..988a775d10
--- /dev/null
+++ b/suite/auto-sync/src/autosync/cpptranslator/patches/BadConditionCode.py
@@ -0,0 +1,32 @@
+# Copyright © 2024 Dmitry Sibitsev <sibirtsevdl@gmail.com>
+# SPDX-License-Identifier: BSD-3
+
+from tree_sitter import Node
+
+from autosync.cpptranslator.patches.Patch import Patch
+
+
+class BadConditionCode(Patch):
+    """
+    Patch   return BadConditionCode
+    to      CS_ASSERT(0 && "Unknown condition code passed")
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return (
+            "(return_statement "
+            "    (call_expression "
+            '        (identifier) @fcn_name (#eq? @fcn_name "BadConditionCode")'
+            "        (argument_list)"
+            "    )"
+            ") @bad_condition_code"
+        )
+
+    def get_main_capture_name(self) -> str:
+        return "bad_condition_code"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        return b'CS_ASSERT(0 && "Unknown condition code passed");'
diff --git a/suite/auto-sync/src/autosync/cpptranslator/patches/FieldFromInstr.py b/suite/auto-sync/src/autosync/cpptranslator/patches/FieldFromInstr.py
index 58092ea09d..ffcd65ab7c 100644
--- a/suite/auto-sync/src/autosync/cpptranslator/patches/FieldFromInstr.py
+++ b/suite/auto-sync/src/autosync/cpptranslator/patches/FieldFromInstr.py
@@ -47,14 +47,20 @@ def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
         else:
             # Get the Val/Inst parameter.
             # Its type determines the instruction width.
-            inst_param: Node = param_list_caller.named_children[1]
+            if len(param_list_caller.named_children) == 1:
+                # If function just return fieldFromInstruction(...)
+                inst_param: Node = param_list_caller.named_children[0]
+            else:
+                inst_param = param_list_caller.named_children[1]
             inst_param_text = get_text(src, inst_param.start_byte, inst_param.end_byte)
 
             # Search for the 'Inst' parameter and determine its type
             # and with it the width of the instruction.
             inst_type = inst_param_text.split(b" ")[0]
             if inst_type:
-                if inst_type in [b"unsigned", b"uint32_t"]:
+                if inst_type in [b"uint64_t"]:
+                    inst_width = b"8"
+                elif inst_type in [b"unsigned", b"uint32_t"]:
                     inst_width = b"4"
                 elif inst_type in [b"uint16_t"]:
                     inst_width = b"2"
diff --git a/suite/auto-sync/src/autosync/cpptranslator/patches/Includes.py b/suite/auto-sync/src/autosync/cpptranslator/patches/Includes.py
index a5417a0a1b..579eea9640 100644
--- a/suite/auto-sync/src/autosync/cpptranslator/patches/Includes.py
+++ b/suite/auto-sync/src/autosync/cpptranslator/patches/Includes.py
@@ -70,6 +70,8 @@ def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
                 return res + get_SystemZ_includes(filename) + get_general_macros()
             case "Xtensa":
                 return res + get_Xtensa_includes(filename) + get_general_macros()
+            case "ARC":
+                return res + get_ARC_includes(filename) + get_general_macros()
             case "TEST_ARCH":
                 return res + b"test_output"
             case _:
@@ -416,6 +418,33 @@ def get_Xtensa_includes(filename: str) -> bytes:
             return b""
 
 
+def get_ARC_includes(filename: str) -> bytes:
+    match filename:
+        case "ARCDisassembler.cpp":
+            return (
+                b'#include "../../MCInst.h"\n'
+                + b'#include "../../SStream.h"\n'
+                + b'#include "../../MCDisassembler.h"\n'
+                + b'#include "../../MCFixedLenDisassembler.h"\n'
+                + b'#include "../../MathExtras.h"\n'
+                + b'#include "../../utils.h"\n'
+            )
+        case "ARCInstPrinter.cpp":
+            return (
+                b'#include "../../SStream.h"\n'
+                + b'#include "../../MCInst.h"\n'
+                + b'#include "../../MCInstPrinter.h"\n'
+                + b'#include "ARCInfo.h"\n'
+                + b'#include "ARCInstPrinter.h"\n'
+                + b'#include "ARCLinkage.h"\n'
+                + b'#include "ARCMapping.h"\n'
+            )
+        case "ARCInstPrinter.h":
+            return b'#include "../../SStream.h"\n' + b'#include "../../MCInst.h"\n'
+    log.fatal(f"No includes given for ARC source file: {filename}")
+    exit(1)
+
+
 def get_general_macros():
     return (
         b"#define CONCAT(a, b) CONCAT_(a, b)\n" b"#define CONCAT_(a, b) a ## _ ## b\n"
diff --git a/suite/capstone_get_setup.c b/suite/capstone_get_setup.c
index efbd725f0b..f682b5b326 100644
--- a/suite/capstone_get_setup.c
+++ b/suite/capstone_get_setup.c
@@ -85,6 +85,9 @@ int main()
 	if (cs_support(CS_ARCH_XTENSA)) {
 		printf("xtensa=1 ");
 	}
+	if (cs_support(CS_ARCH_ARC)) {
+		printf("arc=1 ");
+	}
 	printf("\n");
 
 	return 0;
diff --git a/suite/cstest/include/test_detail.h b/suite/cstest/include/test_detail.h
index 0d82cd51df..16c726915e 100644
--- a/suite/cstest/include/test_detail.h
+++ b/suite/cstest/include/test_detail.h
@@ -32,6 +32,7 @@
 #include "test_detail_x86.h"
 #include "test_detail_m68k.h"
 #include "test_detail_xtensa.h"
+#include "test_detail_arc.h"
 #include "test_compare.h"
 #include <capstone/capstone.h>
 #include <cyaml/cyaml.h>
@@ -61,6 +62,7 @@ typedef struct {
 	TestDetailX86 *x86;
 	TestDetailM68K *m68k;
 	TestDetailXtensa *xtensa;
+	TestDetailARC *arc;
 
 	char **regs_read;
 	uint8_t regs_read_count;
@@ -150,6 +152,9 @@ static const cyaml_schema_field_t test_detail_mapping_schema[] = {
 	CYAML_FIELD_MAPPING_PTR(
 		"xtensa", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetail,
 		xtensa, test_detail_xtensa_mapping_schema),
+	CYAML_FIELD_MAPPING_PTR(
+		"arc", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetail,
+		arc, test_detail_arc_mapping_schema),
 	CYAML_FIELD_SEQUENCE("regs_read",
 			     CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
 			     TestDetail, regs_read, &single_string_schema, 0, 255),
diff --git a/suite/cstest/include/test_detail_arc.h b/suite/cstest/include/test_detail_arc.h
new file mode 100644
index 0000000000..b841f79d98
--- /dev/null
+++ b/suite/cstest/include/test_detail_arc.h
@@ -0,0 +1,60 @@
+// Copyright © 2024 Sibirtsev Dmitry <sibirtsevdl@gmail.com>
+// SPDX-License-Identifier: BSD-3
+
+#ifndef TEST_DETAIL_ARC_H
+#define TEST_DETAIL_ARC_H
+
+#include "test_compare.h"
+#include <cyaml/cyaml.h>
+#include <capstone/capstone.h>
+
+typedef struct {
+	char *type;
+	char *access;
+
+	char *reg;
+	int64_t imm;
+} TestDetailARCOp;
+
+static const cyaml_schema_field_t test_detail_arc_op_mapping_schema[] = {
+	CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailARCOp, type, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("access",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailARCOp, access, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailARCOp, reg, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailARCOp, imm),
+	CYAML_FIELD_END
+};
+
+static const cyaml_schema_value_t test_detail_arc_op_schema = {
+	CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailARCOp,
+			    test_detail_arc_op_mapping_schema),
+};
+
+typedef struct {
+	TestDetailARCOp **operands;
+	uint32_t operands_count;
+} TestDetailARC;
+
+static const cyaml_schema_field_t test_detail_arc_mapping_schema[] = {
+	CYAML_FIELD_SEQUENCE(
+		"operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailARC, operands, &test_detail_arc_op_schema, 0,
+		CYAML_UNLIMITED), // 0-MAX options
+	CYAML_FIELD_END
+};
+
+TestDetailARC *test_detail_arc_new();
+TestDetailARC *test_detail_arc_clone(const TestDetailARC *detail);
+void test_detail_arc_free(TestDetailARC *detail);
+
+TestDetailARCOp *test_detail_arc_op_new();
+TestDetailARCOp *test_detail_arc_op_clone(const TestDetailARCOp *detail);
+void test_detail_arc_op_free(TestDetailARCOp *detail);
+
+bool test_expected_arc(csh *handle, const cs_arc *actual,
+			 const TestDetailARC *expected);
+
+#endif // TEST_DETAIL_ARC_H
diff --git a/suite/cstest/include/test_mapping.h b/suite/cstest/include/test_mapping.h
index d82ec5462a..e5b47c44c6 100644
--- a/suite/cstest/include/test_mapping.h
+++ b/suite/cstest/include/test_mapping.h
@@ -18,6 +18,7 @@ static const cs_enum_id_map test_arch_map[] = {
 	{ .str = "AArch64", .val = CS_ARCH_AARCH64 },
 	{ .str = "CS_ARCH_AARCH64", .val = CS_ARCH_AARCH64 },
 	{ .str = "CS_ARCH_ALPHA", .val = CS_ARCH_ALPHA },
+	{ .str = "CS_ARCH_ARC", .val = CS_ARCH_ARC },
 	{ .str = "CS_ARCH_ARM", .val = CS_ARCH_ARM },
 	{ .str = "CS_ARCH_BPF", .val = CS_ARCH_BPF },
 	{ .str = "CS_ARCH_EVM", .val = CS_ARCH_EVM },
@@ -40,6 +41,7 @@ static const cs_enum_id_map test_arch_map[] = {
 	{ .str = "CS_ARCH_XTENSA", .val = CS_ARCH_XTENSA },
 	{ .str = "aarch64", .val = CS_ARCH_AARCH64 },
 	{ .str = "alpha", .val = CS_ARCH_ALPHA },
+	{ .str = "arc", .val = CS_ARCH_ARC },
 	{ .str = "arm", .val = CS_ARCH_ARM },
 	{ .str = "bpf", .val = CS_ARCH_BPF },
 	{ .str = "evm", .val = CS_ARCH_EVM },
@@ -313,6 +315,8 @@ static const cs_enum_id_map cs_enum_map[] = {
 	{ .str = "AArch64CC_VS", .val = AArch64CC_VS },
 	{ .str = "ALPHA_OP_IMM", .val = ALPHA_OP_IMM },
 	{ .str = "ALPHA_OP_REG", .val = ALPHA_OP_REG },
+	{ .str = "ARC_OP_IMM", .val = ARC_OP_IMM },
+	{ .str = "ARC_OP_REG", .val = ARC_OP_REG },
 	{ .str = "ARMCC_AL", .val = ARMCC_AL },
 	{ .str = "ARMCC_EQ", .val = ARMCC_EQ },
 	{ .str = "ARMCC_GE", .val = ARMCC_GE },
@@ -461,6 +465,10 @@ static const cs_enum_id_map cs_enum_map[] = {
 	{ .str = "Alpha_GRP_CALL", .val = Alpha_GRP_CALL },
 	{ .str = "Alpha_GRP_ENDING", .val = Alpha_GRP_ENDING },
 	{ .str = "Alpha_GRP_JUMP", .val = Alpha_GRP_JUMP },
+	{ .str = "ARC_GRP_JUMP", .val = ARC_GRP_JUMP },
+	{ .str = "ARC_GRP_CALL", .val = ARC_GRP_CALL },
+	{ .str = "ARC_GRP_RET", .val = ARC_GRP_RET },
+	{ .str = "ARC_GRP_BRANCH_RELATIVE", .val = ARC_GRP_BRANCH_RELATIVE },
 	{ .str = "BPF_EXT_LEN", .val = BPF_EXT_LEN },
 	{ .str = "BPF_GRP_ALU", .val = BPF_GRP_ALU },
 	{ .str = "BPF_GRP_CALL", .val = BPF_GRP_CALL },
diff --git a/suite/cstest/src/test_detail.c b/suite/cstest/src/test_detail.c
index 4755dc2273..6b7aa9d703 100644
--- a/suite/cstest/src/test_detail.c
+++ b/suite/cstest/src/test_detail.c
@@ -130,6 +130,9 @@ TestDetail *test_detail_clone(TestDetail *detail)
 	if (detail->xtensa) {
 		clone->xtensa = test_detail_xtensa_clone(detail->xtensa);
 	}
+	if (detail->arc) {
+		clone->arc = test_detail_arc_clone(detail->arc);
+	}
 
 	return clone;
 }
@@ -230,7 +233,11 @@ void test_detail_free(TestDetail *detail)
 	}
 	if (detail->xtensa) {
 		test_detail_xtensa_free(detail->xtensa);
+	}	
+	if (detail->arc) {
+		test_detail_arc_free(detail->arc);
 	}
+
 	cs_mem_free(detail);
 }
 
@@ -413,5 +420,9 @@ bool test_expected_detail(csh *handle, const cs_insn *insn,
 		return test_expected_xtensa(handle, &actual->xtensa,
 					    expected->xtensa);
 	}
+	if (expected->arc) {
+		return test_expected_arc(handle, &actual->arc,
+					  expected->arc);
+	}
 	return true;
 }
diff --git a/suite/cstest/src/test_detail_arc.c b/suite/cstest/src/test_detail_arc.c
new file mode 100644
index 0000000000..41047a7b64
--- /dev/null
+++ b/suite/cstest/src/test_detail_arc.c
@@ -0,0 +1,99 @@
+// Copyright © 2024 Sibirtsev Dmitry <sibirtsevdl@gmail.com>
+// SPDX-License-Identifier: BSD-3
+
+#include "test_compare.h"
+#include "test_detail_arc.h"
+#include <capstone/capstone.h>
+#include <stdio.h>
+#include <string.h>
+
+TestDetailARC *test_detail_arc_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailARC), 1);
+}
+
+void test_detail_arc_free(TestDetailARC *detail)
+{
+	if (!detail) {
+		return;
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		test_detail_arc_op_free(detail->operands[i]);
+	}
+	cs_mem_free(detail->operands);
+	cs_mem_free(detail);
+}
+
+TestDetailARC *test_detail_arc_clone(const TestDetailARC *detail)
+{
+	TestDetailARC *clone = test_detail_arc_new();
+
+	clone->operands_count = detail->operands_count;
+	if (detail->operands_count > 0) {
+		clone->operands = cs_mem_calloc(sizeof(TestDetailARCOp *),
+						detail->operands_count);
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		clone->operands[i] =
+			test_detail_arc_op_clone(detail->operands[i]);
+	}
+
+	return clone;
+}
+
+TestDetailARCOp *test_detail_arc_op_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailARCOp), 1);
+}
+
+TestDetailARCOp *test_detail_arc_op_clone(const TestDetailARCOp *op)
+{
+	TestDetailARCOp *clone = test_detail_arc_op_new();
+
+	clone->type = op->type ? strdup(op->type) : NULL;
+	clone->access = op->access ? strdup(op->access) : NULL;
+	clone->reg = op->reg ? strdup(op->reg) : NULL;
+	clone->imm = op->imm;
+
+	return clone;
+}
+
+void test_detail_arc_op_free(TestDetailARCOp *op)
+{
+	if (!op) {
+		return;
+	}
+	cs_mem_free(op->type);
+	cs_mem_free(op->access);
+	cs_mem_free(op->reg);
+	cs_mem_free(op);
+}
+
+bool test_expected_arc(csh *handle, const cs_arc *actual,
+			 const TestDetailARC *expected)
+{
+	assert(handle && actual && expected);
+
+	compare_uint8_ret(actual->op_count, expected->operands_count, false);
+	for (size_t i = 0; i < actual->op_count; ++i) {
+		const cs_arc_op *op = &actual->operands[i];
+		TestDetailARCOp *eop = expected->operands[i];
+		compare_enum_ret(op->type, eop->type, false);
+		compare_enum_ret(op->access, eop->access, false);
+		switch (op->type) {
+		default:
+			fprintf(stderr,
+				"arc op type %" PRId32 " not handled.\n",
+				op->type);
+			return false;
+		case ARC_OP_REG:
+			compare_reg_ret(*handle, op->reg, eop->reg, false);
+			break;
+		case ARC_OP_IMM:
+			compare_int64_ret(op->imm, eop->imm, false);
+			break;
+		}
+	}
+
+	return true;
+}
diff --git a/suite/test_corpus3.py b/suite/test_corpus3.py
index 3e634eb6e9..b09789bbbf 100755
--- a/suite/test_corpus3.py
+++ b/suite/test_corpus3.py
@@ -45,6 +45,7 @@ def test_file(fname):
         "CS_ARCH_TRICORE": CS_ARCH_TRICORE,
         "CS_ARCH_ALPHA": CS_ARCH_ALPHA,
         "CS_ARCH_HPPA": CS_ARCH_HPPA,
+        "CS_ARCH_ARC": CS_ARCH_ARC,
     }
 
     modes = {
@@ -134,6 +135,7 @@ def test_file(fname):
         ("CS_ARCH_ALPHA", "CS_MODE_BIG_ENDIAN"): 56,
         ("CS_ARCH_HPPA", "CS_MODE_HPPA_11+CS_MODE_BIG_ENDIAN"): 57,
         ("CS_ARCH_HPPA", "CS_MODE_HPPA_20+CS_MODE_BIG_ENDIAN"): 58,
+        ("CS_ARCH_ARC", "CS_MODE_LITTLE_ENDIAN"): 59,
     }
 
     # if not option in ('', 'None'):
diff --git a/tests/MC/ARC/alu_arc.s.yaml b/tests/MC/ARC/alu_arc.s.yaml
new file mode 100644
index 0000000000..7344edfd67
--- /dev/null
+++ b/tests/MC/ARC/alu_arc.s.yaml
@@ -0,0 +1,1390 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x00, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add %r0, %r0, %r0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x04, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add %r4, %r0, %r0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x04, 0x80 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.f %r4, %r0, %r0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xc2, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add %r2, %r0, %r3"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x02, 0x01 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add %r2, %r0, %r4"
+
+  -
+    input:
+      bytes: [ 0x00, 0x27, 0x02, 0x01 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add %r2, %r7, %r4"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x20, 0x61, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.eq %r0, %r0, 1"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x26, 0x2b, 0x04 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.lt %r6, %r6, 16"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x27, 0xec, 0x17 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.le %r15, %r15, 31"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x20, 0x69, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.gt %r0, %r0, 1"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x26, 0x2a, 0x04 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.ge %r6, %r6, 16"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x27, 0xe3, 0x17 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.p %r15, %r15, 31"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x20, 0x64, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.n %r0, %r0, 1"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x26, 0x27, 0x04 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.vs %r6, %r6, 16"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x27, 0xef, 0x17 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.pnz %r15, %r15, 31"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x20, 0x61, 0x80 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.eq.f %r0, %r0, 1"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x26, 0x2b, 0x84 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.lt.f %r6, %r6, 16"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x27, 0xec, 0x97 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.le.f %r15, %r15, 31"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x20, 0x69, 0x80 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.gt.f %r0, %r0, 1"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x26, 0x2a, 0x84 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.ge.f %r6, %r6, 16"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x27, 0xe3, 0x97 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.p.f %r15, %r15, 31"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x20, 0x64, 0x80 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.n.f %r0, %r0, 1"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x26, 0x27, 0x84 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.vs.f %r6, %r6, 16"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x27, 0xef, 0x97 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.pnz.f %r15, %r15, 31"
+
+  -
+    input:
+      bytes: [ 0x04, 0x27, 0x02, 0x01 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "and %r2, %r7, %r4"
+
+  -
+    input:
+      bytes: [ 0x04, 0x27, 0x02, 0x81 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.f %r2, %r7, %r4"
+
+  -
+    input:
+      bytes: [ 0x44, 0x27, 0x02, 0x01 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "and %r2, %r7, 4"
+
+  -
+    input:
+      bytes: [ 0x84, 0x21, 0xc3, 0x0f ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "and %r1, %r1, 255"
+
+  -
+    input:
+      bytes: [ 0x84, 0x21, 0xc3, 0x8f ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.f %r1, %r1, 255"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x20, 0x21, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.eq %r0, %r0, 0"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x26, 0x2b, 0x04 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.lt %r6, %r6, 16"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x27, 0xec, 0x17 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.le %r15, %r15, 31"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x20, 0x29, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.gt %r0, %r0, 0"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x26, 0x2a, 0x04 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ge %r6, %r6, 16"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x27, 0xe3, 0x17 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.p %r15, %r15, 31"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x20, 0x24, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.n %r0, %r0, 0"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x26, 0x27, 0x04 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.vs %r6, %r6, 16"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x27, 0xef, 0x17 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.pnz %r15, %r15, 31"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x20, 0x21, 0x80 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.eq.f %r0, %r0, 0"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x26, 0x2b, 0x84 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.lt.f %r6, %r6, 16"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x27, 0xec, 0x97 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.le.f %r15, %r15, 31"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x20, 0x29, 0x80 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.gt.f %r0, %r0, 0"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x26, 0x2a, 0x84 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ge.f %r6, %r6, 16"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x27, 0xe3, 0x97 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.p.f %r15, %r15, 31"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x20, 0x24, 0x80 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.n.f %r0, %r0, 0"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x26, 0x27, 0x84 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.vs.f %r6, %r6, 16"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x27, 0xef, 0x97 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.pnz.f %r15, %r15, 31"
+
+  -
+    input:
+      bytes: [ 0x40, 0x29, 0x81, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "asl %r1, %r1, 2"
+
+  -
+    input:
+      bytes: [ 0x00, 0x28, 0x00, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "asl %r0, %r0, %r0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x28, 0x00, 0x80 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "asl.f %r0, %r0, %r0"
+
+  -
+    input:
+      bytes: [ 0x42, 0x2a, 0xc1, 0x07 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr %r1, %r2, 31"
+
+  -
+    input:
+      bytes: [ 0x42, 0x2a, 0xc1, 0x87 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr.f %r1, %r2, 31"
+
+  -
+    input:
+      bytes: [ 0x42, 0x2b, 0xc1, 0x01 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr %r1, %r3, 7"
+
+  -
+    input:
+      bytes: [ 0x02, 0x29, 0x81, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr %r1, %r1, %r2"
+
+  -
+    input:
+      bytes: [ 0x08, 0x22, 0x40, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "max %r0, %r2, %r1"
+
+  -
+    input:
+      bytes: [ 0x48, 0x21, 0xc0, 0x03 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "max %r0, %r1, 15"
+
+  -
+    input:
+      bytes: [ 0x08, 0x22, 0x80, 0x0f, 0x00, 0x00, 0xa0, 0x0f ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "max %r0, %r2, 4000"
+
+  -
+    input:
+      bytes: [ 0x88, 0x22, 0xc3, 0x0f ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "max %r2, %r2, 255"
+
+  -
+    input:
+      bytes: [ 0x05, 0x20, 0x92, 0x2f, 0x00, 0x00, 0x00, 0xf0 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "or %r18, %r16, 61440"
+
+  -
+    input:
+      bytes: [ 0x05, 0x20, 0x92, 0xaf, 0x00, 0x00, 0x00, 0xf0 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.f %r18, %r16, 61440"
+
+  -
+    input:
+      bytes: [ 0x05, 0x21, 0x81, 0x03 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "or %r1, %r1, %r14"
+
+  -
+    input:
+      bytes: [ 0x05, 0x26, 0x41, 0x10 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "or %r1, %r14, %r1"
+
+  -
+    input:
+      bytes: [ 0x85, 0x21, 0x02, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "or %r1, %r1, 128"
+
+  -
+    input:
+      bytes: [ 0x02, 0x23, 0x9c, 0x3f, 0x00, 0x00, 0x5c, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub %sp, %fp, 92"
+
+  -
+    input:
+      bytes: [ 0x02, 0x27, 0x02, 0x01 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub %r2, %r7, %r4"
+
+  -
+    input:
+      bytes: [ 0x02, 0x27, 0x02, 0x81 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.f %r2, %r7, %r4"
+
+  -
+    input:
+      bytes: [ 0x02, 0x26, 0x00, 0x20 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub %r0, %r22, %r0"
+
+  -
+    input:
+      bytes: [ 0x17, 0x23, 0x43, 0x30 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub1 %r3, %fp, %r1"
+
+  -
+    input:
+      bytes: [ 0x58, 0x23, 0x43, 0x34 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub2 %r3, %fp, 17"
+
+  -
+    input:
+      bytes: [ 0x99, 0x23, 0xff, 0x3f ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub3 %fp, %fp, -1"
+
+  -
+    input:
+      bytes: [ 0x99, 0x23, 0xff, 0xbf ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub3.f %fp, %fp, -1"
+
+  -
+    input:
+      bytes: [ 0xce, 0x20, 0xe2, 0x07 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub.ne %r0, %r0, 31"
+
+  -
+    input:
+      bytes: [ 0xce, 0x20, 0x61, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub.eq %r0, %r0, 1"
+
+  -
+    input:
+      bytes: [ 0xce, 0x26, 0x2b, 0x04 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub.lt %r6, %r6, 16"
+
+  -
+    input:
+      bytes: [ 0xce, 0x27, 0xec, 0x17 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub.le %r15, %r15, 31"
+
+  -
+    input:
+      bytes: [ 0xce, 0x20, 0x69, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub.gt %r0, %r0, 1"
+
+  -
+    input:
+      bytes: [ 0xce, 0x26, 0x2a, 0x04 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub.ge %r6, %r6, 16"
+
+  -
+    input:
+      bytes: [ 0xce, 0x27, 0xe3, 0x17 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub.p %r15, %r15, 31"
+
+  -
+    input:
+      bytes: [ 0xce, 0x20, 0x64, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub.n %r0, %r0, 1"
+
+  -
+    input:
+      bytes: [ 0xce, 0x26, 0x27, 0x04 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub.vs %r6, %r6, 16"
+
+  -
+    input:
+      bytes: [ 0xce, 0x27, 0xef, 0x17 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub.pnz %r15, %r15, 31"
+
+  -
+    input:
+      bytes: [ 0xce, 0x20, 0xe2, 0x87 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub.ne.f %r0, %r0, 31"
+
+  -
+    input:
+      bytes: [ 0xce, 0x20, 0x61, 0x80 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub.eq.f %r0, %r0, 1"
+
+  -
+    input:
+      bytes: [ 0xce, 0x26, 0x2b, 0x84 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub.lt.f %r6, %r6, 16"
+
+  -
+    input:
+      bytes: [ 0xce, 0x27, 0xec, 0x97 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub.le.f %r15, %r15, 31"
+
+  -
+    input:
+      bytes: [ 0xce, 0x20, 0x69, 0x80 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub.gt.f %r0, %r0, 1"
+
+  -
+    input:
+      bytes: [ 0xce, 0x26, 0x2a, 0x84 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub.ge.f %r6, %r6, 16"
+
+  -
+    input:
+      bytes: [ 0xce, 0x27, 0xe3, 0x97 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub.p.f %r15, %r15, 31"
+
+  -
+    input:
+      bytes: [ 0xce, 0x20, 0x64, 0x80 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub.n.f %r0, %r0, 1"
+
+  -
+    input:
+      bytes: [ 0xce, 0x26, 0x27, 0x84 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub.vs.f %r6, %r6, 16"
+
+  -
+    input:
+      bytes: [ 0xce, 0x27, 0xef, 0x97 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub.pnz.f %r15, %r15, 31"
+
+  -
+    input:
+      bytes: [ 0x01, 0x20, 0x00, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc %r0, %r0, %r0"
+
+  -
+    input:
+      bytes: [ 0x01, 0x20, 0x04, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc %r4, %r0, %r0"
+
+  -
+    input:
+      bytes: [ 0x01, 0x20, 0x04, 0x80 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc.f %r4, %r0, %r0"
+
+  -
+    input:
+      bytes: [ 0x01, 0x20, 0xc2, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc %r2, %r0, %r3"
+
+  -
+    input:
+      bytes: [ 0x01, 0x20, 0x02, 0x01 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc %r2, %r0, %r4"
+
+  -
+    input:
+      bytes: [ 0x01, 0x27, 0x02, 0x01 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc %r2, %r7, %r4"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x20, 0x61, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc.eq %r0, %r0, 1"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x26, 0x2b, 0x04 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc.lt %r6, %r6, 16"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x27, 0xec, 0x17 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc.le %r15, %r15, 31"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x20, 0x69, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc.gt %r0, %r0, 1"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x26, 0x2a, 0x04 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc.ge %r6, %r6, 16"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x27, 0xe3, 0x17 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc.p %r15, %r15, 31"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x20, 0x64, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc.n %r0, %r0, 1"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x26, 0x27, 0x04 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc.vs %r6, %r6, 16"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x27, 0xef, 0x17 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc.pnz %r15, %r15, 31"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x20, 0x61, 0x80 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc.eq.f %r0, %r0, 1"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x26, 0x2b, 0x84 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc.lt.f %r6, %r6, 16"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x27, 0xec, 0x97 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc.le.f %r15, %r15, 31"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x20, 0x69, 0x80 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc.gt.f %r0, %r0, 1"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x26, 0x2a, 0x84 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc.ge.f %r6, %r6, 16"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x27, 0xe3, 0x97 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc.p.f %r15, %r15, 31"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x20, 0x64, 0x80 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc.n.f %r0, %r0, 1"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x26, 0x27, 0x84 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc.vs.f %r6, %r6, 16"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x27, 0xef, 0x97 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc.pnz.f %r15, %r15, 31"
+
+  -
+    input:
+      bytes: [ 0x03, 0x20, 0x00, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbc %r0, %r0, %r0"
+
+  -
+    input:
+      bytes: [ 0x03, 0x20, 0x04, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbc %r4, %r0, %r0"
+
+  -
+    input:
+      bytes: [ 0x03, 0x20, 0x04, 0x80 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbc.f %r4, %r0, %r0"
+
+  -
+    input:
+      bytes: [ 0x03, 0x20, 0xc2, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbc %r2, %r0, %r3"
+
+  -
+    input:
+      bytes: [ 0x03, 0x20, 0x02, 0x01 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbc %r2, %r0, %r4"
+
+  -
+    input:
+      bytes: [ 0x03, 0x27, 0x02, 0x01 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbc %r2, %r7, %r4"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x20, 0x61, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbc.eq %r0, %r0, 1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x26, 0x2b, 0x04 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbc.lt %r6, %r6, 16"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x27, 0xec, 0x17 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbc.le %r15, %r15, 31"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x20, 0x69, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbc.gt %r0, %r0, 1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x26, 0x2a, 0x04 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbc.ge %r6, %r6, 16"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x27, 0xe3, 0x17 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbc.p %r15, %r15, 31"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x20, 0x64, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbc.n %r0, %r0, 1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x26, 0x27, 0x04 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbc.vs %r6, %r6, 16"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x27, 0xef, 0x17 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbc.pnz %r15, %r15, 31"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x20, 0x61, 0x80 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbc.eq.f %r0, %r0, 1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x26, 0x2b, 0x84 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbc.lt.f %r6, %r6, 16"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x27, 0xec, 0x97 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbc.le.f %r15, %r15, 31"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x20, 0x69, 0x80 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbc.gt.f %r0, %r0, 1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x26, 0x2a, 0x84 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbc.ge.f %r6, %r6, 16"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x27, 0xe3, 0x97 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbc.p.f %r15, %r15, 31"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x20, 0x64, 0x80 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbc.n.f %r0, %r0, 1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x26, 0x27, 0x84 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbc.vs.f %r6, %r6, 16"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x27, 0xef, 0x97 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbc.pnz.f %r15, %r15, 31"
diff --git a/tests/MC/ARC/br_arc.s.yaml b/tests/MC/ARC/br_arc.s.yaml
new file mode 100644
index 0000000000..fa9f77b925
--- /dev/null
+++ b/tests/MC/ARC/br_arc.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x3d, 0x0a, 0x12, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "brlt %r2, 0, 60"
+
+  -
+    input:
+      bytes: [ 0x91, 0x0a, 0x04, 0x91 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "brlo %r10, %r4, -112"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x0a, 0x40, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "breq %r2, %r1, 44"
+
+  -
+    input:
+      bytes: [ 0xf1, 0x08, 0x11, 0x80 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "brne %r0, 0, -16"
+
+  -
+    input:
+      bytes: [ 0x27, 0x0a, 0x05, 0x02 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "brhs %r2, %r8, 38"
+
+  -
+    input:
+      bytes: [ 0x30, 0x01, 0x02, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bne 304"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x01, 0x01, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "beq 268"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x01, 0x0d, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bhi 416"
+
+  -
+    input:
+      bytes: [ 0xbd, 0x07, 0xcf, 0xff ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "b -68"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x9e, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "b 4096"
diff --git a/tests/MC/ARC/compact_arc.s.yaml b/tests/MC/ARC/compact_arc.s.yaml
new file mode 100644
index 0000000000..ad22897c2e
--- /dev/null
+++ b/tests/MC/ARC/compact_arc.s.yaml
@@ -0,0 +1,1260 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x31, 0x78 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs_s %r0, %r1"
+
+  -
+    input:
+      bytes: [ 0x58, 0x61 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add_s %r0, %r1, %r2"
+
+  -
+    input:
+      bytes: [ 0x63, 0x70 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add_s %r0, %r0, %fp"
+
+  -
+    input:
+      bytes: [ 0x67, 0x77 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add_s %fp, %fp, -1"
+
+  -
+    input:
+      bytes: [ 0x67, 0x76 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add_s %fp, %fp, 6"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x70, 0x22, 0x11, 0x44, 0x33 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add_s %r0, %r0, 287454020"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x74, 0x22, 0x11, 0x44, 0x33 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add_s 0, 287454020, 4"
+
+  -
+    input:
+      bytes: [ 0x90, 0xc0 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add_s %r0, %sp, 64"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe0 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add_s %r0, %r0, 64"
+
+  -
+    input:
+      bytes: [ 0x07, 0x69 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add_s %r0, %r1, 7"
+
+  -
+    input:
+      bytes: [ 0xb0, 0xc0 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add_s %sp, %sp, 64"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcf ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add_s %r0, %gp, -4"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x49 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add_s %r0, %r1, 4"
+
+  -
+    input:
+      bytes: [ 0x8c, 0x48 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add_s %r1, %r0, 4"
+
+  -
+    input:
+      bytes: [ 0x34, 0x78 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add1_s %r0, %r0, %r1"
+
+  -
+    input:
+      bytes: [ 0x35, 0x78 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add2_s %r0, %r0, %r1"
+
+  -
+    input:
+      bytes: [ 0x36, 0x78 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add3_s %r0, %r0, %r1"
+
+  -
+    input:
+      bytes: [ 0x24, 0x78 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "and_s %r0, %r0, %r1"
+
+  -
+    input:
+      bytes: [ 0x3b, 0x78 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "asl_s %r0, %r1"
+
+  -
+    input:
+      bytes: [ 0x34, 0x68 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "asl_s %r1, %r0, 4"
+
+  -
+    input:
+      bytes: [ 0x38, 0x78 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "asl_s %r0, %r0, %r1"
+
+  -
+    input:
+      bytes: [ 0x10, 0xb8 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "asl_s %r0, %r0, 16"
+
+  -
+    input:
+      bytes: [ 0x3c, 0x78 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr_s %r0, %r1"
+
+  -
+    input:
+      bytes: [ 0x3c, 0x68 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr_s %r1, %r0, 4"
+
+  -
+    input:
+      bytes: [ 0x3a, 0x78 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr_s %r0, %r0, %r1"
+
+  -
+    input:
+      bytes: [ 0x50, 0xb8 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr_s %r0, %r0, 16"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf0 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "b_s 256"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xf1 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "b_s -4"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xf3 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "beq_s -4"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xf5 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bne_s -4"
+
+  -
+    input:
+      bytes: [ 0x3e, 0xf6 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bgt_s -4"
+
+  -
+    input:
+      bytes: [ 0x7e, 0xf6 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bge_s -4"
+
+  -
+    input:
+      bytes: [ 0xbe, 0xf6 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "blt_s -4"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xf6 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ble_s -4"
+
+  -
+    input:
+      bytes: [ 0x3e, 0xf7 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bhi_s -4"
+
+  -
+    input:
+      bytes: [ 0x7e, 0xf7 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bhs_s -4"
+
+  -
+    input:
+      bytes: [ 0xbe, 0xf7 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "blo_s -4"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xf7 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bls_s -4"
+
+  -
+    input:
+      bytes: [ 0xb8, 0xb8 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bclr_s %r0, %r0, 24"
+
+  -
+    input:
+      bytes: [ 0x26, 0x78 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic_s %r0, %r0, %r1"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xff ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bl_s -256"
+
+  -
+    input:
+      bytes: [ 0xd8, 0xb8 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bmsk_s %r0, %r0, 24"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xe8 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "brne_s %r0, 0, -128"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe8 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "breq_s %r0, 0, -128"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "brk_s"
+
+  -
+    input:
+      bytes: [ 0x98, 0xb8 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bset_s %r0, %r0, 24"
+
+  -
+    input:
+      bytes: [ 0xf8, 0xb8 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btst_s %r0, 24"
+
+  -
+    input:
+      bytes: [ 0x93, 0x70 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp_s %r0, %sp"
+
+  -
+    input:
+      bytes: [ 0x97, 0x77 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp_s %sp, -1"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xe2 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp_s %r2, 64"
+
+  -
+    input:
+      bytes: [ 0x00, 0x5e ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ei_s 512"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc1 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "enter_s 16"
+
+  -
+    input:
+      bytes: [ 0x2f, 0x78 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "extb_s %r0, %r1"
+
+  -
+    input:
+      bytes: [ 0x30, 0x78 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "exth_s %r0, %r1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x78 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "j_s [%r0]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x7e ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "j_s [%blink]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x78 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "j_s.d [%r0]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x7f ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "j_s.d [%blink]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x7c ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq_s [%blink]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x7d ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne_s [%blink]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x78 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jl_s [%r0]"
+
+  -
+    input:
+      bytes: [ 0x60, 0x78 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jl_s.d [%r0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x5a ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jli_s 512"
+
+  -
+    input:
+      bytes: [ 0x40, 0x61 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld_s %r0, [%r1, %r2]"
+
+  -
+    input:
+      bytes: [ 0x10, 0xc0 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld_s %r0, [%sp, 64]"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd0 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld_s %r0, [%pcl, 512]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x80 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld_s %r1, [%r0, 64]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc9 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld_s %r0, [%gp, -1024]"
+
+  -
+    input:
+      bytes: [ 0x48, 0x61 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldb_s %r0, [%r1, %r2]"
+
+  -
+    input:
+      bytes: [ 0x30, 0xc0 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldb_s %r0, [%sp, 64]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x88 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldb_s %r1, [%r0, 16]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcb ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldb_s %r0, [%gp, -256]"
+
+  -
+    input:
+      bytes: [ 0x50, 0x61 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldh_s %r0, [%r1, %r2]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x90 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldh_s %r1, [%r0, 32]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcd ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldh_s %r0, [%gp, -512]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x98 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldh_s.x %r1, [%r0, 32]"
+
+  -
+    input:
+      bytes: [ 0x36, 0x40 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld_s %r0, [%r17, 8]"
+
+  -
+    input:
+      bytes: [ 0x36, 0x41 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld_s %r1, [%r17, 8]"
+
+  -
+    input:
+      bytes: [ 0x36, 0x42 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld_s %r2, [%r17, 8]"
+
+  -
+    input:
+      bytes: [ 0x36, 0x43 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld_s %r3, [%r17, 8]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x49 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld_s.as %r0, [%r1, %r2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x54 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld_s %r1, [%gp, -1024]"
+
+  -
+    input:
+      bytes: [ 0x88, 0x50 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldi_s %r0, [64]"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc1 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "leave_s 16"
+
+  -
+    input:
+      bytes: [ 0x3d, 0x78 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr_s %r0, %r1"
+
+  -
+    input:
+      bytes: [ 0x39, 0x78 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr_s %r0, %r0, %r1"
+
+  -
+    input:
+      bytes: [ 0x30, 0xb8 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr_s %r0, %r0, 16"
+
+  -
+    input:
+      bytes: [ 0x2e, 0x77 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov_s %r17, -1"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x75 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov_s 0, 5"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x70 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov_s.ne %r0, %r17"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x70, 0x00, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov_s.ne %r0, 1024"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd8 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov_s %r0, 128"
+
+  -
+    input:
+      bytes: [ 0x32, 0x40 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov_s %r16, %r17"
+
+  -
+    input:
+      bytes: [ 0xd3, 0x40, 0x00, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov_s %r16, 1024"
+
+  -
+    input:
+      bytes: [ 0x3a, 0x46 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov_s 0, %r17"
+
+  -
+    input:
+      bytes: [ 0xdb, 0x46, 0x00, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov_s 0, 1024"
+
+  -
+    input:
+      bytes: [ 0x2c, 0x78 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mpy_s %r0, %r0, %r1"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x78 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mpyuw_s %r0, %r0, %r1"
+
+  -
+    input:
+      bytes: [ 0x29, 0x78 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mpyw_s %r0, %r0, %r1"
+
+  -
+    input:
+      bytes: [ 0x33, 0x78 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg_s %r0, %r1"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x78 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "nop_s"
+
+  -
+    input:
+      bytes: [ 0x32, 0x78 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "not_s %r0, %r1"
+
+  -
+    input:
+      bytes: [ 0x25, 0x78 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "or_s %r0, %r0, %r1"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xc0 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "pop_s %r0"
+
+  -
+    input:
+      bytes: [ 0xd1, 0xc0 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "pop_s %blink"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xc0 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "push_s %r0"
+
+  -
+    input:
+      bytes: [ 0xf1, 0xc0 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "push_s %blink"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x78 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sexb_s %r0, %r1"
+
+  -
+    input:
+      bytes: [ 0x2e, 0x78 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sexh_s %r0, %r1"
+
+  -
+    input:
+      bytes: [ 0x50, 0xc0 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "st_s %r0, [%sp, 64]"
+
+  -
+    input:
+      bytes: [ 0x30, 0xa0 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "st_s %r1, [%r0, 64]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x54 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "st_s %r0, [%gp, -1024]"
+
+  -
+    input:
+      bytes: [ 0x70, 0xc0 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stb_s %r0, [%sp, 64]"
+
+  -
+    input:
+      bytes: [ 0x30, 0xa8 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stb_s %r1, [%r0, 16]"
+
+  -
+    input:
+      bytes: [ 0x30, 0xb0 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sth_s %r1, [%r0, 32]"
+
+  -
+    input:
+      bytes: [ 0x2c, 0x68 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub_s %r1, %r0, 4"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x78 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub_s.ne %r0, %r0, %r0"
+
+  -
+    input:
+      bytes: [ 0x22, 0x78 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub_s %r0, %r0, %r1"
+
+  -
+    input:
+      bytes: [ 0x70, 0xb8 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub_s %r0, %r0, 16"
+
+  -
+    input:
+      bytes: [ 0xb0, 0xc1 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub_s %sp, %sp, 64"
+
+  -
+    input:
+      bytes: [ 0x50, 0x49 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub_s %r0, %r1, %r2"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x7a ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "swi_s"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x7c ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "trap_s 32"
+
+  -
+    input:
+      bytes: [ 0x2b, 0x78 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tst_s %r0, %r1"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x79 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "unimp_s"
+
+  -
+    input:
+      bytes: [ 0x27, 0x78 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor_s %r0, %r0, %r1"
diff --git a/tests/MC/ARC/ldst_arc.s.yaml b/tests/MC/ARC/ldst_arc.s.yaml
new file mode 100644
index 0000000000..344cafc4ff
--- /dev/null
+++ b/tests/MC/ARC/ldst_arc.s.yaml
@@ -0,0 +1,360 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0x00, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld %r0, [%r0,0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0x00, 0x01 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldh %r0, [%r0,0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0x80, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldb %r0, [%r0,0]"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x10, 0x01, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld %r1, [%r0,12]"
+
+  -
+    input:
+      bytes: [ 0xf4, 0x13, 0x0e, 0xb0 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld %r14, [%fp,-12]"
+
+  -
+    input:
+      bytes: [ 0xf4, 0x10, 0x03, 0x80 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld %r3, [%r0,-12]"
+
+  -
+    input:
+      bytes: [ 0xf4, 0x10, 0x00, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld %r0, [%r0,244]"
+
+  -
+    input:
+      bytes: [ 0xf4, 0x10, 0x00, 0x80 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld %r0, [%r0,-12]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x11, 0x43, 0x01 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldh.x %r3, [%r1,0]"
+
+  -
+    input:
+      bytes: [ 0x02, 0x11, 0x42, 0x01 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldh.x %r2, [%r1,2]"
+
+  -
+    input:
+      bytes: [ 0x7c, 0x13, 0x42, 0xb1 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldh.x %r2, [%fp,-132]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x20, 0x80, 0x0f, 0x00, 0x00, 0x00, 0xfa ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld %r0, [%r0,64000]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x16, 0x06, 0x70, 0x00, 0x00, 0xb0, 0xf9 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld %r6, [63920]"
+
+  -
+    input:
+      bytes: [ 0x23, 0x1c, 0x82, 0x30 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stb %r2, [%sp,35]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x1e, 0xc0, 0x71, 0x00, 0x00, 0xb0, 0xf9 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "st %r7, [63920]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x10, 0x81, 0x04 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldb.ab %r1, [%r0,1]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x18, 0x92, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stb.ab %r2, [%r0,1]"
+
+  -
+    input:
+      bytes: [ 0x0C, 0x10, 0x03, 0x05 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldh.ab %r3, [%r0,12]"
+
+  -
+    input:
+      bytes: [ 0x12, 0x18, 0x14, 0x01 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sth.ab %r4, [%r0,18]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x12, 0x05, 0x04 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.ab %r5, [%r2,128]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x1A, 0x90, 0x01 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.ab %r6, [%r2,64]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x10, 0x87, 0x02 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldb.aw %r7, [%r0,1]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x18, 0x0A, 0x02 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stb.aw %r8, [%r0,1]"
+
+  -
+    input:
+      bytes: [ 0x0C, 0x10, 0x03, 0x03 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldh.aw %r3, [%r0,12]"
+
+  -
+    input:
+      bytes: [ 0x12, 0x18, 0xCC, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sth.aw %r3, [%r0,18]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x12, 0x06, 0x02 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.aw %r6, [%r2,128]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x1A, 0x88, 0x01 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.aw %r6, [%r2,64]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x10, 0xC0, 0x1A ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldb.x.di.aw %r0, [%r8,8]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x19, 0x32, 0x10 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stb.di.ab %r0, [%r9,64]"
+
+  -
+    input:
+      bytes: [ 0x6a, 0x20, 0x40, 0x08 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lr %r0, [33]"
+
+  -
+    input:
+      bytes: [ 0x6a, 0x27, 0x40, 0x08 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lr %r7, [33]"
+
+  -
+    input:
+      bytes: [ 0x6a, 0x27, 0x40, 0x18 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lr %r15, [33]"
+
+  -
+    input:
+      bytes: [ 0x6a, 0x26, 0x40, 0x28 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lr %r22, [33]"
+
+  -
+    input:
+      bytes: [ 0xaa, 0x20, 0x60, 0x08 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lr %r0, [-33]"
+
+  -
+    input:
+      bytes: [ 0xaa, 0x20, 0x41, 0x08 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lr %r0, [97]"
+
+  -
+    input:
+      bytes: [ 0xaa, 0x20, 0x61, 0x08 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lr %r0, [-97]"
diff --git a/tests/MC/ARC/misc_arc.s.yaml b/tests/MC/ARC/misc_arc.s.yaml
new file mode 100644
index 0000000000..e51f310b03
--- /dev/null
+++ b/tests/MC/ARC/misc_arc.s.yaml
@@ -0,0 +1,490 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x8a, 0x20, 0xff, 0x0f ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov %r0, -1"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x24, 0x80, 0x0f, 0x00, 0x00, 0xff, 0x7f ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov %r4, 32767"
+
+  -
+    input:
+      bytes: [ 0xca, 0x22, 0x81, 0x01 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.eq %r2, %r6"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x25, 0x80, 0x10 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov %r13, %r2"
+
+  -
+    input:
+      bytes: [ 0x4a, 0x21, 0x00, 0x05 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov %r1, 20"
+
+  -
+    input:
+      bytes: [ 0xca, 0x20, 0x21, 0x08 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.eq %r0, 32"
+
+  -
+    input:
+      bytes: [ 0xca, 0x20, 0x22, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.ne %r0, 0"
+
+  -
+    input:
+      bytes: [ 0xca, 0x20, 0x21, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.eq %r0, 0"
+
+  -
+    input:
+      bytes: [ 0xca, 0x26, 0x2b, 0x04 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.lt %r6, 16"
+
+  -
+    input:
+      bytes: [ 0xca, 0x27, 0xec, 0x17 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.le %r15, 31"
+
+  -
+    input:
+      bytes: [ 0xca, 0x20, 0x29, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.gt %r0, 0"
+
+  -
+    input:
+      bytes: [ 0xca, 0x26, 0x2a, 0x04 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.ge %r6, 16"
+
+  -
+    input:
+      bytes: [ 0xca, 0x27, 0xe3, 0x17 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.p %r15, 31"
+
+  -
+    input:
+      bytes: [ 0xca, 0x20, 0x24, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.n %r0, 0"
+
+  -
+    input:
+      bytes: [ 0xca, 0x26, 0x27, 0x04 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.vs %r6, 16"
+
+  -
+    input:
+      bytes: [ 0xca, 0x27, 0xef, 0x17 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.pnz %r15, 31"
+
+  -
+    input:
+      bytes: [ 0x4a, 0x20, 0x00, 0x80 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.f %r0, 0"
+
+  -
+    input:
+      bytes: [ 0x4a, 0x26, 0x00, 0x84 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.f %r6, 16"
+
+  -
+    input:
+      bytes: [ 0x4a, 0x27, 0xc0, 0x97 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.f %r15, 31"
+
+  -
+    input:
+      bytes: [ 0xca, 0x20, 0x21, 0x80 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.eq.f %r0, 0"
+
+  -
+    input:
+      bytes: [ 0xca, 0x26, 0x2b, 0x84 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.lt.f %r6, 16"
+
+  -
+    input:
+      bytes: [ 0xca, 0x27, 0xec, 0x97 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.le.f %r15, 31"
+
+  -
+    input:
+      bytes: [ 0xca, 0x20, 0x29, 0x80 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.gt.f %r0, 0"
+
+  -
+    input:
+      bytes: [ 0xca, 0x26, 0x2a, 0x84 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.ge.f %r6, 16"
+
+  -
+    input:
+      bytes: [ 0xca, 0x27, 0xe3, 0x97 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.p.f %r15, 31"
+
+  -
+    input:
+      bytes: [ 0xca, 0x20, 0x24, 0x80 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.n.f %r0, 0"
+
+  -
+    input:
+      bytes: [ 0xca, 0x26, 0x27, 0x84 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.vs.f %r6, 16"
+
+  -
+    input:
+      bytes: [ 0xca, 0x27, 0xef, 0x97 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.pnz.f %r15, 31"
+
+  -
+    input:
+      bytes: [ 0xfc, 0x1c, 0xc8, 0xb6 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.aw %fp, [%sp,-4]"
+
+  -
+    input:
+      bytes: [ 0x04, 0x14, 0x1b, 0x34 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.ab %fp, [%sp,4]"
+
+  -
+    input:
+      bytes: [ 0x16, 0x08, 0xcf, 0xff ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bl -2028"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x25, 0x80, 0x92 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp %r13, %r10"
+
+  -
+    input:
+      bytes: [ 0x4c, 0x26, 0x00, 0x90 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp %r14, 0"
+
+  -
+    input:
+      bytes: [ 0x4c, 0x27, 0x40, 0xa0 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp %r23, 1"
+
+  -
+    input:
+      bytes: [ 0x22, 0x20, 0x40, 0x05 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jl [%r21]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x20, 0x80, 0x0f, 0x00, 0x00, 0x39, 0x30 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jl 12345"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0xc0, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "j [%r3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x80, 0x0f, 0x00, 0x00, 0x39, 0x30 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "j 12345"
+
+  -
+    input:
+      bytes: [ 0x38, 0x23, 0x43, 0x30 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "seteq %r3, %fp, %r1"
+
+  -
+    input:
+      bytes: [ 0x78, 0x23, 0x43, 0x34 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "seteq %r3, %fp, 17"
+
+  -
+    input:
+      bytes: [ 0xb8, 0x23, 0xff, 0x3f,  ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "seteq %fp, %fp, -1"
+
+  -
+    input:
+      bytes: [ 0x2f, 0x28, 0x13, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fls %r0, %r0"
+
+  -
+    input:
+      bytes: [ 0x2f, 0x28, 0x13, 0x80 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fls.f %r0, %r0"
+
+  -
+    input:
+      bytes: [ 0x2f, 0x28, 0x12, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ffs %r0, %r0"
+
+  -
+    input:
+      bytes: [ 0x2f, 0x28, 0x12, 0x80 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ffs.f %r0, %r0"
+
+  -
+    input:
+      bytes: [ 0x2f, 0x2f, 0xd2, 0x13 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ffs %r15, %r15"
+
+  -
+    input:
+      bytes: [ 0x2f, 0x2f, 0xd2, 0x93 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ffs.f %r15, %r15"
+
+  -
+    input:
+      bytes: [ 0x2f, 0x2e, 0xc1, 0x27 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "norm %r22, %blink"
+
+  -
+    input:
+      bytes: [ 0x2f, 0x2f, 0x88, 0x04 ]
+      arch: "CS_ARCH_ARC"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "normh %r7, %r18"
diff --git a/tests/details/arc.yaml b/tests/details/arc.yaml
new file mode 100644
index 0000000000..adc8475b02
--- /dev/null
+++ b/tests/details/arc.yaml
@@ -0,0 +1,204 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x04, 0x11, 0x00, 0x00, 0x04, 0x11, 0x00, 0x02, 0x04, 0x11, 0x00, 0x04, 0x04, 0x11, 0x00, 0x01, 0x04, 0x11, 0x00, 0x03, 0x04, 0x11, 0x00, 0x05, 0x04, 0x11, 0x80, 0x00, 0x04, 0x11, 0x80, 0x02, 0x04, 0x11, 0x80, 0x04, 0x2d, 0x0a, 0x40, 0x00, 0xca, 0x22, 0x81, 0x01 ]
+      arch: "arc"
+      options: [ CS_OPT_DETAIL, CS_MODE_LITTLE_ENDIAN ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ld %r0, [%r1,4]"
+        details:
+          arc:
+            operands:
+              -
+                type: ARC_OP_REG
+                reg: "%r0"
+                access: CS_AC_WRITE
+              -
+                type: ARC_OP_REG
+                reg: "%r1"
+                access: CS_AC_READ
+              -
+                type: ARC_OP_IMM
+                imm: 4
+                access: CS_AC_READ
+      -
+        asm_text: "ld.aw %r0, [%r1,4]"
+        details:
+          arc:
+            operands:
+              -
+                type: ARC_OP_REG
+                reg: "%r0"
+                access: CS_AC_WRITE
+              -
+                type: ARC_OP_REG
+                reg: "%r1"
+                access: CS_AC_READ
+              -
+                type: ARC_OP_IMM
+                imm: 4
+                access: CS_AC_READ
+      -
+        asm_text: "ld.ab %r0, [%r1,4]"
+        details:
+          arc:
+            operands:
+              -
+                type: ARC_OP_REG
+                reg: "%r0"
+                access: CS_AC_WRITE
+              -
+                type: ARC_OP_REG
+                reg: "%r1"
+                access: CS_AC_READ
+              -
+                type: ARC_OP_IMM
+                imm: 4
+                access: CS_AC_READ
+      -
+        asm_text: "ldh %r0, [%r1,4]"
+        details:
+          arc:
+            operands:
+              -
+                type: ARC_OP_REG
+                reg: "%r0"
+                access: CS_AC_WRITE
+              -
+                type: ARC_OP_REG
+                reg: "%r1"
+                access: CS_AC_READ
+              -
+                type: ARC_OP_IMM
+                imm: 4
+                access: CS_AC_READ
+      -
+        asm_text: "ldh.aw %r0, [%r1,4]" 
+        details:
+          arc:
+            operands:
+              -
+                type: ARC_OP_REG
+                reg: "%r0"
+                access: CS_AC_WRITE
+              -
+                type: ARC_OP_REG
+                reg: "%r1"
+                access: CS_AC_READ
+              -
+                type: ARC_OP_IMM
+                imm: 4
+                access: CS_AC_READ
+      -
+        asm_text: "ldh.ab %r0, [%r1,4]"
+        details:
+          arc:
+            operands:
+              -
+                type: ARC_OP_REG
+                reg: "%r0"
+                access: CS_AC_WRITE
+              -
+                type: ARC_OP_REG
+                reg: "%r1"
+                access: CS_AC_READ
+              -
+                type: ARC_OP_IMM
+                imm: 4
+                access: CS_AC_READ
+      -
+        asm_text: "ldb %r0, [%r1,4]"
+        details:
+          arc:
+            operands:
+              -
+                type: ARC_OP_REG
+                reg: "%r0"
+                access: CS_AC_WRITE
+              -
+                type: ARC_OP_REG
+                reg: "%r1"
+                access: CS_AC_READ
+              -
+                type: ARC_OP_IMM
+                imm: 4
+                access: CS_AC_READ
+      -
+        asm_text: "ldb.aw %r0, [%r1,4]"
+        details:
+          arc:
+            operands:
+              -
+                type: ARC_OP_REG
+                reg: "%r0"
+                access: CS_AC_WRITE
+              -
+                type: ARC_OP_REG
+                reg: "%r1"
+                access: CS_AC_READ
+              -
+                type: ARC_OP_IMM
+                imm: 4
+                access: CS_AC_READ
+      -
+        asm_text: "ldb.ab %r0, [%r1,4]"
+        details:
+          arc:
+            operands:
+              -
+                type: ARC_OP_REG
+                reg: "%r0"
+                access: CS_AC_WRITE
+              -
+                type: ARC_OP_REG
+                reg: "%r1"
+                access: CS_AC_READ
+              -
+                type: ARC_OP_IMM
+                imm: 4
+                access: CS_AC_READ
+      -
+        asm_text: "breq %r2, %r1, 80"
+        details:
+          arc:
+            operands:
+              -
+                type: ARC_OP_IMM
+                imm: 0
+                access: CS_AC_READ
+              -
+                type: ARC_OP_REG
+                reg: "%r2"
+                access: CS_AC_READ
+              -
+                type: ARC_OP_REG
+                reg: "%r1"
+                access: CS_AC_READ
+              -
+                type: ARC_OP_IMM
+                imm: 0x50
+                access: CS_AC_READ
+          regs_read: [ "%r2", "%r1" ]
+          groups: [ jump, branch_relative ]
+      -
+        asm_text: "mov.eq %r2, %r6"
+        details:
+          arc:
+            operands:
+              -
+                type: ARC_OP_IMM
+                imm: 1
+                access: CS_AC_READ
+              -
+                type: ARC_OP_REG
+                reg: "%r2"
+                access: CS_AC_WRITE
+              -
+                type: ARC_OP_REG
+                reg: "%r6"
+                access: CS_AC_READ
+          regs_read: [ "status32", "%r6" ]
+          regs_write: [ "%r2" ]     
\ No newline at end of file
diff --git a/tests/integration/test_iter.c b/tests/integration/test_iter.c
index ec611fe523..f97842182e 100644
--- a/tests/integration/test_iter.c
+++ b/tests/integration/test_iter.c
@@ -91,6 +91,10 @@ static void test()
 #define HPPA_11_CODE     "\xc3\x40\x41\x24\xc3\x60\x41\x24\xe3\x40\x41\x24\xe3\x60\x41\x24\xe3\x68\x41\x24\xc3\x40\x41\x2c\xc3\x60\x41\x2c\xe3\x40\x41\x2c\xe3\x60\x41\x2c\xe3\x68\x41\x2c\xc1\x42\x62\x24\xc1\x62\x62\x24\xe1\x42\x62\x24\xe1\x46\x62\x24\xe1\x62\x62\x24\xe1\x6a\x62\x24\xc1\x42\x62\x2c\xc1\x62\x62\x2c\xe1\x42\x62\x2c\xe1\x46\x62\x2c\xe1\x62\x62\x2c\xe1\x6a\x62\x2c\xc2\x50\x3e\x24\xe2\x50\x3e\x24\xe2\x70\x3e\x24\xe2\x78\x3e\x24\xc2\x50\x3e\x2c\xe2\x50\x3e\x2c\xe2\x70\x3e\x2c\xe2\x78\x3e\x2c\xc1\x52\x5e\x24\xe1\x52\x5e\x24\xe1\x56\x5e\x24\xe1\x72\x5e\x24\xe1\x7a\x5e\x24\xc1\x52\x5e\x2c\xe1\x52\x5e\x2c\xe1\x56\x5e\x2c\xe1\x72\x5e\x2c\xe1\x7a\x5e\x2c"
 #endif
 
+#ifdef CAPSTONE_HAS_ARC
+#define ARC_CODE "\x04\x11\x00\x00\x04\x11\x00\x02\x04\x11\x00\x04\x04\x11\x00\x01\x04\x11\x00\x03\x04\x11\x00\x05\x04\x11\x80\x00\x04\x11\x80\x02\x04\x11\x80\x04"
+#endif
+
 struct platform platforms[] = {
 #ifdef CAPSTONE_HAS_X86
 		{
@@ -319,6 +323,15 @@ struct platform platforms[] = {
 		sizeof(HPPA_11_CODE) - 1,
 		"HPPA 1.1 (Little-endian)"
 	    },
+#endif
+#ifdef CAPSTONE_HAS_ARC
+	    {
+		CS_ARCH_ARC,
+		CS_MODE_LITTLE_ENDIAN,
+		(unsigned char*)ARC_CODE,
+		sizeof(ARC_CODE) - 1,
+		"ARC"
+	    },
 #endif
 	};