From 05a368d19cd4405babb462925a0c0f70c24e8126 Mon Sep 17 00:00:00 2001 From: Rachit Nigam Date: Fri, 16 Feb 2024 23:14:49 +0530 Subject: [PATCH] Add names to fields in `ir::Canonical` (#1920) --- calyx-backend/src/verilog.rs | 2 +- calyx-ir/src/from_ast.rs | 14 ++++++-------- calyx-ir/src/structure.rs | 18 +++++++++++++++--- calyx-opt/src/analysis/dataflow_order.rs | 4 ++-- calyx-opt/src/passes/comb_prop.rs | 2 +- calyx-opt/src/passes/compile_invoke.rs | 4 ++-- calyx-opt/src/passes/compile_static.rs | 2 +- calyx-opt/src/passes/component_iniliner.rs | 10 +++++++--- calyx-opt/src/passes/dump_ports.rs | 2 +- calyx-opt/src/passes/simplify_with_control.rs | 5 ++--- interp/src/structures/environment.rs | 2 +- 11 files changed, 39 insertions(+), 26 deletions(-) diff --git a/calyx-backend/src/verilog.rs b/calyx-backend/src/verilog.rs index 9da5f2ebf9..742a8b9e28 100644 --- a/calyx-backend/src/verilog.rs +++ b/calyx-backend/src/verilog.rs @@ -478,7 +478,7 @@ fn emit_guard_disjoint_check( let mut check = v::SequentialIfElse::new(not_onehot0); // Generated error message - let ir::Canonical(cell, port) = dst.borrow().canonical(); + let ir::Canonical { cell, port } = dst.borrow().canonical(); let msg = format!("Multiple assignment to port `{}.{}'.", cell, port); let err = v::Sequential::new_seqexpr(v::Expr::new_call( "$fatal", diff --git a/calyx-ir/src/from_ast.rs b/calyx-ir/src/from_ast.rs index 9930d0d1d0..446f41706b 100644 --- a/calyx-ir/src/from_ast.rs +++ b/calyx-ir/src/from_ast.rs @@ -1,6 +1,6 @@ use super::{ - Assignment, Attributes, BackendConf, Builder, Canonical, Cell, CellType, - Component, Context, Control, Direction, GetAttributes, Guard, Id, Invoke, + Assignment, Attributes, BackendConf, Builder, Cell, CellType, Component, + Context, Control, Direction, GetAttributes, Guard, Id, Invoke, LibrarySignatures, Port, PortDef, StaticControl, StaticInvoke, RESERVED_NAMES, RRC, }; @@ -490,17 +490,15 @@ fn ensure_direction(pr: RRC, dir: Direction) -> CalyxResult> { let port_dir = pr.borrow().direction.clone(); match (dir, port_dir) { (Direction::Input, Direction::Output) => { - let Canonical(c, p) = pr.borrow().canonical(); + let name = pr.borrow().canonical(); Err(Error::malformed_structure(format!( - "Port `{}.{}` occurs in write position but is an output port", - c, p + "Port `{name}` occurs in write position but is an output port", ))) } (Direction::Output, Direction::Input) => { - let Canonical(c, p) = pr.borrow().canonical(); + let name = pr.borrow().canonical(); Err(Error::malformed_structure(format!( - "Port `{}.{}` occurs in write position but is an output port", - c, p + "Port `{name}` occurs in write position but is an output port", ))) } _ => Ok(pr), diff --git a/calyx-ir/src/structure.rs b/calyx-ir/src/structure.rs index 8d40bd8f8d..3a6f3444ac 100644 --- a/calyx-ir/src/structure.rs +++ b/calyx-ir/src/structure.rs @@ -39,11 +39,20 @@ pub struct Port { /// Canonical name of a Port #[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord, Hash)] -pub struct Canonical(pub Id, pub Id); +pub struct Canonical { + pub cell: Id, + pub port: Id, +} + +impl Canonical { + pub const fn new(cell: Id, port: Id) -> Self { + Self { cell, port } + } +} impl std::fmt::Display for Canonical { fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { - write!(f, "{}.{}", self.0, self.1) + write!(f, "{}.{}", self.cell, self.port) } } @@ -96,7 +105,10 @@ impl Port { /// Get the canonical representation for this Port. pub fn canonical(&self) -> Canonical { - Canonical(self.get_parent_name(), self.name) + Canonical { + cell: self.get_parent_name(), + port: self.name, + } } /// Returns the value of an attribute if present diff --git a/calyx-opt/src/analysis/dataflow_order.rs b/calyx-opt/src/analysis/dataflow_order.rs index 1b6e0e415e..1e0f604ac7 100644 --- a/calyx-opt/src/analysis/dataflow_order.rs +++ b/calyx-opt/src/analysis/dataflow_order.rs @@ -140,7 +140,7 @@ impl DataflowOrder { // XXX(rachit): This probably adds a bunch of duplicate edges and in the // worst case makes this pass much slower than it needs to be. for (r_idx, (comp, canonical_port)) in reads { - let ir::Canonical(inst, port) = canonical_port; + let ir::Canonical { cell: inst, port } = canonical_port; let dep_ports = self .write_map .get(&comp) @@ -159,7 +159,7 @@ impl DataflowOrder { dep_ports .iter() .cloned() - .flat_map(|port| writes.get(&ir::Canonical(inst, port))) + .flat_map(|port| writes.get(&ir::Canonical::new(inst, port))) .flatten() .try_for_each(|w_idx| { if *w_idx == r_idx { diff --git a/calyx-opt/src/passes/comb_prop.rs b/calyx-opt/src/passes/comb_prop.rs index 566e2f6d45..739485d7f4 100644 --- a/calyx-opt/src/passes/comb_prop.rs +++ b/calyx-opt/src/passes/comb_prop.rs @@ -131,7 +131,7 @@ impl From for ir::rewriter::PortRewriteMap { impl std::fmt::Debug for WireRewriter { fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { - for (ir::Canonical(cell, port), port_ref) in &self.rewrites { + for (ir::Canonical { cell, port }, port_ref) in &self.rewrites { writeln!( f, "{}.{} -> {}", diff --git a/calyx-opt/src/passes/compile_invoke.rs b/calyx-opt/src/passes/compile_invoke.rs index 3bc81493db..c40d60e219 100644 --- a/calyx-opt/src/passes/compile_invoke.rs +++ b/calyx-opt/src/passes/compile_invoke.rs @@ -158,12 +158,12 @@ impl CompileInvoke { continue; } - let canon = ir::Canonical(ref_cell_name, port.name); + let canon = ir::Canonical::new(ref_cell_name, port.name); let Some(comp_port) = comp_ports.get(&canon) else { unreachable!("port `{}` not found in the signature of {}. Known ports are: {}", canon, inv_comp, - comp_ports.keys().map(|c| c.1.as_ref()).collect_vec().join(", ") + comp_ports.keys().map(|c| c.port.as_ref()).collect_vec().join(", ") ) }; // Get the port on the new cell with the same name as ref_port diff --git a/calyx-opt/src/passes/compile_static.rs b/calyx-opt/src/passes/compile_static.rs index 3f91527e3f..beaf6acca2 100644 --- a/calyx-opt/src/passes/compile_static.rs +++ b/calyx-opt/src/passes/compile_static.rs @@ -731,7 +731,7 @@ impl Visitor for CompileStatic { // technically could do this w/ early_reset_map but is easier w/ // group_rewrite, which is explicitly of type `PortRewriterMap` self.group_rewrite.insert( - ir::Canonical(sgroup_name, ir::Id::from("go")), + ir::Canonical::new(sgroup_name, ir::Id::from("go")), g.borrow().find("go").unwrap_or_else(|| { unreachable!("group {} has no go port", g.borrow().name()) }), diff --git a/calyx-opt/src/passes/component_iniliner.rs b/calyx-opt/src/passes/component_iniliner.rs index 8699513d35..43fc3e7f9e 100644 --- a/calyx-opt/src/passes/component_iniliner.rs +++ b/calyx-opt/src/passes/component_iniliner.rs @@ -341,14 +341,17 @@ impl ComponentInliner { // Return as an iterator because it's immediately merged into the global rewrite map. let rev_interface_map = rewrite.port_map.into_iter().map(move |(cp, pr)| { - let ir::Canonical(_, p) = cp; + let ir::Canonical { port: p, .. } = cp; let port = pr.borrow(); let np = match port.name.id.as_str() { "in" => "out", "out" => "in", _ => unreachable!(), }; - (ir::Canonical(name, p), port.cell_parent().borrow().get(np)) + ( + ir::Canonical::new(name, p), + port.cell_parent().borrow().get(np), + ) }); (con, rev_interface_map) @@ -528,7 +531,8 @@ impl Visitor for ComponentInliner { }) .map(|(name, param)| { let port = Rc::clone( - &interface_rewrites[&ir::Canonical(instance, name)], + &interface_rewrites + [&ir::Canonical::new(instance, name)], ); // The parameter can refer to port on a cell that has been // inlined. diff --git a/calyx-opt/src/passes/dump_ports.rs b/calyx-opt/src/passes/dump_ports.rs index ce3eeb3408..ae2b4b301d 100644 --- a/calyx-opt/src/passes/dump_ports.rs +++ b/calyx-opt/src/passes/dump_ports.rs @@ -15,7 +15,7 @@ pub struct DumpResults { /// Formats name of a port given the id of the cell and the port pub(super) fn format_port_name(canon: &ir::Canonical) -> ir::Id { - format!("{}_{}", canon.0, canon.1).into() + format!("{}_{}", canon.cell, canon.port).into() } /// Remove all the cells matching the given criterion (f evaluates to true) from diff --git a/calyx-opt/src/passes/simplify_with_control.rs b/calyx-opt/src/passes/simplify_with_control.rs index eddfa273e5..55a37aef86 100644 --- a/calyx-opt/src/passes/simplify_with_control.rs +++ b/calyx-opt/src/passes/simplify_with_control.rs @@ -224,10 +224,9 @@ impl Visitor for SimplifyWithControl { let (port_ref, cond_ref) = self.port_rewrite.get(&key).unwrap_or_else(|| { panic!( - "{}: Port `{}.{}` in group `{}` doesn't have a rewrite", + "{}: Port `{}` in group `{}` doesn't have a rewrite", Self::name(), - key.1 .0, - key.1 .1, + key.1, key.0 ) }); diff --git a/interp/src/structures/environment.rs b/interp/src/structures/environment.rs index 85d6ee2174..51e51f2c24 100644 --- a/interp/src/structures/environment.rs +++ b/interp/src/structures/environment.rs @@ -690,7 +690,7 @@ impl InterpreterState { if val.len() != 1 { let can = p.borrow().canonical(); return Err(InterpreterError::InvalidBoolCast( - (can.0, can.1), + (can.cell, can.port), p.borrow().width, ) .into());