Initial support for vex encoding for the new assembler.

Author: jlb6740

cranelift/assembler-x64/meta/src/dsl.rs

@@ -8,13 +8,14 @@ mod encoding;
 mod features;
 pub mod format;
 
+pub use encoding::{rex, vex};
 pub use encoding::{
-    Encoding, Group1Prefix, Group2Prefix, Group3Prefix, Group4Prefix, Opcodes, Prefixes, Rex,
+    rex, vex, Encoding, Group1Prefix, Group2Prefix, Group3Prefix, Group4Prefix, Opcodes, Prefixes,
+    Rex, Vex, VexLength, VexMMMMM, VexPP,
 };
-pub use encoding::{rex, vex};
-pub use features::{ALL_FEATURES, Feature, Features};
-pub use format::{Extension, Format, Location, Mutability, Operand, OperandKind, RegClass};
+pub use features::{Feature, Features, ALL_FEATURES};
 pub use format::{align, fmt, implicit, r, rw, sxl, sxq, sxw, w};
+pub use format::{Extension, Format, Location, Mutability, Operand, OperandKind, RegClass};
 
 /// Abbreviated constructor for an x64 instruction.
 pub fn inst(

cranelift/assembler-x64/meta/src/dsl/encoding.rs

@@ -32,8 +32,18 @@ pub fn rex(opcode: impl Into<Opcodes>) -> Rex {
 
 /// An abbreviated constructor for VEX-encoded instructions.
 #[must_use]
-pub fn vex() -> Vex {
-    Vex {}
+pub fn vex(opcode: impl Into<Opcodes>) -> Vex {
+    Vex {
+        opcodes: opcode.into(),
+        w: false,
+        wig: false,
+        length: VexLength::default(),
+        mmmmm: VexMMMMM::None,
+        pp: VexPP::None,
+        reg: 0x00,
+        vvvv: None,
+        imm: None,
+    }
 }
 
 /// Enumerate the ways x64 encodes instructions.
@@ -48,7 +58,7 @@ impl Encoding {
     pub fn validate(&self, operands: &[Operand]) {
         match self {
             Encoding::Rex(rex) => rex.validate(operands),
-            Encoding::Vex(vex) => vex.validate(),
+            Encoding::Vex(vex) => vex.validate(operands),
         }
     }
 }
@@ -57,7 +67,7 @@ impl fmt::Display for Encoding {
     fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
         match self {
             Encoding::Rex(rex) => write!(f, "{rex}"),
-            Encoding::Vex(_vex) => todo!(),
+            Encoding::Vex(vex) => write!(f, "{vex}"),
         }
     }
 }
@@ -408,6 +418,23 @@ impl Prefixes {
             && self.group3.is_none()
             && self.group4.is_none()
     }
+
+    pub fn bits(&self) -> u8 {
+        let mut bits = 0;
+        if self.group1.is_some() {
+            bits |= 0b0001;
+        }
+        if self.group2.is_some() {
+            bits |= 0b0010;
+        }
+        if self.group3.is_some() {
+            bits |= 0b0100;
+        }
+        if self.group4.is_some() {
+            bits |= 0b1000;
+        }
+        bits
+    }
 }
 
 pub enum Group1Prefix {
@@ -584,7 +611,7 @@ pub enum Imm {
 }
 
 impl Imm {
-    fn bits(&self) -> u8 {
+    fn bits(&self) -> u16 {
         match self {
             Imm::None => 0,
             Imm::ib => 8,
@@ -607,10 +634,126 @@ impl fmt::Display for Imm {
     }
 }
 
-pub struct Vex {}
+pub struct Vex {
+    pub opcodes: Opcodes,
+    pub w: bool,
+    pub wig: bool,
+    pub length: VexLength,
+    pub mmmmm: VexMMMMM,
+    pub pp: VexPP,
+    pub reg: u8,
+    pub vvvv: Option<Register>,
+    pub imm: Option<u8>,
+}
+
+#[derive(PartialEq)]
+pub enum VexPP {
+    None,
+    /// Operand size override -- here, denoting "16-bit operation".
+    _66,
+    /// REPNE, but no specific meaning here -- is just an opcode extension.
+    _F2,
+    /// REP/REPE, but no specific meaning here -- is just an opcode extension.
+    _F3,
+}
+
+impl fmt::Display for VexPP {
+    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+        match self {
+            VexPP::None => write!(f, "None"),
+            VexPP::_66 => write!(f, "_66"),
+            VexPP::_F3 => write!(f, "_F3"),
+            VexPP::_F2 => write!(f, "_F2"),
+        }
+    }
+}
+
+#[derive(PartialEq)]
+pub enum VexMMMMM {
+    None,
+    _OF,
+    /// Operand size override -- here, denoting "16-bit operation".
+    _OF3A,
+    /// The lock prefix.
+    _OF38,
+}
+
+impl fmt::Display for VexMMMMM {
+    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+        match self {
+            VexMMMMM::None => write!(f, "None"),
+            VexMMMMM::_OF => write!(f, "_0F"),
+            VexMMMMM::_OF3A => write!(f, "_OF3A"),
+            VexMMMMM::_OF38 => write!(f, "_OF38"),
+        }
+    }
+}
+
+pub enum VexLength {
+    _128,
+    _256,
+}
+
+impl VexLength {
+    /// Encode the `L` bit.
+    pub fn bits(&self) -> u8 {
+        match self {
+            Self::_128 => 0b0,
+            Self::_256 => 0b1,
+        }
+    }
+}
+
+impl Default for VexLength {
+    fn default() -> Self {
+        Self::_128
+    }
+}
+
+/// Describe the register index to use. This wrapper is a type-safe way to pass
+/// around the registers defined in `inst/regs.rs`.
+#[derive(Debug, Copy, Clone, Default)]
+pub struct Register(u8);
+impl From<u8> for Register {
+    fn from(reg: u8) -> Self {
+        debug_assert!(reg < 16);
+        Self(reg)
+    }
+}
+impl Into<u8> for Register {
+    fn into(self) -> u8 {
+        self.0
+    }
+}
 
 impl Vex {
-    fn validate(&self) {
-        todo!()
+    pub fn length(self, length: VexLength) -> Self {
+        Self { length, ..self }
+    }
+    pub fn pp(self, pp: VexPP) -> Self {
+        Self { pp, ..self }
+    }
+    pub fn mmmmm(self, mmmmm: VexMMMMM) -> Self {
+        Self { mmmmm, ..self }
+    }
+
+    fn validate(&self, _operands: &[Operand]) {}
+}
+
+impl From<Vex> for Encoding {
+    fn from(vex: Vex) -> Encoding {
+        Encoding::Vex(vex)
+    }
+}
+
+impl fmt::Display for Vex {
+    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+        write!(f, "VEX")?;
+        match self.length {
+            VexLength::_128 => write!(f, ".128")?,
+            VexLength::_256 => write!(f, ".256")?,
+        }
+        write!(f, " {:#04x}", self.opcodes.primary)?;
+        Ok(())
     }
 }

cranelift/assembler-x64/meta/src/dsl/format.rs

@@ -300,35 +300,47 @@ pub enum Location {
     rm64,
 
     // XMM registers, and their memory forms.
-    xmm,
     xmm_m32,
     xmm_m64,
     xmm_m128,
+    ymm_m256,
+    zmm_m512,
 
     // Memory-only locations.
     m8,
     m16,
     m32,
     m64,
+    xmm1,
+    xmm2,
+    xmm3,
+    ymm1,
+    ymm2,
+    ymm3,
+    zmm1,
+    zmm2,
+    zmm3,
 }
 
 impl Location {
     /// Return the number of bits accessed.
     #[must_use]
-    pub fn bits(&self) -> u8 {
+    pub fn bits(&self) -> u16 {
         use Location::*;
         match self {
             al | cl | imm8 | r8 | rm8 | m8 => 8,
             ax | dx | imm16 | r16 | rm16 | m16 => 16,
             eax | edx | imm32 | r32 | rm32 | m32 | xmm_m32 => 32,
             rax | rdx | r64 | rm64 | m64 | xmm_m64 => 64,
-            xmm | xmm_m128 => 128,
+            xmm1 | xmm2 | xmm3 | xmm_m128 => 128,
+            ymm1 | ymm2 | ymm3 | ymm_m256 => 256,
+            zmm1 | zmm2 | zmm3 | zmm_m512 => 512,
         }
     }
 
     /// Return the number of bytes accessed, for convenience.
     #[must_use]
-    pub fn bytes(&self) -> u8 {
+    pub fn bytes(&self) -> u16 {
         self.bits() / 8
     }
 
@@ -338,8 +350,9 @@ impl Location {
         use Location::*;
         match self {
             al | ax | eax | rax | cl | dx | edx | rdx | imm8 | imm16 | imm32 | r8 | r16 | r32
-            | r64 | xmm => false,
-            rm8 | rm16 | rm32 | rm64 | xmm_m32 | xmm_m64 | xmm_m128 | m8 | m16 | m32 | m64 => true,
+            | r64 | xmm1 | xmm2 | xmm3 | ymm1 | ymm2 | ymm3 | zmm1 | zmm2 | zmm3 => false,
+            rm8 | rm16 | rm32 | rm64 | xmm_m32 | xmm_m64 | xmm_m128 | m8 | m16 | m32 | m64
+            | ymm_m256 | zmm_m512 => true,
         }
     }
 
@@ -351,7 +364,8 @@ impl Location {
         match self {
             imm8 | imm16 | imm32 => false,
             al | ax | eax | rax | cl | dx | edx | rdx | r8 | r16 | r32 | r64 | rm8 | rm16
-            | rm32 | rm64 | xmm | xmm_m32 | xmm_m64 | xmm_m128 | m8 | m16 | m32 | m64 => true,
+            | rm32 | rm64 | m8 | m16 | m32 | m64 | xmm1 | xmm2 | xmm3 | xmm_m32 | xmm_m64
+            | ymm1 | ymm2 | ymm3 | zmm1 | zmm2 | zmm3 | xmm_m128 | ymm_m256 | zmm_m512 => true,
         }
     }
 
@@ -362,8 +376,12 @@ impl Location {
         match self {
             al | ax | eax | rax | cl | dx | edx | rdx => OperandKind::FixedReg(*self),
             imm8 | imm16 | imm32 => OperandKind::Imm(*self),
-            r8 | r16 | r32 | r64 | xmm => OperandKind::Reg(*self),
-            rm8 | rm16 | rm32 | rm64 | xmm_m32 | xmm_m64 | xmm_m128 => OperandKind::RegMem(*self),
+            r8 | r16 | r32 | r64 | xmm1 | xmm2 | xmm3 | ymm1 | ymm2 | ymm3 | zmm1 | zmm2 | zmm3 => {
+                OperandKind::Reg(*self)
+            }
+            rm8 | rm16 | rm32 | rm64 | xmm_m32 | xmm_m64 | xmm_m128 | ymm_m256 | zmm_m512 => {
+                OperandKind::RegMem(*self)
+            }
             m8 | m16 | m32 | m64 => OperandKind::Mem(*self),
         }
     }
@@ -379,7 +397,8 @@ impl Location {
             imm8 | imm16 | imm32 | m8 | m16 | m32 | m64 => None,
             al | ax | eax | rax | cl | dx | edx | rdx | r8 | r16 | r32 | r64 | rm8 | rm16
             | rm32 | rm64 => Some(RegClass::Gpr),
-            xmm | xmm_m32 | xmm_m64 | xmm_m128 => Some(RegClass::Xmm),
+            xmm1 | xmm2 | xmm3 | ymm1 | ymm2 | ymm3 | zmm1 | zmm2 | zmm3 | xmm_m32 | xmm_m64
+            | xmm_m128 | ymm_m256 | zmm_m512 => Some(RegClass::Xmm),
         }
     }
 }
@@ -410,15 +429,28 @@ impl core::fmt::Display for Location {
             rm32 => write!(f, "rm32"),
             rm64 => write!(f, "rm64"),
 
-            xmm => write!(f, "xmm"),
             xmm_m32 => write!(f, "xmm_m32"),
             xmm_m64 => write!(f, "xmm_m64"),
             xmm_m128 => write!(f, "xmm_m128"),
+            ymm_m256 => write!(f, "ymm_m256"),
+            zmm_m512 => write!(f, "zmm_m512"),
 
             m8 => write!(f, "m8"),
             m16 => write!(f, "m16"),
             m32 => write!(f, "m32"),
             m64 => write!(f, "m64"),
+
+            xmm1 => write!(f, "xmm1"),
+            xmm2 => write!(f, "xmm2"),
+            xmm3 => write!(f, "xmm3"),
+
+            ymm1 => write!(f, "ymm1"),
+            ymm2 => write!(f, "ymm2"),
+            ymm3 => write!(f, "ymm3"),
+
+            zmm1 => write!(f, "zmm1"),
+            zmm2 => write!(f, "zmm2"),
+            zmm3 => write!(f, "zmm3"),
         }
     }
 }