wip

Author: ghostway0

cranelift/codegen/src/isa/riscv64/inst.isle

@@ -2871,6 +2871,19 @@
 ;; zero-extension for the `Value` input.
 (decl put_value_in_reg_for_icmp (IntCC Value) XReg)
 
+(decl madd_overflow64 (XReg XReg XReg) ValueRegs)
+
+(rule (madd_overflow64 x y z)
+  (let ((one XReg (imm $I8 1))
+        (hi XReg (rv_mulhu x y))
+        (m XReg (rv_mul x y))
+        (of_mul XReg (gen_select_xreg (cmp_eqz hi) (zero_reg) one))
+        (sum XReg (rv_add m z))
+        (of_add XReg (gen_select_xreg (int_compare (IntCC.UnsignedLessThan) sum m) one (zero_reg)))
+        (of XReg (rv_or of_mul of_add)))
+    (value_regs sum of)))
+
+
 ;; Base cases, use the `cc` to determine whether to zero or sign extend.
 (rule 0 (put_value_in_reg_for_icmp cc val)
   (zext val))

cranelift/codegen/src/isa/riscv64/lower.isle

@@ -347,14 +347,56 @@
 (rule 0 (lower (has_type (fits_in_32 ty) (umul_overflow x y)))
   (let ((tmp_x XReg (zext x))
         (tmp_y XReg (zext y))
-        (res XReg (rv_mulhu tmp_x tmp_y))
-        (hi XReg (rv_mul tmp_x tmp_y))
-        (one XReg (imm $I32 1))
-        (of XReg (gen_select_xreg (cmp_eqz res) one (zero_reg))))
+        (res XReg (rv_mul tmp_x tmp_y))
+        (hi XReg (rv_srli res (imm12_const (ty_bits ty))))
+        (one XReg (imm $I8 1))
+        (of XReg (gen_select_xreg (cmp_eqz hi) (zero_reg) one)))
+    (output_pair
+         (value_reg res)
+         (value_reg of))))
+
+(rule 1 (lower (has_type $I64 (umul_overflow x y)))
+  (let ((hi XReg (rv_mulhu x y))
+        (res XReg (rv_mul x y))
+        (one XReg (imm $I8 1))
+        (of XReg (gen_select_xreg (cmp_eqz hi) (zero_reg) one)))
     (output_pair
          (value_reg res)
          (value_reg of))))
 
+;; TODO
+(rule 2 (lower (has_type $I128 (umul_overflow x y)))
+  (let
+    ((x_regs ValueRegs x)
+      (x_lo XReg (value_regs_get x_regs 0))
+      (x_hi XReg (value_regs_get x_regs 1))
+
+      ;; Get the high/low registers for `y`.
+      (y_regs ValueRegs y)
+      (y_lo XReg (value_regs_get y_regs 0))
+      (y_hi XReg (value_regs_get y_regs 1))
+
+      ;; 128bit mul formula:
+      ;;   dst_lo = x_lo * y_lo
+      ;;   dst_hi = mulhu(x_lo, y_lo) + (x_lo * y_hi) + (x_hi * y_lo)
+      ;;
+      ;; We can convert the above formula into the following
+      ;; mulhu   dst_hi, x_lo, y_lo
+      ;; madd    dst_hi, x_lo, y_hi, dst_hi
+      ;; madd    dst_hi, x_hi, y_lo, dst_hi
+      ;; madd    dst_lo, x_lo, y_lo, zero
+      (dst_hi1 XReg (rv_mulhu x_lo y_lo))
+      (one XReg (imm $I32 1))
+      (dst_hi2 ValueRegs (madd_overflow64 x_lo y_hi (value_regs_get dst_hi1 0)))
+      (dst_hi ValueRegs (madd_overflow64 x_hi y_lo (value_regs_get dst_hi2 0)))
+      (dst_lo XReg (madd x_lo y_lo (zero_reg)))
+
+      (of_res1 XReg (rv_or (value_regs_get dst_hi1 1) (value_regs_get dst_hi2 1)))
+      (of_res XReg (rv_or of_res1 (value_regs_get dst_hi 1))))
+    (output_pair
+         (value_regs dst_lo (value_regs_get dst_hi 0))
+     (value_reg of_res))))
+
 ;;;; Rules for `isub` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;; Base case, simply subtracting things in registers.