@@ -1007,7 +1007,7 @@ impl MachInstEmit for Inst {
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sink. put4 ( enc_vecmov ( /* 16b = */ true , rd, rn) ) ;
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}
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& Inst :: FpuMoveFromVec { rd, rn, idx, size } => {
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- let ( imm5, shift, mask) = match size {
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+ let ( imm5, shift, mask) = match size. lane_size ( ) {
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ScalarSize :: Size32 => ( 0b00100 , 3 , 0b011 ) ,
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ScalarSize :: Size64 => ( 0b01000 , 4 , 0b001 ) ,
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_ => unimplemented ! ( ) ,
@@ -1048,6 +1048,10 @@ impl MachInstEmit for Inst {
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FPUOp2 :: Max64 => 0b000_11110_01_1_00000_010010 ,
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FPUOp2 :: Min32 => 0b000_11110_00_1_00000_010110 ,
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FPUOp2 :: Min64 => 0b000_11110_01_1_00000_010110 ,
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+ FPUOp2 :: Sqadd64 => 0b010_11110_11_1_00000_000011 ,
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+ FPUOp2 :: Uqadd64 => 0b011_11110_11_1_00000_000011 ,
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+ FPUOp2 :: Sqsub64 => 0b010_11110_11_1_00000_001011 ,
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+ FPUOp2 :: Uqsub64 => 0b011_11110_11_1_00000_001011 ,
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} ;
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sink. put4 ( enc_fpurrr ( top22, rd, rn, rm) ) ;
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}
@@ -1102,31 +1106,25 @@ impl MachInstEmit for Inst {
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} ;
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sink. put4 ( enc_fpurrrr ( top17, rd, rn, rm, ra) ) ;
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}
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- & Inst :: VecMisc { op, rd, rn, ty } => {
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- let enc_size = match ty {
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- I8X16 => 0b00 ,
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- I16X8 => 0b01 ,
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- I32X4 => 0b10 ,
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- I64X2 => 0b11 ,
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- _ => 0 ,
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+ & Inst :: VecMisc { op, rd, rn, size } => {
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+ let enc_size = match size {
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+ VectorSize :: Size8x16 => 0b00 ,
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+ VectorSize :: Size16x8 => 0b01 ,
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+ VectorSize :: Size32x4 => 0b10 ,
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+ VectorSize :: Size64x2 => 0b11 ,
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+ _ => unimplemented ! ( ) ,
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} ;
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let ( bits_12_16, size) = match op {
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- VecMisc2 :: Not => {
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- debug_assert_eq ! ( 128 , ty_bits( ty) ) ;
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- ( 0b00101 , 0b00 )
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- }
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- VecMisc2 :: Neg => {
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- debug_assert_eq ! ( 128 , ty_bits( ty) ) ;
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- ( 0b01011 , enc_size)
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- }
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+ VecMisc2 :: Not => ( 0b00101 , 0b00 ) ,
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+ VecMisc2 :: Neg => ( 0b01011 , enc_size) ,
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} ;
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sink. put4 ( enc_vec_rr_misc ( size, bits_12_16, rd, rn) ) ;
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}
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- & Inst :: VecLanes { op, rd, rn, ty } => {
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- let ( q, size) = match ty {
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- I8X16 => ( 0b1 , 0b00 ) ,
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- I16X8 => ( 0b1 , 0b01 ) ,
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- I32X4 => ( 0b1 , 0b10 ) ,
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+ & Inst :: VecLanes { op, rd, rn, size } => {
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+ let ( q, size) = match size {
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+ VectorSize :: Size8x16 => ( 0b1 , 0b00 ) ,
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+ VectorSize :: Size16x8 => ( 0b1 , 0b01 ) ,
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+ VectorSize :: Size32x4 => ( 0b1 , 0b10 ) ,
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_ => unreachable ! ( ) ,
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} ;
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let ( u, opcode) = match op {
@@ -1250,12 +1248,12 @@ impl MachInstEmit for Inst {
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| machreg_to_vec ( rd. to_reg ( ) ) ,
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) ;
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}
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- & Inst :: MovFromVec { rd, rn, idx, ty } => {
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- let ( q, imm5, shift, mask) = match ty {
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- I8 => ( 0b0 , 0b00001 , 1 , 0b1111 ) ,
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- I16 => ( 0b0 , 0b00010 , 2 , 0b0111 ) ,
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- I32 => ( 0b0 , 0b00100 , 3 , 0b0011 ) ,
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- I64 => ( 0b1 , 0b01000 , 4 , 0b0001 ) ,
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+ & Inst :: MovFromVec { rd, rn, idx, size } => {
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+ let ( q, imm5, shift, mask) = match size {
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+ VectorSize :: Size8x16 => ( 0b0 , 0b00001 , 1 , 0b1111 ) ,
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+ VectorSize :: Size16x8 => ( 0b0 , 0b00010 , 2 , 0b0111 ) ,
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+ VectorSize :: Size32x4 => ( 0b0 , 0b00100 , 3 , 0b0011 ) ,
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+ VectorSize :: Size64x2 => ( 0b1 , 0b01000 , 4 , 0b0001 ) ,
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_ => unreachable ! ( ) ,
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} ;
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debug_assert_eq ! ( idx & mask, idx) ;
@@ -1268,12 +1266,12 @@ impl MachInstEmit for Inst {
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| machreg_to_gpr ( rd. to_reg ( ) ) ,
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) ;
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}
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- & Inst :: VecDup { rd, rn, ty } => {
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- let imm5 = match ty {
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- I8 => 0b00001 ,
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- I16 => 0b00010 ,
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- I32 => 0b00100 ,
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- I64 => 0b01000 ,
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+ & Inst :: VecDup { rd, rn, size } => {
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+ let imm5 = match size {
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+ VectorSize :: Size8x16 => 0b00001 ,
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+ VectorSize :: Size16x8 => 0b00010 ,
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+ VectorSize :: Size32x4 => 0b00100 ,
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+ VectorSize :: Size64x2 => 0b01000 ,
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_ => unimplemented ! ( ) ,
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} ;
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sink. put4 (
@@ -1283,10 +1281,10 @@ impl MachInstEmit for Inst {
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| machreg_to_vec ( rd. to_reg ( ) ) ,
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) ;
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}
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- & Inst :: VecDupFromFpu { rd, rn, ty } => {
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- let imm5 = match ty {
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- F32 => 0b00100 ,
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- F64 => 0b01000 ,
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+ & Inst :: VecDupFromFpu { rd, rn, size } => {
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+ let imm5 = match size {
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+ VectorSize :: Size32x4 => 0b00100 ,
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+ VectorSize :: Size64x2 => 0b01000 ,
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_ => unimplemented ! ( ) ,
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} ;
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sink. put4 (
@@ -1318,41 +1316,25 @@ impl MachInstEmit for Inst {
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rn,
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rm,
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alu_op,
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- ty ,
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+ size ,
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} => {
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- let enc_size = match ty {
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- I8X16 => 0b00 ,
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- I16X8 => 0b01 ,
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- I32X4 => 0b10 ,
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- I64X2 => 0b11 ,
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+ let enc_size = match size {
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+ VectorSize :: Size8x16 => 0b00 ,
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+ VectorSize :: Size16x8 => 0b01 ,
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+ VectorSize :: Size32x4 => 0b10 ,
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+ VectorSize :: Size64x2 => 0b11 ,
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_ => 0 ,
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} ;
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- let enc_size_for_fcmp = match ty {
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- F32X4 => 0b0 ,
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- F64X2 => 0b1 ,
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+ let enc_size_for_fcmp = match size {
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+ VectorSize :: Size32x4 => 0b0 ,
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+ VectorSize :: Size64x2 => 0b1 ,
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_ => 0 ,
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} ;
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let ( top11, bit15_10) = match alu_op {
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- VecALUOp :: SQAddScalar => {
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- debug_assert_eq ! ( I64 , ty) ;
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- ( 0b010_11110_11_1 , 0b000011 )
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- }
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VecALUOp :: Sqadd => ( 0b010_01110_00_1 | enc_size << 1 , 0b000011 ) ,
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- VecALUOp :: SQSubScalar => {
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- debug_assert_eq ! ( I64 , ty) ;
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- ( 0b010_11110_11_1 , 0b001011 )
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- }
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VecALUOp :: Sqsub => ( 0b010_01110_00_1 | enc_size << 1 , 0b001011 ) ,
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- VecALUOp :: UQAddScalar => {
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- debug_assert_eq ! ( I64 , ty) ;
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- ( 0b011_11110_11_1 , 0b000011 )
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- }
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VecALUOp :: Uqadd => ( 0b011_01110_00_1 | enc_size << 1 , 0b000011 ) ,
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- VecALUOp :: UQSubScalar => {
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- debug_assert_eq ! ( I64 , ty) ;
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- ( 0b011_11110_11_1 , 0b001011 )
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- }
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VecALUOp :: Uqsub => ( 0b011_01110_00_1 | enc_size << 1 , 0b001011 ) ,
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VecALUOp :: Cmeq => ( 0b011_01110_00_1 | enc_size << 1 , 0b100011 ) ,
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VecALUOp :: Cmge => ( 0b010_01110_00_1 | enc_size << 1 , 0b001111 ) ,
@@ -1364,31 +1346,16 @@ impl MachInstEmit for Inst {
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VecALUOp :: Fcmge => ( 0b011_01110_00_1 | enc_size_for_fcmp << 1 , 0b111001 ) ,
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// The following logical instructions operate on bytes, so are not encoded differently
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// for the different vector types.
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- VecALUOp :: And => {
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- debug_assert_eq ! ( 128 , ty_bits( ty) ) ;
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- ( 0b010_01110_00_1 , 0b000111 )
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- }
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- VecALUOp :: Bic => {
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- debug_assert_eq ! ( 128 , ty_bits( ty) ) ;
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- ( 0b010_01110_01_1 , 0b000111 )
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- }
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- VecALUOp :: Orr => {
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- debug_assert_eq ! ( 128 , ty_bits( ty) ) ;
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- ( 0b010_01110_10_1 , 0b000111 )
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- }
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- VecALUOp :: Eor => {
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- debug_assert_eq ! ( 128 , ty_bits( ty) ) ;
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- ( 0b011_01110_00_1 , 0b000111 )
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- }
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- VecALUOp :: Bsl => {
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- debug_assert_eq ! ( 128 , ty_bits( ty) ) ;
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- ( 0b011_01110_01_1 , 0b000111 )
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- }
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+ VecALUOp :: And => ( 0b010_01110_00_1 , 0b000111 ) ,
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+ VecALUOp :: Bic => ( 0b010_01110_01_1 , 0b000111 ) ,
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+ VecALUOp :: Orr => ( 0b010_01110_10_1 , 0b000111 ) ,
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+ VecALUOp :: Eor => ( 0b011_01110_00_1 , 0b000111 ) ,
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+ VecALUOp :: Bsl => ( 0b011_01110_01_1 , 0b000111 ) ,
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VecALUOp :: Umaxp => ( 0b011_01110_00_1 | enc_size << 1 , 0b101001 ) ,
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VecALUOp :: Add => ( 0b010_01110_00_1 | enc_size << 1 , 0b100001 ) ,
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VecALUOp :: Sub => ( 0b011_01110_00_1 | enc_size << 1 , 0b100001 ) ,
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VecALUOp :: Mul => {
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- debug_assert_ne ! ( I64X2 , ty ) ;
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+ debug_assert_ne ! ( size , VectorSize :: Size64x2 ) ;
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( 0b010_01110_00_1 | enc_size << 1 , 0b100111 )
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}
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VecALUOp :: Sshl => ( 0b010_01110_00_1 | enc_size << 1 , 0b010001 ) ,
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