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boiler_plate.py
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boiler_plate.py
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import os
HOME = os.getcwd()
HEADER = '''
<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01//EN">
<html>
<head>
<title>Rassul Bairamkulov: Homepage</title>
<link rel="stylesheet" href="css/style.css">
<!-- based on https://cdn.simplecss.org/simple.css -->
</head>
'''
def make_header(append_str : str) -> str:
return f'''
<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01//EN">
<html>
<head>
<title>Rassul Bairamkulov | {append_str}</title>
<link rel="stylesheet" href="css/style.css">
<!-- based on https://cdn.simplecss.org/simple.css -->
</head>
'''
NAVBAR = '''
<nav>
<a href="index.html">Home </a>
<a href="pub.html" >Publications</a>
<a href="CV_Main.html" > CV </a>
</nav>
'''
FOOTER = '''
</p>
</body>
</html>
'''
BODY_HEADER = '''
<!-- Main content -->
<h1>Rassul Bairamkulov</h1>
<h3>Advancing EDA tools for next-generation computing systems</h3>
'''
# <h2>Postdoctoral Scholar at EPFL</h2>
# <h3>Advancing EDA for next-generation computing systems</h3>
ADDRESS = '''
<address>
<br><br><br>
Integrated Systems Laboratory LSI<br>
EPFL, Building INF 339<br>
Lausanne 1015, Switzerland<br>
</address>
'''
# <img width="100em" src="images/part1.png" alt="part1">
# <img width="190em" src="images/part2.png" alt="part2">
WELCOME = '''
<p>Hello and welcome to my webpage.</p>
<p>I am a postdoctoral scholar in the <a href="https://www.epfl.ch/labs/lsi/">Integrated Systems Laboratory</a> (LSI) at EPFL, Lausanne, Switzerland, working alongside <a href="https://si2.epfl.ch/~demichel/">Professor Giovanni De Micheli</a> developing electronic design automation tools for the emerging VLSI technologies. </p>
<p>I completed my Ph.D. in Electrical and Computer Engineering at the <a href="https://www.hajim.rochester.edu/ece/">University of Rochester</a>, Rochester, New York, under the supervision of <a href="http://www2.ece.rochester.edu/users/friedman/">Professor E. G. Friedman</a>.</p>
<p>I was an intern at Qualcomm Inc., San Diego, California, during the summers of 2018 and 2020.</p>
<p>Prior to my doctoral studies, I received my B.Eng. in Electrical and Electronic Engineering at <a href="https://nu.edu.kz">Nazarbayev University</a>, Astana, Kazakhstan.</p>
<p>For more information, please see my <a href="CV_Main.html">CV</a>, <a href="pub.html">list of my publications</a>, or my profile at <a href="https://scholar.google.com/citations?hl=en&user=RgDE-cIAAAAJ">Google Scholar</a>.</p>
'''
BIO = '''
<p>Rassul Bairamkulov was born in August 1994 in Karaganda, Kazakhstan.<br>
He received a Bachelor of Engineering degree in Electrical and Electronic Engineering from Nazarbayev University in Astana, Kazakhstan in 2016, and a Master of Science degree in Electrical and Computer Engineering from the University of Rochester in Rochester, NY in 2018.
I was an intern at Qualcomm in San Diego, California, during the summers of 2018 and 2020
He is currently completing the Ph.D. degree in Electrical and Computer Engineering from the University of Rochester in Rochester, NY under the supervision of Prof. Eby G. Friedman.
His current research interests include graph theory, physical design of integrated circuits, and electronic design automation of conventional and emerging VLSI technologies.</p>
'''
SKIP = '''
<h3 id="up">Skip to</h3>
<p>
<a href="#conference">Conference papers</a><br>
<a href="#presentation">Talks</a><br>
<a href="#dissertation">Dissertation</a>
</p>
'''
JOURNALS = {
'tcad' : 'IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems',
'tvlsi' : 'IEEE Transactions on Very Large Scale Integration (VLSI) Systems',
'tcasi': 'IEEE Transactions on Circuits and Systems I: Regular Papers',
}
CONFERENCES = {
'aspdac24': 'Proceedings of the ACM/IEEE Asia South Pacific Design Automation Conference, Incheon, South Korea',
'vlsisoc23': 'Proceedings of the IEEE/IFIP International Conference on Very Large Scale Integration, Sharjah, United Arab Emirates',
'glsvlsi23': 'Proceedings of the ACM Great Lakes Symposium on VLSI, Knoxville, Tennessee',
'iscas20': 'Proceedings of the IEEE International Symposium on Circuits and Systems, Virtual',
'iscas18': 'Proceedings of the IEEE International Symposium on Circuits and Systems, Florence, Italy',
'dac21' : 'Proceedings of the ACM/IEEE Design Automation Conference, San Francisco, California',
'pemc' : 'Proceedings of the IEEE International Power Electronics and Motion Control Conference, Varna, Bulgaria'
}
BOOKS = {
'springer_cham' : 'Springer, Cham, Switzerland'
}
JC = {**JOURNALS,**CONFERENCES, **BOOKS}
FANCY_NAMES = {
'me' : '<strong>R. Bairamkulov</strong>',
'EGF' : '<a href="http://www2.ece.rochester.edu/~friedman/">E. G. Friedman</a>',
'AR' : 'A. Ruderman',
'YLF' : 'Y. L. Familiant',
'ARoy': 'A. Roy',
'JSO' : 'J. S. Ochoa',
'KX' : 'K. Xu',
'MN' : 'M. Nagarajan',
'NZ' : 'N. Zhuldassov',
'MP' : 'M. Popovich',
'TJ' : 'T. Jabbari',
'VS' : 'V. Srinivas',
'GDM' : '<a href="https://si2.epfl.ch/~demichel/">G. De Micheli</a>',
'ATC' : '<a href="https://aletempiac.github.io/">A. Tempia Calvino</a>',
}
PLAIN_NAMES = {
'me' : 'R. Bairamkulov',
'EGF' : 'E. G. Friedman',
'AR' : 'A. Ruderman',
'YLF' : 'Y. L. Familiant',
'ARoy' : 'A. Roy',
'JSO' : 'J. S. Ochoa',
'KX' : 'K. Xu',
'MN' : 'M. Nagarajan',
'NZ' : 'N. Zhuldassov',
'MP' : 'M. Popovich',
'TJ' : 'T. Jabbari',
'VS' : 'V. Srinivas',
'GDM' : 'G. De Micheli',
'ATC' : 'A. Tempia Calvino',
}
PRESENTATIONS = '''
<h2 id="presentation">Talks</h2><a href=#up>Return to top</a>
<p>
<strong>R. Bairamkulov</strong>, "Graph Algorithms for VLSI Power and Clock Networks," University of Rochester, Rochester, New York, April 27, 2022.<br>
<a href="talks/Defense.pdf">PDF</a> <a href="talks/maps.pptx">Maps</a> <a href="talks/Defense_Supplemental.zip">Supplemental Material</a>
</p>
<p>
<strong>R. Bairamkulov</strong>, "SPROUT—Smart Power Routing Tool for Board-Level Exploration and Prototyping," ACM/IEEE Design Automation Conference, San Francisco, California, December 7, 2022.<br>
</p>
<p>
<strong>R. Bairamkulov</strong>, "Graph-Based Power Network Routing for Board-Level High Performance Systems," IEEE International Symposium on Circuits and Systems, (Virtual Event), October 12, 2020.<br>
<a href="https://doi.org/10.1109/ISCAS45731.2020.9181140">Video@IEEEXplore</a>
</p>
'''
DISSERTATION = '''
<h2 id="dissertation">Dissertation</h2><a href=#up>Return to top</a>
<p>
<strong>R. Bairamkulov</strong>, "Graph Algorithms for VLSI Power and Clock Networks," University of Rochester, Rochester, New York, April 2022.
<details>
<summary>
<u>Bibtex</u>
<a href="papers/Thesis_PQ.pdf">PDF</a>
<a href="http://hdl.handle.net/1802/36890">UR Research Repository</a>
<a href="https://dl.acm.org/doi/book/10.5555/AAI29259269">ACM</a>
<a href="https://www.proquest.com/docview/2708414430?parentSessionId=kJ3vHKHHaTgHThkZUqwg3O96bNcasUUodmcR5E2mK38%3D">ProQuest</a>
</summary>
<span>@phdthesis{bairamkulov_2022_thesis,<br> author = "R. Bairamkulov",<br> title = "Graph Algorithms for VLSI Power and Clock Networks",<br> school = "University of Rochester",<br> year = "2022",<br>}
</span>
</details>
</p>
'''
MONTHS = { 'Jan': 'January', 'Feb': 'February', 'Mar': 'March', 'Apr': 'April', 'May': 'May', 'Jun': 'June', 'Jul': 'July', 'Aug': 'August', 'Sep': 'September', 'Oct': 'October', 'Nov': 'November', 'Dec': 'December', 1: 'January', 2: 'February', 3: 'March', 4: 'April', 5: 'May', 6: 'June', 7: 'July', 8: 'August', 9: 'September', 10: 'October', 11: 'November', 12: 'December',}
PROJECTS = '''
'''
# https://dl.acm.org/doi/book/10.5555/AAI29259269