From b42c1356f8ce54388dd9bc7dc88d0f52a4be9a43 Mon Sep 17 00:00:00 2001 From: Patrick Egan Date: Fri, 25 Mar 2016 15:11:31 -0400 Subject: [PATCH 01/12] Added _VHDLNameValidation.py with a list to contain all VHDL keywords and a function to return true if a string passed through matched one of the VHDL keywords --- myhdl/conversion/_VHDLNameValidation.py | 34 +++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 myhdl/conversion/_VHDLNameValidation.py diff --git a/myhdl/conversion/_VHDLNameValidation.py b/myhdl/conversion/_VHDLNameValidation.py new file mode 100644 index 000000000..8fc6603c2 --- /dev/null +++ b/myhdl/conversion/_VHDLNameValidation.py @@ -0,0 +1,34 @@ +#Save all words which would generate errors in VHDL here +#TODO: Make appropriate calls to raise warnings in _toVHDL.py + +#A list of all reserved words within VHDL which should not be used for +#anything other than their own specific purpose +_vhdl_keywords = ("-", "abs", "access", "after", "alias", "all", + "and", "architecture", "array", "assert", + "attribute", "begin", "block", "body", "buffer", + "bus", "case", "component", "configuration", + "constant", "disconnect", "downto", "else", + "elseif", "end", "entity", "exit", "file", "for", + "function", "generate", "generic", "group", + "guarded", "if", "impure", "in", "inertial", + "inout", "is", "label", "library", "linkage", + "literal", "loop", "map", "mod", "nand", "new", + "next", "nor", "not", "null", "of", "on", "open", + "or", "others", "out", "package", "port", + "postponed", "procedure", "process", "pure", + "range", "record", "register", "reject", "rem", + "report", "return", "rol", "ror", "select", + "severity", "signal", "shared", "sla", "sll", "sra", + "srl", "subtype", "then", "to", "transport", "type", + "unaffected", "units", "until", "use", "variable", + "wait", "when", "while", "with", "xnor", "xor") + +#Function which compares current parsed signal/entity to all keywords to +#ensure reserved words are not being used for the wrong purpose +def _syntaxValid(keyword): + for i in _vhdl_keywords: + if keyword == _vhdl_keywords[i]: + return True + if keyword[0] == '_': + return True + return False \ No newline at end of file From 246377894b339baf85babf4925173ab34a467a86 Mon Sep 17 00:00:00 2001 From: Patrick Egan Date: Fri, 25 Mar 2016 15:53:11 -0400 Subject: [PATCH 02/12] Completed nameValid function --- myhdl/conversion/_VHDLNameValidation.py | 27 ++++++++++++++++++------- 1 file changed, 20 insertions(+), 7 deletions(-) diff --git a/myhdl/conversion/_VHDLNameValidation.py b/myhdl/conversion/_VHDLNameValidation.py index 8fc6603c2..6a9c0a8ec 100644 --- a/myhdl/conversion/_VHDLNameValidation.py +++ b/myhdl/conversion/_VHDLNameValidation.py @@ -1,9 +1,12 @@ +import warnings +from myhdl import ToVHDLWarning + #Save all words which would generate errors in VHDL here #TODO: Make appropriate calls to raise warnings in _toVHDL.py #A list of all reserved words within VHDL which should not be used for #anything other than their own specific purpose -_vhdl_keywords = ("-", "abs", "access", "after", "alias", "all", +_vhdl_keywords = ["abs", "access", "after", "alias", "all", "and", "architecture", "array", "assert", "attribute", "begin", "block", "body", "buffer", "bus", "case", "component", "configuration", @@ -21,14 +24,24 @@ "severity", "signal", "shared", "sla", "sll", "sra", "srl", "subtype", "then", "to", "transport", "type", "unaffected", "units", "until", "use", "variable", - "wait", "when", "while", "with", "xnor", "xor") + "wait", "when", "while", "with", "xnor", "xor"]; + +#A list to hold all signal names being used in lowercase to raise an error +#if no names are reused with different casing +_usedNames = []; #Function which compares current parsed signal/entity to all keywords to #ensure reserved words are not being used for the wrong purpose -def _syntaxValid(keyword): +def _nameValid(keyword): for i in _vhdl_keywords: if keyword == _vhdl_keywords[i]: - return True - if keyword[0] == '_': - return True - return False \ No newline at end of file + warnings.warn("VHDL keyword used: %s" % keyword, category=ToVHDLWarning) + for i in _usedNames: + if keyword.lower() == _usedNames[i]: + warnings.warn("Previously used name being reused: %s" % keyword, category=ToVHDLWarning) + _usedNames.append(keyword).lower + if keyword[0] == '_': + warnings.warn("VHDL variable names cannot contain '_': %s" % keyword, category=ToVHDLWarning) + for i in keyword: + if keyword[i] == '-': + warnings.warn("VHDL variable names cannot contain '-': %s" % keyword, category=ToVHDLWarning) \ No newline at end of file From 56429acf398fb42bc25f07b66315a86f8fa35240 Mon Sep 17 00:00:00 2001 From: Patrick Egan Date: Fri, 25 Mar 2016 15:59:21 -0400 Subject: [PATCH 03/12] Encapsulated all of the name validation script into a class --- myhdl/conversion/_VHDLNameValidation.py | 40 +++++++++++++------------ 1 file changed, 21 insertions(+), 19 deletions(-) diff --git a/myhdl/conversion/_VHDLNameValidation.py b/myhdl/conversion/_VHDLNameValidation.py index 6a9c0a8ec..04a4c7391 100644 --- a/myhdl/conversion/_VHDLNameValidation.py +++ b/myhdl/conversion/_VHDLNameValidation.py @@ -6,7 +6,9 @@ #A list of all reserved words within VHDL which should not be used for #anything other than their own specific purpose -_vhdl_keywords = ["abs", "access", "after", "alias", "all", + +class NameValidation: + _vhdl_keywords = ["abs", "access", "after", "alias", "all", "and", "architecture", "array", "assert", "attribute", "begin", "block", "body", "buffer", "bus", "case", "component", "configuration", @@ -26,22 +28,22 @@ "unaffected", "units", "until", "use", "variable", "wait", "when", "while", "with", "xnor", "xor"]; -#A list to hold all signal names being used in lowercase to raise an error -#if no names are reused with different casing -_usedNames = []; + #A list to hold all signal names being used in lowercase to raise an error + #if no names are reused with different casing + _usedNames = []; -#Function which compares current parsed signal/entity to all keywords to -#ensure reserved words are not being used for the wrong purpose -def _nameValid(keyword): - for i in _vhdl_keywords: - if keyword == _vhdl_keywords[i]: - warnings.warn("VHDL keyword used: %s" % keyword, category=ToVHDLWarning) - for i in _usedNames: - if keyword.lower() == _usedNames[i]: - warnings.warn("Previously used name being reused: %s" % keyword, category=ToVHDLWarning) - _usedNames.append(keyword).lower - if keyword[0] == '_': - warnings.warn("VHDL variable names cannot contain '_': %s" % keyword, category=ToVHDLWarning) - for i in keyword: - if keyword[i] == '-': - warnings.warn("VHDL variable names cannot contain '-': %s" % keyword, category=ToVHDLWarning) \ No newline at end of file + #Function which compares current parsed signal/entity to all keywords to + #ensure reserved words are not being used for the wrong purpose + def _nameValid(keyword): + for i in NameValidation._vhdl_keywords: + if keyword == NameValidation._vhdl_keywords[i]: + warnings.warn("VHDL keyword used: %s" % keyword, category=ToVHDLWarning) + for i in NameValidation._usedNames: + if keyword.lower() == NameValidation._usedNames[i]: + warnings.warn("Previously used name being reused: %s" % keyword, category=ToVHDLWarning) + NameValidation._usedNames.append(keyword).lower + if keyword[0] == '_': + warnings.warn("VHDL variable names cannot contain '_': %s" % keyword, category=ToVHDLWarning) + for i in keyword: + if keyword[i] == '-': + warnings.warn("VHDL variable names cannot contain '-': %s" % keyword, category=ToVHDLWarning) \ No newline at end of file From 68f86002cdf84047ee0f65f1b2e3e8d6d53abe6a Mon Sep 17 00:00:00 2001 From: Patrick Egan Date: Fri, 25 Mar 2016 16:18:05 -0400 Subject: [PATCH 04/12] Added implementation of nameValid to toVHDL.py --- myhdl/conversion/_VHDLNameValidation.py | 12 ++++++------ myhdl/conversion/_toVHDL.py | 8 ++++++++ 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/myhdl/conversion/_VHDLNameValidation.py b/myhdl/conversion/_VHDLNameValidation.py index 04a4c7391..6f141555e 100644 --- a/myhdl/conversion/_VHDLNameValidation.py +++ b/myhdl/conversion/_VHDLNameValidation.py @@ -7,7 +7,7 @@ #A list of all reserved words within VHDL which should not be used for #anything other than their own specific purpose -class NameValidation: +class _nameCheck(): _vhdl_keywords = ["abs", "access", "after", "alias", "all", "and", "architecture", "array", "assert", "attribute", "begin", "block", "body", "buffer", @@ -35,13 +35,13 @@ class NameValidation: #Function which compares current parsed signal/entity to all keywords to #ensure reserved words are not being used for the wrong purpose def _nameValid(keyword): - for i in NameValidation._vhdl_keywords: - if keyword == NameValidation._vhdl_keywords[i]: + for i in _nameCheck._vhdl_keywords: + if keyword == _nameCheck._vhdl_keywords[i]: warnings.warn("VHDL keyword used: %s" % keyword, category=ToVHDLWarning) - for i in NameValidation._usedNames: - if keyword.lower() == NameValidation._usedNames[i]: + for i in _nameCheck._usedNames: + if keyword.lower() == _nameCheck._usedNames[i]: warnings.warn("Previously used name being reused: %s" % keyword, category=ToVHDLWarning) - NameValidation._usedNames.append(keyword).lower + _nameCheck._usedNames.append(keyword).lower if keyword[0] == '_': warnings.warn("VHDL variable names cannot contain '_': %s" % keyword, category=ToVHDLWarning) for i in keyword: diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py index a518232e3..7d92d85f0 100644 --- a/myhdl/conversion/_toVHDL.py +++ b/myhdl/conversion/_toVHDL.py @@ -55,6 +55,8 @@ from myhdl._util import _flatten from myhdl._compat import integer_types, class_types, StringIO from myhdl._ShadowSignal import _TristateSignal, _TristateDriver +from myhdl.conversion._VHDLNameValidation import _nameCheck + from myhdl._block import _Block from myhdl._getHierarchy import _getHierarchy @@ -351,6 +353,8 @@ def _writeModuleHeader(f, intf, needPck, lib, arch, useClauses, doc, stdLogicPor pt = st = _getTypeString(s) if convertPort: pt = "std_logic_vector" + # Check if VHDL keyword or reused name + _nameCheck._nameValid(s) if s._driven: if s._read: if not isinstance(s, _TristateSignal): @@ -414,6 +418,8 @@ def _writeSigDecls(f, intf, siglist, memlist): # print >> f, "%s %s%s = %s;" % (s._driven, r, s._name, int(s._val)) print("signal %s: %s%s;" % (s._name, p, r), file=f) elif s._read: + # Check if VHDL keyword or reused name + _nameCheck._nameValid(s) # the original exception # raise ToVHDLError(_error.UndrivenSignal, s._name) # changed to a warning and a continuous assignment to a wire @@ -433,6 +439,8 @@ def _writeSigDecls(f, intf, siglist, memlist): m._read = s._read if not m._driven and not m._read: continue + # Check if VHDL keyword or reused name + _nameCheck._nameValid(m) r = _getRangeString(m.elObj) p = _getTypeString(m.elObj) t = "t_array_%s" % m.name From 06845b8f9028fc1aab835259223c28a35128da8c Mon Sep 17 00:00:00 2001 From: Patrick Egan Date: Fri, 25 Mar 2016 16:38:56 -0400 Subject: [PATCH 05/12] Finished documentation --- myhdl/conversion/_VHDLNameValidation.py | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/myhdl/conversion/_VHDLNameValidation.py b/myhdl/conversion/_VHDLNameValidation.py index 6f141555e..17ab5a71d 100644 --- a/myhdl/conversion/_VHDLNameValidation.py +++ b/myhdl/conversion/_VHDLNameValidation.py @@ -1,13 +1,11 @@ import warnings from myhdl import ToVHDLWarning -#Save all words which would generate errors in VHDL here -#TODO: Make appropriate calls to raise warnings in _toVHDL.py - -#A list of all reserved words within VHDL which should not be used for -#anything other than their own specific purpose - class _nameCheck(): + 'Saves all reserved words in VHDL and variable names used in a MyHDL circuit to check for any name collisions' + + #A list of all reserved words within VHDL which should not be used for + #anything other than their own specific purpose _vhdl_keywords = ["abs", "access", "after", "alias", "all", "and", "architecture", "array", "assert", "attribute", "begin", "block", "body", "buffer", From 7f5daed963c7e3d62ec08a8f98e82de9d101b793 Mon Sep 17 00:00:00 2001 From: Patrick Egan Date: Fri, 25 Mar 2016 19:43:33 -0400 Subject: [PATCH 06/12] Fixed naming in code --- myhdl/conversion/_VHDLNameValidation.py | 26 ++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/myhdl/conversion/_VHDLNameValidation.py b/myhdl/conversion/_VHDLNameValidation.py index 17ab5a71d..e99ceb4e2 100644 --- a/myhdl/conversion/_VHDLNameValidation.py +++ b/myhdl/conversion/_VHDLNameValidation.py @@ -32,16 +32,16 @@ class _nameCheck(): #Function which compares current parsed signal/entity to all keywords to #ensure reserved words are not being used for the wrong purpose - def _nameValid(keyword): - for i in _nameCheck._vhdl_keywords: - if keyword == _nameCheck._vhdl_keywords[i]: - warnings.warn("VHDL keyword used: %s" % keyword, category=ToVHDLWarning) - for i in _nameCheck._usedNames: - if keyword.lower() == _nameCheck._usedNames[i]: - warnings.warn("Previously used name being reused: %s" % keyword, category=ToVHDLWarning) - _nameCheck._usedNames.append(keyword).lower - if keyword[0] == '_': - warnings.warn("VHDL variable names cannot contain '_': %s" % keyword, category=ToVHDLWarning) - for i in keyword: - if keyword[i] == '-': - warnings.warn("VHDL variable names cannot contain '-': %s" % keyword, category=ToVHDLWarning) \ No newline at end of file + def _nameValid(name): + for keyword in _nameCheck._vhdl_keywords: + if name == _nameCheck._vhdl_keywords[keyword]: + warnings.warn("VHDL keyword used: %s" % name, category=ToVHDLWarning) + for saved_name in _nameCheck._usedNames: + if name.lower() == _nameCheck._usedNames[saved_name]: + warnings.warn("Previously used name being reused: %s" % name, category=ToVHDLWarning) + _nameCheck._usedNames.append(name).lower + if name[0] == '_': + warnings.warn("VHDL variable names cannot contain '_': %s" % name, category=ToVHDLWarning) + for pos in name: + if name[pos] == '-': + warnings.warn("VHDL variable names cannot contain '-': %s" % name, category=ToVHDLWarning) \ No newline at end of file From acbe257c8575bebaea394c0ff15eb617aada5ce4 Mon Sep 17 00:00:00 2001 From: Patrick Egan Date: Mon, 30 May 2016 00:10:41 -0400 Subject: [PATCH 07/12] Fixed type error in for loops --- myhdl/conversion/_VHDLNameValidation.py | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/myhdl/conversion/_VHDLNameValidation.py b/myhdl/conversion/_VHDLNameValidation.py index e99ceb4e2..73f55f5d8 100644 --- a/myhdl/conversion/_VHDLNameValidation.py +++ b/myhdl/conversion/_VHDLNameValidation.py @@ -1,5 +1,7 @@ import warnings -from myhdl import ToVHDLWarning +from myhdl import * +from myhdl.conversion import analyze +import pytest class _nameCheck(): 'Saves all reserved words in VHDL and variable names used in a MyHDL circuit to check for any name collisions' @@ -34,14 +36,14 @@ class _nameCheck(): #ensure reserved words are not being used for the wrong purpose def _nameValid(name): for keyword in _nameCheck._vhdl_keywords: - if name == _nameCheck._vhdl_keywords[keyword]: + if name == keyword: warnings.warn("VHDL keyword used: %s" % name, category=ToVHDLWarning) for saved_name in _nameCheck._usedNames: - if name.lower() == _nameCheck._usedNames[saved_name]: + if name.lower() == saved_name: warnings.warn("Previously used name being reused: %s" % name, category=ToVHDLWarning) _nameCheck._usedNames.append(name).lower if name[0] == '_': warnings.warn("VHDL variable names cannot contain '_': %s" % name, category=ToVHDLWarning) - for pos in name: - if name[pos] == '-': + for char in name: + if char == '-': warnings.warn("VHDL variable names cannot contain '-': %s" % name, category=ToVHDLWarning) \ No newline at end of file From 1520d995c146394f344f9404a09f214c8b7bfe18 Mon Sep 17 00:00:00 2001 From: Patrick Egan Date: Thu, 1 Sep 2016 01:51:25 -0400 Subject: [PATCH 08/12] Fixed analyze import problem and updated .gitignore to exclude pycharm configuration files --- myhdl/conversion/_VHDLNameValidation.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/myhdl/conversion/_VHDLNameValidation.py b/myhdl/conversion/_VHDLNameValidation.py index 73f55f5d8..0a3430263 100644 --- a/myhdl/conversion/_VHDLNameValidation.py +++ b/myhdl/conversion/_VHDLNameValidation.py @@ -1,6 +1,6 @@ import warnings from myhdl import * -from myhdl.conversion import analyze +from myhdl.conversion import _analyze import pytest class _nameCheck(): @@ -46,4 +46,4 @@ def _nameValid(name): warnings.warn("VHDL variable names cannot contain '_': %s" % name, category=ToVHDLWarning) for char in name: if char == '-': - warnings.warn("VHDL variable names cannot contain '-': %s" % name, category=ToVHDLWarning) \ No newline at end of file + warnings.warn("VHDL variable names cannot contain '-': %s" % name, category=ToVHDLWarning) From e11125a07a2c7f8aa0db243a77574548b6e733f5 Mon Sep 17 00:00:00 2001 From: Patrick Egan Date: Thu, 1 Sep 2016 12:01:02 -0400 Subject: [PATCH 09/12] Removed class structure and fixed errors related to .lower() usage --- .gitignore | 3 + myhdl/conversion/_VHDLNameValidation.py | 81 ++++++++++++------------- myhdl/conversion/_toVHDL.py | 2 +- 3 files changed, 43 insertions(+), 43 deletions(-) diff --git a/.gitignore b/.gitignore index bd0d0aff6..10fa616dc 100644 --- a/.gitignore +++ b/.gitignore @@ -32,3 +32,6 @@ work_vcom/ # Test artifacts myhdl/**/*.v myhdl/**/*.vhd + +# Pycharm ide junk +.idea/ diff --git a/myhdl/conversion/_VHDLNameValidation.py b/myhdl/conversion/_VHDLNameValidation.py index 0a3430263..e8e27f771 100644 --- a/myhdl/conversion/_VHDLNameValidation.py +++ b/myhdl/conversion/_VHDLNameValidation.py @@ -3,47 +3,44 @@ from myhdl.conversion import _analyze import pytest -class _nameCheck(): - 'Saves all reserved words in VHDL and variable names used in a MyHDL circuit to check for any name collisions' +#A list of all reserved words within VHDL which should not be used for +#anything other than their own specific purpose +_vhdl_keywords = ["abs", "access", "after", "alias", "all", + "and", "architecture", "array", "assert", + "attribute", "begin", "block", "body", "buffer", + "bus", "case", "component", "configuration", + "constant", "disconnect", "downto", "else", + "elseif", "end", "entity", "exit", "file", "for", + "function", "generate", "generic", "group", + "guarded", "if", "impure", "in", "inertial", + "inout", "is", "label", "library", "linkage", + "literal", "loop", "map", "mod", "nand", "new", + "next", "nor", "not", "null", "of", "on", "open", + "or", "others", "out", "package", "port", + "postponed", "procedure", "process", "pure", + "range", "record", "register", "reject", "rem", + "report", "return", "rol", "ror", "select", + "severity", "signal", "shared", "sla", "sll", "sra", + "srl", "subtype", "then", "to", "transport", "type", + "unaffected", "units", "until", "use", "variable", + "wait", "when", "while", "with", "xnor", "xor"]; - #A list of all reserved words within VHDL which should not be used for - #anything other than their own specific purpose - _vhdl_keywords = ["abs", "access", "after", "alias", "all", - "and", "architecture", "array", "assert", - "attribute", "begin", "block", "body", "buffer", - "bus", "case", "component", "configuration", - "constant", "disconnect", "downto", "else", - "elseif", "end", "entity", "exit", "file", "for", - "function", "generate", "generic", "group", - "guarded", "if", "impure", "in", "inertial", - "inout", "is", "label", "library", "linkage", - "literal", "loop", "map", "mod", "nand", "new", - "next", "nor", "not", "null", "of", "on", "open", - "or", "others", "out", "package", "port", - "postponed", "procedure", "process", "pure", - "range", "record", "register", "reject", "rem", - "report", "return", "rol", "ror", "select", - "severity", "signal", "shared", "sla", "sll", "sra", - "srl", "subtype", "then", "to", "transport", "type", - "unaffected", "units", "until", "use", "variable", - "wait", "when", "while", "with", "xnor", "xor"]; +#A list to hold all signal names being used in lowercase to raise an error +#if no names are reused with different casing +_usedNames = []; - #A list to hold all signal names being used in lowercase to raise an error - #if no names are reused with different casing - _usedNames = []; - - #Function which compares current parsed signal/entity to all keywords to - #ensure reserved words are not being used for the wrong purpose - def _nameValid(name): - for keyword in _nameCheck._vhdl_keywords: - if name == keyword: - warnings.warn("VHDL keyword used: %s" % name, category=ToVHDLWarning) - for saved_name in _nameCheck._usedNames: - if name.lower() == saved_name: - warnings.warn("Previously used name being reused: %s" % name, category=ToVHDLWarning) - _nameCheck._usedNames.append(name).lower - if name[0] == '_': - warnings.warn("VHDL variable names cannot contain '_': %s" % name, category=ToVHDLWarning) - for char in name: - if char == '-': - warnings.warn("VHDL variable names cannot contain '-': %s" % name, category=ToVHDLWarning) +#Function which compares current parsed signal/entity to all keywords to +#ensure reserved words are not being used for the wrong purpose +def _nameValid(name): + for keyword in _vhdl_keywords: + if name == keyword: + warnings.warn("VHDL keyword used: %s" % name, category=ToVHDLWarning) + for saved_name in _usedNames: + if name.lower() == saved_name: + warnings.warn("Previously used name being reused: %s" % name, category=ToVHDLWarning) + _usedNames.append(name).lower + if name[0] == '_': + warnings.warn("VHDL variable names cannot contain '_': %s" % name, category=ToVHDLWarning) + for char in name: + if char == '-': + warnings.warn("VHDL variable names cannot contain '-': %s" % name, category=ToVHDLWarning) diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py index 7d92d85f0..f66fc53ed 100644 --- a/myhdl/conversion/_toVHDL.py +++ b/myhdl/conversion/_toVHDL.py @@ -55,7 +55,7 @@ from myhdl._util import _flatten from myhdl._compat import integer_types, class_types, StringIO from myhdl._ShadowSignal import _TristateSignal, _TristateDriver -from myhdl.conversion._VHDLNameValidation import _nameCheck +import myhdl.conversion._VHDLNameValidation from myhdl._block import _Block From 7f31b570f7d3cc503219b856b130fe2c8f3fec73 Mon Sep 17 00:00:00 2001 From: Patrick Egan Date: Thu, 1 Sep 2016 23:57:03 -0400 Subject: [PATCH 10/12] Fixed _VHDLNameValidation.py method calls in _toVHDL.py --- myhdl/conversion/_toVHDL.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py index f66fc53ed..980ad4bb3 100644 --- a/myhdl/conversion/_toVHDL.py +++ b/myhdl/conversion/_toVHDL.py @@ -354,7 +354,7 @@ def _writeModuleHeader(f, intf, needPck, lib, arch, useClauses, doc, stdLogicPor if convertPort: pt = "std_logic_vector" # Check if VHDL keyword or reused name - _nameCheck._nameValid(s) + _VHDLNameValidation._nameValid(s) if s._driven: if s._read: if not isinstance(s, _TristateSignal): @@ -419,7 +419,7 @@ def _writeSigDecls(f, intf, siglist, memlist): print("signal %s: %s%s;" % (s._name, p, r), file=f) elif s._read: # Check if VHDL keyword or reused name - _nameCheck._nameValid(s) + _VHDLNameValidation._nameValid(s) # the original exception # raise ToVHDLError(_error.UndrivenSignal, s._name) # changed to a warning and a continuous assignment to a wire @@ -440,7 +440,7 @@ def _writeSigDecls(f, intf, siglist, memlist): if not m._driven and not m._read: continue # Check if VHDL keyword or reused name - _nameCheck._nameValid(m) + _VHDLNameValidation._nameValid(m) r = _getRangeString(m.elObj) p = _getTypeString(m.elObj) t = "t_array_%s" % m.name From 0d6a5d78d0fdb273ab0c355463f0a17eeb74f3c0 Mon Sep 17 00:00:00 2001 From: Patrick Egan Date: Fri, 2 Sep 2016 15:45:03 -0400 Subject: [PATCH 11/12] made import statement in _toVHDL.py more specific and fixed warning in _VHDLNameValidation --- myhdl/conversion/_VHDLNameValidation.py | 11 ++++++----- myhdl/conversion/_toVHDL.py | 8 ++++---- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/myhdl/conversion/_VHDLNameValidation.py b/myhdl/conversion/_VHDLNameValidation.py index e8e27f771..28ab471ad 100644 --- a/myhdl/conversion/_VHDLNameValidation.py +++ b/myhdl/conversion/_VHDLNameValidation.py @@ -1,5 +1,6 @@ import warnings from myhdl import * +from myhdl import ToVHDLWarning from myhdl.conversion import _analyze import pytest @@ -34,13 +35,13 @@ def _nameValid(name): for keyword in _vhdl_keywords: if name == keyword: - warnings.warn("VHDL keyword used: %s" % name, category=ToVHDLWarning) + warnings.warn("VHDL keyword used: %s" % (name), category=ToVHDLWarning) for saved_name in _usedNames: if name.lower() == saved_name: - warnings.warn("Previously used name being reused: %s" % name, category=ToVHDLWarning) - _usedNames.append(name).lower + warnings.warn("Previously used name being reused: %s" % (name), category=ToVHDLWarning) + _usedNames.append(name.lower()) if name[0] == '_': - warnings.warn("VHDL variable names cannot contain '_': %s" % name, category=ToVHDLWarning) + warnings.warn("VHDL variable names cannot contain '_': %s" % (name), category=ToVHDLWarning) for char in name: if char == '-': - warnings.warn("VHDL variable names cannot contain '-': %s" % name, category=ToVHDLWarning) + warnings.warn("VHDL variable names cannot contain '-': %s" % (name), category=ToVHDLWarning) diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py index 980ad4bb3..4b734ec28 100644 --- a/myhdl/conversion/_toVHDL.py +++ b/myhdl/conversion/_toVHDL.py @@ -55,7 +55,7 @@ from myhdl._util import _flatten from myhdl._compat import integer_types, class_types, StringIO from myhdl._ShadowSignal import _TristateSignal, _TristateDriver -import myhdl.conversion._VHDLNameValidation +from myhdl.conversion._VHDLNameValidation import _nameValid from myhdl._block import _Block @@ -354,7 +354,7 @@ def _writeModuleHeader(f, intf, needPck, lib, arch, useClauses, doc, stdLogicPor if convertPort: pt = "std_logic_vector" # Check if VHDL keyword or reused name - _VHDLNameValidation._nameValid(s) + _nameValid(s) if s._driven: if s._read: if not isinstance(s, _TristateSignal): @@ -419,7 +419,7 @@ def _writeSigDecls(f, intf, siglist, memlist): print("signal %s: %s%s;" % (s._name, p, r), file=f) elif s._read: # Check if VHDL keyword or reused name - _VHDLNameValidation._nameValid(s) + _nameValid(s) # the original exception # raise ToVHDLError(_error.UndrivenSignal, s._name) # changed to a warning and a continuous assignment to a wire @@ -440,7 +440,7 @@ def _writeSigDecls(f, intf, siglist, memlist): if not m._driven and not m._read: continue # Check if VHDL keyword or reused name - _VHDLNameValidation._nameValid(m) + _nameValid(m) r = _getRangeString(m.elObj) p = _getTypeString(m.elObj) t = "t_array_%s" % m.name From 62e1fb9a54bf843cea1eaaa486efb71a3baeeafb Mon Sep 17 00:00:00 2001 From: Patrick Egan Date: Fri, 2 Sep 2016 17:30:38 -0400 Subject: [PATCH 12/12] Fixed object being passed to _nameValidate --- myhdl/conversion/_toVHDL.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py index 4b734ec28..37bda8d87 100644 --- a/myhdl/conversion/_toVHDL.py +++ b/myhdl/conversion/_toVHDL.py @@ -354,7 +354,7 @@ def _writeModuleHeader(f, intf, needPck, lib, arch, useClauses, doc, stdLogicPor if convertPort: pt = "std_logic_vector" # Check if VHDL keyword or reused name - _nameValid(s) + _nameValid(s._name) if s._driven: if s._read: if not isinstance(s, _TristateSignal): @@ -419,7 +419,7 @@ def _writeSigDecls(f, intf, siglist, memlist): print("signal %s: %s%s;" % (s._name, p, r), file=f) elif s._read: # Check if VHDL keyword or reused name - _nameValid(s) + _nameValid(s._name) # the original exception # raise ToVHDLError(_error.UndrivenSignal, s._name) # changed to a warning and a continuous assignment to a wire @@ -440,7 +440,7 @@ def _writeSigDecls(f, intf, siglist, memlist): if not m._driven and not m._read: continue # Check if VHDL keyword or reused name - _nameValid(m) + _nameValid(m.name) r = _getRangeString(m.elObj) p = _getTypeString(m.elObj) t = "t_array_%s" % m.name