diff --git a/bittide-instances/src/Bittide/Instances/Hitl/VexRiscv.hs b/bittide-instances/src/Bittide/Instances/Hitl/VexRiscv.hs
index 64d043fa0..bcb705d6f 100644
--- a/bittide-instances/src/Bittide/Instances/Hitl/VexRiscv.hs
+++ b/bittide-instances/src/Bittide/Instances/Hitl/VexRiscv.hs
@@ -97,7 +97,7 @@ vexRiscvInner jtagIn0 uartRx =
     [timeBus, uartBus, statusRegisterBus] <- processingElement NoDumpVcd peConfig -< jtag
     (uartTx, _uartStatus) <-
       uartInterfaceWb @dom d16 d16 (uartDf baud) -< (uartBus, uartRx)
-    timeWb -< timeBus
+    _localCounter <- timeWb -< timeBus
     testResult <- statusRegister -< statusRegisterBus
     idC -< (testResult, uartTx)
 
diff --git a/bittide-instances/src/Bittide/Instances/Pnr/Ethernet.hs b/bittide-instances/src/Bittide/Instances/Pnr/Ethernet.hs
index 81ac92223..1bfe58210 100644
--- a/bittide-instances/src/Bittide/Instances/Pnr/Ethernet.hs
+++ b/bittide-instances/src/Bittide/Instances/Pnr/Ethernet.hs
@@ -100,7 +100,7 @@ vexRiscGmii SNat sysClk sysRst rxClk rxRst txClk txRst fwd =
       ( circuit $ \(uartTx, gmiiRx, jtag) -> do
           [uartBus, timeBus, wbAxiRx, wbAxiTx, dnaWb, gpioWb, macWb] <- pe -< jtag
           (uartRx, _uartStatus) <- uart -< (uartBus, uartTx)
-          time -< timeBus
+          _localCounter <- time -< timeBus
           _dna <- dnaC -< dnaWb
           macStatIf -< (macWb, macStatus)
           gpioDf <- idleSource -< ()
diff --git a/bittide-instances/src/Bittide/Instances/Pnr/ProcessingElement.hs b/bittide-instances/src/Bittide/Instances/Pnr/ProcessingElement.hs
index b28b80b9d..9c023c5fe 100644
--- a/bittide-instances/src/Bittide/Instances/Pnr/ProcessingElement.hs
+++ b/bittide-instances/src/Bittide/Instances/Pnr/ProcessingElement.hs
@@ -50,7 +50,7 @@ vexRiscUartHello diffClk rst_in =
       [uartBus, timeBus] <- processingElement @Basic200 NoDumpVcd peConfig -< jtag
       (uartTx, _uartStatus) <-
         uartInterfaceWb d16 d16 (uartDf $ SNat @921600) -< (uartBus, uartRx)
-      timeWb -< timeBus
+      _localCounter <- timeWb -< timeBus
       idC -< uartTx
  where
   (clk200, rst200_) = clockWizardDifferential diffClk noReset
diff --git a/bittide-instances/tests/Wishbone/SwitchDemoProcessingElement.hs b/bittide-instances/tests/Wishbone/SwitchDemoProcessingElement.hs
index 0f2b2ee49..5d27b70ad 100644
--- a/bittide-instances/tests/Wishbone/SwitchDemoProcessingElement.hs
+++ b/bittide-instances/tests/Wishbone/SwitchDemoProcessingElement.hs
@@ -90,7 +90,7 @@ dut localCounter dnaA dnaB = circuit $ do
   (uartRx, jtagIdle) <- idleSource -< ()
   [uartBus, timeBus, peBusA, peBusB] <- processingElement NoDumpVcd peConfig -< jtagIdle
   (uartTx, _uartStatus) <- uartInterfaceWb d16 d2 uartSim -< (uartBus, uartRx)
-  timeWb -< timeBus
+  _localCounter <- timeWb -< timeBus
   linkAB <- switchDemoPeWb d2 localCounter -< (peBusA, dnaAC, linkBA)
   linkBA <- switchDemoPeWb d2 localCounter -< (peBusB, dnaBC, linkAB)
   dnaAC <- signalToCSignal dnaA -< ()
diff --git a/bittide-instances/tests/Wishbone/Time.hs b/bittide-instances/tests/Wishbone/Time.hs
index 1b2ee1f61..2b4924c2c 100644
--- a/bittide-instances/tests/Wishbone/Time.hs
+++ b/bittide-instances/tests/Wishbone/Time.hs
@@ -70,7 +70,7 @@ dut = withClockResetEnable clockGen resetGen enableGen
     (uartRx, jtag) <- idleSource -< ()
     [uartBus, timeBus] <- processingElement NoDumpVcd peConfig -< jtag
     (uartTx, _uartStatus) <- uartInterfaceWb d2 d2 uartSim -< (uartBus, uartRx)
-    timeWb -< timeBus
+    _localCounter <- timeWb -< timeBus
     idC -< uartTx
  where
   (iMem, dMem) =
diff --git a/bittide-instances/tests/Wishbone/Watchdog.hs b/bittide-instances/tests/Wishbone/Watchdog.hs
index 0f9b9f474..5734934bd 100644
--- a/bittide-instances/tests/Wishbone/Watchdog.hs
+++ b/bittide-instances/tests/Wishbone/Watchdog.hs
@@ -67,7 +67,7 @@ dut = withClockResetEnable clockGen resetGen enableGen
       <| (watchDogWb @_ @_ @4 "50 us" (SNat @(PeriodToCycles Basic200 (Microseconds 50))))
       -< idleBusB
 
-    timeWb <| (watchDogWb @_ @_ @4 "" d0) -< timeBus
+    _localCounter <- timeWb <| (watchDogWb @_ @_ @4 "" d0) -< timeBus
     (uartTx, _uartStatus) <- (uartInterfaceWb @_ @_ @4) d2 d2 uartSim -< (uartBus, uartRx)
     idC -< uartTx
  where
diff --git a/bittide/src/Bittide/Wishbone.hs b/bittide/src/Bittide/Wishbone.hs
index d5d197b4e..5dc783712 100644
--- a/bittide/src/Bittide/Wishbone.hs
+++ b/bittide/src/Bittide/Wishbone.hs
@@ -578,11 +578,11 @@ timeWb ::
   , KnownNat addrW
   , 1 <= DomainPeriod dom
   ) =>
-  Circuit (Wishbone dom 'Standard addrW (Bytes 4)) ()
-timeWb = Circuit $ \(wbM2S, _) -> (mealy goMealy (False, 0, 0) wbM2S, ())
+  Circuit (Wishbone dom 'Standard addrW (Bytes 4)) (CSignal dom (Unsigned 64))
+timeWb = Circuit $ \(wbM2S, _) -> unbundle $ mealy goMealy (False, 0, 0) wbM2S
  where
   goMealy (reqCmp0, scratch0 :: Unsigned 64, count :: Unsigned 64) wbM2S =
-    ((reqCmp1, scratch1, succ count), wbS2M1)
+    ((reqCmp1, scratch1, succ count), (wbS2M1, count))
    where
     freq = natToNum @(DomainToHz dom) :: Unsigned 64
     RegisterBank (splitAtI -> (freqMsbs, freqLsbs)) = getRegsBe @8 freq