From a26b40256d91b8cffab312b234330568972b2a36 Mon Sep 17 00:00:00 2001
From: Ryan Slawson <ryan@qbaylogic.com>
Date: Fri, 21 Feb 2025 14:55:31 +0100
Subject: [PATCH] fixup! (DROPME) Fix up debugging ILA

---
 .../src/Bittide/Instances/Hitl/Demo.hs        | 39 +++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/bittide-instances/src/Bittide/Instances/Hitl/Demo.hs b/bittide-instances/src/Bittide/Instances/Hitl/Demo.hs
index bc1bd6070..5d7e3269c 100644
--- a/bittide-instances/src/Bittide/Instances/Hitl/Demo.hs
+++ b/bittide-instances/src/Bittide/Instances/Hitl/Demo.hs
@@ -58,6 +58,7 @@ import Clash.Cores.Xilinx.Ila (Depth (..), IlaConfig (..), ila, ilaConfig)
 import Clash.Cores.Xilinx.VIO (vioProbe)
 import Clash.Cores.Xilinx.Xpm.Cdc (xpmCdcArraySingle, xpmCdcSingle)
 import Clash.Functor.Extra ((<<$>>))
+import Clash.Sized.Extra (unsignedToSigned)
 import Clash.Xilinx.ClockGen (clockWizardDifferential)
 import Protocols
 import Protocols.Wishbone
@@ -206,6 +207,9 @@ dut refClk refRst skyClk rxNs rxPs allProgrammed miso jtagIn =
           :> "dd_ebReadys"
           -- Other
           :> "dd_transceiversFailedAfterUp"
+          :> "dd_nFincs"
+          :> "dd_nFdecs"
+          :> "dd_netFincs"
           :> Nil
       )
         { depth = D16384
@@ -220,6 +224,9 @@ dut refClk refRst skyClk rxNs rxPs allProgrammed miso jtagIn =
       allStable
       (bundle $ xpmCdcArraySingle bittideClk refClk <$> ebReadys)
       transceiversFailedAfterUp
+      nFincs
+      nFdecs
+      (fmap unsignedToSigned nFincs - fmap unsignedToSigned nFdecs)
 
   captureFlag =
     riseEvery
@@ -228,6 +235,38 @@ dut refClk refRst skyClk rxNs rxPs allProgrammed miso jtagIn =
       enableGen
       (SNat @(PeriodToCycles Basic125 (Milliseconds 1)))
 
+  nFincs :: Signal Basic125 (Unsigned 32)
+  nFincs =
+    regEn
+      refClk
+      refRst
+      enableGen
+      (0 :: Unsigned 32)
+      ( isFalling
+          refClk
+          refRst
+          enableGen
+          False
+          ((== Just SpeedUp) <$> callistoResult.maybeSpeedChangeC)
+      )
+      (satSucc SatBound <$> nFincs)
+
+  nFdecs :: Signal Basic125 (Unsigned 32)
+  nFdecs =
+    regEn
+      refClk
+      refRst
+      enableGen
+      (0 :: Unsigned 32)
+      ( isFalling
+          refClk
+          refRst
+          enableGen
+          False
+          ((== Just SlowDown) <$> callistoResult.maybeSpeedChangeC)
+      )
+      (satSucc SatBound <$> nFdecs)
+
   -- Step 1, wait for SPI:
   (_, _, spiState, spiOut) =
     withClockResetEnable refClk spiRst enableGen