From 2bfb98b845877f82aa93b54f10779c20cae12a7c Mon Sep 17 00:00:00 2001 From: Ryan Slawson Date: Tue, 4 Mar 2025 13:22:17 +0100 Subject: [PATCH] Add ILA for demo device Bittide domain PE. --- .../src/Bittide/Instances/Hitl/Demo.hs | 105 +++++++++++++++--- .../Wishbone/SwitchDemoProcessingElement.hs | 4 +- .../Bittide/SwitchDemoProcessingElement.hs | 19 ++-- .../Tests/SwitchDemoProcessingElement.hs | 1 + 4 files changed, 102 insertions(+), 27 deletions(-) diff --git a/bittide-instances/src/Bittide/Instances/Hitl/Demo.hs b/bittide-instances/src/Bittide/Instances/Hitl/Demo.hs index 4c6c40ae2..cb7a251b0 100644 --- a/bittide-instances/src/Bittide/Instances/Hitl/Demo.hs +++ b/bittide-instances/src/Bittide/Instances/Hitl/Demo.hs @@ -52,7 +52,7 @@ import Bittide.Jtag (jtagChain, unsafeJtagSynchronizer) import Bittide.ProcessingElement (PeConfig (..), processingElement, splitAtC) import Bittide.SharedTypes (Bytes) import Bittide.Switch (switchC) -import Bittide.SwitchDemoProcessingElement (switchDemoPeWb) +import Bittide.SwitchDemoProcessingElement (SimplePeState (Idle), switchDemoPeWb) import Bittide.Transceiver (transceiverPrbsN) import Bittide.Wishbone (readDnaPortE2Wb, timeWb, whoAmIC) @@ -231,18 +231,20 @@ dut :: dut refClk refRst skyClk rxNs rxPs allProgrammed miso jtagIn = hwSeqX debugIla - ( transceivers.txNs - , transceivers.txPs - , handshakesCompleteFree - , frequencyAdjustments - , spiDone - , spiOut - , jtagOut - , transceiversFailedAfterUp - , allStable - , fifoOverflowsSticky - , fifoUnderflowsSticky - ) + hwSeqX + bittidePeIla + ( transceivers.txNs + , transceivers.txPs + , handshakesCompleteFree + , frequencyAdjustments + , spiDone + , spiOut + , jtagOut + , transceiversFailedAfterUp + , allStable + , fifoOverflowsSticky + , fifoUnderflowsSticky + ) where debugIla :: Signal Basic125 () debugIla = @@ -467,6 +469,9 @@ dut refClk refRst skyClk rxNs rxPs allProgrammed miso jtagIn = , ( Signal Basic125 () , Vec LinkCount (Signal GthTx ()) , Signal GthTx () + , Signal GthTx () + , Signal GthTx () + , Signal GthTx () ) ) -> ( ( Signal Basic125 JtagOut @@ -479,6 +484,9 @@ dut refClk refRst skyClk rxNs rxPs allProgrammed miso jtagIn = , ( Signal Basic125 (CallistoCResult LinkCount) , Vec LinkCount (Signal GthTx (BitVector 64)) , Signal GthTx (Unsigned 64) + , Signal GthTx (SimplePeState FpgaCount) + , Signal GthTx (BitVector 64) + , Signal GthTx (BitVector 64) ) ) Circuit circuitFn = circuit $ \(jtag, linkIn, reframe, mask, dc, [rx0, rx1, rx2, rx3, rx4, rx5, rx6]) -> do @@ -517,15 +525,17 @@ dut refClk refRst skyClk rxNs rxPs allProgrammed miso jtagIn = enableGen switchC calendarConfig - -< ([peOut, urx0, urx1, urx2, urx3, urx4, urx5, urx6], switchWb) + -< ([peOut0, urx0, urx1, urx2, urx3, urx4, urx5, urx6], switchWb) + [peIn0, peIn1] <- fanoutC -< peIn - peOut <- + (peOut, ps) <- -- CDC this too withClockResetEnable bittideClk handshakeRstTx enableGen (switchDemoPeWb (SNat @FpgaCount)) - -< (lc7, peWb, dna, peIn) + -< (lc7, peWb, dna, peIn0) -- CDC all of these + [peOut0, peOut1] <- fanoutC -< peOut dna <- withClockResetEnable @@ -557,10 +567,10 @@ dut refClk refRst skyClk rxNs rxPs allProgrammed miso jtagIn = (whoAmIC 0x6363_7773) -< ccWhoAmI - idC -< (swCcOut, [tx0, tx1, tx2, tx3, tx4, tx5, tx6], lc8) + idC -< (swCcOut, [tx0, tx1, tx2, tx3, tx4, tx5, tx6], lc8, ps, peIn1, peOut1) ( (jtagOut, _linkInBwd, _reframingBwd, _maskBwd, _diffsBwd, _insBwd) - , (callistoResult, switchDataOut, localCounter) + , (callistoResult, switchDataOut, localCounter, peState, peInput, peOutput) ) = circuitFn ( @@ -575,9 +585,68 @@ dut refClk refRst skyClk rxNs rxPs allProgrammed miso jtagIn = ( pure () , repeat (pure ()) , pure () + , pure () + , pure () + , pure () ) ) + peNotIdle :: Signal GthTx Bool + peNotIdle = (/= Idle) <$> peState + peNotIdleSticky :: Signal GthTx Bool + peNotIdleSticky = sticky bittideClk handshakeRstTx peNotIdle + peNotIdleStickyFree :: Signal Basic125 Bool + peNotIdleStickyFree = xpmCdcSingle bittideClk refClk peNotIdleSticky + + bittidePeIla :: Signal Basic125 () + bittidePeIla = + setName @"bittidePeIla" + ila + ( ilaConfig + $ "triger_fdi_pe" + :> "capture_fdi_pe" + :> "pe_input" + :> "pe_state" + :> "pe_output" + :> "pe_rx_0" + :> "pe_rx_1" + :> "pe_rx_2" + :> "pe_rx_3" + :> "pe_rx_4" + :> "pe_rx_5" + :> "pe_rx_6" + :> "pe_tx_0" + :> "pe_tx_1" + :> "pe_tx_2" + :> "pe_tx_3" + :> "pe_tx_4" + :> "pe_tx_5" + :> "pe_tx_6" + :> Nil + ) + { depth = D4096 + } + refClk + peNotIdleStickyFree + (pure True :: Signal Basic125 Bool) + (xpmCdcArraySingle bittideClk refClk peInput) + (pack <$> xpmCdcArraySingle bittideClk refClk peState) + (xpmCdcArraySingle bittideClk refClk peOutput) + (xpmCdcArraySingle bittideClk refClk (rxDatasEbs !! (0 :: Index LinkCount))) + (xpmCdcArraySingle bittideClk refClk (rxDatasEbs !! (1 :: Index LinkCount))) + (xpmCdcArraySingle bittideClk refClk (rxDatasEbs !! (2 :: Index LinkCount))) + (xpmCdcArraySingle bittideClk refClk (rxDatasEbs !! (3 :: Index LinkCount))) + (xpmCdcArraySingle bittideClk refClk (rxDatasEbs !! (4 :: Index LinkCount))) + (xpmCdcArraySingle bittideClk refClk (rxDatasEbs !! (5 :: Index LinkCount))) + (xpmCdcArraySingle bittideClk refClk (rxDatasEbs !! (6 :: Index LinkCount))) + (xpmCdcArraySingle bittideClk refClk (switchDataOut !! (0 :: Index LinkCount))) + (xpmCdcArraySingle bittideClk refClk (switchDataOut !! (1 :: Index LinkCount))) + (xpmCdcArraySingle bittideClk refClk (switchDataOut !! (2 :: Index LinkCount))) + (xpmCdcArraySingle bittideClk refClk (switchDataOut !! (3 :: Index LinkCount))) + (xpmCdcArraySingle bittideClk refClk (switchDataOut !! (4 :: Index LinkCount))) + (xpmCdcArraySingle bittideClk refClk (switchDataOut !! (5 :: Index LinkCount))) + (xpmCdcArraySingle bittideClk refClk (switchDataOut !! (6 :: Index LinkCount))) + frequencyAdjustments :: Signal Basic125 (FINC, FDEC) frequencyAdjustments = delay refClk enableGen minBound diff --git a/bittide-instances/tests/Wishbone/SwitchDemoProcessingElement.hs b/bittide-instances/tests/Wishbone/SwitchDemoProcessingElement.hs index bc823204f..18d95bea5 100644 --- a/bittide-instances/tests/Wishbone/SwitchDemoProcessingElement.hs +++ b/bittide-instances/tests/Wishbone/SwitchDemoProcessingElement.hs @@ -91,8 +91,8 @@ dut localCounter dnaA dnaB = circuit $ do [uartBus, timeBus, peBusA, peBusB] <- processingElement NoDumpVcd peConfig -< jtagIdle (uartTx, _uartStatus) <- uartInterfaceWb d16 d2 uartSim -< (uartBus, uartRx) _localCounter <- timeWb -< timeBus -- todo: use this counter instead of the external one - linkAB <- switchDemoPeWb d2 -< (Fwd localCounter, peBusA, dnaAC, linkBA) - linkBA <- switchDemoPeWb d2 -< (Fwd localCounter, peBusB, dnaBC, linkAB) + (linkAB, _stateAB) <- switchDemoPeWb d2 -< (Fwd localCounter, peBusA, dnaAC, linkBA) + (linkBA, _stateBA) <- switchDemoPeWb d2 -< (Fwd localCounter, peBusB, dnaBC, linkAB) dnaAC <- signalToCSignal dnaA -< () dnaBC <- signalToCSignal dnaB -< () idC -< uartTx diff --git a/bittide/src/Bittide/SwitchDemoProcessingElement.hs b/bittide/src/Bittide/SwitchDemoProcessingElement.hs index efe5eb5bc..4e03a4c2f 100644 --- a/bittide/src/Bittide/SwitchDemoProcessingElement.hs +++ b/bittide/src/Bittide/SwitchDemoProcessingElement.hs @@ -52,9 +52,11 @@ switchDemoPe :: Signal dom (BitVector 64) , -- \| Buffer output Signal dom (Vec (bufferSize * 3) (BitVector 64)) + , -- \| Current state + Signal dom (SimplePeState bufferSize) ) switchDemoPe SNat localCounter linkIn dna readStart readCycles writeStart writeCycles = - (linkOut, buffer) + (linkOut, buffer, peState) where readCyclesExtended = checkedResize . zeroExtendTimesThree <$> readCycles writeCyclesExtended = zeroExtendTimesThree <$> writeCycles @@ -71,7 +73,7 @@ switchDemoPe SNat localCounter linkIn dna readStart readCycles writeStart writeC SimplePeState bufferSize -> Vec (bufferSize * 3) (BitVector 64) -> Vec 3 (BitVector 64) -> - BitVector 64 + BitVector 64 -- also output boolean? stateToLinkOutput state buf locData = case state of Write i @@ -138,7 +140,7 @@ data SimplePeState bufferSize = Idle | Read (Index (bufferSize * 3 + 1)) | Write (Index ((bufferSize + 1) * 3)) - deriving (Generic, NFDataX, Eq, Show) + deriving (Generic, NFDataX, Eq, Show, BitPack) {- | Wishbone circuit wrapper for `switchDemoPe`. @@ -168,11 +170,14 @@ switchDemoPeWb :: , -- \| Incoming crossbar link CSignal dom (BitVector 64) ) - -- \| Outgoing crossbar link - (CSignal dom (BitVector 64)) + ( -- \| Outgoing crossbar link + CSignal dom (BitVector 64) + , -- \| Current state + CSignal dom (SimplePeState bufferSize) + ) switchDemoPeWb SNat = Circuit go where - go ((localCounter, wbM2S, dna, linkIn), _) = ((pure (), wbS2M, pure (), pure ()), linkOut) + go ((localCounter, wbM2S, dna, linkIn), _) = ((pure (), wbS2M, pure (), pure ()), (linkOut, state)) where readVec :: Vec (8 + bufferSize * 3 * 2 + 2) (Signal dom (BitVector 32)) readVec = @@ -182,7 +187,7 @@ switchDemoPeWb SNat = Circuit go ++ unbundle (bitCoerce . map swapWords <$> buffer) ) - (linkOut, buffer) = + (linkOut, buffer, state) = switchDemoPe (SNat @bufferSize) localCounter diff --git a/bittide/tests/Tests/SwitchDemoProcessingElement.hs b/bittide/tests/Tests/SwitchDemoProcessingElement.hs index 1e095852f..319c3ae32 100644 --- a/bittide/tests/Tests/SwitchDemoProcessingElement.hs +++ b/bittide/tests/Tests/SwitchDemoProcessingElement.hs @@ -123,6 +123,7 @@ prop_readThenWrite = H.property $ do E.sample $ bundle $ withClockResetEnable @System clockGen noReset enableGen + $ (\(a, b, _) -> (a, b)) $ switchDemoPe bufferSizeSNat (fromList [clockStart ..])