diff --git a/compiler/src/passes/assign/assign.rs b/compiler/src/passes/assign/assign.rs
index 892c313..bdcb8a3 100644
--- a/compiler/src/passes/assign/assign.rs
+++ b/compiler/src/passes/assign/assign.rs
@@ -53,7 +53,7 @@ fn assign_instr<'p>(
     let map = |arg: VarArg<UniqueSym<'p>>| -> Arg {
         match arg {
             VarArg::Imm(imm) => Arg::Imm(imm),
-            VarArg::Reg { reg } => Arg::Reg { reg },
+            VarArg::Reg(reg) => Arg::Reg(reg),
             VarArg::Deref { reg, off } => Arg::Deref { reg, off },
             VarArg::XVar { sym } => color_map[&sym].clone(),
         }
diff --git a/compiler/src/passes/assign/color_interference.rs b/compiler/src/passes/assign/color_interference.rs
index e3d4e42..235a031 100644
--- a/compiler/src/passes/assign/color_interference.rs
+++ b/compiler/src/passes/assign/color_interference.rs
@@ -84,22 +84,22 @@ impl<'p> InterferenceGraph<'p> {
 
 fn arg_from_color(i: isize) -> Arg {
     match i {
-        -5 => Arg::Reg { reg: Reg::R15 },
-        -4 => Arg::Reg { reg: Reg::R11 },
-        -3 => Arg::Reg { reg: Reg::RBP },
-        -2 => Arg::Reg { reg: Reg::RSP },
-        -1 => Arg::Reg { reg: Reg::RAX },
-        0 => Arg::Reg { reg: Reg::RCX },
-        1 => Arg::Reg { reg: Reg::RDX },
-        2 => Arg::Reg { reg: Reg::RSI },
-        3 => Arg::Reg { reg: Reg::RDI },
-        4 => Arg::Reg { reg: Reg::R8 },
-        5 => Arg::Reg { reg: Reg::R9 },
-        6 => Arg::Reg { reg: Reg::R10 },
-        7 => Arg::Reg { reg: Reg::RBX },
-        8 => Arg::Reg { reg: Reg::R12 },
-        9 => Arg::Reg { reg: Reg::R13 },
-        10 => Arg::Reg { reg: Reg::R14 },
+        -5 => Arg::Reg(Reg::R15),
+        -4 => Arg::Reg(Reg::R11),
+        -3 => Arg::Reg(Reg::RBP),
+        -2 => Arg::Reg(Reg::RSP),
+        -1 => Arg::Reg(Reg::RAX),
+        0 => Arg::Reg(Reg::RCX),
+        1 => Arg::Reg(Reg::RDX),
+        2 => Arg::Reg(Reg::RSI),
+        3 => Arg::Reg(Reg::RDI),
+        4 => Arg::Reg(Reg::R8),
+        5 => Arg::Reg(Reg::R9),
+        6 => Arg::Reg(Reg::R10),
+        7 => Arg::Reg(Reg::RBX),
+        8 => Arg::Reg(Reg::R12),
+        9 => Arg::Reg(Reg::R13),
+        10 => Arg::Reg(Reg::R14),
         i => {
             assert!(
                 i > 10,
diff --git a/compiler/src/passes/assign/compute_interference.rs b/compiler/src/passes/assign/compute_interference.rs
index 4e34a2c..842afb0 100644
--- a/compiler/src/passes/assign/compute_interference.rs
+++ b/compiler/src/passes/assign/compute_interference.rs
@@ -15,7 +15,7 @@ impl<'p> LFun<'p> {
                 //TODO move optimization: If instruction is a move instruction then for every in w in writes, if w != dst and v != src, add the edge (dst, w).
                 handle_instr(instr, &HashMap::new(), |arg, op| {
                     let w = match (arg, op) {
-                        (VarArg::Reg { reg }, ReadWriteOp::Write | ReadWriteOp::ReadWrite) => {
+                        (VarArg::Reg(reg), ReadWriteOp::Write | ReadWriteOp::ReadWrite) => {
                             LArg::Reg { reg: *reg }
                         }
                         (VarArg::XVar { sym }, ReadWriteOp::Write | ReadWriteOp::ReadWrite) => {
diff --git a/compiler/src/passes/assign/include_liveness.rs b/compiler/src/passes/assign/include_liveness.rs
index fc5a298..a6d117f 100644
--- a/compiler/src/passes/assign/include_liveness.rs
+++ b/compiler/src/passes/assign/include_liveness.rs
@@ -79,10 +79,10 @@ fn block_liveness<'p>(
 
         handle_instr(instr, before_map, |arg, op| match (arg, op) {
             (VarArg::Imm { .. }, _) => {}
-            (VarArg::Reg { reg }, ReadWriteOp::Read | ReadWriteOp::ReadWrite) => {
+            (VarArg::Reg(reg), ReadWriteOp::Read | ReadWriteOp::ReadWrite) => {
                 live.insert(LArg::Reg { reg: *reg });
             }
-            (VarArg::Reg { reg }, ReadWriteOp::Write) => {
+            (VarArg::Reg(reg), ReadWriteOp::Write) => {
                 live.remove(&LArg::Reg { reg: *reg });
             }
             (VarArg::XVar { sym }, ReadWriteOp::Read | ReadWriteOp::ReadWrite) => {
@@ -146,35 +146,35 @@ pub fn handle_instr<'p>(
         }
         Instr::CallqDirect { arity, .. } => {
             for reg in CALLER_SAVED.into_iter().skip(*arity) {
-                arg(&VarArg::Reg { reg }, W);
+                arg(&VarArg::Reg(reg), W);
             }
             for reg in CALLER_SAVED.into_iter().take(*arity) {
-                arg(&VarArg::Reg { reg }, RW);
+                arg(&VarArg::Reg(reg), RW);
             }
         }
         Instr::Syscall { arity } => {
             for reg in CALLER_SAVED {
-                arg(&VarArg::Reg { reg }, W);
+                arg(&VarArg::Reg(reg), W);
             }
             for reg in SYSCALL_REGS.into_iter().take(*arity) {
-                arg(&VarArg::Reg { reg }, R);
+                arg(&VarArg::Reg(reg), R);
             }
         }
         Instr::Retq => {
             // Because the return value of our function is in RAX, we need to consider it being read at the end of a block.
-            arg(&VarArg::Reg { reg: Reg::RAX }, R);
+            arg(&VarArg::Reg(Reg::RAX), R);
         }
         Instr::Setcc { .. } => {
-            arg(&VarArg::Reg { reg: Reg::RAX }, W);
+            arg(&VarArg::Reg(Reg::RAX), W);
         }
         Instr::Mulq { src } => {
-            arg(&VarArg::Reg { reg: Reg::RDX }, W);
-            arg(&VarArg::Reg { reg: Reg::RAX }, RW);
+            arg(&VarArg::Reg(Reg::RDX), W);
+            arg(&VarArg::Reg(Reg::RAX), RW);
             arg(src, R);
         }
         Instr::Divq { divisor } => {
-            arg(&VarArg::Reg { reg: Reg::RDX }, RW);
-            arg(&VarArg::Reg { reg: Reg::RAX }, RW);
+            arg(&VarArg::Reg(Reg::RDX), RW);
+            arg(&VarArg::Reg(Reg::RAX), RW);
             arg(divisor, R);
         }
         Instr::Jmp { lbl } | Instr::Jcc { lbl, .. } => {
@@ -187,10 +187,10 @@ pub fn handle_instr<'p>(
         }
         Instr::CallqIndirect { src, arity } => {
             for reg in CALLER_SAVED.into_iter().skip(*arity) {
-                arg(&VarArg::Reg { reg }, W);
+                arg(&VarArg::Reg(reg), W);
             }
             for reg in CALLER_SAVED.into_iter().take(*arity) {
-                arg(&VarArg::Reg { reg }, RW);
+                arg(&VarArg::Reg(reg), RW);
             }
             arg(src, R);
         }
diff --git a/compiler/src/passes/assign/mod.rs b/compiler/src/passes/assign/mod.rs
index f9e835a..789973b 100644
--- a/compiler/src/passes/assign/mod.rs
+++ b/compiler/src/passes/assign/mod.rs
@@ -31,8 +31,8 @@ pub type InstrAssigned<'p> = Instr<Arg, UniqueSym<'p>>;
 pub enum Arg {
     #[display(fmt = "${_0}")]
     Imm(Imm),
-    #[display(fmt = "%{reg}")]
-    Reg { reg: Reg },
+    #[display(fmt = "%{_0}")]
+    Reg(Reg),
     #[display(fmt = "[%{reg} + ${off}]")]
     Deref { reg: Reg, off: i64 },
 }
@@ -65,7 +65,7 @@ impl<'p> From<LArg<'p>> for VarArg<UniqueSym<'p>> {
     fn from(val: LArg<'p>) -> Self {
         match val {
             LArg::Var { sym } => VarArg::XVar { sym },
-            LArg::Reg { reg } => VarArg::Reg { reg },
+            LArg::Reg { reg } => VarArg::Reg(reg),
         }
     }
 }
@@ -82,7 +82,7 @@ impl<'p> From<Arg> for VarArg<UniqueSym<'p>> {
     fn from(value: Arg) -> Self {
         match value {
             Arg::Imm(imm) => VarArg::Imm(imm),
-            Arg::Reg { reg } => VarArg::Reg { reg },
+            Arg::Reg(reg) => VarArg::Reg(reg),
             Arg::Deref { reg, off } => VarArg::Deref { reg, off },
         }
     }
diff --git a/compiler/src/passes/emit/binary.rs b/compiler/src/passes/emit/binary.rs
index c9c411c..75c08bd 100644
--- a/compiler/src/passes/emit/binary.rs
+++ b/compiler/src/passes/emit/binary.rs
@@ -64,7 +64,7 @@ pub const MOVQ_INFO: BinaryOpInfo = BinaryOpInfo {
 
 pub fn encode_binary_instr(op_info: BinaryOpInfo, src: &Arg, dst: &Arg) -> Vec<u8> {
     match (src, dst) {
-        (Arg::Reg { reg: src }, Arg::Reg { reg: dst }) => {
+        (Arg::Reg(src), Arg::Reg(dst)) => {
             let (s, sss) = encode_reg(src);
             let (d, ddd) = encode_reg(dst);
             vec![
@@ -73,7 +73,7 @@ pub fn encode_binary_instr(op_info: BinaryOpInfo, src: &Arg, dst: &Arg) -> Vec<u
                 0b11_000_000 | sss << 3 | ddd,
             ]
         }
-        (Arg::Deref { reg: src, off }, Arg::Reg { reg: dst }) => {
+        (Arg::Deref { reg: src, off }, Arg::Reg(dst)) => {
             let (s, sss) = encode_reg(src);
             let (d, ddd) = encode_reg(dst);
             let off = *off as i32;
@@ -89,7 +89,7 @@ pub fn encode_binary_instr(op_info: BinaryOpInfo, src: &Arg, dst: &Arg) -> Vec<u
             v.extend(off.to_le_bytes());
             v
         }
-        (Arg::Reg { reg: src }, Arg::Deref { reg: dst, off }) => {
+        (Arg::Reg(src), Arg::Deref { reg: dst, off }) => {
             let (s, sss) = encode_reg(src);
             let (d, ddd) = encode_reg(dst);
             let off = *off as i32;
@@ -105,7 +105,7 @@ pub fn encode_binary_instr(op_info: BinaryOpInfo, src: &Arg, dst: &Arg) -> Vec<u
             v.extend(off.to_le_bytes());
             v
         }
-        (Arg::Imm(imm), Arg::Reg { reg: dst }) => match imm {
+        (Arg::Imm(imm), Arg::Reg(dst)) => match imm {
             Imm::Imm8(_) => todo!(),
             Imm::Imm16(_) => todo!(),
             Imm::Imm32(imm) => {
diff --git a/compiler/src/passes/emit/mul_div.rs b/compiler/src/passes/emit/mul_div.rs
index 61639bf..eb7070d 100644
--- a/compiler/src/passes/emit/mul_div.rs
+++ b/compiler/src/passes/emit/mul_div.rs
@@ -8,8 +8,8 @@ pub struct MulDivOpInfo {
 
 pub fn encode_muldiv_instr(op_info: MulDivOpInfo, reg: &Arg) -> Vec<u8> {
     match reg {
-        Arg::Imm { .. } => todo!(),
-        Arg::Reg { reg } => {
+        Arg::Imm(..) => todo!(),
+        Arg::Reg(reg) => {
             let (d, ddd) = encode_reg(reg);
             vec![
                 0b0100_1000 | d,
diff --git a/compiler/src/passes/emit/push_pop.rs b/compiler/src/passes/emit/push_pop.rs
index 949c4a9..baac639 100644
--- a/compiler/src/passes/emit/push_pop.rs
+++ b/compiler/src/passes/emit/push_pop.rs
@@ -35,7 +35,7 @@ pub fn encode_push_pop(op_info: PushPopInfo, reg: &Arg) -> Vec<u8> {
             }
             Imm::Imm64(_) => todo!(),
         },
-        Arg::Reg { reg } => {
+        Arg::Reg(reg) => {
             let (r, rrr) = emit::encode_reg(reg);
             if r == 0 {
                 vec![op_info.op_reg | rrr]
diff --git a/compiler/src/passes/emit/unary.rs b/compiler/src/passes/emit/unary.rs
index 68857d6..8656079 100644
--- a/compiler/src/passes/emit/unary.rs
+++ b/compiler/src/passes/emit/unary.rs
@@ -13,7 +13,7 @@ pub const CALLQ_INDIRECT_INFO: UnaryOpInfo = UnaryOpInfo { op: 0xFF, pad: 0x2 };
 
 pub fn encode_unary_instr(op_info: UnaryOpInfo, dst: &Arg) -> Vec<u8> {
     match dst {
-        Arg::Reg { reg: dst } => {
+        Arg::Reg(dst) => {
             // use: REX.W + opcode /r
             let (d, ddd) = emit::encode_reg(dst);
             vec![
diff --git a/compiler/src/passes/parse/grammar.lalrpop b/compiler/src/passes/parse/grammar.lalrpop
index 9649a36..9820944 100644
--- a/compiler/src/passes/parse/grammar.lalrpop
+++ b/compiler/src/passes/parse/grammar.lalrpop
@@ -403,7 +403,7 @@ AsmInstr: InstrParsed<'input> = {
 }
 
 AsmArg: VarArg<Spanned<&'input str>> = {
-    <reg:AsmReg> => VarArg::Reg { reg },
+    <reg:AsmReg> => VarArg::Reg(reg),
     "{" <sym:Ident> "}" => VarArg::XVar { sym },
     "$" <val:Int> => VarArg::Imm(Imm::Imm32(val.parse().expect("Internal compiler error (oh no!): We were too lazy to make a proper error for this"))),
     "[" <reg:AsmReg> "+" <off:Int> "]"  => VarArg::Deref {
diff --git a/compiler/src/passes/select/macros.rs b/compiler/src/passes/select/macros.rs
index f610d1f..52c9227 100644
--- a/compiler/src/passes/select/macros.rs
+++ b/compiler/src/passes/select/macros.rs
@@ -194,10 +194,7 @@ macro_rules! imm32 {
 #[macro_export]
 macro_rules! reg {
     ($reg:ident) => {
-        $crate::passes::assign::Arg::Reg {
-            reg: $crate::passes::select::Reg::$reg,
-        }
-        .into()
+        $crate::passes::assign::Arg::Reg($crate::passes::select::Reg::$reg).into()
     };
 }
 
diff --git a/compiler/src/passes/select/mod.rs b/compiler/src/passes/select/mod.rs
index 77d415a..a6e16ee 100644
--- a/compiler/src/passes/select/mod.rs
+++ b/compiler/src/passes/select/mod.rs
@@ -101,8 +101,8 @@ pub enum Instr<Arg: Display, IdentVars: Display> {
 pub enum VarArg<IdentVars: Display> {
     #[display(fmt = "${_0}")]
     Imm(Imm),
-    #[display(fmt = "%{reg}")]
-    Reg { reg: Reg },
+    #[display(fmt = "%{_0}")]
+    Reg(Reg),
     #[display(fmt = "[%{reg} + ${off}]")]
     Deref { reg: Reg, off: i64 },
     #[display(fmt = "{sym}")]
diff --git a/compiler/src/passes/select/select.rs b/compiler/src/passes/select/select.rs
index 8b3a7ed..448bd8b 100644
--- a/compiler/src/passes/select/select.rs
+++ b/compiler/src/passes/select/select.rs
@@ -61,7 +61,7 @@ fn entry_block<'p>(
 
     // Save callee-saved registers (excluding stack pointers).
     for reg in CALLEE_SAVED_NO_STACK {
-        instrs.push(pushq!(VarArg::Reg { reg }));
+        instrs.push(pushq!(VarArg::Reg(reg)));
     }
 
     // Prepare temporary stack space - this will be optimized in later passes.
@@ -69,7 +69,7 @@ fn entry_block<'p>(
 
     // Introduce parameters as local variables.
     for (reg, param) in CALLER_SAVED.into_iter().zip(fun.params.iter()) {
-        instrs.push(movq!(VarArg::Reg { reg }, VarArg::XVar { sym: param.sym }));
+        instrs.push(movq!(VarArg::Reg(reg), VarArg::XVar { sym: param.sym }));
     }
 
     assert!(
@@ -95,7 +95,7 @@ fn exit_block<'p>(
 
     // Restore callee-saved registers (excluding stack pointers).
     for reg in CALLEE_SAVED_NO_STACK.into_iter().rev() {
-        instrs.push(popq!(VarArg::Reg { reg }));
+        instrs.push(popq!(VarArg::Reg(reg)));
     }
 
     // Restore stack pointers.
@@ -118,7 +118,7 @@ fn select_tail<'p>(
                 "Argument passing to stack is not yet implemented."
             );
             for (reg, arg) in CALLER_SAVED.into_iter().zip(exprs) {
-                instrs.push(movq!(select_atom(arg), VarArg::Reg { reg }));
+                instrs.push(movq!(select_atom(arg), VarArg::Reg(reg)));
             }
             instrs.push(jmp!(exit));
         }
@@ -235,7 +235,7 @@ fn select_assign<'p>(
             let mut instrs = vec![];
 
             for (arg, reg) in args.iter().zip(CALLER_SAVED.into_iter()) {
-                instrs.push(movq!(select_atom(*arg), VarArg::Reg { reg }));
+                instrs.push(movq!(select_atom(*arg), VarArg::Reg(reg)));
             }
             assert!(
                 args.len() <= 9,
@@ -245,7 +245,7 @@ fn select_assign<'p>(
             instrs.push(callq_indirect!(select_atom(fun), args.len()));
 
             for (reg, dst) in CALLER_SAVED.into_iter().zip(dsts) {
-                instrs.push(movq!(VarArg::Reg { reg }, var!(*dst)));
+                instrs.push(movq!(VarArg::Reg(reg), var!(*dst)));
             }
 
             instrs
diff --git a/compiler/src/passes/validate/resolve.rs b/compiler/src/passes/validate/resolve.rs
index 160a244..9c6078c 100644
--- a/compiler/src/passes/validate/resolve.rs
+++ b/compiler/src/passes/validate/resolve.rs
@@ -309,7 +309,7 @@ pub fn resolve_instr<'p>(
 ) -> InstrSelected<'p> {
     let map = |arg: VarArg<Spanned<UniqueSym<'p>>>| match arg {
         VarArg::Imm(imm) => VarArg::Imm(imm),
-        VarArg::Reg { reg } => VarArg::Reg { reg },
+        VarArg::Reg(reg) => VarArg::Reg(reg),
         VarArg::Deref { reg, off } => VarArg::Deref { reg, off },
         VarArg::XVar { sym } => VarArg::XVar { sym: sym.inner },
     };
diff --git a/compiler/src/passes/validate/uniquify/expr.rs b/compiler/src/passes/validate/uniquify/expr.rs
index 8734f4f..e411850 100644
--- a/compiler/src/passes/validate/uniquify/expr.rs
+++ b/compiler/src/passes/validate/uniquify/expr.rs
@@ -114,7 +114,7 @@ fn uniquify_instr<'p>(
     let map = |arg: VarArg<Spanned<&'p str>>| {
         Ok(match arg {
             VarArg::Imm(imm) => VarArg::Imm(imm),
-            VarArg::Reg { reg } => VarArg::Reg { reg },
+            VarArg::Reg(reg) => VarArg::Reg(reg),
             VarArg::Deref { reg, off } => VarArg::Deref { reg, off },
             VarArg::XVar { sym } => VarArg::XVar {
                 sym: try_get(sym, scope)?,