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added all non-binary files to repository
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‎.run_manager.ini

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[Runmanager]
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Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1e\0\0\0\xdd\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0)
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windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)
4+
headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0)
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[impl1%3CStrategy1%3E]
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isChecked=false
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isHidden=false
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isExpanded=false

‎.setting.ini

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[General]
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Export.auto_tasks=Bitgen, Jedecgen
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Map.auto_tasks=MapTrace
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PAR.auto_tasks=PARTrace, IOTiming

‎.spread_sheet.ini

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[General]
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COLUMN_POS_INFO_NAME_-1_0=Prioritize
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COLUMN_POS_INFO_NAME_-1_1=PIO Register

‎.spreadsheet_view.ini

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[General]
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pin_sort_type=0
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pin_sort_ascending=true
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sig_sort_type=0
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sig_sort_ascending=true
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active_Sheet=Port Assignments
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[Port%20Assignments]
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Name="148,0"
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Group%20By="100,1"
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Pin="67,2"
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BANK="77,3"
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BANK_VCC="108,4"
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VREF="71,5"
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IO_TYPE="149,6"
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PULLMODE="114,7"
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DRIVE="79,8"
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SLEWRATE="106,9"
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CLAMP="85,10"
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OPENDRAIN="120,11"
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DIFFRESISTOR="131,12"
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DIFFDRIVE="108,13"
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HYSTERESIS="114,14"
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Outload%20%28pF%29="121,15"
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MaxSkew="103,16"
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Clock%20Load%20Only="144,17"
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SwitchingID="119,18"
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Ground%20plane%20PCB%20noise%20%28mV%29="231,19"
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Power%20plane%20PCB%20noise%20%28mV%29="222,20"
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SSO%20Allowance%28%25%29="157,21"
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sort_columns="Name,Ascending"
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[Pin%20Assignments]
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Pin="100,0"
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Pad%20Name="106,1"
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Dual%20Function="264,2"
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Polarity="91,3"
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BANK="0,4"
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BANK_VCC="108,5"
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IO_TYPE="149,6"
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Signal%20Name="127,7"
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Signal%20Type="115,8"
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sort_columns="Pin,Ascending"
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[Clock%20Resource]
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Clock%20Type="100,ELLIPSIS"
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Clock%20Name="100,ELLIPSIS"
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Selection="100,ELLIPSIS"
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[Global%20Preferences]
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Preference%20Name="233,ELLIPSIS"
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Preference%20Value="236,ELLIPSIS"
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[Cell%20Mapping]
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Type="100,ELLIPSIS"
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Name="100,ELLIPSIS"
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Din\Dout="100,ELLIPSIS"
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PIO%20Register="100,ELLIPSIS"
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[Route%20Priority]
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Type="100,ELLIPSIS"
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Name="100,ELLIPSIS"
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Prioritize="100,ELLIPSIS"
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[Timing%20Preferences]
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Preference%20Name="139,ELLIPSIS"
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Preference%20Value="122,ELLIPSIS"
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Preference%20Unit="113,ELLIPSIS"
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[Group]
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Group%20Type\Name="135,ELLIPSIS"
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Value="46,ELLIPSIS"
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[Misc%20Preferences]
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Preference%20Name="124,ELLIPSIS"
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Preference%20Value="122,ELLIPSIS"

‎Makefile

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GHLD=$(shell command -v ghdl)
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FLAGS="--std=08"
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all:
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ghdl -a $(FLAGS) bldc_drv.vhd bldc_drvTb.vhd
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ghdl -e $(FLAGS) bldc_drvTb
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ghdl -r $(FLAGS) bldc_drvTb --wave=wave.ghw --stop-time=800ms

‎bldc_drvtb

1.22 MB
Binary file not shown.

‎bldc_fpga.ccl

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VERSION=20110520

‎bldc_fpga.ldf

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<?xml version="1.0" encoding="UTF-8"?>
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<BaliProject version="3.2" title="bldc_fpga" device="LCMXO3L-6900C-6BG256C" default_implementation="impl1">
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<Options/>
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<Implementation title="impl1" dir="impl1" description="impl1" synthesis="lse" default_strategy="Strategy1">
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<Options def_top="top"/>
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<Source name="bldc_drv.vhd" type="VHDL" type_short="VHDL">
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<Options/>
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</Source>
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<Source name="top.vhd" type="VHDL" type_short="VHDL">
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<Options top_module="top"/>
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</Source>
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<Source name="bldc_fpga.lpf" type="Logic Preference" type_short="LPF">
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<Options/>
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</Source>
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<Source name="impl1/impl1.xcf" type="Programming Project File" type_short="Programming">
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<Options/>
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</Source>
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</Implementation>
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<Strategy name="Strategy1" file="bldc_fpga1.sty"/>
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</BaliProject>

‎bldc_fpga.lpf

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BLOCK RESETPATHS ;
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BLOCK ASYNCPATHS ;
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BANK 1 VCCIO 3.3 V;
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LOCATE COMP "o_hbIN[0]" SITE "G14" ;
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IOBUF PORT "o_hbIN[0]" IO_TYPE=LVCMOS33 ;
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IOBUF PORT "o_nSD[0]" DRIVE=8 IO_TYPE=LVCMOS33 ;
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LOCATE COMP "o_hbIN[1]" SITE "D14" ;
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LOCATE COMP "o_hbIN[2]" SITE "D16" ;
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LOCATE COMP "o_nSD[0]" SITE "B16" ;
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LOCATE COMP "o_nSD[1]" SITE "F14" ;
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LOCATE COMP "o_nSD[2]" SITE "C15" ;
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IOBUF PORT "o_hbIN[1]" IO_TYPE=LVCMOS33 ;
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IOBUF PORT "o_hbIN[2]" IO_TYPE=LVCMOS33 ;
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IOBUF PORT "o_nSD[1]" IO_TYPE=LVCMOS33 ;
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IOBUF PORT "o_nSD[2]" IO_TYPE=LVCMOS33 ;

‎bldc_fpga1.sty

+205
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<?xml version="1.0" encoding="UTF-8"?>
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<!DOCTYPE strategy>
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<Strategy version="1.0" predefined="0" description="" label="Strategy1">
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<Property name="PROP_BD_CmdLineArgs" value="" time="0"/>
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<Property name="PROP_BD_EdfHardtimer" value="Enable" time="0"/>
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<Property name="PROP_BD_EdfInBusNameConv" value="None" time="0"/>
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<Property name="PROP_BD_EdfInLibPath" value="" time="0"/>
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<Property name="PROP_BD_EdfInRemLoc" value="Off" time="0"/>
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<Property name="PROP_BD_EdfMemPath" value="" time="0"/>
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<Property name="PROP_BD_ParSearchPath" value="" time="0"/>
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<Property name="PROP_BIT_AddressBitGen" value="Increment" time="0"/>
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<Property name="PROP_BIT_AllowReadBitGen" value="Disable" time="0"/>
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<Property name="PROP_BIT_ByteWideBitMirror" value="Disable" time="0"/>
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<Property name="PROP_BIT_CapReadBitGen" value="Disable" time="0"/>
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<Property name="PROP_BIT_ConModBitGen" value="Disable" time="0"/>
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<Property name="PROP_BIT_CreateBitFile" value="True" time="0"/>
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<Property name="PROP_BIT_DisRAMResBitGen" value="True" time="0"/>
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<Property name="PROP_BIT_DisableUESBitgen" value="False" time="0"/>
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<Property name="PROP_BIT_DonePinBitGen" value="Pullup" time="0"/>
20+
<Property name="PROP_BIT_DoneSigBitGen" value="4" time="0"/>
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<Property name="PROP_BIT_EnIOBitGen" value="TriStateDuringReConfig" time="0"/>
22+
<Property name="PROP_BIT_EnIntOscBitGen" value="Disable" time="0"/>
23+
<Property name="PROP_BIT_ExtClockBitGen" value="False" time="0"/>
24+
<Property name="PROP_BIT_GSREnableBitGen" value="True" time="0"/>
25+
<Property name="PROP_BIT_GSRRelOnBitGen" value="DoneIn" time="0"/>
26+
<Property name="PROP_BIT_GranTimBitGen" value="0" time="0"/>
27+
<Property name="PROP_BIT_IOTriRelBitGen" value="Cycle 2" time="0"/>
28+
<Property name="PROP_BIT_JTAGEnableBitGen" value="False" time="0"/>
29+
<Property name="PROP_BIT_LenBitsBitGen" value="24" time="0"/>
30+
<Property name="PROP_BIT_MIFFileBitGen" value="" time="0"/>
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<Property name="PROP_BIT_NoHeader" value="False" time="0"/>
32+
<Property name="PROP_BIT_OutFormatBitGen" value="Bit File (Binary)" time="0"/>
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<Property name="PROP_BIT_OutFormatBitGen_REF" value="" time="0"/>
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<Property name="PROP_BIT_OutFormatPromGen" value="Intel Hex 32-bit" time="0"/>
35+
<Property name="PROP_BIT_ParityCheckBitGen" value="True" time="0"/>
36+
<Property name="PROP_BIT_ReadBackBitGen" value="Flash" time="0"/>
37+
<Property name="PROP_BIT_ReadCaptureBitGen" value="Disable" time="0"/>
38+
<Property name="PROP_BIT_RemZeroFramesBitGen" value="False" time="0"/>
39+
<Property name="PROP_BIT_RunDRCBitGen" value="True" time="0"/>
40+
<Property name="PROP_BIT_SearchPthBitGen" value="" time="0"/>
41+
<Property name="PROP_BIT_StartUpClkBitGen" value="Cclk" time="0"/>
42+
<Property name="PROP_BIT_SynchIOBitGen" value="True" time="0"/>
43+
<Property name="PROP_BIT_SysClockConBitGen" value="Reset" time="0"/>
44+
<Property name="PROP_BIT_SysConBitGen" value="Reset" time="0"/>
45+
<Property name="PROP_BIT_WaitStTimBitGen" value="5" time="0"/>
46+
<Property name="PROP_IOTIMING_AllSpeed" value="False" time="0"/>
47+
<Property name="PROP_LST_AllowDUPMod" value="False" time="0"/>
48+
<Property name="PROP_LST_CarryChain" value="True" time="0"/>
49+
<Property name="PROP_LST_CarryChainLength" value="0" time="0"/>
50+
<Property name="PROP_LST_CmdLineArgs" value="" time="0"/>
51+
<Property name="PROP_LST_DSPStyle" value="DSP" time="0"/>
52+
<Property name="PROP_LST_DSPUtil" value="100" time="0"/>
53+
<Property name="PROP_LST_DecodeUnreachableStates" value="False" time="0"/>
54+
<Property name="PROP_LST_DisableDistRam" value="False" time="0"/>
55+
<Property name="PROP_LST_EBRUtil" value="100" time="0"/>
56+
<Property name="PROP_LST_EdfFrequency" value="200" time="0"/>
57+
<Property name="PROP_LST_EdfHardtimer" value="Enable" time="0"/>
58+
<Property name="PROP_LST_EdfInLibPath" value="" time="0"/>
59+
<Property name="PROP_LST_EdfInRemLoc" value="Off" time="0"/>
60+
<Property name="PROP_LST_EdfMemPath" value="" time="0"/>
61+
<Property name="PROP_LST_FIXGATEDCLKS" value="True" time="0"/>
62+
<Property name="PROP_LST_FSMEncodeStyle" value="Auto" time="0"/>
63+
<Property name="PROP_LST_ForceGSRInfer" value="Auto" time="0"/>
64+
<Property name="PROP_LST_IOInsertion" value="True" time="0"/>
65+
<Property name="PROP_LST_InterFileDump" value="False" time="0"/>
66+
<Property name="PROP_LST_LoopLimit" value="1950" time="0"/>
67+
<Property name="PROP_LST_MaxFanout" value="1000" time="0"/>
68+
<Property name="PROP_LST_MuxStyle" value="Auto" time="0"/>
69+
<Property name="PROP_LST_NumCriticalPaths" value="3" time="0"/>
70+
<Property name="PROP_LST_OptimizeGoal" value="Balanced" time="0"/>
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<Property name="PROP_LST_PropagatConst" value="True" time="0"/>
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<Property name="PROP_LST_RAMStyle" value="Auto" time="0"/>
73+
<Property name="PROP_LST_ROMStyle" value="Auto" time="0"/>
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<Property name="PROP_LST_RemoveDupRegs" value="True" time="0"/>
75+
<Property name="PROP_LST_ResolvedMixedDrivers" value="False" time="0"/>
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<Property name="PROP_LST_ResourceShare" value="True" time="0"/>
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<Property name="PROP_LST_UseIOReg" value="Auto" time="0"/>
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<Property name="PROP_LST_UseLPF" value="True" time="0"/>
79+
<Property name="PROP_LST_VHDL2008" value="False" time="0"/>
80+
<Property name="PROP_MAPSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
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<Property name="PROP_MAPSTA_AutoTiming" value="True" time="0"/>
82+
<Property name="PROP_MAPSTA_CheckUnconstrainedConns" value="False" time="0"/>
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<Property name="PROP_MAPSTA_CheckUnconstrainedPaths" value="False" time="0"/>
84+
<Property name="PROP_MAPSTA_FullName" value="False" time="0"/>
85+
<Property name="PROP_MAPSTA_NumUnconstrainedPaths" value="0" time="0"/>
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<Property name="PROP_MAPSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
87+
<Property name="PROP_MAPSTA_RouteEstAlogtithm" value="0" time="0"/>
88+
<Property name="PROP_MAPSTA_RptAsynTimLoop" value="False" time="0"/>
89+
<Property name="PROP_MAPSTA_WordCasePaths" value="1" time="0"/>
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<Property name="PROP_MAP_IgnorePreErr" value="True" time="0"/>
91+
<Property name="PROP_MAP_MAPIORegister" value="Auto" time="0"/>
92+
<Property name="PROP_MAP_MAPInferGSR" value="True" time="0"/>
93+
<Property name="PROP_MAP_MapModArgs" value="" time="0"/>
94+
<Property name="PROP_MAP_OvermapDevice" value="False" time="0"/>
95+
<Property name="PROP_MAP_PackLogMapDes" value="0" time="0"/>
96+
<Property name="PROP_MAP_RegRetiming" value="False" time="0"/>
97+
<Property name="PROP_MAP_SigCrossRef" value="False" time="0"/>
98+
<Property name="PROP_MAP_SymCrossRef" value="False" time="0"/>
99+
<Property name="PROP_MAP_TimingDriven" value="False" time="0"/>
100+
<Property name="PROP_MAP_TimingDrivenNodeRep" value="False" time="0"/>
101+
<Property name="PROP_MAP_TimingDrivenPack" value="False" time="0"/>
102+
<Property name="PROP_PARSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
103+
<Property name="PROP_PARSTA_AutoTiming" value="True" time="0"/>
104+
<Property name="PROP_PARSTA_CheckUnconstrainedConns" value="False" time="0"/>
105+
<Property name="PROP_PARSTA_CheckUnconstrainedPaths" value="False" time="0"/>
106+
<Property name="PROP_PARSTA_FullName" value="False" time="0"/>
107+
<Property name="PROP_PARSTA_NumUnconstrainedPaths" value="0" time="0"/>
108+
<Property name="PROP_PARSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
109+
<Property name="PROP_PARSTA_RptAsynTimLoop" value="False" time="0"/>
110+
<Property name="PROP_PARSTA_SpeedForHoldAnalysis" value="m" time="0"/>
111+
<Property name="PROP_PARSTA_SpeedForSetupAnalysis" value="default" time="0"/>
112+
<Property name="PROP_PARSTA_WordCasePaths" value="10" time="0"/>
113+
<Property name="PROP_PAR_CrDlyStFileParDes" value="False" time="0"/>
114+
<Property name="PROP_PAR_DisableTDParDes" value="False" time="0"/>
115+
<Property name="PROP_PAR_EffortParDes" value="5" time="0"/>
116+
<Property name="PROP_PAR_MultiSeedSortMode" value="Worst Slack" time="0"/>
117+
<Property name="PROP_PAR_NewRouteParDes" value="NBR" time="0"/>
118+
<Property name="PROP_PAR_PARClockSkew" value="Off" time="0"/>
119+
<Property name="PROP_PAR_PARModArgs" value="" time="0"/>
120+
<Property name="PROP_PAR_ParMultiNodeList" value="" time="0"/>
121+
<Property name="PROP_PAR_ParRunPlaceOnly" value="False" time="0"/>
122+
<Property name="PROP_PAR_PlcIterParDes" value="1" time="0"/>
123+
<Property name="PROP_PAR_PlcStCostTblParDes" value="1" time="0"/>
124+
<Property name="PROP_PAR_PrefErrorOut" value="True" time="0"/>
125+
<Property name="PROP_PAR_RemoveDir" value="True" time="0"/>
126+
<Property name="PROP_PAR_RouteDlyRedParDes" value="0" time="0"/>
127+
<Property name="PROP_PAR_RoutePassParDes" value="6" time="0"/>
128+
<Property name="PROP_PAR_RouteResOptParDes" value="0" time="0"/>
129+
<Property name="PROP_PAR_RoutingCDP" value="0" time="0"/>
130+
<Property name="PROP_PAR_RoutingCDR" value="0" time="0"/>
131+
<Property name="PROP_PAR_RunParWithTrce" value="False" time="0"/>
132+
<Property name="PROP_PAR_RunTimeReduction" value="True" time="0"/>
133+
<Property name="PROP_PAR_SaveBestRsltParDes" value="1" time="0"/>
134+
<Property name="PROP_PAR_StopZero" value="False" time="0"/>
135+
<Property name="PROP_PAR_parHold" value="On" time="0"/>
136+
<Property name="PROP_PAR_parPathBased" value="Off" time="0"/>
137+
<Property name="PROP_PRE_CmdLineArgs" value="" time="0"/>
138+
<Property name="PROP_PRE_EdfArrayBoundsCase" value="False" time="0"/>
139+
<Property name="PROP_PRE_EdfAutoResOfRam" value="False" time="0"/>
140+
<Property name="PROP_PRE_EdfClockDomainCross" value="False" time="0"/>
141+
<Property name="PROP_PRE_EdfDSPAcrossHie" value="False" time="0"/>
142+
<Property name="PROP_PRE_EdfFullCase" value="False" time="0"/>
143+
<Property name="PROP_PRE_EdfIgnoreRamRWCol" value="False" time="0"/>
144+
<Property name="PROP_PRE_EdfMissConstraint" value="False" time="0"/>
145+
<Property name="PROP_PRE_EdfNetFanout" value="True" time="0"/>
146+
<Property name="PROP_PRE_EdfParaCase" value="False" time="0"/>
147+
<Property name="PROP_PRE_EdfReencodeFSM" value="True" time="0"/>
148+
<Property name="PROP_PRE_EdfResSharing" value="True" time="0"/>
149+
<Property name="PROP_PRE_EdfTimingViolation" value="True" time="0"/>
150+
<Property name="PROP_PRE_EdfUseSafeFSM" value="False" time="0"/>
151+
<Property name="PROP_PRE_EdfVlog2001" value="True" time="0"/>
152+
<Property name="PROP_PRE_VSynComArea" value="True" time="0"/>
153+
<Property name="PROP_PRE_VSynCritcal" value="3" time="0"/>
154+
<Property name="PROP_PRE_VSynFSM" value="Auto" time="0"/>
155+
<Property name="PROP_PRE_VSynFreq" value="200" time="0"/>
156+
<Property name="PROP_PRE_VSynGSR" value="False" time="0"/>
157+
<Property name="PROP_PRE_VSynGatedClk" value="False" time="0"/>
158+
<Property name="PROP_PRE_VSynIOPad" value="False" time="0"/>
159+
<Property name="PROP_PRE_VSynOutNetForm" value="None" time="0"/>
160+
<Property name="PROP_PRE_VSynOutPref" value="True" time="0"/>
161+
<Property name="PROP_PRE_VSynRepClkFreq" value="True" time="0"/>
162+
<Property name="PROP_PRE_VSynRetime" value="True" time="0"/>
163+
<Property name="PROP_PRE_VSynTimSum" value="10" time="0"/>
164+
<Property name="PROP_PRE_VSynTransform" value="True" time="0"/>
165+
<Property name="PROP_PRE_VSyninpd" value="0" time="0"/>
166+
<Property name="PROP_PRE_VSynoutd" value="0" time="0"/>
167+
<Property name="PROP_SYN_ClockConversion" value="True" time="0"/>
168+
<Property name="PROP_SYN_CmdLineArgs" value="" time="0"/>
169+
<Property name="PROP_SYN_DisableRegisterRep" value="False" time="0"/>
170+
<Property name="PROP_SYN_EdfAllowDUPMod" value="False" time="0"/>
171+
<Property name="PROP_SYN_EdfArea" value="False" time="0"/>
172+
<Property name="PROP_SYN_EdfArrangeVHDLFiles" value="True" time="0"/>
173+
<Property name="PROP_SYN_EdfDefEnumEncode" value="Default" time="0"/>
174+
<Property name="PROP_SYN_EdfFanout" value="1000" time="0"/>
175+
<Property name="PROP_SYN_EdfFrequency" value="100" time="0"/>
176+
<Property name="PROP_SYN_EdfGSR" value="False" time="0"/>
177+
<Property name="PROP_SYN_EdfInsertIO" value="False" time="0"/>
178+
<Property name="PROP_SYN_EdfNumCritPath" value="" time="0"/>
179+
<Property name="PROP_SYN_EdfNumStartEnd" value="" time="0"/>
180+
<Property name="PROP_SYN_EdfOutNetForm" value="None" time="0"/>
181+
<Property name="PROP_SYN_EdfPushTirstates" value="True" time="0"/>
182+
<Property name="PROP_SYN_EdfResSharing" value="True" time="0"/>
183+
<Property name="PROP_SYN_EdfRunRetiming" value="Pipelining Only" time="0"/>
184+
<Property name="PROP_SYN_EdfSymFSM" value="True" time="0"/>
185+
<Property name="PROP_SYN_EdfUnconsClk" value="False" time="0"/>
186+
<Property name="PROP_SYN_EdfVerilogInput" value="Verilog 2001" time="0"/>
187+
<Property name="PROP_SYN_ExportSetting" value="No" time="0"/>
188+
<Property name="PROP_SYN_LibPath" value="" time="0"/>
189+
<Property name="PROP_SYN_ResolvedMixedDrivers" value="False" time="0"/>
190+
<Property name="PROP_SYN_UpdateCompilePtTimData" value="False" time="0"/>
191+
<Property name="PROP_SYN_UseLPF" value="True" time="0"/>
192+
<Property name="PROP_SYN_VHDL2008" value="False" time="0"/>
193+
<Property name="PROP_THERMAL_DefaultFreq" value="0" time="0"/>
194+
<Property name="PROP_TIM_MaxDelSimDes" value="" time="0"/>
195+
<Property name="PROP_TIM_MinSpeedGrade" value="False" time="0"/>
196+
<Property name="PROP_TIM_ModPreSimDes" value="" time="0"/>
197+
<Property name="PROP_TIM_NegStupHldTim" value="True" time="0"/>
198+
<Property name="PROP_TIM_TimSimGenPUR" value="True" time="0"/>
199+
<Property name="PROP_TIM_TimSimGenX" value="False" time="0"/>
200+
<Property name="PROP_TIM_TimSimHierSep" value="" time="0"/>
201+
<Property name="PROP_TIM_TransportModeOfPathDelay" value="False" time="0"/>
202+
<Property name="PROP_TIM_TrgtSpeedGrade" value="" time="0"/>
203+
<Property name="PROP_TIM_WriteVerboseNetlist" value="False" time="0"/>
204+
<Property name="PROP_TMCHK_EnableCheck" value="True" time="0"/>
205+
</Strategy>

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