HLX flow FIFO IP generator version conflict

[cholan2100]

I am having trouble adding native FIFO xci IP generated in Vivado 2021.2.

Conflict seems to arise from the cl_axi_interconnect (shipped with Shell) which uses fifo_generator_v13_2_1(probably from past versions) while newly generated FIFO IP's use fifo_generator_v13_2_6.

When i add the new IP, Vivado points to fifo_generator_v13_2_6, making cl_axi_interconnect fail.

Can get around by generating IPs and including generated .v files, rather than using xci blocks, but soon becomes a mess.

any other better way of handling this?

[cholan2100]

for now i patched axi_clock_converter_v2_1_vl_rfs.v to use 13.2.6, so that all IP's are on same version.

[czfpga]

Hi cholan2100,

I sounds like you're following the HDK flow not the HLX flow. Can you please confirm that?

Have you tried to open the cl_axi_interconnect.xci file in Vivado 2021.2 and check the IP status? If not, can you please give that a try? I would suggest to reset and regenerate the output files for the cl_axi_interconnect IP. It should be upgraded to use the fifo_generator_v13_2_6 instead of the fifo_generator_v13_2_1 code.

Hope that helps,

Chen