Loading of simulation waveform in Vivado is too slow

[Gogul-N]

Hi,

I have been running a simulation in Vivado. Writing into the BRAM of 16 KB through PCIS is taking more than 2 hours. I need to write more than 10 BRAMS. If it takes time like this, I am worrying that I need to wait more than a day to simulate my design.
Is it expected behaviour?
Is there any way to reduce the simulation time?

Regards
Gogul

[Gogul-N]

Hi @ljp0101

I am trying to use the above as follows

`function access_t::write_host_dw (input[63:0] addr, input[31:0] data);
for (int i=0; i<4; i++)
begin
tb.hm_put_byte(.addr(addr+i), .d(data[i*8+:8]));
end

endfunction

access_t access_inst;

access_inst = new();
access_inst.write_host_dw(64'h44A00000, 32'h00008000);
access_inst.write_host_dw(64'h44A00004, 32'h00000505);
access_inst.write_host_dw(64'h44A00008, 32'h000004F5);
access_inst.write_host_dw(64'h44A0000C, 32'h000004E5);`

But, nothing is written to the BRAM in those locations.

Am I following the correct method?

Regards
Gogul

[ljp0101]

Hi @ljp0101

I am trying to use the above as follows

`function access_t::write_host_dw (input[63:0] addr, input[31:0] data); for (int i=0; i<4; i++) begin tb.hm_put_byte(.addr(addr+i), .d(data[i*8+:8])); end

endfunction

access_t access_inst;

access_inst = new(); access_inst.write_host_dw(64'h44A00000, 32'h00008000); access_inst.write_host_dw(64'h44A00004, 32'h00000505); access_inst.write_host_dw(64'h44A00008, 32'h000004F5); access_inst.write_host_dw(64'h44A0000C, 32'h000004E5);`

But, nothing is written to the BRAM in those locations.

Am I following the correct method?

Regards Gogul

Sorry, thought you were using DDR. You can use a COE file or initial statements with block RAM depending on how you're instantiating it. Xilinx support has details.