PCIM ARID all bits can be used?

[tewujianke]

Hello,

The EC2 FPGA Shell Errata Document mentions that read-request is limited to 32 outstanding. Does this limit the AXI arid's valid range to 0-31? Or can the entire 16-bit ARID be used, as long as there are no more than 32 outstanding read requests?

Thanks

[czfpga]

Hi,

Sorry we somehow missed this question earlier. For the PCIM interface, the supported outstanding read request number is defined by the AMD PCIe bridge IP, for which you can find all the useful details in https://docs.xilinx.com/r/en-US/pg194-axi-bridge-pcie-gen3. What seems missing in this document is that the PCIe bridge IP does not support multiple IDs on the slave bridge so the PCIM ARID/AWID are ignored by the bridge IP. All transactions therefore would be treated as using a single ID. The ordering will be preserved per AXI protocol. We've provided feedback to AMD on the documentation. I hope this answers your question.

Thanks