v1.3.4 patch (#378)

* Create HOWTO_detect_power_gated_AFI.md

* Update strategy_TIMING.tcl

* Update RTL_Simulating_CL_Designs.md

* Update RELEASE_NOTES.md

* Update README.md

* Update ERRATA.md

* Update FAQs.md

Author: kristopk

ERRATA.md

@@ -2,10 +2,10 @@
 # AWS EC2 FPGA HDK+SDK Errata
 
 
-## Release 1.3.0 
+## Release 1.3.X
 ### Implementation Restrictions
 *    PCIE AXI4 interfaces between Custom Logic(CL) and Shell(SH) have following restrictions:
-    *    All PCIe transactions must adhere to the PCIe Exress base spec
+    *    All PCIe transactions must adhere to the PCIe Express base spec
     *    4Kbyte Address boundary for all transactions(PCIe restriction)
     *    Multiple outstanding outbound PCIe Read transactions with same ID not supported
     *    PCIE extended tag not supported, so read-request is limited to 32 outstanding
@@ -19,7 +19,7 @@
 ## Unsupported Features (Planned for future releases)
 * FPGA to FPGA communication over PCIe for F1.16xl
 * FPGA to FPGA over the 400Gbps Ring for F1.16xl
-* Aurora and Reliabile Aurora modules for the FPGA-to-FPGA 
+* Aurora and Reliable Aurora modules for the FPGA-to-FPGA 
 * Preserving the DRAM content between different AFI loads (by the same running instance)
 * Cadence RTL simulations tools
 * PCIM and DMA-PCIS AXI-4 interfaces do not support AxSIZE other than 3'b110 (64B)

FAQs.md

@@ -26,7 +26,7 @@ AWS designed its FPGA instances to provide a developer experience with ease of u
 
 - Developers don’t need to purchase / design / bringup or debug the physical hardware where the FPGA is hosted, nor the platform/server hardware: all the hardware is verified, monitored, and maintained by AWS.
 
-- AWS provides an [FPGA Developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) that contains Xilinx Vivado development environment, with all the needed licenses. By using the FPGA developer AMI developers have a choice to a wide range of instance (different CPU and Memory configutation) allowing developers to optimize their development flow.
+- AWS provides an [FPGA Developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) that contains Xilinx Vivado development environment, with all the needed licenses. By using the FPGA developer AMI developers have a choice to a wide range of instance (different CPU and Memory configuration) allowing developers to optimize their development flow.
 
 - AWS provides cloud based debug tools: [Virtual JTAG](./hdk/docs/Virtual_JTAG_XVC.md) which is equivalent to debug using JTAG with on-premises development, and Virtual LED together with Virtual DIP Switch emulation the LED and DIP switches in typical development board.
 
@@ -58,7 +58,7 @@ Once developers complete their DCP, they submit the design through an AWS EC2 AP
 
 As AWS has taken all the non-differentiating, heavy lifting of hardware design, debug and implementation of PCIe tuning, FPGA I/O assignment, power, thermal management, and runtime health monitoring. Therefore AWS FPGA developers can focus on their own differentiating logic, instead of spending time on hardware bringup/debug and maintenance.
 
-On the business side, AWS Marketplace (MP) provides FPGA developers the opportunity to sell hardware accelerations to all of AWS users: Ramping on AWS MP services, capabilities and commercial opportunities are recommended knowledge for developers interested in selling their AFIs on AWS MP. Education and research institutes can use AWS MP to distribute their research work ; having access to vast amounts of free [public data-sets](https://aws.amazon.com/public-datasets/ ) can be of value when running research hardware accelarations on AWS.
+On the business side, AWS Marketplace (MP) provides FPGA developers the opportunity to sell hardware accelerations to all of AWS users: Ramping on AWS MP services, capabilities and commercial opportunities are recommended knowledge for developers interested in selling their AFIs on AWS MP. Education and research institutes can use AWS MP to distribute their research work ; having access to vast amounts of free [public data-sets](https://aws.amazon.com/public-datasets/ ) can be of value when running research hardware accelerations on AWS.
 
 Finally, AWS consulting and technology partners can offer their services through the [AWS Partner Network](https://aws.amazon.com/ec2/instance-types/f1/partners/) to AWS users that don’t have specific FPGA development knowledge, in order to develop FPGA accelerations in the cloud by themselves.
 
@@ -107,7 +107,7 @@ The developer can create multiple AFIs at no extra cost, up to a defined limited
 
 **Q: What regions are supported?**
 
-AWS FPGA generation and EC2 F1 instances are supported in us-east-1 (N. Virginia), us-west-2 (Oregon) and ue-west-1 (Ireland).
+AWS FPGA generation and EC2 F1 instances are supported in us-east-1 (N. Virginia), us-west-2 (Oregon) and eu-west-1 (Ireland).
 
 
 **Q: What is the process for creating an AFI?**
@@ -121,7 +121,7 @@ Use the AWS CLI `describe-fpga-images` API to get information about the created
 
 Yes, but you must first copy the AFI using the [copy-fpga-image](./hdk/docs/copy_fpga_image.md) API.  You should generate AFIs in one region and use copy to make them available in other regions.  Copy preserves the Global AFI ID used to load an AFI on a EC2 instance.
 
-Use [describe-fpga-images](./hdk/docs/describe_fpga_images.md) with the [--region command line option](http://docs.aws.amazon.com/cli/latest/userguide/cli-command-line.html) to list AFIs available in a specific region.  Use `FpgaImageGlobalId` attribute and `fpga-image-global-id` filter to match AFI copies accross regions.
+Use [describe-fpga-images](./hdk/docs/describe_fpga_images.md) with the [--region command line option](http://docs.aws.amazon.com/cli/latest/userguide/cli-command-line.html) to list AFIs available in a specific region.  Use `FpgaImageGlobalId` attribute and `fpga-image-global-id` filter to match AFI copies across regions.
 
 **Q: Can I share an AFI with other AWS accounts?**
 
@@ -135,7 +135,7 @@ Use [reset-fpga-image-attribute](./hdk/docs/fpga_image_attributes.md) API to rev
 
 Yes, use [delete-fpga-image](./hdk/docs/delete_fpga_image.md) to delete an AFI in a specific region.  Deleting an AFI in one region does not affect AFIs in other regions.
 
-Use [delete-fpga-image](./hdk/docs/delete_fpga_image.md) carefully. Once all AFIs of the same global AFI ID are deleted, the AFIs cannot be recovered from deletion.  Review [IAM policy best practices](http://docs.aws.amazon.com/IAM/latest/UserGuide/best-practices.html#grant-least-privilege) to resrict access to this API.
+Use [delete-fpga-image](./hdk/docs/delete_fpga_image.md) carefully. Once all AFIs of the same global AFI ID are deleted, the AFIs cannot be recovered from deletion.  Review [IAM policy best practices](http://docs.aws.amazon.com/IAM/latest/UserGuide/best-practices.html#grant-least-privilege) to restrict access to this API.
 
 **Q: Can I bring my own bitstream for loading on an F1 FPGA?**
 
@@ -160,7 +160,7 @@ AWS prefers not to limit developers to a specific template in terms of how we ad
 
 If you decide to use the [FPGA Developer AMI on AWS Marketplace](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ), Xilinx licenses for simulation, encryption, SDAccel and Design Checkpoint generation are included at no additional cost. 
 
-If you want to run using other methods or on a local machine, you will need to obtain any necessary licenses, specifically you will need to have setup the approproate Xilinx Vivado license. For more details, please refer to [On-premises licensing help](./hdk/docs/on_premise_licensing_help.md)
+If you want to run using other methods or on a local machine, you will need to obtain any necessary licenses, specifically you will need to have setup the appropriate Xilinx Vivado license. For more details, please refer to [On-premises licensing help](./hdk/docs/on_premise_licensing_help.md)
 
 
 **Q: Does AWS provide physical FPGA boards for on-premises development?**
@@ -381,7 +381,7 @@ The FPGA Shell provides a selectable frequency clocks (up to 8 clocks) from the
 
 **Q: What memory is attached to the FPGA?**
 
-Each FPGA on F1 has 4 x DDR4 interfaces, each is 72bits wide (64bit data). Each DRAM interface has 16GiB of RDRAM attached. This yields 64GiB of total DRAM memory avaliable localy to each F1 FPGA.
+Each FPGA on F1 has 4 x DDR4 interfaces, each is 72bits wide (64bit data). Each DRAM interface has 16GiB of RDRAM attached. This yields 64GiB of total DRAM memory available localy to each F1 FPGA.
 
 
 **Q: What FPGA debug capabilities are supported?**

README.md

@@ -43,11 +43,11 @@ The [HDK directory](./hdk) contains useful information and scripts for developer
 
 Developers have the option of working in a GUI mode using Vivado IPI.  With IPI you can create complex F1 custom designs on a graphical interface design canvas.  The HDK development kit provides AWS FPGA IP which will help you quickly develop your custom designs by enabling you to quickly drop in IP blocks into your design.
 
-The IPI flow isolates the Custom Logic (CL) from the shell, allowing the developer to focus on differentiating logic and leave the heavy lifting, undeferentiated hardware interfaces development to the AWS FPGA Shell.  Generating a logic diagram is simplified with designer automation that connects RTL, IP, and peripherals like DDR and PCIe in a correct by construction flow.  The “what you see is what you get” tool generates the equivalent code by instantiating the underlying IP and RTL with access via the Vivado project to the entire FPGA hardware design flow.  A video walk through of this flow for a simple diagram is available at https://www.xilinx.com/video/hardware/using-vivado-ip-integrator-and-amazon-f1.html.  This flow example is a good starting point for developers who want to quickly add IP blocks with high performance access to multiple external memories.
+The IPI flow isolates the Custom Logic (CL) from the shell, allowing the developer to focus on differentiating logic and leave the heavy lifting, undifferentiated hardware interfaces development to the AWS FPGA Shell.  Generating a logic diagram is simplified with designer automation that connects RTL, IP, and peripherals like DDR and PCIe in a correct by construction flow.  The “what you see is what you get” tool generates the equivalent code by instantiating the underlying IP and RTL with access via the Vivado project to the entire FPGA hardware design flow.  A video walk through of this flow for a simple diagram is available at https://www.xilinx.com/video/hardware/using-vivado-ip-integrator-and-amazon-f1.html.  This flow example is a good starting point for developers who want to quickly add IP blocks with high performance access to multiple external memories.
 
 The IPI RTL flow enables the developer a single graphical environment to add sources and IP, simulate, synthesize the RTL, and then stitch together the Custom Logic (CL) with the Shell’s design checkpoint (DCP).  For design debug, developers can easily instantiate logic analyzers or other debug logic, investigate timing and resource reports, and quickly link from implementation messages to the design view and source code when applicable.  This flow is a good starting point for experts in RTL design or designs who have a minimal amount of interconnection between RTL modules.
 
-The below documentation covers the setup, tutorials of the IPI flows and IPI FAQ.  Developers are advised to read all documents before starting thier first AWS FPGA design with IPI.  
+The below documentation covers the setup, tutorials of the IPI flows and IPI FAQ.  Developers are advised to read all documents before starting their first AWS FPGA design with IPI.  
 
 [IPI Setup](./hdk/docs/IPI_GUI_Vivado_Setup.md)
 
@@ -71,7 +71,7 @@ The [SDK directory](./sdk) includes the runtime environment required to run on E
 <a name="sdaccel"></a>
 ## OpenCL Development Environment with Amazon EC2 F1 FPGA Instances to accelerate your C/C++ applications
 
-The OpenCL development enviroment allows customers to use OpenCL with Amazon EC2 F1 FPGA Instances to accelerate their C/C++ applications. Software developers with little to no FPGA experience, will find a familiar development experience and now can use the cloud-scale availability of FPGAs to supercharge their applications. 
+The OpenCL development environment allows customers to use OpenCL with Amazon EC2 F1 FPGA Instances to accelerate their C/C++ applications. Software developers with little to no FPGA experience, will find a familiar development experience and now can use the cloud-scale availability of FPGAs to supercharge their applications. 
 
 Kernels are expressed in OpenCL or C/C++ and accelerated by implementing them in custom FPGA hardware. In addition, the development environment from Xilinx called SDAccel allows the acceleration to be performed using pre-existing RTL designs. 
 

RELEASE_NOTES.md

@@ -31,18 +31,18 @@
    *    Additional SDAccel Platforms
          *    1DDR for faster build times and smaller expanded shell
          *    RTL Kernel Debug adds support for virtual jtag debug on RTL kernels
-   *    IP Integrator GUI (HLx) improvments 
+   *    IP Integrator GUI (HLx) improvements 
    *    CL\_DRAM\_DMA fixes and improvements
          *    Dual master support
-   *    Simulation enviroment fixes and improvements
+   *    Simulation environment fixes and improvements
          *    AXI/AXIL Protocol checkers
          *    Shell model improvements
          *    SW co-simulation support on cl\_hello\_world
          *    DDR Model patch
-   *    Updated SH\_DDR module in preperation for upcoming feature release	
+   *    Updated SH\_DDR module in preparation for upcoming feature release	
 
 ## Release 1.3.3 (See [ERRATA](./ERRATA.md) for unsupported features)
-   *    New FPGA Image APIs for deleteing and reading/editing attributes 
+   *    New FPGA Image APIs for deleting and reading/editing attributes 
 
 ## Release 1.3.2 (See [ERRATA](./ERRATA.md) for unsupported features)
    *    SDAccel general availability