From 6bb1bdac335cabfd3e3c0e01de255f0abbff8f80 Mon Sep 17 00:00:00 2001 From: Maxwell Thimmig Date: Fri, 27 Dec 2024 18:39:43 -0600 Subject: [PATCH] Release v2.0.1 (#665) --- .readthedocs.yaml | 13 + ERRATA.md | 24 +- README.md | 4 + RELEASE_NOTES.md | 5 +- docs-rtd/Makefile | 156 + docs-rtd/requirements.txt | 1 + docs-rtd/source/ERRATA.rst | 83 + docs-rtd/source/RELEASE_NOTES.rst | 19 + ...ser_Guide_AWS_EC2_FPGA_Development_Kit.rst | 317 ++ .../source/_static/F2_Shell_interface.png | Bin 0 -> 54884 bytes .../source/_static/VJTAG_images/vjtag_1.jpg | Bin 0 -> 136367 bytes .../source/_static/VJTAG_images/vjtag_2.jpg | Bin 0 -> 185390 bytes .../source/_static/VJTAG_images/vjtag_3.jpg | Bin 0 -> 218825 bytes .../source/_static/VJTAG_images/vjtag_4.jpg | Bin 0 -> 204763 bytes .../source/_static/VJTAG_images/vjtag_5.jpg | Bin 0 -> 277270 bytes .../source/_static/VJTAG_images/vjtag_6.jpg | Bin 0 -> 1045637 bytes docs-rtd/source/_static/accel_card_specs.png | Bin 0 -> 230566 bytes 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vitis/README.md | 8 +- vitis/tools/create_vitis_afi.sh | 287 -- vitis_setup.sh | 114 +- 366 files changed, 16644 insertions(+), 3226 deletions(-) create mode 100644 .readthedocs.yaml create mode 100644 docs-rtd/Makefile create mode 100644 docs-rtd/requirements.txt create mode 100644 docs-rtd/source/ERRATA.rst create mode 100644 docs-rtd/source/RELEASE_NOTES.rst create mode 100644 docs-rtd/source/User_Guide_AWS_EC2_FPGA_Development_Kit.rst create mode 100644 docs-rtd/source/_static/F2_Shell_interface.png create mode 100644 docs-rtd/source/_static/VJTAG_images/vjtag_1.jpg create mode 100644 docs-rtd/source/_static/VJTAG_images/vjtag_2.jpg create mode 100644 docs-rtd/source/_static/VJTAG_images/vjtag_3.jpg create mode 100644 docs-rtd/source/_static/VJTAG_images/vjtag_4.jpg create mode 100644 docs-rtd/source/_static/VJTAG_images/vjtag_5.jpg create mode 100644 docs-rtd/source/_static/VJTAG_images/vjtag_6.jpg create mode 100644 docs-rtd/source/_static/accel_card_specs.png create mode 100644 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docs-rtd/source/spelling_wordlist.txt create mode 100644 docs-rtd/source/vitis/README.rst create mode 100644 shared/bin/check_doc_links.py delete mode 100755 vitis/tools/create_vitis_afi.sh diff --git a/.readthedocs.yaml b/.readthedocs.yaml new file mode 100644 index 000000000..e88e65ea8 --- /dev/null +++ b/.readthedocs.yaml @@ -0,0 +1,13 @@ +version: 2 + +build: + os: ubuntu-20.04 + tools: + python: "3.10" + +python: + install: + - requirements: docs-rtd/requirements.txt + +sphinx: + configuration: docs-rtd/source/conf.py diff --git a/ERRATA.md b/ERRATA.md index a5e42ae2c..ed9bb726f 100644 --- a/ERRATA.md +++ b/ERRATA.md @@ -7,13 +7,15 @@ Shell errata is [documented here](./hdk/docs/AWS_Shell_ERRATA.md) ## HDK -1. CL simulation might show the following "error" message if the [CL clock generator](./hdk/docs/AWS_CLK_GEN_spec.md) is contained in the design. By default, the generator blocks all output clocks (except for `o_clk_main_a0`) and asserts all output resets. This behavior violates the built-in reset check in the [AXI SmartConnect IP](https://www.xilinx.com/products/intellectual-property/smartconnect.html#overview). This message can be safely ignored. A Fix for this issue is in progress. +1. Support for the XDMA Shell in the HDK design flow is not available at this time. CL builds using the XDMA Shell will result in a build failure. + +2. CL simulation might show the following "error" message if the [CL clock generator](./hdk/docs/AWS_CLK_GEN_spec.md) is contained in the design. By default, the generator blocks all output clocks (except for `o_clk_main_a0`) and asserts all output resets. This behavior violates the built-in reset check in the [AXI SmartConnect IP](https://www.xilinx.com/products/intellectual-property/smartconnect.html#overview). This message can be safely ignored. A Fix for this issue is in progress. ```bash # ** Error: [SmartConnect 500-33] s_sc_aresetn should be asserted for at least 16 cycles of m_sc_aclk. tb.card.fpga.CL.CL_HBM.HBM_PRESENT_EQ_1.AXI_CONVERTER_AXI4_AXI3.cl_axi_sc_1x1_i.smartconnect_0.inst.s00_nodes.s00_aw_node.inst.. ``` -2. CL simulation might show the following "error" message. This message can be safely ignored. A Fix for this issue is in progress. +3. CL simulation might show the following "error" message. This message can be safely ignored. A Fix for this issue is in progress. ```bash # Initializing memory from data in 'ddr4_ddr_10.mem'. @@ -22,11 +24,9 @@ Shell errata is [documented here](./hdk/docs/AWS_Shell_ERRATA.md) # ERROR: Failed to write data burst length to 16. Only <4,8> are valid. ``` -3. XSIM simulator does not support a cycle-accurate simulation model for the HBM IP. We’re observing significantly longer simulation times compared to VCS and Questa simulators. This is caused by the HBM BFM used in XSIM. Therefore, running HBM simulation using VCS or Questa is strongly recommended. - -4. XDMA driver interrupt mode doesn't work currently on instances. Runtime examples have temporarily switched to use the polling mode and the interrupt mode test has been temporarily removed. Refer to the [XDMA driver installation guide](./hdk/docs/XDMA_Install.md) for instructions on how to load XDMA driver using the polling mode. +4. XSIM simulator does not support a cycle-accurate simulation model for the HBM IP. We’re observing significantly longer simulation times compared to VCS and Questa simulators. This is caused by the HBM BFM used in XSIM. Therefore, running HBM simulation using VCS or Questa is strongly recommended. -5. The following hdk tests are not supported in XSIM currently and will report not supported warning if ran: +5. The following HDK tests are currently not supported in XSIM and will report not supported warning if ran: - cl_mem_perf: - test_dram_dma_4k_crossing @@ -40,10 +40,18 @@ Shell errata is [documented here](./hdk/docs/AWS_Shell_ERRATA.md) 6. Simulation of the [HBM monitor interface](./hdk/docs/AWS_Shell_Interface_Specification.md/#hbm-monitor-interface) is not supported in this release. The HBM IP always passes initialization and remains in an operating state for all tests. Simulation support for the HBM monitor will be added in a future release. -7. AFIs created based on HDK XDMA shell or Vitis are not supported on F2 instances at this time. +7. AFIs created based on HDK XDMA shell or Vitis are not supported on F2 + instances at this time. + +8. The following ddr simulation backdoor test is not working with 64GB memory: + - test_ddr_peek_bdr_walking_ones ## SDK ## Software defined Accelerator Development (Vitis) -- Support for 2024.1 and hardware emulation only. Software emulation and F2 instance support is not supported at this time. +1. Only hardware emulation via Vitis 2024.1 is currently supported. + +2. Support for Vitis 2024.1 accelerator binary creation and AFI creation is not supported, but will be released at a later time. + +3. Support for Vitis software emulation has been deprecated by AMD, therefore, no longer supported. diff --git a/README.md b/README.md index ae5df7364..9348c7a7f 100644 --- a/README.md +++ b/README.md @@ -12,6 +12,10 @@ The F2 FPGA Development Kit is a hardware-software development kit that enables For full documentation, including a user guide, code snippets, and tutorials, see the [AWS EC2 FPGA Development Kit User Guide](./User_Guide_AWS_EC2_FPGA_Development_Kit.md) +## F2 FPGA ReadTheDocs (Beta) + +We are currently migrating our F2 documentation to comply with the ReadTheDocs standard. To familiarize yourself with the new layout, please [click here](https://awsdocs-fpga-f2.readthedocs-hosted.com). + ## Support To raise an issue or receive support, please [open an issue on the official GitHub page](https://github.com/aws/aws-fpga/issues). diff --git a/RELEASE_NOTES.md b/RELEASE_NOTES.md index 67e5f991a..8e92820c9 100644 --- a/RELEASE_NOTES.md +++ b/RELEASE_NOTES.md @@ -1,4 +1,7 @@ # F2 Developer Kit Release Notes +## v2.0.1 +Updates to HDK, SDK, and Vitis documentation. Added check for XRT install to enable Vitis hardware emulation. XRT install can now be performed automatically by running a command presented during `vitis_setup.sh`. + ## v2.0.0 -Initial release. F2 general-availability companion. \ No newline at end of file +Initial release. F2 general-availability companion. diff --git a/docs-rtd/Makefile b/docs-rtd/Makefile new file mode 100644 index 000000000..c7bdfa521 --- /dev/null +++ b/docs-rtd/Makefile @@ -0,0 +1,156 @@ +# Makefile for Sphinx documentation +# + +# You can set these variables from the command line. +SPHINXOPTS = +SPHINXBUILD = sphinx-build +PAPER = +BUILDDIR = build + +# Internal variables. +PAPEROPT_a4 = -D latex_paper_size=a4 +PAPEROPT_letter = -D latex_paper_size=letter +ALLSPHINXOPTS = -d $(BUILDDIR)/doctrees $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) source +# the i18n builder cannot share the environment and doctrees with the others +I18NSPHINXOPTS = $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) source + +.PHONY: help clean html dirhtml singlehtml pickle json htmlhelp qthelp devhelp epub latex latexpdf text man changes linkcheck doctest gettext + +help: + @echo "Please use \`make ' where is one of" + @echo " html to make standalone HTML files" + @echo " dirhtml to make HTML files named index.html in directories" + @echo " singlehtml to make a single large HTML file" + @echo " pickle to make pickle files" + @echo " json to make JSON files" + @echo " htmlhelp to make HTML files and a HTML help project" + @echo " qthelp to make HTML files and a qthelp project" + @echo " devhelp to make HTML files and a Devhelp project" + @echo " epub to make an epub" + @echo " latex to make LaTeX files, you can set PAPER=a4 or PAPER=letter" + @echo " latexpdf to make LaTeX files and run them through pdflatex" + @echo " text to make text files" + @echo " man to make manual pages" + @echo " texinfo to make Texinfo files" + @echo " info to make Texinfo files and run them through makeinfo" + @echo " gettext to make PO message catalogs" + @echo " changes to make an overview of all changed/added/deprecated items" + @echo " linkcheck to check all external links for integrity" + @echo " doctest to run all doctests embedded in the documentation (if enabled)" + +clean: + -rm -rf $(BUILDDIR)/* + +html: + $(SPHINXBUILD) -a -b html $(ALLSPHINXOPTS) $(BUILDDIR)/html + @echo + @echo "Build finished. The HTML pages are in $(BUILDDIR)/html." + +dirhtml: + $(SPHINXBUILD) -b dirhtml $(ALLSPHINXOPTS) $(BUILDDIR)/dirhtml + @echo + @echo "Build finished. The HTML pages are in $(BUILDDIR)/dirhtml." + +singlehtml: + $(SPHINXBUILD) -b singlehtml $(ALLSPHINXOPTS) $(BUILDDIR)/singlehtml + @echo + @echo "Build finished. The HTML page is in $(BUILDDIR)/singlehtml." + +pickle: + $(SPHINXBUILD) -b pickle $(ALLSPHINXOPTS) $(BUILDDIR)/pickle + @echo + @echo "Build finished; now you can process the pickle files." + +json: + $(SPHINXBUILD) -b json $(ALLSPHINXOPTS) $(BUILDDIR)/json + @echo + @echo "Build finished; now you can process the JSON files." + +htmlhelp: + $(SPHINXBUILD) -b htmlhelp $(ALLSPHINXOPTS) $(BUILDDIR)/htmlhelp + @echo + @echo "Build finished; now you can run HTML Help Workshop with the" \ + ".hhp project file in $(BUILDDIR)/htmlhelp." + +qthelp: + $(SPHINXBUILD) -b qthelp $(ALLSPHINXOPTS) $(BUILDDIR)/qthelp + @echo + @echo "Build finished; now you can run "qcollectiongenerator" with the" \ + ".qhcp project file in $(BUILDDIR)/qthelp, like this:" + @echo "# qcollectiongenerator $(BUILDDIR)/qthelp/F2.qhcp" + @echo "To view the help file:" + @echo "# assistant -collectionFile $(BUILDDIR)/qthelp/F2.qhc" + +devhelp: + $(SPHINXBUILD) -b devhelp $(ALLSPHINXOPTS) $(BUILDDIR)/devhelp + @echo + @echo "Build finished." + @echo "To view the help file:" + @echo "# mkdir -p $$HOME/.local/share/devhelp/F2" + @echo "# ln -s $(BUILDDIR)/devhelp $$HOME/.local/share/devhelp/F2" + @echo "# devhelp" + +epub: + $(SPHINXBUILD) -b epub $(ALLSPHINXOPTS) $(BUILDDIR)/epub + @echo + @echo "Build finished. The epub file is in $(BUILDDIR)/epub." + +latex: + $(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) $(BUILDDIR)/latex + @echo + @echo "Build finished; the LaTeX files are in $(BUILDDIR)/latex." + @echo "Run \`make' in that directory to run these through (pdf)latex" \ + "(use \`make latexpdf' here to do that automatically)." + +latexpdf: + $(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) $(BUILDDIR)/latex + @echo "Running LaTeX files through pdflatex..." + $(MAKE) -C $(BUILDDIR)/latex all-pdf + @echo "pdflatex finished; the PDF files are in $(BUILDDIR)/latex." + +text: + $(SPHINXBUILD) -b text $(ALLSPHINXOPTS) $(BUILDDIR)/text + @echo + @echo "Build finished. The text files are in $(BUILDDIR)/text." + +man: + $(SPHINXBUILD) -b man $(ALLSPHINXOPTS) $(BUILDDIR)/man + @echo + @echo "Build finished. The manual pages are in $(BUILDDIR)/man." + +texinfo: + $(SPHINXBUILD) -b texinfo $(ALLSPHINXOPTS) $(BUILDDIR)/texinfo + @echo + @echo "Build finished. The Texinfo files are in $(BUILDDIR)/texinfo." + @echo "Run \`make' in that directory to run these through makeinfo" \ + "(use \`make info' here to do that automatically)." + +info: + $(SPHINXBUILD) -b texinfo $(ALLSPHINXOPTS) $(BUILDDIR)/texinfo + @echo "Running Texinfo files through makeinfo..." + make -C $(BUILDDIR)/texinfo info + @echo "makeinfo finished; the Info files are in $(BUILDDIR)/texinfo." + +gettext: + $(SPHINXBUILD) -b gettext $(I18NSPHINXOPTS) $(BUILDDIR)/locale + @echo + @echo "Build finished. The message catalogs are in $(BUILDDIR)/locale." + +changes: + $(SPHINXBUILD) -b changes $(ALLSPHINXOPTS) $(BUILDDIR)/changes + @echo + @echo "The overview file is in $(BUILDDIR)/changes." + +linkcheck: + $(SPHINXBUILD) -b linkcheck $(ALLSPHINXOPTS) $(BUILDDIR)/linkcheck + @echo + @echo "Link check complete; look for any errors in the above output " \ + "or in $(BUILDDIR)/linkcheck/output.txt." + +doctest: + $(SPHINXBUILD) -b doctest $(ALLSPHINXOPTS) $(BUILDDIR)/doctest + @echo "Testing of doctests in the sources finished, look at the " \ + "results in $(BUILDDIR)/doctest/output.txt." + +spelling: + $(SPHINXBUILD) -b spelling source/ build/ \ No newline at end of file diff --git a/docs-rtd/requirements.txt b/docs-rtd/requirements.txt new file mode 100644 index 000000000..5388c8836 --- /dev/null +++ b/docs-rtd/requirements.txt @@ -0,0 +1 @@ +sphinx==5.3.0 diff --git a/docs-rtd/source/ERRATA.rst b/docs-rtd/source/ERRATA.rst new file mode 100644 index 000000000..092b164c5 --- /dev/null +++ b/docs-rtd/source/ERRATA.rst @@ -0,0 +1,83 @@ +F2 Developer Kit Errata +======================= + +Shell Errata +------------ + +Shell errata is `documented here <./hdk/docs/AWS_Shell_ERRATA.md>`__ + +HDK +--- + +1. Support for the XDMA Shell in the HDK design flow is not available at this time. + CL builds using the XDMA Shell will result in a build failure. + +2. CL simulation might show the following "error" message if the `CL + clock generator <./hdk/docs/AWS_CLK_GEN_spec.md>`__ is contained in + the design. By default, the generator blocks all output clocks + (except for ``o_clk_main_a0``) and asserts all output resets. This + behavior violates the built-in reset check in the `AXI SmartConnect + IP `__. + This message can be safely ignored. A Fix for this issue is in + progress. + + .. code:: bash + + # ** Error: [SmartConnect 500-33] s_sc_aresetn should be asserted for at least 16 cycles of m_sc_aclk. tb.card.fpga.CL.CL_HBM.HBM_PRESENT_EQ_1.AXI_CONVERTER_AXI4_AXI3.cl_axi_sc_1x1_i.smartconnect_0.inst.s00_nodes.s00_aw_node.inst.. + +3. CL simulation might show the following "error" message. This message + can be safely ignored. A Fix for this issue is in progress. + + .. code:: bash + + # Initializing memory from data in 'ddr4_ddr_10.mem'. + # Reading data in x8 and bl:8 mode (Change with 'config <4,8,16> <4,8>' in this file). + # 'ddr4_ddr_10.mem' set write data width to x4. + # ERROR: Failed to write data burst length to 16. Only <4,8> are valid. + +4. XSIM simulator does not support a cycle-accurate simulation model for + the HBM IP. We’re observing significantly longer simulation times + compared to VCS and Questa simulators. This is caused by the HBM BFM + used in XSIM. Therefore, running HBM simulation using VCS or Questa + is strongly recommended. + +5. The following hdk tests are not supported in XSIM currently and will + report not supported warning if ran: + + - cl_mem_perf: + + - test_dram_dma_4k_crossing + - test_dram_dma + - test_dram_dma_align_addr_4k + - test_dram_dma_single_beat_4k + - test_dram_dma_rnd + + - cl_dram_hbm_dma: + + - test_dram_dma_4k_crossing + +6. Simulation of the `HBM monitor + interface <./hdk/docs/AWS_Shell_Interface_Specification.md/#hbm-monitor-interface>`__ + is not supported in this release. The HBM IP always passes + initialization and remains in an operating state for all tests. + Simulation support for the HBM monitor will be added in a future + release. + +7. AFIs created based on HDK XDMA shell or Vitis are not supported on F2 + instances at this time. + +8. The following ddr simulation backdoor test is not working with 64GB memory: + + - test_ddr_peek_bdr_walking_ones + +SDK +--- + +Software defined Accelerator Development (Vitis) +------------------------------------------------ + +1. Only hardware emulation via Vitis 2024.1 is currently supported. + +2. Support for Vitis 2024.1 accelerator binary creation and AFI creation is not supported, but will be released at a later time. + +3. Support for Vitis software emulation has been deprecated by AMD, therefore, no longer supported. diff --git a/docs-rtd/source/RELEASE_NOTES.rst b/docs-rtd/source/RELEASE_NOTES.rst new file mode 100644 index 000000000..69577a958 --- /dev/null +++ b/docs-rtd/source/RELEASE_NOTES.rst @@ -0,0 +1,19 @@ +F2 Developer Kit Release Notes +============================== + +.. _v201: + +v2.0.1 +------ + +Updates to HDK, SDK, and Vitis documentation. +Added check for XRT install to enable Vitis hardware emulation. +XRT install can now be performed automatically by running a +command presented during `vitis_setup.sh`. + +.. _v200: + +v2.0.0 +------ + +Initial release. F2 general-availability companion. diff --git a/docs-rtd/source/User_Guide_AWS_EC2_FPGA_Development_Kit.rst b/docs-rtd/source/User_Guide_AWS_EC2_FPGA_Development_Kit.rst new file mode 100644 index 000000000..36b148341 --- /dev/null +++ b/docs-rtd/source/User_Guide_AWS_EC2_FPGA_Development_Kit.rst @@ -0,0 +1,317 @@ +`AWS EC2 FPGA Development Kit `__ +================================================================== + +The development kit includes example designs to get you familiar with +developing for AWS EC2 FPGA Instances. + +- `AWS EC2 FPGA Development Kit <#aws-ec2-fpga-development-kit>`__ + + - `AWS EC2 F2 Instance Overview <#aws-ec2-f2-instance-overview>`__ + + - `Instance Types <#instance-types>`__ + - `2nd Generation On-Cloud FPGA Accelerator + Card <#2nd-generation-on-cloud-fpga-accelerator-card>`__ + - `Comparison to F1 <#comparison-to-f1>`__ + + - `AWS EC2 F2 FPGA Development + Kit <#aws-ec2-f2-fpga-development-kit>`__ + + - `Development Environments <#development-environments>`__ + - `AWS Shells <#aws-shells>`__ + - `Hardware Development Kit (HDK) <#hardware-development-kit-hdk>`__ + - `Software-Defined Development + Environment <#software-defined-development-environment>`__ + + - `Hardware Emulation <#hardware-emulation>`__ + - `Host Application and FPGA Binary + Builds <#host-application-and-fpga-binary-builds>`__ + - `AFI Generation <#afi-generation>`__ + + - `Additional Vitis + Documentation <#additional-vitis-documentation>`__ + - `FPGA Developer AMI <#fpga-developer-ami>`__ + + - `Getting Started <#getting-started>`__ + + - `Getting Familiar with AWS <#getting-familiar-with-aws>`__ + - `Customer Hardware Development <#customer-hardware-development>`__ + + - `Next Steps <#next-steps>`__ + +AWS EC2 F2 Instance Overview +---------------------------- + +Amazon EC2 F2 instances are Amazon’s second-generation FPGA-powered +instances, purpose-built for customers to develop and deploy +reconfigurable hardware in the cloud. With AMD UltraScale+ VU47P FPGAs +and High Bandwidth Memory (HBM), customers can achieve +orders-of-magnitude application acceleration such as 95x faster graph +database analysis and 10x faster genomics secondary analysis when +compared to CPU-only analysis. F2 instances provide up to 8 FPGAs paired +with a 3rd-generation AMD EPYC (Milan) processor. F2 instances provide +3x more processor cores (192 vCPU), 2x more system memory (2 TiB), 2x +NVMe SSDs (7.6 TiB), and 4x more networking bandwidth (100 Gbps), +compared to the previous generation FPGA-based instances. The +accompanying AWS FPGA Developer kit empowers developers to quickly start +building with their hardware accelerations and adopting advanced +technology, such as HBM, to process data at up to 460 GiB/s. + +This documentation is relevant to F2 only. Therefore, it applies to all +branches on the `GitHub repo `__ +prefixed with ``f2``. Any branches not prefixed f2 in their name are not +referred to in this documentation. + +Instance Types +~~~~~~~~~~~~~~ + +|f2_instances| + +.. _2nd-generation-on-cloud-fpga-accelerator-card: + +2nd Generation On-Cloud FPGA Accelerator Card +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +|image1| + +Comparison to F1 +~~~~~~~~~~~~~~~~ + +|f2_f1_comp| + +AWS EC2 F2 FPGA Development Kit +------------------------------- + +Development Environments +~~~~~~~~~~~~~~~~~~~~~~~~ + +This table lists the F2 development flows currently enabled and +supported in the development kit. + +.. list-table:: + :header-rows: 1 + :class: user-guide-dev-envs-table + :widths: 10 50 20 20 10 15 + + * - Development Environment + - Description + - Accelerator Language + - Hardware interface + - Debug Options + - Typical Developer + * - `Hardware accelerator development using Vivado <./hdk/README.html>`__ + - This environment supports the Hardware Development Kit (HDK) design flow, + which empowers FPGA developers to create accelerator designs from scratch, + using HDL source code and IPs. The AMD Vivado tool synthesizes, implements, + and generates the Design Check Point (DCP) file used in F2 AFI creation. + AWS FPGA developers benefit from the suite of scripts supplied in the HDK + that help to automate different design steps. This allows for flexibility + in architecting, implementing, and optimizing accelerator designs while + using the HDK. + - Verilog/System Verilog/VHDL + - User-implemented DMA engine or Streaming Data Engine (SDE) + - Simulation + - Hardware developers with advanced FPGA experience + * - `Hardware accelerator development using Vitis <./vitis/README.html>`__ + - This environment supports the Vitis design flow, + which enables software developers to write C++ code, + which may then be compiled into RTL and used in + cycle-accurate hardware simulation. After it may + then be built into an accelerator design. This step + is not necessary, but is encouraged. Vitis may also + be used to implement accelerator designs from scratch, + using HDL and IPs directly, similar to Vivado. Vitis + offers additional analysis tools to aid in the + refinement of designs. + - C/C++/Verilog/System Verilog/VHDL + - XDMA Engine (coming soon) + - Hardware Emulation + - Advanced software developers or hardware developers + with intermediate to advanced FPGA experiences + +On-premise environment: Customers can set up a on-premise development +environment using 2024.1 AMD tools with their own licenses. Refer to +this guide `here <./hdk/docs/on_premise_licensing_help.html>`__ for +licensing requirements. + +AWS Shells +~~~~~~~~~~ + +For AWS EC2 F2 FPGA instances, each FPGA is divided into two partitions: + +- Shell (SH) – AWS platform logic implementing system management and + external peripherals like PCIe and interrupts to the host. +- Custom Logic (CL) – Custom acceleration logic created by the FPGA + developer and equipped with direct memory access (DMA) to DDR and HBM. + +At the end of the development process, combining the Shell and CL +creates an Amazon FPGA Image (AFI) that is then available to load onto +all F2 FPGA cards on instances owned by the developer. + +The HDK design flow currently supports the Small Shell. The Small Shell +offers 88% usable FPGA resources. The `common +interface <./hdk/docs/AWS_Shell_Interface_Specification.html>`__ (is +defined in +`cl_ports.vh `__) +along with the `floorplans <./hdk/docs/shell_floorplan.html>`__ and +built-in functions. CL designs must integrate with the small shell. The +table below details the released shell version and its main features. + +.. list-table:: + :header-rows: 1 + :class: user-guide-shells-table + :widths: 20 20 60 + + * - Shell Name + - Shell Version + - Description + * - F2 Small Shell + - 0x10212415 + - Shell with no built-in DMA engine (40% smaller shell footprint). + +Hardware Development Kit (HDK) +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The Hardware Development Kit (HDK) comes with an ``hdk_setup.sh`` script +to set up environment variables required for customer design development +using HDL source code. + +The `HDK directory structure <./hdk/README.html>`__ contains: + +- `common/shell_stable `__: All build + scripts, constraints, and other directory structures required to + support design builds using the supported shells. +- `common/lib `__: All common IPs used in various + examples and Tcl scripts to build IPs are available here. +- `cl/examples `__: Multiple CL examples to + demonstrate connectivity between CL logic, the F2 Shell, and + accelerator resources like DDR and HBM. +- Support for 3rd party simulators + +The HDK currently supports the following tool versions: + +.. list-table:: + :header-rows: 1 + :class: user-guide-simulators-table + :widths: 50 30 + + * - Tool + - Version + * - AMD Vivado Design Suite + - 2024.1 + * - Synopsys VCS (Bring your own license) + - U-2023.03-SP2 + * - Siemens Questa (Bring your own license) + - 2023.3 + +Our scripts require a minimum Python version of 3.10, under +``/usr/bin/env python3``: + +.. list-table:: + :header-rows: 1 + :class: user-guide-python-table + :widths: 10 15 + + * - Tool + - Minimum Version + * - Python + - 3.10+ + +Software-Defined Development Environment +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The software-defined development environment allows customers to compile +their C/C++/OpenCL code into AFIs and use C/C++/OpenCL APIs to interface +with the accelerator, running on the FPGA. Software developers with +little or no FPGA experience will be able to quickly familiarize +themselves with the development experience that accelerates cloud +applications. The optimized compiler, Vitis, allows easy F2 accelerator +development using C/C++/OpenCL and/or Verilog/VHDL. + +The F2 developer kit provides development tools for Vitis hardware +emulation, example host applications, and FPGA Binary builds, followed +by AFI generation. + +To get started, please see the `README for a hello world accelerator +example <./vitis/README.html>`__ + +FPGA Developer AMI +~~~~~~~~~~~~~~~~~~ + +A free-to-use FPGA developer AMI is available for on-cloud F2 +development with AMD tools pre-installed on a variety of AWS EC2 +instance types. Customers can use this AMI to design, simulate, and +build their designs. The table below lists the FPGA Developer AMI(s) +currently released to customers: + +.. list-table:: + :header-rows: 1 + :class: user-guide-dev-ami-table + :widths: 20 25 20 30 + + * - FPGA Developer AMI Version + - FPGA Developer AMI ID + - Vivado/Vitis Version Supported + - Operating System Version + * - 1.16.0 + - `ami-0e6383ac30e23cf97 `__ + - 2024.1 + - Ubuntu 20.04.6 (kernel 5.15) + +Given the large size of the FPGA used for F2, AMD tools work best with +at least 4 vCPU’s and 32GiB Memory. We recommend `Compute Optimized and +Memory Optimized instance +types `__ to successfully +run the synthesis of acceleration code. Developers may start coding and +run simulations on low-cost `General Purpose instances +types `__. + +Note that the tools used by the HDK are only supported on x86-based EC2 +instances (Graviton-based instances are not compatible with the tools). + +Getting Started +--------------- + +Getting Familiar with AWS +~~~~~~~~~~~~~~~~~~~~~~~~~ + +If you have never used AWS before, we recommend you start with `AWS +getting started training `__, +focusing on the basics of the `AWS EC2 `__ +and `AWS S3 `__ services. Understanding the +fundamentals of these services will further enhance the developer +experience with AWS F2 instances and the FPGA Developer Kit. + +Next Steps +---------- + +Before you create your own AWS FPGA design, we recommend that you go +through the `step-by-step quickstart guide for customer hardware +development <./hdk/README.html>`__. + +Once developers are familiar with the F2 development kit and the HDK +development environment, we recommend exploring the following contents +to master all the design features and examples offered in the AWS EC2 +FPGA Development Kit: + +- `Run RTL + simulations <./hdk/docs/RTL_Simulation_Guide_for_HDK_Design_Flow.html>`__ + provided in CL examples to learn the design verification setup in the + HDK development environment. +- Familiarize yourself with the `AWS F2 Shell-CL + interfaces <./hdk/docs/AWS_Shell_Interface_Specification.html>`__, e.g. `the HBM monitor + interface <./hdk/docs/AWS_Shell_Interface_Specification.html#hbm-monitor-interface>`__ +- Examine the `shell + floorplan <./hdk/docs/shell_floorplan.html>`__ and locations of major + shell interfaces. +- Deep dive into `CL examples <./hdk/README.html#cl-examples>`__ to + explore shell-to-CL connectivity, CL resources e.g. DDR and HBM, and + features e.g. `CL clock generation + block <./hdk/docs/AWS_CLK_GEN_spec.html>`__. +- Create a custom CL design using the + `CL_TEMPLATE <./hdk/cl/examples/CL_TEMPLATE/README.html>`__ example. +- Connect to a custom CL design in FPGA through `Virtual + JTAG <./hdk/docs/Virtual_JTAG_XVC.html>`__ to run hardware debug. + +.. |f2_instances| image:: ./_static/instance_sizes.png +.. |image1| image:: ./_static/accel_card_specs.png +.. |f2_f1_comp| image:: ./_static/f2_f1_comp.png diff --git a/docs-rtd/source/_static/F2_Shell_interface.png b/docs-rtd/source/_static/F2_Shell_interface.png new file mode 100644 index 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Default is the same as html_title. +#html_short_title = None + +# The name of an image file (relative to this directory) to place at the top +# of the sidebar. +#html_logo = None + +# The name of an image file (within the static path) to use as favicon of the +# docs. This file should be a Windows icon file (.ico) being 16x16 or 32x32 +# pixels large. +#html_favicon = None + +# Add any paths that contain custom static files (such as style sheets) here, +# relative to this directory. They are copied after the builtin static files, +# so a file named "default.css" will overwrite the builtin "default.css". +html_static_path = ['_static'] +html_css_files= ['css/custom.css'] +# If not '', a 'Last updated on:' timestamp is inserted at every page bottom, +# using the given strftime format. +#html_last_updated_fmt = '%b %d, %Y' + +# If true, SmartyPants will be used to convert quotes and dashes to +# typographically correct entities. +#html_use_smartypants = True + +# Custom sidebar templates, maps document names to template names. +#html_sidebars = {} + +# Additional templates that should be rendered to pages, maps page names to +# template names. +#html_additional_pages = {} + +# If false, no module index is generated. +#html_domain_indices = True + +# If false, no index is generated. +#html_use_index = True + +# If true, the index is split into individual pages for each letter. +#html_split_index = False + +# If true, links to the reST sources are added to the pages. +#html_show_sourcelink = True + +# If true, "Created using Sphinx" is shown in the HTML footer. Default is True. +#html_show_sphinx = True + +# If true, "(C) Copyright ..." is shown in the HTML footer. Default is True. +#html_show_copyright = True + +# If true, an OpenSearch description file will be output, and all pages will +# contain a tag referring to it. The value of this option must be the +# base URL from which the finished HTML is served. +#html_use_opensearch = '' + +# This is the file name suffix for HTML files (e.g. ".xhtml"). +#html_file_suffix = None + +# Output file base name for HTML help builder. +htmlhelp_basename = 'F2doc' + + +# -- Options for LaTeX output -------------------------------------------------- + +latex_elements = { +# The paper size ('letterpaper' or 'a4paper'). +#'papersize': 'letterpaper', + +# The font size ('10pt', '11pt' or '12pt'). +#'pointsize': '10pt', + +# Additional stuff for the LaTeX preamble. +#'preamble': '', +} + +# Grouping the document tree into LaTeX files. List of tuples +# (source start file, target name, title, author, documentclass [howto/manual]). +latex_documents = [ + ('index', 'F2.tex', u'F2 Documentation', + copyright), +] + +# The name of an image file (relative to this directory) to place at the top of +# the title page. +#latex_logo = None + +# For "manual" documents, if this is true, then toplevel headings are parts, +# not chapters. +#latex_use_parts = False + +# If true, show page references after internal links. +#latex_show_pagerefs = False + +# If true, show URL addresses after external links. +#latex_show_urls = False + +# Documents to append as an appendix to all manuals. +#latex_appendices = [] + +# If false, no module index is generated. +#latex_domain_indices = True + + +# -- Options for manual page output -------------------------------------------- + +# One entry per manual page. List of tuples +# (source start file, name, description, authors, manual section). +man_pages = [ + ('index', 'f2', u'F2 Documentation', + [copyright], 1) +] + +# If true, show URL addresses after external links. +#man_show_urls = False + + +# -- Options for Texinfo output ------------------------------------------------ + +# Grouping the document tree into Texinfo files. List of tuples +# (source start file, target name, title, author, +# dir menu entry, description, category) +texinfo_documents = [ + ('index', 'F2', u'F2 Documentation', + copyright, 'AWS EC2 F2 Instance Documentation', + 'Miscellaneous'), +] + +# Documents to append as an appendix to all manuals. +#texinfo_appendices = [] + +# If false, no module index is generated. +#texinfo_domain_indices = True + +# How to display URL addresses: 'footnote', 'no', or 'inline'. +#texinfo_show_urls = 'footnote' + + +# Example configuration for intersphinx: refer to the Python standard library. +# intersphinx_mapping = {'http://docs.python.org/': None} diff --git a/docs-rtd/source/developer_resources/DCV.rst b/docs-rtd/source/developer_resources/DCV.rst new file mode 100644 index 000000000..1d1b945a4 --- /dev/null +++ b/docs-rtd/source/developer_resources/DCV.rst @@ -0,0 +1,22 @@ +GUI FPGA Development Environment with NICE DCV +============================================== + +`NICE +DCV `__ +can be used create a virtual desktop on your FPGA Developer AMI +instance. + +`NICE +DCV `__ +is a high-performance remote display protocol that provides customers +with a secure way to deliver remote desktops and application streaming +from any cloud or data center to any device, over varying network +conditions. + +With NICE DCV and Amazon EC2, customers can run graphics-intensive +applications remotely on EC2 instances and stream the results to simpler +client machines, eliminating the need for expensive dedicated +workstations. Customers across a broad range of HPC workloads use NICE +DCV for their remote visualization requirements. Please refer to the +`Official DCV +documentation `__ diff --git a/docs-rtd/source/hdk/README.rst b/docs-rtd/source/hdk/README.rst new file mode 100644 index 000000000..b10c37cc6 --- /dev/null +++ b/docs-rtd/source/hdk/README.rst @@ -0,0 +1,737 @@ +AWS FPGA Hardware Development Kit (HDK) +======================================= + +Table of Contents +----------------- + +- `AWS FPGA Hardware Development Kit + (HDK) <#aws-fpga-hardware-development-kit-hdk>`__ + + - `Table of Contents <#table-of-contents>`__ + - `HDK Overview <#hdk-overview>`__ + - `Getting Started <#getting-started>`__ + + - `Build Accelerator AFI using HDK Design + Flow <#build-accelerator-afi-using-hdk-design-flow>`__ + + - `Step 1. Setup Development + Environment <#step-1-setup-development-environment>`__ + - `Step 2. Clone Developer Kit + Repository <#step-2-clone-developer-kit-repository>`__ + - `Step 3. Setup Environment for HDK Design + Flow <#step-3-setup-environment-for-hdk-design-flow>`__ + - `Step 4. Build CL Design Check Point + (DCP) <#step-4-build-cl-design-check-point-dcp>`__ + - `Step 5. Explore Build + Artifacts <#step-5-explore-build-artifacts>`__ + - `Step 6. Submit Generated DCP for AFI + Creation <#step-6-submit-generated-dcp-for-afi-creation>`__ + - `Step 7. Load Accelerator AFI on F2 + Instance <#step-7-load-accelerator-afi-on-f2-instance>`__ + - `Step 8. Validate your AFI using Example Runtime + Software <#step-8-validate-your-afi-using-example-runtime-software>`__ + + - `CL Examples <#cl-examples>`__ + + - `cl_sde <#cl_sde>`__ + - `cl_dram_hbm_dma <#cl_dram_hbm_dma>`__ + - `cl_mem_perf <#cl_mem_perf>`__ + - `CL_TEMPLATE - Create your own + design <#cl_template---create-your-own-design>`__ + + - `CL Example Hierarchy <#cl-example-hierarchy>`__ + + - `Design <#design>`__ + - `Verification <#verification>`__ + - `Software <#software>`__ + - `Build <#build>`__ + + - `HDK Common Library <#hdk-common-library>`__ + + - `/shell_stable <#shell_stable>`__ + - `/verif <#verif>`__ + - `/ip <#ip>`__ + - `/lib <#lib>`__ + + - `Next Steps <#next-steps>`__ + +HDK Overview +------------ + +The HDK design flow enables developers to create RTL-based accelerator +designs for F2 instances using AMD Vivado. HDK designs must be +integrated with Small Shell, which does not include a built-in Direct +Memory Access (DMA) engine and offers full resources in the top Super +Logic Region (SLR) of the FPGA to developers. + +Getting Started +--------------- + +Build Accelerator AFI using HDK Design Flow +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This section provides a step-by-step guide to build an F2 AFI using the +HDK design flow. The flow starts with an existing Customer Logic (CL) +example design. Steps 1 through 3 demonstrate how to set up the HDK +development environment. Steps 4 through 5 show the commands used to +generate CL Design Checkpoint (DCP) files and other build artifacts. +Steps 6 and 7 demonstrate how to submit the DCP file to generate an AFI +for use on F2 instances. + +.. _step-1-setup-development-environment: + +Step 1. Setup Development Environment +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Developers can either use the AWS-provided developer AMI for F2 or their +on-premise development environment for this demo. + +.. _step-2-clone-developer-kit-repository: + +Step 2. Clone Developer Kit Repository +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. code:: bash + + git clone https://github.com/aws/aws-fpga.git + +.. _step-3-setup-environment-for-hdk-design-flow: + +Step 3. Setup Environment for HDK Design Flow +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The `hdk_setup.sh <../hdk_setup.sh>`__ script needs to be sourced for +each terminal and takes ~2 minutes to complete when first run. + +.. code:: bash + + cd aws-fpga + source hdk_setup.sh + +After the setup is done successfully, you should see +``AWS HDK setup PASSED``. Sourcing ``hdk_setup.sh`` does the following: + +- Verifies a supported Vivado installation +- Sets up all environment variables required by the HDK design flow +- Generates IP simulation models for CL examples +- Downloads all required shell files from a shared S3 bucket + +.. _step-4-build-cl-design-check-point-dcp: + +Step 4. Build CL Design Check Point (DCP) +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +After the HDK design environment is set up, you are ready to build a +design example. Run the following commands to build CL DCP files in +Vivado. This tutorial uses the `cl_sde <./cl/examples/cl_sde/>`__ +example. The same steps can be used for any other `CL +examples <./cl/examples>`__. + +.. code:: bash + + cd hdk/cl/examples/cl_sde + export CL_DIR=$(pwd) + cd build/scripts + ./aws_build_dcp_from_cl.py -c cl_sde + +The Shell supplies two base clocks to the CL: a 250MHz ``clk_main_a0`` clock and +a 100MHz ``clk_hbm_ref`` clock. However, the CL can run at higher frequencies +using locally generated clocks. F2 Developer Kit offers an +`AWS Clock Generation (AWS_CLK_GEN) IP <./docs/AWS_CLK_GEN_spec.html>`__ +that you can leverage in your design to generate CL clocks with frequencies +specified in the `Clock Recipes User Guide <./docs/Clock_Recipes_User_Guide.html>`__. + +Run the command below to build a DCP with desired clock recipes: + +.. code:: bash + + ./aws_build_dcp_from_cl.sh -c cl_mem_perf --aws_clk_gen --clock_recipe_a A1 --clock_recipe_b B2 --clock_recipe_c C0 --clock_recipe_hbm H2 + +**NOTE**: The `cl_sde <./cl/examples/cl_sde/README.html/>`__ example does not contain +the AWS_CLK_GEN component. This command uses the `cl_mem_perf <./cl/examples/cl_mem_perf/README.html/>`__ +example to demonstrate the AWS_CLK_GEN usage. + +A few more notes on +`./aws_build_dcp_from_cl.py `__: + +- Use ``--mode small_shell`` option to build CL designs with Small + Shell. +- Use ``--cl `` option to build a different CL design. This is + default to ``cl_dram_hbm_dma``. +- Use ``--aws_clk_gen`` option to annotate the use of `AWS clock + generation block <./hdk/docs/AWS_CLK_GEN_spec.md>`__ and `customer + clock recipes <./hdk/docs/Clock_Recipes_User_Guide.md>`__. +- The script also allows developers to pass different Vivado directives + as shown below: + + - ``--place ``: Default to ``SSI_SpreadLogic_high`` + placement strategy. Please refer to `Vivado User + Guide `__ + for supported directives. + - ``--phy_opt `` : Default to ``AggressiveExplore`` + physical optimization strategy. Please refer to `Vivado User + Guide `__ + for supported directives + - ``--route `` : Default to ``AggressiveExplore`` routing + strategy. Please refer to `Vivado User + Guide `__ + for supported directives. + +- Run ``./aws_build_dcp_from_cl.py --help`` to see more build options + available in building CL designs. + +.. _step-5-explore-build-artifacts: + +Step 5. Explore Build Artifacts +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +While Vivado is running, a build log file +``YYYYY_MM_DD-HHMMSS.vivado.log`` will be created in +``$CL_DIR/build/scripts`` to track the build’s progress. DCP build times +will vary based on the design size and complexity. The examples in the +development kit take between 30 to 90 minutes to build. After the design +is finished building, the following information will be shown at the +bottom of the log file: + +.. code:: bash + + tail + + ... + AWS FPGA: (16:05:44): Finished building design checkpoints for customer design cl_sde + ... + INFO: [Common 17-206] Exiting Vivado at ... + +Generated post-route DCP and design manifest files are archived into a +tarball file ``.Developer_CL.tar`` and saved in the +``$CL_DIR/build/checkpoints/`` directory. All design timing reports are +saved in the ``$CL_DIR/build/reports/`` directory. + +⚠️ If Vivado cannot achieve timing closure for the design, the +post-route DCP file name will be marked with ``.VIOLATED`` as an +indicator. Developers need to refer to the DCPs and timing reports for +detailed timing failures. + +⚠️ The build process will generate a DCP tarball file regardless of the +design’s timing closure state. However, in case of a DCP with timing +failures, the design’s functionality is no longer guaranteed. Therefore, +the AFI created using this DCP should be used for testing purpose ONLY. +The following warning is shown in this case: + +.. code:: text + + !!! WARNING: Detected a post-route DCP with timing failure for AFI creation. Design functionalities are NOT guaranteed. + +.. _step-6-submit-generated-dcp-for-afi-creation: + +Step 6. Submit Generated DCP for AFI Creation +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +To submit the DCP, create an S3 bucket and upload the DCP tarball file +to the bucket. DCP submission requires the following information: + +- Name of the design (Optional). +- Generic description of the logic design (Optional). +- Destination location of the tarball file object in your S3 bucket. +- Destination location of an S3 directory where AWS can save the logs + for your AFI’s creation. + +To upload your tarball file to S3, you can use any of `the tools +supported by +S3 `__. + +For example, you can use the AWS CLI as follows: + +Create a bucket and folder for your tarball, then copy to S3. + +Currently, ``us-east-1`` and ``eu-west-2`` are available as ``REGION`` +options. + +.. code:: bash + + export DCP_BUCKET_NAME='' + export DCP_FOLDER_NAME='' + export REGION='us-east-1' + export DCP_TARBALL_TO_INGEST='<$CL_DIR/build/checkpoints/to_aws/YYYY_MM_DD-HHMMSS.Developer_CL.tar>' + + # Create an S3 bucket (choose a unique bucket name) + aws s3 mb s3://${DCP_BUCKET_NAME} --region ${REGION} + # Create folder for your tarball files + aws s3 mb s3://${DCP_BUCKET_NAME}/${DCP_FOLDER_NAME}/ + # Upload the file to S3 + aws s3 cp ${DCP_TARBALL_TO_INGEST} s3://${DCP_BUCKET_NAME}/${DCP_FOLDER_NAME}/ + +**NOTE**: The trailing '/' is required after ``${DCP_FOLDER_NAME}`` + +Create a folder for your log files + +.. code:: bash + + export LOGS_BUCKET_NAME='' + export LOGS_FOLDER_NAME='' + + # Create a folder to keep your logs + aws s3 mb s3://${LOGS_BUCKET_NAME}/${LOGS_FOLDER_NAME}/ --region ${REGION} + # Create a temp file + touch LOGS_FILES_GO_HERE.txt + # Create the folder on S3 + aws s3 cp LOGS_FILES_GO_HERE.txt s3://${LOGS_BUCKET_NAME}/${LOGS_FOLDER_NAME}/ + +**NOTE**: The trailing '/' is required after ``${LOGS_FOLDER_NAME}`` + +The output of this command includes two identifiers for your AFI: + +.. code:: bash + + export DCP_TARBALL_NAME=$(basename ${DCP_TARBALL_TO_INGEST}) + export CL_DESIGN_NAME='' + export CL_DESIGN_DESCRIPTION='Description of ${CL_DESIGN_NAME}' + + # Call AWS CLI ingestion command + aws ec2 create-fpga-image --name ${CL_DESIGN_NAME} --description "${CL_DESIGN_DESCRIPTION}" --input-storage-location Bucket=${DCP_BUCKET_NAME},Key=${DCP_FOLDER_NAME}/${DCP_TARBALL_NAME} --logs-storage-location Bucket=${LOGS_BUCKET_NAME},Key=${LOGS_FOLDER_NAME}/ --region ${REGION} + + { + "FpgaImageId": "afi-09953582f46c45b17", + "FpgaImageGlobalId": "agfi-0925b211f5a81b071" + } + +- ``FpgaImageId`` or AFI ID: This is the main ID used to manage + developer’s AFI through the AWS EC2 CLI and AWS SDK APIs. This ID is + regional, i.e., if an AFI is copied across multiple regions, it will + have a different, unique AFI ID in each region. + +- ``FpgaImageGlobalId`` or AGFI ID: This is a global ID used to refer to + an AFI from within an F2 instance. For example, to load or clear an + AFI from an FPGA slot, developers need to use the AGFI ID. Since the + AGFI IDs is global (by design), it allows developers to copy a + combination of AFI/AMI to multiple regions and they will work without + any extra setup. + +The ``describe-fpga-images`` command allows developers to check the +AFI’s state while the AFI creation process runs in the background. The +AFI ID returned by the ``create-fpga-image`` command must be provided. +The AFI is ready to be deployed once the creation completes and the +state code returned is ``available``. + +.. code:: bash + + aws ec2 describe-fpga-images --fpga-image-ids afi-09953582f46c45b17 --region us-east-1 + + ... + + { + "FpgaImages": [ + { + "FpgaImageId": "afi-09953582f46c45b17", + "FpgaImageGlobalId": "agfi-0925b211f5a81b071", + "Name": "cl_sde_0x10212415", + "Description": "Latest devkit build of cl_sde with 0x10212415 small shell release", + ... + "State": { + "Code": "available" + }, + ... + } + ] + } + +.. _step-7-load-accelerator-afi-on-f2-instance: + +Step 7. Load Accelerator AFI on F2 Instance +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Now that your AFI is available, it can be tested on an F2 instance. The +instance can be launched using any preferred AMI, private or public, +from the AWS Marketplace catalog. AWS recommends using AMIs with Ubuntu +20.04 and kernel version 5.15. + +Now you need to install the FPGA Management tools by sourcing the +``sdk_setup.sh`` script: + +.. code:: bash + + cd aws-fpga + source sdk_setup.sh + +Once the tools are installed, you can load the AFI onto a slot on the F2 +instance. It is a good practice to clear any previously loaded AFI from +that slot: + +.. code:: bash + + $ sudo fpga-clear-local-image -S 0 + AFI 0 No AFI cleared 1 ok 0 0x10212415 + AFIDEVICE 0 0x1d0f 0x9048 0000:00:1e.0 + +You can also invoke the ``fpga-describe-local-image`` command to learn +which AFI, if any, is loaded onto a particular slot. For example, if the +slot is cleared (``slot 0`` in this example), you should get an output +similar to the following: + +.. code:: bash + + $ sudo fpga-describe-local-image -S 0 -H + Type FpgaImageSlot FpgaImageId StatusName StatusCode ErrorName ErrorCode ShVersion + AFI 0 No AFI cleared 1 ok 0 0x10212415 + Type FpgaImageSlot VendorId DeviceId DBDF + AFIDEVICE 0 0x1d0f 0x9048 0000:00:1e.0 + +If ``fpga-describe-local-image`` API call returns a status ``busy``, the +FPGA is still performing the previous operation in the background. +Please wait until the status is ``cleared`` as above. + +Now, let’s load your AFI onto the FPGA on ``slot 0``: + +.. code:: bash + + $ sudo fpga-load-local-image -S 0 -I agfi-0925b211f5a81b071 + AFI 0 agfi-0925b211f5a81b071 loaded 0 ok 0 0x10212415 + AFIDEVICE 0 0x1d0f 0x9048 0000:00:1e.0 + +**NOTE**: *The FPGA Management tools use the AGFI ID (not the AFI ID).* + +Now, you can verify that the AFI was loaded properly. The output shows +the FPGA in the ``loaded`` state after the FPGA image “load” operation. +The ``-R`` option performs a PCI device remove and rescan in order to +expose the unique AFI Vendor and Device Id. + +.. code:: bash + + Type FpgaImageSlot FpgaImageId StatusName StatusCode ErrorName ErrorCode ShVersion + AFI 0 agfi-0925b211f5a81b071 loaded 0 ok 0 0x10212415 + Type FpgaImageSlot VendorId DeviceId DBDF + AFIDEVICE 0 0x1d0f 0x9048 0000:00:1e.0 + +.. _step-8-validate-your-afi-using-example-runtime-software: + +Step 8. Validate your AFI using Example Runtime Software +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Each CL example includes a runtime software binary, located in the +``$CL_DIR/software/runtime/`` subdirectory. Executing the software +requires the corresponding AFI to be loaded onto the FPGA. This step +demonstrates runtime software execution using the ``CL_SDE`` example. + +.. code:: bash + + # Ensure the $CL_DIR is pointing to the CL_SDE example directory + $ cd $CL_DIR/software/runtime/ + $ make + + ... + + Logical Core 1 (socket 0) forwards packets on 1 streams: + RX P=0/Q=0 (socket 0) -> TX P=0/Q=0 (socket 0) peer=02:00:00:00:00:00 + + io packet forwarding packets/burst=32 + nb forwarding cores=1 - nb forwarding ports=1 + port 0: RX queue number: 1 Tx queue number: 1 + Rx offloads=0x0 Tx offloads=0x0 + RX queue: 0 + RX desc=0 - RX free threshold=0 + RX threshold registers: pthresh=0 hthresh=0 wthresh=0 + RX Offloads=0x0 + TX queue: 0 + TX desc=0 - TX free threshold=0 + TX threshold registers: pthresh=0 hthresh=0 wthresh=0 + TX offloads=0x0 - TX RS bit threshold=0 + Press enter to exit + + Telling cores to stop... + Waiting for lcores to finish... + + ---------------------- Forward statistics for port 0 ---------------------- + RX-packets: 10771136 RX-dropped: 0 RX-total: 10771136 + TX-packets: 8160479 TX-dropped: 2610689 TX-total: 10771168 + ---------------------------------------------------------------------------- + + +++++++++++++++ Accumulated forward statistics for all ports+++++++++++++++ + RX-packets: 10771136 RX-dropped: 0 RX-total: 10771136 + TX-packets: 8160479 TX-dropped: 2610689 TX-total: 10771168 + ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + + Done. + + Stopping port 0... + Stopping ports... + Done + + Shutting down port 0... + Closing ports... + Done + + Bye... + +CL Examples +----------- + +All examples have the following features: + +- Simulation model, tests, and scripts +- Xilinx Vivado implementation scripts for generating bitstream + +`cl_sde <./cl/examples/cl_sde>`__ +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The cl_sde example implements the Streaming Data Engine (SDE) IP block +into FPGA custom logic to demonstrate the `Virtual Ethernet +Application <../sdk/apps/virtual-ethernet/README.md>`__. + +See `cl_sde <./cl/examples/cl_sde>`__ for more information + +`cl_dram_hbm_dma <./cl/examples/cl_dram_hbm_dma>`__ +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The cl_dram_hbm_dma example demonstrates the use and connectivity for +many of the Shell/CL interfaces and functionality. The OCL (AXI-Lite) +interface is used for general configuration, the PCIS (AXI4) interface +is used for data traffic from the host to DDR and HBM DRAM channels in +the CL (initiated by the host), and the PCIM (AXI4) interface is used +for data traffic between the host and the CL (initiated by the CL). + +See `cl_dram_hbm_dma <./cl/examples/cl_dram_hbm_dma>`__ for more +information + +`cl_mem_perf <./cl/examples/cl_mem_perf>`__ +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The cl_mem_perf is a reference design for F2 where the objective is to +demonstrate fine tuned data paths to HBM and DDR to achieve maximum +throughput to the memories. The example also demonstrates datapath +connectivity between Host, AWS Shell, Custom Logic (CL) region in the +FPGA, HBM and DDR DIMM on the FPGA card. + +See `cl_mem_perf <./cl/examples/cl_mem_perf>`__ for more information + +`CL_TEMPLATE <./cl/examples/CL_TEMPLATE>`__ - Create your own design +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +CL_TEMPLATE is targeted to help customers create a new CustomLogic +example. Users can update the design, verification, and build flow to +meet their needs without having to tear down a separate example. We +recommend going through other CL examples before creating a new CL. + +All of the design files and tests can be compiled, simulated, built, and +deployed on hardware (without any modifications). Users can add/update +design files, add new verification tests, and add new build directives +to meet their needs. + +A full guide on creating your own CL design can be found in +`CL_TEMPLATE <./cl/examples/CL_TEMPLATE>`__ + +To create a new CL example: + +.. code:: bash + + export NEW_CL_NAME='New CL Name' + cd hdk/cl/examples + ./create_new_cl.py --new_cl_name ${NEW_CL_NAME} + +CL Example Hierarchy +-------------------- + +The following sections describe common functionality across all CL +examples. `CL_TEMPLATE <./CL_TEMPLATE>`__ can be used as a reference for +what features are available in all CL examples; as well as what's +required to verify, test, and build. + +Design +~~~~~~ + +- All CL examples store the design files under + ``/hdk/cl/examples/$CL_DIR/design/`` + + - For example: + `/hdk/cl/examples/CL_TEMPLATE/design/ <./cl/examples/CL_TEMPLATE/design/>`__ + +- All IP designs available by default are stored in + `/hdk/common/ip/cl_ip <./common/ip/>`__ + + - More can be added from the Xilinx Vivado IP catalog + +Verification +~~~~~~~~~~~~ + +- All CL examples utilize infrastructure found under + `/hdk/common/verif/ <./common/verif>`__ +- Simulation libraries are generated under + ``/hdk/common/verif/ip_simulation_libraries/`` +- All examples should list out the + ``/hdk/cl/examples/$CL_DIR/verif/tests/`` and ``Makefile.tests`` + + - For example + `/hdk/cl/examples/CL_TEMPLATE/verif/tests/ <./cl/examples/CL_TEMPLATE/verif/tests/>`__ + - and ` <./cl/examples/CL_TEMPLATE/verif/scripts/Makefile.tests>`__ + +- All HDK examples support a SH_DDR with 64GB access with an optional + user controlled auto-precharge mode. Users can select the DDR access + modes as follows: + +.. code:: bash + + export TEST_NAME=test_ddr + + # To Run simulations with a 64 GB DDR DIMM + make TEST=${TEST_NAME} USE_64GB_DDR_DIMM=1 + + # To Run simulations with a 64 GB DDR DIMM and DDR core with user controlled auto-precharge mode + make TEST=${TEST_NAME} USE_AP_64GB_DDR_DIMM=1 + +**NOTE**: Please refer to +`Supported_DDR_Modes.md <./docs/Supported_DDR_Modes.md>`__ for details +on supported DDR configurations. + +After adding new design IPs, make sure to add the new simulation +``COMMON_LIBLISTS`` in +`$AWS-FPGA/hdk/common/verif/tb/scripts/Makefile.common.inc <./common/verif/tb/scripts/Makefile.common.inc>`__ + +⚠️ **Required for XSIM and Questa simulations** + +- Make sure to add the new simulation libraries to ``COMMON_LIBLISTS`` + in + `$AWS_FPGA_REPO_DIR/hdk/common/verif/tb/scripts/Makefile.common.inc <./common/verif/tb/scripts/Makefile.common.inc>`__ + + - This is required for XSIM and Questa simulations + - These libraries can be found in + `$AWS_FPGA_REPO_DIR/hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts <./common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts>`__ + followed by ``"IP_NAME"/"SIMULATOR"/"IP_NAME".sh`` + +- After adding new IP's to + `$AWS_FPGA_REPO_DIR/hdk/common/ip <./common/ip>`__ the simulation + libraries need to be recompiled + + - Run ``make regenerate_sim_libs =1`` + +Software +~~~~~~~~ + +All software runtime code can be found under the ``software`` directory. + +Build +~~~~~ + +- All CL examples utilize infrastructure found under + `$AWS_FPGA_REPO_DIR/hdk/common/shell_stable/build <./common/shell_stable/build>`__ +- Users can modify the following files to meet their build requirements: + + - `synth_CL_NAME.tcl <./cl/examples/CL_TEMPLATE/build/scripts/synth_CL_TEMPLATE.tcl>`__ + - top level script that reads design, IP, and constraint files + - `cl_synth_user.xdc <./cl/examples/CL_TEMPLATE/build/constraints/cl_synth_user.xdc>`__ + - synthesis build constraints specific to that example + - `cl_timing_user.xdc <./cl/examples/CL_TEMPLATE/build/constraints/cl_timing_user.xdc>`__ + - timing build constraints specific to that example + - `small_shell_cl_pnr_user.xdc <./cl/examples/CL_TEMPLATE/build/constraints/small_shell_cl_pnr_user.xdc>`__ + - place and route constraints specific to that example's small shell + build + +For more information on +`synth_CL_NAME.tcl <./cl/examples/CL_TEMPLATE/build/scripts/synth_CL_TEMPLATE.tcl>`__ +see: + +- `synth_cl_header.tcl <./common/shell_stable/build/scripts/synth_cl_header.tcl>`__ +- `synth_cl_footer.tcl <./common/shell_stable/build/scripts/synth_cl_footer.tcl>`__ + +After adding new design IPs: + +- Make sure to add the new ``.xci`` files to your `synthesis TCL + script <./cl/examples/CL_TEMPLATE/build/scripts/synth_CL_TEMPLATE.tcl>`__ + +HDK Common Library +------------------ + +This directory includes the shell versions, scripts, timing constraints +and compile settings required during the AFI generation process. + +Developers should not modify or remove these files. + +`/shell_stable <./common/shell_stable>`__ +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The `shell_stable <./common/shell_stable>`__ contains all the IPs, +constraints and scripts for each shell release. + +`/verif <./hdk/verif>`__ +~~~~~~~~~~~~~~~~~~~~~~~~ + +The `verif directory <./common/verif>`__ includes reference verification +modules to be used as Bus Functional Models (BFM) as the external +interface to simulate the CL. The verification related files common to +all the CL examples are located in this directory. It has models, +include, scripts, tb directories. + +The `verif models directory <./common/verif/models>`__ includes simple +models of the DRAM interface around the FPGA, shell, and card. You can +also find Xilinx protocol checkers in this directory. + +The `verif scripts directory <./common/verif/scripts>`__ includes +scripts needed to generate DDR models and other scripts needed for HDK +setup. + +The `verif include directory <./common/verif/include>`__ includes +sh_dpi_tasks.vh needed for DPI-C. + +The `verif tb directory <./common/verif/tb>`__ includes top level test +bench related files common for all the CL examples. + +The verif ip_simulation_libraries directory is created during runtime +and includes the simulation libraries and CL IP compilation for all +supported simulators. + +`/ip <./common/ip>`__ +~~~~~~~~~~~~~~~~~~~~~ + +The `ip directory <./common/ip>`__ includes basic IP that is used by +CL's. + +`/lib <./common/lib>`__ +~~~~~~~~~~~~~~~~~~~~~~~ + +The `lib directory <./common/lib>`__ includes basic "library" elements +that may be used by CL's. + +- aws_clk_gen.sv - Generate clocks and resets to the CL design +- aws_clk_regs.sv - Houses all the Control/Status Regs for AWS_CLK_GEN + design +- axi_clock_conv.sv - AXI-4 bus clock converter +- axil_to_cfg_cnv.sv - Convert AXIL transaction into a simple CFG bus +- axis_flop_fifo.sv - Flop based FIFO for AXI-Stream protocol +- bram_1w1r.sv - BRAM (1 write/1 read port) RTL model. +- bram_wr2.sv - BRAM (2 read/write ports) RTL model. +- ccf_ctl.v - Clock crossing FIFO control block (pointers, address + generation, etc...) +- cdc_async_fifo.sv - Async FF-based FIFO for CDC +- cdc_sync.sv - Single- or Multi-bit Synchronizer based on Xilinx XPM +- flop_ccf.sv - Flop based clock crossing FIFO. +- flop_fifo.sv - Flop based FIFO. +- flop_fifo_in.sv - Flop based FIFO, where input is flopped by common + flops (can be used for input signal registering). +- ft_fifo.v - Flow through FIFO. +- ft_fifo_p.v - Flow through FIFO to be used with pipelined RAM. +- gray.inc - Gray code +- hbm_wrapper.sv - Wrapper for HBM IP +- interfaces.sv - Generic interfaces (AXI-4, AXI-L, etc...) +- lib_pipe.sv - Pipeline block. +- macros.svh - Instantiation macros (AXI-4, AXI-L, etc...) +- mgt_acc_axl.sv - Used by AWS provided sh_ddr.sv +- mgt_gen_axl.sv - Used by AWS provided sh_ddr.sv +- ram_fifo_ft.sv - Ram based FIFO +- rr_arb.sv - Round robin arbiter. +- srl_fifo.sv - Shift register based fifo. +- sync.v - Synchronizer +- xpm_fifo.sv - Synchronous clock FIFO + +.. _getting-started-1: + +Getting Started +--------------- + +- Review the + `cl_dram_hbm_dma <./cl/examples/cl_dram_hbm_dma/README.md>`__ and + `cl_sde <./cl/examples/cl_sde>`__ examples +- `Run RTL + Simulations <./docs/RTL_Simulation_Guide_for_HDK_Design_Flow.md>`__ on + the example designs +- Dive deep into `Shell interface + specifications <./docs/AWS_Shell_Interface_Specification.md>`__ and + `PCIe Memory map <./docs/AWS_Fpga_Pcie_Memory_Map.md>`__ +- Create your own designs/Port F1 designs to F2 systems. diff --git a/docs-rtd/source/hdk/cl/CHECKLIST_BEFORE_BUILDING_CL.rst b/docs-rtd/source/hdk/cl/CHECKLIST_BEFORE_BUILDING_CL.rst new file mode 100644 index 000000000..9efa77968 --- /dev/null +++ b/docs-rtd/source/hdk/cl/CHECKLIST_BEFORE_BUILDING_CL.rst @@ -0,0 +1,18 @@ +Checklist Before Building +========================= + +This checklist includes important items that the developer should check before +building a CL Design Check Point (DCP) file for AFI generation. + +1. Verify that the environment variables ``$HDK_SHELL_DIR`` and ``$CL_DIR`` are + set correctly. + +2. Verify that the ``$CL_DIR`` directory has a ``/build`` sub-directory. + +3. Update ``$CL_DIR/build/script/encrypt.tcl`` script for your design specific + changes, including the list of all the source files (including header files + like .inc and .h/.vh), so they all get copied to ``src_post_encryption`` + directory + +4. Update the timing and placement constraints under + ``$CL_DIR/build/constraints`` for your design specific changes. diff --git a/docs-rtd/source/hdk/cl/examples/CL_TEMPLATE/README.rst b/docs-rtd/source/hdk/cl/examples/CL_TEMPLATE/README.rst new file mode 100644 index 000000000..460535bd5 --- /dev/null +++ b/docs-rtd/source/hdk/cl/examples/CL_TEMPLATE/README.rst @@ -0,0 +1,422 @@ +CL_TEMPLATE +=========== + +Table of Content +---------------- + +- `Overview <#overview>`__ +- `Features <#features>`__ + + - `Design <#design>`__ + - `Verification <#verification>`__ + - `Software <#software>`__ + - `Build <#Build>`__ + +- `CL Template Quick Start Guide <#cl_template-quick-start-guide>`__ + +Overview +-------- + +CL_TEMPLATE is targeted to help customers create a new CustomLogic +example. Developers can update the design, verification, and build flow +to meet their needs without having to tear down a separate example. We +recommend going through other CL examples before creating a new CL. + +All of the design files and tests can be compiled, simulated, built, and +deployed on hardware (without any modifications). Developers can +add/update design files, add new verification tests, and create new +build directives to meet their needs. + +**To quickly add in design files and test:** + +1. Run ``source hdk_setup.sh`` from the top of ``$AWS_FPGA_REPO_DIR/`` +2. Run ``cd hdk/cl/examples`` and + ``./create_new_cl.py --new_cl_name `` +3. Run ``cd `` and ``export CL_DIR=$PWD`` +4. Place all design files into ``$CL_DIR/design`` (overwriting the + existing .sv file) +5. Simulate with + ``cd $CL_DIR/verif/scripts and make _base_test =1`` + +Features +-------- + +Design +~~~~~~ + +CL_TEMPLATE contains the minimum required set of design files. All +examples require a SystemVerilog file (.sv) named after the CL example +and a Verilog header file (.vh) with required defines. + +⚠️ ``cl_id_defines.vh`` is used in the design manifest file generation. +Therefore, this file is required for all CL designs. + +`CL_TEMPLATE.sv <./design/CL_TEMPLATE.sv>`__ with the following: + +- CL port connections with signal tie downs to avoid simulation errors +- SH_DDR (change ``.EN_DDR(0)`` to ``.EN_DDR(1)`` to elaborate the DDR + interface) +- ``CL_SH_ID0`` and ``CL_SH_ID1`` connections (see the defines below) + +`cl_id_defines.vh <./design/cl_id_defines.vh>`__ with the following +defines: + +- ``CL_SH_ID0`` +- ``CL_SH_ID1`` + +`CL_TEMPLATE_defines.vh <./design/CL_TEMPLATE_defines.vh>`__ with the +following defines: + +- ``CL_NAME`` + + - See `fpga.sv <./../../../common/verif/models/fpga/fpga.sv>`__ for + details + +Customers can add all other design files and replace these default files +with their own. + +Verification +~~~~~~~~~~~~ + +All examples use the same SystemVerilog `test +bench <./../../../common/verif/tb/sv/tb.sv>`__. The common verification +files can be found under +`:math:`AWS_FPGA_REPO_DIR/hdk/common/verif](./../../../common/verif). This includes a [common Makefile flow](./../../../common/verif/tb/scripts) that expects a [Makefile.tests](./verif/scripts/Makefile.tests) file that exposes Makefile targets for each test located under [`\ CL_DIR/verif/tests <./verif/tests>`__. + +This CL_TEMPLATE example includes a single `base +test <./verif/tests/CL_TEMPLATE_base_test.sv>`__ that will allow all +files to be compiled, elaborated, and quickly simulated to expose any +protocol violations. A `top.SIMULATOR.f <./verif/scripts/top.xsim.f>`__ +file is required for each simulator in use. These file lists are auto +generated by default (including all SystemVerilog source files found +under the `./design <./design>`__ directory). Manual updates are +required for design files or verification infrastructure developed +outside of the `design <./design>`__ or `verif <./verif>`__ directories. +Each example builds on top of the `common file +lists <./../../../common/verif/tb/filelists>`__. + +Required script files: + +- `Makefile <./verif/scripts/Makefile>`__ +- `Makefile.tests <./verif/scripts/Makefile.tests>`__ +- `top.xsim.f <./verif/scripts/top.xsim.f>`__ +- `waves.tcl <./verif/scripts/waves.tcl>`__ (for XSIM only) +- `top.vcs.f <./verif/scripts/top.vcs.f>`__ +- `top.questa.f <./verif/scripts/top.questa.f>`__ + +For more information on test bench architecture and functionality: + +- Base testbench: + `$AWS_FPGA_REPO_DIR/hdk/common/verif/tb/sv/tb.sv <./../../../common/verif/tb/sv/tb.sv>`__ +- Basic shell DPI tasks: + `$AWS_FPGA_REPO_DIR/hdk/common/verif/include/sh_dpi_tasks.svh <./../../../common/verif/include/sh_dpi_tasks.svh>`__ + + - Accessible from the ``tb`` hierarchy + (``tb.poke_ocl(.addr(64'h100), .data(32'h0)``) + +- Basic test tasks: + `$AWS_FPGA_REPO_DIR/hdk/common/verif/include/common_base_test.svh <./../../../common/verif/include/common_base_test.svh>`__ + + - The `base test <./verif/tests/CL_TEMPLATE_base_test.sv>`__ uses + ``report_pass_fail_status()`` + +- Required config files for HBM simulation (not supported in XSIM): + `$AWS_FPGA_REPO_DIR/hdk/common/verif/include/xpm\_\* <./../../../common/verif/include/>`__ + +Co-Simulation with C tests is not yet supported. + +Software +~~~~~~~~ + +CL_TEMPLATE does not yet support stand alone software tests. Please +refer to other examples such as +`CL_DRAM_HBM_DMA <./../cl_dram_hbm_dma#software>`__ + +Build +~~~~~ + +The build flow is identical to all other examples: + +1. Populate the `constraint files <./build/constraints>`__ as needed +2. Update + `synth_CL_TEMPLATE.tcl <./build/scripts/synth_CL_TEMPLATE.tcl>`__ + with relevant IP's, constraints, etc. +3. Run `aws_build_dcp_from_cl.py + <../../../common/shell_stable/build/scripts/aws_build_dcp_from_cl.py>`__. + + - Run ``aws_build_dcp_from_cl.py --help`` for more details. + +See the following ``tcl`` scripts for more details on the build flow +(they are sourced in +`synth_CL_TEMPLATE.tcl <./build/scripts/synth_CL_TEMPLATE.tcl>`__): + +- `$AWS_FPGA_REPO_DIR/hdk/common/shell_stable/build/scripts/synth_cl_header.tcl <./../../../common/shell_stable/build/scripts/synth_cl_header.tcl>`__ +- `$AWS_FPGA_REPO_DIR/hdk/common/shell_stable/build/scripts/synth_cl_footer.tcl <./../../../common/shell_stable/build/scripts/synth_cl_footer.tcl>`__ + +Required build scripts: + +- `aws_build_dcp_from_cl.py <./../../../common/shell_stable/build/scripts/aws_build_dcp_from_cl.py>`__ + (symlink) - Python script to run builds +- `build_all.tcl <./../../../common/shell_stable/build/scripts/build_all.tcl>`__ + (symlink) - Common build script used across examples +- `build_level_1_cl.tcl <./../../../common/shell_stable/build/scripts/build_level_1_cl.tcl>`__ + (symlink) - Common build script used across examples +- `encrypt.tcl <./../../../common/shell_stable/build/scripts/encrypt.tcl>`__ + (symlink) - Common build script used across examples to encrypt design + files +- `synth_CL_TEMPLATE.tcl <./build/scripts/synth_CL_TEMPLATE.tcl>`__ - + Refer to `STEP 5: Build and Deploy the + Design <#step-5-build-and-deploy-the-design>`__ below for more + information. + +AWS has integrated basic constraints required across example designs. +These constraint files can be found in +`$AWS_FPGA_REPO_DIR/hdk/common/shell_stable/build/constraints <./../../../common/shell_stable/build/constraints>`__ + +Required constraint files: + +- `cl_synth_user.xdc <./build/constraints/cl_synth_user.xdc>`__ - Custom + constraints applied to the synthesizer (called in + `synth_CL_TEMPLATE.tcl <./build/scripts/synth_CL_TEMPLATE.tcl>`__) +- `cl_timing_user.xdc <./build/constraints/cl_timing_user.xdc>`__ - + Custom timing constraints applied to the synthesizer (called in + `synth_CL_TEMPLATE.tcl <./build/scripts/synth_CL_TEMPLATE.tcl>`__) +- `small_shell_cl_pnr_user.xdc <./build/constraints/small_shell_cl_pnr_user.xdc>`__ + - Floorplan constraints for the CL design when building with + SMALL_SHELL. See `CL_DRAM_HBM_DMA's + constraints <./../cl_dram_hbm_dma/build/constraints/small_shell_cl_pnr_user.xdc>`__ + for reference. +- `xdma_shell_cl_pnr_user.xdc <./build/constraints/xdma_shell_cl_pnr_user.xdc>`__ + - Floorplan constraints for the CL design when building with + XDMA_SHELL. See `CL_DRAM_HBM_DMA's + constraints <./../cl_dram_hbm_dma/build/constraints/xdma_shell_cl_pnr_user.xdc>`__ + for reference. + +For more information on how to populate the constraint files and build +scripts, please refer to other examples such as +`CL_DRAM_HBM_DMA <./../cl_dram_hbm_dma/build>`__. + +CL_TEMPLATE Quick Start Guide +----------------------------- + +The HDK top level `Quick Start Guide <./../../../README.html#getting-started>`__ +will provide an introduction to this guide. + +STEP 1: Create a New CL +~~~~~~~~~~~~~~~~~~~~~~~ + +The first step is to copy this example into a new directory and replace all +references to CL_TEMPLATE with the new example name. To automatically create +your own example, run `create_new_cl.py <./../create_new_cl.py>`__ from the +``$AWS_FPGA_REPO_DIR/hdk/cl/examples`` directory + +.. code:: bash + + # CL names are typically all lowercase + export NEW_CL_NAME='' + cd $AWS_FPGA_REPO_DIR/hdk/cl/examples + ./create_new_cl.py --new_cl_name ${NEW_CL_NAME} + +Or run these shell commands + +.. code:: bash + + export NEW_CL_NAME='' + + # Everything below can be copied and pasted into a bash terminal + CL_TEMPLATE=CL_TEMPLATE + echo "Creating $CL_TEMPLATE directory" + cp -r $CL_TEMPLATE $NEW_CL_NAME + + echo "Replacing CL_TEMPLATE with $CL_TEMPLATE in all files" + grep -rl $CL_TEMPLATE $NEW_CL_NAME | xargs sed -i "s/$CL_TEMPLATE/$NEW_CL_NAME/g" + + echo "Updating CL_TEMPLATE with $CL_TEMPLATE in all file names" + CL_TEMPLATE=$CL_TEMPLATE NEW_CL_NAME=$NEW_CL_NAME find $NEW_CL_NAME -name "*$CL_TEMPLATE*" -exec sh -c 'mv "$0" "${$0/$CL_TEMPLATE/$NEW_CL_NAME}"' {} \; + +The result will be a directory containing everything in CL_TEMPLATE +(renamed to the new CL name) with functional tools and scripts. Please +note that these files need to be manually updated to include any design +specific changes. + +STEP 2: Add Design Files +~~~~~~~~~~~~~~~~~~~~~~~~ + +All CL design files should be placed under the `design <./design>`_ directory. +Please see the `Design <#design>`__ section for information on the CL_TEMPLATE +design files. + +Users may modify these files and add new ones as their designs grow. +Xilinx IP's are available to all CL examples (found under +`$AWS_FPGA_REPO_DIR/hdk/common/ip <./../../../common/ip>`__). + +STEP 3: Develop Design Verification Tests (OPTIONAL) +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Once design files have been added, run the +`CL_TEMPLATE_base_test <./verif/tests/CL_TEMPLATE_base_test.sv>`__. This +test only powers up the test bench to make sure the design can be +compiled and simulated. All tests should be located under +`$CL_DIR/verif/tests <./verif/tests>`__ and test targets added to +`Makefile.tests <./verif/scripts/Makefile.tests>`__: + +.. code:: bash + + cd $AWS_FPGA_REPO_DIR/hdk/cl/examples/CL_TEMPLATE + export CL_DIR=$(pwd) + cd ${CL_DIR}/verif/scripts + make CL_TEMPLATE_base_test + +Or specify an `available simulator +<./../../../../User_Guide_AWS_EC2_FPGA_Development_Kit.html#hardware-development-kit-hdk>`__: + +.. code:: bash + + make CL_TEMPLATE_base_test =1 + +This will first generate and compile the simulation libraries required for the +requested SIMULATOR. Test results will be stored in the +``$CL_DIR/verif/sim/`` directory (created upon first simulation +run). After adding new IP's to +`$AWS_FPGA_REPO_DIR/hdk/common/ip <./../../../common/ip>`__, the simulation +libraries need to be recompiled: ``make regenerate_sim_libs =1``. + +File List Generation +^^^^^^^^^^^^^^^^^^^^ + +The Makefile includes ``$AWS_FPGA_REPO_DIR/hdk/common/verif/tb/scripts/Makefile.common.inc`` +which runs a Python script to automatically update each ``top..f`` file list with +all SystemVerilog files found under the ``$CL_DIR/design/``directory. + +- To disable the generation, run ``export DONT_GENERATE_FILE_LIST=1``. +- To re-enable the generation, run ``unset DONT_GENERATE_FILE_LIST``. +- To generate the file list by itself, run ``make generate_sim_file_list =1``. +- To add additional files, add them outside of the auto generation section: + +.. code:: text + + # Add code up here or below the comment block to persist between simulations + + ############################## + #### BEGIN AUTO-GENERATE ##### + + +incdir+$CL_DIR/design/ + + $CL_DIR/design/CL_TEMPLATE.sv + + ##### END AUTO-GENERATE ###### + ############################## + +Xilinx/AMD IP Discovery and Compilation +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +When running your first test, all Xilinx IP's under +`$AWS_FPGA_REPO_DIR/hdk/common/ip/cl_ip <./../../../common/ip/cl_ip>`__ +are automatically compiled + +- You can find the ``xil_defaultlib`` library for each simulator in + `$AWS_FPGA_REPO_DIR/hdk/common/verif/ip_simulation_libraries/ + <./../../../common/verif>`__ (created after first simulation run) + +If a design adds new IP's, make sure to add the new simulation libraries +to ``COMMON_LIBLISTS`` in: + +- `$AWS_FPGA_REPO_DIR/hdk/common/verif/tb/scripts/Makefile.common.inc + <./../../../common/verif/tb/scripts/Makefile.common.inc>`__ (this is + required for XSIM and Questa simulations). + +Simulation library names can be found under: + +- `$AWS_FPGA_REPO_DIR/hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts + <./../../../common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts>`__ followed + by ``//.sh`` + +All verification work is located under the `verif <./verif>`__ +directory. Please see the `Verification <#verification>`__ section for +the CL_TEMPLATE verification details. + +STEP 4: Develop Software Tests (OPTIONAL) +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +CL_TEMPLATE does not yet support standalone software tests. Please +refer to other examples such as `CL_DRAM_HBM_DMA +<./../cl_dram_hbm_dma/README.html#software>`__ + +STEP 5: Build and Deploy the Design +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Once design files have been added and tested, constraint and build +script updates need to be made. The build flow creates a bitstream that +is used to create an AFI to deploy on hardware. The build and deployment +flows can be found in the `Quick Start Guide +<./../../../README.html#getting-started>`__. Examples for all constraint files +and build scripts can be found in other examples such as +`CL_DRAM_HBM_DMA <./../cl_dram_hbm_dma/build>`__. + +1. Populate existing and/or add new constraint files to + `./build/constraints <./build/constraints>`__ + + - AWS has provided basic constraints required in example designs in + `$AWS_FPGA_REPO_DIR/hdk/common/shell_stable/build/constraints <./../../../common/shell_stable/build/constraints>`__ + +2. Update + `synth_CL_TEMPLATE.tcl <./build/scripts/synth_CL_TEMPLATE.tcl>`__ + with: + + - Additional constraint files to be applied during a build + - Additional tcl scripts to synthesize the design + - Xilinx IP's utilized in the design + + - IP's used in AWS example designs can uncommented be in + `synth_CL_TEMPLATE.tcl <./build/scripts/synth_CL_TEMPLATE.tcl>`__ + and found under + `$AWS_FPGA_REPO_DIR/hdk/common/ip/cl_ip <./../../../common/ip/cl_ip>`__ + - If a design adds new IP's, make sure to add the new ``xci`` files + to the build script + `$CL_DIR/build/scripts/synth_CL_TEMPLATE.tcl <./build/scripts/synth_CL_TEMPLATE.tcl>`__ + +3. Run `aws_build_dcp_from_cl.py <./build/scripts/aws_build_dcp_from_cl.py>`__. + All defaults can be found by running ``aws_build_dcp_from_cl.py --help`` + + .. code:: bash + + cd $AWS_FPGA_REPO_DIR/hdk/cl/examples/CL_TEMPLATE + export CL_DIR=$(pwd) + cd ${CL_DIR}/build/scripts + ./aws_build_dcp_from_cl.py -c CL_TEMPLATE + + The start of the log will provide build details: + + .. code:: bash + + ================================================== + Running CL builds + ================================================== + cl : cl_mem_perf + mode : xdma_shell + clock_recipe_a : A1 + clock_recipe_b : B2 + clock_recipe_c : C0 + clock_recipe_hbm : H2 + flow : BuildAll + place_direct : SSI_ExtraTimingOpt + phy_opt_direct : Explore + route_direct : AggressiveExplore + build_tag : None + ================================================== + vivado -mode batch -source build_all.tcl -log 04_06_2023-181511_build_all.log -tclargs SSI_ExtraTimingOpt Explore AggressiveExplore A1 B2 C0 H2 + + The build will create 4 new subdirectories under `./build <./build>`__: + - ``src_post_encryption`` - encrypted design files + - ``checkpoints`` - design checkpoints (``.dcp``) for each stage used by + Vivado + - ``reports`` - reports for each build stage + - ``bitstreams`` - CustomLogic bitstreams used for AFI creation + + Builds with timing violations will have a suffix of ``_VIOLATED`` under the + ``checkpoints`` directory. Details can be found under the ``reports`` + directory. + +After a successful build, you can follow the AFI creation, loading, and +testing instructions in the `Hardware Development Kit (HDK) top level document +<./../../../README.html#build-accelerator-afi-using-hdk-design-flow>`__. diff --git a/docs-rtd/source/hdk/cl/examples/cl_dram_hbm_dma/README.rst b/docs-rtd/source/hdk/cl/examples/cl_dram_hbm_dma/README.rst new file mode 100644 index 000000000..b788e48db --- /dev/null +++ b/docs-rtd/source/hdk/cl/examples/cl_dram_hbm_dma/README.rst @@ -0,0 +1,273 @@ +CL_DRAM_HBM_DMA CustomLogic Example +=================================== + +⚠️ **Features using XDMA engine are currently unsupported on F2 +instances** + +Table of Content +---------------- + +1. `Overview <#overview>`__ +2. `Functional Description <#functional-description>`__ +3. `Software <#software>`__ + +Overview +======== + +The CL_DRAM_HBM_DMA example demonstrates the use and connectivity for +many of the Shell/CL interfaces and functionality, including: + +1. Register access over OCL AXI-Lite interface + +2. Mapping of the external DRAM channel to instance memory via PCIe + AppPF BAR4, and the 512-bit ``sh_cl_dma_pcis_*`` AXI4 bus + +3. Mapping of HBM memory to instance memory via PCIe AppPF BAR4, and the + 512-bit ``sh_cl_dma_pcis_*`` AXI4 bus + +4. Debugging using Virtual JTAG and Xilinx Integrated Logic Analyzer (ILA) cores. + +5. User-defined interrupts + +6. ``cl_sh_pcim_*`` AXI4 traffic for Host memory accesses from CL + +System diagram +-------------- + +|cl_dram_hbm_dma| + +Functional Description +====================== + +Memory Interface +---------------- + +The cl_dram_hbm_dma demonstrates accessing 64GB of DDR memory and 16GB +of single channel HBM memory over the ``sh_cl_dma_pcis`` AXI4 bus. + +The CL provides access to the DDR memory through ``sh_ddr.sv`` which +consists of the DDR controller required to interact with the external +DDR DIMM on the FPGA card. The ``sh_ddr.sv`` is also connected to the +Shell's ``sh_cl_ddr_stat_*`` ports to enable Shell to manage DDR +calibration upon CL AFI loads. + +The CL also provides access to the on-chip HBM available in the FPGA. +The HBM IP is configured for dual stack 16GB capacity which exposes 32 +AXI3 (not AXI4) channels running on 450MHz clock. However, only one HBM +channel is being used in this example design to demonstrate datapath +connection to the HBM. The `cl_hbm_axi4.sv <./design/cl_hbm_axi4.sv>`__ +does the AXI4-to-AXI3 conversion, crosses clock domain between +the 250 MHz ``clk_main_a0`` and HBM's up to 450 MHz ``axi_clk`` for the datapath and feeds +the ``cl_hbm_wrapper.sv``. The +`cl_hbm_wrapper.sv <./design/cl_hbm_wrapper.sv>`__ instantiates the HBM +IP, houses MMCM to generate 450MHz interface clock, and connects the +datapath to Channel#0 of the HBM IP core. + +**NOTE:** Since the CL utilizes only one HBM Channel which is fed by +data source running at 250MHz clock, it does not accomplish the max +available bandwidth from HBM. For demonstration of the max performance from +HBM. refer to the `cl_mem_perf <../cl_mem_perf/README.html>`__ example. + +Design Changes +-------------- + +Individual controllers (DDR, HBM) can be enabled and disabled by simply +updating the appropriate defines in the +`cl_dram_hbm_dma_defines.vh `__ file. The +`sh_ddr.sv <../../../common/shell_stable/design/sh_ddr/sim/sh_ddr.sv>`__ +file contains the necessary logic to remove and tie-off appropriate +interfaces when the DDR controller is disabled. + +For the cl_dram_hbm_dma example memory ranges have been allocated for +DDR and HBM. So, if a particular memory is disabled, then the developer +should take care to handle transactions to that address range since +there will be no controller to respond to the request. The address +ranges for each controller is described below in the `dma_pcis AXI4 bus +section <#dma_pcis>`__. + +Test Changes +------------ + +If a particular controller is disabled, make sure that the test is not +accessing address space for that controller. + +Please look at `dma_pcis AXI4 bus section <#dma_pcis>`__ for address +ranges. + +If DDR is enabled, make sure that the DDRs are initialized using the +poke_stat commands below. + +eg: To initialize DDR + +.. code:: Verilog + + tb.poke_stat(.addr(8'h0c), .ddr_idx(0), .data(32'h0000_0000)); + +Make sure that the Host to Card and Card to Host DMA transfers only +access enabled DDR controller address space. + +dma_pcis AXI4 bus +----------------- + +sh_cl_dma_pcis exposes a address windows of 128GB matching AppPF BAR4. + +This memory space is mapped to the 64GB DRAM space and 16GB HBM space. +An axi_crossbar interconnects the incoming address requests to the +target memories as shown below: + +- DDR base_addr=0x00_0000_0000 (range=64GB) +- HBM base_addr=0x10_0000_0000 (range=16GB) + +**NOTE**: Please refer to +`Supported DDR Modes <./../../../docs/Supported_DDR_Modes.html>`__ for +details on supported DDR configurations in ``sh_ddr.sv``. + +ocl\_ AXI-Lite +-------------- + +The cl_ocl\_ AXI-Lite bus is connected to +`cl_ocl_slv.sv `__ module, and is used for +register access to the Automatic Test Generator (ATG) etc. + +The valid address map is as shown below: + +.. list-table:: + :header-rows: 1 + :class: user-guide-dev-envs-table + :widths: 10 15 15 60 + + * - Module + - OCL Start Address + - OCL End Address + - Description + * - PCIM ATG + - 0x0000 + - 0x00FF + - PCIM Traffic Generator (refer to ``cl_tst.sv``). + * - DDR ATG + - 0x0100 + - 0x01FF + - DDR Traffic Generator + * - HBM ATG + - 0x0200 + - 0x02FF + - HBM Traffic Generator + * - HBM Status + - 0x0300 + - 0x0300 + - + - bit[31:3] - Reserved (RO) + - bit[31:3] - Reserved (RO) + - bit[2:1] - HBM Initialized + - bit[0] - SW Reset for HBM. (1 = Reset HBM) + +Any access to invalid address shall return ``32'hDEADBEEF`` + +sda\_ AXI-Lite +-------------- + +The sh_cl_sda\_ AXI-Lite bus is connected to +`cl_sda_slv.sv `__ module, which provides 1KiB of +scratch RAM. + +Address bits [9:0] will be used to access the location of the RAM, but +the upper bits of the address are ignored. + +pcim\_ AXI4 +----------- + +The cl_sh_pcim\_ AXI4 bus is driven by Automatic Test Generator (ATG) +and connected to `cl_pcim_mstr.sv `__. It can be +used to read/write from the host memory. + +irq/ack +------- + +`cl_int_slv.sv `__ provides an example for +generating the IRQ requests and checks if ACK has been received. + +Virtual JTAG +------------ + +3 ILA cores are integrated, one to monitoring the sh_c_dma_pcis bus, one +to monitor the AXI4 signals on DDR and the third to monitor the AXI4 +signals on HBM. An example usage is provided in +`cl_ila.sv `__. An example usage for Xilinx VIO is +provided in `cl_vio.sv `__ + +Clocks +------ + +CL_DRAM_HBM_DMA uses the main ``clk_main_a0``. It's frequency is set in +`cl_clocks_aws.xdc <./build/constraints/cl_clocks_aws.xdc>`__ + +Software +-------- + +DMA accesses rely on the `XDMA +driver `__ + +The DRAM_HBM DMA example includes runtime software to demonstrate +working DMA accesses. The runtime example is located `in the runtime +directory `__ + +There are three example tests in cl_dram_hbm_dma example. + +.. _test_dram_dmac: + +test_dram_dma.c +~~~~~~~~~~~~~~~ + +This test runs a software test with data transfer with DDR enabled. + +.. _test_hbm_dmac: + +test_hbm_dma.c +~~~~~~~~~~~~~~ + +This test runs a software test with data transfer with HBM enabled. + +.. _test_dram_hbm_dmac: + +test_dram_hbm_dma.c +~~~~~~~~~~~~~~~~~~~ + +This test runs a software test with data transfer with both DDR and HBM +enabled + +Compile and run instructions +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. code:: bash + + cd ${CL_DIR}/software/runtime + make all + sudo ./test_dram_hbm_dma + +.. _test_dram_hbm_dma_hwsw_cosimc: + +test_dram_hbm_dma_hwsw_cosim.c +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +This test runs a software test with HW/SW co-simulation enabled with +both DDR and HBM enabled. + +.. _compile-and-run-instructions-1: + +Compile and run instructions +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. code:: bash + + cd ${CL_DIR}/software/runtime + make TEST=test_dram_hbm_dma_hwsw_cosim + sudo ./test_dram_hbm_dma_hwsw_cosim + +The test can be simulated with XSIM as follows. + +.. code:: bash + + cd ${CL_DIR}/verif/scripts + make C_TEST=test_dram_hbm_dma_hwsw_cosim + +.. |cl_dram_hbm_dma| image:: ../../../../_static/cl_dram_hbm_dma_images/cl_dram_hbm_dma.png diff --git a/docs-rtd/source/hdk/cl/examples/cl_dram_hbm_dma/verif/README.rst b/docs-rtd/source/hdk/cl/examples/cl_dram_hbm_dma/verif/README.rst new file mode 100644 index 000000000..c471bbfe9 --- /dev/null +++ b/docs-rtd/source/hdk/cl/examples/cl_dram_hbm_dma/verif/README.rst @@ -0,0 +1,347 @@ +CL_DRAM_HBM_DMA Example Simulation +================================== + +Table of Contents +----------------- + +- `CL_DRAM_HBM_DMA Example + Simulation <#cl_dram_hbm_dma-example-simulation>`__ + + - `Table of Contents <#table-of-contents>`__ + - `Overview <#overview>`__ + - `Dump Waves <#dump-waves>`__ + - `SystemVerliog Tests <#systemverliog-tests>`__ + + - `test_clk_recipe.sv <#test_clk_recipesv>`__ + - `test_ddr_peek_poke.sv <#test_ddr_peek_pokesv>`__ + - `test_ddr.sv <#test_ddrsv>`__ + - `test_hbm.sv <#test_hbmsv>`__ + - `test_dram_dma.sv <#test_dram_dmasv>`__ + - `test_dram_dma_rnd.sv <#test_dram_dma_rndsv>`__ + - `test_dma_pcim_concurrent.sv <#test_dma_pcim_concurrentsv>`__ + - `test_dma_pcis_concurrent.sv <#test_dma_pcis_concurrentsv>`__ + - `test_dma_sda_concurrent.sv <#test_dma_sda_concurrentsv>`__ + - `test_dram_dma_4k_crossing.sv <#test_dram_dma_4k_crossingsv>`__ + - `test_dram_dma_allgn_addr_4k.sv <#test_dram_dma_allgn_addr_4ksv>`__ + - `test_dram_dma_single_beat_4k.sv <#test_dram_dma_single_beat_4ksv>`__ + - `test_dram_dma_axi_mstr.sv <#test_dram_dma_axi_mstrsv>`__ + - `test_int.sv <#test_intsv>`__ + - `test_peek_poke.sv <#test_peek_pokesv>`__ + - `test_peek_poke_wc.sv <#test_peek_poke_wcsv>`__ + - `test_peek_poke_len.sv <#test_peek_poke_lensv>`__ + - `test_peek_poke_rnd_lengths.sv <#test_peek_poke_rnd_lengthssv>`__ + - `test_peek_poke_pcis_axsize.sv <#test_peek_poke_pcis_axsizesv>`__ + - `test_ddr_peek_bdr_walking_ones <#test_ddr_peek_bdr_walking_ones>`__ + - `test_sda.sv <#test_sdasv>`__ + - `test_null.sv <#test_nullsv>`__ + + - `AXI_MEMORY_MODEL Mode + Simulations <#axi_memory_model-mode-simulations>`__ + + - `test_dram_dma_mem_model_bdr_wr <#test_dram_dma_mem_model_bdr_wr>`__ + - `test_dram_dma_mem_model_bdr_rd <#test_dram_dma_mem_model_bdr_rd>`__ + + - `DDR Backdoor Loading <#ddr-backdoor-loading>`__ + + - `HW/SW Co-Simulation Test <#hwsw-co-simulation-test>`__ + +Overview +-------- + +This readme provides information about the simulation environment for +the ``cl_dram_hbm_dma`` example. For more details about overall HDK +simulation environment and CL bringup in simulation please refer to the +`RTL Simulation Guide for HDK Design +Flow <../../../../docs/RTL_Simulation_Guide_for_HDK_Design_Flow.md>`__ + +SystemVerilog (SV) simulations can be run from the +``$CL_DIR/verif/scripts/`` directory with all supported simulators (HBM +simulation using VCS & QUESTA is strongly recommended). You can run +tests by calling the make target for that test located in +``$CL_DIR/verif/scripts/Makefile.tests``: + +.. code:: bash + + make test_ddr # Runs with XSIM by default + make test_ddr VCS=1 + make test_ddr QUESTA=1 + + make test_hbm # Runs with VCS by default + +Alternatively, you can run each test by setting ``TEST=\`` +followed by the environment variables required to run that test. + +.. code:: bash + + make TEST=test_dram_dma # Runs with XSIM by default + make TEST=test_dram_dma VCS=1 + make TEST=test_dram_dma QUESTA=1 + + # To Run simulations with a 64 GB DDR DIMM (with user-controlled auto-precharge mode) + make TEST=test_dram_dma USE_AP_64GB_DDR_DIMM=1 + + # To Run Simulations in AXI_MEMORY_MODEL mode + make TEST=test_dram_dma AXI_MEMORY_MODEL=1 # Runs with XSIM by default in AXI_MEMORY_MODEL mode + make TEST=test_dram_dma AXI_MEMORY_MODEL=1 VCS=1 + make TEST=test_dram_dma AXI_MEMORY_MODEL=1 QUESTA=1 + + # To Run DDR backdoor loading tests + make TEST=test_ddr_peek_bdr_walking_ones # Runs with XSIM by default + make TEST=test_ddr_peek_bdr_walking_ones VCS=1 + make TEST=test_ddr_peek_bdr_walking_ones QUESTA=1 + + # Backdoor loading test list. Description can be found in the sections below. + test_dram_dma_mem_model_bdr_rd + test_dram_dma_mem_model_bdr_wr + test_ddr_peek_bdr_walking_ones + +**NOTE**: Please refer to +`Supported_DDR_Modes.md <./../../../../docs/Supported_DDR_Modes.md>`__ +for details on supported DDR configurations. + +The HW/SW co-simulation tests can be run from the ``verif/scripts/`` +directory with all supported simulators: + +.. code:: bash + + make C_TEST=test_dram_dma_hwsw_cosim # Runs with XSIM by default + make C_TEST=test_dram_dma_hwsw_cosim VCS=1 + make C_TEST=test_dram_dma_hwsw_cosim QUESTA=1 + + # To Run in AXI_MEMORY_MODEL mode with AXI memory models instead of DDR. + + make C_TEST=test_dram_dma_hwsw_cosim AXI_MEMORY_MODEL=1 # Runs with XSIM by default + make C_TEST=test_dram_dma_hwsw_cosim AXI_MEMORY_MODEL=1 VCS=1 + make C_TEST=test_dram_dma_hwsw_cosim AXI_MEMORY_MODEL=1 QUESTA=1 + +Note that the appropriate simulators must be installed. + +Dump Waves +---------- + +For information about how to dump waves with XSIM or VCS, please refer +to +`debugging-custom-logic-using-the-aws-hdk <../../../../docs/RTL_Simulation_Guide_for_HDK_Design_Flow.md#>`__ + +SystemVerliog Tests +------------------- + +The SystemVerilog test cases are located at ``verif/tests/``. Most tests +include ``base_test_utils.svh`` which includes common signals and tasks +used across tests. Please refer to this file for the DPI-C tasks used. +Information about each test can be found below. + +.. _test_clk_recipesv: + +test_clk_recipe.sv +~~~~~~~~~~~~~~~~~~ + +This test programs valid clock recipes defined within and verifies the +corresponding clock frequencies. + +.. _test_ddr_peek_pokesv: + +test_ddr_peek_poke.sv +~~~~~~~~~~~~~~~~~~~~~ + +This does a walking ones test through the DDR address range. Also checks +if any of the bits are stuck at '0'. + +.. _test_ddrsv: + +test_ddr.sv +~~~~~~~~~~~ + +This test programs the CL_TST (ATG) to generate traffic to access all +four DDR channels. + +.. _test_hbmsv: + +test_hbm.sv +~~~~~~~~~~~ + +This test programs the CL_TST (ATG) to generate traffic to access both +HBM stacks. + +.. _test_dram_dmasv: + +test_dram_dma.sv +~~~~~~~~~~~~~~~~ + +Basic H2C and C2H DMA test through all 4 DDR channels and 2 HBM stacks. + +.. _test_dram_dma_rndsv: + +test_dram_dma_rnd.sv +~~~~~~~~~~~~~~~~~~~~ + +This test programs DMA transfers with random lengths. + +.. _test_dma_pcim_concurrentsv: + +test_dma_pcim_concurrent.sv +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This test programs both the DMA and PCIM traffic to run concurrently and +verifies that there are no errors on both DMA and PCIM interfaces. + +.. _test_dma_pcis_concurrentsv: + +test_dma_pcis_concurrent.sv +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This test programs both the DMA and PCIS traffic to run concurrently and +verifies that there are no errors on both DMA and PCIS interfaces. + +.. _test_dma_sda_concurrentsv: + +test_dma_sda_concurrent.sv +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This test programs both the DMA and SDA traffic to run concurrently and +verifies that there are no errors on both DMA and SDA interfaces. + +.. _test_dram_dma_4k_crossingsv: + +test_dram_dma_4k_crossing.sv +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This test programs DMA transfers that will cross a 4k boundary. All +transfers are of same length with different destination addresses. + +.. _test_dram_dma_allgn_addr_4ksv: + +test_dram_dma_allgn_addr_4k.sv +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This test programs DMA transfers that will cross a 4k boundary. All +transfers are of different length with different destination addresses. + +.. _test_dram_dma_single_beat_4ksv: + +test_dram_dma_single_beat_4k.sv +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This test programs single beat DMA transfers that will cross a 4k +boundary. + +.. _test_dram_dma_axi_mstrsv: + +test_dram_dma_axi_mstr.sv +~~~~~~~~~~~~~~~~~~~~~~~~~ + +This test configures the cl_dram_dma_axi_mstr.sv module to send and +receive traffic from the DDR in the CL design. + +.. _test_intsv: + +test_int.sv +~~~~~~~~~~~ + +This test programs enables interrupts in CL and verifies them. + +.. _test_peek_pokesv: + +test_peek_poke.sv +~~~~~~~~~~~~~~~~~ + +This test programs ATG in CL to do 128 byte PCIM reads and writes. + +.. _test_peek_poke_wcsv: + +test_peek_poke_wc.sv +~~~~~~~~~~~~~~~~~~~~ + +This test performs pcis write combine operations and reads back the +data. + +.. _test_peek_poke_lensv: + +test_peek_poke_len.sv +~~~~~~~~~~~~~~~~~~~~~ + +This test programs tester block to do PCIM reads and writes with +incremental lengths. + +.. _test_peek_poke_rnd_lengthssv: + +test_peek_poke_rnd_lengths.sv +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This test programs tester block to do PCIM reads and writes with random +lengths within valid range. + +.. _test_peek_poke_pcis_axsizesv: + +test_peek_poke_pcis_axsize.sv +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This test does PCIS peek and poke with different sizes. Although shell +model allows different size transfers on PCIS interface, Shell only +supports transfer of size 6 on PCIS interface. + +test_ddr_peek_bdr_walking_ones +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +DDR test which uses backdoor loading to populate DDR memory. The test +writes data(walking ones) for different addresses. The test backdoor +loads DDR memory and reads through frontdoor and checks that the data +matches. + +.. _test_sdasv: + +test_sda.sv +~~~~~~~~~~~ + +This test does transfers to different addresses on SDA AXIL interface. + +.. _test_nullsv: + +test_null.sv +~~~~~~~~~~~~ + +test_null is not an actual test. This is a base SV file needed for HW/SW +co-simulation + + + +AXI_MEMORY_MODEL Mode Simulations +--------------------------------- + +AXI_MEMORY_MODEL mode can be used for better simulation performance. +AXI_MEMORY_MODEL mode enables a test to run with AXI memory models +instead of DDR memory. The documentation can be found in AXI memory +model section at `RTL simulation +guide <../../../../docs/RTL_Simulation_Guide_for_HDK_Design_Flow.md>`__. +Any test that accesses DDR memory can be run in AXI_MEMORY_MODEL mode. +Below are some example tests for ECC and backdoor loading support +features of AXI memory model. + +test_dram_dma_mem_model_bdr_wr +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This test backdoor writes AXI memory model, reads through frontdoor and +checks that the data matches. + +test_dram_dma_mem_model_bdr_rd +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This test backdoor reads AXI memory model, writes through frontdoor and +checks that the data matches. + +DDR Backdoor Loading +-------------------- + +The description of DDR backdoor loading can be found in DDR backdoor loading +support section at `RTL simulation +guide <../../../../docs/RTL_Simulation_Guide_for_HDK_Design_Flow.md>`__. + +HW/SW Co-Simulation Test +------------------------ + +The software test with HW/SW co-simulation support +`test_dram_dma_hwsw_cosim.c <../software/runtime/test_dram_dma_hwsw_cosim.c>`__ +can be found at ``software/runtime/``. For Information about how HW/SW +co-simulation support can be added to a software test please refer to +"Code changes to enable HW/SW co-simulation" section in `RTL simulation +guide <../../../../docs/RTL_Simulation_Guide_for_HDK_Design_Flow.md>`__. diff --git a/docs-rtd/source/hdk/cl/examples/cl_mem_perf/README.rst b/docs-rtd/source/hdk/cl/examples/cl_mem_perf/README.rst new file mode 100644 index 000000000..8d2197bf8 --- /dev/null +++ b/docs-rtd/source/hdk/cl/examples/cl_mem_perf/README.rst @@ -0,0 +1,800 @@ +CL_MEM_PERF Custom Logic Example +================================ + +⚠️ **Features using XDMA engine are currently unsupported on F2 instances** + +Table of Content +---------------- + +- `CL_MEM_PERF Custom Logic + Example <#cl_mem_perf-custom-logic-example>`__ + + - `Table of Content <#table-of-content>`__ + +- `Introduction <#introduction>`__ +- `Architecture Overview <#architecture-overview>`__ + + - `Clocks and Reset <#clocks-and-reset>`__ + - `OCL <#ocl>`__ + - `PCIM <#pcim>`__ + - `PCIS <#pcis>`__ + - `DDR <#ddr>`__ + - `HBM <#hbm>`__ + - `SDA <#sda>`__ + - `Interrupts <#interrupts>`__ + - `Virtual JTAG <#virtual-jtag>`__ + +- `Address Space <#address-space>`__ + + - `OCL Address Space <#ocl-address-space>`__ + - `PCIS Memory Address Space <#pcis-memory-address-space>`__ + - `HBM Memory Address Space <#hbm-memory-address-space>`__ + - `CL_HBM_AXI4 Register Address + Space <#cl_hbm_axi4-register-address-space>`__ + - `SDA Memory Address Space <#sda-memory-address-space>`__ + +- `Simulations <#simulations>`__ +- `Software <#software>`__ + + - `test_hbm_perf32.c <#test_hbm_perf32c>`__ + - `test_dram_hbm_dma.c <#test_dram_hbm_dmac>`__ + - `test_hbm_perf32.c <#test_hbm_perf32c-1>`__ + - `test_aws_clk_gen.c <#test_aws_clk_genc>`__ + - `test_clk_freq.c <#test_clk_freqc>`__ + + - `Compile and run instructions <#compile-and-run-instructions>`__ + + - `test_dram_hbm_dma_hwsw_cosim.c <#test_dram_hbm_dma_hwsw_cosimc>`__ + + - `Compile and run instructions <#compile-and-run-instructions-1>`__ + +- `HBM Performance Tests <#hbm-performance-tests>`__ + + - `Instructions to run HBM Performance + Test <#instructions-to-run-hbm-performance-test>`__ + +Introduction +============ + +The CL_MEM_PERF is a customer reference design for F2 where the +objective is to demonstrate fine tuned data paths to HBM and DDR to +achieve maximum throughput to the memories. The example also +demonstrates datapath connectivity between Host, AWS Shell, Custom Logic +(CL) region in the FPGA, HBM and DDR DIMM on the FPGA card. Following +are the major highlights of CL_MEM_PERF design: + +1. Datapath to 64GB DDR and 16GB HBM through Shell's PCIS Interface. + DDR and HBM memories in the FPGFA are accessible from the Host on + PF0-BAR4, as well as from the DMA engine in the XDMA_SHELL. Both + these accesses show up as AXI4 transaction on PCIS interface which + ultimately reach the targeted memory. +2. Demonstrate the use of PCIM interface for applications where CL is + the PCIe Requester to the Host. This can also be used to test peak + PCIe transfer rates between Host and FPGA over PCIM interface. +3. Register access to various blocks through Shell's OCL interface. +4. 1KB BRAM accessible through Shell's SDA interface. +5. Supports user defined interrupts generated by the CL. +6. Demonstrate Virtual JTAG using debug cores and AMD Integrated Logic + Analyzers (ILA). +7. AXI4 Traffic Generators to test peak DDR4 performance. +8. HBM Performance Kernels to test peak HBM performance. This example + shows how the micro-architecture to saturate all 32 Channels of HBM, + achieve timing closure at 450MHz and achieve peak performance close + to the theoretical number described in `AMD/Xilinx HBM Userguide + `__ +9. Build scripts and constraints to create or manage pblock/placement + and timing constraints. +10. Software runtime tests to exercise max performance to the HBM, and + other tests to exercise DMA engine in the AWS Shell to perform data + transfers between the Host and CL. + +Overall, CL_MEM_PERF enables customers to quickly integrate their CL +accelerator designs to interface with various memories on the FPGA and +to use as reference to fine tune their CL performance. + +Architecture Overview +===================== + +Figure below shows an architectural overview of CL_MEM_PERF design: + +|cl_mem_perf| + +All interfaces in this CL example are accessible from the Host on the +PF/BARs as stated in the table below. Please See the `PCIe Memory Map +<../../../docs/AWS_Fpga_Pcie_Memory_Map.html>`__ for more details on bar sizes, +and `AWS Shell Interface Specification +<../../../docs/AWS_Shell_Interface_Specification.html>`__ for available +interfaces between the Shell and the CL. + +.. list-table:: + :header-rows: 1 + :class: user-guide-dev-envs-table + :widths: 30 5 5 + + * - Interface + - PF + - BAR + * - OCL + - 0 + - 0 + * - XDMA BAR (not an interface between Shell/CL) + - 0 + - 2 + * - PCIS + - 0 + - 4 + * - Reserved for AWS + - 1 + - 0 + * - Virtual JTAG + - 1 + - 2 + * - SDA + - 1 + - 4 + +Clocks and Reset +---------------- + +- clk_main_a0 (250 MHz) from Shell for majority of the design except for + HBM. +- rst_main_n from Shell sync'd to clk_main_a0. +- clk_hbm_ref (100 MHz) from Shell as reference clock for HBM IP. +- HBM AXI3 interface is clocked by the 450MHz clock generated from the + `AWS_CLK_GEN <./../../../common/lib/aws_clk_gen.sv>`__ IP. This IP also + generates several other clocks to match with the clock recipes supported in + F1. Please refer to the `AWS_CLK_GEN specifiction + <./../../../docs/AWS_CLK_GEN_spec.html>`__ for details on this block. The + `Clock Recipes User Guide <./../../../docs/Clock_Recipes_User_Guide.html>`__ + describes various clock recipes available for F2 developers and options on + configuring clocks dynamically. The user guide also describes porting + of CL designs based on F1 clock recipes into F2. +- NOTE: There is a SW control register at `OCL offset + 0x300 <#hbm-memory-address-space>`__ to reset only the HBM IP core. + This reset register does not reset the whole CL_HBM_AXI4 block. + +OCL +--- + +The `CL_MEM_OCL_DEC `__ module converts OCL +32-bit AXI-L Interface to simple config bus interface. It consists of an +address decoder to access register space of various blocks. See `OCL +Address Space <#ocl-address-space>`__ for available ranges. + +PCIM +---- + +The `CL_PCIM_MSTR <../cl_dram_hbm_dma/design/cl_pcim_mstr.sv>`__ module +is connected to the 512-bit AXI4 PCIM interface. It consists of AXI4 +Traffic Generator capable of issuing Read/Write requests to the Host +over the PCIe link. This block can also be used to test the peak PCIe +transfer rates across the PCIe link. + +While this block is essentially a traffic generator, CL designers could +potentially swap this block with their custom Kernel that acts as a PCIe +Requester to the Host Memory. + +PCIS +---- + +The PCIS is a 512-bit AXI4 interface from the Shell which can be +accessed either by Host over PF0-BAR4, or by the XDMA engine in the AWS +Shell. The PCIS interface is used in CL_MEM_PERF example to provide +datapaths to the DDR and HBM memories in the FPGA. The address range to +access DDR and HBM memories is described in `PCIS Memory Address +Space <#pcis-memory-address-space>`__. + +The `CL_AXI_MSTR <../cl_dram_hbm_dma/design/cl_dram_dma_axi_mstr.sv>`__ +module is another simple AXI4 traffic generator whose traffic pattern +and access length can be configured using the registers. The AXI4 +interface from CL_AXI_MSTR and PCIS feed to CL_AXI_INTERCONNECT which +ultimately connects to DDR and HBM based on the access address request. + +There are two MUXes - one along the datapath to DDR, and another MUX +along datapath to HBM. These MUXes default to connecting +CL_AXI_INTERCONNECT's path to the target memories. However, setting +these MUXes enables traffic from the ATGs to the target memories. PCIS +path to the target memories is disabled when the MUXes are enabled. + +DDR +--- + +AWS provides +`SH_DDR <../../../common/shell_stable/design/sh_ddr/synth/sh_ddr.sv>`__ +that houses the DDR4 Controller specifically configured to the DDR DIMM +on the FPGA Card. The SH_DDR is also connected to the Shell's +sh_cl_ddr_stat\_\* ports to enable Shell to manage DDR calibration upon +CL AFI loads. The SH_DDR exposes an AXI4 512-bit interface for the CL +logic to perform Read/Write data transfers into DDR. Please refer to the +`Supported DDR Modes <./../../../docs/Supported_DDR_Modes.html>`__ for +details on supported DDR configurations in ``sh_ddr.sv``. + +HBM +--- + +F2 FPGA has on-chip HBM with a maximum capacity of 16GiB, accessible +through 32 AXI3 Channels running at a maximum clock speed of up to +450MHz. CL designs should leverage all the available channels and aim +for achieving timing closure of the interface at 450MHz to get the best +possible performance out of HBM. HBM offers theoretical max bandwidth of +460GB/s when traffic is active across all the 32 Channels with 450MHz +clock. + +The `CL_HBM_AXI4 `__ module demonstrates an +use case for HBM traffic as shown in the block diagram below: + +|cl_hbm_kernel| + +CL_HBM_AXI4 exposes an AXI4 512-bit interface and two configuration +interfaces clocked using the 250MHz clk_main_a0. The Host (PCIS) can +access HBM through this AXI4 Interface. The AXI4 interface then connects +to 512-to-256 bit width converter, clock crossing converters between +clk_main_a0 and HBM's AXI3 clock, and +AXI4-to-AXI3 protocol converter to ultimately connect to HBM AXI Channel#0 + +The hbm_stat_bus is a simple config bus that connects to CL_HBM_WRAPPER +and facilitates access to the Reset Register inside the CL_HBM_WRAPPER +(mainly to reset HBM IP and check HBM read). + +The hbm_kern_cfg_bus is a simple config bus to configure the HBM +Performance Kernels (CL_HBM_PERF_KERNEL) + +In addition to providing a datapath from PCIS to HBM, the CL_HBM_AXI4 +block also instantiates CL_HBM_PERF_KERNEL which is designed to maximize +the available bandwidth from HBM. It demonstrates the microarchitecture +for Customer Kernels interfacing with HBM, supports multiple outstanding +transactions in the queue across all 32 channels, with AXI3 interface +running at 450MHz clock. This design provides clock domain crossing +mechanism, performance measurement counters along with floorplan and +timing constraints to achieve easier timing closure at 450 MHz. + +CL_HBM_PERF_KERNEL consists of the following blocks: + +- CL_KERNEL_CTL: This is the main controller for the Kernel. It is + responsible for posting write/read requests and track pending + transactions. The block is capable of producing write and read + requests in parallel to saturate all the channels of HBM. Keeping the + channels active is key for maximizing the available HBM bandwidth and + CL_KERNEL_CTL achieves that by arbitrating and issues multiple + outstanding requests. +- CL_KERNEL_REGS: Houses all the control and status registers including + performance measurement counters. +- CL_KERNEL_REQ: This block is instantiated inside CL_KERNEL_CTL and is + mainly responsible to perform Clock Domain Crossing of read/write + requests from clk_main_a0 to clk_hbm domain. This block is replicated + to server each channel of the HBM. +- CL_AXI_CTL: Contains the control logic and datapath required to serve + the AXI3 read/write requests to the HBM core. This module accepts + read/write requests from CL_KERNEL_REQ pipe and interface with HBM's + AXI3 interface. The entire block runs on clk_hbm domain. CL_AXI_CTL is + replicated for each HBM channel. Note that, the AXI3 interface for + channel#0 is muxed along with the AXI4 data path from the + hbm_axi4_bus. Users should enable this mux such that the traffic from + CL_AXI_CTL#0 drives into HBM Channel#0. Please see description for + details. +- While the data is produced/consumed locally in this specific design, + customers will be able to leverage the microarchitecture by feeding + the data to/from CL_KERNEL_REQ and interfacing it to their data + producer/consumer logic. + +CL_HBM_WRAPPER: + +- The CL_HBM_WRAPPER block houses the main HBM IP configured in 16GiB + capacity with 32- AXI3 Channels running at 450MHz clk_hbm clock. +- The hbm_stats_bus config interface provides access to reset the MMCM + and check if the HBM is ready. See registers in CL_HBM_AXI4 Register + Address Space for details. + +Please refer to `CL_HBM_AXI4 Register Address +Space <#cl-hbm-axi4-register-address-space>`__ for details on register address +space and HBM memory address space. + +SDA +--- + +The SDA interface is shared between two modules: + +1. The `CL_SDA_SLV <../cl_dram_hbm_dma/design/cl_sda_slv.sv>`__ module + provides access to a 1KB BRAM through SDA 32-bit AXI-L Interface. +2. The `AWS_CLK_GEN <./../../../common/lib/aws_clk_gen.sv>`__ module + generates all the required clocks for the design. Please refer to the + `AWS_CLK_GEN specifiction <./../../../docs/AWS_CLK_GEN_spec.html>`__ for + details on this block. The `Clock Recipes User + Guide <./../../../docs/Clock_Recipes_User_Guide.html>`__ describes + various clock recipes available for F2 developers and options on + configuring clocks dynamically. The user guide also describes porting + of CL designs based on F1 clock recipes into F2. + +Interrupts +---------- + +The `CL_INT_SLV <../cl_dram_hbm_dma/design/cl_int_tst.sv>`__ module +implements simple mechanism to trigger MSIX interrupts to the host over +sh_cl_apppf_irq_req/ack interface. SW can check the status of the +interrupt triggers and also configure the interrupt masks. The +``interrupt_example()`` routine in +`test_dram_hbm_dma.c <./software/runtime/test_dram_hbm_dma.c>`__ +demonstrates interrupts functionality. + +Virtual JTAG +------------ + +The `CL_ILA <../cl_dram_hbm_dma/design/cl_ila.sv>`__ instantiates the +Debug Bridge IP required to support Virtual JTAG and the two example +ILAs. One ILA snoops the PCIS bus, whereas second ILA snoops DDR-AXI4 +bus. + +Address Space +============= + +OCL Address Space +----------------- + +The OCL AXI-L is decoded into following address ranges for various +design blocks: + +.. list-table:: + :header-rows: 1 + :class: user-guide-dev-envs-table + :widths: 20 20 20 40 + + * - Module + - OCL Start Address + - OCL End Address + - Description + * - PCIM ATG + - 0x0000 + - 0x00FF + - PCIM AXI4 Traffic Generator + * - DDR ATG + - 0x0100 + - 0x01FF + - DDR AXI4 Traffic Generator + * - HBM ATG + - 0x0200 + - 0x02FF + - HBM AXI4 Traffic Generator + * - HBM Status + - 0x0300 + - 0x03FF + - Configure the CL_HBM_WRAPPER block + * - HBM Status + - 0x0300 + - 0x03FF + - Configure the CL_HBM_WRAPPER block + * - HBM Performance Kernels + - 0x0500 + - 0x05FF + - CL_AXI_MSTR block + * - Clock Frequency Measurement + - 0x0600 + - 0x06FF + - CL_CLK_FREQ block + * - Interrupt Generator + - 0x0D00 + - 0x0DFF + - CL_INT_SLV block + +PCIS Memory Address Space +------------------------- + +.. list-table:: + :header-rows: 1 + :class: user-guide-dev-envs-table + :widths: 10 10 10 10 + + * - Target Memory + - Start Address + - End Address + - Range + * - DDR + - 0x00_0000_0000 + - 0x0F_FFFF_FFFF + - 64 GB + * - HBM + - 0x10_0000_0000 + - 0x13_FFFF_FFFF + - 16 GB + +**NOTE**: Accessing memory beyond DDR and HBM's range can potentially corrupt +the data in either of the memories. + +HBM Memory Address Space +------------------------ + +HBM Memory Address Space is as shown in the `HBM User +Guide `__ +for 16GB capacity. Each CL_AXI_CTL instantiated in CL_HBM_PERG_KERNEL is +mapped to serve the address range defined for each channel in the HBM +user guide. For example: + +- Channel#0 \| Start Address = 0x0000_0000 \| End Address = 0x1FFF_FFFF +- Channel#1 \| Start Address = 0x2000_0000 \| End Address = 0x3FFF_FFFF + and so on... + +CL_HBM_AXI4 Register Address Space +---------------------------------- + +The table below describes the registers available in CL_HBM_AXI4 block. +This includes registers inside CL_HBM_WRAPPER and CL_KERNEL_REGS: + +.. list-table:: + :header-rows: 1 + :class: user-guide-dev-envs-table + :widths: 15 10 5 5 5 60 + + * - OCL Address offset + - Register Name + - Bits + - Access + - Default Value + - Description + * - 0x300 + - HBM_CTL_STATUS + - 31:3 + - RO + - 0x0 + - Reserved + * - + - + - 2:1 + - RO + - 0x0 + - + - 2'b00 : No initialized stack + - 2'b01 : HBM Stack#0 is initialized + - 2'b10 : HBM Stack#1 is initialized + - 2'b11 : HBM Stack#0 and Stack#1 are initialized. HBM is now ready to use. + * - + - + - 0 + - RW + - 0x0 + - 1'b1 : Reset HBM IP + * - 0x400 + - CHANNEL_AVAIL_REG + - 31:1 + - RW + - 0x0 + - Reserved + * - + - + - 0 + - RW + - 0x0 + - 1'b1 : Enable HBM Channel#0 MUX to drive AXI3 traffic from CL_AXI_CTL#0 + to HBM. NOTE: This bit must be set in order to use CL_HBM_PERF_KERNEL + * - 0x404 + - CHANNEL_AVAIL_REG + - 31:0 + - RO + - 0x20 + - Total number of HBM channels available for CL_HBM_PERF_KERNEL + * - 0x408 + - NUM_OT_REG + - 31:0 + - RO + - 0x0 + - Number of outstanding transactions supported + * - 0x40C + - CHNL_SEL_REG + - 31:0 + - RW + - 0x0 + - Select the Channel# to measure write and read latencies. This field is + 0-based. Max Value = 31. + * - 0x410 + - AXLEN_REG + - 31:0 + - RW + - 0x0 + - AWLEN/ARLEN to use. This field is 0-based and the value will be used to + drive axi_awlen and axi_arlen signals to HBM. + * - 0x414 + - WDATA_PATTERN_REG + - 31:0 + - RW + - 0x0 + - Initial 32-bit data pattern for writes + * - 0x418 + - WR_CTL_REG + - 31:0 + - RW + - 0x0 + - Start write transactions on each channel. Each bit corresponds to a HBM + channel. bit[0] = Start write transfers on HBM Channel#0. bit[1] = Start + write transfers on HBM Channel#1 ... bit[31] = Start write transfers on + HBM Channel#31 + * - 0x41C + - RD_CTL_REG + - 31:0 + - RW + - 0x0 + - Start read transactions on each channel. Each bit corresponds to a HBM + channel. bit[0] = Start read transfers on HBM Channel#0. bit[1] = Start + read transfers on HBM Channel#1 ... bit[31] = Start read transfers on + HBM Channel#31 + * - 0x430 + - WR_CYC_CNT_LO_REG + - 31:0 + - RW + - 0x0 + - Total number of write requests to HBM aggregated across all HBM channels. + LSB 32 bits. SW write 0 to clear. + * - 0x434 + - WR_CYC_CNT_HI_REG + - 31:0 + - RW + - 0x0 + - Total number of write requests to HBM aggregated across all HBM channels. + MSB 32 bits. SW write 0 to WR_CYC_CNT_LO_REG to clear this reg. + * - 0x438 + - WR_TIMER_LO_REG + - 31:0 + - RW + - 0x0 + - Timer during which Write requests were in progress. LSB 32 bits. + SW write 0 to clear. + * - 0x43C + - WR_TIMER_HI_REG + - 31:0 + - RW + - 0x0 + - Timer during which Write requests were in progress. MSB 32 bits. + SW write 0 to WR_TIMER_LO_REG to clear. + * - 0x440 + - WR_LATENCY_REG + - 31:0 + - RW + - 0x0 + - Measure latency between first AW request and B-response from HBM Channel + specified in CHNL_SEL_REG + * - 0x444 + - WR_OT_REG + - 31:0 + - RO + - 0x0 + - Pending write requests in the queue. + * - 0x448 + - BRESP_ERR_REG + - 31:0 + - RW + - 0x0 + - 1'b1 : Bresp error from HBM Channel# corresponding to that bit. + SW writes 0 to clear the bit + * - 0x450 + - RD_CYC_CNT_LO_REG + - 31:0 + - RW + - 0x0 + - Total number of Read requests to HBM aggregated across all HBM channels. + LSB 32 bits. SW write 0 to clear. + * - 0x454 + - RD_CYC_CNT_HI_REG + - 31:0 + - RW + - 0x0 + - Total number of Read requests to HBM aggregated across all HBM channels. + MSB 32 bits. SW write 0 to RD_CYC_CNT_LO_REG to clear this reg. + * - 0x458 + - RD_TIMER_LO_REG + - 31:0 + - RW + - 0x0 + - Timer during which Read requests were in progress. LSB 32 bits. + SW write 0 to clear. + * - 0x45C + - RD_TIMER_HI_REG + - 31:0 + - RW + - 0x0 + - Timer during which Read requests were in progress. MSB 32 bits. + SW write 0 to RD_TIMER_LO_REG to clear. + * - 0x460 + - RD_LATENCY_REG + - 31:0 + - RW + - 0x0 + - Measure latency between first AR request and R-last response from HBM + Channel specified in CHNL_SEL_REG + * - 0x464 + - RD_OT_REG + - 31:0 + - RO + - 0x0 + - Pending Read requests in the queue. + * - 0x468 + - RRESP_ERR_REG + - 31:0 + - RW + - 0x0 + - 1'b1 : Rresp error from HBM Channel# corresponding to that bit. + SW writes 0 to clear the bit + +SDA Memory Address Space +------------------------ + +.. list-table:: + :header-rows: 1 + :class: user-guide-dev-envs-table + :widths: 20 20 20 40 + + * - Target + - Start Address + - End Address + - Notes + * - SDA_SLV (BRAM) + - 0x0000_0000 + - 0x0004_FFFF + - 1KB BRAM. Upper address rolls over. + * - AWS_CLK_GEN + - 0x0050_0000 + - 0xFFFF_FFFF + - `AWS_CLK_GEN specifiction <./../../../docs/AWS_CLK_GEN_spec.html>`__ + +Simulations +=========== + +Please see more details on running simulations in this +`README `__ + +Software +======== + +DMA accesses rely on the `XDMA +driver `__ + +The CL_MEM_PERF example includes runtime software to demonstrate working +DMA accesses. The runtime example is located `in the runtime +directory `__ + +Following runtime tests are provided in the cl_mem_perf example: + +.. _test_hbm_perf32c: + +test_hbm_perf32.c +----------------- + +This test runs traffic and measure HBM performance aggregated across all +32 HBM Channels. + +.. _test_dram_hbm_dmac: + +test_dram_hbm_dma.c +------------------- + +This test runs a software test with data transfer with both DDR and HBM +enabled + +.. _test_hbm_perf32c-1: + +test_hbm_perf32.c +----------------- + +This test exercises all 32 HBM Channels using data transfers from +HBM_PERF_KERNEL. Achieves 400+ GB/s of writes and read performance. + +.. _test_aws_clk_genc: + +test_aws_clk_gen.c +------------------ + +This test uses `CL_CLK_FREQ `__ to measure the +clock frequencies from +`AWS_CLK_GEN <./../../../common/lib/aws_clk_gen.sv>`__ block + +.. _test_clk_freqc: + +test_clk_freq.c +--------------- + +This test uses AWS APIs to configure clock frequencies into +`AWS_CLK_GEN <./../../../common/lib/aws_clk_gen.sv>`__ block + +Compile and run instructions +---------------------------- + +.. code:: bash + + cd $CL_DIR/software/runtime + make all + sudo ./test_dram_hbm_dma + +.. _test_dram_hbm_dma_hwsw_cosimc: + +test_dram_hbm_dma_hwsw_cosim.c +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This test runs a software test with HW/SW co-simulation enabled with +both DDR and HBM enabled. + +.. _compile-and-run-instructions-1: + +Compile and run instructions +---------------------------- + +.. code:: bash + + cd $CL_DIR/software/runtime + make TEST=test_dram_hbm_dma_hwsw_cosim + sudo ./test_dram_hbm_dma_hwsw_cosim + +The test can be simulated with XSIM as follows. + +.. code:: bash + + cd $CL_DIR/verif/scripts + make C_TEST=test_dram_hbm_dma_hwsw_cosim + +HBM Performance Tests +===================== + +A runtime test is provided to measure HBM performance aggregated across +all 32 HBM Channels. The runtime test should be run on a real machine +consisting of F2 FPGA loaded with CL_MEM_PERF bitstreams. The runtime +test `test_hbm_perf32.c `__ +exercises `CL_HBM_PERF_KERNEL `__ module +to generate data across all 32 channels of the HBM running at 450MHz +speeds. The test configures to run traffic across all 32 channels. There +are config registers in CL_HBM_PERF_KERNEL that keep track of the number +of write/read requests that were serviced and timers during which the +CL_HBM_PERF_KERNEL was busy servicing the AXI3 Channels of HBM. The +runtime test reads these transaction counters to compute the aggregate +HBM performance across all the channels. + +Instructions to run HBM Performance Test +---------------------------------------- + +Run the following commands to start the runtime test + +.. code:: bash + + cd $CL_DIR/software/runtime + make all + sudo ./test_hbm_perf32 + +Sample output: + +.. code:: bash + + =================================================== + Running test_hbm_perf32 + =================================================== + slot_id = 0 + cfg_axlen = 0x0000000f + cfg_wdata = 0x12345678 + cfg_wr_ctl = 0xffffffff + cfg_rd_ctl = 0xffffffff + cfg_runtime = 0x0000001e + =================================================== + __INFO__: deassert_clk_resets() + __INFO__: initialize_hbm() + __INFO__: enable_hbm_kernl() + __INFO__: run_hbm_write_test() for 30s + __INFO__: run_hbm_read_test() for 30s + __INFO__: enable_hbm_kernl() + __INFO__: display_results() + __INFO__: ------------------------- + __INFO__: Write Performance Results + __INFO__: ------------------------- + __INFO__: calculate_perf() + __INFO__: WR CycCount = 0x00000005eaad0180 + __INFO__: WR Timer = 0x00000001bf0a2c29 + __INFO__: WR Latency = 172ns + __INFO__: WR Pending Txns = 0 + __INFO__: WR RespError = 0x00000000 + __INFO__: WR Bandwidth = 433.69 GBytes/s + __INFO__: ------------------------- + __INFO__: Read Performance Results + __INFO__: ------------------------- + __INFO__: calculate_perf() + __INFO__: RD CycCount = 0x00000005d0cad52f + __INFO__: RD Timer = 0x00000001bf0a8f0e + __INFO__: RD Latency = 280ns + __INFO__: RD Pending Txns = 0 + __INFO__: RD RespError = 0x00000000 + __INFO__: RD Bandwidth = 426.28 GBytes/s + 2023-01-24T18:13:21.555468Z, test_dram_hbm_dma, INFO, test_hbm_perf32.c +152: main(): TEST PASSED + +.. |cl_mem_perf| image:: ../../../../_static/cl_mem_perf_images/cl_mem_perf.png +.. |cl_hbm_kernel| image:: ../../../../_static/cl_mem_perf_images/cl_hbm_kernel.png diff --git a/docs-rtd/source/hdk/cl/examples/cl_mem_perf/verif/README.rst b/docs-rtd/source/hdk/cl/examples/cl_mem_perf/verif/README.rst new file mode 100644 index 000000000..11d8f3aa7 --- /dev/null +++ b/docs-rtd/source/hdk/cl/examples/cl_mem_perf/verif/README.rst @@ -0,0 +1,383 @@ +CL_MEM_PERF Example Simulation +============================== + +Table of Contents +----------------- + +- `CL_MEM_PERF Example Simulation <#cl_mem_perf-example-simulation>`__ + + - `Table of Contents <#table-of-contents>`__ + - `Overview <#overview>`__ + - `Dump Waves <#dump-waves>`__ + - `System Verilog Tests <#system-verliog-tests>`__ + + - `test_aws_clk_gen_recipe.sv (VCS and QUESTA + only) <#test_aws_clk_gen_recipesv-vcs-and-questa-only>`__ + - `test_clk_recipe.sv <#test_clk_recipesv>`__ + - `test_ddr_peek_poke.sv <#test_ddr_peek_pokesv>`__ + - `test_ddr.sv <#test_ddrsv>`__ + - `test_hbm.sv <#test_hbmsv>`__ + - `test_hbm_perf32.sv <#test_hbm_perf32sv>`__ + - `test_hbm_perf_kernel_cfg.sv <#test_hbm_perf_kernel_cfgsv>`__ + - `test_hbm_perf_random.sv <#test_hbm_perf_randomsv>`__ + - `test_dram_dma.sv <#test_dram_dmasv>`__ + - `test_dram_dma_rnd.sv <#test_dram_dma_rndsv>`__ + - `test_dma_pcim_concurrent.sv <#test_dma_pcim_concurrentsv>`__ + - `test_dma_pcis_concurrent.sv <#test_dma_pcis_concurrentsv>`__ + - `test_dma_sda_concurrent.sv <#test_dma_sda_concurrentsv>`__ + - `test_dram_dma_4k_crossing.sv <#test_dram_dma_4k_crossingsv>`__ + - `test_dram_dma_allgn_addr_4k.sv <#test_dram_dma_allgn_addr_4ksv>`__ + - `test_dram_dma_single_beat_4k.sv <#test_dram_dma_single_beat_4ksv>`__ + - `test_dram_dma_axi_mstr.sv <#test_dram_dma_axi_mstrsv>`__ + - `test_int.sv <#test_intsv>`__ + - `test_peek_poke.sv <#test_peek_pokesv>`__ + - `test_peek_poke_wc.sv <#test_peek_poke_wcsv>`__ + - `test_peek_poke_len.sv <#test_peek_poke_lensv>`__ + - `test_peek_poke_rnd_lengths.sv <#test_peek_poke_rnd_lengthssv>`__ + - `test_peek_poke_pcis_axsize.sv <#test_peek_poke_pcis_axsizesv>`__ + - `test_ddr_peek_bdr_walking_ones <#test_ddr_peek_bdr_walking_ones>`__ + - `test_sda.sv <#test_sdasv>`__ + - `test_null.sv <#test_nullsv>`__ + + - `AXI_MEMORY_MODEL Mode + Simulations <#axi_memory_model-mode-simulations>`__ + + - `test_dram_dma_mem_model_bdr_wr <#test_dram_dma_mem_model_bdr_wr>`__ + - `test_dram_dma_mem_model_bdr_rd <#test_dram_dma_mem_model_bdr_rd>`__ + + - `DDR Backdoor Loading <#ddr-backdoor-loading>`__ + + - `HW/SW Co-Simulation Test <#hwsw-co-simulation-test>`__ + +Overview +-------- + +This readme provides information about the simulation environment for +the ``cl_mem_perf`` example. For more details about overall HDK +simulation environment and CL bringup in simulation please refer to `RTL +Simulation Guide for HDK Design +Flow <../../../../docs/RTL_Simulation_Guide_for_HDK_Design_Flow.md>`__. + +The SystemVerilog (SV) simulation can be run from the +``$CL_DIR/verif/scripts/`` directory with all supported simulators (HBM +simulation using VCS & QUESTA is strongly recommended). You can run +tests by calling the make target for that test located in +``$CL_DIR/verif/scripts/Makefile.tests``: + +.. code:: bash + + make test_ddr # Runs with XSIM by default + make test_ddr VCS=1 + make test_ddr QUESTA=1 + + make test_hbm # Runs with VCS by default + +Alternatively, you can run each test by setting ``TEST=\`` +followed by the environment variables required to run that test. + +.. code:: bash + + make TEST=test_dram_dma # Runs with XSIM by default + make TEST=test_dram_dma VCS=1 + make TEST=test_dram_dma QUESTA=1 + + # To Run simulations with a 64 GB DDR DIMM # With user-controlled auto-precharge mode + make TEST=test_dram_dma USE_AP_64GB_DDR_DIMM=1 + + # To Run Simulations in AXI_MEMORY_MODEL mode + make TEST=test_dram_dma AXI_MEMORY_MODEL=1 # Runs with XSIM by default in AXI_MEMORY_MODEL mode + make TEST=test_dram_dma AXI_MEMORY_MODEL=1 VCS=1 + make TEST=test_dram_dma AXI_MEMORY_MODEL=1 QUESTA=1 + + # To Run DDR backdoor loading tests + make TEST=test_ddr_peek_bdr_walking_ones # Runs with XSIM by default + make TEST=test_ddr_peek_bdr_walking_ones VCS=1 + make TEST=test_ddr_peek_bdr_walking_ones QUESTA=1 + + # Backdoor loading test list. Description can be found in the sections below. + test_dram_dma_mem_model_bdr_rd + test_dram_dma_mem_model_bdr_wr + test_ddr_peek_bdr_walking_ones + +**NOTE**: Please refer to +`Supported_DDR_Modes.md <./../../../../docs/Supported_DDR_Modes.md>`__ +for details on supported DDR configurations. + +The HW/SW co-simulation tests can be run from the ``verif/scripts/`` +directory with all supported simulators: + +.. code:: bash + + make C_TEST=test_dram_dma_hwsw_cosim # Runs with XSIM by default + make C_TEST=test_dram_dma_hwsw_cosim VCS=1 + make C_TEST=test_dram_dma_hwsw_cosim QUESTA=1 + + # To Run in AXI_MEMORY_MODEL mode with AXI memory models instead of DDR. + make C_TEST=test_dram_dma_hwsw_cosim AXI_MEMORY_MODEL=1 (Runs with XSIM by default) + make C_TEST=test_dram_dma_hwsw_cosim AXI_MEMORY_MODEL=1 VCS=1 + make C_TEST=test_dram_dma_hwsw_cosim AXI_MEMORY_MODEL=1 QUESTA=1 + +Note that the appropriate simulators must be installed. + +Dump Waves +---------- + +For information about how to dump waves with XSIM or VCS, please refer +to +`debugging-custom-logic-using-the-aws-hdk <../../../../docs/RTL_Simulation_Guide_for_HDK_Design_Flow.md#debugging-custom-logic-using-the-aws-hdk>`__ + +System Verilog Tests +-------------------- + +The SystemVerilog tests are located at ``verif/tests/``. Most tests +include ``base_test_utils.svh`` which includes common signals and tasks +used across tests. Please refer to this file for the DPI-C tasks used. +Information about each test can be found below. + +.. _test_aws_clk_gen_recipesv-vcs-and-questa-only: + +test_aws_clk_gen_recipe.sv (VCS and QUESTA only) +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This test programs valid clock recipes to the CL and verifies the +corresponding clock frequencies. + +.. _test_clk_recipesv: + +test_clk_recipe.sv +~~~~~~~~~~~~~~~~~~ + +This test programs valid clock recipes defined within and verifies the +corresponding clock frequencies. + +.. _test_ddr_peek_pokesv: + +test_ddr_peek_poke.sv +~~~~~~~~~~~~~~~~~~~~~ + +This does a walking ones test through the DDR address range. Also checks +if any of the bits are stuck at '0'. + +.. _test_ddrsv: + +test_ddr.sv +~~~~~~~~~~~ + +This test programs the CL_TST (ATG) to generate traffic to access all +four DDR channels. + +.. _test_hbmsv: + +test_hbm.sv +~~~~~~~~~~~ + +This test programs the CL_TST (ATG) to generate traffic to access both +HBM stacks. + +.. _test_hbm_perf32sv: + +test_hbm_perf32.sv +~~~~~~~~~~~~~~~~~~ + +This test programs the HBM performance kernel to run all 32 channels for +maximum bandwidth. The kernel collects timer and bandwidth statistics +and stores them in registers. At the end of the test, the performance is +calculated and printed in the ``sim.log``. + +.. _test_hbm_perf_kernel_cfgsv: + +test_hbm_perf_kernel_cfg.sv +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This test exercises each register in the HBM performance kernel +configuration space. + +.. _test_hbm_perf_randomsv: + +test_hbm_perf_random.sv +~~~~~~~~~~~~~~~~~~~~~~~ + +This test executes the same flow as ``test_hbm_perf32.sv`` except with a +random axi length and a random number of channels. + +.. _test_dram_dmasv: + +test_dram_dma.sv +~~~~~~~~~~~~~~~~ + +Basic H2C and C2H DMA test through all 4 DDR channels and 2 HBM stacks. + +.. _test_dram_dma_rndsv: + +test_dram_dma_rnd.sv +~~~~~~~~~~~~~~~~~~~~ + +This test programs DMA transfers with random lengths. + +.. _test_dma_pcim_concurrentsv: + +test_dma_pcim_concurrent.sv +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This test programs both the DMA and PCIM traffic to run concurrently and +verifies that there are no errors on both DMA and PCIM interfaces. + +.. _test_dma_pcis_concurrentsv: + +test_dma_pcis_concurrent.sv +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This test programs both the DMA and PCIS traffic to run concurrently and +verifies that there are no errors on both DMA and PCIS interfaces. + +.. _test_dma_sda_concurrentsv: + +test_dma_sda_concurrent.sv +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This test programs both the DMA and SDA traffic to run concurrently and +verifies that there are no errors on both DMA and SDA interfaces. + +.. _test_dram_dma_4k_crossingsv: + +test_dram_dma_4k_crossing.sv +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This test programs DMA transfers that will cross a 4k boundary. All +transfers are of same length with different destination addresses. + +.. _test_dram_dma_allgn_addr_4ksv: + +test_dram_dma_allgn_addr_4k.sv +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This test programs DMA transfers that will cross a 4k boundary. All +transfers are of different length with different destination addresses. + +.. _test_dram_dma_single_beat_4ksv: + +test_dram_dma_single_beat_4k.sv +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This test programs single beat DMA transfers that will cross a 4k +boundary. + +.. _test_dram_dma_axi_mstrsv: + +test_dram_dma_axi_mstr.sv +~~~~~~~~~~~~~~~~~~~~~~~~~ + +This test configures the cl_dram_dma_axi_mstr.sv module to send and +receive traffic from the DDR in the CL design. + +.. _test_intsv: + +test_int.sv +~~~~~~~~~~~ + +This test programs enables interrupts in CL and verifies them. + +.. _test_peek_pokesv: + +test_peek_poke.sv +~~~~~~~~~~~~~~~~~ + +This test programs ATG in CL to do 128 byte PCIM reads and writes. + +.. _test_peek_poke_wcsv: + +test_peek_poke_wc.sv +~~~~~~~~~~~~~~~~~~~~ + +This test performs pcis write combine operations and reads back the +data. + +.. _test_peek_poke_lensv: + +test_peek_poke_len.sv +~~~~~~~~~~~~~~~~~~~~~ + +This test programs tester block to do PCIM reads and writes with +incremental lengths. + +.. _test_peek_poke_rnd_lengthssv: + +test_peek_poke_rnd_lengths.sv +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This test programs tester block to do PCIM reads and writes with random +lengths within valid range. + +.. _test_peek_poke_pcis_axsizesv: + +test_peek_poke_pcis_axsize.sv +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This test does PCIS peek and poke with different sizes. Although shell +model allows different size transfers on PCIS interface, Shell only +supports transfer of size 6 on PCIS interface. + +test_ddr_peek_bdr_walking_ones +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +DDR test which uses backdoor loading to populate DDR memory. The test +writes data(walking ones) for different addresses. The test backdoor +loads DDR memory and reads through frontdoor and checks that the data +matches. + +.. _test_sdasv: + +test_sda.sv +~~~~~~~~~~~ + +This test does transfers to different addresses on SDA AXIL interface. + +.. _test_nullsv: + +test_null.sv +~~~~~~~~~~~~ + +test_null is not an actual test. This is a base SystemVerilog file +needed for HW/SW co-simulation + + +AXI_MEMORY_MODEL Mode Simulations +--------------------------------- + +AXI_MEMORY_MODEL mode can be used for better simulation performance. +AXI_MEMORY_MODEL mode enables a test to run with AXI memory models +instead of DDR memory. The documentation can be found in AXI memory +model section at `RTL simulation +guide <../../../../docs/RTL_Simulation_Guide_for_HDK_Design_Flow.md>`__. +Any test that accesses DDR memory can be run in AXI_MEMORY_MODEL mode. +Below are some example tests for ECC and backdoor loading support +features of AXI memory model. + +test_dram_dma_mem_model_bdr_wr +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This test backdoor writes AXI memory model, reads through frontdoor and +checks that the data matches. + +test_dram_dma_mem_model_bdr_rd +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This test backdoor reads AXI memory model, writes through frontdoor and +checks that the data matches. + +DDR Backdoor Loading +-------------------- + +The description of DDR backdoor loading can be found in DDR backdoor loading +support section at `RTL simulation +guide <../../../../docs/RTL_Simulation_Guide_for_HDK_Design_Flow.md>`__ + +HW/SW Co-Simulation Test +------------------------ + +The software test with HW/SW co-simulation support +`test_dram_dma_hwsw_cosim.c <../software/runtime/test_dram_dma_hwsw_cosim.c>`__ +can be found at ``software/runtime/``. For Information about how HW/SW +co-simulation support can be added to a software test please refer to +"Code changes to enable HW/SW co-simulation" section in `RTL simulation +guide <../../../../docs/RTL_Simulation_Guide_for_HDK_Design_Flow.md>`__ diff --git a/docs-rtd/source/hdk/cl/examples/cl_sde/README.rst b/docs-rtd/source/hdk/cl/examples/cl_sde/README.rst new file mode 100644 index 000000000..9919d3779 --- /dev/null +++ b/docs-rtd/source/hdk/cl/examples/cl_sde/README.rst @@ -0,0 +1,156 @@ +CL_SDE Custom Logic Example +=========================== + +⚠️ **NOTE: Please note that Virtual Ethernet/SDE is not supported by +Vitis (XRT)** + +Table of Contents +----------------- + +1. `Overview <#overview>`__ +2. `System Diagram <#system-diagram>`__ +3. `Functional Description <#functional-description>`__ +4. `Interfaces and Address Range <#interfaces-and-address-range>`__ +5. `Software <#software>`__ +6. `Metadata <#metadata>`__ + +Overview +-------- + +The CL_SDE example implements the FPGA custom logic used to generate the +AFI to demonstrate the `Virtual Ethernet Application +<../../../../sdk/apps/virtual-ethernet/doc/Virtual_Ethernet_Application_Guide.html>`__. +The CL_SDE demonstrates the following: + +1. Using the `Streaming Data Engine + <../../../../sdk/apps/virtual-ethernet/doc/SDE_HW_Guide.html>`__ + (SDE) IP Block in your custom logic. +2. Connectivity between the `Virtual Ethernet Application + <../../../../sdk/apps/virtual-ethernet/doc/Virtual_Ethernet_Application_Guide.html>`__ + and the SDE. +3. Connectivity between the Shell and the SDE. +4. Clocks and Resets for the SDE. +5. Floorplanning and Implementation with the SDE including pipelining + for AXI buses, resets etc. + +System Diagram +~~~~~~~~~~~~~~ + +|CL_SDE_Block_Diagram| + +Functional Description +---------------------- + +The following functionality is implemented in the CL_SDE - + +1. Capability to loopback from H2C and C2H. +2. Memory to store and read H2C packets for H2C functional testing +3. AXI Stream Traffic Generator for C2H functional and performance testing +4. AXI4 Traffic Generator for PCIM performance testing +5. Configuration and Reset generation logic. +6. Pipelining for PCIM and PCIS interfaces. + +See `SDE HW Guide <../../../../sdk/apps/virtual-ethernet/doc/SDE_HW_Guide.html>`__ +for details about the functional description of the SDE. + +Interfaces and Address Range +---------------------------- + +Interfaces +~~~~~~~~~~ + +CL_SDE uses three interfaces from the Shell. The PCIS interface is used +to provide connectivity between the `Virtual Ethernet Application +<../../../../sdk/apps/virtual-ethernet/doc/Virtual_Ethernet_Application_Guide.html>`__ +and the SDE. The OCL interface is used to provide connectivity between +the host and all the test/control/utility blocks (except the SDE). The +PCIM interfaces is used by the SDE to read and write to host memory. + +Address Range +~~~~~~~~~~~~~ + +PCIS +^^^^ + +.. list-table:: + :header-rows: 1 + :class: user-guide-dev-envs-table + :widths: 20 20 40 + + * - Low Address + - High Address + - Description + * - 0x00_0000_0000 + - 0x00_0000_3FFF + - `SDE HW Guide <../../../../sdk/apps/virtual-ethernet/doc/SDE_HW_Guide.html>`__ + * - 0x00_0000_4000 + - 0x1F_FFFF_FFFF + - Unused + +OCL +^^^ + +.. list-table:: + :header-rows: 1 + :class: user-guide-dev-envs-table + :widths: 20 20 40 + + * - Low Address + - High Address + - Description + * - 0x0000_0000 + - 0x0000_017F + - AXI-Stream Automatic Traffic Generator + * - 0x0000_0180 + - 0x0000_0FFF + - Loopback Block + * - 0x0000_1000 + - 0x0000_10FF + - Unused + * - 0x0000_1100 + - 0x0000_11FF + - AXI4 Automatic Traffic Generator + * - 0x0000_1200 + - 0x0000_1FFF + - Unused + * - 0x0000_2000 + - 0x0000_2FFF + - CL Reset and Control + * - 0x0000_3000 + - 0x0200_0000 + - Unused + +Software +-------- + +The software is provided as part of the `Virtual Ethernet Application +<../../../../sdk/apps/virtual-ethernet/doc/Virtual_Ethernet_Application_Guide.html>`__. + +Metadata +-------- + +The following table displays information about the CL that is required +to register it as an AFI with AWS. Alternatively, you can directly use a +pre-generated AFI for this CL. + +.. list-table:: + :header-rows: 1 + :class: user-guide-dev-envs-table + :widths: 30 30 + + * - Key + - Value + * - Shell Version + - 0x10212415 + * - PCI Device ID + - 0xF002 + * - PCI Vendor ID + - 0x1D0F (Amazon) + * - PCI Subsystem ID + - 0x1D51 + * - PCI Subsystem Vendor ID + - 0xFEDC + * - Pre-generated AGFI ID + - agfi-0925b211f5a81b071 + +.. |CL_SDE_Block_Diagram| image:: ../../../../_static/cl_sde_images/CL_SDE_Block_Diagram.jpg diff --git a/docs-rtd/source/hdk/cl/examples/cl_sde/verif/README.rst b/docs-rtd/source/hdk/cl/examples/cl_sde/verif/README.rst new file mode 100644 index 000000000..a0793a50f --- /dev/null +++ b/docs-rtd/source/hdk/cl/examples/cl_sde/verif/README.rst @@ -0,0 +1,52 @@ +SDE CL Example Simulation +========================= + +Table of Contents +----------------- + +- `SDE CL Example Simulation <#sde-cl-example-simulation>`__ + + - `Table of Contents <#table-of-contents>`__ + - `Overview <#overview>`__ + - `Dump Waves <#dump-waves>`__ + +Overview +-------- + +This readme provides information about the simulation environment for +the ``cl_sde`` example. For more details about overall HDK simulation +environment and CL bringup in simulation please refer to `RTL Simulation +Guide for HDK Design +Flow <../../../../docs/RTL_Simulation_Guide_for_HDK_Design_Flow.md>`__. + +The system verilog simulation tests can be run from the +``$CL_DIR/verif/scripts/`` directory with all supported simulators. You +can run each test by setting ``TEST=\``. + +.. code:: bash + + cd aws-fpga + source hdk_setup.sh + cd hdk/cl/examples/cl_sde + export CL_DIR=$(pwd) + cd ${CL_DIR}/verif/scripts + +Run the tests + +.. code:: bash + + make TEST=test_simple_h2c (Runs with XSIM by default) + make TEST=test_simple_c2h (Runs with XSIM by default) + + make TEST=test_simple_h2c VCS=1 + make TEST=test_simple_c2h VCS=1 + + make TEST=test_simple_h2c QUESTA=1 + make TEST=test_simple_c2h QUESTA=1 + +Dump Waves +---------- + +For information about how to dump waves with XSIM or VCS, please refer +to +`debugging-custom-logic-using-the-aws-hdk <../../../../docs/RTL_Simulation_Guide_for_HDK_Design_Flow.md#debugging-custom-logic-using-the-aws-hdk>`__ diff --git a/docs-rtd/source/hdk/docs/AWS_CLK_GEN_spec.rst b/docs-rtd/source/hdk/docs/AWS_CLK_GEN_spec.rst new file mode 100644 index 000000000..d04e78b2b --- /dev/null +++ b/docs-rtd/source/hdk/docs/AWS_CLK_GEN_spec.rst @@ -0,0 +1,505 @@ +AWS_CLK_GEN - CL Clock Generator +====================================== + +Table of Contents +----------------- + +- `AWS_CLK_GEN - CL Clock Generator <#aws_clk_gen---cl-clock-generator>`__ + + - `Table of Contents <#table-of-contents>`__ + - `Introduction <#introduction>`__ + - `Architecture Overview <#architecture-overview>`__ + - `Clock and Reset <#clock-and-reset>`__ + - `Ports Description <#ports-description>`__ + - `Address Space <#address-space>`__ + - `Register Definitions <#register-definitions>`__ + - `Clock Recipes User Guide <#clock-recipes-user-guide>`__ + - `Implementation Example <#implementation-example>`__ + +Introduction +------------ + +F1 Shell provides eight clocks to the CL and supports multiple `clock +recipes `__ +to choose from at the time of CL builds. It also allows to scale clock +frequencies during runtime (or after AFI/bitstream is loaded into FPGA) +using +`dynamic_clock_config `__. +While this architecture provides multiple clock choices for customer +designs, it locks up the global clock routing resources in the CL +region. This can pose limitations for customers who do not require all +the clocks provided from Shell to the CL. + +Therefore, F2 Shell provides only two clocks - ``clk_main_a0`` and +``clk_hbm_ref`` - to the CL resulting in efficient use of global routing +resources. The ``clk_main_a0`` is currently a fixed frequency 250MHz +clock (❗ dynamic scaling of frequency as F1 using the SW APIs will be added +in a future release). The ``clk_hbm_ref`` is a fixed frequency 100MHz clock +which can be used by customer as a reference clock for their MMCMs. This scheme +provides flexibility for customers to devise their own clocking mechanisms with +desired number of clocks. + +In order to provide F1’s clock recipes in F2, as well as support Vitis +development in F2, AWS offers the Clock Generator +(AWS_CLK_GEN) IP. AWS_CLK_GEN provides various clocks to the CL design +and supports dynamic frequency scaling. The Vitis XSA for F2 relies on +AWS_CLK_GEN for all the clocking needs in the design. This document +details the Microarchitecture Specification for AWS_CLK_GEN. + +⚠️ The AWS_CLK_GEN instantiation **must** be named to +``AWS_CLK_GEN`` and located in the CL top module. + +⚠️ The AWS_CLK_GEN is optional for CL designs that do not require +same clocking scheme as F1. This IP is not required if the CL designs +use only ``clk_main_a0`` and/or ``clk_hbm_ref``. + +Architecture Overview +--------------------- + +Figure 1 below shows an overview of the AWS_CLK_GEN IP. It primarily +consists of the following: + +1. MMCMs to generate desired clocks. The clocks are grouped together and + are generated by specific MMCM assigned to that clock group. Please + refer to + `PG065-Clocking-Wizard-v6.0-LogiCORE-IP-Product-Guide `__ + for MMCM details. + +2. AWS_CLK_REGS houses few AWS specific Control and Status Registers for + the IP. This block is also responsible for driving various resets to + the customer design. + +3. AXI-Lite address decoder. + +4. AXI-Lite clock converter. + +5. AXI-Lite interface to connect to the AWS Shell or user defined + address space. + +|aws_clk_gen| + +Clock and Reset +--------------- + +The AWS_CLK_GEN IP requires following primary clocks and resets as +inputs: + +1. clk_hbm_ref : This is fixed frequency 100MHz clock from the Shell. + This is used as primary clock for the entire IP including the MMCMs + and AWS_REGS. +2. clk_main_a0 : This is interface clock from Shell whose frequency is + scaled by the Shell but maxes out at 250MHz. +3. rst_main_n : Active low reset from Shell. + +Ports Description +----------------- + +.. list-table:: + :header-rows: 1 + :class: user-guide-dev-envs-table + :widths: 20 30 50 + + * - Port Name + - Direction + - Description + * - i_clk_hbm_ref + - input + - HBM ref clock from the Shell. Fixed frequency of 100MHz. + * - i_clk_main_a0 + - input + - clk_main_a0 from the Shell. + * - i_rst_main_n + - input + - rst_main_n from the Shell sync'ed to clk_main_a0 + * - s_sh_cl_cctrl_axil + - AXI-L Consumer interface + - AXI-Lite interface to access address space of the IP. Recommend connecting + this interface to AXI-Lite on PF1-BAR4 from the Shell. + * - clk_hbm_ref + - output + - Pass-through of input clk_hbm_ref from the Shell. + * - clk_main_a0 + - output + - Pass-through of input clk_main_a0 from the Shell. + * - clk_extra_a1 + - output + - Max frequency = 125 MHz + * - clk_extra_a2 + - output + - Max frequency = 375 MHz + * - clk_extra_a3 + - output + - Max frequency = 500 MHz + * - clk_extra_b0 + - output + - Max Frequency = 450 MHz | Used by Vitis as ap_clk0 + * - clk_extra_b1 + - output + - Max Frequency = 225 + * - clk_extra_c0 + - output + - Max Frequency = 300 MHz | used by Vitis as ap_clk1 + * - clk_extra_c1 + - output + - Max Frequency = 400 MHz + * - clk_hbm_axi + - output + - Max Frequency = 450 MHz + * - cl_rst_main_n + - output + - rst_main_n sync'ed to clk_main_a0 and controlled by SYS_RST + * - cl_rst_a1_n + - output + - rst_main_n sync'ed to clk_extra_a1 and controlled by SYS_RST + * - cl_rst_a2_n + - output + - rst_main_n sync'ed to clk_extra_a2 and controlled by SYS_RST + * - cl_rst_a3_n + - output + - rst_main_n sync'ed to clk_extra_a3 and controlled by SYS_RST + * - cl_rst_b0_n + - output + - rst_main_n sync'ed to clk_extra_b0 and controlled by SYS_RST + * - cl_rst_b1_n + - output + - rst_main_n sync'ed to clk_extra_b1 and controlled by SYS_RST + * - cl_rst_c0_n + - output + - rst_main_n sync'ed to clk_extra_c0 and controlled by SYS_RST + * - cl_rst_c1_n + - output + - rst_main_n sync'ed to clk_extra_c1 and controlled by SYS_RST + * - cl_rst_hbm_ref_n + - output + - rst_main_n sync'ed to clk_hbm_ref and controlled by SYS_RST + * - cl_rst_hbm_axi_n + - output + - rst_main_n sync'ed to clk_hbm_axi and controlled by SYS_RST + +Address Space +------------- + +The AXI-Lite address space is decoded as shown in the table below: + +.. list-table:: + :header-rows: 1 + :class: user-guide-dev-envs-table + :widths: 10 10 5 5 70 + + * - Address Start + - Address End + - Size + - Decode + - Description + * - 0x0005_2000 + - 0x0005_2FFF + - 4KB + - BASE_A + - MMCM registers for clock group A. See + `Example-for-Dynamic-Reconfiguration-through-AXI4-Lite `__ + * - 0x0005_0000 + - 0x0005_0FFF + - 4KB + - BASE_B + - MMCM registers for clock group B. See + `Example-for-Dynamic-Reconfiguration-through-AXI4-Lite `__ + * - 0x0005_1000 + - 0x0005_1FFF + - 4KB + - BASE_C + - MMCM registers for clock group C. See + `Example-for-Dynamic-Reconfiguration-through-AXI4-Lite `__ + * - 0x0005_4000 + - 0x0005_4FFF + - 4KB + - BASE_HBM + - MMCM registers for HBM interface clock. See + `Example-for-Dynamic-Reconfiguration-through-AXI4-Lite `__ + * - 0x0005_8000 + - 0x0005_8FFF + - 4KB + - BASE_REG + - Address space for AWS specific registers in AWS_CLK_REGS. + +**NOTES**: + +1. Refer to the ``_clkgen`` CLIs in `FPGA Management + Tools <./../../sdk/userspace/fpga_mgmt_tools/README.md>`__ for + setting the output clock frequencies of AWS_CLK_GEN IP. + +2. Write access to undefined address space is ignored. Reading from + undefined address space returns 0xDEAD_DEC0. Reading from undefined + address space within MMCM results in MMCM’s default behavior. + AWS_CLK_GEN IP does not have any protection against illegal use of + MMCMs. User discretion is recommended regarding such accesses. + +Register Definitions +-------------------- + +Following registers are housed inside AWS_CLK_REGS component and are +accessible from the AXIL interface from base address = ``BASE_REG`` as +described in `Address Space <#ancAddressSpace>`__ + +.. list-table:: + :header-rows: 1 + :class: user-guide-dev-envs-table + :widths: 10 10 5 5 10 60 + + * - Address Offset + - Register Name + - Bits + - Access + - Default Value + - Description + * - 0x00 + - ID_REG + - 31:0 + - RO + - 0x9048_1D0F + - 32-bit value to uniquely identify the AWS_CLK_GEN IP + * - 0x04 + - VER_REG + - 31:0 + - RO + - 0x0201_0000 + - Version Register + * - 0x08 + - BUILD_REG + - 31:0 + - RO + - 0x0923_2223 + - build timestamp in 0xMM_DD_YY_HH format + * - 0x0C + - CLKS_AVAIL_REG + - 31:9 + - RO + - 0x0 + - Reserved + * - + - + - 8 + - RO + - 0x1 + - 1 = clk_hbm_axi available | 0 = clock unavailable + * - + - + - 7 + - RO + - 0x1 + - 1 = clk_extra_c1 available | 0 = clock unavailable + * - + - + - 6 + - RO + - 0x1 + - 1 = clk_extra_c0 available | 0 = clock unavailable + * - + - + - 5 + - RO + - 0x1 + - 1 = clk_extra_b1 available | 0 = clock unavailable + * - + - + - 4 + - RO + - 0x1 + - 1 = clk_extra_b0 available | 0 = clock unavailable + * - + - + - 3 + - RO + - 0x1 + - 1 = clk_extra_a3 available | 0 = clock unavailable + * - + - + - 2 + - RO + - 0x1 + - 1 = clk_extra_a2 available | 0 = clock unavailable + * - + - + - 1 + - RO + - 0x1 + - 1 = clk_extra_a1 available | 0 = clock unavailable + * - + - + - 0 + - RO + - 0x1 + - 1 = clk_main_a0 available | 0 = clock unavailable + * - 0x10 + - G_RST_REG + - 31:0 + - RW + - 0x0 + - Write 0xFFFF_FFFF to globally reset the AWS_CLK_GEN IP. Following blocks + are affected: + - Assert reset to all MMCMs. + - Assert reset to SYS_RST and its output to CL. + Write 0x0000_0000 to de-assert global resets + * - 0x14 + - SYS_RST_REG + - 31:10 + - RW + - 0xFF + - Reserved + * - + - + - 9 + - RW + - 0x1 + - 1 = Assert reset on cl_rst_hbm_axi_n + * - + - + - 8 + - RW + - 0x1 + - 1 = Assert reset on cl_rst_hbm_ref_n + * - + - + - 7 + - RW + - 0x1 + - 1 = Assert reset on cl_rst_c1_n + * - + - + - 6 + - RW + - 0x1 + - 1 = Assert reset on cl_rst_c0_n + * - + - + - 5 + - RW + - 0x1 + - 1 = Assert reset on cl_rst_b1_n + * - + - + - 4 + - RW + - 0x1 + - 1 = Assert reset on cl_rst_b0_n + * - + - + - 3 + - RW + - 0x1 + - 1 = Assert reset on cl_rst_a3_n + * - + - + - 2 + - RW + - 0x1 + - 1 = Assert reset on cl_rst_a2_n + * - + - + - 1 + - RW + - 0x1 + - 1 = Assert reset on cl_rst_a1_n + * - + - + - 0 + - RW + - 0x1 + - 1 = Assert reset on cl_rst_main_n. NOTE: cl_rst_main_n is deasserted by default + * - + - + - + - + - + - NOTE: This register takes effect only if G_RST_REG = 0 + * - 0x18 + - DIS_RST_MAIN_REG + - 0 + - RW + - 0x0 + - Reserved + * - + - + - 31:1 + - RO + - 0x0 + - 1 = Disable rst_main_n from asserting resets in SYS_RST block. i.e rst_main_n no longer affects the reset outputs from SYS_RST block + * - 0x20 + - MMCM_LOCK_REG + - 31:9 + - RO + - 0x0 + - Reserved + * - + - + - 8 + - RO + - 0x0 + - 1 = MMCM_BASE_HBM locked + * - + - + - 7 + - RO + - 0x0 + - Reserved + * - + - + - 6 + - RO + - 0x0 + - 1 = MMCM_BASE_C locked + * - + - + - 5 + - RO + - 0x0 + - Reserved + * - + - + - 4 + - RO + - 0x0 + - 1 = MMCM_BASE_B locked + * - + - + - 3 + - RO + - 0x0 + - Reserved + * - + - + - 2 + - RO + - 0x0 + - Reserved + * - + - + - 1 + - RO + - 0x0 + - Reserved + * - + - + - 0 + - RO + - 0x0 + - 1 = MMCM_BASE_A locked + +**NOTE**: Write access to undefined address space is ignored. Reading from +undefined address space returns ``0xDEAD_DEC0``. + +Clock Recipes User Guide +------------------------ + +The `Clock Recipes User Guide <./Clock_Recipes_User_Guide.html>`__ +describes various clock recipes available for F2 developers and build +options support in the HDK development environment. The user guide also +describes porting of CL designs based on F1 clock recipes into F2. + +Implementation Example +---------------------- + +Usage of the AWS_CLK_GEN IP is fully demonstrated in the +`cl_mem_perf <../cl/examples/cl_mem_perf/README.html>`__ example. Please +refer to that example for more details. + +.. |aws_clk_gen| image:: ./../../_static/aws_clk_gen.png diff --git a/docs-rtd/source/hdk/docs/AWS_Fpga_Pcie_Memory_Map.rst b/docs-rtd/source/hdk/docs/AWS_Fpga_Pcie_Memory_Map.rst new file mode 100644 index 000000000..46f7cba55 --- /dev/null +++ b/docs-rtd/source/hdk/docs/AWS_Fpga_Pcie_Memory_Map.rst @@ -0,0 +1,102 @@ +AWS FPGA PCIe Memory Map +======================== + +FPGAs are PCIe-attached to an AWS EC2 instance. Each FPGA slot presents +a single FPGA with two PCIe Physical Functions (PFs), each with multiple +PCIe Base Address Registers (BARs) as defined in the `AWS Shell +Specification <./AWS_Shell_Interface_Specification.html>`__. + +This document describes the size and attributes of each BAR. Even though +all of these PCIe BARs are mapped to the EC2 Instance memory-mapped I/O +(MMIO) space, they need to be mapped to the Linux kernel or a userspace +application before accessing them. + +Memory Map per Slot +------------------- + +.. code:: text + + --- FPGA Slot X + |--- Application PF (AppPF) + | |-- BAR0 + | | * 64-bit, prefetchable + | | * 64MiB (0x000_0000 to 0x3FF_FFFF) + | | * Mapped to the OCL AXI-lite interface of CL + | | * Typically used for CL application registers or OpenCL kernels + | | + | |-- BAR2 + | | * 64-bit, prefetchable + | | * 64KiB (0x0000 to 0xFFFF) + | | * Not mapped to CL. + | | * Used by internal DMA inside the Shell + | | + | |-- BAR4 + | * 64-bit, prefetchable + | * 128GiB (0x00_0000_0000 to 0x1F_FFFF_FFFF) + | * Mapped to the PCIS AXI4 interface of CL + | * Typically used for DMA traffic bewteen the host and HBM/DDR memories on the card + | + |--- Management PF (MgmtPF) + |-- BAR0 + | * 64-bit, prefetchable + | * 16KiB (0x0000 to 0x3FFF) + | * Not mapped to CL + | * Used by the FPGA management tools + | + |-- BAR2 + | * 64-bit, prefetchable + | * 16KiB (0x0000 to 0x3FFF) + | * Not mapped to CL + | * Used by the FPGA management tools + | + |-- BAR4 + * 64-bit BAR, prefetchable + * 4MiB (0x00_0000 to 0x3F_FFFF) + * Mapped to the SDA AXI-lite interface of CL + * Could be used by developer applications, AWS CL clock generator , or if using the AWS Runtime Environment (like SDAccel case), it will be used for performance monitoring. + +Prefetchable BAR Setting +------------------------ + +The F2 shell is configured with all the Base Address Registers (BARs) in +the host PCIe endpoint as prefetchable. Prefetchable BARs allow the use +of optimization techniques like prefetching, write-combining (also +referred to as write-merging) to improve the BAR-access performance. To +take advantage of that, customers must ensure the logic mapped to a +prefetchable BAR complies with the PCIe specification (see section +7.5.1.2.1 for details). This design choice was carefully considered to +allow F2, a general-purpose accelerator platform, to be easily +integrated with a wide range of customer acceleration applications. +Customers who do not require these optimizations can still access +prefetchable BARs in a non-prefetchable way without penalty or side +effect. + +Marking a PCIe BAR as prefetchable or non-prefetchable is a hardware +design decision driven by providing maximum flexibility to the software +because the configuration cannot be modified by the customer. AWS offers +this flexibility to F2 customers by advertising all the BARs in the +shell as prefetchable. Customer applications must access BARs in a way +supported by the customer logic (CL). For example, enabling +write-combining on a prefetchable BAR requires a custom kernel driver or +application to map and mark the target memory space as `write-combining +(WC) +memory `__. +Additionally, applications enabling prefetching should avoid caching +data from a memory space that contains any clear-on-read registers or +FIFOs. + +The PCIe specification encourages the use of prefetchable BAR memory +space whenever possible, even if a BAR might contain non-prefetchable +logic. As stated in the "Additional Guidance on the Prefetchable Bit in +Memory Space BARs" under the PCIe specification, section 7.5.1.2.1, +there are system configurations where having the Prefetchable bit set +can still allow correct operation, even if the conditions for +prefetchability are not met. + +Third-party accelerator cards +[`1 `__, +`2 `__] that are +compatible with the F2 card (with multi-SLR, HBM FPGA) also only carry +prefetchable BARs. Aligning the F2 BAR settings with these cards +provides our customers flexibility to migrate between on-premise and +cloud without having to change software/hardware. diff --git a/docs-rtd/source/hdk/docs/AWS_Shell_ERRATA.rst b/docs-rtd/source/hdk/docs/AWS_Shell_ERRATA.rst new file mode 100644 index 000000000..fb709e5d6 --- /dev/null +++ b/docs-rtd/source/hdk/docs/AWS_Shell_ERRATA.rst @@ -0,0 +1,36 @@ +AWS EC2 F2 Shell Errata +======================= + +Implementation Restrictions +--------------------------- + +- PCIE AXI4 interfaces between Custom Logic(CL) and Shell(SH) have + following restrictions: + + - All PCIe transactions must adhere to the PCIe base spec + - 4-KByte address boundary for all transactions (PCIe restriction) + - Multiple outstanding outbound PCIe read transactions with same ID is + not supported + - PCIe extended tag not supported. Read-request is limited to 32 + outstanding + - Address must match DoubleWord(DW) address of the transaction + - WSTRB (write strobe) must reflect appropriate valid bytes for AXI + write beats + - Only increment burst type is supported + - AXI lock, memory type, protection type, quality of service (QoS) and + region identifier are not supported + - Transactions from the Shell to CL must complete within the timeout + period to avoid transaction termination by the Shell + - DMA transactions from the Shell to CL must complete within the + timeout period to avoid transaction termination and invalid data + returned for the DMA transaction + - PCIM and DMA-PCIS AXI4 interfaces do not support AxSIZE other than + 3'b110 (64B) + +Unsupported Features +-------------------- + +- HBM metrics not yet supported + +Known Bugs/Issues +----------------- diff --git a/docs-rtd/source/hdk/docs/AWS_Shell_Interface_Specification.rst b/docs-rtd/source/hdk/docs/AWS_Shell_Interface_Specification.rst new file mode 100644 index 000000000..56dc49270 --- /dev/null +++ b/docs-rtd/source/hdk/docs/AWS_Shell_Interface_Specification.rst @@ -0,0 +1,1009 @@ +AWS Shell Interface Specification +================================= + +Table of Contents +----------------- + +- `AWS Shell Interface + Specification <#aws-shell-interface-specification>`__ + + - `Table of Contents <#table-of-contents>`__ + - `Overview <#overview>`__ + + - `Architecture and Version <#architecture-and-version>`__ + - `Conventions <#conventions>`__ + + - `Shell Interfaces <#shell-interfaces>`__ + - `External FPGA Interfaces <#external-fpga-interfaces>`__ + + - `FPGA PCIe Representation to EC2 + Instance <#fpga-pcie-representation-to-ec2-instance>`__ + + - `Management PF (MgmtPF) <#management-pf-mgmtpf>`__ + - `Application PF (AppPF) <#application-pf-apppf>`__ + + - `DDR4 DRAM <#ddr4-dram>`__ + - `DDR4 AXI <#ddr4-axi>`__ + - `DMA <#dma>`__ + + - `Interfaces between Shell and + CL <#interfaces-between-shell-and-cl>`__ + + - `CL/Shell AXI Interfaces <#cl-shell-axi-interfaces>`__ + - `Clocks and Reset <#clocks-and-reset>`__ + + - `Clocks <#clocks>`__ + - `Reset <#reset>`__ + + - `PCIS Interface <#pcis-interface>`__ + + - `PCIS Interface Timeout + Details <#pcis-interface-timeout-details>`__ + + - `PCIM Interface <#pcim-interface>`__ + - `Outbound PCIe AXI-4 Interface + Restrictions <#outbound-pcie-axi-4-interface-restrictions>`__ + - `Byte Enable Rules <#byte-enable-rules>`__ + - `AXI4 Error Handling for CL outbound Transactions <#axi4-error-handling-for-cl-outbound-transactions>`__ + - `OCL/SDA Interfaces for Register Access <#ocl-sda-interfaces-for-register-access>`__ + + - `CL AXI Completer Error Reporting <#cl-axi-completer-error-reporting>`__ + + - `Accessing Aligned/Unaligned Addresses from PCIe (Shell is Requester, CL is Completer) <#accessing-alignedunaligned-addresses-from-pcie-shell-is-requester-cl-is-completer>`__ + - `Interrupts <#interrupts>`__ + - `HBM Monitor Interface <#hbm-monitor-interface>`__ + - `Miscellaneous Signals <#miscellaneous-signals>`__ + + - `Integrity Check <#integrity-check>`__ + - `General Control/Status <#general-controlstatus>`__ + - `Virtual LED/DIP <#virtual-leddip>`__ + - `Global Counters <#global-counters>`__ + + - `Implementation Tips <#implementation-tips>`__ + + - `Multi-SLR FPGA <#multi-slr-fpga>`__ + - `Logic Levels <#logic-levels>`__ + - `Reset <#reset-1>`__ + - `Pipeline Registers <#pipeline-registers>`__ + - `Vivado Analysis <#vivado-analysis>`__ + +Overview +-------- + +With Amazon EC2 FPGA instances, each FPGA is divided into two +partitions: + +- Shell (SH) – AWS platform logic implementing the FPGA external + peripherals, PCIe, DMA, and Interrupts. +- Custom Logic (CL) – Custom acceleration logic created by an FPGA + Developer. + +At the end of the development process, combining the Shell and CL +creates an Amazon FPGA Image (AFI) that can be loaded onto the Amazon +EC2 FPGA Instances. + +This document specifies the hardware interface and functional behavior +between the SH and the CL. + +Architecture and Version +~~~~~~~~~~~~~~~~~~~~~~~~ + +This specification applies to Xilinx Virtex Ultrascale+ platform +available on EC2 F2. Each update of the Shell is tagged with a revision +number. Note while AWS tries to keep the revision constant, sometimes it +is necessary to update the revision due to discovered issues or added +functionality. The HDK release includes the latest Shell version under +`shell_stable <./../common/shell_stable/>`__ + +The Shell is reconfigurable, allowing developers to select which Shell +version to create the AFI with. However, an AFI is tied to the specific +Shell version it is built with. Therefore, customers should re-build CL +design if they choose to use another version of the Shell. + +Conventions +~~~~~~~~~~~ + +**CL –** Custom Logic: Custom design created by the developer and +integrated with AWS Shell. + +**DW –** Double Word (DW): Refers to 4-byte (32-bit) data size. + +`AXI-4 ARM Advanced eXtensible +Interface. `__ + +`AXI-4 Stream – ARM Advanced eXtensible Stream +Interface. `__ + +**M –** Typically refers to the Requester (M) side of an AXI bus. + +**S –** Typically refers to the Completer (S) side of an AXI bus. + +Shell Interfaces +---------------- + +The following diagram and table summarize the various interfaces between +the Shell and CL as defined in +`cl_ports.vh <../common/shell_stable/design/interfaces/cl_ports.vh>`__. + +|F2_Shell_interface| + +.. list-table:: + :header-rows: 1 + :class: user-guide-dev-envs-table + :widths: 20 80 + + * - Interface + - Description + * - Clocks and Resets + - There are multiple clocks and resets provided by the Shell to the CL. + Refer to the `Clocks and Resets <#clocks-and-reset>`__ section for more + information. + * - PCIM + - The PCIe Requester (PCIM) Interface is an AXI-4 interface used for + Outbound PCIe transactions. Refer to the `PCIM Interface <#pcim-interface>`__ + section for more information. + * - PCIS + - The PCIe Completer (PCIS) Interface is an AXI-4 interface used for + Inbound PCIe transactions. Refer to the `PCIS Interface <#pcis-interface>`__ + section for more information. + * - OCL + - The OCL Interface is an AXI-Lite interface associated with AppPF and BAR0. + Refer to the `OCL/SDA AXI-Lite Interfaces for Register Access <#ocl-sda-interfaces-for-register-access>`__ + session for more information. + * - Miscellaneous + - There are various generic signals, such as ID's, status, counters, etc., + between the Shell and CL that are described in the + `Miscellaneous Signals <#miscellaneous-signals>`__ section. + * - SDA + - The SDA Interface is an AXI-Lite interface associated with MgmtPF and + BAR4. Please refer to the + `OCL/SDA AXI-Lite Interfaces for Register Access <#ocl-sda-interfaces-for-register-access>`__ + for more information. + * - HBM MON APB + - The HBM monitor interfaces. Customers using HBM IP are required to + connect these interfaces to the HBM IP. Refer to the + `HBM monitor interface <#hbm-monitor-interface>`__ for more information. + * - DDR4 Stats + - This is the control interface from the Shell to the DDR4 Controller in + the CL. Shell uses this interface to calibrate the DDR core. Refer to + the `DDR4 DRAM <#ddr4-dram>`__ section for more information. + * - Interrupts + - There are 16 user interrupts available. Refer to the + `Interrupts <#interrupts>`__ section for more information. + +External FPGA Interfaces +------------------------ + +The FPGA platform includes the following external interfaces: + +- One x8 PCI Express 4.0 Interface. + +- One DDR4 DIMM interfaces, 72-bit wide (including ECC). + +FPGA PCIe Representation to EC2 Instance +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +There are two PCIe Physical Functions (PFs) presented to the instance: + +- Management PF – This PF is used for management of the FPGA. The + Management PF provides access to various control functions like + Virtual-LED, Virtual-DIPSwitch. + +- Application PF (AppPF)– The AppPF is used for CL specific + functionality. + +Please refer to `PCI Address map <./AWS_Fpga_Pcie_Memory_Map.html>`__ for +a more detailed view of the address map. + +Management PF (MgmtPF) +^^^^^^^^^^^^^^^^^^^^^^ + +The Management PF details are provided for reference to help +understanding the PCIe mapping from an F2 instance. This interface is +strictly used by the AWS FPGA Management Tools. + +The Management PF exposes: + +a) Amazon’s specific Shell Version and Revision numbers. + +b) Three BARs: + + - BAR0 - 16KiB + - BAR2 - 16KiB + - BAR4 - 4MiB + +c) A range of 32-bit addressable registers. + +The Management PF is persistent throughout the lifetime of the instance, +and it will not be reset or cleared (even during the AFI Load/Clear +process). + +Application PF (AppPF) +^^^^^^^^^^^^^^^^^^^^^^ + +The Application PF exposes: + +a) PCIe BAR0 as a 64-bit prefetchable BAR sized as 64MiB. This BAR maps +to the OCL AXI-Lite interface. + +b) PCIe BAR2 as a 64-bit prefetchable BAR sized as 64KiB. This BAR is +not CL visible. This BAR maps to the MSI-X tables and XDMA (if enabled). + +c) PCIe BAR4 as a 64-bit prefetchable BAR sized as 128GiB. This BAR may +be used to map the entire External/Internal memory space to the instance +address space if desired, through ``mmap()`` type calls or use +``fpga_pci_lib`` APIs. + +d) BusMaster capability to allow the CL to initiate transactions towards +the instance memory. + +e) CL’s specific PCIe VendorID, DeviceID, VendorSystemID and SubsystemID +as registered through ``aws ec2 fpgaImageCreate`` + +The Developer can write drivers for the AppPF or leverage the reference +driver provided in the SDK. + +The PCIe interface connecting the FPGA to the instance is in the Shell, +and the CL can access it through two AXI-4 interfaces: + +- `PCI Completer + (PCIS) <#pcis-interface>`__ + +- `PCI Requester + (PCIM) <#pcim-interface>`__ + +DDR4 DRAM +~~~~~~~~~ + +FPGA card provides one DDR DIMM that can be interfaced with the CL +design. AWS offers the DDR Controller IP readily configured to suit the +DDR DIMM's configuration in the +`sh_ddr.sv <../common/shell_stable/design/sh_ddr/synth/sh_ddr.sv>`__ +file which should be instantiated in the CL. The ``sh_ddr_stat_bus*`` +ports in ``sh_ddr.sv`` should be connected to the respective +``sh_cl_ddr_stat*`` ports in the ``cl_ports.vh`` along with the DDR I/O +ports. It exposes a 512-bit AXI-4 interface ``cl_sh_ddr_axi_*`` for the +CL design to drive traffic requests into the DDR. The ``sh_ddr.sv`` has +been optimized to reduce resource footprint in the FPGA, yet offer max +DDR performance. It comes with all the required constraints for the +implementation, and also ensures DDR calibration upon CL AFI loads into +the FPGA. + +**NOTE:** Even if DDR controller is not required in the CL design, the +``sh_ddr.sv`` block **must** be instantiated in the CL, with parameter +``DDR_PRESENT=0`` (defaults to DDR_PRESENT=1). This will automatically +remove DDR Controller IP, and instead, adds the required buffers to +properly load or terminate the I/O pins interfacing the external DDR +DIMM. **WARNING** If the CL does not instantiate the ``sh_ddr.sv`` +block, then it will result in implementation errors. + +DDR4 AXI +~~~~~~~~ + +The DDR4 Controller has an AXI-4 interface with a 512-bit data bus. + +The DRAM interface is accessed via an AXI-4 interface: + +- AXI-4 (CL is Requester and DRAM controller is Completer) – 512-bit + AXI-4 interface to read/write DDR. + +There is a single status signal that the DRAM interface is trained and +ready for access. DDR access should be gated when the DRAM interface is +not ready. The addressing uses ROW/COLUMN/BANK (Interleaved) mapping of +AXI address to DRAM Row/Col/BankGroup. The Read and Write channels are +serviced with round-robin arbitration (i.e. equal priority). + +The DRAM interface uses the Xilinx DDR-4 Interface controller. The AXI-4 +interface adheres to the Xilinx specification. Uncorrectable ECC errors +are signaled with RRESP. ECC error status can be read using AWS +Management Software APIs. + +Additionally, there is a statistics interface between the Shell and CL. +If the DDR controllers are being used by the CL, then the interfaces +must be connected between the Shell and the DRAM interface controller +modules. + +**WARNING:** If the stats interfaces are not connected, the DDR +controllers will not function. However, the CL developer should not +otherwise use them since they are specific to Shell management +functions. If the DDR controllers are not used by the CL, then the +interfaces should be left unconnected. + +DMA +~~~ + +There is an integrated DMA controller inside the XDMA Shell (Xilinx DMA, +not supported at this time), which writes/reads data to/from the CL via +the sh_cl_pcis_dma bus. Because of the shared DMA/PCIS interface, this +maps to the same address space exposed by the AppPF BAR4 address. XDMA +driver is available on Xilinx +`github `__. + +Interfaces between Shell and CL +------------------------------- + +CL/Shell AXI Interfaces +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +All AXI interfaces use the AXI-4 or AXI-Lite protocol. The AXI-L buses are +for register access use cases, and can access lower speed control +interfaces that use the AXI-Lite protocol. + +For bulk data transfer, wide AXI-4 buses are used. AXI-4 on the CL/Shell +interfaces have the following restrictions: + +- AxBURST – Only INCR burst is supported. +- AxLOCK – Lock is not supported. +- AxCACHE – Memory type is not supported. +- AxPROT – Protection type is not supported. +- AxQOS – Quality of Service is not supported. +- AxREGION – Region identifier is not supported. + +These signals are not included on the AXI-4 interfaces of the shell. If +connecting to a fabric or component that supports these signals, these +constant values should be used: + +.. list-table:: + :header-rows: 1 + :class: user-guide-dev-envs-table + :widths: 20 60 + * - Signal + - Value + * - AxBURST[1:0] + - 0b01 + * - AxLOCK[1:0] + - 0b00 + * - AxCACHE[3:0] + - 0b000x (bit 0 is Bufferable bit and may be 0 or 1) + * - AxPROT[2:0] + - 0b000 + * - AxQOS[3:0] + - 0b0000 + * - AxREGION[3:0] + - 0b0000 + +Clocks and Reset +~~~~~~~~~~~~~~~~ + +Clocks +^^^^^^ + +The Shell provides 250MHz ``clk_main_a0`` and 100MHz ``hbm_ref_clk`` +from shell-to-CL. Customers can use these clocks in their designs +directly or instantiate MMCMs to generate clock frequencies of interest +for their designs. All the interfaces between the CL and SH, as listed +in +`cl_ports.vh <../common/shell_stable/design/interfaces/cl_ports.vh>`__ +are synchronous to ``clk_main_a0``. The CL design must perform the +required clock domain crossing when interfacing logic in another clock +domain with Shell-CL interface ports. + +Please note that the extensive list of clocks and resets, as compared to +F1 shell, are removed from Shell-CL interface. This improves overall +routability for the CL designs that do not require all those multiple +clocks from the Shell. However, AWS offers +`AWS_CLK_GEN <./AWS_CLK_GEN_spec.html>`__ IP that supports multiple +clocks, resets and clock recipes similar to F1. The AWS_CLK_GEN IP can +be optionally instantiated in the CL for an easier migration of designs +from F1 involving multiple clocks. +`CL_MEM_PERF <./../cl/examples/cl_mem_perf/design/cl_mem_perf.sv>`__ +demonstrates integration of `AWS_CLK_GEN +IP <../common/lib/aws_clk_gen.sv>`__ into CL design. + +Please refer to the +`Clock Recipes User Guide <./Clock_Recipes_User_Guide.html>`__ for +details on supported clock recipes in F2, dynamic clock reconfiguration +and specifying clock recipes during the build time. + +Similar to F1, the ``clk_main_a0`` in F2 also supports multiple clock +recipes and the frequency can be scaled using SW APIs at the time of AFI +loads (this feature is currently not available and will be added in a future +release). + +Reset +^^^^^ + +The shell provides an active-low reset signal synchronous to +clk_main_a0: rst_main_n. This is an active low reset signal, and +combines the board reset and PCIe link-level reset conditions. + +PCIS Interface +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This an 512-bit wide AXI-4 interface for Inbound PCIe Transactions (Shell is +Requester, CL is Completer). It is used for: + +- PCIe transactions initiated by the instance and targeting AppPF BAR4 + (PCIS) +- DMA transactions (if enabled) (XDMA) + +A read or write request on this AXI-4 bus that is not acknowledged by +the CL within a certain time window, will be internally terminated by +the Shell. If the time-out error happens on a read, the Shell will +return ``0xFFFFFFFF`` data back to the instance. This error is reported +through the Management PF and can be retrieved by the AFI Management +Tools metric reporting APIs. + +The AXI ID can be used to determine the source of the transaction: + +- 0x20 : PCI Interface +- 0x00 : XDMA Channel 0 +- 0x01 : XDMA Channel 1 +- 0x02 : XDMA Channel 2 +- 0x03 : XDMA Channel 3 + +PCIS Interface Timeout Details +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The PCIS interface multiplexes the XDMA requests and PCIS requests. Each +type of request has a different timeout time: + +- XDMA (DMA transactions) : 5 seconds +- PCIS (PCIe transactions initiated from the instance) : 8 us + +Transactions on the PCIS interface must complete before the associated +timeout time or the SH will timeout the transactions and complete the +transactions on behalf of the CL (BVALID/RVALID). Each "issued" +transaction has an independent timeout counter. For example if 4 +transactions are issued from the PCIS interface "simultaneously" (i.e. +back-to-back cycles), then all 4 must complete within 8us. A transaction +is considered "issued" when the AxVALID is asserted for the transaction +by the Timeout Detection block. AxREADY does not have to be asserted for +the transaction to be considered "issued". Note there is a 16 deep clock +crossing FIFO between the Timeout Detection block and the CL logic. So +if the CL is asserting backpressure (de-asserting AxVALID) there can +still be 16 transactions issued by the Timeout Detection block. The SH +supports a maximum of 32 transactions outstanding for each type +(read/write). It is advisable for the CL to implement enough buffering +for 32 transactions per type so that it is aware of all issued +transactions. + +Once a transaction is issued, it must fully be completed within the +timeout time (Address, Data, Ready). Any transaction that does not +completed in time will be terminated by the shell. This means write data +will be accepted and thrown away, and default data ``0xFFFFFFFF`` will be +returned for reads. + +If a timeout occurs, the Shell will timeout all further transactions in +16ns for a moderation time (4ms). + +**WARNING**: If a timeout happens, the DMA/PCIS interface may no longer +be functional and the AFI/Shell must be re-loaded. This can be done by +adding the "-F" option to ``fpga-load-local-image``. + +PCIM Interface +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This is an 512-bit wide AXI-4 interface for Outbound PCIe Transactions (CL is +Requester, Shell is Completer). It is used by the CL to initiate cycles to the PCIe bus, for example, to push +data from the CL to instance memory, or read from the instance memory. + +⚠️ **The CL must use physical addresses, and developers must be careful +not to use userspace/virtual addresses.** + +The following PCIe interface configuration parameters are provided from +the Shell to the CL as informational: + +- sh_cl_cfg_max_payload[1:0] – PCIe maximum payload size: + +.. list-table:: + :header-rows: 1 + :class: user-guide-dev-envs-table + :widths: 20 40 + + * - Value + - Max Payload Size + * - 0b00 + - 128 Bytes + * - 0b01 + - 256 Bytes (Most probable value) + * - 0b10 + - 512 Bytes + * - 0b11 + - Reserved + +- sh_cl_cfg_max_read_req[2:0] - PCIe maximum read request size: + +.. list-table:: + :header-rows: 1 + :class: user-guide-dev-envs-table + :widths: 20 40 + + * - Value + - Max Read Request Size + * - 0b000 + - 128 Bytes + * - 0b001 + - 256 Bytes + * - 0b010 + - 512 Bytes (Most probable value) + * - 0b011 + - 1024 Bytes + * - 0b100 + - 2048 Bytes + * - 0b101 + - 4096 Bytes + * - Others + - Reserved + +Outbound PCIe AXI-4 Interface Restrictions +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- Transfers must not violate PCIe byte enable rules (see byte enable + rules below). +- Transfers must adhere to all AXI-4 protocol rules + +Byte Enable Rules +~~~~~~~~~~~~~~~~~ + +All AXI-4 transactions to the PCIe interface must adhere to the PCIe +Byte Enable rules (see PCI Express Base specification). Rules are +summarized below: + +- All transactions larger than two DW must have contiguous byte enables. +- Transactions that are less than two DW may have non-contiguous byte + enables. + +Note on AXI-4 byte enables are signaled using WSTRB. + +AXI4 Error Handling for CL outbound Transactions +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Transactions on AXI4 interface will be terminated and reported as SLVERR +on the RRESP/BRESP signals and will not be passed to the instance in the +following cases: + +- PCIe BusMaster Enable (BME) is not set in the PCIe configuration + space. +- Illegal transaction address; i.e. addressing memory space that isn't + supported by the instance. +- Transaction crossing 4KB boundaries violating AXI-4/PCIe + specifications. +- Illegal byte-enable. +- Illegal length (AXI-4 write doesn't match length). +- Illegal AXI-Size (only full width 512-bit transfers, size=0b110 are + supported) +- Timeout. Each channel must complete in 8 us or it will timeout: 1. + Once AW is asserted, the write data must be supplied in 8us 2. Once + RVALID is asserted, RREADY must be asserted, and all data transferred + within 8us 3. Once BVALID is asserted, BREADY must be asserted within + 8us + +⚠️ **If a timeout occurs, the PCIM bus will no longer be functional. +This can be cleared by clearing/re-loading the AFI.** + +OCL/SDA AXI-Lite Interfaces for Register Access +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +There are two AXI-L requester interfaces (Shell is Requester) that can +be used for register access interfaces. Each interface is sourced from a +different PCIe PF/BAR. Breaking this into multiple interfaces allows for +different software entities to have a control interface into the CL: + +- OCL AXI-L: Associated with AppPF, BAR0. If the developer is using AWS + OpenCL runtime lib (as in SDAccel case), this interface will be used + for OpenCL Kernel access + +- SDA AXI-L: Associated with MgmtPF, BAR4. If the developer is using AWS + OpenCL runtime Lib (as in SDAccel case), this interface will be used + for performance monitors etc. This interface is also used for accessing the + `AWS_CLK_GEN IP <./AWS_CLK_GEN_spec.html>`__ for CL clock management. + +Please refer to `PCI Address Map <./AWS_Fpga_Pcie_Memory_Map.html>`__ for +a more detailed view of the address map. + +CL AXI Completer Error Reporting +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Each AXI (AXI-4/AXI-L) transaction is terminated with a response +(BRESP/RRESP). The AXI responses may signal an error such as Completer +Error, or Decode Error. PCIe also has error reporting for non-posted +requests (Unsupported Requests/Completer Abort). The shell does not +propagate the AXI-4 error responses to the PCIe bus. All PCIe cycles are +terminated with non-error responses. The AXI-4 errors are reported +through the Management PF and can be retrieved by the AFI Management +Tools metric reporting APIs. + +Accessing Aligned/Unaligned Addresses from PCIe +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The Shell (Requester) supports DW aligned and unaligned transfers from PCIe (address +is aligned/unaligned to DW-4byte boundary) + +Following are a few examples of how aligned and unaligned access from +PCIe to CL on PCIS interface work: + +1. Writing 8 bytes to DW aligned address through PCIe on AXI4 + Interface (PCIS 512-bit interface): + + If the transaction on the PCIe is as follows: + - Addr : 0x0000002000000000 + - dw_cnt : 2 + - first_be : 4’b1111 + - last_be : 4’b1111 + + Then the transaction on the AXI4 interface will have the following + AXI attributes: + - awaddr = 64’h0000_0000_0000_0000 + - awlen = 0 + - wstrb = 64’h0000_0000_0000_00ff + +2. Writing 8 bytes to DW unaligned address on AXI4 Interface(PCIS + 512-bit interface): + + If the transaction on the PCIe is as follows: + - Addr : 0x0000002000000001 + - dw_cnt : 3 + - first_be : 4’b1110 + - last_be : 4’b0001 + + Then the transaction on the AXI4 interface will have the following + AXI attributes: + - awaddr = 64’h0000_0000_0000_0001 + - awlen = 0 + - wstrb = 64’h0000_0000_0000_01fe + +The addresses for the Read transactions will work similar to writes. + +**Note**: If a transaction from PCIe is initiated on AXI-Lite (SDA/OCL) +interfaces with dw_cnt greater than 1, i.e. >32bits, the transaction is +split into multiple 32-bit transactions by the Shell. + +Following are a few examples of how aligned and Unaligned access from +PCIe to CL on SDA/OCL AXI-Lite interfaces work: + +1. Writing 8 bytes to DW aligned address on AXI Lite interface + (SDA/OCL 32-bit interface): + + If the transaction on the PCIe is as follows: + - Addr : 0x0000000002000000 + - dw_cnt : 2 + - first_be : 4’b1111 + - last_be : 4’b1111 + + Then the transaction on the AXI-Lite interface will be split and will + have the following AXI attributes: Transaction is split into 2 + transfers. + + 1st transfer + - awaddr = 32’h0000_0000 + - wstrb = 4’hf + 2nd transfer + - awaddr = 32’h0000_0004 + - wstrb = 4’hf + +2. Writing 64 bits to DW unaligned address on AXI Lite interface + (SDA/OCL 32-bit interface): + + If the transaction on the PCIe is as follows: + - Addr : 0x0000000002000001 + - dw_cnt : 3 + - first_be : 4’b1110 + - last_be : 4’b0001 + + Transaction on AXI-Lite interface will be split and will have the + following AXI attributes: Transaction is split into 3 transfers. + + 1st transfer + - awaddr = 32’h0000_0001 + - wstrb = 4’he + + 2nd transfer + - awaddr = 32’h0000_0004 + - wstrb = 4’hf + + 3rd transfer + - awaddr = 32’h0000_0008 + - wstrb = 4’h1 + +The transaction splitting and addresses for the Read transactions will +work similar to writes. + +Interrupts +~~~~~~~~~~ + +16 user interrupt sources are supported. There is mapping logic that +maps the user interrupts to MSI-X vectors. Mapping registers in the DMA +controller map the 16 user interrupt sources to MSI-X vectors. + +There are two sets of signals to generate interrupts: + +- cl_sh_apppf_irq_req[15:0] (from CL to SH) +- sh_cl_apppf_irq_ack[15:0] (from SH to CL) + +This interface uses single clock pulses for the req/ack. The CL asserts +(active high) cl_sh_apppf_irq_req[x] for a single clock to assert the +interrupt request to the SH. The SH will respond with a single clock +pulse on sh_cl_apppf_irq_ack[x] to acknowledge the interrupt. Once the +CL asserts a request on a particular bit[x], it should not assert a +request for the same bit[x] until it has received the ack for bit[x] +from the SH. The CL may assert requests on other bits[y] (y!=x). + +HBM Monitor Interface +~~~~~~~~~~~~~~~~~~~~~ + +There are two sets of HBM monitor APB interfaces exposed to the CL, one +for each HBM rack. These interfaces are used by the shell to ensure the +HBM's integrity and reliability whenever the HBM IP is enabled in the +CL. + +When the interfaces are connected to the HBM IP properly, the shell +monitors the HBM controller traffic and forces an HBM rack reset if any +transaction is detected accessing an address space in the IP that's not +defined in the `AMD HBM User +Guide `__. + +The active-low ``hbm_apb_preset`` signal connected to each HBM rack +remains at logic-high during power-on and normal operation. This allows +the HBM to initialize and communicate with the rest of the CL logic. If +an HBM access violation (i.e., an APB transaction to an undefined +address space) occurs, the shell will pull the ``hbm_apb_preset`` signal +low to force a reset of the HBM rack. Subsequent usage of this rack is +blocked. The customer must reload the AFI to get it recovered from this +blocked state. + +These steps must be followed to properly connect the monitor interfaces +to HBM: + +1. Expose the HBM monitor I/Os on the HBM IP by running the following + Tcl commands in the Vivado IP management project: + + .. code:: Tcl + + # Enable the `MON_APB` interface on the IP + set_property CONFIG.USER_MON_APB_EN TRUE [get_ips ] + + # Confirm the enabling state + get_property CONFIG.USER_MON_APB_EN [get_ips ] + true + + **NOTE:** This step can be skipped if the customer uses the + ``CL_HBM`` IP from the `CL examples <./../../hdk/common/ip/cl_ip/>`__. + This IP has the ``MON_APB`` interface enabled and is ready to be + integrated to a customer design as-is. + +2. Connect the HBM monitor interface from the shell to the HBM IP. The + customer can leave the interface floating if the corresponding HBM + rack is not used. For example, the ``hbm_apb_p_1`` signals can be + left unconnected if HBM rack 1 is unused. + +3. All the HBM monitor interfaces are synchronized to the 100MHz + ``clk_hbm_ref`` clock. + +4. The ``hbm_apb_preset_n_<1/0>`` signals, treated as asynchronous + resets by the HBM IP, must be directly connected to the IP's + ``MON_APB_<1/0>_PRESET_N`` inputs. Other APB interfaces can be + pipelined using APB register slices for timing closure purposes. + +⚠️ **Failing to connect these HBM monitor interfaces between the shell +and the HBM IP will result in an AFI creation error.** + +Miscellaneous Signals +~~~~~~~~~~~~~~~~~~~~~ + +There are some miscellaneous generic signals between the Shell and CL. + +Integrity Check +^^^^^^^^^^^^^^^ + +The 64-bit ch_sh_id0/id1 are used by AWS to validate the signature of +the DCP while being loaded into an FPGA in AWS. + +Initial versions of the HDK and Shell used the 4-tuple: PCIe VendorID, +DeviceID, SubsystemVendorID and SubsystemID (which are used during AFI +registration via ``aws ec2 create-fpga-image`` API) as the Integrity +check mechanism, following the next mapping + +- cl_sh_id0 + + - [15:0] – Vendor ID + - [31:16] – Device ID + +- cl_sh_id1 + + - [15:0] – Subsystem Vendor ID + - [31:16] – Subsystem ID + +In future revisions of the HDK, AWS scripts may override the +cl_sh_id0/id1 to include an integrity hash function. + +General Control/Status +^^^^^^^^^^^^^^^^^^^^^^ + +The functionality of these signals is TBD. + +- cl_sh_status0[31:0] – Placeholder for generic CL to Shell status. +- cl_sh_status1[31:0] – Placeholder for generic CL to Shell status. +- sh_cl_ctl0[31:0] – Placeholder for generic Shell to CL control + information. +- sh_cl_ctl1[31:0] – Placeholder for generic Shell to CL control + information. +- sh_cl_pwr_state[1:0] – This is the power state of the FPGA. + + - 0x0 – Power is normal + - 0x1 – Power level 1 + - 0x2 – Power level 2 + - 0x3 – Power is critical and FPGA may be shutting off clocks or + powering down + +Virtual LED/DIP +^^^^^^^^^^^^^^^ + +There are virtual LED/DIP switches that can be used to control/monitor +CL logic. There are 16 LEDs and 16 DIP Switches. Registers exposed to +the Management PF are used to control/monitor the LED/DIP Switches. + +vLED - There are 16 virtual LEDs that can be driven from the CL logic to +the SH (cl_sh_status_vled[15:0]). The value of these signals can be read +by S/W in the Instance. An API is also provided through AWS Management +Software. + +vDIP - There are 16 virtual DIP switches that drive from the SH to the +CL logic (sh_cl_status_vdip[15:0]). These can be used to control logic +in the CL. The value of these signals can be written/read by S/W in the +instance. An API is also provided through AWS Management Software. + +These signals are asynchronous to the CL clocks, and the following must +be done when using these signals: + +- vLED: In implementation a false path should be set from the vLED + signals. For example, in the constraints for place and route add: + + .. code:: bash + + set_false_path -from [get_cells CL/cl_sh_status_vled_reg*] + + +- vDIP: The vDIP signals should be synchronized to a CL clock before + being used. + + .. code:: verilog + + always @(posedge clk_main_a0) + begin + pre_sync_vdip <= sh_cl_status_vdip; + sync_vdip <= pre_sync_vdip; + end + + my_logic = sync_vdip[0]; + +Global Counters +^^^^^^^^^^^^^^^ + +There are two global counter outputs that increment every 4ns. These can +be used to measure time inside of the CL. They are synchronized to +clk_main_a0. Note if clk_main_a0 is running slower than 250MHz, the +counters will appear to skip values. The counters are: + +- sh_cl_glcount0[63:0] +- sh_cl_glcount1[63:0] + +Implementation Tips +------------------- + +Here are some implementation tips. + +Multi-SLR FPGA +~~~~~~~~~~~~~~ + +The VU47P FPGA is a stacked FPGA that has 3-die stacked together. Each +Die is called a “Super Logic Region” (SLR). Crossing an SLR boundary is +expensive from a timing perspective. It is good practice to pipeline +interfaces between major blocks to allow the tool freedom to have SLR +crossings between the major blocks. Even with pipelined interfaces it is +possible the tool has sub-optimal logic to SLR mapping (i.e. a major +block is spread out over multiple SLR's). In this case you may want to +at map major blocks to specific SLRs (define the logic that should be +constrained to each SLR). Any crossing of SLR’s should have flops on +either side (or register slices for AXI). + +It is ideal to place logic that interfaces to the shell in the same SLR +as the Shell logic for that interface. If this is not possible, the +first flop/register slice should be placed in the same SLR: + +- TOP SLR: + + - CL_SH_DDR + - DDR Stats + - PCIS + +- MID SLR: + + - PCIM + - OCL + - SDA + +- MID/BOTTOM + + - HBM MON APB + +Please see the `Shell Floorplan <./shell_floorplan.html>`__ for additional +details on Shell-CL interface placements in SMALL_SHELL. + +For the interfaces that are in both the MID/BOTTOM the recommendation is +to use flops for pipelining, but don’t constrain to an SLR. You can +constrain logic to a particular SLR by creating PBLOCKs (one per SLR), +and assigning logic to the PBLOCKs (refer to cl_dram_hbm_dma example +`small_shell_cl_pnr_user.xdc <../cl/examples/cl_dram_hbm_dma/build/constraints/small_shell_cl_pnr_user.xdc>`__). +Dataflow should be mapped so that SLR crossing is minimized (for example +a pipeline should be organized such that successive stages are mostly in +the same SLR). + +There are some good timing closure tips in this +`UltraFast Design Methodology Guide `__ + +Logic Levels +~~~~~~~~~~~~ + +You can report all paths that are greater than a certain number of logic +levels. This can be used to iterate on timing in synthesis rather than +waiting for place and route. For example at 250MHz a general rule of +thumb is try to keep logic levels to around 10. The following commands +report on all paths that have more than 10 logic levels: + + .. code:: Tcl + + report_design_analysis -logic_level_distribution -of [get_timing_paths -max_paths 10000 -filter {LOGIC_LEVELS > **10**}] + + foreach gtp [get_timing_paths -max_paths 5000 ?nworst 100 -filter {LOGIC_LEVELS > **10**}] { + puts "[get_property STARTPOINT_PIN $gtp] + [get_property ENDPOINT_PIN $gtp] [get_property SLACK $gtp] + [get_propert LOGIC_LEVELS $gtp]" + } + +.. _reset-1: + +Reset +~~~~~ + +Reset fanout can be minimized in an FPGA. This helps with routing +congestion. Flops can be initialized in their declaration and generally +do not require resets: + +.. code:: Verilog + + logic[3:0] my_flops = 4'ha; + + If logic must have a reset, use synchronous resets rather than + asynchronous resets: + +.. code:: Verilog + + always @(posedge clk) + if (reset) + my_flop <= 4'ha; + else + my_flop <= nxt_my_flop; + +If there is still significant fanout of reset, it should be replicated +and pipelined. For example each major block could have its own pipelined +version of reset. + +Pipeline Registers +~~~~~~~~~~~~~~~~~~ + +You have to be careful that pipeline registers do not infer a shift +register component. The shift register is placed in a single area and +does not accomplish any distance pipelining. Here is a snippet to force +the tools to not infer a shift register (shreg_extract="no" directive): + +.. code:: Verilog + + (*shreg_extract="no"*) logic [WIDTH-1:0] pipe[STAGES-1:0] = '{default:'0}; + +Vivado Analysis +~~~~~~~~~~~~~~~ + +Vivado has some nice analysis capabilities: + +- report_methodology (includes CDC report) +- clock interaction report (see if paths between async clocks are erroneously being timed) +- congestion heat map +- power analysis +- physical implementation analysis (placement, routing) +- linked timing/schematic/physical views + +Refer to `Vivado Design Suite User Guide `__ +for more information. + +.. |F2_Shell_interface| image:: ./../../_static/F2_Shell_interface.png diff --git a/docs-rtd/source/hdk/docs/Clock_Recipes_User_Guide.rst b/docs-rtd/source/hdk/docs/Clock_Recipes_User_Guide.rst new file mode 100644 index 000000000..c490e7035 --- /dev/null +++ b/docs-rtd/source/hdk/docs/Clock_Recipes_User_Guide.rst @@ -0,0 +1,326 @@ +F2 Clock Recipes User Guide +=========================== + +Table of Content +---------------- + +- `F2 Clock Recipes User Guide <#f2-clock-recipes-user-guide>`__ + + - `Table of Content <#table-of-content>`__ + - `Introduction <#introduction>`__ + - `F2 Clock Recipe Tables <#f2-clock-recipe-tables>`__ + - `How to Specify Clock Recipe During Build + Time <#how-to-specify-clock-recipe-during-build-time>`__ + - `How to Dynamically Configure Clocks during + Runtime <#how-to-dynamically-configure-clocks-during-runtime>`__ + - `Clock Consideration When Porting CL Designs from F1 into + F2 <#clock-consideration-when-porting-cl-designs-from-f1-into-f2>`__ + - `References <#references>`__ + +Introduction +------------ + +F2 Shell offers two clocks - ``clk_main_a0`` and ``clk_hbm_ref`` to the +CL. This is different from F1 Shell, which offers total of 8 clocks from +Shell to the CL as described in `F1 Shell Interface +Spec `__. +Offering fewer clocks from the Shell to CL is beneficial because it does +not lock up the routing resources for customers who do not require all +the clocks from the Shell. + +The ``clk_main_a0`` defaults to 250MHz. Dynamic reconfiguration of the +frequency for ``clk_main_a0`` is currently NOT supported. However, this +will be supported in future. + +The ``clk_hbm_ref`` is a fixed frequency 100MHz clock required for the +HBM IP to clock the APB interface. + +F2 Developer Kit provides a clocking IP +`AWS_CLK_GEN <./AWS_CLK_GEN_spec.md>`__ for customers who desire to have +same clocks and clock recipe support as F1. +`Tables <./Clock_Recipes_User_Guide.md#f2-clock-recipe-table>`__ +below shows the clock recipes supported in F2. + +F2 Clock Recipe Tables +--------------------- + +.. list-table:: + :header-rows: 2 + :class: user-guide-dev-envs-table + :widths: 10 10 10 10 10 50 + + * - Clock Group A + - + - + - + - + - + * - Recipe Number + - clk_main_a0 + - clk_extra_a1 + - clk_extra_a2 + - clk_extra_a3 + - Notes + * - A0 + - 250 + - 62.5 + - 187.5 + - 250 + - AWS_CLK_GEN is not required in the CL design for clk_main_a0 recipes. + clk_extra_a0/a1/a2 clocks require AWS_CLK_GEN block instantiated in + CL design. + * - A1 + - 250 + - 125 + - 375 + - 500 + - + * - A2 + - 250 + - 15.625 + - 125 + - 62.5 + - + +.. list-table:: + :header-rows: 2 + :class: user-guide-dev-envs-table + :widths: 10 10 10 10 10 50 + + * - Clock Group B + - + - + - + - + - + * - Recipe Number + - clk_extra_b0 + - clk_extra_b1 + - + - + - Notes + * - B0 + - 250 + - 125 + - + - + - clk_extra_b0/b1 require AWS _CLK_GEN block instantiated in the CL design. + * - B1 + - 125 + - 62.5 + - + - + - + * - B2 + - 450 + - 225 + - + - + - + * - B3 + - 250 + - 62.5 + - + - + - + * - B4 + - 300 + - 75 + - + - + - + * - B5 + - 400 + - 100 + - + - + - + +.. list-table:: + :header-rows: 2 + :class: user-guide-dev-envs-table + :widths: 10 10 10 10 10 50 + + * - Clock Group C + - + - + - + - + - + * - Recipe Number + - clk_extra_c0 + - clk_extra_c1 + - + - + - Notes + * - C0 + - 300 + - 400 + - + - + - + * - C1 + - 150 + - 200 + - + - + - + * - C2 + - 75 + - 100 + - + - + - + * - C3 + - 200 + - 266.667 + - + - + - + +.. list-table:: + :header-rows: 2 + :class: user-guide-dev-envs-table + :widths: 10 10 10 10 10 50 + + * - Clock Group HBM + - + - + - + - + - + * - Recipe Number + - clk_hbm_axi + - + - + - + - Notes + * - H0 + - 300 + - 400 + - + - + - clk _hbm_axi requires AWS_CLK_GEN IP instantiated in the CL design. + The clk _hbm_axi is used to clock the AXI interfaces of HBM IP. + This clock is not available in F1. + * - H1 + - 125 + - + - + - + - + * - H2 + - 450 + - + - + - + - + * - H3 + - 300 + - + - + - + - + * - H4 + - 400 + - + - + - + - + +.. list-table:: + :header-rows: 2 + :class: user-guide-dev-envs-table + :widths: 10 10 10 10 10 50 + + * - Reference Clock Group + - + - + - + - + - + * - Recipe Number + - clk_hbm_ref + - + - + - + - Notes + * - + - 100 + - + - + - + - Fixed frequency 100MHz reference clock from the Shell for HBM IP. + +**NOTE:** ``clk_main_a0`` supports A0, A1 and A2 clock recipes without +requiring AWS_CLK_GEN IP instantiated in the CL design. All other clocks +and their respective clock recipes require AWS_CLK_GEN IP instantiated +in the CL design and interfaced to the SDA interface from the Shell. +`CL_MEM_PERF <./../cl/examples/cl_mem_perf/design/cl_mem_perf.sv>`__ +demonstrates how `AWS_CLK_GEN <./../common/lib/aws_clk_gen.sv>`__ is +integrated into CL design. + +How to Specify Clock Recipe During Build Time +--------------------------------------------- + +Developers who wish to build CL design for a specific clock frequency +defined in the `F2 Clock Recipe +Tables <./Clock_Recipes_User_Guide.html#f2-clock-recipe-tables>`__ can do so +by passing the following arguments at the time of CL builds. Specifying +clock recipe at the time of build, automatically adjusts the design +clock constraints enabling the Vivado tool to close timing of CL based +on chosen clock frequency. + +For example, command below shows CL_MEM_PERF built using user specified +clock recipes: + +.. code:: bash + + cd $CL_DIR/build/scripts/ + ./aws_build_dcp_from_cl.py --cl=cl_mem_perf --clock_recipe_a=A0 --clock_recipe_b=B3 --clock_recipe_c=C3 --clock_recipe_hbm=H4 + +When the clock recipe options are not explicitly specified, +``aws_build_dcp_from_cl.py`` defaults to +``--clock_recipe_a=A1 --clock_recipe_b=B2 --clock_recipe_c=C0 --clock_recipe_hbm=H2`` + +**NOTE:** If AWS_CLK_GEN IP is not instantiated in the CL design, the +recipes for AWS_CLK_GEN clocks will be ignored. Users may see CRITICAL +WARNING related to missing AWS_CLK_GEN instantiation during builds. + +How to Dynamically Configure Clocks during Runtime +-------------------------------------------------- + +Support for SW API to do clock frequency dynamic configuration is +available using the ``fpga-load-clkgen-dynamic`` and +``fpga-load-clkgen-recipe`` command line interfaces detailed in `Amazon +FPGA Image (AFI) Management +Tools <../../sdk/userspace/fpga_mgmt_tools/README.html>`__. + +Clock Consideration When Porting CL Designs from F1 into F2 +----------------------------------------------------------- + +1. The ``clk_main_a0`` is now fixed at 250MHz. It does not support clock + recipes or dynamic frequency reconfiguration. However, they will be + supported in future. + +2. F1 designs that relied on additional clocks such as ``clk_extra_*`` + will now have two options in F2: + + a. Customers can instantiate required number of MMCMs in their CL + design to meet the clocking requirement. + + b. Alternately, customers can instantiate + `AWS_CLK_GEN <./../common/lib/aws_clk_gen.sv>`__ IP in their CL which + offers same set of clocks from F1, in addition to ``clk_hbm_axi`` for + HBM clocking. AWS provides `SW + APIs <./../../sdk/userspace/fpga_libs/fpga_clkgen/fpga_clkgen_utils.c>`__ + to simplify clock configuration for the user application. + +3. F2 supports same clock recipe build switches as F1 to simplify + porting of F1 designs into F2. + +References +---------- + +`F1 Dynamic Clock +Configuration `__ diff --git a/docs-rtd/source/hdk/docs/RTL_Simulation_Guide_for_HDK_Design_Flow.rst b/docs-rtd/source/hdk/docs/RTL_Simulation_Guide_for_HDK_Design_Flow.rst new file mode 100644 index 000000000..f59a0baba --- /dev/null +++ b/docs-rtd/source/hdk/docs/RTL_Simulation_Guide_for_HDK_Design_Flow.rst @@ -0,0 +1,1418 @@ +RTL Simulation Guide for HDK Design Flow +======================================== + +Table of Contents +----------------- + +- `Introduction <#introduction>`__ +- `Quick Start <#quick-start>`__ + + - `Use F2 Developer AMI <#use-f2-developer-ami>`__ + - `Install the HDK and Setup + Environment <#install-the-hdk-and-setup-environment>`__ + - `Try Out One of HDK Examples or Write Your + Own <#try-out-one-of-hdk-examples-or-write-your-own>`__ + - `Xilinx's Library + Compilation <#xilinxs-library-compilation-complib_dir>`__ + +- `Create Your Own Tests for RTL + Simulation <#create-your-own-tests-for-rtl-simulation>`__ + + - `SystemVerilog Tests <#systemverilog-tests>`__ + +- `Accessing Host Memory During + Simulation <#accessing-host-memory-during-simulation>`__ +- `Debugging Custom Logic using the AWS + HDK <#debugging-custom-logic-using-the-aws-hdk>`__ + + - `Protocol Checkers <#protocol-checkers>`__ + - `Re-Run Simulation to Dump + Waves <#re-run-simulation-to-dump-waves>`__ + - `View Waves in Vivado Using Tcl <#view-waves-in-vivado-using-tcl>`__ + +- `SV Test API Reference <#sv-test-api-reference>`__ +- `C Test API Reference <#c-test-api-reference>`__ + +Introduction +------------ + +The HDK development environment comes with a shell simulation model that +supports RTL-level simulation using Vivado XSIM, Synopsys VCS or Siemens +Questa RTL simulators. Developers can leverage this simulation model and +create test cases in SystemVerilog to verify CL design's +functionalities. + +|alt tag| + +Quick Start +----------- + +Use F2 Developer AMI +~~~~~~~~~~~~~~~~~~~~ + +One easy way is to use the F2 Developer AMI that will be shared +privately with the customers. This developer AMI comes with +pre-installed Vivado tools and license. + +Please refer to the `release notes <../../RELEASE_NOTES.md>`__ or the +`supported Vivado version <../../supported_vivado_versions.txt>`__ for +the exact version of Vivado tools, and the required license components. + +Install the HDK and Setup Environment +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +AWS FPGA HDK can be cloned and installed on your EC2 instance or server +by calling: + +.. code:: bash + + git clone https://github.com/aws/aws-fpga.git + cd aws-fpga + source hdk_setup.sh + +Try Out One of HDK Examples or Write Your Own +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. code:: bash + + # $CL_DIR must be set before running simulations + export CL_DIR=$PWD/hdk/cl/examples/cl_sde + + # Simulations are launched from the scripts subdir of the design + cd ${CL_DIR}/verif/scripts + + # Run the default test using the VCS SIM + export TEST_NAME=test_ddr + make ${TEST_NAME} VCS=1 + + # To view the test log files (this is defined by SIM_DIR makefile variable) + cd ${CL_DIR}/verif/sim/vcs/${TEST_NAME}_sv + # Compile log + vi compile.vcs.log + # Simulation run log file + vi ${TEST_NAME}.log + +The call of the ``make ${TEST_NAME}`` as above executes following steps. + ++-------+-------------+----------------------------------------------+ +| Order | Flow | Description | ++=======+=============+==============================================+ +| 1st | ``ip-gen`` | Generate Xilinx IPs. Executed only once when | +| | | the IPs are initially generated. \ **NOTE:** | +| | | An IP must be regenerated if the IP's XCI | +| | | file gets updated | ++-------+-------------+----------------------------------------------+ +| 2nd | ``complib`` | Compile Xilinx libraries. Executed only once | +| | | when the libraries are initially compiled | ++-------+-------------+----------------------------------------------+ +| 3rd | ``compile`` | compile RTL source and testbench | ++-------+-------------+----------------------------------------------+ +| 4th | ``pre-run`` | Pre-simulation. Generate simulation input | +| | | files etc | ++-------+-------------+----------------------------------------------+ +| 5th | ``run`` | Run the simulation | ++-------+-------------+----------------------------------------------+ + +Xilinx's Library Compilation (``COMPLIB_DIR``) +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +When using simulator other than Vivado SIM, the Xilinx's library will be +compiled under the ``COMPLIB_DIR``. The default ``COMPLIB_DIR`` path is +identified as below. + +.. code:: bash + + COMPLIB_DIR = $CL_DIR/verif/sim//_complib + +Compiling the Xilinx's library is very time consuming and can take up to +2 hours to complete. User can skip this step if they already have a +pre-compiled Xilinx library that was compiled using the current Vivado +version. + +Please do as below steps to setup to use the pre-compiled Xilinx library +instead of getting it to be compiled for each clean clone of aws-fpga +into a new directory. + +- Set the COMPLIB_DIR environment variable pointing to the pre-compiled + Xilinx library. + +.. code:: bash + + export COMPLIB_DIR=/path/to/user/complib/dir + +- Create a ``.done`` file under the ``COMPLIB_DIR`` to tell the Makefile + system to not recompile + +.. code:: bash + + touch $COMPLIB_DIR/.done + +Create Your Own Tests for RTL Simulation +---------------------------------------- + +SystemVerilog Tests +~~~~~~~~~~~~~~~~~~~ + +One fast way to write your own test is to start with an example test +from one of the examples designs and customize it for your design. All +SV tests must be placed in the verif/tests sub-directory of CL design +root and use the ".sv" file extension. + +.. code:: bash + + cl_my_design # Custom Logic (CL) design root directory + |-- build + |-- design + |-- software + | `--runtime # C source files and header files for simulation + +-- verif + |-- scripts # Makefiles and file lists + |-- sim # sim results directory + |-- sv # additional CL-specific test bench source + +-- tests # test directory + +**NOTE:** All the tests are written to run on 64-bit instances/servers +with 64-bit Linux OS. Many of the tests and reference Custom Logic (CL) +examples use 64-bit address formats + +.. code:: verilog + + module test_peek_poke(); + + `define WR_INSTR_INDEX 64'h1c + `define WR_ADDR_LOW 64'h20 + `define WR_ADDR_HIGH 64'h24 + `define WR_DATA 64'h28 + `define WR_SIZE 64'h2c + + `define RD_INSTR_INDEX 64'h3c + `define RD_ADDR_LOW 64'h40 + `define RD_ADDR_HIGH 64'h44 + `define RD_DATA 64'h48 + `define RD_SIZE 64'h4c + + `define CNTL_REG 64'h08 + + `define WR_START_BIT 32'h00000001 + `define RD_START_BIT 32'h00000002 + + logic [63:0] pcim_address = 64'h0000_0000_1234_0000; + + initial begin + + tb.power_up(); + + tb.poke_ocl(`WR_INSTR_INDEX, 0); // write index + tb.poke_ocl(`WR_ADDR_LOW, pcim_address[31:0]); // write address low + tb.poke_ocl(`WR_ADDR_HIGH, pcim_address[63:32]); // write address high + tb.poke_ocl(`WR_DATA, 32'h0000_0000); // write data + tb.poke_ocl(`WR_SIZE, 32'h0000_0002); // write 32b + + tb.poke_ocl(`RD_INSTR_INDEX, 0); // read index + tb.poke_ocl(`RD_ADDR_LOW, pcim_address[31:0]); // read address low + tb.poke_ocl(`RD_ADDR_HIGH, pcim_address[63:32]); // read address high + tb.poke_ocl(`RD_DATA, 32'h0000_0000); // read data + tb.poke_ocl(`RD_SIZE, 32'h0000_0002); // read 32b + + tb.poke_ocl(`CNTL_REG, 32'h0003); // start read & write + + #500ns; // give the hardware time to run + + ... + + tb.power_down(); + + $finish; + end + + endmodule // test_peek_poke + +Once your test is written, you are ready to run a simulation. The +``/scripts`` directory is where you must launch all simulations. + +.. code:: bash + + cd ${CL_DIR}/verif/scripts + # Compile and run using XSIM by default (NOTE: Do Not include .sv) + make TEST='' + # To view the test log files, `cd` here + cd ${CL_DIR}/verif/sim// + +If your have Cadence and Synopsys VCS RTL simulator or Modelsim Questa, +then add ``VCS=1`` or ``QUESTA=1``. + +.. code:: bash + + make TEST='' VCS=1 + +All of the default tests include Makefile targets under +``$CL_DIR/verif/scripts/Makefile.tests``. Some tests require additional +environment variables to be set to configure the design. HBM specific +tests require ``VCS=1`` or ``QUESTA=1`` as well as ``COMPILE_HBM`` to be +defined. + +Use only the SV test APIs supplied with the developer's kit to stimulate +your CL design. They were designed specifically to mimic the behavior of +the actual AWS Shell logic. If you choose to control CL signaling via +another method, proper operation with Shell logic is not guaranteed. + +The AWS Shell Interface specification can be found +`here <./AWS_Shell_Interface_Specification.md>`__ + +Accessing Host Memory During Simulation +--------------------------------------- + +Your design may share data between host memory and logic within the CL. +To verify your CL is accessing host memory, the test bench includes a +host memory implemented using an associative array. The address is the +key to locate a 32-bit data value. + +.. code:: verilog + + logic [31:0] sv_host_memory[*]; + +If you are are using C to verify your CL, then use C domain host memory. +Allocate a memory buffer in your C code and pass the pointer to the SV +domain. The AXI BFM connected to the PCIM port will use DPI calls to +read and write the memory buffer. + +Backdoor access to host memory is provided by two functions: + +.. code:: c + + function void hm_put_byte(input longint unsigned addr, byte d); + function byte hm_get_byte(input longint unsigned addr); + +Use these functions when you need to access data in the host memory. +They take zero simulation time and are useful for initializing memory or +checking results stored in memory. + +Debugging Custom Logic using the AWS HDK +---------------------------------------- + +If a simulation fails, developers can debug issues by dumping waves of +the simulation and then view them to determine the source of the +problem. + +The process for dumping and viewing waves can differ depending on the +simulator being used. To dump and view waves using the Xilinx Vivado +tools included with the AWS HDK: + +- Specify scope of logic for wave dump +- Re-run simulation to dump waves +- View waves in Vivado using Tcl + +VCS .vpd files can be found under +``$CL_DIR/verif/sim/vcs/_sv/.vpd`` and viewed with DVE. + +Protocol Checkers +~~~~~~~~~~~~~~~~~ + +Xilinx Protocol Checkers are instantiated on all AXI4 and AXIL +interfaces in Shell BFM. By default, all the tests run with protocol +checkers enabled. If there is a protocol error in any one of the AXI +interfaces, then the protocol checker will fire an error as below. + +.. code:: verilog + + tb.card.fpga.sh.axl_pc_sda_slv_inst.REP : BIT( 35) : ERROR : Invalid state x + tb.card.fpga.sh.axi_pc_mstr_inst_pcim.REP : BIT( 33) : ERROR : Invalid state x + tb.card.fpga.sh.axi_pc_mstr_inst_pcis.REP : BIT( 35) : ERROR : Invalid state x + tb.card.fpga.sh.axl_pc_ocl_slv_inst.REP : BIT( 35) : ERROR : Invalid state x + +Please refer to the `protocol +checker <./../common/verif/models/xilinx_axi_pc/axi_protocol_checker_v1_1_vl_rfs.v>`__ +for mapping between bit positions and the protocol errors. + +Re-Run Simulation to Dump Waves +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Once ``waves.tcl`` has been modified, re-run the simulation with +``make`` as shown at the top of this document. + +View Waves in Vivado Using Tcl +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +As mentioned above, all simulation results will be placed in +``sim/vivado/``. If using the included CL examples, the waves +database should appear as ``tb.wdb``. + +To view the waves, first create a Tcl file called ``open_waves.tcl`` +with the following commands: + +.. code:: tcl + + current_fileset + open_wave_database tb.wdb + +Then open Vivado and specify this Tcl file to execute: + +.. code:: bash + + vivado -source open_waves.tcl + +The design hierarchy and waves should then be visible and can be +inspected and debugged + +The usage of Vivado for wave debug is beyond the scope of this document. +See the `Vivado Design Suite +Tutorials `__ +for more details. + +SV Test API Reference +--------------------- + +*set_virtual_dip_switch* +~~~~~~~~~~~~~~~~~~~~~~~~ + +Description +^^^^^^^^^^^ + +Writes virtual dip switches. + +Declaration +^^^^^^^^^^^ + +task set_virtual_dip_switch(input int slot_id=0, int dip); +'''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +======== ======================== +Argument Description +======== ======================== +slot_id Slot ID +dip 16bit dip switch setting +======== ======================== + +*get_virtual_dip_switch* +~~~~~~~~~~~~~~~~~~~~~~~~ + +.. _description-1: + +Description +^^^^^^^^^^^ + +Reads virtual dip switches. + +.. _declaration-1: + +Declaration +^^^^^^^^^^^ + +function logic [15:0] get_virtual_dip_switch(input int slot_id=0); +'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +======== =========== +Argument Description +======== =========== +slot_id Slot ID +======== =========== + +*get_virtual_led* +~~~~~~~~~~~~~~~~~ + +.. _description-2: + +Description +^^^^^^^^^^^ + +Reads virtual LEDs. + +.. _declaration-2: + +Declaration +^^^^^^^^^^^ + +function logic [15:0] get_virtual_led(input int slot_id=0); +''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +======== =========== +Argument Description +======== =========== +slot_id Slot ID +======== =========== + +*kernel_reset* +~~~~~~~~~~~~~~ + +.. _description-3: + +Description +^^^^^^^^^^^ + +Issues a kernel reset. + +.. _declaration-3: + +Declaration +^^^^^^^^^^^ + +.. _function-void-kernel_resetinput-int-slot_id0-logic-d--1: + +function void kernel_reset(input int slot_id=0, logic d = 1); +''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +======== =========== +Argument Description +======== =========== +slot_id Slot ID +d reset value +======== =========== + +*poke* +~~~~~~ + +.. _description-4: + +Description +^^^^^^^^^^^ + +The SV Test API task 'poke' writes 512 bits of data to the CL via the +AXI PCIeS interface. + +.. _declaration-4: + +Declaration +^^^^^^^^^^^ + +.. _task-pokeinput-int-slot_id--0-logic-630-addr-logic-5110-data-logic-50-id--6h0-datasizedata_size-size--datasizeuint32-axiportaxi_port-intf--axiportport_dma_pcis: + +task poke(input int slot_id = 0, logic [63:0] addr, logic [511:0] data, logic [5:0] id = 6'h0, DataSize::DATA_SIZE size = DataSize::UINT32, AxiPort::AXI_PORT intf = AxiPort::PORT_DMA_PCIS); +''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +======== ============= +Argument Description +======== ============= +slot_id Slot ID +addr Write Address +data Write Data +id AXI ID +size Data Size +intf AXI CL Port +======== ============= + +*poke_pcis* +~~~~~~~~~~~ + +.. _description-5: + +Description +^^^^^^^^^^^ + +The SV Test API task 'poke_pcis' writes 512 bits of data to the CL via +the AXI PCIE interface. + +.. _declaration-5: + +Declaration +^^^^^^^^^^^ + +.. _task-poke_pcisinput-int-slot_id--0-logic-630-addr-logic-5110-data-logic-630-strb-logic-50-id--6h0: + +task poke_pcis(input int slot_id = 0, logic [63:0] addr, logic [511:0] data, logic [63:0] strb, logic [5:0] id = 6'h0); +''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +======== ============= +Argument Description +======== ============= +slot_id Slot ID +addr Write Address +data Write Data +strb Write Strobe +id AXI ID +======== ============= + +*poke_pcis_wc* +~~~~~~~~~~~~~~ + +.. _description-6: + +Description +^^^^^^^^^^^ + +The SV Test API task 'poke' writes 64 bits of data to the CL via the AXI +PCIeS interface. + +.. _declaration-6: + +Declaration +^^^^^^^^^^^ + +.. _task-poke_pcis_wcinput-int-slot_id--0-input-logic-630-addr-logic-310-data--logic-50-id--6h0-logic-20-size--3d6: + +task poke_pcis_wc(input int slot_id = 0, input logic [63:0] addr, logic [31:0] data [$], logic [5:0] id = 6'h0, logic [2:0] size = 3'd6); +''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +======== ======================= +Argument Description +======== ======================= +slot_id Slot ID +addr Write Address +data [$] DW array for Write Data +id AXI ID +size Data Size +======== ======================= + +*peek* +~~~~~~ + +.. _description-7: + +Description +^^^^^^^^^^^ + +The SV Test API task 'peek' reads up to 512 bits of data from the CL via +the AXI PCIeS interface. + +.. _declaration-7: + +Declaration +^^^^^^^^^^^ + +.. _task-peekinput-int-slot_id--0-input-logic-630-addr-output-logic-5110-data-input-logic-50-id--6h0-datasizedata_size-size--datasizeuint32-axiportaxi_port-intf--axiportport_dma_pcis: + +task peek(input int slot_id = 0, input logic [63:0] addr, output logic [511:0] data, input logic [5:0] id = 6'h0, DataSize::DATA_SIZE size = DataSize::UINT32, AxiPort::AXI_PORT intf = AxiPort::PORT_DMA_PCIS); +'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +======== ============ +Argument Description +======== ============ +slot_id Slot ID +addr Read Address +data Read Data +id AXI ID +size Data Size +intf AXI CL Port +======== ============ + +*peek_pcis* +~~~~~~~~~~~ + +.. _description-8: + +Description +^^^^^^^^^^^ + +The SV Test API function 'task peek_pcis' reads 512 bits of data from +the CL via the AXI PCIS interface. + +.. _declaration-8: + +Declaration +^^^^^^^^^^^ + +.. _task-peek_pcisinput-int-slot_id--0-logic-630-addr-output-logic-5110-data-input-logic-50-id--6h0: + +task peek_pcis(input int slot_id = 0, logic [63:0] addr, output logic [511:0] data, input logic [5:0] id = 6'h0); +''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +======== ============ +Argument Description +======== ============ +slot_id Slot ID +addr Read Address +data Read Data +id AXI ID +======== ============ + +*issue_flr* +~~~~~~~~~~~ + +.. _description-9: + +Description +^^^^^^^^^^^ + +Issues a PCIe Function Level Reset (FLR). + +.. _declaration-9: + +Declaration +^^^^^^^^^^^ + +task issue_flr(input int slot_id=0); +'''''''''''''''''''''''''''''''''''' + +======== =========== +Argument Description +======== =========== +slot_id Slot ID +======== =========== + +*nsec_delay* +~~~~~~~~~~~~ + +.. _description-10: + +Description +^^^^^^^^^^^ + +Wait dly nanoseconds. + +.. _declaration-10: + +Declaration +^^^^^^^^^^^ + +.. _task-nsec_delayinput-int-dly--10000: + +task nsec_delay(input int dly = 10000); +''''''''''''''''''''''''''''''''''''''' + +======== ==================== +Argument Description +======== ==================== +dly delay in nanoseconds +======== ==================== + +*poke_ocl* +~~~~~~~~~~ + +.. _description-11: + +Description +^^^^^^^^^^^ + +The SV Test API task 'poke_ocl' writes 32 bits of data to the CL via the +AXI OCL interface. + +.. _declaration-11: + +Declaration +^^^^^^^^^^^ + +.. _task-poke_oclinput-int-slot_id--0-logic-630-addr-logic-310-data-logic-50-id--6h0: + +task poke_ocl(input int slot_id = 0, logic [63:0] addr, logic [31:0] data, logic [5:0] id = 6'h0); +'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +======== ============= +Argument Description +======== ============= +slot_id Slot ID +addr Write Address +data Write Data +id AXI ID +======== ============= + +*peek_ocl* +~~~~~~~~~~ + +.. _description-12: + +Description +^^^^^^^^^^^ + +The SV Test API function 'task peek_ocl' reads 64 bits of data from the +CL via the AXI OCL interface. + +.. _declaration-12: + +Declaration +^^^^^^^^^^^ + +.. _task-peek_oclinput-int-slot_id--0-logic-630-addr-output-logic-630-data-input-logic-50-id--6h0: + +task peek_ocl(input int slot_id = 0, logic [63:0] addr, output logic [63:0] data, input logic [5:0] id = 6'h0); +''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +======== ============ +Argument Description +======== ============ +slot_id Slot ID +addr Read Address +data Read Data +id AXI ID +======== ============ + +*poke_sda* +~~~~~~~~~~ + +.. _description-13: + +Description +^^^^^^^^^^^ + +The SV Test API task 'poke_sda' writes 32 bits of data to the CL via the +AXI OCL interface. + +.. _declaration-13: + +Declaration +^^^^^^^^^^^ + +.. _task-poke_sdainput-int-slot_id--0-logic-630-addr-logic-310-data-logic-50-id--6h0: + +task poke_sda(input int slot_id = 0, logic [63:0] addr, logic [31:0] data, logic [5:0] id = 6'h0); +'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +======== ============= +Argument Description +======== ============= +slot_id Slot ID +addr Write Address +data Write Data +id AXI ID +======== ============= + +*peek_sda* +~~~~~~~~~~ + +.. _description-14: + +Description +^^^^^^^^^^^ + +The SV Test API function 'task peek_sda' reads 64 bits of data from the +CL via the AXI SDA interface. + +.. _declaration-14: + +Declaration +^^^^^^^^^^^ + +.. _task-peek_sdainput-int-slot_id--0-logic-630-addr-output-logic-630-data-input-logic-50-id--6h0: + +task peek_sda(input int slot_id = 0, logic [63:0] addr, output logic [63:0] data, input logic [5:0] id = 6'h0); +''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +======== ============ +Argument Description +======== ============ +slot_id Slot ID +addr Read Address +data Read Data +id AXI ID +======== ============ + +*is_dma_to_cl_done* +~~~~~~~~~~~~~~~~~~~ + +.. _description-15: + +Description +^^^^^^^^^^^ + +Returns non-zero if the DMA to the CL is complete. + +.. _declaration-15: + +Declaration +^^^^^^^^^^^ + +.. _function-bit-is_dma_to_cl_doneinput-int-slot_id--0-input-int-chan: + +function bit is_dma_to_cl_done(input int slot_id = 0, input int chan); +'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +======== ======================== +Argument Description +======== ======================== +slot_id Slot ID +chan DMA channel to use (0-3) +======== ======================== + +*is_dma_to_buffer_done* +~~~~~~~~~~~~~~~~~~~~~~~ + +.. _description-16: + +Description +^^^^^^^^^^^ + +Returns non-zero if the DMA to the buffer is complete. + +.. _declaration-16: + +Declaration +^^^^^^^^^^^ + +.. _function-bit-is_dma_to_buffer_doneinput-int-slot_id--0-input-int-chan: + +function bit is_dma_to_buffer_done(input int slot_id = 0, input int chan); +'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +======== ======================== +Argument Description +======== ======================== +slot_id Slot ID +chan DMA channel to use (0-3) +======== ======================== + +*set_chk_clk_freq* +~~~~~~~~~~~~~~~~~~ + +.. _description-17: + +Description +^^^^^^^^^^^ + +The SV test API function 'function void set_chk_clk_freq(input int +slot_id = 0, logic chk_freq = 1'b1);' is used to enable frequency checks +in shell model. + +.. _declaration-17: + +Declaration +^^^^^^^^^^^ + +.. _function-void-set_chk_clk_freqinput-int-slot_id--0-logic-chk_freq--1b1: + +function void set_chk_clk_freq(input int slot_id = 0, logic chk_freq = 1'b1); +''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +======== =========== +Argument Description +======== =========== +slot_id Slot ID +chk_freq enable bit +======== =========== + +*chk_prot_err_stat* +~~~~~~~~~~~~~~~~~~~ + +.. _description-18: + +Description +^^^^^^^^^^^ + +The SV test API function 'function logic chk_prot_err_stat(input int +slot_id = 0);' is used to check protocol error status. + +.. _declaration-18: + +Declaration +^^^^^^^^^^^ + +.. _function-logic-chk_clk_err_cntinput-int-slot_id--0: + +function logic chk_clk_err_cnt(input int slot_id = 0); +'''''''''''''''''''''''''''''''''''''''''''''''''''''' + +======== =========== +Argument Description +======== =========== +slot_id Slot ID +======== =========== + +*que_buffer_to_cl* +~~~~~~~~~~~~~~~~~~ + +.. _description-19: + +Description +^^^^^^^^^^^ + +Queues a buffer for the DMA to send data to the CL. + +.. _declaration-19: + +Declaration +^^^^^^^^^^^ + +.. _function-void-que_buffer_to_clinput-int-slot_id--0-int-chan-logic-630-src_addr-logic-630-cl_addr-logic-270-len: + +function void que_buffer_to_cl(input int slot_id = 0, int chan, logic [63:0] src_addr, logic [63:0] cl_addr, logic [27:0] len); +''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +======== ======================== +Argument Description +======== ======================== +slot_id Slot ID +chan DMA channel to use (0-3) +src_addr Data's Source Address +cl_addr Custom Logic Address +len Length of DMA in bytes +======== ======================== + +*que_cl_to_buffer* +~~~~~~~~~~~~~~~~~~ + +.. _description-20: + +Description +^^^^^^^^^^^ + +Queues a buffer for the DMA to receive data from the CL. + +.. _declaration-20: + +Declaration +^^^^^^^^^^^ + +.. _function-void-que_cl_to_bufferinput-int-slot_id--0-int-chan-logic-630-dst_addr-logic-630-cl_addr-logic-270-len: + +function void que_cl_to_buffer(input int slot_id = 0, int chan, logic [63:0] dst_addr, logic [63:0] cl_addr, logic [27:0] len); +''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +======== ========================== +Argument Description +======== ========================== +slot_id Slot ID +chan DMA channel to use (0-3) +dst_addr Data's Destination Address +cl_addr Custom Logic Address +len Length of DMA in bytes +======== ========================== + +*start_que_to_cl* +~~~~~~~~~~~~~~~~~ + +.. _description-21: + +Description +^^^^^^^^^^^ + +Starts the DMA operation to the CL. + +.. _declaration-21: + +Declaration +^^^^^^^^^^^ + +.. _function-void-start_que_to_clinput-int-slot_id--0-int-chan: + +function void start_que_to_cl(input int slot_id = 0, int chan); +''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +======== ======================== +Argument Description +======== ======================== +slot_id Slot ID +chan DMA channel to use (0-3) +======== ======================== + +*start_que_to_buffer* +~~~~~~~~~~~~~~~~~~~~~ + +.. _description-22: + +Description +^^^^^^^^^^^ + +Starts the DMA operation from the CL. + +.. _declaration-22: + +Declaration +^^^^^^^^^^^ + +.. _function-void-start_que_to_bufferinput-int-slot_id--0-int-chan: + +function void start_que_to_buffer(input int slot_id = 0, int chan); +''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +======== ======================== +Argument Description +======== ======================== +slot_id Slot ID +chan DMA channel to use (0-3) +======== ======================== + +*map_host_memory* +~~~~~~~~~~~~~~~~~ + +.. _description-23: + +Description +^^^^^^^^^^^ + +The SV Test API function 'task map_host_memory(input logic [63:0] addr)' +maps host memory to 64-bit address. + +.. _declaration-23: + +Declaration +^^^^^^^^^^^ + +task map_host_memory(input logic [63:0] addr); +'''''''''''''''''''''''''''''''''''''''''''''' + +======== =========== +Argument Description +======== =========== +addr Address +======== =========== + +*hm_put_byte* +~~~~~~~~~~~~~ + +.. _description-24: + +Description +^^^^^^^^^^^ + +The SV Test API function 'function void hm_put_byte(input longint +unsigned addr, byte d)' is used to backdoor load host memory. + +.. _declaration-24: + +Declaration +^^^^^^^^^^^ + +function void hm_put_byte(input longint unsigned addr, byte d); +''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +======== =========== +Argument Description +======== =========== +addr Address +d data +======== =========== + +*hm_get_byte* +~~~~~~~~~~~~~ + +.. _description-25: + +Description +^^^^^^^^^^^ + +The SV Test API function 'function void hm_get_byte(input longint +unsigned addr)' is used to read data from host memory using backdoor. + +.. _declaration-25: + +Declaration +^^^^^^^^^^^ + +function void hm_get_byte(input longint unsigned addr); +''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +======== =========== +Argument Description +======== =========== +addr Address +======== =========== + +C Test API Reference +-------------------- + +*cl_poke* +~~~~~~~~~ + +.. _description-26: + +Description +^^^^^^^^^^^ + +The C Test API function 'extern void cl_poke(uint64_t addr, uint32_t +data)' writes 32 bits of data to the CL via the AXI PCIeS interface. +This function calls the SV poke function via DPI calls. + +.. _declaration-26: + +Declaration +^^^^^^^^^^^ + +extern void cl_poke(uint64_t addr, uint32_t data); +'''''''''''''''''''''''''''''''''''''''''''''''''' + +======== ============= +Argument Description +======== ============= +addr Write Address +data Write Data +======== ============= + +*cl_peek* +~~~~~~~~~ + +.. _description-27: + +Description +^^^^^^^^^^^ + +The C Test API function 'extern void cl_peek(uint64_t addr)' Reads 32 +bits of data from the CL via the AXI PCIeS interface. This function +calls the SV peek function via DPI calls. + +.. _declaration-27: + +Declaration +^^^^^^^^^^^ + +extern void cl_peek(uint64_t addr, uint32_t data); +'''''''''''''''''''''''''''''''''''''''''''''''''' + +======== ============ +Argument Description +======== ============ +addr Read Address +data Read Data +======== ============ + +*sv_map_host_memory* +~~~~~~~~~~~~~~~~~~~~ + +.. _description-28: + +Description +^^^^^^^^^^^ + +The C Test API function 'extern void sv_map_host_memory(uint8_t +\*memory)' maps host memory to memory allocated by memory buffer. This +function calls the SV map_host_memory function via DPI calls. + +.. _declaration-28: + +Declaration +^^^^^^^^^^^ + +extern void sv_map_host_memory(uint8_t \*memory); +''''''''''''''''''''''''''''''''''''''''''''''''' + +======== ======================== +Argument Description +======== ======================== +\*memory pointer to memory buffer +======== ======================== + +*host_memory_putc* +~~~~~~~~~~~~~~~~~~ + +.. _description-29: + +Description +^^^^^^^^^^^ + +The C Test API function 'void host_memory_putc(uint64_t addr, uint8_t +data)' is used to backdoor load host memory. + +.. _declaration-29: + +Declaration +^^^^^^^^^^^ + +void host_memory_putc(uint64_t addr, uint8_t data) +'''''''''''''''''''''''''''''''''''''''''''''''''' + +======== =========== +Argument Description +======== =========== +addr Address +data data +======== =========== + +*host_memory_getc* +~~~~~~~~~~~~~~~~~~ + +.. _description-30: + +Description +^^^^^^^^^^^ + +The C Test API function 'void host_memory_getc(uint64_t addr)' is used +to backdoor load host memory. + +.. _declaration-30: + +Declaration +^^^^^^^^^^^ + +.. _void-host_memory_putcuint64_t-addr-uint8_t-data-1: + +void host_memory_putc(uint64_t addr, uint8_t data) +'''''''''''''''''''''''''''''''''''''''''''''''''' + +======== =========== +Argument Description +======== =========== +addr Address +======== =========== + +*log_printf* +~~~~~~~~~~~~ + +.. _description-31: + +Description +^^^^^^^^^^^ + +The C Test API function 'void log_printf(const char \*format, ...)' is +used to print messages when running a simulation. The regular 'C' printf +will not work when running a 'C' and 'SV' mixed language simulation. +This 'C' function calls SV function sv_printf via DPI calls. + +.. _declaration-31: + +Declaration +^^^^^^^^^^^ + +.. _void-log_printfconst-char-format-: + +void log_printf(const char \*format, ...); +'''''''''''''''''''''''''''''''''''''''''' + +======== ===================== +Argument Description +======== ===================== +\*format message to be printed +======== ===================== + +*sv_printf* +~~~~~~~~~~~ + +.. _description-32: + +Description +^^^^^^^^^^^ + +The C Test API function 'extern void sv_printf(char \*msg)' is used to +send a message buffer to the SV side of simulation. + +.. _declaration-32: + +Declaration +~~~~~~~~~~~ + +extern void sv_printf(char \*msg); +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +======== ================ +Argument Description +======== ================ +\*msg Character buffer +======== ================ + +*sv_pause* +~~~~~~~~~~ + +.. _description-33: + +Description +^^^^^^^^^^^ + +The C test API function 'extern void sv_pause(uint32_t x);' is used to +add delay to a simulation. + +.. _declaration-33: + +Declaration +^^^^^^^^^^^ + +extern void sv_pause(uint32_t x); +''''''''''''''''''''''''''''''''' + +======== ====================== +Argument Description +======== ====================== +x Delay in micro seconds +======== ====================== + +*sv_fpga_start_buffer_to_cl* +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. _description-34: + +Description +^^^^^^^^^^^ + +The C test API function 'extern "DPI-C" task +sv_fpga_start_buffer_to_cl;' is used to do DMA data transfer from Host +to CL. + +.. _declaration-34: + +Declaration +^^^^^^^^^^^ + +extern void sv_fpga_start_buffer_to_cl(uint32_t slot_id, uint32_t chan, uint32_t buf_size, const char \*wr_buffer, uint64_t cl_addr); +''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +========= ====================== +Argument Description +========= ====================== +slot_id Slot ID +chan DMA channel +buf_size Size of the buffer +wr_buffer Data to be transferred +cl_addr Destination CL address +========= ====================== + +*sv_fpga_start_cl_to_buffer* +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. _description-35: + +Description +^^^^^^^^^^^ + +The C test API function 'extern "DPI-C" task +sv_fpga_start_cl_to_buffer;' is used to do DMA data transfer from Host +to CL. + +.. _declaration-35: + +Declaration +^^^^^^^^^^^ + +extern void sv_fpga_start_cl_to_buffer(uint32_t slot_id, uint32_t chan, uint32_t buf_size, uint64_t cl_addr); +''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +========= ====================== +Argument Description +========= ====================== +slot_id Slot ID +chan DMA channel +buf_size Size of the buffer +wr_buffer Data to be transferred +cl_addr Destination CL address +========= ====================== + +*get_global_counter_0* +~~~~~~~~~~~~~~~~~~~~~~ + +.. _description-36: + +Description +^^^^^^^^^^^ + +The SV test API function 'function logic [63:0] +get_global_counter_0(input int slot_id = 0);' is used to get global +counter_0 value. + +.. _declaration-36: + +Declaration +^^^^^^^^^^^ + +.. _function-logic-630-get_global_counter_0input-int-slot_id--0: + +function logic [63:0] get_global_counter_0(input int slot_id = 0); +'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +======== =========== +Argument Description +======== =========== +slot_id Slot ID +======== =========== + +*get_global_counter_1* +~~~~~~~~~~~~~~~~~~~~~~ + +.. _description-37: + +Description +^^^^^^^^^^^ + +The SV test API function 'function logic [63:0] +get_global_counter_1(input int slot_id = 0);' is used to get global +counter_1 value. + +.. _declaration-37: + +Declaration +^^^^^^^^^^^ + +.. _function-logic-630-get_global_counter_1input-int-slot_id--0: + +function logic [63:0] get_global_counter_1(input int slot_id = 0); +'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +======== =========== +Argument Description +======== =========== +slot_id Slot ID +======== =========== + +.. |alt tag| image:: ./images/cl-sim-testbench.png diff --git a/docs-rtd/source/hdk/docs/Supported_DDR_Modes.rst b/docs-rtd/source/hdk/docs/Supported_DDR_Modes.rst new file mode 100644 index 000000000..04142cadc --- /dev/null +++ b/docs-rtd/source/hdk/docs/Supported_DDR_Modes.rst @@ -0,0 +1,109 @@ +.. _supported-ddr-configurations-in-sh_ddrsv: + +Supported DDR configurations in `sh_ddr.sv <./../common/shell_stable/design/sh_ddr/sh_ddr.stub.sv>`__ +===================================================================================================== + +Table of Contents +----------------- + +- `Supported DDR configurations in + sh_ddr.sv <#supported-ddr-configurations-in-sh_ddrsv>`__ + + - `Table of Contents <#table-of-contents>`__ + - `Overview <#overview>`__ + - `Required RTL Modifications <#required-rtl-modifications>`__ + - `Required Verification + Modifications <#required-verification-modifications>`__ + - `Required Build Script + Modifications <#required-build-script-modifications>`__ + +Overview +-------- + +The +`sh_ddr.sv <./../common/shell_stable/design/sh_ddr/sh_ddr.stub.sv>`__ +now supports following configurations for DDR Controller IPs: + +- DDR Core for 64 GB DIMM. +- DDR Core for 64 GB DIMM with user-controlled Auto-Precharge mode. This + feature allows user designs to issue DDR Auto-Precharge command by + asserting ``cl_sh_ddr_axi_awuser=1`` or ``cl_sh_ddr_axi_aruser=1`` + alongside their corresponding valid control signals. Please refer to + `PG150-User + Guide `__ + for details on user-controlled (app_auto-precharge) Auto-Precharge + mode. +- If DDR core is not required in the CL design, then users still have to + instantiate ``sh_ddr.sv`` in top level CL, with parameter tied off to + ``.DDR_PRESENT(0)``. Failing to do so may result in errors during + synthesis/implementation. + +Required RTL Modifications +-------------------------- + +`sh_ddr.sv <./../common/shell_stable/design/sh_ddr/sh_ddr.stub.sv>`__ +defaults to using 64 GB DDR core along with 64 GB DIMM model, and +without user-controlled Auto-Precharge mode. Users are allowed to define +one of the following macros in the top level of CL where ``sh_ddr.sv`` +is instantiated. This will automatically pick up the desired DDR +controller inside ``sh_ddr.sv``. Supported macros are shown below: + +- :literal:`\`define USE_64GB_DDR_DIMM` : This is 64GB DDR controller +- :literal:`\`define USE_AP_64GB_DDR_DIMM` : This is 64GB DDR controller + with user-controlled Auto Precharge + +For example, please refer to +`cl_mem_perf <./../cl/examples/cl_mem_perf/design/cl_mem_perf.sv>`__ +which has :literal:`\`define USE_AP_64GB_DDR_DIMM` macro to override +sh_ddr.sv to use 64GB DDR core with user controlled Auto-Precharge mode. + +Required Verification Modifications +----------------------------------- + +Users must pass the **same** macro as they defined in top level CL to +simulate with a corresponding DIMM model. + +.. code:: bash + + export TEST_NAME=test_ddr + + # To Run simulations with a 64 GB DDR DIMM + make TEST=${TEST_NAME} USE_64GB_DDR_DIMM=1 + + # To Run simulations with a 64 GB DDR DIMM and DDR core with user controlled auto-precharge mode + make TEST=${TEST_NAME} USE_AP_64GB_DDR_DIMM=1 + +⚠️ The macros passed during sims must match with what is defined in the +top level CL RTL file. Otherwise, users may risk running sims on +unintended DIMM models, yielding inconsistent results. + +Required Build Script Modifications +----------------------------------- + +AWS provides following DDR Core IPs as part of Vivado +`cl_ip.xpr <./../common/ip/cl_ip/cl_ip.xpr>`__ project. Users are +required to enlist one of the following XCI files in the synthesis +scripts, depending on the desired DDR configuration and macros defined: + ++----------------------+----------------------+----------------------+ +| Macro definition in | Description | DDR XCI file to read | +| top level CL | | in synthesis script | ++======================+======================+======================+ +| \`define | 64 GB DDR core | ``cl_ddr4.xci`` | +| USE_64GB_DDR_DIMM | without | | +| | user-controlled | | +| | Auto-Precharge mode. | | ++----------------------+----------------------+----------------------+ +| \`define | 64 GB DDR core with | `` | +| USE_AP_64GB_DDR_DIMM | user-controlled | cl_ddr4_64g_ap.xci`` | +| | Auto-Precharge mode. | | ++----------------------+----------------------+----------------------+ + +Alternately, users may choose to enlist all four DDR XCI files in their +synthesis script. The Vivado tool automatically elaborates the correct +DDR core based on the macro defined in top level CL file. For example, +`CL_MEM_PERF synthesis +script <./../cl/examples/cl_mem_perf/build/scripts/synth_cl_mem_perf.tcl>`__ +reads in all four XCI files but elaborates the desired DDR core at the +time of synthesis based on macro defined in +`cl_mem_perf.sv <./../cl/examples/cl_mem_perf/design/cl_mem_perf.sv>`__ diff --git a/docs-rtd/source/hdk/docs/Virtual_JTAG_XVC.rst b/docs-rtd/source/hdk/docs/Virtual_JTAG_XVC.rst new file mode 100644 index 000000000..cc5ebe1e0 --- /dev/null +++ b/docs-rtd/source/hdk/docs/Virtual_JTAG_XVC.rst @@ -0,0 +1,298 @@ +Virtual JTAG for Real-time FPGA Debug +===================================== + +Table of Contents +----------------- + +- `Virtual JTAG for Real-time FPGA + Debug <#virtual-jtag-for-real-time-fpga-debug>`__ + + - `Table of Contents <#table-of-contents>`__ + - `Overview <#overview>`__ + - `Install XVC Driver on F2 + Instances <#install-xvc-driver-on-f2-instances>`__ + - `Start Local Debug Server on F2 + Instances <#start-local-debug-server-on-f2-instances>`__ + - `Connect to target FPGA via Virtual + JTAG <#connect-to-target-fpga-via-virtual-jtag>`__ + - `Start Remote Debug Server on F2 Instances (Coming + Soon) <#start-remote-debug-server-on-f2-instances-coming-soon>`__ + - `Embedded Debug Bridge in CL <#embedded-debug-bridge-in-cl>`__ + - `Frequently Asked Questions <#frequently-asked-questions>`__ + +Overview +-------- + +Amazon EC2 F2 instances offer debugging capabilities through Virtual +JTAG. This feature leverages the Xilinx Virtual Cable (XVC) protocol to +emulate JTAG cable connectivity to a target FPGA over the PCIe +interface. Developers can connect to Xilinx debug cores, such as the +`Integrated Logic Analyzer +(ILA) `__ +and `Virtual Input/Output +(VIO) `__ +in Custom Logic (CL) designs within Vivado, to monitor, control, and +debug their designs. + +The Virtual JTAG solution consists of three main elements: + +- [A] Debug cores and a debug bridge that must be implemented and + connected properly in the CL design. + Refer to the `cl_dram_hbm_dma <../cl/examples/cl_dram_hbm_dma/README.html>`__ + example design for details. +- [B] A Virtual JTAG service acting as an XVC server that runs on the + target F2 instance. +- [C] A local or remote Vivado application for interactive debugging. + +Install XVC Driver on F2 Instances +---------------------------------- + +To begin debugging a CL design, the developer must first install the XVC +driver (skip this step if the driver is pre-installed). This section +provides a guide for installing the XVC driver on F2 instances using the +AWS FPGA developer AMI. For detailed compilation and installation +information, refer to the `AMD prodct +guide `__. + +1. Locate and unzip the XVC driver file from the Vivado tool installation + directory: + + ⚠️ Remember to update tool installation directory with the one if you own AMI. + The example below is for demonstration only. + + .. code:: bash + + unzip /opt/Xilinx/Vivado/2024.1/data/xicom/drivers/pcie/xvc_pcie.zip + cd driver_v0.4 + +2. To correctly bind the XVC driver to the FPGA, update the ``PCIE_VENDOR_ID`` + and ``PCIE_DEVICE_ID`` in ``xvc_pcie_user_config.h`` file: + + .. code:: bash + + vim xvc_pcie_user_config.h + + ... + #define PCIE_VENDOR_ID 0x1D0F // Update to use PF1 for Virtual JTAG + #define PCIE_DEVICE_ID 0x9248 // Update to use PF1 for Virtual JTAG + + ... + { + .name = "", + .config_space = AUTO, + .config_info = { + .config_vsec_id = 0x0008, + .config_vsec_rev = 0x0, + }, + .bar_info = { + .bar_index = 0x2, // Update to bind to BAR2 + .bar_offset = 0x0000, // Update to bind to offset 0 + }, + }, + + ⚠️ Developers may encounter a compilation error in some operating systems due + to driver incompatibility, like this: + + .. code:: bash + + /home/ubuntu/driver_v0.4/xvc_pcie_driver_base.c:306:25: error: too many arguments to function ‘class_create’ + 306 | xvc_dev_class = class_create(THIS_MODULE, "xil_xvc_class"); + +3. To resolve the error, update the ``xvc_pcie_driver_base.c`` file as follows: + + .. code:: C + + 305 // Register the character device class for the actual files + 306 xvc_dev_class = class_create("xil_xvc_class"); // Remove THIS_MODULE here + 307 if (IS_ERR(xvc_dev_class)) { + 308 xil_xvc_cleanup(); + 308 xil_xvc_cleanup(); + 309 return PTR_ERR(xvc_dev_class); + 310 } + +4. Next, compile and install the XVC driver: + + .. code:: bash + + sudo su + cd driver_v0.4 + make install + depmod -a + modprobe xilinx_xvc_pci_driver + lsmod | grep xilinx + ... + xilinx_xvc_pci_driver 20480 0 ---> This means XVC driver is successfully installed + +Start Local Debug Server on F2 Instances +---------------------------------------- + +To start the XVC server on a instance, run the ``xvc_pcie`` executable in Vivado +installation directory. The application should spit out the host server name and +port number. These information will later be used to create a virtual JTAG cable +in Vivado Hardware Manager. + +.. code:: bash + + sudo su + cd /opt/Xilinx/Vivado/2024.1/bin/ + ./xvc_pcie + + Description: + Xilinx xvc_pcie v2024.1 + Build date : May 22 2024-19:19:01 + Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. + + INFO: XVC PCIe Driver character file - /dev/xil_xvc/cfg_ioc0 + INFO: XVC PCIe Driver configured to communicate with Debug Bridge IP in AXI mode (PCIe BAR space). + INFO: PCIe BAR index=0x0002 and PCIe BAR offset=0x0000 + INFO: XVC PCIE Driver Loopback test successful. + + INFO: xvc_pcie application started + INFO: Use Ctrl-C to exit xvc_pcie application + + INFO: To connect to this xvc_pcie instance use url: tcp:ip-172-31-8-59:10200 ---> This shows the host server name and the port nummber + +Connect to target FPGA via Virtual JTAG +--------------------------------------- + +With a XVC server up and running, a Virtual JTAG cable connection to the +target FPGA is ready to be built in Vivado. + +1. Prior to executing Vivado, verify that the ``.LTX`` probe file from the CL + design DCP tarball is saved on the instance. + + .. code:: bash + + $ tar -tvf 2024_08_21-122520.Developer_CL.tar + + drwxr-sr-x 0 2024-08-21 13:15 to_aws/ + -rw-r--r-- 91676787 2024-08-21 13:15 to_aws/2024_08_21-122520.SH_CL_routed.dcp + -rw-r--r-- 655601 2024-08-21 13:15 to_aws/2024_08_21-122520.debug_probes.ltx ---> This is the probe file + -rw-r--r-- 398 2024-08-21 13:54 to_aws/2024_08_21-122520.manifest.txt + +2. Open Vivado GUI and select "Open Hardware Manager" + +|vjtag_1| + +3. Click "Open target" and select the "Open New Target...". + +|vjtag_2| + +4. For hardware server setting, connect to "Local server" and click + "Next" + +|vjtag_3| + +5. Click "Add Xilinx Virtual Cable (XVC)" and put in "Host name" and "Port" + collected previously from the XVC server. Click "OK" to proceed. + +|vjtag_4| + +6. The debug bridge in the target design should be detected and listed in + "Hardware Targets". Click "Next" and "Finish" to finish setting up the + Virtual JTAG connection. + +|vjtag_5| + +7. All the debug cores embedded in the CL design should be now listed under + ``debug_bridge_0``. Highlight ``debug_bridge_0`` and add the CL design + ``.LTX`` probe file to "Probes file" in the "Hardware Device Properties" + window. After the probe file gets loaded, the waveform and configuration + windows will be available for each debug core in Vivado. The CL design at + this point is ready to be debugged. + +|vjtag_6| + +Start Remote Debug Server on F2 Instances (Coming Soon) +------------------------------------------------------- + +Guide for debugging designs through Vivado running on a remote machine +is coming soon. + +Embedded Debug Bridge in CL +--------------------------- + +The `CL_Debug_Bridge +<./../common/ip/cl_ip/cl_ip.srcs/sources_1/ip/cl_debug_bridge/cl_debug_bridge.xci>`__ +IP must be embedded in the CL design to enable the use of debug cores like ILA +and VIO. According to the `AMD user guide +`__ +, the clock of ``CL_Debug_Bridge`` must be at least 2.5 times faster than the +JTAG clock. The JTAG clock frequency is fixed at 31.25 MHz in the F2 shells. +Therefore, the frequency of the clock connected to the ``CL_Debug_Bridge`` +should be at least 2.5 x 31.25 MHz = 78.125 MHz. Failure to meet this +requirement will result in the debug network not functioning correctly. +However, this minimum clock frequency requirement does not apply to the ILA or +VIO debug cores or the rest of the CL logic. If the CL design is running on a +slower clock from the available clock recipes, care must be taken to ensure +that the ``CL_Debug_Bridge`` is clocked at 78.125 MHz or above. + +.. code:: verilog + + //----------------------------------- + // Debug bridge + //----------------------------------- + cl_debug_bridge CL_DEBUG_BRIDGE + ( + .clk (aclk ), + .S_BSCAN_drck (drck ), + .S_BSCAN_shift (shift ), + .S_BSCAN_tdi (tdi ), + .S_BSCAN_update (update ), + .S_BSCAN_sel (sel ), + .S_BSCAN_tdo (tdo ), + .S_BSCAN_tms (tms ), + .S_BSCAN_tck (tck ), + .S_BSCAN_runtest (runtest ), + .S_BSCAN_reset (reset ), + .S_BSCAN_capture (capture ), + .S_BSCAN_bscanid_en (bscanid_en ) + ); + +All debug cores within the CL must be connected to the ``CL_Debug_Bridge``. +These connections can be automatically inserted during the design synthesis +process. For an example implementation, please refer to the +`synth_cl_dram_hbm_dma.tcl script +<./../cl/examples/cl_dram_hbm_dma/build/scripts/synth_cl_dram_hbm_dma.tcl>`__ +in the cl_dram_hbm_dma example. + +.. code:: bash + + AWS FPGA: (12:35:47): Connecting debug network + + ## set cl_ila_cells [get_cells [list CL_ILA/CL_DMA_ILA_0 CL_ILA/ddr_A_hookup.CL_DDRA_ILA_0]] + ## if {$cl_ila_cells != ""} { + ## connect_debug_cores -master [get_cells [get_debug_cores -filter {NAME=~*CL_DEBUG_BRIDGE*}]] \ + ## -slaves $cl_ila_cells + ## } + + INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 + Done building netlist checker database: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.13 . Memory (MB): peak = 7233.012 ; gain = 0.000 ; free physical = 1006692 ; free virtual = 1545285 + INFO: [Chipscope 16-344] Connected debug slave core CL_ILA/CL_DMA_ILA_0 to master core CL_ILA/CL_DEBUG_BRIDGE/inst/xsdbm + INFO: [Chipscope 16-344] Connected debug slave core CL_ILA/ddr_A_hookup.CL_DDRA_ILA_0 to master core CL_ILA/CL_DEBUG_BRIDGE/inst/xsdbm + connect_debug_cores: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 7233.012 ; gain = 0.000 ; free physical = 1006693 ; free virtual = 1545287 + +Frequently Asked Questions +-------------------------- + +**Q: Do I need full Vivado installation to run Virtual JTAG debug on a F2 +instance?** + +A: No. If you are utilizing the AWS FPGA developer AMI, you can leverage the +built-in Vivado. If you using a different runtime AMI, you can download the +standalone Vivado Lab Solutions from `AMD website +`__ +and use that for free. + +**Q: Do I need a Vivado license to use Virtual JTAG and Xilinx VIO/LIA debug +capabilities?** + +A: No. All you require is the Vivado Hardware Manager, which is included with +the Vivado Lab Solutions and is available free of charge. + +.. |vjtag_1| image:: ./../../_static/VJTAG_images/vjtag_1.jpg +.. |vjtag_2| image:: ./../../_static/VJTAG_images/vjtag_2.jpg +.. |vjtag_3| image:: ./../../_static/VJTAG_images/vjtag_3.jpg +.. |vjtag_4| image:: ./../../_static/VJTAG_images/vjtag_4.jpg +.. |vjtag_5| image:: ./../../_static/VJTAG_images/vjtag_5.jpg +.. |vjtag_6| image:: ./../../_static/VJTAG_images/vjtag_6.jpg diff --git a/docs-rtd/source/hdk/docs/on_premise_licensing_help.rst b/docs-rtd/source/hdk/docs/on_premise_licensing_help.rst new file mode 100644 index 000000000..a978448a8 --- /dev/null +++ b/docs-rtd/source/hdk/docs/on_premise_licensing_help.rst @@ -0,0 +1,41 @@ +Enabling on-premises development with Xilinx tools +================================================== + +This document helps developers who choose to develop on-premises with +specifying and licensing AWS-compatible Xilinx tools for use with the +AWS FPGA HDK. + +.. _requirements-for-aws-hdk-20241: + +Requirements for AWS HDK (2024.1) +--------------------------------- + +- Xilinx Vivado ML Enterprise Edition v2024.1 +- Floating License: ``EF-VIVADO-ENTER-FL`` +- Node locked License: ``EF-VIVADO-ENTER-NL`` +- `URL `__ +- MD5 SUM Value: ``372c0b184e32001137424e395823de3c`` + +Licensing Details +----------------- + +- On-Premises customers may need a new or updated license + + - New users will need to obtain a Vivado ML Enterprise license. This + can be purchased via the AMD website `Vivado License + Link `__ + - The correct ordering number for the Node-locked is + EF-VIVADO-ENTER-NL and Floating is EF-VIVADO-ENTER-FL + - Please send a request to xilinx_security_app@amd.com to have the + encryption license added to your existing one + - You can confirm you are using the correct license for this product + by ensuring you have the following in Xilinx License Manager: + + - EncryptedWriter_v2 + - Analyzer + - Synthesis + - Implementation + - HLS + - SDK + - Partial Reconfiguration + - Simulation diff --git a/docs-rtd/source/hdk/docs/shell_floorplan.rst b/docs-rtd/source/hdk/docs/shell_floorplan.rst new file mode 100644 index 000000000..719d02528 --- /dev/null +++ b/docs-rtd/source/hdk/docs/shell_floorplan.rst @@ -0,0 +1,17 @@ +Shell Floorplan Reference +========================= + +This document provides the floorplan of Small Shell + +Small Shell +----------- + +|Small_shell_floorplan| + +Recommendations +--------------- + +- PCIS bus is physically located in SLR1 in SMALL_SHELL. Any customer + logic interfacing with this bus should reside in SLR1. + +.. |Small_shell_floorplan| image:: ./../../_static/small_shell_fp.png diff --git a/docs-rtd/source/index.rst b/docs-rtd/source/index.rst new file mode 100644 index 000000000..b59defc2f --- /dev/null +++ b/docs-rtd/source/index.rst @@ -0,0 +1,55 @@ +.. F2 documentation master file, created by + sphinx-quickstart on Sat Nov 23 04:21:40 2024. + You can adapt this file completely to your liking, but it should at least + contain the root `toctree` directive. + +Welcome to F2's documentation! +============================== + +Contents: + +.. toctree:: + :maxdepth: 5 + + ERRATA + README + RELEASE_NOTES + User_Guide_AWS_EC2_FPGA_Development_Kit.rst + + developer_resources/DCV + + hdk/README + hdk/cl/CHECKLIST_BEFORE_BUILDING_CL + hdk/cl/examples/cl_sde/README + hdk/cl/examples/cl_sde/verif/README + hdk/cl/examples/cl_mem_perf/README + hdk/cl/examples/cl_mem_perf/verif/README + hdk/cl/examples/CL_TEMPLATE/README + hdk/cl/examples/cl_dram_hbm_dma/README + hdk/cl/examples/cl_dram_hbm_dma/verif/README + hdk/docs/Virtual_JTAG_XVC + hdk/docs/on_premise_licensing_help + hdk/docs/RTL_Simulation_Guide_for_HDK_Design_Flow + hdk/docs/AWS_CLK_GEN_spec + hdk/docs/Clock_Recipes_User_Guide + hdk/docs/AWS_Shell_Interface_Specification + hdk/docs/AWS_Shell_ERRATA + hdk/docs/AWS_Fpga_Pcie_Memory_Map + hdk/docs/shell_floorplan + hdk/docs/Supported_DDR_Modes + + sdk/README + sdk/apps/virtual-ethernet/README + sdk/apps/virtual-ethernet/doc/Virtual_Ethernet_Application_Guide + sdk/apps/virtual-ethernet/doc/SDE_HW_Guide + sdk/userspace/fpga_mgmt_tools/README + + vitis/README + + +Indices and tables +================== + +* :ref:`genindex` +* :ref:`modindex` +* :ref:`search` diff --git a/docs-rtd/source/sdk/README.rst b/docs-rtd/source/sdk/README.rst new file mode 100644 index 000000000..6ab28a03b --- /dev/null +++ b/docs-rtd/source/sdk/README.rst @@ -0,0 +1,63 @@ +AWS EC2 FPGA Software Development Kit +===================================== + +This directory includes the drivers and runtime environment required by +any EC2 FPGA Instance. + +The `SDK userspace directory <./userspace>`__ contains the `Amazon FPGA +Image (AFI) Management Tools <./userspace/fpga_mgmt_tools/README.md>`__, +which includes both the source code to the AFI Management Tools as well +as detailed descriptions of the commands to use on an FPGA instance. + +The SDK is **NOT** used to build or register AFI, rather it is only used +for managing and deploying pre-built AFIs. For building and registering +AFIs, please refer to the `HDK <../hdk/README.md>`__. + +**NOTE:** This SDK is designed and tested for Linux environments only. + +Quick Start +=========== + +Using an AFI on an EC2 FPGA Instance +------------------------------------ + +You can setup and install the SDK with the following few steps. Note +that the first two steps may be skipped if you have already ran them in +the above HDK setup. + +.. code:: bash + + # Fetch the HDK and SDK code + git clone https://github.com/aws/aws-fpga.git + # Move to the root directory of the repository before running the next script + cd aws-fpga + # Set up the envronment variables, build and install the SDK + source sdk_setup.sh + +**NOTE:** The ``sdk_setup.sh`` would install the `FPGA management +tools <./userspace/fpga_mgmt_tools/README.md>`__ if they are not already +available in ``/usr/bin``. The ``sdk_setup.sh`` requires having ``gcc`` +installed. if it is not installed, try running the next command to +install it on Amazon Linux, Centos or Redhat distributions: + +Notes on using AFI Management Tools +----------------------------------- + +Early release of the AFI management tools may return uninformative +errors or unexpected responses. We recommend running commands a second +time after waiting 15-30 seconds if an unexpected response is received. +For example, if a loaded image does not show up when using the +``fpga-describe-local-image`` API, attempt rerunning the command prior +to calling ``fpga-load-local-image`` again. + +The ``fpga-describe-local-image`` API is currently asynchronous which +will require polling with ``fpga-describe-local-image`` until the +expected image appears. If the describe call does not provide the +expected response, attempt the ``fpga-load-local-image`` one more time. +Attempting to load images that are not compatible with the currently +loaded shell will fail and may not return an informative error message. +Please verify the design was built with the shell that is loaded on the +instance. + +Please reach out to the AWS FPGA team with any instability issues so we +can help as soon as possible. diff --git a/docs-rtd/source/sdk/apps/virtual-ethernet/README.rst b/docs-rtd/source/sdk/apps/virtual-ethernet/README.rst new file mode 100644 index 000000000..cec4930fd --- /dev/null +++ b/docs-rtd/source/sdk/apps/virtual-ethernet/README.rst @@ -0,0 +1,103 @@ +Virtual Ethernet +================ + +The Virtual Ethernet framework facilitates streaming Ethernet frames +from a network interface (or any source) into the FPGA for processing +and back out to some destination. Possible use cases for this include +deep packet inspection, software defined networking, stream encryption +or compression, and more. + +⚠️\ **Note**: Please note that Virtual Ethernet/SDE is not supported by +Vitis (XRT) + +Prerequisites +------------- + +In order to get the most from this document, readers may want to +familiarize themselves with the following: + +1. The `F2 customer logic + flow <../../../hdk/README.md#build-accelerator-afi-using-hdk-design-flow>`__; + creating and loading AFIs (Amazon FPGA Images) +2. `DPDK `__ (Data Plane Development Kit), a framework + for creating high performance network traffic handling tools in + userspace by limiting context switches, locks, or other blocking + logic. +3. `EC2 Networking + Concepts `__ + +Virtual Ethernet Architecture +============================= + +The Virtual Ethernet architecture is built upon DPDK (http://dpdk.org). +DPDK is an open source set of libraries and drivers for fast packet +processing, and runs mostly in Linux user-space. + +The following diagram shows the high level architecture for the Virtual +Ethernet sample application(s) and Bringup/Debug tools. + +|alt tag| + +User Space +---------- + +**[1]** **Virtual Ethernet Sample Applications(s)**: The Virtual +Ethernet sample application(s) use the DPDK testpmd application for +simple and efficient port-to-port forwarding. You can use this as a +starting point for your custom applications. + +**[2]** **DPDK Environment**: The DPDK Environment Abstraction Layer +(EAL) that provides the fast packet processing infrastructure in user +space. + +**[3]** **DPDK SPP PMD Driver**: The AWS Streaming Packet Port (SPP) +poll-mode driver that interfaces to the Streaming Data Engine (SDE). + +**[4]** **DPDK KNI PMD Driver**: An optional driver that may be used for +Linux kernel Ethernet frame ingress/egress. + +**[5]** **DPDK PCAP PMD Driver**: An optional driver that may be used +for PCAP Ethernet frame ingress/egress. + +**[6]** **DPDK ENA PMD Driver**: The AWS Enhanced Network Adapter (ENA) +poll-mode driver that interfaces to the Enhanced Network Interface +(ENI). + +Kernel +------ + +**[7]** **KNI**: The optional DPDK Kernel Network Interface (KNI) +provides a path from DPDK in user space to the Linux kernel for Linux +kernel Ethernet frame ingress/egress. DPDK applications that want to +handle network control plane protocols like DHCP and ARP within the +Linux kernel may leverage the DPDK KNI interface for this purpose. + +Hardware +-------- + +**[8]** **SDE**: The Streaming Data Engine that supports the AXI-4 +streaming interface to the FPGA custom logic (CL). + +**[9]** **ENI**: The sample application setup scripts will configure the +data-plane end-to-end traffic to use the ENI eth1 interface. ENI eth0 +will be reserved for your SSH connections, and other control-plane +traffic. + +Application Guide +================= + +The above Virtual Ethernet architecture supports your development phases +with sample applications that include loopback paths for bringup and +debug of the Virtual Ethernet application and custom CL, all the way to +end-to-end application integration with live traffic. + +Please refer to the `Application +Guide <./doc/Virtual_Ethernet_Application_Guide.md>`__ for details. + +Hardware Guide +============== + +More details about the Streaming Data Engine itself are covered in the +`Hardware Guide <./doc/SDE_HW_Guide.md>`__. + +.. |alt tag| image:: ./images/Virtual_Ethernet_Arch.jpg diff --git a/docs-rtd/source/sdk/apps/virtual-ethernet/doc/SDE_HW_Guide.rst b/docs-rtd/source/sdk/apps/virtual-ethernet/doc/SDE_HW_Guide.rst new file mode 100644 index 000000000..8cbffa082 --- /dev/null +++ b/docs-rtd/source/sdk/apps/virtual-ethernet/doc/SDE_HW_Guide.rst @@ -0,0 +1,2826 @@ +SDE Hardware Guide +================== + +Table of Contents: +================== + +- `Overview <#Overview>`__ + +- `Feature List <#FeatureList>`__ + +- `Architecture <#Architecture>`__ + +- `Designing with the SDE <#DesignCLwSDE>`__ + + - `IOs <#IOs>`__ + + - `Design Configuration Parameters <#DesignParam>`__ + + - `PF and Address Range <#PF_AddressRange>`__ + + - `CSR Description and Address Mapping <#CSRRange>`__ + + - `Descriptors and Write-Back Metadata <#Descriptors>`__ + + - `Credit Mechanism <#Credit>`__ + + - `Write-Back Mechanism <#WBM>`__ + + - `Data Flow Model <#DataFlow>`__ + + - `Error Conditions <#Error>`__ + + - `Implementation - Maximum Clock Frequency <#MaxClockFreq>`__ + + - `Implementation - Resource Utilization <#ResourceUtil>`__ + +- `Example Design <#ExampleDesign>`__ + +- `FAQ <#FAQ>`__ + +Overview +======== + +The Streaming Data Engine (SDE) provides high-performance packet +streaming connectivity between the Custom Logic (CL) and the host +application. The SDE provides a streaming interface to the CL and uses +the shell's PCIM AXI4 interface to move packets between the CL and the +host application. The SDE is a parameterizable, soft IP block that is +intended to be instantiated within the CL. Each instance of the SDE +provides two AXI streaming compliant interfaces viz. one Card-to-Host +(C2H) and one Host-to-Card (H2C) channel. + +Feature List +============ + +1. High Performance PPS for C2H and H2C. +2. 12GB/s Bandwidth per channel for C2H and H2C (4KB packet at 250MHz). +3. AXI Stream compliant on the CL facing side. +4. AXI Stream supports parameterizable data widths 64, 128, 256 and 512 + bits (Current version supports 512 bits only). +5. AXI4 complaint on the shell facing side. +6. AXI4 supports parameterizable data widths 64, 128, 256 and 512 bits + (Current version supports 512 bits only). +7. User bits on the RX and TX streaming interfaces. +8. Multiple descriptor types (Normal and Compact). +9. Multiple descriptors per packet. +10. Write-back for credits and metadata. +11. Multiple write-back metadata types (Normal and compact) +12. One instance of the streaming data engine can be configured at + compile-time to provide the following channel combinations + +- One full-duplex streaming channel (one C2H and one H2C). +- One Streaming C2H Channel only (No H2C Channel) +- One Streaming H2C Channel only (No C2H Channel) + +Architecture +============ + +|alt tag| + +The SDE uses shell's PCIM AXI4 interface to move packets between the AXI +Streaming interface and the host. It implements a store and forward +mechanism. For C2H, the packets received from the AXI Streaming +interface is stored in the C2H packet buffer and are then transmitted on +the PCIM AXI4 interface. For H2C, the packets received from the PCIM +AXI4 interface are stored in the H2C packet buffer and are then +transmitted on the AXI Streaming interface. + +SDE uses descriptors to perform the data movement and the bit-fields of +the descriptors are defined to contain all required information for data +transfer like buffer physical addresses, length etc. To achieve minimum +latency, the SDE implements a descriptor RAM that can be written by +software using the PCIS interface utilizing write-combine using +PF0-BAR4. The SDE implements a credit based mechanism to allow the +software to track the descriptor utilization. + +In order to minimize latency and reduce the complexity of the +software/driver, all the information that is polled by the +driver/software (for example, descriptor credits, write-back ring write +pointer, etc...) is stored in a contiguous host memory range. The SDE is +architected to update these variables together by writing to the +physical memory location using the PCIM interface. + +Designing with the SDE +====================== + +IOs +--- + +- PCIM AXI4 Master Interface: SDE uses this interface to write data to + the host. +- PCIS AXI4 Slave Interface: Software uses this interface to write + descriptors and configuration data to the SDE. +- H2C AXI Stream Master Interface: SDE uses this interface to transmit + H2C packets to the CL. +- C2H AXI Stream Slave Interface: SDE uses this interface to receive C2H + packets from the CL. +- Clocks and Reset: SDE uses a single clock and a single synchronous + active-low reset. + +Design Configuration parameters +------------------------------- + +The SDE can be parameterized when the SDE is instanced in the CL. These +configuration parameters are static parameters and are expected to be +set when the SDE is instanced in the CL. Some important parameters are +summarized below. + +- C2H_ONLY: Disable SDE H2C logic (Can be set to 1 if only the C2H + channel is required). +- H2C_ONLY: Disable SDE C2H logic (Can be set to 1 if only the C2H + channel is required). +- C2H_DESC_TYPE & H2C_DESC_TYPE: Descriptor Type (0 - Regular, 1 - + Compact) for C2H and H2C respectively. +- C2H_DESC_RAM_DEPTH & H2C_DESC_RAM_DEPTH: Descriptor RAM depth. The + maximum number of descriptors for C2H and H2C respectively. +- C2H_BUF_DEPTH & H2C_BUF_DEPTH: Buffer RAM depth. + +Full List of Parameters are listed in table below. **Supported values +for each parameter are listed in Supported Configurations column.** + ++-----------------+-------------+-----------------+-----------------+ +| **Name** | **Default** | **Supported | **Description** | +| | | C | | +| | | onfigurations** | | ++=================+=============+=================+=================+ +| C2H_ONLY | 0 | 0, 1 | This should be | +| | | | set to 1 if | +| | | | only C2H is | +| | | | required and | +| | | | H2C is not | +| | | | required. NOTE: | +| | | | If C2H_ONLY = | +| | | | 1, H2C_ONLY | +| | | | should be 0. | ++-----------------+-------------+-----------------+-----------------+ +| H2C_ONLY | 0 | 0, 1 | This should be | +| | | | set to 1 if | +| | | | only H2C is | +| | | | required and | +| | | | C2H is not | +| | | | required. NOTE: | +| | | | If H2C_ONLY = | +| | | | 1, C2H_ONLY | +| | | | should be 0. | ++-----------------+-------------+-----------------+-----------------+ +| PCIS_DATA_WIDTH | 512 | Default only | PCIS AXI4 Data | +| | | | Bus Width | ++-----------------+-------------+-----------------+-----------------+ +| PCIS_ID_WIDTH | 16 | Default only | PCIS AXI4 ID | +| | | | Width | ++-----------------+-------------+-----------------+-----------------+ +| PCIS_LEN_WIDTH | 8 | Default only | PCIS AXI4 AWLEN | +| | | | and ARLEN Width | ++-----------------+-------------+-----------------+-----------------+ +| PCIS_ADDR_WIDTH | 64 | Default only | PCIS AXI4 | +| | | | AWADDR and | +| | | | ARADDR Width | ++-----------------+-------------+-----------------+-----------------+ +| PCIM_DATA_WIDTH | 512 | Default only | PCIM AXI4 Data | +| | | | Bus Width | ++-----------------+-------------+-----------------+-----------------+ +| PCIM_ID_WIDTH | 3 | Default only | PCIM AXI4 ID | +| | | | Width | ++-----------------+-------------+-----------------+-----------------+ +| PCIM_LEN_WIDTH | 8 | Default only | PCIM AXI4 AWLEN | +| | | | and ARLEN Width | ++-----------------+-------------+-----------------+-----------------+ +| PCIM_ADDR_WIDTH | 64 | Default only | PCIM AXI4 | +| | | | AWADDR and | +| | | | ARADDR Width | ++-----------------+-------------+-----------------+-----------------+ +| C2H_DESC_TYPE | 0 | 0, 1 | Descriptor Type | +| | | | (0 – Regular, 1 | +| | | | – Compact) | ++-----------------+-------------+-----------------+-----------------+ +| C2H | 64 | 64, 128 | Descriptor RAM | +| _DESC_RAM_DEPTH | | | Depth. This is | +| | | | the maximum | +| | | | number of | +| | | | descriptors | ++-----------------+-------------+-----------------+-----------------+ +| C2H_BUF_DEPTH | 512 | 64, 128, 256, | C2H Buffer RAM | +| | | 512 | Depth. This is | +| | | | the maximum | +| | | | number of data | +| | | | slices that the | +| | | | buffer can | +| | | | hold. C2H | +| | | | buffer width is | +| | | | equal to | +| | | | P | +| | | | CIM_DATA_WIDTH. | +| | | | C2H Buffer size | +| | | | is | +| | | | (C2 | +| | | | H_BUF_DEPTH*PCI | +| | | | M_DATA_WIDTH/8) | +| | | | bytes. | ++-----------------+-------------+-----------------+-----------------+ +| C2H_ | 512 | Default only | AXIS Data Width | +| AXIS_DATA_WIDTH | | | | ++-----------------+-------------+-----------------+-----------------+ +| C2H | 64 | Default only | User Bit Width | +| _USER_BIT_WIDTH | | | | ++-----------------+-------------+-----------------+-----------------+ +| H2C_DESC_TYPE | 0 | 0, 1 | Descriptor Type | +| | | | (0 – Regular, 1 | +| | | | – Compact) | ++-----------------+-------------+-----------------+-----------------+ +| H2C | 64 | 64, 128 | Descriptor RAM | +| _DESC_RAM_DEPTH | | | Depth. This is | +| | | | the maximum | +| | | | number of | +| | | | descriptors | ++-----------------+-------------+-----------------+-----------------+ +| H2C_BUF_DEPTH | 512 | 64, 128, 256, | H2C Buffer RAM | +| | | 512 | Depth. This is | +| | | | the maximum | +| | | | number of data | +| | | | slices that the | +| | | | buffer can | +| | | | hold. Buffer | +| | | | width is equal | +| | | | to | +| | | | P | +| | | | CIM_DATA_WIDTH. | +| | | | H2C Buffer size | +| | | | is | +| | | | (H2 | +| | | | C_BUF_DEPTH*PCI | +| | | | M_DATA_WIDTH/8) | +| | | | bytes. | ++-----------------+-------------+-----------------+-----------------+ +| H2C_ | 512 | Default only | AXIS Data Width | +| AXIS_DATA_WIDTH | | | | ++-----------------+-------------+-----------------+-----------------+ +| H2C | 64 | Default only | User Bit Width | +| _USER_BIT_WIDTH | | | | ++-----------------+-------------+-----------------+-----------------+ +| H2C | 64 | Default only | H2C Small | +| _PKT_SIZE_BYTES | | | Packet Size in | +| | | | Bytes | ++-----------------+-------------+-----------------+-----------------+ +| C | 0 | Default only | AWID for C2H | +| 2H_PCIM_DM_AWID | | | Data Mover PCIM | +| | | | AXI4 Write | +| | | | Accesses | ++-----------------+-------------+-----------------+-----------------+ +| C | 1 | Default only | AWID for C2H | +| 2H_PCIM_WB_AWID | | | Write-Back PCIM | +| | | | AXI4 Write | +| | | | Accesses | ++-----------------+-------------+-----------------+-----------------+ +| H | 2 | Default only | AWID for C2H | +| 2C_PCIM_WB_AWID | | | Write-Back PCIM | +| | | | AXI4 Write | +| | | | Accesses | ++-----------------+-------------+-----------------+-----------------+ +| C2H | 0 | Default only | ARID for C2H | +| _PCIM_DESC_ARID | | | Descriptor PCIM | +| | | | AXI4 Read | +| | | | Accesses | ++-----------------+-------------+-----------------+-----------------+ +| H2C | 1 | Default only | ARID for H2C | +| _PCIM_DESC_ARID | | | Descriptor PCIM | +| | | | AXI4 Read | +| | | | Accesses | ++-----------------+-------------+-----------------+-----------------+ +| H | 2 | Default only | ARID for C2H | +| 2C_PCIM_DM_ARID | | | Data Mover PCIM | +| | | | AXI4 Read | +| | | | Accesses | ++-----------------+-------------+-----------------+-----------------+ +| PCIM_NUM_OT_RD | 64 | Default only | PCIM Number of | +| | | | Outstanding | +| | | | Reads. This | +| | | | should be 64 | +| | | | when using the | +| | | | AWS shell in | +| | | | order to | +| | | | maximize H2C | +| | | | performance. | ++-----------------+-------------+-----------------+-----------------+ +| H2C_P | 0 | Default only | H2C Maximum AXI | +| CIM_MAX_RD_SIZE | | | Read request | +| | | | size (0 – 512B, | +| | | | 1 – 1KB, 2 – | +| | | | 2KB, 3 – 4KB). | +| | | | This should be | +| | | | 0 when using | +| | | | the AWS shell | +| | | | in order to | +| | | | maximize H2C | +| | | | performance. | ++-----------------+-------------+-----------------+-----------------+ +| C2H_P | 0 | Default only | C2H Maximum AXI | +| CIM_MAX_WR_SIZE | | | Write request | +| | | | size (0 – 512B, | +| | | | 1 – 1KB, 2 – | +| | | | 2KB, 3 – 4KB). | +| | | | This should be | +| | | | 3 when using | +| | | | the AWS shell | +| | | | in order to | +| | | | maximize C2H | +| | | | performance. | ++-----------------+-------------+-----------------+-----------------+ + +PF and Address Mapping +~~~~~~~~~~~~~~~~~~~~~~ + +SDE implements a 16KB address space on the PCIS interface and therefore +can be accessed using the PF0-BAR4. SDE uses the lower 16 bits of the +address bus of the PCIS interface. The SDE address window should be 16KB +aligned. The following table describes address mapping within SDE. + ++-------------+-------------+-------------+-------------+-------------+ +| **Address | **Size | **Name** | **Access | **De | +| Range** | (Bytes)** | | Type** | scription** | ++=============+=============+=============+=============+=============+ +| 0x0000 – | 4K | C2H | Write Only | Software | +| 0x0FFC | | Descriptor | (wri | should use | +| | | RAM | te-combine) | this | +| | | | | address | +| | | | | range when | +| | | | | writing the | +| | | | | C2H | +| | | | | D | +| | | | | escriptors. | +| | | | | Software | +| | | | | should only | +| | | | | use 64 byte | +| | | | | aligned | +| | | | | addresses | +| | | | | in this | +| | | | | range to | +| | | | | write | +| | | | | partial or | +| | | | | full | +| | | | | d | +| | | | | escriptors. | +| | | | | SDE will | +| | | | | write the | +| | | | | descriptors | +| | | | | into the | +| | | | | descriptor | +| | | | | RAM in a | +| | | | | FIFO | +| | | | | pattern. | +| | | | | Only write | +| | | | | accesses of | +| | | | | 1DW, 4DW or | +| | | | | 8DW are | +| | | | | allowed to | +| | | | | this | +| | | | | address | +| | | | | range. Read | +| | | | | accesses | +| | | | | should not | +| | | | | be | +| | | | | performed | +| | | | | and are not | +| | | | | supported | +| | | | | in this | +| | | | | address | +| | | | | range. | ++-------------+-------------+-------------+-------------+-------------+ +| 0x1000 – | 4K | H2C | Write Only | Software | +| 0x1FFC | | Descriptor | (wri | should use | +| | | RAM | te-combine) | this | +| | | | | address | +| | | | | range when | +| | | | | writing the | +| | | | | H2C | +| | | | | D | +| | | | | escriptors. | +| | | | | Software | +| | | | | should only | +| | | | | use 64 byte | +| | | | | aligned | +| | | | | addresses | +| | | | | in this | +| | | | | range to | +| | | | | write | +| | | | | partial or | +| | | | | full | +| | | | | d | +| | | | | escriptors. | +| | | | | SDE will | +| | | | | write the | +| | | | | descriptors | +| | | | | into the | +| | | | | descriptor | +| | | | | RAM in a | +| | | | | FIFO | +| | | | | pattern. | +| | | | | Only write | +| | | | | accesses of | +| | | | | 1DW, 4DW or | +| | | | | 8DW are | +| | | | | allowed to | +| | | | | this | +| | | | | address | +| | | | | range. Read | +| | | | | accesses | +| | | | | should not | +| | | | | be | +| | | | | performed | +| | | | | and are not | +| | | | | supported | +| | | | | in this | +| | | | | address | +| | | | | range. | ++-------------+-------------+-------------+-------------+-------------+ +| 0x2000 – | 4K | RSVD | Do not use | Reserved | +| 0x2FFC | | | | for future | +| | | | | use | ++-------------+-------------+-------------+-------------+-------------+ +| 0x3000 – | 4K | CSRs | Read-Write | Software | +| 0x3FFC | | | (DW | should use | +| | | | accesses) | this | +| | | | | address | +| | | | | range when | +| | | | | accessing | +| | | | | CSRs. | +| | | | | Software | +| | | | | should use | +| | | | | only 4 byte | +| | | | | aligned | +| | | | | address of | +| | | | | the | +| | | | | registers | +| | | | | to access | +| | | | | CSRs | +| | | | | implemented | +| | | | | in this | +| | | | | range. Only | +| | | | | 1 DW read | +| | | | | or 1 DW | +| | | | | write | +| | | | | accesses | +| | | | | are allowed | +| | | | | in this | +| | | | | range. | ++-------------+-------------+-------------+-------------+-------------+ + +CSR Description and Address Mapping +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +-------------- + +The CSR address space starts at the CSR base address and is organized as +shown below + ++-----------------+-----------------+-----------+-----------------+ +| **Address | **Size | **Name** | **Description** | +| Range** | (Bytes)** | | | ++=================+=================+===========+=================+ +| 0x3000 – 0x31FC | 512 | PCIS CSRs | PCIS slave | +| | | | Config and | +| | | | Status | +| | | | Registers | ++-----------------+-----------------+-----------+-----------------+ +| 0x3200 – 0x33FC | 512 | PCIM CSRs | PCIM arbiter | +| | | | Config and | +| | | | Status | +| | | | Registers | ++-----------------+-----------------+-----------+-----------------+ +| 0x3400 – 0x39FC | 1536 | C2H CSRs | C2H Config and | +| | | | Status | +| | | | Registers | ++-----------------+-----------------+-----------+-----------------+ +| 0x3A00 – 0x3FFC | 1536 | H2C CSRs | H2C Config and | +| | | | Status | +| | | | Registers | ++-----------------+-----------------+-----------+-----------------+ + +PCIS CSRs +--------- + +1. **Software Reset Register** + + Address – PCIS_BASE_ADDR + 0x3000 + + CSR Offset – CSR_BASE_ADDR + 0x000 + + PCIS CSR Offset – PCIS_CSR_BASE_ADDR + 0x000 + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| SW_RST | 0 | RW | 0x0 | Software | +| | | | | Reset. When | +| | | | | Set, reset | +| | | | | is asserted | +| | | | | to all the | +| | | | | functional | +| | | | | blocks of | +| | | | | the SDE | +| | | | | except the | +| | | | | PCIS Slave | +| | | | | Block. | ++-------------+-------------+----------+-------------+-------------+ +| RSVD | 31:1 | RO | 0x0 | Reserved | ++-------------+-------------+----------+-------------+-------------+ + +2. **SDE Info Register** + + Address – PCIS_BASE_ADDR + 0x3004 + + CSR Offset – CSR_BASE_ADDR + 0x004 + + PCIS CSR Offset – PCIS_CSR_BASE_ADDR + 0x004 + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| C2H_PRESENT | 0 | RO | 0x0 | 1 = C2H | +| | | | | Instanced 0 | +| | | | | = C2H Not | +| | | | | Instanced | ++-------------+-------------+----------+-------------+-------------+ +| RSVD | 15:1 | RO | 0x0 | Reserved | ++-------------+-------------+----------+-------------+-------------+ +| H2C_PRESENT | 16 | RO | 0x0 | 1 = H2C | +| | | | | Instanced 0 | +| | | | | = H2C Not | +| | | | | Instanced | ++-------------+-------------+----------+-------------+-------------+ +| RSVD | 31:17 | RO | 0x0 | Reserved | ++-------------+-------------+----------+-------------+-------------+ + +PCIM CSRs +--------- + +RSVD for future Use + +C2H CSRs +-------- + +**C2H CSR Address Mapping** + ++----------------+----------------+----------------+----------------+ +| **Address | **Size | **Name** | * | +| Range** | (Bytes)** | | *Description** | ++================+================+================+================+ +| 0x3400 – | 256 | C2H Global | C2H Global | +| 0x34FC | | CSRs | Config and | +| | | | Status | +| | | | Registers | ++----------------+----------------+----------------+----------------+ +| 0x3500 – | 256 | C2H Descriptor | C2H Descriptor | +| 0x35FC | | CSRs | Config and | +| | | | Status | +| | | | Registers | ++----------------+----------------+----------------+----------------+ +| 0x3600 – | 256 | C2H Data Mover | C2H Data Mover | +| 0x36FC | | CSRs | Config and | +| | | | Status | +| | | | Registers | ++----------------+----------------+----------------+----------------+ +| 0x3700 – | 256 | C2H Write-back | C2H Write-Back | +| 0x37FC | | CSRs | Config and | +| | | | Status | +| | | | Registers | ++----------------+----------------+----------------+----------------+ +| 0x3800 – | 256 | C2H Buffer | C2H Buffer | +| 0x38FC | | CSRs | Config and | +| | | | Status | +| | | | Registers | ++----------------+----------------+----------------+----------------+ +| 0x3900 – | 256 | C2H AXIS CSRs | C2H AXI-Stream | +| 0x39FC | | | Config and | +| | | | Status | +| | | | Registers | ++----------------+----------------+----------------+----------------+ + +C2H Global CSRs +--------------- + +RSVD for future use. + +C2H Descriptor CSRs +------------------- + +1. **Descriptor Credit Consumed Counter** + + Address – PCIS_BASE_ADDR + 0x3500 + + CSR Offset – CSR_BASE_ADDR + 0x500 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x100 + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| C | 31:0 | RW0C | 0x0 | Descriptor | +| DT_CONSUMED | | | | Credit | +| | | | | Consumed | +| | | | | Counter. | +| | | | | Write 0 to | +| | | | | clear. | ++-------------+-------------+----------+-------------+-------------+ + +2. **Descriptor Credit Limit Counter** + + Address – PCIS_BASE_ADDR + 0x3504 + + CSR Offset – CSR_BASE_ADDR + 0x504 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x104 + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| CDT_LIMIT | 31:0 | RW0C | C2H_DES | Descriptor | +| | | | C_RAM_DEPTH | Credit | +| | | | | Limit | +| | | | | Counter. | +| | | | | Write 0 to | +| | | | | clear. When | +| | | | | cleared, | +| | | | | the value | +| | | | | of the | +| | | | | counter is | +| | | | | reset to | +| | | | | C2H_DESC | +| | | | | _RAM_DEPTH. | ++-------------+-------------+----------+-------------+-------------+ + +3. **Completed Descriptors Counter** + + Address – PCIS_BASE_ADDR + 0x3508 + + CSR Offset – CSR_BASE_ADDR + 0x508 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x108 + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| COMP_COUNT | 31:0 | RW0C | 0x0 | Completed | +| | | | | Descriptor | +| | | | | Counter. | +| | | | | Write 0 to | +| | | | | clear. | ++-------------+-------------+----------+-------------+-------------+ + +4. **Descriptor FIFO Pointers** + + Address – PCIS_BASE_ADDR + 0x350C + + CSR Offset – CSR_BASE_ADDR + 0x50C + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x10C + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| FIFO_WR_PTR | 14:0 | RO | 0x0 | Descriptor | +| | | | | FIFO Write | +| | | | | Pointer | ++-------------+-------------+----------+-------------+-------------+ +| FIFO | 15 | RO | 0x0 | Descriptor | +| _WR_PTR_MSB | | | | FIFO Write | +| | | | | Pointer MSB | ++-------------+-------------+----------+-------------+-------------+ +| FIFO_RD_PTR | 30:16 | RO | 0x0 | Descriptor | +| | | | | FIFO Read | +| | | | | Pointer | ++-------------+-------------+----------+-------------+-------------+ +| FIFO | 31 | RO | 0x0 | Descriptor | +| _RD_PTR_MSB | | | | FIFO Read | +| | | | | Pointer MSB | ++-------------+-------------+----------+-------------+-------------+ + +5. **Descriptor RAM Address** + + Address – PCIS_BASE_ADDR + 0x3510 + + CSR Offset – CSR_BASE_ADDR + 0x510 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x110 + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| DE | 15:0 | RW | 0x0 | Descriptor | +| SC_RAM_ADDR | | | | RAM Address | ++-------------+-------------+----------+-------------+-------------+ +| DESC | 19:16 | RWC | 0x0 | Descriptor | +| _RAM_DW_IDX | | | | RAM Data DW | +| | | | | Index. This | +| | | | | bitfield is | +| | | | | cleared | +| | | | | when this | +| | | | | register is | +| | | | | written. | +| | | | | This will | +| | | | | aut | +| | | | | o-increment | +| | | | | when | +| | | | | DE | +| | | | | SC_RAM_DATA | +| | | | | is read or | +| | | | | written. | ++-------------+-------------+----------+-------------+-------------+ +| RSVD | 31:20 | RO | 0x0 | Reserved | ++-------------+-------------+----------+-------------+-------------+ + +6. **Descriptor RAM Data** + + Address – PCIS_BASE_ADDR + 0x3514 + + CSR Offset – CSR_BASE_ADDR + 0x514 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x114 + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| DESC_ | 31:0 | RW | 0x0 | Descriptor | +| RAM_DATA_DW | | | | RAM Data. | +| | | | | When | +| | | | | writing the | +| | | | | descriptor | +| | | | | RAM, SDE | +| | | | | initiates a | +| | | | | write to | +| | | | | the | +| | | | | descriptor | +| | | | | RAM after | +| | | | | all the DWs | +| | | | | that make | +| | | | | up the | +| | | | | descriptor | +| | | | | are written | +| | | | | to this | +| | | | | register. | +| | | | | When | +| | | | | reading the | +| | | | | descriptor | +| | | | | RAM, SDE | +| | | | | initiates a | +| | | | | read from | +| | | | | the | +| | | | | descriptor | +| | | | | RAM when | +| | | | | this | +| | | | | register is | +| | | | | read and | +| | | | | when the | +| | | | | DESC | +| | | | | _RAM_DW_IDX | +| | | | | is 0. | ++-------------+-------------+----------+-------------+-------------+ + +7. **Descriptor RAM Status** + + Address – PCIS_BASE_ADDR + 0x3518 + + CSR Offset – CSR_BASE_ADDR + 0x518 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x118 + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| DESC_OFLOW | 0 | RW1C | 0x0 | Desc RAM | +| | | | | Overflow | +| | | | | Indicates | +| | | | | that a | +| | | | | descriptor | +| | | | | was written | +| | | | | when the | +| | | | | descriptor | +| | | | | RAM is full | ++-------------+-------------+----------+-------------+-------------+ +| DES | 1 | RW1C | 0x0 | Desc Out of | +| C_OOO_ERROR | | | | Order Error | ++-------------+-------------+----------+-------------+-------------+ +| DESC_U | 2 | RW1C | 0x0 | Desc | +| NALIN_ERROR | | | | Unaligned | +| | | | | Address | +| | | | | Error | ++-------------+-------------+----------+-------------+-------------+ +| DESC_FULL | 3 | RO | 0x0 | Desc RAM | +| | | | | Full | ++-------------+-------------+----------+-------------+-------------+ +| DESC_EMPTY | 4 | RO | 0x0 | Desc RAM | +| | | | | Empty | ++-------------+-------------+----------+-------------+-------------+ +| RSVD | 31:5 | RO | 0x0 | Reserved | ++-------------+-------------+----------+-------------+-------------+ + +8. **Descriptor Info** + + Address – PCIS_BASE_ADDR + 0x3520 + + CSR Offset – CSR_BASE_ADDR + 0x520 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x120 + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| DESC_TYPE | 0 | RO | 0x0 | Descriptor | +| | | | | /Write-Back | +| | | | | Type 0 – | +| | | | | Regular 1 – | +| | | | | Compact | ++-------------+-------------+----------+-------------+-------------+ +| RSVD | 15:1 | RO | 0x0 | RSVD | ++-------------+-------------+----------+-------------+-------------+ +| DES | 31:16 | RO | 0x0 | Descriptor | +| C_RAM_DEPTH | | | | RAM Depth. | +| | | | | Maximum | +| | | | | Number of | +| | | | | d | +| | | | | escriptors. | ++-------------+-------------+----------+-------------+-------------+ + +C2H Data Mover CSRs +------------------- + +1. **Data Mover Config Register 0** + + Address – PCIS_BASE_ADDR + 0x3600 + + CSR Offset – CSR_BASE_ADDR + 0x600 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x200 + +============== ============= ======== ================= =============== +**Field Name** **Bit Range** **Type** **Default Value** **Description** +============== ============= ======== ================= =============== +RSVD 31:0 RW 0x0 Reserved +============== ============= ======== ================= =============== + +2. **Data Mover Status Register** + + Address – PCIS_BASE_ADDR + 0x3604 + + CSR Offset – CSR_BASE_ADDR + 0x604 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x204 + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| D | 0 | RW1C | 0x0 | Data Mover | +| M_BRESP_ERR | | | | Bresp Error | ++-------------+-------------+----------+-------------+-------------+ +| DM_D | 1 | RW1C | 0x0 | Descriptor | +| ESC_LEN_ERR | | | | Length | +| | | | | equal to 0 | ++-------------+-------------+----------+-------------+-------------+ +| RSVD | 31:2 | RO | 0x0 | Reserved | ++-------------+-------------+----------+-------------+-------------+ + +C2H Write-Back CSRs +------------------- + +1. **Write-Back Config Register 0** + + Address – PCIS_BASE_ADDR + 0x3700 + + CSR Offset – CSR_BASE_ADDR + 0x700 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x300 + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| DES | 0 | RW | 0x0 | Descriptor | +| C_CNT_WB_EN | | | | Count | +| | | | | Write-Back | +| | | | | Trigger | +| | | | | Enable. | +| | | | | When set, | +| | | | | SDE | +| | | | | schedules a | +| | | | | status | +| | | | | counter | +| | | | | write-back | +| | | | | when | +| | | | | descriptor | +| | | | | count | +| | | | | increments | ++-------------+-------------+----------+-------------+-------------+ +| PK | 1 | RW | 0x0 | Packet | +| T_CNT_WB_EN | | | | Count | +| | | | | Write-Back | +| | | | | Trigger | +| | | | | Enable. | +| | | | | When set, | +| | | | | SDE | +| | | | | schedules a | +| | | | | status | +| | | | | counter | +| | | | | write-back | +| | | | | when packet | +| | | | | count | +| | | | | increments. | ++-------------+-------------+----------+-------------+-------------+ +| DES | 2 | RW | 0x0 | Descriptor | +| C_CDT_WB_EN | | | | Credit | +| | | | | Write-Back | +| | | | | Trigger | +| | | | | Enable. | +| | | | | When set, | +| | | | | SDE | +| | | | | schedules a | +| | | | | status | +| | | | | counter | +| | | | | write-back | +| | | | | when | +| | | | | descriptor | +| | | | | credit | +| | | | | “limit” | +| | | | | increments. | ++-------------+-------------+----------+-------------+-------------+ +| MD_PTR_EN | 3 | RW | 0x0 | Metadata | +| | | | | Pointer | +| | | | | Write-Back | +| | | | | Trigger | +| | | | | Enable. | +| | | | | When this | +| | | | | bit is not | +| | | | | set, SDE | +| | | | | will not | +| | | | | perform | +| | | | | ring | +| | | | | occupancy | +| | | | | check (ring | +| | | | | full | +| | | | | condition) | +| | | | | i.e the SDE | +| | | | | will | +| | | | | disregard | +| | | | | the | +| | | | | Metadata | +| | | | | Read | +| | | | | Pointer | +| | | | | register. | ++-------------+-------------+----------+-------------+-------------+ +| DES | 4 | RW | 0x0 | Descriptor | +| C_CDT_WC_EN | | | | Credit | +| | | | | “Limit” | +| | | | | Write-Back | +| | | | | Coalesce | +| | | | | Enable | ++-------------+-------------+----------+-------------+-------------+ +| DES | 5 | RW | 0x0 | Descriptor | +| C_CNT_WC_EN | | | | Count | +| | | | | Write-Back | +| | | | | Coalesce | +| | | | | Enable | ++-------------+-------------+----------+-------------+-------------+ +| PK | 6 | RW | 0x0 | Packet | +| T_CNT_WC_EN | | | | Count | +| | | | | Write-Back | +| | | | | Coalesce | +| | | | | Enable | ++-------------+-------------+----------+-------------+-------------+ +| MD_W | 7 | RW | 0x0 | Metadata | +| R_PTR_WC_EN | | | | Write | +| | | | | Pointer | +| | | | | Write-Back | +| | | | | Coalesce | +| | | | | Enable | ++-------------+-------------+----------+-------------+-------------+ +| WC | 13:8 | RW | 0x0 | Write-Back | +| _CNT_MINUS1 | | | | Coalesce | +| | | | | Count Minus | +| | | | | 1. Number | +| | | | | of writes | +| | | | | to | +| | | | | coalesce. | ++-------------+-------------+----------+-------------+-------------+ +| RSVD | 31:14 | RO | 0x0 | Reserved | ++-------------+-------------+----------+-------------+-------------+ + +2. **Status Counters Base Address Low** + + Address – PCIS_BASE_ADDR + 0x3704 + + CSR Offset – CSR_BASE_ADDR + 0x704 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x304 + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| STATUS | 31:0 | RW | 0x0 | Status | +| _WB_ADDR_LO | | | | Counters | +| | | | | Base | +| | | | | Address | +| | | | | [31:0] This | +| | | | | address | +| | | | | should be | +| | | | | 64B | +| | | | | aligned. | +| | | | | The least | +| | | | | significant | +| | | | | 6 bits of | +| | | | | the address | +| | | | | should 0. | ++-------------+-------------+----------+-------------+-------------+ + +3. **Status Write-Back Address High** + + Address – PCIS_BASE_ADDR + 0x3708 + + CSR Offset – CSR_BASE_ADDR + 0x708 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x308 + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| STATUS | 15:0 | RW | 0x0 | Status | +| _WB_ADDR_HI | | | | Counters | +| | | | | Base | +| | | | | Address | +| | | | | [47:32] | ++-------------+-------------+----------+-------------+-------------+ +| RSVD | 31:16 | RO | 0x0 | Reserved | ++-------------+-------------+----------+-------------+-------------+ + +4. **Write-Back Coalesce Timeout Count** + + Address – PCIS_BASE_ADDR + 0x370C + + CSR Offset – CSR_BASE_ADDR + 0x70C + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x30C + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| WC_ | 19:0 | RW | 0x0 | Write-Back | +| TO_TICK_CNT | | | | Coalesce | +| | | | | Timeout | +| | | | | Tick Count | ++-------------+-------------+----------+-------------+-------------+ +| WC_TO_CNT | 23:20 | RW | 0x0 | Write-Back | +| | | | | Coalesce | +| | | | | Timeout | +| | | | | Count | ++-------------+-------------+----------+-------------+-------------+ +| RSVD | 31:24 | RO | 0x0 | Reserved | ++-------------+-------------+----------+-------------+-------------+ + +5. **Metadata Ring Base Address Low** + + Address – PCIS_BASE_ADDR + 0x3718 + + CSR Offset – CSR_BASE_ADDR + 0x718 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x318 + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| MD | 31:0 | RW | 0x0 | Metadata | +| _WB_ADDR_LO | | | | Ring Base | +| | | | | Address | +| | | | | [31:0] This | +| | | | | address | +| | | | | should be | +| | | | | 64B | +| | | | | aligned. | +| | | | | The least | +| | | | | significant | +| | | | | 6 bits of | +| | | | | the address | +| | | | | should 0. | ++-------------+-------------+----------+-------------+-------------+ + +6. **Metadata Ring Base Address High** + + Address – PCIS_BASE_ADDR + 0x371C + + CSR Offset – CSR_BASE_ADDR + 0x71C + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x31C + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| MD | 15:0 | RW | 0x0 | Metadata | +| _WB_ADDR_HI | | | | Ring Base | +| | | | | Address | +| | | | | [47:32] | ++-------------+-------------+----------+-------------+-------------+ +| RSVD | 31:16 | RO | 0x0 | Reserved | ++-------------+-------------+----------+-------------+-------------+ + +7. **Metadata Ring Size** + + Address – PCIS_BASE_ADDR + 0x3720 + + CSR Offset – CSR_BASE_ADDR + 0x720 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x320 + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| MD_RING | 31:0 | RW | 0x0 | Metadata | +| _SIZE_BYTES | | | | Ring Size | +| | | | | (in Bytes). | +| | | | | Should be | +| | | | | integer | +| | | | | multiple of | +| | | | | Metadata | +| | | | | Size (in | +| | | | | Bytes). The | +| | | | | maximum | +| | | | | number of | +| | | | | descriptors | +| | | | | in the ring | +| | | | | is 65536 | +| | | | | and minimum | +| | | | | number of | +| | | | | descriptors | +| | | | | in the ring | +| | | | | is 2. For | +| | | | | Regular | +| | | | | Type | +| | | | | metadata, | +| | | | | the maximum | +| | | | | Metadata | +| | | | | ring size | +| | | | | is 1MB. For | +| | | | | Compact | +| | | | | Type | +| | | | | metadata, | +| | | | | the maximum | +| | | | | Metadata | +| | | | | ring size | +| | | | | is 512KB. | ++-------------+-------------+----------+-------------+-------------+ + +8. **Metadata Ring Read Pointer** + + Address – PCIS_BASE_ADDR + 0x3724 + + CSR Offset – CSR_BASE_ADDR + 0x724 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x324 + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| MD_RD_PTR | 15:0 | RW | 0x0 | Metadata | +| | | | | Ring Read | +| | | | | Pointer | ++-------------+-------------+----------+-------------+-------------+ +| RSVD | 31:16 | RO | 0x0 | Reserved | ++-------------+-------------+----------+-------------+-------------+ + +9. **Metadata Ring Write Pointer** + + Address – PCIS_BASE_ADDR + 0x3728 + + CSR Offset – CSR_BASE_ADDR + 0x728 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x328 + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| MD_WR_PTR | 15:0 | RW0C | 0x0 | Metadata | +| | | | | Ring Write | +| | | | | Pointer. | +| | | | | Write 0 to | +| | | | | clear. | ++-------------+-------------+----------+-------------+-------------+ +| RSVD | 31:16 | RO | 0x0 | Reserved | ++-------------+-------------+----------+-------------+-------------+ + +10. **Write Back Status Register** + + Address – PCIS_BASE_ADDR + 0x372C + + CSR Offset – CSR_BASE_ADDR + 0x72C + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x32C + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| WB_STS_ | 0 | RW1C | 0x0 | Write Back | +| BRESP_ERROR | | | | BRESP Error | +| | | | | for Status | +| | | | | Write-Back | ++-------------+-------------+----------+-------------+-------------+ +| WB_MD_ | 1 | RW1C | 0x0 | Write Back | +| BRESP_ERROR | | | | BRESP Error | +| | | | | for | +| | | | | Metadata | +| | | | | Write-Back | ++-------------+-------------+----------+-------------+-------------+ +| RSVD | 31:2 | RO | 0x0 | Reserved | ++-------------+-------------+----------+-------------+-------------+ + +11. **Status DW Register** + + Address – PCIS_BASE_ADDR + 0x3730 + + CSR Offset – CSR_BASE_ADDR + 0x730 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x330 + +============== ============= ======== ================= ================ +**Field Name** **Bit Range** **Type** **Default Value** **Description** +============== ============= ======== ================= ================ +DESC_ERROR 0 RO 0x0 Descriptor Error +DM_ERROR 1 RO 0x0 Data Mover Error +WB_ERROR 2 RO 0x0 Write Back Error +RSVD 31:3 RO 0x0 Reserved +============== ============= ======== ================= ================ + +C2H Buffer CSRs +--------------- + +1. **Buffer Config Register 0** + + Address – PCIS_BASE_ADDR + 0x3800 + + CSR Offset – CSR_BASE_ADDR + 0x800 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x400 + +============== ============= ======== ================= =============== +**Field Name** **Bit Range** **Type** **Default Value** **Description** +============== ============= ======== ================= =============== +RSVD 31:0 RW 0x0 Reserved +============== ============= ======== ================= =============== + +2. **Buffer Status Register** + + Address – PCIS_BASE_ADDR + 0x3804 + + CSR Offset – CSR_BASE_ADDR + 0x804 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x404 + +============== ============= ======== ================= =============== +**Field Name** **Bit Range** **Type** **Default Value** **Description** +============== ============= ======== ================= =============== +BUF_FULL 0 RO 0x0 Buffer Full +BUF_EMPTY 1 RO 0x0 Buffer Empty +AUX_FIFO_FULL 2 RO 0x0 Aux FIFO Full +AUX_FIFO_EMPTY 3 RO 0x0 Aux FIFO Empty +RSVD 31:4 RO 0x0 Reserved +============== ============= ======== ================= =============== + +3. **Buffer Input Packet Count Register** + + Address – PCIS_BASE_ADDR + 0x3808 + + CSR Offset – CSR_BASE_ADDR + 0x808 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x408 + ++----------------+---------------+----------+-------------------+--------------------+ +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | ++================+===============+==========+===================+====================+ +| IN_PKT_CNT | 31:0 | RW0C | 0x0 | Input Packet Count | ++----------------+---------------+----------+-------------------+--------------------+ + +4. **Buffer Output Packet Count Register** + + Address – PCIS_BASE_ADDR + 0x380C + + CSR Offset – CSR_BASE_ADDR + 0x80C + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x40C + ++----------------+---------------+----------+-------------------+---------------------+ +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | ++================+===============+==========+===================+=====================+ +| OUT_PKT_CNT | 31:0 | RW0C | 0x0 | Output Packet Count | ++----------------+---------------+----------+-------------------+---------------------+ + +5. **Buffer Pointer Register** + + Address – PCIS_BASE_ADDR + 0x3810 + + CSR Offset – CSR_BASE_ADDR + 0x810 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x410 + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| BUF_WR_PTR | 15:0 | RO | 0x0 | Buffer | +| | | | | Write | +| | | | | Pointer | +| | | | | (RAM entry | +| | | | | based) | ++-------------+-------------+----------+-------------+-------------+ +| BUF_RD_ADDR | 31:16 | RO | 0x0 | Buffer Read | +| | | | | Address | +| | | | | (Byte | +| | | | | based) | ++-------------+-------------+----------+-------------+-------------+ + +6. **Aux RAM Pointers** + + Address – PCIS_BASE_ADDR + 0x3814 + + CSR Offset – CSR_BASE_ADDR + 0x814 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x414 + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| AUX | 14:0 | RO | 0x0 | Aux RAM | +| _RAM_WR_PTR | | | | Write | +| | | | | Pointer | ++-------------+-------------+----------+-------------+-------------+ +| AUX_RAM | 15 | RO | 0x0 | Aux RAM | +| _WR_PTR_MSB | | | | Write | +| | | | | Pointer MSB | ++-------------+-------------+----------+-------------+-------------+ +| AUX | 30:16 | RO | 0x0 | Aux RAM | +| _RAM_RD_PTR | | | | Read | +| | | | | Pointer | ++-------------+-------------+----------+-------------+-------------+ +| AUX_RAM | 31 | RO | 0x0 | Aux RAM | +| _RD_PTR_MSB | | | | Read | +| | | | | Pointer MSB | ++-------------+-------------+----------+-------------+-------------+ + +7. **Number of Bytes in Buffer Register** + + Address – PCIS_BASE_ADDR + 0x3818 + + CSR Offset – CSR_BASE_ADDR + 0x818 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x418 + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| NUM_BYTES | 15:0 | RO | 0x0 | Number of | +| | | | | Bytes in | +| | | | | Buffer When | +| | | | | Aux FIFO is | +| | | | | valid, this | +| | | | | is the | +| | | | | number of | +| | | | | bytes until | +| | | | | end of | +| | | | | current | +| | | | | packet When | +| | | | | Aux FIFO is | +| | | | | not valid, | +| | | | | this is the | +| | | | | number of | +| | | | | bytes in | +| | | | | the buffer | ++-------------+-------------+----------+-------------+-------------+ +| RSVD | 31:16 | RO | 0x0 | Reserved | ++-------------+-------------+----------+-------------+-------------+ + +C2H AXI-Stream CSRs +------------------- + +1. **Packet Count** + + Address – PCIS_BASE_ADDR + 0x3900 + + CSR Offset – CSR_BASE_ADDR + 0x900 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x500 + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| PKT_CNT | 31:0 | RW0C | 0x0 | Number of | +| | | | | packets | +| | | | | transmitted | +| | | | | on the AXIS | +| | | | | interface. | +| | | | | Increments | +| | | | | after | +| | | | | t | +| | | | | ransmitting | +| | | | | an EOP. | +| | | | | Write 0 to | +| | | | | clear. | ++-------------+-------------+----------+-------------+-------------+ + +H2C CSRs +-------- + +H2C CSR Address Mapping +----------------------- + ++----------------+----------------+----------------+----------------+ +| **Range** | **Size | **Name** | * | +| | (Bytes)** | | *Description** | ++================+================+================+================+ +| 0x3A00 – | 256 | H2C Global | H2C Global | +| 0x3AFC | | CSRs | Config and | +| | | | Status | +| | | | Registers | ++----------------+----------------+----------------+----------------+ +| 0x3B00 – | 256 | H2C Descriptor | H2C Descriptor | +| 0x3BFC | | CSRs | Config and | +| | | | Status | +| | | | Registers | ++----------------+----------------+----------------+----------------+ +| 0x3C00 – | 256 | H2C Data Mover | H2C Data Mover | +| 0x3CFC | | CSRs | Config and | +| | | | Status | +| | | | Registers | ++----------------+----------------+----------------+----------------+ +| 0x3D00 – | 256 | H2C Write-back | H2C Write-Back | +| 0x3DFC | | CSRs | Config and | +| | | | Status | +| | | | Registers | ++----------------+----------------+----------------+----------------+ +| 0x3E00 – | 256 | H2C Buffer | H2C Buffer | +| 0x3EFC | | CSRs | Config and | +| | | | Status | +| | | | Registers | ++----------------+----------------+----------------+----------------+ +| 0x3F00 – | 256 | H2C AXIS CSRs | H2C AXI-Stream | +| 0x3FFC | | | Config and | +| | | | Status | +| | | | Registers | ++----------------+----------------+----------------+----------------+ + +H2C Global CSRs +--------------- + +RSVD for future use + +H2C Descriptor CSRs +------------------- + +1. **Descriptor Credit Consumed Counter** + + Address – PCIS_BASE_ADDR + 0x3B00 + + CSR Offset – CSR_BASE_ADDR + 0xB00 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x100 + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| C | 31:0 | RW0C | 0x0 | Descriptor | +| DT_CONSUMED | | | | Credit | +| | | | | Consumed | +| | | | | Counter. | +| | | | | Write 0 to | +| | | | | clear. | ++-------------+-------------+----------+-------------+-------------+ + +2. **Descriptor Credit Limit Counter** + + Address – PCIS_BASE_ADDR + 0x3B04 + + CSR Offset – CSR_BASE_ADDR + 0xB04 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x104 + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| CDT_LIMIT | 31:0 | RW0C | H2C_DES | Descriptor | +| | | | C_RAM_DEPTH | Credit | +| | | | | Limit | +| | | | | Counter. | +| | | | | Write 0 to | +| | | | | clear. When | +| | | | | cleared, | +| | | | | the value | +| | | | | of the | +| | | | | counter is | +| | | | | reset to | +| | | | | H2C_DESC | +| | | | | _RAM_DEPTH. | ++-------------+-------------+----------+-------------+-------------+ + +3. **Completed Descriptors Counter** + + Address – PCIS_BASE_ADDR + 0x3B08 + + CSR Offset – CSR_BASE_ADDR + 0xB08 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x108 + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| COMP_COUNT | 31:0 | RW0C | 0x0 | Completed | +| | | | | Descriptor | +| | | | | Counter. | +| | | | | Write 0 to | +| | | | | clear. | ++-------------+-------------+----------+-------------+-------------+ + +4. **Descriptor FIFO Pointers** + + Address – PCIS_BASE_ADDR + 0x3B0C + + CSR Offset – CSR_BASE_ADDR + 0xB0C + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x10C + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| FIFO_WR_PTR | 14:0 | RO | 0x0 | Descriptor | +| | | | | FIFO Write | +| | | | | Pointer | ++-------------+-------------+----------+-------------+-------------+ +| FIFO | 15 | RO | 0x0 | Descriptor | +| _WR_PTR_MSB | | | | FIFO Write | +| | | | | Pointer MSB | ++-------------+-------------+----------+-------------+-------------+ +| FIFO_RD_PTR | 30:16 | RO | 0x0 | Descriptor | +| | | | | FIFO Read | +| | | | | Pointer | ++-------------+-------------+----------+-------------+-------------+ +| FIFO | 31 | RO | 0x0 | Descriptor | +| _RD_PTR_MSB | | | | FIFO Read | +| | | | | Pointer MSB | ++-------------+-------------+----------+-------------+-------------+ + +5. **Descriptor RAM Address** + + Address – PCIS_BASE_ADDR + 0x3B10 + + CSR Offset – CSR_BASE_ADDR + 0xB10 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x110 + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| DE | 15:0 | RW | 0x0 | Descriptor | +| SC_RAM_ADDR | | | | RAM Address | ++-------------+-------------+----------+-------------+-------------+ +| DESC | 19:16 | RWC | 0x0 | Descriptor | +| _RAM_DW_IDX | | | | RAM Data DW | +| | | | | Index. This | +| | | | | bitfield is | +| | | | | cleared | +| | | | | when this | +| | | | | register is | +| | | | | written. | +| | | | | This will | +| | | | | aut | +| | | | | o-increment | +| | | | | when | +| | | | | DE | +| | | | | SC_RAM_DATA | +| | | | | is read or | +| | | | | written. | ++-------------+-------------+----------+-------------+-------------+ +| RSVD | 31:20 | RO | 0x0 | Reserved | ++-------------+-------------+----------+-------------+-------------+ + +6. **Descriptor RAM Data** + + Address – PCIS_BASE_ADDR + 0x3B14 + + CSR Offset – CSR_BASE_ADDR + 0xB14 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x114 + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| DESC_ | 31:0 | RW | 0x0 | Descriptor | +| RAM_DATA_DW | | | | RAM Data. | +| | | | | When | +| | | | | writing the | +| | | | | descriptor | +| | | | | RAM, SDE | +| | | | | initiates a | +| | | | | write to | +| | | | | the | +| | | | | descriptor | +| | | | | RAM after | +| | | | | all the DWs | +| | | | | that make | +| | | | | up the | +| | | | | descriptor | +| | | | | are written | +| | | | | to this | +| | | | | register. | +| | | | | When | +| | | | | reading the | +| | | | | descriptor | +| | | | | RAM, SDE | +| | | | | initiates a | +| | | | | read from | +| | | | | the | +| | | | | descriptor | +| | | | | RAM when | +| | | | | this | +| | | | | register is | +| | | | | read and | +| | | | | when the | +| | | | | DESC | +| | | | | _RAM_DW_IDX | +| | | | | is 0. | ++-------------+-------------+----------+-------------+-------------+ + +7. **Descriptor RAM Status** + + Address – PCIS_BASE_ADDR + 0x3B18 + + CSR Offset – CSR_BASE_ADDR + 0xB18 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x118 + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| DESC_OFLOW | 0 | RW1C | 0x0 | Desc RAM | +| | | | | Overflow | +| | | | | Indicates | +| | | | | that a | +| | | | | descriptor | +| | | | | was written | +| | | | | when the | +| | | | | descriptor | +| | | | | RAM is full | ++-------------+-------------+----------+-------------+-------------+ +| DES | 1 | RW1C | 0x0 | Desc Out of | +| C_OOO_ERROR | | | | Order Error | ++-------------+-------------+----------+-------------+-------------+ +| DESC_U | 2 | RW1C | 0x0 | Desc | +| NALIN_ERROR | | | | Unaligned | +| | | | | Address | +| | | | | Error | ++-------------+-------------+----------+-------------+-------------+ +| DESC_FULL | 3 | RO | 0x0 | Desc RAM | +| | | | | Full | ++-------------+-------------+----------+-------------+-------------+ +| DESC_EMPTY | 4 | RO | 0x0 | Desc RAM | +| | | | | Empty | ++-------------+-------------+----------+-------------+-------------+ +| RSVD | 31:1 | RO | 0x0 | Reserved | ++-------------+-------------+----------+-------------+-------------+ + +8. **Descriptor Info** + + Address – PCIS_BASE_ADDR + 0x3B20 + + CSR Offset – CSR_BASE_ADDR + 0xB20 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x120 + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| DESC_TYPE | 0 | RO | 0x0 | Descriptor | +| | | | | /Write-Back | +| | | | | Type 0 – | +| | | | | Regular 1 – | +| | | | | Compact | ++-------------+-------------+----------+-------------+-------------+ +| RSVD | 15:1 | RO | 0x0 | RSVD | ++-------------+-------------+----------+-------------+-------------+ +| DES | 31:16 | RO | 0x0 | Descriptor | +| C_RAM_DEPTH | | | | RAM Depth. | +| | | | | Maximum | +| | | | | Number of | +| | | | | d | +| | | | | escriptors. | ++-------------+-------------+----------+-------------+-------------+ + +H2C Data Mover CSRs +------------------- + +1. **Data Mover Config Register 0** + + Address – PCIS_BASE_ADDR + 0x3C00 + + CSR Offset – CSR_BASE_ADDR + 0xC00 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x200 + +============== ============= ======== ================= =============== +**Field Name** **Bit Range** **Type** **Default Value** **Description** +============== ============= ======== ================= =============== +RSVD 31:0 RW 0x0 Reserved +============== ============= ======== ================= =============== + +2. **Data Mover Status Register** + + Address – PCIS_BASE_ADDR + 0x3C04 + + CSR Offset – CSR_BASE_ADDR + 0xC04 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x204 + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| D | 0 | RW1C | 0x0 | Data Mover | +| M_RRESP_ERR | | | | Rresp Error | ++-------------+-------------+----------+-------------+-------------+ +| DM_D | 1 | RW1C | 0x0 | Descriptor | +| ESC_LEN_ERR | | | | Length | +| | | | | equal to 0 | ++-------------+-------------+----------+-------------+-------------+ +| RSVD | 31:2 | RO | 0x0 | Reserved | ++-------------+-------------+----------+-------------+-------------+ + +H2C Write-Back CSRs +------------------- + +1. **Write-Back Config Register 0** + + Address – PCIS_BASE_ADDR + 0x3D00 + + CSR Offset – CSR_BASE_ADDR + 0xD00 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x300 + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| DES | 0 | RW | 0x0 | Descriptor | +| C_CNT_WB_EN | | | | Count | +| | | | | Write-Back | +| | | | | Trigger | +| | | | | Enable. | +| | | | | When set, | +| | | | | SDE | +| | | | | schedules a | +| | | | | status | +| | | | | counter | +| | | | | write-back | +| | | | | when | +| | | | | descriptor | +| | | | | count | +| | | | | increments | ++-------------+-------------+----------+-------------+-------------+ +| PK | 1 | RW | 0x0 | Packet | +| T_CNT_WB_EN | | | | Count | +| | | | | Write-Back | +| | | | | Trigger | +| | | | | Enable. | +| | | | | When set, | +| | | | | SDE | +| | | | | schedules a | +| | | | | status | +| | | | | counter | +| | | | | write-back | +| | | | | when packet | +| | | | | count | +| | | | | increments. | ++-------------+-------------+----------+-------------+-------------+ +| DES | 2 | RW | 0x0 | Descriptor | +| C_CDT_WB_EN | | | | Credit | +| | | | | Write-Back | +| | | | | Trigger | +| | | | | Enable. | +| | | | | When set, | +| | | | | SDE | +| | | | | schedules a | +| | | | | status | +| | | | | counter | +| | | | | write-back | +| | | | | when | +| | | | | descriptor | +| | | | | credit | +| | | | | “limit” | +| | | | | increments. | ++-------------+-------------+----------+-------------+-------------+ +| RSVD | 3 | RO | 0x0 | Reserved | ++-------------+-------------+----------+-------------+-------------+ +| DES | 4 | RW | 0x0 | Descriptor | +| C_CDT_WC_EN | | | | Credit | +| | | | | “Limit” | +| | | | | Write-Back | +| | | | | Coalesce | +| | | | | Enable | ++-------------+-------------+----------+-------------+-------------+ +| DES | 5 | RW | 0x0 | Descriptor | +| C_CNT_WC_EN | | | | Count | +| | | | | Write-Back | +| | | | | Coalesce | +| | | | | Enable. | ++-------------+-------------+----------+-------------+-------------+ +| PK | 6 | RW | 0x0 | Packet | +| T_CNT_WC_EN | | | | Count | +| | | | | Write-Back | +| | | | | Coalesce | +| | | | | Enable | ++-------------+-------------+----------+-------------+-------------+ +| RSVD | 7 | RO | 0x0 | Reserved | ++-------------+-------------+----------+-------------+-------------+ +| WC | 13:8 | RW | 0x0 | Write-Back | +| _CNT_MINUS1 | | | | Coalesce | +| | | | | Count Minus | +| | | | | 1. Number | +| | | | | of writes | +| | | | | to | +| | | | | coalesce. | ++-------------+-------------+----------+-------------+-------------+ +| RSVD | 31:14 | RO | 0x0 | Reserved | ++-------------+-------------+----------+-------------+-------------+ + +2. **Status Counters Base Address Low** + + Address – PCIS_BASE_ADDR + 0x3D04 + + CSR Offset – CSR_BASE_ADDR + 0xD04 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x304 + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| STATUS | 31:0 | RW | 0x0 | Status | +| _WB_ADDR_LO | | | | Counters | +| | | | | Base | +| | | | | Address | +| | | | | [31:0] This | +| | | | | address | +| | | | | should be | +| | | | | 64B | +| | | | | aligned. | +| | | | | The least | +| | | | | significant | +| | | | | 6 bits of | +| | | | | the address | +| | | | | should 0. | ++-------------+-------------+----------+-------------+-------------+ + +3. **Status Write-Back Address High** + + Address – PCIS_BASE_ADDR + 0x3D08 + + CSR Offset – CSR_BASE_ADDR + 0xD08 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x308 + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| STATUS | 15:0 | RW | 0x0 | Status | +| _WB_ADDR_HI | | | | Counters | +| | | | | Base | +| | | | | Address | +| | | | | [47:32] | ++-------------+-------------+----------+-------------+-------------+ +| RSVD | 31:16 | RO | 0x0 | Reserved | ++-------------+-------------+----------+-------------+-------------+ + +4. **Write-Back Coalesce Timeout Count** + + Address – PCIS_BASE_ADDR + 0x3D0C + + CSR Offset – CSR_BASE_ADDR + 0xD0C + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x30C + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| WC_ | 19:0 | RW | 0x0 | Write-Back | +| TO_TICK_CNT | | | | Coalesce | +| | | | | Timeout | +| | | | | Tick Count | ++-------------+-------------+----------+-------------+-------------+ +| WC_TO_CNT | 23:20 | RW | 0x0 | Write-Back | +| | | | | Coalesce | +| | | | | Timeout | +| | | | | Count | ++-------------+-------------+----------+-------------+-------------+ +| RSVD | 31:24 | RO | 0x0 | Reserved | ++-------------+-------------+----------+-------------+-------------+ + +5. **Write Back Status Register** + + Address – PCIS_BASE_ADDR + 0x3D10 + + CSR Offset – CSR_BASE_ADDR + 0xD10 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x310 + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| WB_STS_ | 0 | RW1C | 0x0 | Write Back | +| BRESP_ERROR | | | | BRESP Error | +| | | | | for Status | +| | | | | Write-Back | ++-------------+-------------+----------+-------------+-------------+ +| RSVD | 31:1 | RO | 0x0 | Reserved | ++-------------+-------------+----------+-------------+-------------+ + +6. **Status DW Register** + + Address – PCIS_BASE_ADDR + 0x3D14 + + CSR Offset – CSR_BASE_ADDR + 0xD14 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x314 + +============== ============= ======== ================= ================ +**Field Name** **Bit Range** **Type** **Default Value** **Description** +============== ============= ======== ================= ================ +DESC_ERROR 0 RO 0x0 Descriptor Error +DM_ERROR 1 RO 0x0 Data Mover Error +WB_ERROR 2 RO 0x0 Write Back Error +RSVD 31:3 RO 0x0 Reserved +============== ============= ======== ================= ================ + +H2C Buffer CSRs +--------------- + +1. **Buffer Config Register 0** + + Address – PCIS_BASE_ADDR + 0x3E00 + + CSR Offset – CSR_BASE_ADDR + 0xE00 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x400 + +============== ============= ======== ================= =============== +**Field Name** **Bit Range** **Type** **Default Value** **Description** +============== ============= ======== ================= =============== +RSVD 31:0 RW 0x0 Reserved +============== ============= ======== ================= =============== + +2. **Buffer Status Register** + + Address – PCIS_BASE_ADDR + 0x3E04 + + CSR Offset – CSR_BASE_ADDR + 0xE04 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x404 + +============== ============= ======== ================= =============== +**Field Name** **Bit Range** **Type** **Default Value** **Description** +============== ============= ======== ================= =============== +BUF_FULL 0 RO 0x0 Buffer Full +BUF_EMPTY 1 RO 0x0 Buffer Empty +AUX_FIFO_FULL 2 RO 0x0 Aux FIFO Full +AUX_FIFO_EMPTY 3 RO 0x0 Aux FIFO Empty +RSVD 31:4 RO 0x0 Reserved +============== ============= ======== ================= =============== + +3. **Buffer Input Packet Count Register** + + Address – PCIS_BASE_ADDR + 0x3E08 + + CSR Offset – CSR_BASE_ADDR + 0xE08 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x408 + ++----------------+---------------+----------+-------------------+--------------------+ +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | ++================+===============+==========+===================+====================+ +| IN_PKT_CNT | 31:0 | RW0C | 0x0 | Input Packet Count | ++----------------+---------------+----------+-------------------+--------------------+ + +4. **Buffer Output Packet Count Register** + + Address – PCIS_BASE_ADDR + 0x3E0C + + CSR Offset – CSR_BASE_ADDR + 0xE0C + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x40C + ++----------------+---------------+----------+-------------------+---------------------+ +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | ++================+===============+==========+===================+=====================+ +| OUT_PKT_CNT | 31:0 | RW0C | 0x0 | Output Packet Count | ++----------------+---------------+----------+-------------------+---------------------+ + +5. **Buffer Pointer Register** + + Address – PCIS_BASE_ADDR + 0x3E10 + + CSR Offset – CSR_BASE_ADDR + 0xE10 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x410 + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| BUF_WR_PTR | 15:0 | RO | 0x0 | Buffer | +| | | | | Write | +| | | | | Pointer | +| | | | | (RAM entry | +| | | | | based) | ++-------------+-------------+----------+-------------+-------------+ +| BUF_RD_ADDR | 31:16 | RO | 0x0 | Buffer Read | +| | | | | Address | +| | | | | (Byte | +| | | | | based) | ++-------------+-------------+----------+-------------+-------------+ + +6. **Aux RAM Pointers** + + Address – PCIS_BASE_ADDR + 0x3E14 + + CSR Offset – CSR_BASE_ADDR + 0xE14 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x414 + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| AUX | 14:0 | RO | 0x0 | Aux RAM | +| _RAM_WR_PTR | | | | Write | +| | | | | Pointer | ++-------------+-------------+----------+-------------+-------------+ +| AUX_RAM | 15 | RO | 0x0 | Aux RAM | +| _WR_PTR_MSB | | | | Write | +| | | | | Pointer MSB | ++-------------+-------------+----------+-------------+-------------+ +| AUX | 30:16 | RO | 0x0 | Aux RAM | +| _RAM_RD_PTR | | | | Read | +| | | | | Pointer | ++-------------+-------------+----------+-------------+-------------+ +| AUX_RAM | 31 | RO | 0x0 | Aux RAM | +| _RD_PTR_MSB | | | | Read | +| | | | | Pointer MSB | ++-------------+-------------+----------+-------------+-------------+ + +7. **Number of Entries in Buffer Register** + + Address – PCIS_BASE_ADDR + 0x3E18 + + CSR Offset – CSR_BASE_ADDR + 0xE18 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x418 + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| NUM_F | 15:0 | RO | 0x0 | Number of | +| REE_ENTRIES | | | | Free | +| | | | | Entries in | +| | | | | Buffer RAM | ++-------------+-------------+----------+-------------+-------------+ +| RSVD | 31:16 | RO | 0x0 | Reserved | ++-------------+-------------+----------+-------------+-------------+ + +8. **Data Mover Buffer Pointer Register** + + Address – PCIS_BASE_ADDR + 0x3E1C + + CSR Offset – CSR_BASE_ADDR + 0xE1C + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x41C + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| DM | 14:0 | RO | 0x0 | Data Mover | +| _BUF_WR_PTR | | | | Buffer | +| | | | | Write | +| | | | | Pointer | ++-------------+-------------+----------+-------------+-------------+ +| DM_BUF | 15 | RO | 0x0 | Data Mover | +| _WR_PTR_MSB | | | | Buffer | +| | | | | Write | +| | | | | Pointer MSB | ++-------------+-------------+----------+-------------+-------------+ +| DM | 30:16 | RO | 0x0 | Data Mover | +| _AUX_WR_PTR | | | | Aux RAM | +| | | | | Read | +| | | | | Pointer | ++-------------+-------------+----------+-------------+-------------+ +| DM_AUX | 31 | RO | 0x0 | Data Mover | +| _WR_PTR_MSB | | | | Aux RAM | +| | | | | Read | +| | | | | Pointer MSB | ++-------------+-------------+----------+-------------+-------------+ + +H2C AXI-Stream CSRs +------------------- + +1. **Packet Count** + + Address – PCIS_BASE_ADDR + 0x3F00 + + CSR Offset – CSR_BASE_ADDR + 0xF00 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x500 + ++-------------+-------------+----------+-------------+-------------+ +| **Field | **Bit | **Type** | **Default | **De | +| Name** | Range** | | Value** | scription** | ++=============+=============+==========+=============+=============+ +| PKT_CNT | 31:0 | RW0C | 0x0 | Number of | +| | | | | packets | +| | | | | received on | +| | | | | the AXIS | +| | | | | interface. | +| | | | | Increments | +| | | | | after | +| | | | | receiving | +| | | | | an EOP. | +| | | | | Write 0 to | +| | | | | clear. | ++-------------+-------------+----------+-------------+-------------+ + +Descriptors and Write-Back Metadata +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Descriptors are used to provide all required information for the data +transfer. The software/driver is expected to provide this information to +the SDE. SDE supports two types of descriptors – Normal and compact +type. The choice of the descriptor type is static and has to be chosen +during the design of the application when the SDE is instanced in the +CL. The normal type descriptor is 256 bit wide and the compact type +descriptor is 128 bit wide. The advantage of using the compact +descriptor is the reduction in the BRAM use for the descriptor RAM in +the SDE. Write-Back Metadata is used to provide all the required +information about a completed data transfer. SDE provides this data to +the software/driver by writing to a write-back metadata ring stored in +host memory. Write-Back Metadata is only used for C2H transfers. SDE +supports two types of write-back metadata – Normal and compact type. The +choice of the write-back metadata type is static and has to be chosen +during the design of the application when the SDE is instanced in the +CL. The normal type write-back metadata is 128 bit wide and the compact +type write-back metadata is 64 bit wide. The type of the write- back +metadata will be the same as the descriptor type chosen. + +C2H Descriptor and Metadata +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +C2H Descriptor +^^^^^^^^^^^^^^ + ++---------+---------+---------+---------+---------+---------+---------+ +| ** | | * | | | ** | | +| Field** | | *Normal | | | Compact | | +| | | Type** | | | Type** | | ++=========+=========+=========+=========+=========+=========+=========+ +| | **Bit- | **High | **Low | **Bit- | **High | **Low | +| | Width** | Bit | Bit | Width** | Bit | Bit | +| | | Index** | Index** | | Index** | Index** | ++---------+---------+---------+---------+---------+---------+---------+ +| * | 32 | 31 | 0 | 32 | 31 | 0 | +| *Length | | | | | | | +| (B | | | | | | | +| ytes)** | | | | | | | ++---------+---------+---------+---------+---------+---------+---------+ +| **P | 64 | 95 | 32 | 48 | 79 | 32 | +| hysical | | | | | | | +| Ad | | | | | | | +| dress** | | | | | | | ++---------+---------+---------+---------+---------+---------+---------+ +| * | 32 | 127 | 96 | 48 | 127 | 80 | +| *RSVD** | | | | | | | ++---------+---------+---------+---------+---------+---------+---------+ +| ** | 128 | | 128 | | | | +| Total** | | | | | | | ++---------+---------+---------+---------+---------+---------+---------+ + +Description of Fields + +1) Physical Address: Destination physical address for the data. This is + the host guest physical address used by the SDE to write the packet. + For compact descriptor type, this address is 48 bits wide. +2) Length: Number of bytes for the data transfer. The minimum length is + 1 byte. +3) RSVD: These bits are used to adjust the total length of the + descriptor to 128 bits and unused in the SDE. SDE does not store + these bits in the descriptor RAM. + +C2H Write-Back Metadata +^^^^^^^^^^^^^^^^^^^^^^^ + ++---------+---------+---------+---------+---------+---------+---------+ +| ** | | * | | | ** | | +| Field** | | *Normal | | | Compact | | +| | | Type** | | | Type** | | ++=========+=========+=========+=========+=========+=========+=========+ +| | **Bit- | **High | **Low | **Bit- | **High | **Low | +| | Width** | Bit | Bit | Width** | Bit | Bit | +| | | Index** | Index** | | Index** | Index** | ++---------+---------+---------+---------+---------+---------+---------+ +| * | 32 | 31 | 0 | 32 | 31 | 0 | +| *Length | | | | | | | +| (B | | | | | | | +| ytes)** | | | | | | | ++---------+---------+---------+---------+---------+---------+---------+ +| ** | 1 | 32 | 32 | 1 | 32 | 32 | +| Valid** | | | | | | | ++---------+---------+---------+---------+---------+---------+---------+ +| **EOP** | 1 | 33 | 33 | 1 | 33 | 33 | ++---------+---------+---------+---------+---------+---------+---------+ +| * | 30 | 63 | 34 | 30 | 63 | 34 | +| *RSVD** | | | | | | | ++---------+---------+---------+---------+---------+---------+---------+ +| **User | 64 | 127 | 64 | NA | NA | NA | +| Bits** | | | | | | | ++---------+---------+---------+---------+---------+---------+---------+ +| ** | 128 | | 64 | | | | +| Total** | | | | | | | ++---------+---------+---------+---------+---------+---------+---------+ + +Description of Fields + +1. Valid: This is set to 1 when the SDE writes the write-back metadata. + +2. EOP: This indicates that the EOP was received on the AXI Streaming + interface during the data transfer for this descriptor. + +3. Length: Number of bytes of data transferred for this descriptor. + +4. User Bits: These bits are sampled on the user bus of the AXI + Streaming Interface when the EOP is asserted. + +5. RVSD: These bits are used to adjust the total length of the + write-back metadata to 128 bits and are unused in the SDE. + +H2C Descriptor +~~~~~~~~~~~~~~ + ++---------+---------+---------+---------+---------+---------+---------+ +| ** | | * | | | ** | | +| Field** | | *Normal | | | Compact | | +| | | Type** | | | Type** | | ++=========+=========+=========+=========+=========+=========+=========+ +| | **Bit- | **High | **Low | **Bit- | **High | **Low | +| | Width** | Bit | Bit | Width** | Bit | Bit | +| | | Index** | Index** | | Index** | Index** | ++---------+---------+---------+---------+---------+---------+---------+ +| * | 32 | 31 | 0 | 32 | 31 | 0 | +| *Length | | | | | | | +| (B | | | | | | | +| ytes)** | | | | | | | ++---------+---------+---------+---------+---------+---------+---------+ +| **P | 64 | 95 | 32 | 48 | 79 | 32 | +| hysical | | | | | | | +| Ad | | | | | | | +| dress** | | | | | | | ++---------+---------+---------+---------+---------+---------+---------+ +| **EOP** | 1 | NA | 96 | 1 | NA | 80 | ++---------+---------+---------+---------+---------+---------+---------+ +| **SPB** | 1 | NA | 97 | 1 | NA | 81 | ++---------+---------+---------+---------+---------+---------+---------+ +| * | 94 | 191 | 98 | 46 | 127 | 82 | +| *RSVD** | | | | | | | ++---------+---------+---------+---------+---------+---------+---------+ +| **User | 64 | 255 | 192 | NA | NA | NA | +| Bits** | | | | | | | ++---------+---------+---------+---------+---------+---------+---------+ +| ** | 256 | | 128 | | | | +| Total** | | | | | | | ++---------+---------+---------+---------+---------+---------+---------+ + +Descriptions of Fields + +1. Physical Address: Source physical address for the data. This is the + host guest physical address used by the SDE to read the packet. For + compact descriptor type, this address is 48 bits wide. This field is + not used when SPB = 1. + +2. Length: Number of bytes for the data transfer. The minimum length is + 1 byte. + +3. EOP: If bit is set, the SDE will assert the “last” signal on the last + beat of the transfer on the AXI Streaming interface. + +4. SPB: This bit indicates if the source of the packet is Small Packet + Buffer or PCIM. If this bit is set, the SDE data mover will read the + packets from SPB instead of the PCIM. + +5. User Bits: These bits are driven on the user bus of the AXI Streaming + Interface when the EOP is asserted. + +6. RSVD: These bits are used to adjust the total length of the + descriptor to 256 bits and unused in the SDE. SDE does not store + these bits in the descriptor RAM. + +Credit Mechanism +---------------- + +SDE architecture implements a credit mechanism for descriptors and for +small packet buffer. In this section, the description is provided for +descriptors but the mechanism is identical for descriptors and small +packet buffer. The credit mechanism contains two counters “consumed” and +“limit”. The difference between these two counters is the number of +available credits based on which the software can write the descriptors. +These counters are implemented as 32 bit rolling counters. These +counters are present in both the SDE and the software. However, the SDE +updates the software’s copy of the “limit” counter after the SDE reads a +descriptor from the descriptor RAM. + +1) “consumed”: This counter is implemented in the SDE and the software. + This counter is initialized to 0. When the software writes the + descriptor, software will increment its copy of this counter. When + the SDE receives this descriptor into the descriptor RAM, the SDE + will increment its copy of this counter. + +2) “limit”: This counter is implemented in the SDE. The counter is also + present in the software but the software will not change the value. + software will only use this counter to determine number of available + credits. This counter is initialized to the number of available + credits. When the SDE completes a descriptor, it will increment its + copy of this counter. It will also update the software’s copy of this + counter using the PCIM interface. + +3) “available”: This is difference between the “consumed” and the + “limit” counters. The software will compute this locally and will use + this value to determine how many descriptors can be written. + +Write-Back Mechanism +-------------------- + +Status Counter Write-Back +~~~~~~~~~~~~~~~~~~~~~~~~~ + +SDE is architect-ed to update some status counters and C2H metadata to +host memory locations. software should store status counters on +contiguous host memory locations. In order to minimize bandwidth usage, +SDE updates all status counters using a single AXI write transaction on +PCIM. All these status counters are 32 bits wide (DW) and software +should configure the status counters’ host memory base address in the +SDE during initialization. SDE updates the following counters +periodically + +1) Status DW (Offset 0x0) a. Bit 0 – Descriptor Error b. Bit 1 – Data + Mover Error c. Bit 2 – Write Back Error d. Bit 31:3 – RSVD +2) Descriptor Credit “Limit” Counter (Offset 0x4) +3) Number of completed Descriptors (Offset 0x8) +4) Packet count on the AXIS interface (Offset 0xC) +5) Metadata buffer write pointer (C2H Only) (Offset 0x10) + +The Status DW contains bits that denote error conditions in the SDE. +When errors are detected, the SDE will update SW’s copy of the Status +DW. The SW should poll its copy of the status DW periodically and take +recovery action when it reads non-zero values in the Status DW. Each bit +corresponds to a functional block that reported the error and SW should +read the respective functional block’s status register to determine the +exact error. After recovery action is taken, the SW should clear the +error flag from the functional block’s status register. When cleared, +the SDE will also update SW’s copy of the Status DW. The Status DW +should not be written by SW. + +In order to conserve bandwidth and allow for maximum bandwidth usage by +the data mover, SDE is architect-ed to coalesce updates to the status +counters except the Status DW. SDE maintains one coalesce counter for +each status counter and will coalesce the respective status counter. The +number writes to coalesce is configurable using CSRs. SDE also +implements a configurable timeout mechanism to update the status +counters if the required number of writes are not coalesced in the +timeout window. + +C2H Metadata Write-Back +~~~~~~~~~~~~~~~~~~~~~~~ + +SDE writes C2H metadata to a circular buffer that is stored in host +memory. The mechanism contains two pointers – read and write. The +pointers are present in the SDE and the software and they are used to +determine if the circular buffer is full and empty respectively. These +pointers are implemented using counters initialized to 0 and roll over +when their respective values are equal to the number of metadata entries +minus 1. + +The software should configure the circular buffer’s base address and +circular buffer size during initialization. The software should also +clear SDE’s copy of the read pointer and write pointer during +initialization. + +1) Read pointer: software increments the read pointer when it reads the + write-back metadata and software periodically updates SDE’s copy of + the read pointer using CSR memory writes. The SDE uses its copy to + determine if there is room in the circular buffer before writing + metadata. In order to provide as much bandwidth to descriptor writes, + software should keep the frequency of updating the SDE’s copy low. + +When posting descriptors, the software can optionally ensure that there +is room in the metadata ring. If no free entries are available in the +metadata ring, the SDE will keep waiting until software updates the +read-pointer. This will eventually backpressure the data mover. The +software should consider that the metadata ring is full when the value +of write pointer plus 1 is equal to the read pointer. + +2) Write pointer: SDE uses the write-pointer, metadata ring base address + and ring size to determine the address to where the metadata has to + be written. SDE increments the write pointer after the SDE writes the + metadata to host location and SDE updates software’s copy of the + write pointer by writing to host memory. The software can use the + write pointer value to determine how many valid metadata entries are + present in the circular buffer. + +Data Flow Model +--------------- + +C2H +~~~ + +1) APP: Application requests the software to move packets from the CL + by calling software provided APIs. + +2) CL: The CL streams data into the SDE’s buffer. + +3) Software: When enough descriptor credits and metadata entries are + available, software will write the descriptor (physical address of + packet buffer and length) to the SDE’s desc RAM using PF0-BAR4 and + write-combine. + +4) SDE: When the software writes the descriptors, the SDE will + increment the “consumed”. SDE’s data mover will read the descriptor + from the desc RAM. When the SDE’s data mover reads the descriptor, + SDE increments the descriptor credit “limit” counter and also + schedules an update to the software’s copy of this counter using + PCIM. + +5) Software: Software will read the “limit” and compute number of + available credits to figure out if more descriptors can be written. + +6) SDE: If there is enough data (as requested in the desc) or if there + is an EOP, SDE Data Mover initiates data transfer by issuing writes + to host on PCIM. If there is not enough data and if an EOP is not + received, data mover will wait. + +7) SDE: After the data mover completes the data transfer and if + metadata ring is not full, SDE writes the metadata (valid bit, byte + count, EOP and any user bits) to the metadata ring using PCIM. SDE + increments its copy of the metadata ring write-pointer and will also + schedule an update to software’s copy of the metadata ring + write-pointer. + +8) SDE: The SDE increments the “number of completed descriptors” + counter and metadata write pointer. The SDE also schedules an update + to software’s copy of these counters. + +9) Software: Software will poll the valid bit of the metadata to figure + out that the data transfer is complete. + +10) Software: After reading the metadata, software clears the valid bit + of the metadata that was read. Software will increment read pointer + and when required, will update SDE’s copy of the metadata ring read + pointer. Note if software ensures that metadata entries are + available before posting the descriptor, metadata pointers can be + disabled and the software is not required to update SDE’s copy of + the read pointer. + +H2C +~~~ + +1) APP: Application requests the software to move packets to the CL + using software provided APIs. + +2) Software: When enough descriptor credits are available, software + will write the descriptor (physical address of packet buffer, + length, EOP and SPB bits) to the SDE’s desc RAM using PF0-BAR4 and + write-combine. + +3) SDE: When the software writes the descriptors, the SDE will + increment the “consumed”. SDE’s data mover will read the descriptor + from the desc RAM. When the SDE’s data mover reads the descriptor, + SDE increments the descriptor credit “limit” counter and also + schedules an update to the software’s copy of this counter using + PCIM. + +4) Software: Software will read the “limit” and compute number of + available credits to figure out if more descriptors can be written. + +5) SDE: If there is enough room in the SDE buffer (as requested by the + descriptor), SDE Data Mover initiates data transfer by issuing reads + from host DRAM on PCIM. When the descriptor specifies the source of + the packet as the small-pkt buffer, the data mover will read from + small-pkt buffer instead of using PCIM. If there is not enough room + in the buffer, data mover will wait. + +6) SDE: Data mover writes the received PCIM read data to the buffer to + be streamed to the CL (for non-small packet buffer case). + +7) SDE: SDE implements a master streaming interface that reads data + from the buffer and streams it to the CL. + +8) SDE: After the data mover completes the data transfer, SDE + increments the “number of completed descriptors” counter and also + schedules an update to the software’s copy of this counter using + PCIM. + +9) Software: Software will poll its copy of “number of completed + descriptors” to figure out that data transfer is complete. + +10) Software: Software can also poll its copy of “packet count” to + figure out that a packet has been transmitted on the AXI-Stream + interface. + +Error Conditions +---------------- + +C2H Error Conditions +~~~~~~~~~~~~~~~~~~~~ + +1. Descriptor RAM Overflow: Occurs when the descriptor RAM is full and + SW writes a new descriptor + +2. Descriptor Out of Order Error: If a descriptor write is split into + multiple writes, each write should use incrementing address. If this + condition is violated, the out of order error is set. + +3. Descriptor Unaligned Error: Occurs when a non-64B aligned address is + used for writing descriptors. + +4. Data Mover BRESP Error: Occurs when a non-zero BRESP is received on + the PCIM interface for data writes + +5. Data Mover Descriptor Length Error: Occurs when data mover encounters + a descriptor with length equal to 0. + +6. Write Back BRESP Error: Occurs when a non-zero BRESP is received on + the PCIM interface for write-back writes. + +H2C Error Conditions +~~~~~~~~~~~~~~~~~~~~ + +1. Descriptor RAM Overflow: Occurs when the descriptor RAM is full and + SW writes a new descriptor + +2. Descriptor Out of Order Error: If a descriptor write is split into + multiple writes, each write should use incrementing address. If this + condition is violated, the out of order error is set. + +3. Descriptor Unaligned Error: Occurs when a non-64B aligned address is + used for writing descriptors. + +4. Data Mover RRESP Error: Occurs when a non-zero RRESP is received on + the PCIM interface for data reads + +5. Data Mover Descriptor Length Error: Occurs when data mover encounters + a descriptor with length equal to 0. + +6. Write Back BRESP Error: Occurs when a non-zero BRESP is received on + the PCIM interface for write-back writes. + +Implementation - Maximum Clock Frequency +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The SDE can be implemented at a maximum frequency of 250MHz + +Implementation - Resource Utilization +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The resource utilization for the SDE implemented at 250MHz when using 64 +descriptor RAM depth and 32KB buffers for C2H and H2C each. + +========== ========== ======= ==== ===== ======== ==== ============ +Total LUTs Logic LUTs LUTRAMs SRLs FFs RAMB2016 URAM DSP48 Blocks +========== ========== ======= ==== ===== ======== ==== ============ +36330 35672 658 0 23525 15 0 0 +========== ========== ======= ==== ===== ======== ==== ============ + +Example Design +-------------- + +AWS provides an example CL called CL_SDE. CL_SDE instances the SDE and +some utility and test blocks to demonstrate the functionality of the +SDE. See `CL_SDE <../../../../hdk/cl/examples/cl_sde/>`__ for details. + +FAQ +--- + +Q: What is the maximum number of full duplex channels per instance of SDE? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +One instance of SDE will provide one full duplex channel (one C2H and +one H2C). + +.. _q-my-application-does-not-need-c2h-i-only-need-h2c-how-can-this-be-done: + +Q: My application does not need C2H. I only need H2C. How can this be done? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Design parameters C2H_ONLY and H2C_ONLY can be used to get what is +required and avoid unwanted logic. For example, if only C2H is required, +C2H_ONLY should be 1 so that H2C logic is avoided. + +.. _q-my-application-needs-more-than-one-full-duplex-channel-how-can-this-be-achieved: + +Q. My application needs more than one full duplex channel. How can this be achieved? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +With the current version of the SDE, if more than 1 full duplex channel +is needed, multiple SDEs have to be instanced and AXI crossbars have to +be used to connect the PCIS and PCIM buses to/from the corresponding +SDEs. Similarly, if more than 1 C2H or more than 1 H2C channel is +required, multiple SDEs have to be used. + +.. _q-is-there-a-maximum-number-of-sdes-that-can-be-instanced-in-a-cl: + +Q. Is there a maximum number of SDEs that can be instanced in a CL? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +There is no theoretical maximum. There is a practical limitation based +on the number of resources in the CL. + +.. _q-what-kind-of-softwaredriver-is-required-to-use-the-sde: + +Q. What kind of software/Driver is required to use the SDE. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +A userspace or kernel poll-mode driver is required to use the SDE. + +.. _q-does-aws-have-any-example-driverapplication: + +Q. Does AWS have any example Driver/Application? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +AWS provides DPDK based Virtual Ethernet application described +`here <./Virtual_Ethernet_Application_Guide.md>`__. + +.. _q-does-sde-supports-interrupts: + +Q. Does SDE supports interrupts? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Interrupts are not supported by the SDE. + +.. _q-my-application-needs-more-descriptors-in-the-sde-how-can-i-achieve-this: + +Q. My application needs more descriptors in the SDE? How can I achieve this? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Parameters C2H_DESC_RAM_DEPTH and H2C_DESC_RAM_DEPTH can be used to +increase the number of descriptors that can be stored in the SDE. Note +that this will increase BRAM usage in the SDE. + +.. _q-how-can-i-change-the-size-of-the-h2c-and-c2h-buffers: + +Q. How can I change the size of the H2C and C2H buffers? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Parameters C2H_BUF_DEPTH and H2C_BUF_DEPTH can be used to change the +size of the main packet buffers for C2H and H2C respectively. + +.. _q-what-is-the-guideline-for-choosing-buffer-sizes: + +Q. What is the guideline for choosing buffer sizes? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The H2C buffer should be sized according to the bandwidth requirements. +Having a very small H2C buffer will cause the SDE to reduce the +effective number of outstanding PCIM reads leading to host DRAM +latencies getting manifested on the H2C AXI-S interface, leading to +reduced H2C bandwidth. AWS has observed that 32KB buffer is sufficient +to maximize H2C throughput assuming average DRAM latency of 2us and +PCI-E BW of 16GB/s. The C2H buffer should be sized according to CL +resource availability and latency requirements. Assuming 4KB PCIM +writes, AWS recommends at least a size of 16KB C2H buffer to maximize +C2H BW. + +.. _q-my-application-needs-more-than--less-than-64-user-bits-how-can-this-be-achieved: + +Q. My application needs more than / less than 64 user bits. How can this be achieved? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +In the current version of the SDE, User bit width cannot be changed. +Therefore, parameters C2H_USER_BIT_WIDTH and H2C_USER_BIT_WIDTH should +not be changed. If more user bits are required, they will have to be +embedded in the payload of the packet (For example, preamble or appended +at the end of the packet). + +.. _q-can-i-use-write-combine-to-write-multiple-descriptors-per-clock: + +Q. Can I use write-combine to write multiple descriptors per clock? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Traditional Write-combine, explained +`here `__, +routinely causes the CPU to generate out of order writes to the +descriptor address range. SDE does not support out of order writes to +the descriptor range. Therefore, x86 intrinsic load/store instructions +should be used to write descriptors in order. + +.. _q-what-is-the-maximum-throughput-of-the-sde: + +Q. What is the maximum throughput of the SDE? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The maximum throughput for H2C is 12 GB/s and the maximum throughput for +C2h is 12.4 GB/s. + +.. _q-what-is-the-minimum-packet-size-required-for-maximum-throughput: + +Q. What is the minimum packet size required for maximum throughput? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +4KB is the minimum packet size required for maximum throughput. + +.. _q-my-application-uses-pcis-and-pcim-interfaces-for-other-purposes-in-the-cl-can-i-still-use-the-sde: + +Q. My application uses PCIS and PCIM interfaces for other purposes in the CL. Can I still use the SDE? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Yes, the SDE can still be used. However, appropriate AXI +Crossbars/Fabric needs to be used in the CL in order to provide +connectivity for PCIS and PCIM buses to the SDE. Additionally, address +and ARID/AWIDs should be appropriately configured/parameterized in the +software and the SDE respectively. + +.. _q-my-acceleratorcl-cannot-transmitreceive-data-at-512bits-per-clock-can-sde-transmitreceive-less-than-512-bits-per-clock-on-the-h2cc2h-streaming-interfaces: + +Q. My accelerator/CL cannot transmit/receive data at 512bits per clock. Can SDE transmit/receive less than 512 bits per clock on the H2C/C2H Streaming Interfaces? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The current version of the SDE can only transmit/receive data at 512 +bits per clock. The CL developer can use Xilinx AXI-S width converters +to achieve width conversion from any bit width to 512 bits. + +.. _q-what-is-the-guideline-for-choosing-between-regular-and-compact-descriptormetadata-types: + +Q. What is the guideline for choosing between Regular and Compact Descriptor/Metadata types? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Regular Descriptor/Metadata will provide 64 bits for host address and +also provide 64 bits for User bits. Compact Descriptor/Metadata will +provide only 48 bits for host address and does not provide any user +bits. Using the compact type will save PCIS bandwidth for descriptor +writes, save PCIM bandwidth for Metadata writes and save BRAM space in +the SDE. Therefore, the compact type should be chosen when user bits are +not required and also to maximize bandwidth usage for packet data and to +save BRAM utilization in the CL. + +.. _q-how-many-clocks-and-resets-does-the-sde-use: + +Q. How many clocks and resets does the SDE use? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The SDE uses only one clock. The SDE uses only one reset that is +synchronized to the aforementioned clock. + +.. _q-can-the-sde-be-implemented-at-a-clock-frequency-greater-than-250mhz: + +Q. Can the SDE be implemented at a clock frequency greater than 250MHz? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +AWS only supports SDE implemented at a maximum of 250MHz. + +.. _q-should-the-sde-be-constrained-to-a-single-slr: + +Q. Should the SDE be constrained to a single SLR? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +AWS recommends that the all the logic in the SDE be constrained to a +single SLR. Additionally, AWS recommends adding pipelining on the PCIM +and PCIS interfaces from the shell leading up to the SDE. + +.. |alt tag| image:: ../images/SDE_Block_Diagram.jpg diff --git a/docs-rtd/source/sdk/apps/virtual-ethernet/doc/Virtual_Ethernet_Application_Guide.rst b/docs-rtd/source/sdk/apps/virtual-ethernet/doc/Virtual_Ethernet_Application_Guide.rst new file mode 100644 index 000000000..25fe757b8 --- /dev/null +++ b/docs-rtd/source/sdk/apps/virtual-ethernet/doc/Virtual_Ethernet_Application_Guide.rst @@ -0,0 +1,301 @@ +Virtual Ethernet Application Guide +================================== + +Table of Contents: +------------------ + +- `Overview <#Overview>`__ + +- `Example Workflows <#ExampleWorkflows>`__ + + - `"Hello World" Loopback <#HelloWorldLoopback>`__ + +- `FAQ <#FAQ>`__ + +Overview +-------- + +The Virtual Ethernet architecture (`here <../README.md>`__) supports +your development phases with sample applications that include loopback +paths for bringup and debug of the Virtual Ethernet application and +custom CL, all the way to end-to-end application integration with live +traffic. + +Virtual Ethernet Application Setup and Use +------------------------------------------ + +The distinct phases of Virtual Ethernet Application setup and use are: + +- Software installation and build +- System setup and device binding (e.g. FPGA and ENI) +- Application setup and start + +The next sections walk through the setup and usage phases including +example workflows. + +Example Workflows +----------------- + +"Hello World" DPDK testpmd loopback mode, auto-start +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This example maximizes PPS for 64B packets with a single vCPU using the +DPDK testpmd application to drive the DPDK SPP PMD and the FPGA SDE IP. +This may be used for streaming CL bringup and performance measurements +in an isolated loopback environment. It runs testpmd in auto-start mode, +sends the first burst of TX packets (32 packets by default), and +displays packet statistics every 3 seconds (including PPS). To exit the +example, use ``ctrl-c``. + +Software installation and build phase + +:: + + cd $(SDK_DIR)/apps/virtual-ethernet/scripts + sudo ./virtual_ethernet_install.py + +System setup and device bind phase, e.g. on instance boot + +:: + + sudo fpga-load-local-image -S -I + cd $(SDK_DIR)/apps/virtual-ethernet/scripts + sudo ./virtual_ethernet_setup.py /dpdk + +Testpmd application setup and start phase + +:: + + cd /dpdk + sudo ./build/app/dpdk-testpmd -l 0-1 -- --port-topology=loop --auto-start --tx-first --stats-period=3 + +The testpmd application will display the number of TX-packets RX-packets +sent to/from the SDE. Everything three seconds, the number of TX-packets +and RX-packets will be updated to show the new packet total. In +addition, the packets per second throughput is calculated and updated. + +:: + + ######################## NIC statistics for port 0 ######################## + RX-packets: 28791397 RX-missed: 0 RX-bytes: 1842650496 + RX-errors: 0 + RX-nombuf: 0 + TX-packets: 28791429 TX-errors: 0 TX-bytes: 1842651456 + + Throughput (since last show) + Rx-pps: 4798711 Rx-bps: 2456940768 + Tx-pps: 4798711 Tx-bps: 2456940424 + ############################################################################ + +Please refer to `DPDK testpmd <#testpmd>`__ for a quick reference guide +on the supported testpmd features and the link to the full testpmd +documentation. + +FAQ +--- + +Q: What is the AGFI ID for the SDE loopback CL? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The AGFI ID for the SDE loopback CL is found in the +``CL_SDE Example Metadata`` section at the bottom of the +``CL_SDE README`` +`here <../../../../hdk/cl/examples/cl_sde/README.md>`__. + +Q: Where can I find DPDK testpmd feature documentation? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The full documentation for DPDK testpmd features is found +`here `__. + +Note that not all of the DPDK testpmd features are supported by the SPP +and ENI PMDs. SPP supports a limited subset of the DPDK Ethernet upper +API (e.g. DPDK eth_dev_ops) to the DPDK application(s) (e.g. testpmd) +for purposes of passing through streaming packets to/from the SDE. + +The application examples use testpmd auto-start mode. testpmd also +supports an interactive mode that may be used during debug and test +sessions. Interactive mode is especially useful when running testpmd +within the ``gdb`` debugger. Below is a quick reference guide for some +of the supported testpmd interactive mode commands that may be used with +the application examples. + +Q: What performance should I expect? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The goal of SPP on F2 is to sustain line rate network bandwidth for all +network configurations supported on the AWS FPGA instances. + +Q: How does packet drop and flow control work? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Packet drop and flow control characteristics are application specific, +since you are free to use the DPDK drivers and environment in the best +way that suits your specific application. + +As an example, let’s assume we have a packet forwarding topology that +directly connects an ENI to an SPP that does not drop any remaining TX +packets after partial TX packet burst has been submitted to ENI. Since +the application is in control of the packet processing, it can flow off +the SPP RX side by asking for fewer RX packets in the next call to the +SPP RX packet burst API. If the ENI TX backpressure condition persists, +the application may stop calling the SPP RX packet burst API. At this +point, SPP will stop processing RX descriptors, the C2H buffer in the +SDE will become full (see the SDE HW Guide +`here <./SDE_HW_Guide.md>`__), and this will backpressure the AXI-Stream +interface (e.g. the SDE will de-assert the ‘ready’ signal on the C2H +AXI-Stream interface). This may then backpressure the SPP TX side, which +is again under application control. If the SPP TX side backpressure +condition persists, the application may stop processing ENI RX packets +and this will eventually cause packet drops on the ENI RX side facing +the network. + +Q: How are SDE errors reported? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +On each call to the SPP TX/RX packet burst APIs, the DPDK SPP PMD checks +the SDE write-back TX/RX status. If the SDE write-back status is +non-zero, the SPP PMD takes the following steps: + +- Log-info the TX/RX channel SPP driver status variables and the SDE + status write-back variables +- Log-info the specific SDE error info from the SDE block that + encountered the error +- Log-info the descriptor ring entries +- Increments the TX/RX sde_error stat +- Log-error and return from the TX/RX status checking method. +- Return 0 packets processed from the SPP TX/RX packet burst APIs (e.g. + the DPDK TX/RX packet burst APIs return a uint16_t that indicates the + number of packets that were processed in the current call). + +Your application should periodically check to see if the TX/RX sde_error +stat is non-zero (e.g. by calling the eth_dev_ops xstats_get API for +error checking in the ``slow-path``). If the TX/RX sde_error stat is +non-zero, your application should take the following error recovery +steps: + +- Quiesce all calls to TX/RX packet burst (e.g. discontinue calling + ``rte_eth_dev tx/rx_pkt_burst``) +- Release all of the SPP queues (e.g. call + ``eth_dev_ops tx/rx_queue_release``) +- Remove the SPP PCI device (e.g. call ``rte_pci_driver remove``) +- Reload the AGFI using ``fpga-load-local-image`` to ensure the CL is + fully reset + +At this point, the DPDK SPP driver and SDE may be re-initialized as +normal. The SDE is reset during the SPP PCI device probe initialization +step, and the TX/RX queues are re-initialized during the TX/RX queue +setup phase. + +Q: What is the minimal packet size supported by AWS FPGA virtual ethernet IP? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +FPGA CL must generate packets with 64Byte or more to meet the Ethernet +minimum frame size requirement. + +Q: What is the maximal packet size? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +It is the maximal packet size offered by ENI on your instance (including +the 4-byte CRC). + +Q: Should I calculate the Ethernet frame CRC32? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +No, SPP relies on the ENI to check CRC on receive and calculate it on +transmit. + +Q: What MAC address should I use for SPP? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The SPP MAC address is normally unused for testpmd port based forwarding +and defaults to all zeroes. The default SPP MAC address may be changed +if needed using the testpmd ‘mac_addr set’ command when using the +testpmd application, or by your custom application using the DPDK APIs. + +Note that the SPP and SDE do not perform any modifications to the TX +packets (e.g. from the application to the CL), or the RX packets (e.g. +from the CL to the application). The SDE does not perform any packet +filtering (e.g. based on the packet destination MAC address). + +Q: How many TX and RX descriptors are supported? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The number of supported TX and RX descriptors per SPP queue pair is +parameterized within the SDE block and reported by the SDE to SPP via +registers within the SDE block (see the SDE H2C and C2H channels +`here <./SDE_HW_Guide.md>`__). SPP defines a minimum and the maximum +number of descriptors between 64 and 32K. The number of TX and RX +descriptors implemented in the SDE and requested by the DPDK application +in the SPP queue setup phase must be equal, and a power of 2. + +Q: How do I configure SPP to use SDE regular or compact descriptors? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The SDE may be built with regular or compact descriptor types (see the +C2H_DESC_TYPE and H2C_DESC_TYPE in the Design Parameters section +`here <./SDE_HW_Guide.md>`__). The SPP PMD also supports regular or +compact descriptor types at compile time via the SPP_USE_COMPACT_DESCS +define within spp_defs.h. The default descriptor type for the SDE and +SPP is ``regular`` to support the full 64-bit DMA addressing. If there +is a mismatch between the SDE and SPP descriptor type build options, the +SPP driver will log an error similar to the following: + +Mismatched build options: SDE descriptor type is ``regular``, SPP PMD +descriptor type is ``compact``. + +:: + + PMD: spp_dev_cap_get(): SDE C2H Desc Info(0x00400000), type=regular, is not supported + +Mismatched build options: SDE descriptor type is ``compact``, SPP PMD +descriptor type is ``regular``. + +:: + + PMD: spp_dev_cap_get(): SDE C2H Desc Info(0x00800001), type=compact, is not supported + +Q: What operating systems are supported? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The Virtual Ethernet application is tested and supported for Linux +operating systems (Amazon Linux and Ubuntu). + +Q: How do I update DPDK and SPP with the Vendor/Device ID for my CL? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Within ``/dpdk/drivers/net/spp`` there is a file called +``spp_ethdev.c``. Your Vendor and Device ID should be added to the +following table in ``spp_ethdev.c`` and then DPDK should be recompiled. + +.. code:: C + + static const struct rte_pci_id pci_id_spp_map[] = { + { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_SDE_LOOPBACK_CL) }, + { RTE_PCI_DEVICE(, ) }, + { .device_id = 0 }, + }; + +Rebuild DPDK as follows: + +:: + + cd /dpdk + ninja -C build + +Within ``/dpdk/usertools`` there is a file called +``dpdk-devbind.py``. Your Vendor and Device ID should be added to the +following table in ``dpdk-devbind.py``. + +.. code:: python + + aws_fpga_sde = {'Class': '05', 'Vendor': '1d0f', 'Device': 'f002', + 'SVendor': None, 'SDevice': None} + = {'Class': '05', 'Vendor': '', 'Device': '', + 'SVendor': None, 'SDevice': None} + + network_devices = [network_class, cavium_pkx, avp_vnic, aws_fpga_sde, ] + +You should then run the ``virtual_ethernet_setup.py`` script which will +re-run the ``dpdk-devbind.py`` script to bind DPDK and SPP to your +Vendor and Device Id. diff --git a/docs-rtd/source/sdk/userspace/fpga_mgmt_tools/README.rst b/docs-rtd/source/sdk/userspace/fpga_mgmt_tools/README.rst new file mode 100644 index 000000000..a2daaa370 --- /dev/null +++ b/docs-rtd/source/sdk/userspace/fpga_mgmt_tools/README.rst @@ -0,0 +1,438 @@ +Amazon FPGA Image (AFI) Management Tools +======================================== + +AWS provides the following set of command-line tools for Amazon FPGA +Image (AFI) management while running on an FPGA-enabled EC2 instance +(e.g., F2). **The tools currently support Linux Instances only.** + +- **``fpga-describe-local-image-slots``** + + - Returns the FPGA image slot numbers and device mappings to use for + the ``fpga-load-local-image``, ``fpga-clear-local-image``, and + ``fpga-describe-local-image`` commands. + +- **``fpga-describe-local-image``** + + - Returns the status of the FPGA image for a specified FPGA image slot + number. The *fpga-image-slot* parameter is an index that represents + a given FPGA within an instance. Use + ``fpga-describe-local-image-slots`` to return the available FPGA + image slots for the instance. + +- **``fpga-load-local-image``** + + - Loads the specified FPGA image to the specified slot number, and + returns the status of the command. The *fpga-image-slot* parameter + is an index that represents a given FPGA within an instance. Use + ``fpga-describe-local-image`` to return the FPGA image status, and + ``fpga-describe-local-image-slots`` to return the available FPGA + image slots for the instance. + +- **``fpga-clear-local-image``** + + - Clears the specified FPGA image slot, including FPGA internal and + external memories that are used by the slot. The *fpga-image-slot* + parameter is an index that represents a given FPGA within an + instance. Use ``fpga-describe-local-image`` to return the FPGA image + status, and ``fpga-describe-local-image-slots`` to return the + available FPGA image slots for the instance. + +- **``fpga-start-virtual-jtag``** + + - Starts a Virtual JTAG XVC server, to debug tools like Vivado Lab + Edition Hardware Manager to access debug cores inside the AFI. + Please refer to `Virtual JTAG + userguide <../../../hdk/docs/Virtual_JTAG_XVC.md>`__. + +- **``fpga-get-virtual-led``** + + - Returns a bit-map representing the state (1/0) the Virtual LEDs + exposed by the Custom Logic (CL) part of the AFI. + +- **``fpga-get-virtual-dip-switch``** + + - Returns a bit-map representing the current setting for the Virtual + DIP Switches that drives the Custom Logic (CL) part of the AFI. + +- **``fpga-set-virtual-dip-switch``** + + - Takes bit-map (in binary representation) to set for the Virtual DIP + Switches that drives the Custom Logic (CL) part of the AFI. + +- **``fpga-describe-clkgen``** + + - Returns the currently loaded frequencies in MHz for each clock in + each MMCM. The *fpga-image-slot* parameter is an index that + represents a given FPGA within an instance. If the design loaded + onto the FPGA does not have the clkgen IP, error clkgen-ip-not-found + will be returned. + +- **``fpga-load-clkgen-dynamic``** + + - Loads a frequency into the first clock of each specified MMCMs. + MMCMs that are not specified will be set to the default recipes. + Returns the currently loaded frequencies in MHz for each clock in + each MMCM. The *fpga-image-slot* parameter is an index that + represents a given FPGA within an instance. If the design loaded + onto the FPGA does not have the clkgen IP, error clkgen-ip-not-found + will be returned. + +- **``fpga-load-clkgen-recipe``** + + - Loads a clkgen recipe into the specified clocking groups. MMCMs that + are not specified will be set to the default recipes. Returns the + currently loaded frequencies in MHz for each clock in each MMCM. The + *fpga-image-slot* parameter is an index that represents a given FPGA + within an instance. If the design loaded onto the FPGA does not have + the clkgen IP, error clkgen-ip-not-found will be returned. + +All of the AFI Management Tools support a ``-help`` option that may be +used to display the full set of options. + +``sudo`` or ``root`` Privileges +------------------------------- + +The tools require sudo or root access rights since AFI loads and clears +modify the underlying system hardware (also see the FAQ section "Q: How +do the AFI Management Tools work?". + +Installs or Updates to the AFI Management Tools +----------------------------------------------- + +The tools can be downloaded and installed from AWS SDK/HDK GitHub +repository `aws-fpga `__, as follows: + +.. code:: bash + + git clone https://github.com/aws/aws-fpga.git + cd aws-fpga + source sdk_setup.sh + +The ``sdk_setup.sh`` script will build the AFI Management Tools and +install them in ``/usr/bin``. + +Quickstart +---------- + +Once you have the AFI Management Tools installed on your F2 instance, +you can display the FPGA slot numbers and PCIe mappings for driver +attachment (e.g., PCI Domain:Bus:Device:Function). + +Getting Inventory of the Available FPGA Slots +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. code:: bash + + sudo fpga-describe-local-image-slots -H + + ... + + Type FpgaImageSlot VendorId DeviceId DBDF + AFIDEVICE 0 0x1d0f 0x9048 0000:9f:00.0 + Type FpgaImageSlot VendorId DeviceId DBDF + AFIDEVICE 1 0x1d0f 0x9048 0000:a1:00.0 + Type FpgaImageSlot VendorId DeviceId DBDF + AFIDEVICE 2 0x1d0f 0x9048 0000:a3:00.0 + Type FpgaImageSlot VendorId DeviceId DBDF + AFIDEVICE 3 0x1d0f 0x9048 0000:a5:00.0 + Type FpgaImageSlot VendorId DeviceId DBDF + AFIDEVICE 4 0x1d0f 0x9048 0000:ae:00.0 + Type FpgaImageSlot VendorId DeviceId DBDF + AFIDEVICE 5 0x1d0f 0x9048 0000:b0:00.0 + Type FpgaImageSlot VendorId DeviceId DBDF + AFIDEVICE 6 0x1d0f 0x9048 0000:b2:00.0 + Type FpgaImageSlot VendorId DeviceId DBDF + AFIDEVICE 7 0x1d0f 0x9048 0000:b4:00.0 + +- The above list displayed the slots in an F2.48xl instance that has 8 + FPGAs on slot 0 through 7. + +- The VendorId is the PCIe Configuration space Vendor ID, with 0x1d0f + representing the Amazon registered PCIe Vendor ID. The developer can + choose the Vendor ID for their own AFIs. + +- The DeviceId is the PCIe Configuration space Device ID, with 0x9048 + being the default. + +- The DBDF is the common PCIe bus topology representing the + Domain:Bus#:Device#:Function#. + +\*\* NOTE: \*\* *While each FPGA has more than one PCIe Physical +Function, the AFI Management Tools will present the VendorId and +DeviceId of the first PF only*. + +Describing the AFI Content Loaded on a Specific FPGA Slot +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The following command displays the current state for the given FPGA slot +number. The output shows that the FPGA in the “cleared” state right +after instance create. + +.. code:: bash + + sudo fpga-describe-local-image -S 0 -H + + ... + + Type FpgaImageSlot FpgaImageId StatusName StatusCode ErrorName ErrorCode ShVersion + AFI 0 No AFI cleared 1 ok 0 + Type FpgaImageSlot VendorId DeviceId DBDF + AFIDEVICE 0 0x1d0f 0x9048 0000:34:00.0 + +Synchronous AFI Load and Clear Operations +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Synchronously Loading an AFI to a Specific FPGA Slot +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +To load the AFI, use the FPGA slot number and Amazon Global FPGA Image +ID parameters (see FAQ for AGFI). In synchronous mode, this command will +wait for the AFI to transition to the "loaded" state, perform a PCI +device remove and rescan in order to expose the unique AFI Vendor and +Device Id, and display the final state for the given FPGA slot number. + +.. code:: bash + + sudo fpga-load-local-image -S 0 -I agfi-0fedcba9876543210 -H + + ... + + Type FpgaImageSlot FpgaImageId StatusName StatusCode ErrorName ErrorCode ShVersion + AFI 0 agfi-0fedcba9876543210 loaded 0 ok 0 + Type FpgaImageSlot VendorId DeviceId DBDF + AFIDEVICE 0 0x6789 0x1d50 0000:34:00.0 + +Synchronously Clearing the FPGA Image on Specific Slot +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The following command will clear the FPGA image, including internal and +external memories. In synchronous mode, this command will wait for the +AFI to transition to the "cleared" state, perform a PCI device remove +and rescan in order to expose the default AFI Vendor and Device Id, and +display the final state for the given FPGA slot number. + +.. code:: bash + + sudo fpga-clear-local-image -S 0 -H + + ... + + Type FpgaImageSlot FpgaImageId StatusName StatusCode ErrorName ErrorCode ShVersion + AFI 0 No AFI cleared 1 ok 0 + Type FpgaImageSlot VendorId DeviceId DBDF + AFIDEVICE 0 0x1d0f 0x9048 0000:34:00.0 + +Asynchronous AFI Load and Clear Operations +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Asynchronously Loading an AFI to a Specific FPGA Slot +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +To load the AFI, use the FPGA slot number and Amazon Global FPGA Image +ID parameters (see FAQ for AGFI). The "-A" is used for asynchronous AFI +load operations. + +.. code:: bash + + sudo fpga-load-local-image -S 0 -I agfi-0fedcba9876543210 -A + +Describing the AFI content loaded on a specific FPGA slot after an asynchronous AFI load +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Displays the current state for the given FPGA slot number. The output +shows the FPGA in the “loaded” state after the FPGA image "load" +operation. **The "-R" option performs a PCI device remove and rescan in +order to expose the unique AFI Vendor and Device Id.** + +.. code:: bash + + sudo fpga-describe-local-image -S 0 -R -H + + ... + + Type FpgaImageSlot FpgaImageId StatusName StatusCode ErrorName ErrorCode ShVersion + AFI 0 agfi-0fedcba9876543210 loaded 0 ok 0 + Type FpgaImageSlot VendorId DeviceId DBDF + AFIDEVICE 0 0x6789 0x1d50 0000:34:00.0 + +Asynchronously Clearing the FPGA Image on Specific Slot +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The following command will clear the FPGA image, including internal and +external memories. The "-A" is used for asynchronous AFI clear +operations. + +.. code:: bash + + sudo fpga-clear-local-image -S 0 -A + +Describing the AFI content loaded on a specific FPGA slot after an asynchronous AFI clear +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The following command displays the current state for the given FPGA slot +number. It shows that the FPGA is in the “cleared” state after the FPGA +image "clear" operation. **The "-R" option performs a PCI device remove +and rescan in order to expose the default AFI Vendor and Device Id.** + +.. code:: bash + + sudo fpga-describe-local-image -S 0 -R -H + + ... + + Type FpgaImageSlot FpgaImageId StatusName StatusCode ErrorName ErrorCode ShVersion + AFI 0 No AFI cleared 1 ok 0 + Type FpgaImageSlot VendorId DeviceId DBDF + AFIDEVICE 0 0x1d0f 0x9048 0000:34:00.0 + +FAQ +--- + +- **Q: What is the Amazon Global FPGA Image ID (AGFI)?** + + - The AGFI is an AWS **globally** unique identifier that is used to + reference a specific Amazon FPGA Image (AFI). + - It is used to refer to a specific AFI when using the FPGA Management + tools from within an EC2 instance. + - In the examples, ``agfi-0fedcba9876543210`` is specified in the + ``fpga-load-local-image`` command in order to load a specific AFI + into the given ``fpga-image-slot``. + - AGFI IDs should not be confused with AFI IDs. The latter are + **regional** IDs that are used to refer to a specific AFI when using + the AWS EC2 APIs to create or manage and AFI. For example, when + copying an AFI across regions, it will preserve the same AGFI ID, + but get a new regional AFI ID. + +- **Q: What is a ``fpga-image-slot``?** + + - The fpga-image-slot is an index that represents a given FPGA within + an instance. Use ``fpga-describe-local-image-slots`` to return the + available FPGA image slots for the instance. + +- **Q: What are the Vendor and Device IDs listed in the + ``fpga-describe-local-image-slots`` and ``fpga-describe-local-image`` + output?** + + - The VendorId and DeviceId represent the unique identifiers for a PCI + device as seen in the PCI Configuration Header Space. These + identifiers are typically used by device drivers to know which + devices to attach to. The identifiers are assigned by PCI-SIG. You + can use Amazon's default DeviceId, or use your own during the + ``CreateFpgaImage`` EC2 API. + +- **Q: What is a DBDF?** + + - A DBDF is simply an acronym for Domain:Bus:Device.Function (also see + PF). + +- **Q: What is a PF?** + + - A PF refers to a PCI Physical Function that is exposed by the FPGA + hardware. For example, it is accessible by a user-space programs via + the sysfs filesystem in the path + ``/sys/bus/pci/devices/Domain:Bus:Device.Function``. The + ``Domain:Bus:Device.Function`` syntax is the same as returned from + ``lspci`` program output. Examples: **FPGA application PF** + ``0000:34:00.0``, **FPGA management PF** ``0000:34:00.1``. + +- **Q: What is a BAR?** + + - A PCI Base Address Register (BAR) specifies the memory region where + FPGA memory space may be accessed by an external entity (like the + instance CPU or other FPGAs). Multiple BARs may be supported by a + given PCI device. In this FAQ section (also see PF), BAR0 from a + device may be accessed (for example) by opening and memory mapping + the resource0 sysfs file in the path + ``/sys/bus/pci/devices/Domain:Bus:Device.Function/resource0``. Once + BAR0 has been memory mapped, the BAR0 registers may be accessed + through a pointer to the memory mapped region (refer to the open and + mmap system calls). + +- **Q: What is the AFIDEVICE and how is it used?** + + - Within the ``fpga-describe-local-image-slots`` and + ``fpga-describe-local-image`` commands the AFIDEVICE represents the + PCI PF that is used to communicate with the AFI. The AFIDEVICE + functionality exposed through the PF is dependent on the AFI that is + loaded via the ``fpga-load-local-image`` command. For example, DMA + and/or memory-mapped IO (MMIO) may be supported depending on the + loaded AFI, which is then used to communicate with the AFI in order + to perform an accelerated application-dependent task within the + FPGA. User-space applications may access the AFIDEVICE PF through + sysfs as is noted above in this FAQ section (also see PF). + +- **Q: How do the AFI Management Tools work?** + + - Within the F2 instance, the FPGAs expose a management PF (e.g. + ``0000:34:00.1``) that is used for control channel communication + between the instance and AWS. + - The FPGA management PF BAR0 is **reserved** for this communication + path. + - The FPGA application drivers **should not** access the FPGA + management PF BAR0. + - The AFI Management Tools memory map the FPGA management PF BAR0 and + communicate with AWS using internally defined messages and hardware + registers. + - The Amazon FPGA Image Tools require ``sudo`` or ``root`` access + level since AFI loads and clears are modifying the underlying system + hardware. + - ``sudo`` or ``root`` privilege is also required since the tools + access the sysfs PCI subsystem and ``/dev/kmsg`` for ``dmesg`` + logging. + +- **Q: Can the AFI Management Tools work concurently on multiple FPGA + image slots?** + + - The tools can be executed on multiple FPGAs concurrently. This may + be done without synchronization between processes that are using the + tools. + +- **Q: Can the AFI Management Tools work concurrently from multiple + processes on the same FPGA?** + + - Without synchronization between processes, the tools should only be + executed as one worker process per FPGA (highest level of + concurrency), or one worker process across all FPGAs (least level of + concurrency). + - Multiple concurrent process access to the tools using the same FPGA + without proper synchronization between processes will cause response + timeouts, and other indeterminate results. + +- **Q: What is an afi-power-violation?** + + - The F2 system can only reliably provide a certain amount of power to + the FPGA. If an AFI consumes more than this amount of power, the F2 + system will disable the input clocks to the AFI. For more + information on preventing, detecting, and recovering from this + state, see `AFI power guide (COMING + SOON) <../../../hdk/docs/afi_power.md>`__ + +- **Q: How can I reset the AFI?** + + - The AFI may be reset (reloaded) via fpga-load-local-image, and/or + reset back to a fully clean slate via ``fpga-clear-local-image`` and + ``fpga-load-local-image``. + +References +---------- + +- AWS FPGA SDK/HDK on github + `aws-fpga `__ + +AWS EC2 References +~~~~~~~~~~~~~~~~~~ + +- `AWS EC2 Getting + Started `__ +- `AWS EC2 Instance + Types `__ +- `AWS EC2 User + Guide `__ +- `AWS EC2 Networking and + Security `__ +- `AWS EC2 Key + Pairs `__ +- `AWS EC2 Attach EBS + Volume `__ +- `AWS EC2 + Troubleshooting `__ diff --git a/docs-rtd/source/spelling_filters/hex_filter.py b/docs-rtd/source/spelling_filters/hex_filter.py new file mode 100644 index 000000000..3bb1327ae --- /dev/null +++ b/docs-rtd/source/spelling_filters/hex_filter.py @@ -0,0 +1,18 @@ +import enchant +from enchant.tokenize import Filter + +class HexFilter(Filter): + def _skip(self, word): + if word.startswith(("0x", "0X")): + try: + int(word[2:], 16) + return True + except ValueError: + return False + elif word.startswith(("x", "X")): + try: + int(word[1:], 16) + return True + except ValueError: + return False + return False \ No newline at end of file diff --git a/docs-rtd/source/spelling_filters/ordinal_filter.py b/docs-rtd/source/spelling_filters/ordinal_filter.py new file mode 100644 index 000000000..40d70617b --- /dev/null +++ b/docs-rtd/source/spelling_filters/ordinal_filter.py @@ -0,0 +1,20 @@ +import enchant +from enchant.tokenize import Filter + +class OrdinalFilter(Filter): + def _skip(self, word): + is_ordinal = any([word.endswith(suffix) for suffix in ("st", "nd", "rd", "th")]) + if not is_ordinal: + return False + try: + number = int(word[:-2]) + if number % 10 == 1 and number % 100 != 11: + return word.endswith('st') + elif number % 10 == 2 and number % 100 != 12: + return word.endswith('nd') + elif number % 10 == 3 and number % 100 != 13: + return word.endswith('rd') + else: + return word.endswith('th') + except ValueError: + return False \ No newline at end of file diff --git a/docs-rtd/source/spelling_filters/rtl_hex_filter.py b/docs-rtd/source/spelling_filters/rtl_hex_filter.py new file mode 100644 index 000000000..51805cb29 --- /dev/null +++ b/docs-rtd/source/spelling_filters/rtl_hex_filter.py @@ -0,0 +1,31 @@ +import enchant +import re +from enchant.tokenize import Filter + +class RTLHexFilter(Filter): + def _skip(self, word): + rtl_hex_literal_prefix = "’h" + if rtl_hex_literal_prefix in word: + # If the literal makes use of underscores for readability + if "_" in word: + underscore_positions = [pos.start() for pos in re.finditer("_", word)] + for pos in underscore_positions: + aligned_word = "" + try: + aligned_word = word[pos + 1 : pos + 5] + word_len = len(aligned_word) + if word_len < 4: + raise IndexError(f"Word {aligned_word} is only {word_len} hex digits long!") + try: + int(aligned_word, base=16) + return True + except ValueError as v: + print("ERROR: Could not convert hex word literal {aligned_word} to a base-16 integer!") + return False + except IndexError as i: + print(f"ERROR: Could not gather 4 hex digits after underscore: \n\t{aligned_word} \n\t{word}") + print((i)) + return False + else: + return True + return False diff --git a/docs-rtd/source/spelling_wordlist.txt b/docs-rtd/source/spelling_wordlist.txt new file mode 100644 index 000000000..e784d8a1d --- /dev/null +++ b/docs-rtd/source/spelling_wordlist.txt @@ -0,0 +1,231 @@ +Questa +Runtime +hdk +mem +perf +dma +addr +hbm +rnd +Vitis +reconfigurable +genomics +vCPU +Gbps +Vivado +architecting +Verilog +VHDL +Tcl +Synopsys +OpenCL +pre +Graviton +RTL +AWS +rescan +runtime +subdirectory +Xilinx +bitstream +sde +AXI +datapath +verif +Makefile +precharge +tb +dpi +vh +ip +aws +clk +sv +regs +conv +axil +axi +cfg +cnv +fifo +bram +wr +ccf +ctl +cdc +async +Async +Multi +Synchronizer +pipelined +svh +Instantiation +mgt +acc +axl +ddr +rr +arb +srl +xpm +testbench +config +dcp +py +symlink +Floorplan +tcl +uncommented +subdirectories +bitstreams +eg +idx +pcis +ocl +tst +hdeadbeef +sda +pcim +irq +ack +hwsw +cosim +xrt +clkgen +reobtained +fpga +sysfs +filesystem +xl +Quickstart +sudo +clkgen +loopback +bringup +workflows +testpmd +bringup +Testpmd +eth +dev +backpressure +de +uint +xstats +Quiesce +ethernet +parameterized +spp +defs +metadata +pipelining +latencies +userspace +incrementing +desc +Rresp +escriptors +Desc +bitfield +parameterizable +instantiated +Redhat +Centos +floorplan +AMD +JTAG +ap +sims +buf +extern +msg +printf +const +chan +putc +getc +hm +longint +que +dst +src +cnt +chk +prot +dly +nsec +flr +intf +wc +strb +vpd +Modelsim +functionalities +shreg +fanout +gtp +propert +nworst +foreach +Dataflow +glcount +ns +vDIP +vLED +vdip +vled +pwr +tuple +apppf +req +wstrb +awaddr +dw +awlen +PCIe +AFI +rst +routability +Bufferable +Uncorrectable +BankGroup +prefetchable +DIPSwitch +Ultrascale +Virtex +QoS +KByte +multi +Prefetchable +prefetchability +prefetching +optimizations +bm +sync'ed +cctrl +instantiation +Microarchitecture +verilog +readme +agfi +Floorplanning +frontdoor +bdr +axsize +len +mstr +microarchitecture +mux +muxed +kern +datapaths +pblock +allgn +architected +Bresp +arlen +posedge +nxt +sync'd +timestamp +deasserted \ No newline at end of file diff --git a/docs-rtd/source/vitis/README.rst b/docs-rtd/source/vitis/README.rst new file mode 100644 index 000000000..cde29dc6b --- /dev/null +++ b/docs-rtd/source/vitis/README.rst @@ -0,0 +1,264 @@ +Quick Start Guide to Accelerating your C/C++ application on AWS EC2 F2 (FPGA) Instances with Vitis +================================================================================================== + +This quick start guide will utilize a simple ``hello_world`` Vitis +example to get you started. + +Table of Contents +================= + +1. `Overview <#1-overview>`__ +2. `Prerequisites <#2-prerequisites>`__ + + - 2.1 `AWS Account and F2/EC2 + Instances <#21-aws-account-and-f2ec2-instances>`__ + - 2.2 `GitHub and Environment + Setup <#22-github-and-environment-setup>`__ + +3. `Design Emulation and Synthesis <#3-emulating-your-code>`__ + + - 3.1 `Emulate the code <#31-emulation>`__ + + - 3.1.1 `Hardware Emulation <#311-hardware-hw-emulation>`__ + + - 3.2 `Results and Artifacts <#32-results-and-artifacts>`__ + +4. `Next Steps <#4-next-steps>`__ + + - 4.1. `Examining Run Data <#41-examining-run-data>`__ + +5. `Additional Resources <#5-additional-vitis-information>`__ + +.. _1-overview: + +1. Overview +=========== + +- Vitis is a complete development environment for applications + accelerated using AWS EC2 F2 (FPGA) instances +- It leverages the OpenCL heterogeneous computing framework to offload + compute intensive workloads to F2 instances +- The accelerated application is written in C/C++, OpenCL and/or + Verilog/VHDL + +.. _2-prerequisites: + +2. Prerequisites +================ + +.. _21-aws-account-and-f2ec2-instances: + +2.1 AWS Account and F2/EC2 Instances +------------------------------------ + +- Getting Familiar with AWS - If you have never used AWS before, we + recommend you start with AWS getting started training, and focus on + the basics of the AWS EC2 and AWS S3 services. Understanding the + fundamentals of these services will make it easier to work with AWS F2 + instances and the FPGA Developer Kit. `Setup an AWS + Account `__ +- FPGA developer AMI (2024.1) - available for on-cloud F2 development + with AMD tools pre-installed and free to use on AWS EC2 for F2 + development. Customers can use this AMI to design, simulate, and build + their designs. Given the large size of the FPGA used for F2, AMD tools + work best with at least 4 vCPU's and 32GiB Memory. We recommend + Compute Optimized and Memory Optimized instance types to successfully + run the synthesis of acceleration code. Developers may start coding + and run simulations on low-cost General Purpose instances types. + Launch an instance using a pre-installed with Vitis and required + licenses. + +.. _22-github-and-environment-setup: + +2.2 GitHub and Environment Setup +-------------------------------- + +- Clone this github repository, export your AWS IAM credentials, and + source the *vitis_setup.sh* script: + +:: + + cd aws-fpga + source vitis_setup.sh + +- Sourcing the `vitis_setup.sh <../vitis_setup.sh>`__ script does the + following: + + - Downloads and sets the correct AWS Platforms: + + - AWS EC2 F2 Vitis platform package that contains the dynamic + hardware that enables Vitis kernels to run on AWS F2 instances + - Valid platforms for shell_stable: ``AWS_PLATFORM_202401_0`` + (Default) AWS F2 Vitis platform + + - Sets up the Vitis example directories + - Installs the required libraries and package dependencies + - Runs environment checks to verify supported tool/lib versions + - Gathers dependencies needed to install the `Xilinx + Runtime `__ (XRT) + +If the script has successfully set up all of the tools and the +environment, you will see the following message: + +.. code:: bash + + INFO: #-------------------------------------------------------------------------------# + INFO: How to run hardware emulation or synthesis on an example + INFO: cd vitis/examples/vitis_examples/hello_world + INFO: hw_file_check + INFO: #----------------------------- Emulation ---------------------------------------# + INFO: make build TARGET=hw_emu PLATFORM=$SHELL_EMU_VERSION + INFO: #-------------------------------------------------------------------------------# + INFO: Vitis Setup PASSED. + +.. _3-emulating-your-code: + +3. Emulating Your Code +====================== + +Vitis hardware emulation is a cycle-accurate emulation of your +accelerator design. This section will walk you through the +emulation process. + +.. _31-emulation: + +3.1 Emulation +------------- + +The main goal of hardware emulation is to insure functional correctness +and determine how to partition the application between the host CPU and +the FPGA. Hardware emulation does not require use of actual FPGAs and +can be run on any compute instance. Using non-F2 EC2 compute instances +during initial development reduces cost. + +.. _311-hardware-hw-emulation: + +3.1.1 Hardware (HW) Emulation +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The Vitis hardware emulation flow enables the developer to check the +correctness of the logic generated by the tools. This emulation flow +invokes the hardware simulator in the Vitis environment to test the +functionality of the code. + +To perform hardware emulation for any given example, run the following +commands: + +.. code:: bash + + cd $AWS_FPGA_REPO_DIR + cd vitis/examples/vitis_examples + +After listing the contents of ``vitis/examples/vitis_examples``, +navigate to your desired example. + +Prior to starting a hardware emulation run, run the ``hw_file_check`` +command to insure that all files required for simulation are present. If +all required files are present, you will see +``All required simulation files are present!``. Otherwise, the missing +files' names will be displayed. These files can always be reobtained +from the ``aws-fpga`` repository if they are deleted or renamed at any +point. + +The most critical file in each example directory is the ``Makefile``. +Some examples will have sub-examples, whose ``Makefiles`` are located in +the associated subdirectory. + +Note the presence of the ``Makefile`` in this subdirectory. Some +examples will have sub-examples, whose ``Makefiles`` are located in the +associated subdirectory. + +.. warning:: + + A Makefile is required in order to run hardware emulation for all + designs/examples + +We recommend running hardware emulation in the background to prevent +disruption due to the compute intensity and time needed for completion. +Prefixing commands with ``nohup`` and ending them with an ``&`` will +insure more reliable execution. + +Once you've verified that all required files are present in the current +example directory, start the hardware emulation run with the following +command: + +.. code:: bash + + nohup make build TARGET=hw_emu PLATFORM=$SHELL_EMU_VERSION & + +The same command can be used for all Vitis examples after running +``vitis_setup.sh``. + +.. _32-results-and-artifacts: + +3.2 Results and Artifacts +~~~~~~~~~~~~~~~~~~~~~~~~~ + +Once the emulation/build has completed, you will see either a +``TEST PASSED``, or a relevant error message. + +Upon successful emulation/build completion, you will notice that a build +directory has been created in the example's directory: + +.. code:: bash + + aws-fpga/vitis/examples/vitis_examples/ + hello_world/ + build_dir.hw_emu.xilinx_aws-vu47p-f2_202410_1/ + +**This directory will contain the .xclbin file, as well as other +artifacts, depending on the example run:** + +Hardware emulation: + +.. code:: bash + + drwxrwxr-x 2 ubuntu ubuntu 4096 Aug 15 17:58 ./ + drwxr-xr-x 13 ubuntu ubuntu 4096 Aug 15 18:51 ../ + -rw-rw-r-- 1 ubuntu ubuntu 46324262 Aug 15 17:58 vadd.link.xclbin + -rw-rw-r-- 1 ubuntu ubuntu 11777 Aug 15 17:58 vadd.link.xclbin.info + -rw-rw-r-- 1 ubuntu ubuntu 38652 Aug 15 17:58 vadd.link.xclbin.link_summary + -rw-rw-r-- 1 ubuntu ubuntu 46324302 Aug 15 17:58 vadd.xclbin + -rw-rw-r-- 1 ubuntu ubuntu 4414 Aug 15 17:58 vadd.xclbin.package_summary + +.. _4-next-steps: + +4. Next Steps +============= + +.. _41-examining-run-data: + +4.1 Examining Run Data +---------------------- + +After a hardware simulation run, there are three files that contain very +important information: + +- ``vadd.xclbin.info`` + + - A text report of the generated device binary + +- ``vadd.xclbin.link_summary`` + + - A summary report of the linking process which generated the device + binary + +- ``vadd.link.xclbin.link_summary`` + + - Contains an estimate of system performance + +- ``xrt.run_summary`` + + - A summarized report of events captured during application runtime + +The first three of these files can be found in the newly-generated +directory prefixed with ``build_dir.hw_emu.``. The xrt run summary file +can be found in the example directory. + +.. _5-additional-vitis-information: + +5. Additional Vitis Information +=============================== + +- `Vitis Documentation + Hub `__ diff --git a/hdk/README.md b/hdk/README.md index cd2795949..596cad437 100644 --- a/hdk/README.md +++ b/hdk/README.md @@ -8,7 +8,7 @@ - [Getting Started](#getting-started) - [Build Accelerator AFI using HDK Design Flow](#build-accelerator-afi-using-hdk-design-flow) - [Step 1. Setup Development Environment](#step-1-setup-development-environment) - - [Step 2. Clone Developer Dit Repository](#step-2-clone-developer-dit-repository) + - [Step 2. Clone Developer Kit Repository](#step-2-clone-developer-kit-repository) - [Step 3. Setup Environment for HDK Design Flow](#step-3-setup-environment-for-hdk-design-flow) - [Step 4. Build CL Design Check Point (DCP)](#step-4-build-cl-design-check-point-dcp) - [Step 5. Explore Build Artifacts](#step-5-explore-build-artifacts) @@ -20,7 +20,7 @@ - [cl\_dram\_hbm\_dma](#cl_dram_hbm_dma) - [cl\_mem\_perf](#cl_mem_perf) - [CL\_TEMPLATE - Create your own design](#cl_template---create-your-own-design) - - [CL Example Heirarchy](#cl-example-heirarchy) + - [CL Example Hierarchy](#cl-example-hierarchy) - [Design](#design) - [Verification](#verification) - [Software](#software) @@ -30,23 +30,23 @@ - [/verif](#verif) - [/ip](#ip) - [/lib](#lib) - - [Next Steps](#next-steps) + - [Getting Started](#getting-started-1) ## HDK Overview -The HDK flow enables developers to create RTL based accelerator designs targeted for F2 systems using AMD Vivado. Small Shell allows developers to preserve resources in the top SLR by removing the DMA functionality and relying on the basic peek/poke access from Host to FPGA. +The HDK design flow enables developers to create RTL-based accelerator designs for F2 instances using AMD Vivado. HDK designs must be integrated with Small Shell, which does not include a built-in Direct Memory Access (DMA) engine and offers full resources in the top Super Logic Region (SLR) of the FPGA to developers. ## Getting Started ### Build Accelerator AFI using HDK Design Flow -This section provides a step-by-step guide to build an F2 AFI using the HDK design flow. The flow starts with an existing CL example design. Steps 1 through 3 demonstrate how to set up the HDK development environment. Steps 4 through 5 show the commands used to generate the CL DCP files and the expected build artifacts. Steps 6 and 7 show developers how to submit the DCP file to generate an AFI for use on F2 instances. +This section provides a step-by-step guide to build an F2 AFI using the HDK design flow. The flow starts with an existing Customer Logic (CL) example design. Steps 1 through 3 demonstrate how to set up the HDK development environment. Steps 4 through 5 show the commands used to generate CL Design Checkpoint (DCP) files and other build artifacts. Steps 6 and 7 demonstrate how to submit the DCP file to generate an AFI for use on F2 instances. #### Step 1. Setup Development Environment Developers can either use the AWS-provided developer AMI for F2 or their on-premise development environment for this demo. -#### Step 2. Clone Developer Dit Repository +#### Step 2. Clone Developer Kit Repository ```bash git clone https://github.com/aws/aws-fpga.git @@ -70,7 +70,7 @@ After the setup is done successfully, you should see `AWS HDK setup PASSED`. Sou #### Step 4. Build CL Design Check Point (DCP) -After the HDK design environment is set up, you are ready to build a design example. Run the following commands to build CL DCP files in Vivado. This tutorial uses [cl_sde](./cl/examples/cl_sde/), but the same steps can be used for other [CL examples](./cl/examples). +After the HDK design environment is set up, you are ready to build a design example. Run the following commands to build CL DCP files in Vivado. This tutorial uses the [cl_sde](./cl/examples/cl_sde/) example. The same steps can be used for any other [CL examples](./cl/examples). ```bash cd hdk/cl/examples/cl_sde @@ -79,12 +79,22 @@ cd build/scripts ./aws_build_dcp_from_cl.py -c cl_sde ``` -A few notes on [./aws_build_dcp_from_cl.py](./common/shell_stable/build/scripts/aws_build_dcp_from_cl.py): +The Shell supplies two base clocks to the CL: a 250MHz `clk_main_a0` clock and a 100MHz `clk_hbm_ref` clock. However, the CL can run at higher frequencies using locally generated clocks. F2 Developer Kit offers an [AWS Clock Generation (AWS_CLK_GEN) IP](./hdk/docs/AWS_CLK_GEN_spec.md) that you can leverage in your design to generate CL clocks with frequencies specified in the [Clock Recipes User Guide](./docs/Clock_Recipes_User_Guide.md). + +Run the command below to build a DCP with desired clock recipes: + +```bash +./aws_build_dcp_from_cl.sh -c cl_mem_perf --aws_clk_gen --clock_recipe_a A1 --clock_recipe_b B2 --clock_recipe_c C0 --clock_recipe_hbm H2 +``` + +**NOTE**: The [cl_sde](./cl/examples/cl_sde/) example does not contain the AWS_CLK_GEN component. This command uses the [cl_mem_perf](./cl/examples/cl_mem_perf/) example to demonstrate the AWS_CLK_GEN usage. + +A few more notes on [aws_build_dcp_from_cl.py](https://github.com/aws/aws-fpga/blob/-/hdk/common/shell_stable/build/scripts/aws_build_dcp_from_cl.py): - Use `--mode small_shell` option to build CL designs with Small Shell. - Use `--cl ` option to build a different CL design. This is default to `cl_dram_hbm_dma`. -- Use `--aws_clk_gen` option to annotate the use of [AWS clock generation block](./hdk/docs/AWS_CLK_GEN_spec.md) and [customer clock recipes](./hdk/docs/Clock_Recipes_User_Guide.md). -- The script also allows developers to pass different directives supported by the Vivado tool as shown below: +- Use `--aws_clk_gen` option to annotate the use of [AWS clock generation block](./hdk/docs/AWS_CLK_GEN_spec.md) and [customer clock recipes](./docs/Clock_Recipes_User_Guide.md). +- The script also allows developers to pass different Vivado directives as shown below: - `--place `: Default to `SSI_SpreadLogic_high` placement strategy. Please refer to [Vivado User Guide](https://docs.amd.com/r/en-US/ug904-vivado-implementation/Available-Directives) for supported directives. - `--phy_opt ` : Default to `AggressiveExplore` physical optimization strategy. Please refer to [Vivado User Guide](https://docs.amd.com/r/en-US/ug904-vivado-implementation/Using-Directives?tocId=9xJiGeSV35ApxUsX7pAVDg) for supported directives - `--route ` : Default to `AggressiveExplore` routing strategy. Please refer to [Vivado User Guide](https://docs.amd.com/r/en-US/ug904-vivado-implementation/Using-Directives?tocId=dV9wYjuIP6n9oUJhkoHuRg) for supported directives. @@ -92,7 +102,7 @@ A few notes on [./aws_build_dcp_from_cl.py](./common/shell_stable/build/scripts/ #### Step 5. Explore Build Artifacts -While Vivado is running, a build log file `YYYYY_MM_DD-HHMMSS.vivado.log` will be created in `$CL_DIR/build/scripts` to track the build’s progress. DCP build times will vary, based on the design size and complexity. The examples in the development kit take between 30 to 90 minutes to build. After the design is finished building, the following information will be shown at the bottom of the log file: +While Vivado is running, a build log file `YYYYY_MM_DD-HHMMSS.vivado.log` will be created in `$CL_DIR/build/scripts` to track the build’s progress. DCP build times will vary based on the design size and complexity. The examples in the development kit take between 30 to 90 minutes to build. After the design is finished building, the following information will be shown at the bottom of the log file: ```bash tail @@ -105,7 +115,7 @@ tail Generated post-route DCP and design manifest files are archived into a tarball file `.Developer_CL.tar` and saved in the `$CL_DIR/build/checkpoints/` directory. All design timing reports are saved in the `$CL_DIR/build/reports/` directory. -:warning: If Vivado cannot achieve timing closure for thed design, the post-route DCP file name will be marked with `.VIOLATED` as an indicator. Developers need to refer to the DCPs and timing reports for detailed timing failures. +:warning: If Vivado cannot achieve timing closure for the design, the post-route DCP file name will be marked with `.VIOLATED` as an indicator. Developers need to refer to the DCPs and timing reports for detailed timing failures. :warning: The build process will generate a DCP tarball file regardless of the design’s timing closure state. However, in case of a DCP with timing failures, the design’s functionality is no longer guaranteed. Therefore, the AFI created using this DCP should be used for testing purpose ONLY. The following warning is shown in this case: @@ -115,7 +125,7 @@ Generated post-route DCP and design manifest files are archived into a tarball f #### Step 6. Submit Generated DCP for AFI Creation -To submit the DCP, create an S3 bucket for submitting the design and upload the DCP tarball file to the bucket. DCP submission requires the following information: +To submit the DCP, create an S3 bucket and upload the DCP tarball file to the bucket. DCP submission requires the following information: - Name of the design (Optional). - Generic description of the logic design (Optional). @@ -208,7 +218,7 @@ aws ec2 describe-fpga-images --fpga-image-ids afi-09953582f46c45b17 --region us- #### Step 7. Load Accelerator AFI on F2 Instance -Now that your AFI is available, it can be tested on an F2 instance. The instance can be launched using any prefered AMI, private or public, from the AWS Marketplace catalog. AWS recommends using AMIs with Ubuntu 20.04 and kernel version 5.15. +Now that your AFI is available, it can be tested on an F2 instance. The instance can be launched using any preferred AMI, private or public, from the AWS Marketplace catalog. AWS recommends using AMIs with Ubuntu 20.04 and kernel version 5.15. Now you need to install the FPGA Management tools by sourcing the `sdk_setup.sh` script: @@ -320,7 +330,7 @@ All examples have the following features: ### [cl_sde](./cl/examples/cl_sde) The cl_sde example implements the Streaming Data Engine (SDE) IP block -into FPGA custom logic to demonstrate the Virtual Ethernet Application. +into FPGA custom logic to demonstrate the [Virtual Ethernet Application](../sdk/apps/virtual-ethernet/README.md). See [cl_sde](./cl/examples/cl_sde) for more information @@ -332,7 +342,7 @@ See [cl_dram_hbm_dma](./cl/examples/cl_dram_hbm_dma) for more information ### [cl_mem_perf](./cl/examples/cl_mem_perf) -The cl_mem_perf is a customer reference design for F2 where the objective is to demonstrate fine tuned data paths to HBM and DDR to achieve maximum throughput to the memories. The example also demonstrates datapath connectivity between Host, AWS Shell, Custom Logic (CL) region in the FPGA, HBM and DDR DIMM on the FPGA card. +The cl_mem_perf is a reference design for F2 where the objective is to demonstrate fine tuned data paths to HBM and DDR to achieve maximum throughput to the memories. The example also demonstrates datapath connectivity between Host, AWS Shell, Custom Logic (CL) region in the FPGA, HBM and DDR DIMM on the FPGA card. See [cl_mem_perf](./cl/examples/cl_mem_perf) for more information @@ -352,7 +362,7 @@ cd hdk/cl/examples ./create_new_cl.py --new_cl_name ${NEW_CL_NAME} ``` -## CL Example Heirarchy +## CL Example Hierarchy The following sections describe common functionality across all CL examples. [CL_TEMPLATE](./CL_TEMPLATE) can be used as a reference for what features are available in all CL examples; as well as what's required to verify, test, and build. @@ -428,7 +438,7 @@ The [shell_stable](./common/shell_stable) contains all the IPs, constraints and ### [/verif](./hdk/verif) -The [verif directory](./common/verif) includes reference verification modules to be used as Bus Functional Models (BFM) as the external interface to simulate the Custom Logic (CL). The verification related files common to all the CL examples are located in this directory. It has models, include, scripts, tb directories. +The [verif directory](./common/verif) includes reference verification modules to be used as Bus Functional Models (BFM) as the external interface to simulate the CL. The verification related files common to all the CL examples are located in this directory. It has models, include, scripts, tb directories. The [verif models directory](./common/verif/models) includes simple models of the DRAM interface around the FPGA, shell, and card. You can also find Xilinx protocol checkers in this directory. @@ -476,9 +486,9 @@ The [lib directory](./common/lib) includes basic "library" elements that may be - sync.v - Synchronizer - xpm_fifo.sv - Synchronous clock FIFO -## Next Steps +## Getting Started -- Review the [cl_sde](./cl/examples/cl_sde) example -- [Run RTL Simulations](./docs/RTL_Simulation_Guide_for_HDK_Design_Flow.md) on the example designs -- Dive deep into [Shell interface specifications](./docs/AWS_Shell_Interface_Specification.md) and [PCIe Memory map](./docs/AWS_Fpga_Pcie_Memory_Map.md) -- Create your own designs or port an existing F1 design to F2 system +* Review the [cl_dram_hbm_dma](./cl/examples/cl_dram_hbm_dma/README.md) and [cl_sde](./cl/examples/cl_sde) examples +* [Run RTL Simulations](./docs/RTL_Simulation_Guide_for_HDK_Design_Flow.md) on the example designs +* Dive deep into [Shell interface specifications](./docs/AWS_Shell_Interface_Specification.md) and [PCIe Memory map](./docs/AWS_Fpga_Pcie_Memory_Map.md) +* Create your own designs/Port F1 designs to F2 systems. diff --git a/hdk/cl/CHECKLIST_BEFORE_BUILDING_CL.md b/hdk/cl/CHECKLIST_BEFORE_BUILDING_CL.md index 2f4e0468a..18b7431ba 100644 --- a/hdk/cl/CHECKLIST_BEFORE_BUILDING_CL.md +++ b/hdk/cl/CHECKLIST_BEFORE_BUILDING_CL.md @@ -1,10 +1,11 @@ -This checklist includes important items that the developer should check before running a build (Vivado implementation) +# Checklist Before Building + +This checklist includes important items that the developer should check before building a CL Design Check Point (DCP) file for AFI generation. 1. Verify that the environment variables `$HDK_SHELL_DIR` and `$CL_DIR` are set correctly. - + 1. Verify that the `$CL_DIR` directory has a `/build` sub-directory. 1. Update `$CL_DIR/build/script/encrypt.tcl` script for your design specific changes, including the list of all the source files (including header files like .inc and .h/.vh), so they all get copied to `src_post_encryption` directory 1. Update the timing and placement constraints under `$CL_DIR/build/constraints` for your design specific changes. - diff --git a/hdk/cl/examples/CL_TEMPLATE/README.md b/hdk/cl/examples/CL_TEMPLATE/README.md index 076eaac27..501682d27 100644 --- a/hdk/cl/examples/CL_TEMPLATE/README.md +++ b/hdk/cl/examples/CL_TEMPLATE/README.md @@ -87,7 +87,7 @@ The build flow is identical to all other examples: 1. Populate the [constraint files](./build/constraints) as needed 2. Update [synth_CL_TEMPLATE.tcl](./build/scripts/synth_CL_TEMPLATE.tcl) with relevant IP's, constraints, etc. 3. Run [aws_build_dcp_from_cl.py](../../../common/shell_stable/build/scripts/aws_build_dcp_from_cl.py) - - For a full guide on aws_build_dcp_from_cl.py please refer to [Setup the Development Environment and SDK Design Flow](./../../../../README.md#setup-the-development-environment-and-sdk-design-flow) on the main page. + - Run ``aws_build_dcp_from_cl.py --help`` for more details. See the following `tcl` scripts for more details on the build flow (they are sourced in [synth_CL_TEMPLATE.tcl](./build/scripts/synth_CL_TEMPLATE.tcl)): @@ -115,7 +115,7 @@ For more information on how to populate the constraint files and build scripts, ## CL_TEMPLATE Quick Start Guide -The top level [Quick Start Guide](./../../../../README.md#quick-start) on the main page will provide an introduction to this guide. +The top level [Quick Start Guide](./../../../README.md#getting-started) on the main page will provide an introduction to this guide. ### STEP 1: Create a New CL @@ -170,15 +170,16 @@ Or specify an [available simulator](./../../../../README.md#supported-tools-vers make CL_TEMPLATE_base_test =1 ``` -This will first generate and compile the simulation libraries required for the requested SIMULATOR. Test results will be stored in the `$CL_DIR/verif/sim/` directory (created upon first simulation run). After adding new IP's to [`$AWS_FPGA_REPO_DIR/hdk/common/ip`](./../../../common/ip) the simulation libraries need to be recompiled: `make regenerate_sim_libs =1`. For more information, see [`$AWS_FPGA_REPO_DIR/hdk/README.md`](./../../../). +This will first generate and compile the simulation libraries required for the requested SIMULATOR. Test results will be stored in the `$CL_DIR/verif/sim/` directory (created upon first simulation run). After adding new IP's to [`$AWS_FPGA_REPO_DIR/hdk/common/ip`](./../../../common/ip) the simulation libraries need to be recompiled: `make regenerate_sim_libs =1`. #### File List Generation -The Makefile includes [$AWS_FPGA_REPO_DIR/hdk/common/verif/tb/scripts/Makefile.common.inc](./../../../../../common/verif/tb/scripts/Makefile.common.inc) which runs a Python script to automatically update each `top..f` file list with all SystemVerilog files found under the [$CL_DIR/design](./design) directory. -* To disable the generation, run `export DONT_GENERATE_FILE_LIST=1`. -* To re-enable the generation, run `unset DONT_GENERATE_FILE_LIST`. -* To generate the file list by itself, run `make generate_sim_file_list =1`. -* To add additional files, add them outside of the auto generation section: +The Makefile includes [$AWS_FPGA_REPO_DIR/hdk/common/verif/tb/scripts/Makefile.common.inc](./../../../common/verif/tb/scripts/Makefile.common.inc) which runs a Python script to automatically update each `top..f` file list with all SystemVerilog files found under the [$CL_DIR/design](./design) directory. + +- To disable the generation, run `export DONT_GENERATE_FILE_LIST=1`. +- To re-enable the generation, run `unset DONT_GENERATE_FILE_LIST`. +- To generate the file list by itself, run `make generate_sim_file_list =1`. +- To add additional files, add them outside of the auto generation section: ```text # Add code up here or below the comment block to persist between simulations @@ -194,7 +195,7 @@ $CL_DIR/design/CL_TEMPLATE.sv ############################## ``` -#### Xilinx IP Discovery and Compilation +#### Xilinx/AMD IP Discovery and Compilation When running your first test, all Xilinx IP's under [$AWS_FPGA_REPO_DIR/hdk/common/ip/cl_ip](./../../../common/ip/cl_ip) are automatically compiled @@ -207,17 +208,17 @@ If a design adds new IP's, make sure to add the new simulation libraries to `COM Simulation library names can be found under: - [$AWS_FPGA_REPO_DIR/hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts](./../../../common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts) -followed by `"IP_NAME"/"SIMULATOR"/"IP_NAME".sh` +followed by `//.sh` All verification work is located under the [verif](./verif) directory. Please see the [Verification](#verification) section for the CL_TEMPLATE verification details. ### STEP 4: Develop Software Tests (OPTIONAL) -CL_TEMPLATE does not yet support stand alone software tests. Please refer to other examples such as [CL_DRAM_HBM_DMA](./../cl_dram_hbm_dma#software) +CL_TEMPLATE does not yet support standalone software tests. Please refer to other examples such as [CL_DRAM_HBM_DMA](./../cl_dram_hbm_dma/README.md#software) ### STEP 5: Build and Deploy the Design -Once design files have been added and tested, constraint and build script updates need to be made. The build flow creates a bitstream that is used to create an AFI to deploy on hardware. The build and deployment flows can be found in the [Quick Start Guide](./../../../../README.md#setup-the-development-environment-and-sdk-design-flow). Examples for all constraint files and build scripts can be found in other examples such as [CL_DRAM_HBM_DMA](./../cl_dram_hbm_dma/build). +Once design files have been added and tested, constraint and build script updates need to be made. The build flow creates a bitstream that is used to create an AFI to deploy on hardware. The build and deployment flows can be found in the [Quick Start Guide](./../../../../User_Guide_AWS_EC2_FPGA_Development_Kit.md#getting-started). Examples for all constraint files and build scripts can be found in other examples such as [CL_DRAM_HBM_DMA](./../cl_dram_hbm_dma/build). 1. Populate existing and/or add new constraint files to [./build/constraints](./build/constraints) - AWS has provided basic constraints required in example designs in [$AWS_FPGA_REPO_DIR/hdk/common/shell_stable/build/constraints](./../../../common/shell_stable/build/constraints) diff --git a/hdk/cl/examples/CL_TEMPLATE/build/constraints/cl_synth_user.xdc b/hdk/cl/examples/CL_TEMPLATE/build/constraints/cl_synth_user.xdc index 94c355965..91047cc17 100644 --- a/hdk/cl/examples/CL_TEMPLATE/build/constraints/cl_synth_user.xdc +++ b/hdk/cl/examples/CL_TEMPLATE/build/constraints/cl_synth_user.xdc @@ -1 +1,19 @@ +# ============================================================================= +# Amazon FPGA Hardware Development Kit +# +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + + # Add synthesis constraint here diff --git a/hdk/cl/examples/CL_TEMPLATE/build/constraints/cl_timing_user.xdc b/hdk/cl/examples/CL_TEMPLATE/build/constraints/cl_timing_user.xdc index d169aee57..85447a669 100644 --- a/hdk/cl/examples/CL_TEMPLATE/build/constraints/cl_timing_user.xdc +++ b/hdk/cl/examples/CL_TEMPLATE/build/constraints/cl_timing_user.xdc @@ -1,2 +1,19 @@ +# ============================================================================= +# Amazon FPGA Hardware Development Kit +# +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + # Add timing constraints here diff --git a/hdk/cl/examples/CL_TEMPLATE/build/constraints/small_shell_cl_pnr_user.xdc b/hdk/cl/examples/CL_TEMPLATE/build/constraints/small_shell_cl_pnr_user.xdc index ab2308b91..6d223426c 100644 --- a/hdk/cl/examples/CL_TEMPLATE/build/constraints/small_shell_cl_pnr_user.xdc +++ b/hdk/cl/examples/CL_TEMPLATE/build/constraints/small_shell_cl_pnr_user.xdc @@ -1 +1,19 @@ +# ============================================================================= +# Amazon FPGA Hardware Development Kit +# +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + + # Add Small_Shell P&R constraints here diff --git a/hdk/cl/examples/CL_TEMPLATE/build/constraints/xdma_shell_cl_pnr_user.xdc b/hdk/cl/examples/CL_TEMPLATE/build/constraints/xdma_shell_cl_pnr_user.xdc index 60e34ee0e..4110d612d 100644 --- a/hdk/cl/examples/CL_TEMPLATE/build/constraints/xdma_shell_cl_pnr_user.xdc +++ b/hdk/cl/examples/CL_TEMPLATE/build/constraints/xdma_shell_cl_pnr_user.xdc @@ -1 +1,19 @@ +# ============================================================================= +# Amazon FPGA Hardware Development Kit +# +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + + # Add XDMA_Shell P&R constraints here diff --git a/hdk/cl/examples/CL_TEMPLATE/build/scripts/synth_CL_TEMPLATE.tcl b/hdk/cl/examples/CL_TEMPLATE/build/scripts/synth_CL_TEMPLATE.tcl index 9bf9f3870..9e1e380fc 100644 --- a/hdk/cl/examples/CL_TEMPLATE/build/scripts/synth_CL_TEMPLATE.tcl +++ b/hdk/cl/examples/CL_TEMPLATE/build/scripts/synth_CL_TEMPLATE.tcl @@ -1,17 +1,19 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2022 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is # located at # # http://aws.amazon.com/asl/ -#` +# # or in the "license" file accompanying this file. This file is distributed on # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= # Common header diff --git a/hdk/cl/examples/CL_TEMPLATE/design/CL_TEMPLATE.sv b/hdk/cl/examples/CL_TEMPLATE/design/CL_TEMPLATE.sv index e8d4ecf08..45722edb5 100644 --- a/hdk/cl/examples/CL_TEMPLATE/design/CL_TEMPLATE.sv +++ b/hdk/cl/examples/CL_TEMPLATE/design/CL_TEMPLATE.sv @@ -1,7 +1,7 @@ -//==================================================================================== +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2023 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -13,6 +13,9 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + + //==================================================================================== // Top level module file for CL_TEMPLATE //==================================================================================== diff --git a/hdk/cl/examples/CL_TEMPLATE/design/CL_TEMPLATE_defines.vh b/hdk/cl/examples/CL_TEMPLATE/design/CL_TEMPLATE_defines.vh index 5f5885675..f796d4eec 100644 --- a/hdk/cl/examples/CL_TEMPLATE/design/CL_TEMPLATE_defines.vh +++ b/hdk/cl/examples/CL_TEMPLATE/design/CL_TEMPLATE_defines.vh @@ -1,3 +1,21 @@ +// ============================================================================ +// Amazon FPGA Hardware Development Kit +// +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// +// Licensed under the Amazon Software License (the "License"). You may not use +// this file except in compliance with the License. A copy of the License is +// located at +// +// http://aws.amazon.com/asl/ +// +// or in the "license" file accompanying this file. This file is distributed on +// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +// implied. See the License for the specific language governing permissions and +// limitations under the License. +// ============================================================================ + + `ifndef CL_TEMPLATE_DEFINES `define CL_TEMPLATE_DEFINES diff --git a/hdk/cl/examples/CL_TEMPLATE/design/cl_id_defines.vh b/hdk/cl/examples/CL_TEMPLATE/design/cl_id_defines.vh index c8922856c..abe97995d 100644 --- a/hdk/cl/examples/CL_TEMPLATE/design/cl_id_defines.vh +++ b/hdk/cl/examples/CL_TEMPLATE/design/cl_id_defines.vh @@ -1,3 +1,21 @@ +// ============================================================================ +// Amazon FPGA Hardware Development Kit +// +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// +// Licensed under the Amazon Software License (the "License"). You may not use +// this file except in compliance with the License. A copy of the License is +// located at +// +// http://aws.amazon.com/asl/ +// +// or in the "license" file accompanying this file. This file is distributed on +// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +// implied. See the License for the specific language governing permissions and +// limitations under the License. +// ============================================================================ + + `ifndef CL_ID_DEFINES `define CL_ID_DEFINES diff --git a/hdk/cl/examples/CL_TEMPLATE/verif/scripts/Makefile b/hdk/cl/examples/CL_TEMPLATE/verif/scripts/Makefile index 6fba0eedf..094fa0505 100644 --- a/hdk/cl/examples/CL_TEMPLATE/verif/scripts/Makefile +++ b/hdk/cl/examples/CL_TEMPLATE/verif/scripts/Makefile @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2023 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= + ifndef HDK_COMMON_DIR $(error Environment variable HDK_COMMON_DIR not set. Please source hdk_setup.sh) diff --git a/hdk/cl/examples/CL_TEMPLATE/verif/scripts/Makefile.tests b/hdk/cl/examples/CL_TEMPLATE/verif/scripts/Makefile.tests index 2b80a19be..19e72ca26 100644 --- a/hdk/cl/examples/CL_TEMPLATE/verif/scripts/Makefile.tests +++ b/hdk/cl/examples/CL_TEMPLATE/verif/scripts/Makefile.tests @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2023 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= + # Adds an easy make target that sets $TEST and runs the all (compile & run) target CL_TEMPLATE_base_test: TEST=CL_TEMPLATE_base_test diff --git a/hdk/cl/examples/CL_TEMPLATE/verif/scripts/top.questa.f b/hdk/cl/examples/CL_TEMPLATE/verif/scripts/top.questa.f index 3897d312c..19b477767 100644 --- a/hdk/cl/examples/CL_TEMPLATE/verif/scripts/top.questa.f +++ b/hdk/cl/examples/CL_TEMPLATE/verif/scripts/top.questa.f @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2023 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= + +define+CL_NAME=CL_TEMPLATE +define+DISABLE_VJTAG_DEBUG diff --git a/hdk/cl/examples/CL_TEMPLATE/verif/scripts/top.vcs.f b/hdk/cl/examples/CL_TEMPLATE/verif/scripts/top.vcs.f index 3897d312c..19b477767 100644 --- a/hdk/cl/examples/CL_TEMPLATE/verif/scripts/top.vcs.f +++ b/hdk/cl/examples/CL_TEMPLATE/verif/scripts/top.vcs.f @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2023 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= + +define+CL_NAME=CL_TEMPLATE +define+DISABLE_VJTAG_DEBUG diff --git a/hdk/cl/examples/CL_TEMPLATE/verif/scripts/top.xsim.f b/hdk/cl/examples/CL_TEMPLATE/verif/scripts/top.xsim.f index 2569f54b0..47e1f8c38 100644 --- a/hdk/cl/examples/CL_TEMPLATE/verif/scripts/top.xsim.f +++ b/hdk/cl/examples/CL_TEMPLATE/verif/scripts/top.xsim.f @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2023 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= + -define CL_NAME=CL_TEMPLATE -define DISABLE_VJTAG_DEBUG diff --git a/hdk/cl/examples/CL_TEMPLATE/verif/scripts/waves.tcl b/hdk/cl/examples/CL_TEMPLATE/verif/scripts/waves.tcl index 6cb7c4c73..ce36f21fd 100644 --- a/hdk/cl/examples/CL_TEMPLATE/verif/scripts/waves.tcl +++ b/hdk/cl/examples/CL_TEMPLATE/verif/scripts/waves.tcl @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2023 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= + set curr_wave [current_wave_config] if { [string length $curr_wave] == 0 } { @@ -23,5 +26,5 @@ if { [string length $curr_wave] == 0 } { } } -run all +run all quit diff --git a/hdk/cl/examples/CL_TEMPLATE/verif/tests/CL_TEMPLATE_base_test.sv b/hdk/cl/examples/CL_TEMPLATE/verif/tests/CL_TEMPLATE_base_test.sv index 7ff82e660..fa22d7a5d 100644 --- a/hdk/cl/examples/CL_TEMPLATE/verif/tests/CL_TEMPLATE_base_test.sv +++ b/hdk/cl/examples/CL_TEMPLATE/verif/tests/CL_TEMPLATE_base_test.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2023 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + `include "common_base_test.svh" diff --git a/hdk/cl/examples/cl_dram_hbm_dma/README.md b/hdk/cl/examples/cl_dram_hbm_dma/README.md index 6c8ac7af1..fc9f74237 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/README.md +++ b/hdk/cl/examples/cl_dram_hbm_dma/README.md @@ -8,26 +8,23 @@ 2. [Functional Description](#functionalDescription) 3. [Software](#software) - # Overview The CL_DRAM_HBM_DMA example demonstrates the use and connectivity for many of the Shell/CL interfaces and functionality, including: -1) Register Access over OCL AXI-Lite interface +1) Register access over OCL AXI-Lite interface 2) Mapping of the external DRAM channel to instance memory via PCIe AppPF BAR4, and the 512-bit `sh_cl_dma_pcis_*` AXI4 bus 3) Mapping of HBM memory to instance memory via PCIe AppPF BAR4, and the 512-bit `sh_cl_dma_pcis_*` AXI4 bus -4) Virtual JTAG (**Virtual JTAG is not currently supported**) and Xilinx Integrated Logic Analyzer cores +4) Debugging using Virtual JTAG and Xilinx Integrated Logic Analyzer (ILA) cores. 5) User-defined interrupts 6) `cl_sh_pcim_*` AXI4 traffic for host memory accesses from CL - - ### System diagram ![Diagram](design/cl_dram_hbm_dma.png) @@ -37,13 +34,13 @@ The CL_DRAM_HBM_DMA example demonstrates the use and connectivity for many of th # Functional Description ### Memory Interface -The cl_dram_hbm_dma demonstrates accessing 64GiB of DDR memory and 16GiB of single channel HBM memory over `sh_cl_dma_pcis` AXI4 bus. +The cl_dram_hbm_dma demonstrates accessing 64GB of DDR memory and 16GB of single channel HBM memory over the `sh_cl_dma_pcis` AXI4 bus. The CL provides access to the DDR memory through `sh_ddr.sv` which consists of the DDR controller required to interact with the external DDR DIMM on the FPGA card. The `sh_ddr.sv` is also connected to the Shell's `sh_cl_ddr_stat_*` ports to enable Shell to manage DDR calibration upon CL AFI loads. -The CL also provides access to the on-chip HBM available in the FPGA. The HBM IP is configured for dual stack 16GiB capacity which exposes 32 AXI3 (not AXI4) channels running on 450MHz clock. However, only one HBM channel is being used in this example design to demonstrate datapath connection to the HBM. The [cl_hbm_axi4.sv](./design/cl_hbm_axi4.sv) does the AXI4-to-AXI3 conversion, crosses clock domain between `clk_main_a0` and HBM's 450 MHz `axi_clk` for the datapath and feeds the `cl_hbm_wrapper.sv`. The [cl_hbm_wrapper.sv](./design/cl_hbm_wrapper.sv) instantiates the HBM IP, houses MMCM to generate 450MHz interface clock, and connects the datapath to Channel#0 of the HBM IP core. +The CL also provides access to the on-chip HBM available in the FPGA. The HBM IP is configured for dual stack 16GB capacity which exposes 32 AXI3 (not AXI4) channels running on 450MHz clock. However, only one HBM channel is being used in this example design to demonstrate datapath connection to the HBM. The [cl_hbm_axi4.sv](./design/cl_hbm_axi4.sv) does the AXI4-to-AXI3 conversion, crosses clock domain between the 250 MHz `clk_main_a0` and HBM's up to 450 MHz `axi_clk` for the datapath and feeds the `cl_hbm_wrapper.sv`. The [cl_hbm_wrapper.sv](./design/cl_hbm_wrapper.sv) instantiates the HBM IP, houses MMCM to generate 450MHz interface clock, and connects the datapath to Channel#0 of the HBM IP core. -**NOTE:** Since the CL utilizes only one HBM Channel which is fed by data source running at 250MHz clock, it does not accomplish the max available bandwidth from HBM. AWS will provide another example design to demonstrate max performance from HBM. +**NOTE:** Since the CL utilizes only one HBM Channel which is fed by data source running at 250MHz clock, it does not accomplish the max available bandwidth from HBM. For demonstration of the max performance from HBM. refer to the [cl_mem_per](../cl_mem_perf/README.md) example. ### Design Changes @@ -62,22 +59,24 @@ If DDR is enabled, make sure that the DDRs are initialized using the poke_stat c eg: To initialize DDR +```verilog tb.poke_stat(.addr(8'h0c), .ddr_idx(0), .data(32'h0000_0000)); +``` Make sure that the Host to Card and Card to Host DMA transfers only access enabled DDR controller address space. ### dma_pcis AXI4 bus -sh\_cl\_dma\_pcis exposes a address windows of 128GiB matching AppPF BAR4. +sh\_cl\_dma\_pcis exposes a address windows of 128GB matching AppPF BAR4. -This memory space is mapped to the 64GiB DRAM space and 16GiB HBM space. -An axi_crossbar interconnects the incomming addres requests to the target memories as shown below: -* DDR base_addr=0x00_0000_0000 | range=64GiB -* HBM base_addr=0x10_0000_0000 | range=16GiB +This memory space is mapped to the 64GB DRAM space and 16GB HBM space. +An axi_crossbar interconnects the incoming address requests to the target memories as shown below: +* DDR base_addr=0x00_0000_0000 (range=64GB) +* HBM base_addr=0x10_0000_0000 (range=16GB) -**NOTE**: Please refer to [Supported_DDR_Modes.md](./../../../docs/Supported_DDR_Modes.md) for details on supported DDR configurations in `sh_ddr.sv`. +**NOTE**: Please refer to [Supported DDR Modes](./../../../docs/Supported_DDR_Modes.md) for details on supported DDR configurations in `sh_ddr.sv`. ### ocl\_ AXI-Lite @@ -147,9 +146,7 @@ This test runs a software test with data transfer with both DDR and HBM enabled ```bash cd ${CL_DIR}/software/runtime - make all - sudo ./test_dram_hbm_dma ``` @@ -161,9 +158,7 @@ This test runs a software test with HW/SW co-simulation enabled with both DDR an ```bash cd ${CL_DIR}/software/runtime - make TEST=test_dram_hbm_dma_hwsw_cosim - sudo ./test_dram_hbm_dma_hwsw_cosim ``` @@ -171,6 +166,5 @@ The test can be simulated with XSIM as follows. ```bash cd ${CL_DIR}/verif/scripts - make C_TEST=test_dram_hbm_dma_hwsw_cosim ``` diff --git a/hdk/cl/examples/cl_dram_hbm_dma/build/constraints/cl_synth_user.xdc b/hdk/cl/examples/cl_dram_hbm_dma/build/constraints/cl_synth_user.xdc index a9a115428..160f6090c 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/build/constraints/cl_synth_user.xdc +++ b/hdk/cl/examples/cl_dram_hbm_dma/build/constraints/cl_synth_user.xdc @@ -1,3 +1,21 @@ +# ============================================================================= +# Amazon FPGA Hardware Development Kit +# +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + + ############################################################################### # This contains the CL specific constraints for synthesis at the CL leve ############################################################################### diff --git a/hdk/cl/examples/cl_dram_hbm_dma/build/constraints/cl_timing_user.xdc b/hdk/cl/examples/cl_dram_hbm_dma/build/constraints/cl_timing_user.xdc index 45d22f6aa..49212ee53 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/build/constraints/cl_timing_user.xdc +++ b/hdk/cl/examples/cl_dram_hbm_dma/build/constraints/cl_timing_user.xdc @@ -1,3 +1,21 @@ +# ============================================================================= +# Amazon FPGA Hardware Development Kit +# +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + + ############################################################################### # This contains the CL specific timing constraints for CL ############################################################################### diff --git a/hdk/cl/examples/cl_dram_hbm_dma/build/constraints/small_shell_cl_pnr_user.xdc b/hdk/cl/examples/cl_dram_hbm_dma/build/constraints/small_shell_cl_pnr_user.xdc index bfa49af7c..a193ff036 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/build/constraints/small_shell_cl_pnr_user.xdc +++ b/hdk/cl/examples/cl_dram_hbm_dma/build/constraints/small_shell_cl_pnr_user.xdc @@ -1,11 +1,20 @@ # ============================================================================= -# Copyright 2021 Amazon.com, Inc. or its affiliates. -# All Rights Reserved Worldwide. -# Amazon Confidential information -# Restricted NDA Material +# Amazon FPGA Hardware Development Kit +# +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. # ============================================================================= - # Level 1 CL_DRAM_HBM_DMA floorplan for Small Shell diff --git a/hdk/cl/examples/cl_dram_hbm_dma/build/constraints/xdma_shell_cl_pnr_user.xdc b/hdk/cl/examples/cl_dram_hbm_dma/build/constraints/xdma_shell_cl_pnr_user.xdc index cd0fcd32b..85c471f7f 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/build/constraints/xdma_shell_cl_pnr_user.xdc +++ b/hdk/cl/examples/cl_dram_hbm_dma/build/constraints/xdma_shell_cl_pnr_user.xdc @@ -1,11 +1,20 @@ # ============================================================================= -# Copyright 2021 Amazon.com, Inc. or its affiliates. -# All Rights Reserved Worldwide. -# Amazon Confidential information -# Restricted NDA Material +# Amazon FPGA Hardware Development Kit +# +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. # ============================================================================= - # Level 1 CL_DRAM_HBM_DMA floorplan for XDMA Shell diff --git a/hdk/cl/examples/cl_dram_hbm_dma/build/scripts/encrypt.tcl b/hdk/cl/examples/cl_dram_hbm_dma/build/scripts/encrypt.tcl index 924d670f8..bc38f8812 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/build/scripts/encrypt.tcl +++ b/hdk/cl/examples/cl_dram_hbm_dma/build/scripts/encrypt.tcl @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= + # TODO: # Add check if CL_DIR and HDK_SHELL_DIR directories exist diff --git a/hdk/cl/examples/cl_dram_hbm_dma/build/scripts/synth_cl_dram_hbm_dma.tcl b/hdk/cl/examples/cl_dram_hbm_dma/build/scripts/synth_cl_dram_hbm_dma.tcl index ba12aed1e..e03d8978f 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/build/scripts/synth_cl_dram_hbm_dma.tcl +++ b/hdk/cl/examples/cl_dram_hbm_dma/build/scripts/synth_cl_dram_hbm_dma.tcl @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= # Common header diff --git a/hdk/cl/examples/cl_dram_hbm_dma/design/axil_slave.sv b/hdk/cl/examples/cl_dram_hbm_dma/design/axil_slave.sv index b056ff5f5..06e098e2a 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/design/axil_slave.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/design/axil_slave.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,43 +13,45 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + module axil_slave ( input clk, input rst_n, - input awvalid, - input[63:0] awaddr, - output logic awready, - - //Write data - input wvalid, - input[31:0] wdata, - input[3:0] wstrb, - output logic wready, - - //Write response - output logic bvalid, + input awvalid, + input[63:0] awaddr, + output logic awready, + + //Write data + input wvalid, + input[31:0] wdata, + input[3:0] wstrb, + output logic wready, + + //Write response + output logic bvalid, output logic[1:0] bresp, input bready, - + //Read address - input arvalid, - input[63:0] araddr, + input arvalid, + input[63:0] araddr, output logic arready, - + //Read data/response - output logic rvalid, + output logic rvalid, output logic[31:0] rdata, output logic[1:0] rresp, - + input rready ); logic[63:0] awaddr_q; logic arvalid_q; -// Does not work when awvalid and wvalid are asserted at the same time +// Does not work when awvalid and wvalid are asserted at the same time //assign awready = !wvalid; //assign wready = !arvalid; // @@ -57,7 +60,7 @@ logic arvalid_q; // awaddr_q <= 0; // else if (awvalid && awready) // awaddr_q <= awaddr; -// +// //always_ff @(negedge rst_n or posedge clk) // if (!rst_n) // begin @@ -73,7 +76,7 @@ logic arvalid_q; logic wr_active; logic [63:0] wr_addr; - + always_ff @(negedge rst_n or posedge clk) if (!rst_n) begin wr_active <= 0; @@ -88,18 +91,18 @@ logic arvalid_q; assign awready = ~wr_active; assign wready = wr_active && wvalid; - + always_ff @(negedge rst_n or posedge clk) - if (!rst_n) + if (!rst_n) bvalid <= 0; else - bvalid <= bvalid && bready ? 1'b0 : + bvalid <= bvalid && bready ? 1'b0 : ~bvalid && wready ? 1'b1 : bvalid; assign bresp = 0; - + assign arready = !arvalid_q && !rvalid; - + always_ff @(negedge rst_n or posedge clk) if (!rst_n) arvalid_q <= 0; @@ -121,7 +124,7 @@ always_ff @(negedge rst_n or posedge clk) rdata <= 0; rresp <= 0; end - else if (arvalid_q) + else if (arvalid_q) begin rvalid <= 1; rdata <= ram_rdata; @@ -149,5 +152,3 @@ bram_2rw #(.WIDTH(32), .ADDR_WIDTH(8), .DEPTH(256) ) AXIL_RAM ( ); endmodule - - diff --git a/hdk/cl/examples/cl_dram_hbm_dma/design/cl_dma_pcis_slv.sv b/hdk/cl/examples/cl_dram_hbm_dma/design/cl_dma_pcis_slv.sv index a006f8b28..fc78d6034 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/design/cl_dma_pcis_slv.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/design/cl_dma_pcis_slv.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + module cl_dma_pcis_slv #( diff --git a/hdk/cl/examples/cl_dram_hbm_dma/design/cl_dram_dma_axi_mstr.sv b/hdk/cl/examples/cl_dram_hbm_dma/design/cl_dram_dma_axi_mstr.sv index f030c31ac..d41e8e539 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/design/cl_dram_dma_axi_mstr.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/design/cl_dram_dma_axi_mstr.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + // ----------------------------------------------------------------------------- // This module is an example of how to master transactions on a master port diff --git a/hdk/cl/examples/cl_dram_hbm_dma/design/cl_dram_dma_defines.vh b/hdk/cl/examples/cl_dram_hbm_dma/design/cl_dram_dma_defines.vh index 39f554e5c..a4bc494fa 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/design/cl_dram_dma_defines.vh +++ b/hdk/cl/examples/cl_dram_hbm_dma/design/cl_dram_dma_defines.vh @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + `ifndef CL_DRAM_DMA_DEFINES `define CL_DRAM_DMA_DEFINES diff --git a/hdk/cl/examples/cl_dram_hbm_dma/design/cl_dram_dma_pkg.sv b/hdk/cl/examples/cl_dram_hbm_dma/design/cl_dram_dma_pkg.sv index 8f28d2dfa..b50c9f1ae 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/design/cl_dram_dma_pkg.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/design/cl_dram_dma_pkg.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + `ifndef CL_DRAM_DMA_PKG `define CL_DRAM_DMA_PKG diff --git a/hdk/cl/examples/cl_dram_hbm_dma/design/cl_dram_hbm_dma.sv b/hdk/cl/examples/cl_dram_hbm_dma/design/cl_dram_hbm_dma.sv index ec947bb25..eb45a4a53 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/design/cl_dram_hbm_dma.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/design/cl_dram_hbm_dma.sv @@ -1,7 +1,7 @@ -//============================================================================= +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -13,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + //============================================================================= // Top level module file for CL_DRAM_HBM_DMA diff --git a/hdk/cl/examples/cl_dram_hbm_dma/design/cl_hbm_axi4.sv b/hdk/cl/examples/cl_dram_hbm_dma/design/cl_hbm_axi4.sv index ee6933a18..c998d5c40 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/design/cl_hbm_axi4.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/design/cl_hbm_axi4.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,13 +13,15 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ -//============================================================================= + +// ============================================================================ // CL_HBM_AXI4 // -------- // - Convert 512b 250MHz AXI4 to 450MHz AXI3 bus to feed into HBM // - Instantiate HBM Wrapper -//============================================================================= +// ============================================================================ module cl_hbm_axi4 #( diff --git a/hdk/cl/examples/cl_dram_hbm_dma/design/cl_hbm_wrapper.sv b/hdk/cl/examples/cl_dram_hbm_dma/design/cl_hbm_wrapper.sv index 10cd5ab0f..357fea11a 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/design/cl_hbm_wrapper.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/design/cl_hbm_wrapper.sv @@ -1,7 +1,7 @@ -//------------------------------------------------------------------------------------------------------------------------------- +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -13,9 +13,10 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. -// Restricted NDA Material -//------------------------------------------------------------------------------------------------------------------------------- -//=============================================================================================================================== +// ============================================================================ + + +// ============================================================================ // HBM Wrapper // - Wraper for HBM IP // - Implements an MMCM to generate 100MHz and 450MHz clock for the HBM IP. @@ -26,7 +27,6 @@ // by setting parameter AXI4_INTERFACE=1 // - Unused HBM ports are automatically tied off. // - Stats interface to reset the HBM, status check for HBM initialization. -// //------------------------------------------ // HBM Stats Interface Reset Routine: // // Issue HBM soft reset @@ -34,9 +34,7 @@ // write 0x0 @ addr 0x00 // // Poll for lock // poll bits[3:1] = 3'b111 @ addr 0x00 -// -// -//=============================================================================================================================== +// ============================================================================ module cl_hbm_wrapper #( diff --git a/hdk/cl/examples/cl_dram_hbm_dma/design/cl_id_defines.vh b/hdk/cl/examples/cl_dram_hbm_dma/design/cl_id_defines.vh index d957c7093..30faa2608 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/design/cl_id_defines.vh +++ b/hdk/cl/examples/cl_dram_hbm_dma/design/cl_id_defines.vh @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + // CL_SH_ID0 // - PCIe Vendor/Device ID Values @@ -29,5 +32,3 @@ // 15: 0: PCIe Subsystem Vendor ID // - A PCIe Subsystem/Subsystem Vendor ID of 0 (zero) is not valid `define CL_SH_ID1 32'h1D51_FEDC - - diff --git a/hdk/cl/examples/cl_dram_hbm_dma/design/cl_ila.sv b/hdk/cl/examples/cl_dram_hbm_dma/design/cl_ila.sv index e5f72271f..ce549ab6d 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/design/cl_ila.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/design/cl_ila.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + module cl_ila #( parameter DDR_A_PRESENT = 1) ( @@ -35,9 +38,9 @@ module cl_ila #( parameter DDR_A_PRESENT = 1) ( ); -//---------------------------- +//---------------------------- // Debug bridge -//---------------------------- +//---------------------------- cl_debug_bridge CL_DEBUG_BRIDGE ( .clk(aclk), .S_BSCAN_drck(drck), @@ -55,9 +58,9 @@ module cl_ila #( parameter DDR_A_PRESENT = 1) ( ); -//---------------------------- -// Debug Core ILA for dmm pcis AXI4 interface -//---------------------------- +//---------------------------- +// Debug Core ILA for dmm pcis AXI4 interface +//---------------------------- ila_1 CL_DMA_ILA_0 ( .clk (aclk), .probe0 (sh_cl_dma_pcis_q.awvalid), @@ -83,7 +86,7 @@ module cl_ila #( parameter DDR_A_PRESENT = 1) ( .probe20 (sh_cl_dma_pcis_q.arid), .probe21 (sh_cl_dma_pcis_q.awlen), .probe22 (sh_cl_dma_pcis_q.rlast), - .probe23 (3'b0), + .probe23 (3'b0), .probe24 (sh_cl_dma_pcis_q.rresp), .probe25 (sh_cl_dma_pcis_q.rid), .probe26 (sh_cl_dma_pcis_q.rvalid), @@ -109,9 +112,9 @@ generate begin:ddr_A_hookup if (DDR_A_PRESENT == 1) begin -//---------------------------- -// Debug Core ILA for DDRA AXI4 interface monitoring -//---------------------------- +//---------------------------- +// Debug Core ILA for DDRA AXI4 interface monitoring +//---------------------------- ila_1 CL_DDRA_ILA_0 ( .clk (aclk), .probe0 (lcl_cl_sh_ddra.awvalid), @@ -137,7 +140,7 @@ ila_1 CL_DDRA_ILA_0 ( .probe20 (lcl_cl_sh_ddra.arid[4:0]), .probe21 (lcl_cl_sh_ddra.awlen), .probe22 (lcl_cl_sh_ddra.rlast), - .probe23 (3'b0), + .probe23 (3'b0), .probe24 (lcl_cl_sh_ddra.rresp), .probe25 (lcl_cl_sh_ddra.rid[4:0]), .probe26 (lcl_cl_sh_ddra.rvalid), @@ -164,4 +167,3 @@ end //if(DDR_A_PRESET) end //label endgenerate endmodule - diff --git a/hdk/cl/examples/cl_dram_hbm_dma/design/cl_int_slv.sv b/hdk/cl/examples/cl_dram_hbm_dma/design/cl_int_slv.sv index 4e3892462..6b5a6947b 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/design/cl_int_slv.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/design/cl_int_slv.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + module cl_int_slv ( diff --git a/hdk/cl/examples/cl_dram_hbm_dma/design/cl_int_tst.sv b/hdk/cl/examples/cl_dram_hbm_dma/design/cl_int_tst.sv index 4bbee64cf..17abb970f 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/design/cl_int_tst.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/design/cl_int_tst.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + // CL Interrupt Test @@ -36,26 +39,26 @@ module cl_int_tst input sh_cl_msix_int_sent, input sh_cl_msix_int_ack `endif - + ); logic [7:0] cfg_vec_num; logic cfg_wr_stretch; logic cfg_rd_stretch; - + logic [7:0] cfg_addr_q; //Only care about lower 8-bits of address, upper bits are decoded somewhere else logic [31:0] cfg_wdata_q; logic [31:0] int_cfg_rdata; - - + + always_ff @(negedge rst_n or posedge clk) if (!rst_n) begin cfg_wr_stretch <= 0; cfg_rd_stretch <= 0; cfg_addr_q <= 0; - cfg_wdata_q <= 0; + cfg_wdata_q <= 0; end else begin @@ -70,44 +73,44 @@ module cl_int_tst //Readback mux always_ff @(negedge rst_n or posedge clk) - if (!rst_n) + if (!rst_n) tst_cfg_rdata <= 0; else tst_cfg_rdata <= int_cfg_rdata; - + //Ack for cycle always_ff @(negedge rst_n or posedge clk) if (!rst_n) tst_cfg_ack <= 0; else - tst_cfg_ack <= ((cfg_wr_stretch||cfg_rd_stretch) && !tst_cfg_ack); - + tst_cfg_ack <= ((cfg_wr_stretch||cfg_rd_stretch) && !tst_cfg_ack); + `ifndef NO_XDMA logic [15:0] int_ack; logic [15:0] int_trig; logic [15:0] int_wait; logic [15:0] int_done; - + // Addr 0x0 - Control Register // Bit 15:0 - Trigger (Write) / Interrupt Waiting (Read) // Bit 31:16 - Interrupt Done (W1C) assign int_cfg_rdata = {int_done, int_wait}; - - lib_pipe #(.WIDTH(32), .STAGES(4)) PIPE_IN (.clk (clk), - .rst_n (rst_n), + + lib_pipe #(.WIDTH(32), .STAGES(4)) PIPE_IN (.clk (clk), + .rst_n (rst_n), .in_bus({int_trig, sh_cl_irq_ack}), .out_bus({cl_sh_irq_req, int_ack}) ); - - - // Create the Edge + + + // Create the Edge always_ff @(negedge rst_n or posedge clk) if (!rst_n) int_trig <= '{default:'0}; else - for (int idx = 0; idx < 16; idx++) + for (int idx = 0; idx < 16; idx++) int_trig[idx] <= int_trig[idx] ? 1'b0 : cfg_wr_stretch && (cfg_addr_q[7:0] == 8'd0) && cfg_wdata_q[idx] ? 1'b1 : int_trig[idx]; @@ -117,7 +120,7 @@ module cl_int_tst if (!rst_n) int_wait <= '{default:'0}; else - for (int idx = 0; idx < 16; idx++) + for (int idx = 0; idx < 16; idx++) int_wait[idx] <= int_trig[idx] ? 1'b1 : int_wait[idx] && int_ack[idx] ? 1'b0 : int_wait[idx]; @@ -126,22 +129,22 @@ module cl_int_tst if (!rst_n) int_done <= '{default:'0}; else - for (int idx = 0; idx < 16; idx++) + for (int idx = 0; idx < 16; idx++) int_done[idx] <= int_trig[idx] ? 1'b0 : - cfg_wr_stretch && (cfg_addr_q[7:0] == 8'd0) && cfg_wdata_q[16+idx] ? 1'b0 : + cfg_wr_stretch && (cfg_addr_q[7:0] == 8'd0) && cfg_wdata_q[16+idx] ? 1'b0 : int_wait[idx] && int_ack[idx] ? 1'b1 : int_done[idx]; - - + + `else // !`ifndef NO_XDMA - + logic int_ack; logic int_sent; logic int_trig; logic int_wait; logic int_done; logic int_not_sent; - + // Addr 0x0 - Control Register // Bit 0 - Trigger Interrupt (WO) @@ -153,29 +156,29 @@ module cl_int_tst // Bit 31 - ACK (W1C) assign int_cfg_rdata = {int_done, int_not_sent, int_wait, 13'd0, cfg_vec_num[7:0], 8'd0}; - + // Pipeline inputs - lib_pipe #(.WIDTH(2), .STAGES(4)) PIPE_IN (.clk (clk), - .rst_n (rst_n), + lib_pipe #(.WIDTH(2), .STAGES(4)) PIPE_IN (.clk (clk), + .rst_n (rst_n), .in_bus({sh_cl_msix_int_ack, sh_cl_msix_int_sent}), .out_bus({int_ack, int_sent}) ); // Pipeline outputs - lib_pipe #(.WIDTH(8+1), .STAGES(4)) PIPE_OUT (.clk (clk), - .rst_n (rst_n), + lib_pipe #(.WIDTH(8+1), .STAGES(4)) PIPE_OUT (.clk (clk), + .rst_n (rst_n), .in_bus({int_trig, cfg_vec_num}), .out_bus({cl_sh_msix_int, cl_sh_msix_vec}) ); - + always_ff @(negedge rst_n or posedge clk) if (!rst_n) cfg_vec_num[7:0] <= 8'd0; else cfg_vec_num[7:0] <= cfg_wr_stretch && (cfg_addr_q[7:0] == 8'd0) ? cfg_wdata_q[15:8] : cfg_vec_num[7:0]; - // Create the Edge + // Create the Edge always_ff @(negedge rst_n or posedge clk) if (!rst_n) int_trig <= 1'b0; @@ -197,7 +200,7 @@ module cl_int_tst if (!rst_n) int_done <= 1'b0; else - int_done <= int_trig ? 1'b0 : + int_done <= int_trig ? 1'b0 : int_wait && int_ack ? 1'b1 : cfg_wr_stretch && (cfg_addr_q[7:0] == 8'd0) && cfg_wdata_q[31] ? 1'b0 : int_done; @@ -209,7 +212,7 @@ module cl_int_tst int_not_sent <= int_wait && int_ack ? ~int_sent : cfg_wr_stretch && (cfg_addr_q[7:0] == 8'd0) && cfg_wdata_q[30] ? 1'b0 : int_not_sent; - + `endif // !`ifndef NO_XDMA - + endmodule // cl_int_tst diff --git a/hdk/cl/examples/cl_dram_hbm_dma/design/cl_ocl_slv.sv b/hdk/cl/examples/cl_dram_hbm_dma/design/cl_ocl_slv.sv index 00c294735..c17a0e12e 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/design/cl_ocl_slv.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/design/cl_ocl_slv.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + module cl_ocl_slv ( diff --git a/hdk/cl/examples/cl_dram_hbm_dma/design/cl_pcim_mstr.sv b/hdk/cl/examples/cl_dram_hbm_dma/design/cl_pcim_mstr.sv index de96f4271..3dac3e017 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/design/cl_pcim_mstr.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/design/cl_pcim_mstr.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + module cl_pcim_mstr ( input aclk, diff --git a/hdk/cl/examples/cl_dram_hbm_dma/design/cl_sda_slv.sv b/hdk/cl/examples/cl_dram_hbm_dma/design/cl_sda_slv.sv index 84ee130a2..8e1c92122 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/design/cl_sda_slv.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/design/cl_sda_slv.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + module cl_sda_slv ( @@ -47,23 +50,23 @@ axi_bus_t sda_cl_q(); .s_axi_rresp (sda_cl_bus.rresp), .s_axi_rvalid (sda_cl_bus.rvalid), .s_axi_rready (sda_cl_bus.rready), - - .m_axi_awaddr (sda_cl_q.awaddr[31:0]), + + .m_axi_awaddr (sda_cl_q.awaddr[31:0]), .m_axi_awvalid (sda_cl_q.awvalid), .m_axi_awready (sda_cl_q.awready), - .m_axi_wdata (sda_cl_q.wdata[31:0]), + .m_axi_wdata (sda_cl_q.wdata[31:0]), .m_axi_wstrb (sda_cl_q.wstrb[3:0]), - .m_axi_wvalid (sda_cl_q.wvalid), - .m_axi_wready (sda_cl_q.wready), - .m_axi_bresp (sda_cl_q.bresp), - .m_axi_bvalid (sda_cl_q.bvalid), - .m_axi_bready (sda_cl_q.bready), - .m_axi_araddr (sda_cl_q.araddr[31:0]), + .m_axi_wvalid (sda_cl_q.wvalid), + .m_axi_wready (sda_cl_q.wready), + .m_axi_bresp (sda_cl_q.bresp), + .m_axi_bvalid (sda_cl_q.bvalid), + .m_axi_bready (sda_cl_q.bready), + .m_axi_araddr (sda_cl_q.araddr[31:0]), .m_axi_arvalid (sda_cl_q.arvalid), .m_axi_arready (sda_cl_q.arready), - .m_axi_rdata (sda_cl_q.rdata[31:0]), - .m_axi_rresp (sda_cl_q.rresp), - .m_axi_rvalid (sda_cl_q.rvalid), + .m_axi_rdata (sda_cl_q.rdata[31:0]), + .m_axi_rresp (sda_cl_q.rresp), + .m_axi_rvalid (sda_cl_q.rvalid), .m_axi_rready (sda_cl_q.rready) ); @@ -73,30 +76,29 @@ axi_bus_t sda_cl_q(); axil_slave AXIL_SLAVE( .clk(aclk), .rst_n(aresetn), - - .awvalid(sda_cl_q.awvalid), + + .awvalid(sda_cl_q.awvalid), .awaddr({54'b0, sda_cl_q.awaddr[9:0]}), .awready(sda_cl_q.awready), - + .wvalid(sda_cl_q.wvalid), .wdata(sda_cl_q.wdata[31:0]), .wstrb(sda_cl_q.wstrb[3:0]), .wready(sda_cl_q.wready), - - .bvalid(sda_cl_q.bvalid), + + .bvalid(sda_cl_q.bvalid), .bresp(sda_cl_q.bresp), .bready(sda_cl_q.bready), - + .arvalid(sda_cl_q.arvalid), .araddr({54'b0, sda_cl_q.araddr[9:0]}), .arready(sda_cl_q.arready), - + .rvalid(sda_cl_q.rvalid), .rdata(sda_cl_q.rdata[31:0]), .rresp(sda_cl_q.rresp), - + .rready(sda_cl_q.rready) ); endmodule - diff --git a/hdk/cl/examples/cl_dram_hbm_dma/design/cl_tst.sv b/hdk/cl/examples/cl_dram_hbm_dma/design/cl_tst.sv index 3adfddb1f..5affc0a12 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/design/cl_tst.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/design/cl_tst.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ module cl_tst #(parameter DATA_WIDTH=512, parameter NUM_RD_TAG=512) ( diff --git a/hdk/cl/examples/cl_dram_hbm_dma/design/cl_tst_scrb.sv b/hdk/cl/examples/cl_dram_hbm_dma/design/cl_tst_scrb.sv index 418d40ef0..72d1fdd98 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/design/cl_tst_scrb.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/design/cl_tst_scrb.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + module cl_tst_scrb #(parameter DATA_WIDTH=512, NUM_RD_TAG=512, @@ -70,7 +73,7 @@ module cl_tst_scrb #(parameter DATA_WIDTH=512, output slv_rvalid, output [10:0] slv_ruser, input logic slv_rready, - + output logic [15:0] awid, output logic [63:0] awaddr, output logic [7:0] awlen, @@ -153,22 +156,22 @@ module cl_tst_scrb #(parameter DATA_WIDTH=512, scrb_enable_q <= 1'b0; else scrb_enable_q <= scrb_enable; - + // Instance mem_scrb - mem_scrb + mem_scrb #(.DATA_WIDTH(DATA_WIDTH), .ID_WIDTH (6), .USER_WIDTH(11), .BURST_LEN_MINUS1 (SCRB_BURST_LEN_MINUS1), .MAX_ADDR(SCRB_MAX_ADDR) - ) + ) MEM_SCRB ( - + .clk(clk), .rst_n(rst_n), .awid(scrb_awid), - .awaddr(scrb_awaddr), + .awaddr(scrb_awaddr), .awlen(scrb_awlen), .awvalid(scrb_awvalid), .awuser(scrb_awuser), @@ -198,7 +201,7 @@ module cl_tst_scrb #(parameter DATA_WIDTH=512, .dbg_state(scrb_dbg_state), .dbg_addr (scrb_dbg_addr) - + ); end // block: gen_scrb_inst @@ -223,12 +226,12 @@ module cl_tst_scrb #(parameter DATA_WIDTH=512, assign scrb_aruser = '{default:'0}; assign scrb_arready = '{default:'0}; assign scrb_rready = '{default:'0}; - + end // block: gen_noscrb - + endgenerate - - + + // Instance cl_tst logic [8:0] atg_awid; logic [63:0] atg_awaddr; @@ -270,7 +273,7 @@ module cl_tst_scrb #(parameter DATA_WIDTH=512, cl_tst #(.DATA_WIDTH(DATA_WIDTH), .NUM_RD_TAG(NUM_RD_TAG) ) CL_TST ( - + .clk(clk), .rst_n(rst_n), @@ -282,9 +285,9 @@ module cl_tst_scrb #(parameter DATA_WIDTH=512, .tst_cfg_rdata(tst_cfg_rdata), .atg_enable(atg_enable), - + .awid(atg_awid), - .awaddr(atg_awaddr), + .awaddr(atg_awaddr), .awlen(atg_awlen), .awvalid(atg_awvalid), .awuser(atg_awuser), @@ -320,47 +323,47 @@ module cl_tst_scrb #(parameter DATA_WIDTH=512, ); -assign awid = scrb_enable ? {10'h0, scrb_awid} : +assign awid = scrb_enable ? {10'h0, scrb_awid} : atg_enable ? {7'h0, atg_awid} : slv_awid; -assign awaddr = scrb_enable ? scrb_awaddr : +assign awaddr = scrb_enable ? scrb_awaddr : atg_enable ? atg_awaddr : slv_awaddr; -assign awlen = scrb_enable ? scrb_awlen : +assign awlen = scrb_enable ? scrb_awlen : atg_enable ? atg_awlen : slv_awlen ; -assign awsize = scrb_enable ? 3'b110 : +assign awsize = scrb_enable ? 3'b110 : atg_enable ? 3'b110 : slv_awsize ; -assign awvalid = scrb_enable ? scrb_awvalid : +assign awvalid = scrb_enable ? scrb_awvalid : atg_enable ? atg_awvalid : slv_awvalid; -assign awuser = scrb_enable ? scrb_awuser : +assign awuser = scrb_enable ? scrb_awuser : atg_enable ? atg_awuser : slv_awuser; assign atg_awready = atg_enable & awready ; assign scrb_awready = scrb_enable & awready ; assign slv_awready = ~atg_enable & ~scrb_enable & awready; -assign wid = scrb_enable ? scrb_wid : +assign wid = scrb_enable ? scrb_wid : atg_enable ? atg_wid : {2'b0, slv_wid} ; -assign wdata = scrb_enable ? scrb_wdata : +assign wdata = scrb_enable ? scrb_wdata : atg_enable ? atg_wdata : slv_wdata; -assign wstrb = scrb_enable ? scrb_wstrb : +assign wstrb = scrb_enable ? scrb_wstrb : atg_enable ? atg_wstrb : slv_wstrb; -assign wlast = scrb_enable ? scrb_wlast : +assign wlast = scrb_enable ? scrb_wlast : atg_enable ? atg_wlast : slv_wlast; -assign wvalid = scrb_enable ? scrb_wvalid : +assign wvalid = scrb_enable ? scrb_wvalid : atg_enable ? atg_wvalid : slv_wvalid; assign atg_wready = atg_enable & wready ; assign scrb_wready = scrb_enable & wready ; assign slv_wready = ~atg_enable & ~scrb_enable & wready; - + assign atg_bid = bid[8:0] ; assign atg_bresp = bresp ; assign atg_bvalid = atg_enable & bvalid; @@ -373,26 +376,26 @@ assign slv_bid = bid ; assign slv_bresp = bresp ; assign slv_bvalid = ~scrb_enable & ~atg_enable & bvalid; assign slv_buser = buser[10:0] ; -assign bready = scrb_enable ? scrb_bready : +assign bready = scrb_enable ? scrb_bready : atg_enable ? atg_bready : slv_bready; -assign arid = scrb_enable ? {10'b0, scrb_arid} : +assign arid = scrb_enable ? {10'b0, scrb_arid} : atg_enable ? {7'b0, atg_arid} : slv_arid; -assign araddr = scrb_enable ? scrb_araddr : +assign araddr = scrb_enable ? scrb_araddr : atg_enable ? atg_araddr : slv_araddr; -assign arlen = scrb_enable ? scrb_arlen : +assign arlen = scrb_enable ? scrb_arlen : atg_enable ? atg_arlen : slv_arlen; assign arsize = scrb_enable ? 3'b110 : atg_enable ? 3'b110 : slv_arsize; -assign arvalid = scrb_enable ? scrb_arvalid : +assign arvalid = scrb_enable ? scrb_arvalid : atg_enable ? atg_arvalid : slv_arvalid; -assign aruser = scrb_enable ? scrb_aruser : +assign aruser = scrb_enable ? scrb_aruser : atg_enable ? atg_aruser : slv_aruser; assign atg_arready = atg_enable & arready ; @@ -417,10 +420,8 @@ assign slv_rresp = rresp ; assign slv_rlast = rlast ; assign slv_rvalid = ~scrb_enable & ~atg_enable & rvalid; assign slv_ruser = ruser[10:0] ; -assign rready = scrb_enable ? scrb_rready : +assign rready = scrb_enable ? scrb_rready : atg_enable ? atg_rready : slv_rready; - -endmodule // cl_tst_scrb - +endmodule // cl_tst_scrb diff --git a/hdk/cl/examples/cl_dram_hbm_dma/design/cl_vio.sv b/hdk/cl/examples/cl_dram_hbm_dma/design/cl_vio.sv index 66050937c..c82e8e4b3 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/design/cl_vio.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/design/cl_vio.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + module cl_vio ( input clk_extra_a1 @@ -19,7 +22,7 @@ module cl_vio ( ); // Counter running at 125MHz - + logic vo_cnt_enable; logic vo_cnt_load; logic vo_cnt_clear; @@ -40,7 +43,7 @@ module cl_vio ( logic vi_cnt_ge_watermark; logic [7:0] vi_tick_cnt = 0; logic [15:0] vi_cnt = 0; - + // Tick counter and main counter always @(posedge clk_extra_a1) begin @@ -66,9 +69,9 @@ module cl_vio ( vi_tick = (vi_tick_cnt >= vo_tick_value_q); vi_cnt_ge_watermark = (vi_cnt >= vo_cnt_watermark_q); - + end // always @ (posedge clk_extra_a1) - + vio_0 CL_VIO_0 ( .clk (clk_extra_a1), @@ -84,7 +87,7 @@ module cl_vio ( .probe_out5 (vo_cnt_load_value), .probe_out6 (vo_cnt_watermark) ); - + ila_vio_counter CL_VIO_ILA ( .clk (clk_extra_a1), .probe0 (vi_tick), @@ -102,4 +105,3 @@ module cl_vio ( endmodule - diff --git a/hdk/cl/examples/cl_dram_hbm_dma/design/mem_scrb.sv b/hdk/cl/examples/cl_dram_hbm_dma/design/mem_scrb.sv index bd0d11f6c..97c843fa0 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/design/mem_scrb.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/design/mem_scrb.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ module mem_scrb @@ -26,7 +28,7 @@ module mem_scrb ( input clk, input rst_n, - + //------------------------------------------------------ // DDR-4 Interface from CL (AXI-4) //------------------------------------------------------ @@ -61,37 +63,37 @@ module mem_scrb output logic scrb_done, output logic [2:0] dbg_state, - output logic [ADDR_WIDTH-1:0] dbg_addr + output logic [ADDR_WIDTH-1:0] dbg_addr ); localparam DATA_WIDTH_BYTES = DATA_WIDTH/8; - + typedef enum logic [2:0] {FSM_IDLE = 3'd0, FSM_START = 3'd1, FSM_AW = 3'd2, FSM_W = 3'd3, FSM_B = 3'd4, FSM_DONE = 3'd5} fsm_state_t; - + fsm_state_t curr_state; fsm_state_t next_state; logic [ADDR_WIDTH-1:0] curr_addr; logic [15:0] num_txn; logic scrb_enable_q; - + always_ff @(posedge clk or negedge rst_n) if (!rst_n) scrb_enable_q <= 1'b0; else scrb_enable_q <= scrb_enable; - + always_ff @(posedge clk or negedge rst_n) if (!rst_n) curr_state <= FSM_IDLE; - else + else curr_state <= ~scrb_enable_q ? FSM_IDLE : next_state; - + always_comb case (curr_state) FSM_IDLE : next_state = scrb_enable_q ? FSM_START : FSM_IDLE; @@ -108,7 +110,7 @@ module mem_scrb if (!rst_n) curr_addr <= {ADDR_WIDTH{1'b0}}; else - curr_addr <= (curr_state == FSM_START) ? ({ADDR_WIDTH{1'b0}}) : + curr_addr <= (curr_state == FSM_START) ? ({ADDR_WIDTH{1'b0}}) : (curr_state == FSM_W) && wready ? curr_addr + DATA_WIDTH_BYTES : curr_addr; always_ff @(posedge clk or negedge rst_n) @@ -117,7 +119,7 @@ module mem_scrb else num_txn <= (curr_state == FSM_AW) ? 16'd0 : (curr_state == FSM_W) && wready ? num_txn + 16'd1 : num_txn; - + assign awvalid = (curr_state == FSM_AW); assign awaddr = curr_addr; assign awid = {ID_WIDTH{1'b0}}; @@ -129,7 +131,7 @@ module mem_scrb assign wstrb = {(DATA_WIDTH/8){1'b1}}; assign wdata = {DATA_WIDTH{1'b0}}; assign wlast = (num_txn == BURST_LEN_MINUS1); - + assign arvalid = 1'b0; assign araddr = {ADDR_WIDTH{1'b0}}; assign arid = {ID_WIDTH{1'b0}}; @@ -143,19 +145,11 @@ module mem_scrb if (!rst_n) scrb_done <= 1'b0; else - scrb_done <= (curr_state == FSM_IDLE) ? 1'b0: + scrb_done <= (curr_state == FSM_IDLE) ? 1'b0: (curr_state == FSM_DONE) ? 1'b1 : scrb_done; // Debug outputs assign dbg_state = curr_state; assign dbg_addr = curr_addr; - -endmodule // mem_scrb - - - - - - - +endmodule // mem_scrb diff --git a/hdk/cl/examples/cl_dram_hbm_dma/software/include/cl_dram_dma.h b/hdk/cl/examples/cl_dram_hbm_dma/software/include/cl_dram_dma.h index c35a76f66..7d7a29f97 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/software/include/cl_dram_dma.h +++ b/hdk/cl/examples/cl_dram_hbm_dma/software/include/cl_dram_dma.h @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -11,4 +12,5 @@ // or in the "license" file accompanying this file. This file is distributed on // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and -// limitations under the License. \ No newline at end of file +// limitations under the License. +// ============================================================================ diff --git a/hdk/cl/examples/cl_dram_hbm_dma/software/include/sh_dpi_tasks.h b/hdk/cl/examples/cl_dram_hbm_dma/software/include/sh_dpi_tasks.h index 9c7a39127..f74162e62 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/software/include/sh_dpi_tasks.h +++ b/hdk/cl/examples/cl_dram_hbm_dma/software/include/sh_dpi_tasks.h @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + #ifndef SH_DPI_TASKS #define SH_DPI_TASKS diff --git a/hdk/cl/examples/cl_dram_hbm_dma/software/runtime/Makefile b/hdk/cl/examples/cl_dram_hbm_dma/software/runtime/Makefile index 2dc5335b4..c8e6d6438 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/software/runtime/Makefile +++ b/hdk/cl/examples/cl_dram_hbm_dma/software/runtime/Makefile @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= + INCLUDES = -I$(SDK_DIR)/userspace/include diff --git a/hdk/cl/examples/cl_dram_hbm_dma/software/runtime/test_dram_dma_common.c b/hdk/cl/examples/cl_dram_hbm_dma/software/runtime/test_dram_dma_common.c index c6ff7c088..79b0410a7 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/software/runtime/test_dram_dma_common.c +++ b/hdk/cl/examples/cl_dram_hbm_dma/software/runtime/test_dram_dma_common.c @@ -1,19 +1,20 @@ -/* - * Amazon FPGA Hardware Development Kit - * - * Copyright 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Licensed under the Amazon Software License (the "License"). You may not use - * this file except in compliance with the License. A copy of the License is - * located at - * - * http://aws.amazon.com/asl/ - * - * or in the "license" file accompanying this file. This file is distributed on - * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or - * implied. See the License for the specific language governing permissions and - * limitations under the License. - */ +// ============================================================================ +// Amazon FPGA Hardware Development Kit +// +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// +// Licensed under the Amazon Software License (the "License"). You may not use +// this file except in compliance with the License. A copy of the License is +// located at +// +// http://aws.amazon.com/asl/ +// +// or in the "license" file accompanying this file. This file is distributed on +// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +// implied. See the License for the specific language governing permissions and +// limitations under the License. +// ============================================================================ + #include #include @@ -71,7 +72,7 @@ uint64_t buffer_compare(uint8_t *bufa, uint8_t *bufb, size_t i; uint64_t differ = 0; for (i = 0; i < buffer_size; ++i) { - + if (bufa[i] != bufb[i]) { differ += 1; } diff --git a/hdk/cl/examples/cl_dram_hbm_dma/software/runtime/test_dram_dma_common.h b/hdk/cl/examples/cl_dram_hbm_dma/software/runtime/test_dram_dma_common.h index 6fd188728..62018c60a 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/software/runtime/test_dram_dma_common.h +++ b/hdk/cl/examples/cl_dram_hbm_dma/software/runtime/test_dram_dma_common.h @@ -1,19 +1,20 @@ -/* - * Amazon FPGA Hardware Development Kit - * - * Copyright 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Licensed under the Amazon Software License (the "License"). You may not use - * this file except in compliance with the License. A copy of the License is - * located at - * - * http://aws.amazon.com/asl/ - * - * or in the "license" file accompanying this file. This file is distributed on - * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or - * implied. See the License for the specific language governing permissions and - * limitations under the License. - */ +// ============================================================================ +// Amazon FPGA Hardware Development Kit +// +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// +// Licensed under the Amazon Software License (the "License"). You may not use +// this file except in compliance with the License. A copy of the License is +// located at +// +// http://aws.amazon.com/asl/ +// +// or in the "license" file accompanying this file. This file is distributed on +// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +// implied. See the License for the specific language governing permissions and +// limitations under the License. +// ============================================================================ + #pragma once diff --git a/hdk/cl/examples/cl_dram_hbm_dma/software/runtime/test_dram_dma_hwsw_cosim.c b/hdk/cl/examples/cl_dram_hbm_dma/software/runtime/test_dram_dma_hwsw_cosim.c index 230148e29..b0983b4d0 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/software/runtime/test_dram_dma_hwsw_cosim.c +++ b/hdk/cl/examples/cl_dram_hbm_dma/software/runtime/test_dram_dma_hwsw_cosim.c @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + #include #include @@ -62,7 +65,7 @@ int test_main(uint32_t *exit_code) #elif defined(SV_TEST) void test_main(uint32_t *exit_code) -#else +#else int main(int argc, char **argv) #endif diff --git a/hdk/cl/examples/cl_dram_hbm_dma/software/runtime/test_dram_hbm_dma.c b/hdk/cl/examples/cl_dram_hbm_dma/software/runtime/test_dram_hbm_dma.c index 2a25131c8..b9d58cbda 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/software/runtime/test_dram_hbm_dma.c +++ b/hdk/cl/examples/cl_dram_hbm_dma/software/runtime/test_dram_hbm_dma.c @@ -1,19 +1,20 @@ -/* - * Amazon FPGA Hardware Development Kit - * - * Copyright 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Licensed under the Amazon Software License (the "License"). You may not use - * this file except in compliance with the License. A copy of the License is - * located at - * - * http://aws.amazon.com/asl/ - * - * or in the "license" file accompanying this file. This file is distributed on - * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or - * implied. See the License for the specific language governing permissions and - * limitations under the License. - */ +// ============================================================================ +// Amazon FPGA Hardware Development Kit +// +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// +// Licensed under the Amazon Software License (the "License"). You may not use +// this file except in compliance with the License. A copy of the License is +// located at +// +// http://aws.amazon.com/asl/ +// +// or in the "license" file accompanying this file. This file is distributed on +// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +// implied. See the License for the specific language governing permissions and +// limitations under the License. +// ============================================================================ + #include #include diff --git a/hdk/cl/examples/cl_dram_hbm_dma/software/src/test_dram_dma.c b/hdk/cl/examples/cl_dram_hbm_dma/software/src/test_dram_dma.c index 8b230ba34..acbb39c30 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/software/src/test_dram_dma.c +++ b/hdk/cl/examples/cl_dram_hbm_dma/software/src/test_dram_dma.c @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + #include #include diff --git a/hdk/cl/examples/cl_dram_hbm_dma/software/src/test_null.c b/hdk/cl/examples/cl_dram_hbm_dma/software/src/test_null.c index 6532ab75c..04c278623 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/software/src/test_null.c +++ b/hdk/cl/examples/cl_dram_hbm_dma/software/src/test_null.c @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2023 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ #include diff --git a/hdk/cl/examples/cl_dram_hbm_dma/verif/README.md b/hdk/cl/examples/cl_dram_hbm_dma/verif/README.md index 517f04a04..400acf4e8 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/verif/README.md +++ b/hdk/cl/examples/cl_dram_hbm_dma/verif/README.md @@ -1,8 +1,45 @@ -This readme provides information about the simulation environment for the cl_dram_hbm_dma example. For more details about overall HDK simulation environment and CL bringup in simulation please refer to the [RTL Simulation Guide for HDK Design Flow](../../../../docs/RTL_Simulation_Guide_for_HDK_Design_Flow.md) - -# DRAM HBM DMA CL example simulation - -The system verilog simulation tests can be run from the [$CL_DIR/verif/scripts](./scripts) directory with all supported simulators (HBM is only supported in VCS & QUESTA). You can run tests by calling the make target for that test located in [$CL_DIR/verif/scripts/Makefile.tests](./scripts/Makefile.tests): +# CL_DRAM_HBM_DMA Example Simulation + +## Table of Contents + +- [CL\_DRAM\_HBM\_DMA Example Simulation](#cl_dram_hbm_dma-example-simulation) + - [Table of Contents](#table-of-contents) + - [Overview](#overview) + - [Dump Waves](#dump-waves) + - [SystemVerliog Tests](#systemverliog-tests) + - [test\_clk\_recipe.sv](#test_clk_recipesv) + - [test\_ddr\_peek\_poke.sv](#test_ddr_peek_pokesv) + - [test\_ddr.sv](#test_ddrsv) + - [test\_hbm.sv](#test_hbmsv) + - [test\_dram\_dma.sv](#test_dram_dmasv) + - [test\_dram\_dma\_rnd.sv](#test_dram_dma_rndsv) + - [test\_dma\_pcim\_concurrent.sv](#test_dma_pcim_concurrentsv) + - [test\_dma\_pcis\_concurrent.sv](#test_dma_pcis_concurrentsv) + - [test\_dma\_sda\_concurrent.sv](#test_dma_sda_concurrentsv) + - [test\_dram\_dma\_4k\_crossing.sv](#test_dram_dma_4k_crossingsv) + - [test\_dram\_dma\_allgn\_addr\_4k.sv](#test_dram_dma_allgn_addr_4ksv) + - [test\_dram\_dma\_single\_beat\_4k.sv](#test_dram_dma_single_beat_4ksv) + - [test\_dram\_dma\_axi\_mstr.sv](#test_dram_dma_axi_mstrsv) + - [test\_int.sv](#test_intsv) + - [test\_peek\_poke.sv](#test_peek_pokesv) + - [test\_peek\_poke\_wc.sv](#test_peek_poke_wcsv) + - [test\_peek\_poke\_len.sv](#test_peek_poke_lensv) + - [test\_peek\_poke\_rnd\_lengths.sv](#test_peek_poke_rnd_lengthssv) + - [test\_peek\_poke\_pcis\_axsize.sv](#test_peek_poke_pcis_axsizesv) + - [test\_ddr\_peek\_bdr\_walking\_ones](#test_ddr_peek_bdr_walking_ones) + - [test\_sda.sv](#test_sdasv) + - [test\_null.sv](#test_nullsv) + - [AXI\_MEMORY\_MODEL Mode Simulations](#axi_memory_model-mode-simulations) + - [test\_dram\_dma\_mem\_model\_bdr\_wr](#test_dram_dma_mem_model_bdr_wr) + - [test\_dram\_dma\_mem\_model\_bdr\_rd](#test_dram_dma_mem_model_bdr_rd) + - [DDR Backdoor Loading](#ddr-backdoor-loading) + - [HW/SW Co-Simulation Test](#hwsw-co-simulation-test) + +## Overview + +This readme provides information about the simulation environment for the `cl_dram_hbm_dma` example. For more details about overall HDK simulation environment and CL bringup in simulation please refer to the [RTL Simulation Guide for HDK Design Flow](../../../../docs/RTL_Simulation_Guide_for_HDK_Design_Flow.md) + +SystemVerilog (SV) simulations can be run from the `$CL_DIR/verif/scripts/` directory with all supported simulators (HBM simulation using VCS & QUESTA is strongly recommended). You can run tests by calling the make target for that test located in `$CL_DIR/verif/scripts/Makefile.tests`: ```bash make test_ddr # Runs with XSIM by default @@ -12,21 +49,15 @@ make test_ddr QUESTA=1 make test_hbm # Runs with VCS by default ``` -Alternatively, you can run each test by setting TEST= followed by the environment variables required to run that test. - -**NOTE: CL_DRAM_HBM_DMA does not currently have a datapath to all 64 GB of DDR. Only the first 32GB is accessible.** - +Alternatively, you can run each test by setting `TEST=\` followed by the environment variables required to run that test. ```bash make TEST=test_dram_dma # Runs with XSIM by default make TEST=test_dram_dma VCS=1 make TEST=test_dram_dma QUESTA=1 -# To Run simulations with a 32 GB DDR DIMM (without user-controlled auto-precharge mode) -make TEST=test_dram_dma USE_32GB_DDR_DIMM=1 - -# To Run simulations with a 32 GB DDR DIMM (with user-controlled auto-precharge mode) -make TEST=test_dram_dma USE_AP_32GB_DDR_DIMM=1 +# To Run simulations with a 64 GB DDR DIMM (with user-controlled auto-precharge mode) +make TEST=test_dram_dma USE_AP_64GB_DDR_DIMM=1 # To Run Simulations in AXI_MEMORY_MODEL mode make TEST=test_dram_dma AXI_MEMORY_MODEL=1 # Runs with XSIM by default in AXI_MEMORY_MODEL mode @@ -46,7 +77,7 @@ test_ddr_peek_bdr_walking_ones **NOTE**: Please refer to [Supported_DDR_Modes.md](./../../../../docs/Supported_DDR_Modes.md) for details on supported DDR configurations. -The HW/SW co-simulation tests can be run from the [verif/scripts](scripts) directory with all supported simulators: +The HW/SW co-simulation tests can be run from the `verif/scripts/` directory with all supported simulators: ```bash make C_TEST=test_dram_dma_hwsw_cosim # Runs with XSIM by default @@ -66,9 +97,9 @@ Note that the appropriate simulators must be installed. For information about how to dump waves with XSIM or VCS, please refer to [debugging-custom-logic-using-the-aws-hdk](../../../../docs/RTL_Simulation_Guide_for_HDK_Design_Flow.md#) -## System Verliog Tests +## SystemVerliog Tests -The system verilog tests are located at [verif/tests](tests). Most tests include `base_test_utils.svh` which includes common signals and tasks used across tests. Please refer to this file for the DPI-C tasks used. Information about each test can be found below. +The SystemVerilog test cases are located at `verif/tests/`. Most tests include `base_test_utils.svh` which includes common signals and tasks used across tests. Please refer to this file for the DPI-C tasks used. Information about each test can be found below. ### test_clk_recipe.sv This test programs valid clock recipes defined within and verifies the corresponding clock frequencies. @@ -127,18 +158,6 @@ This test programs tester block to do PCIM reads and writes with random lengths ### test_peek_poke_pcis_axsize.sv This test does PCIS peek and poke with different sizes. Although shell model allows different size transfers on PCIS interface, Shell only supports transfer of size 6 on PCIS interface. -## _AXI_MEMORY_MODEL mode simulations_ -AXI_MEMORY_MODEL mode can be used for better simulation perfornmance. AXI_MEMORY_MODEL mode enables a test to run with AXI memory models instead of DDR memory. The documentation can be found in AXI memory model section at [RTL simulation guide](../../../../docs/RTL_Simulation_Guide_for_HDK_Design_Flow.md). Any test that accesses DDR memory can be run in AXI_MEMORY_MODEL mode. Below are some example tests for ECC and backdoor loading support features of AXI memory model. - -### test_dram_dma_mem_model_bdr_wr -This test backdoor writes AXI memory model, reads through frontdoor and checks that the data matches. - -### test_dram_dma_mem_model_bdr_rd -This test backdoor reads AXI memory model, writes through frontdoor and checks that the data matches. - -## _DDR backdoor loading_ -The tests below use backdoor loading to populate DDR memory. The description of DDR backdoor loading can be found in DDR backdoor loading support section at [RTL simulation guide](../../../../docs/RTL_Simulation_Guide_for_HDK_Design_Flow.md). - ### test_ddr_peek_bdr_walking_ones DDR test which uses backdoor loading to populate DDR memory. The test writes data(walking ones) for different addresses. The test backdoor loads DDR memory and reads through frontdoor and checks that the data matches. @@ -146,22 +165,22 @@ DDR test which uses backdoor loading to populate DDR memory. The test writes dat This test does transfers to different addresses on SDA AXIL interface. ### test_null.sv -test_null is not an actual test. This is a base system verilog file needed for HW/SW co-simulation +test_null is not an actual test. This is a base SV file needed for HW/SW co-simulation -## HW/SW co-simulation Test +## AXI_MEMORY_MODEL Mode Simulations -The software test with HW/SW co-simulation support [test_dram_dma_hwsw_cosim.c](../software/runtime/test_dram_dma_hwsw_cosim.c) can be found at [software/runtime](../software/runtime). For Information about how HW/SW co-simulation support can be added to a software test please refer to "Code changes to enable HW/SW co-simulation" section in [RTL simulation guide](../../../../docs/RTL_Simulation_Guide_for_HDK_Design_Flow.md). +AXI_MEMORY_MODEL mode can be used for better simulation performance. AXI_MEMORY_MODEL mode enables a test to run with AXI memory models instead of DDR memory. The documentation can be found in AXI memory model section at [RTL simulation guide](../../../../docs/RTL_Simulation_Guide_for_HDK_Design_Flow.md). Any test that accesses DDR memory can be run in AXI_MEMORY_MODEL mode. Below are some example tests for ECC and backdoor loading support features of AXI memory model. -## Regressions +### test_dram_dma_mem_model_bdr_wr +This test backdoor writes AXI memory model, reads through frontdoor and checks that the data matches. -A regression with full coverage can be run with the following commands +### test_dram_dma_mem_model_bdr_rd +This test backdoor reads AXI memory model, writes through frontdoor and checks that the data matches. -```bash -make regression =1 -make regression AXI_MEMORY_MODEL=1 =1 -make regression ECC_DIRECT=1 =1 -make regression ECC_RAND=1 =1 -make regression DDR_BKDR=1 =1 -make regression AXI_MEMORY_MODEL=1 ECC_DIRECT=1 =1 -make regression AXI_MEMORY_MODEL=1 ECC_RAND=1 =1 -``` +## DDR Backdoor Loading + +The description of DDR backdoor loading can be found in DDR backdoor loading support section at [RTL simulation guide](../../../../docs/RTL_Simulation_Guide_for_HDK_Design_Flow.md). + +## HW/SW Co-Simulation Test + +The software test with HW/SW co-simulation support [test_dram_dma_hwsw_cosim.c](../software/runtime/test_dram_dma_hwsw_cosim.c) can be found at `software/runtime/`. For Information about how HW/SW co-simulation support can be added to a software test please refer to "Code changes to enable HW/SW co-simulation" section in [RTL simulation guide](../../../../docs/RTL_Simulation_Guide_for_HDK_Design_Flow.md). diff --git a/hdk/cl/examples/cl_dram_hbm_dma/verif/scripts/Makefile b/hdk/cl/examples/cl_dram_hbm_dma/verif/scripts/Makefile index 2f8667c36..0d3cc12a0 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/verif/scripts/Makefile +++ b/hdk/cl/examples/cl_dram_hbm_dma/verif/scripts/Makefile @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= + ifndef HDK_COMMON_DIR $(error Environment variable HDK_COMMON_DIR not set. Please source hdk_setup.sh) diff --git a/hdk/cl/examples/cl_dram_hbm_dma/verif/scripts/Makefile.tests b/hdk/cl/examples/cl_dram_hbm_dma/verif/scripts/Makefile.tests index c12c1fc2d..ae44fb2bd 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/verif/scripts/Makefile.tests +++ b/hdk/cl/examples/cl_dram_hbm_dma/verif/scripts/Makefile.tests @@ -1,7 +1,25 @@ +# ============================================================================= +# Amazon FPGA Hardware Development Kit +# +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + + test_dram_dma_axi_mstr: TEST=test_dram_dma_axi_mstr test_dram_dma_axi_mstr: all -#Not supporting until XSIM related issues fixed +#Not supporting until XSIM related issues fixed test_dram_dma_4k_crossing: TEST=test_dram_dma_4k_crossing test_dram_dma_4k_crossing: check_xsim all diff --git a/hdk/cl/examples/cl_dram_hbm_dma/verif/scripts/top.questa.f b/hdk/cl/examples/cl_dram_hbm_dma/verif/scripts/top.questa.f index 24b74ff8a..6eff88d80 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/verif/scripts/top.questa.f +++ b/hdk/cl/examples/cl_dram_hbm_dma/verif/scripts/top.questa.f @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2023 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= + +define+CL_NAME=cl_dram_hbm_dma +define+DISABLE_VJTAG_DEBUG diff --git a/hdk/cl/examples/cl_dram_hbm_dma/verif/scripts/top.vcs.f b/hdk/cl/examples/cl_dram_hbm_dma/verif/scripts/top.vcs.f index 24b74ff8a..6eff88d80 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/verif/scripts/top.vcs.f +++ b/hdk/cl/examples/cl_dram_hbm_dma/verif/scripts/top.vcs.f @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2023 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= + +define+CL_NAME=cl_dram_hbm_dma +define+DISABLE_VJTAG_DEBUG diff --git a/hdk/cl/examples/cl_dram_hbm_dma/verif/scripts/top.vivado.f b/hdk/cl/examples/cl_dram_hbm_dma/verif/scripts/top.vivado.f index dc916e85a..26402da32 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/verif/scripts/top.vivado.f +++ b/hdk/cl/examples/cl_dram_hbm_dma/verif/scripts/top.vivado.f @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= + --define VIVADO_SIM diff --git a/hdk/cl/examples/cl_dram_hbm_dma/verif/scripts/top.xsim.f b/hdk/cl/examples/cl_dram_hbm_dma/verif/scripts/top.xsim.f index 9338ac7a5..3cfc285ff 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/verif/scripts/top.xsim.f +++ b/hdk/cl/examples/cl_dram_hbm_dma/verif/scripts/top.xsim.f @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2023 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= + -define CL_NAME=cl_dram_hbm_dma -define DISABLE_VJTAG_DEBUG diff --git a/hdk/cl/examples/cl_dram_hbm_dma/verif/scripts/waves.tcl b/hdk/cl/examples/cl_dram_hbm_dma/verif/scripts/waves.tcl index 4b14d0da6..584895d66 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/verif/scripts/waves.tcl +++ b/hdk/cl/examples/cl_dram_hbm_dma/verif/scripts/waves.tcl @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= + set curr_wave [current_wave_config] if { [string length $curr_wave] == 0 } { @@ -23,5 +26,5 @@ if { [string length $curr_wave] == 0 } { } } -run 200 us +run 200 us quit diff --git a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/base_test_utils.svh b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/base_test_utils.svh index b1a2eaca1..b6062699e 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/base_test_utils.svh +++ b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/base_test_utils.svh @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ `include "common_base_test.svh" @@ -23,9 +25,4 @@ `define DDR_LEVEL_3 `_24_GB `define HBM_BASE_ADDR `_32_GB -`ifdef AWS_SIM_64GB_DDR - $fatal(1, "CL_DRAM_HBM_DMA does not yet support 64GB DDR simulations"); -`endif - `include "cl_dram_hbm_dma_utils.svh" - diff --git a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/cl_dram_hbm_dma_utils.svh b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/cl_dram_hbm_dma_utils.svh index f2548ce71..a7c517164 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/cl_dram_hbm_dma_utils.svh +++ b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/cl_dram_hbm_dma_utils.svh @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2023 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ task initialize_ddr(); diff --git a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_clk_recipe.sv b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_clk_recipe.sv index 8dc7cde9a..49512147f 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_clk_recipe.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_clk_recipe.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,8 +13,7 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. -// Description: This test tests that the different clock recipes generated by -// shell model are accurate. +// ============================================================================ module test_clk_recipe(); @@ -25,32 +25,32 @@ module test_clk_recipe(); $display("power up with Clock Recipe A0, B0, C0 \n"); //power up with Clock Recipe A0, B0, C0 - tb.power_up(.clk_recipe_a(ClockRecipe::A0), - .clk_recipe_b(ClockRecipe::B0), + tb.power_up(.clk_recipe_a(ClockRecipe::A0), + .clk_recipe_b(ClockRecipe::B0), .clk_recipe_c(ClockRecipe::C0)); // delay before checking the clocks #500ns; - + //Starts checking clock frequency. tb.set_chk_clk_freq(.chk_freq(1'b1)); - + #2000ns; //Stop checking clock frequency. tb.set_chk_clk_freq(.chk_freq(1'b0)); - + // Power down tb.power_down(); #500ns; //power up with Clock Recipe A1, B0, C0 $display("power up with Clock Recipe A1, B0, C0 \n"); - tb.power_up(.clk_recipe_a(ClockRecipe::A1), - .clk_recipe_b(ClockRecipe::B0), + tb.power_up(.clk_recipe_a(ClockRecipe::A1), + .clk_recipe_b(ClockRecipe::B0), .clk_recipe_c(ClockRecipe::C0)); - + // delay before checking the clocks #500ns; @@ -61,17 +61,17 @@ module test_clk_recipe(); //Stop checking clock frequency. tb.set_chk_clk_freq(.chk_freq(1'b0)); - + tb.power_down(); #500ns; //power up with Clock Recipe A2, B1, C0 $display("power up with Clock Recipe A2, B1, C0 \n"); - tb.power_up(.clk_recipe_a(ClockRecipe::A2), - .clk_recipe_b(ClockRecipe::B1), + tb.power_up(.clk_recipe_a(ClockRecipe::A2), + .clk_recipe_b(ClockRecipe::B1), .clk_recipe_c(ClockRecipe::C0)); - + // delay before checking the clocks #500ns; @@ -82,17 +82,17 @@ module test_clk_recipe(); //Stop checking clock frequency. tb.set_chk_clk_freq(.chk_freq(1'b0)); - + tb.power_down(); #500ns; //power up with Clock Recipe A3, B1, C1 $display("power up with Clock Recipe A3, B1, C1 \n"); - tb.power_up(.clk_recipe_a(ClockRecipe::A3), - .clk_recipe_b(ClockRecipe::B1), + tb.power_up(.clk_recipe_a(ClockRecipe::A3), + .clk_recipe_b(ClockRecipe::B1), .clk_recipe_c(ClockRecipe::C1)); - + // delay before checking the clocks #500ns; @@ -103,17 +103,17 @@ module test_clk_recipe(); //Stop checking clock frequency. tb.set_chk_clk_freq(.chk_freq(1'b0)); - + tb.power_down(); #500ns; //power up with Clock Recipe A3, B2, C2 $display("power up with Clock Recipe A3, B2, C2 \n"); - tb.power_up(.clk_recipe_a(ClockRecipe::A3), - .clk_recipe_b(ClockRecipe::B2), + tb.power_up(.clk_recipe_a(ClockRecipe::A3), + .clk_recipe_b(ClockRecipe::B2), .clk_recipe_c(ClockRecipe::C2)); - + // delay before checking the clocks #500ns; @@ -124,17 +124,17 @@ module test_clk_recipe(); //Stop checking clock frequency. tb.set_chk_clk_freq(.chk_freq(1'b0)); - + tb.power_down(); #500ns; //power up with Clock Recipe A3, B3, C3 $display("power up with Clock Recipe A3, B3, C3 \n"); - tb.power_up(.clk_recipe_a(ClockRecipe::A3), - .clk_recipe_b(ClockRecipe::B3), + tb.power_up(.clk_recipe_a(ClockRecipe::A3), + .clk_recipe_b(ClockRecipe::B3), .clk_recipe_c(ClockRecipe::C3)); - + // delay before checking the clocks #500ns; @@ -145,17 +145,17 @@ module test_clk_recipe(); //Stop checking clock frequency. tb.set_chk_clk_freq(.chk_freq(1'b0)); - + tb.power_down(); #500ns; //power up with Clock Recipe A3, B4, C3 $display("power up with Clock Recipe A3, B4, C3 \n"); - tb.power_up(.clk_recipe_a(ClockRecipe::A3), - .clk_recipe_b(ClockRecipe::B4), + tb.power_up(.clk_recipe_a(ClockRecipe::A3), + .clk_recipe_b(ClockRecipe::B4), .clk_recipe_c(ClockRecipe::C3)); - + // delay before checking the clocks #500ns; @@ -166,17 +166,17 @@ module test_clk_recipe(); //Stop checking clock frequency. tb.set_chk_clk_freq(.chk_freq(1'b0)); - + tb.power_down(); #500ns; //power up with Clock Recipe A3, B5, C3 $display("power up with Clock Recipe A3, B5, C3 \n"); - tb.power_up(.clk_recipe_a(ClockRecipe::A3), - .clk_recipe_b(ClockRecipe::B5), + tb.power_up(.clk_recipe_a(ClockRecipe::A3), + .clk_recipe_b(ClockRecipe::B5), .clk_recipe_c(ClockRecipe::C3)); - + // delay before checking the clocks #500ns; @@ -187,22 +187,22 @@ module test_clk_recipe(); //Stop checking clock frequency. tb.set_chk_clk_freq(.chk_freq(1'b0)); - + tb.power_down(); //Stop checking clock frequency. tb.set_chk_clk_freq(.chk_freq(1'b0)); - + tb.power_down(); #500ns; //power up with Clock Recipe A3, B6, C3 $display("power up with Clock Recipe A3, B6, C3 \n"); - tb.power_up(.clk_recipe_a(ClockRecipe::A3), - .clk_recipe_b(ClockRecipe::B6), + tb.power_up(.clk_recipe_a(ClockRecipe::A3), + .clk_recipe_b(ClockRecipe::B6), .clk_recipe_c(ClockRecipe::C3)); - + // delay before checking the clocks #500ns; @@ -213,9 +213,9 @@ module test_clk_recipe(); //Stop checking clock frequency. tb.set_chk_clk_freq(.chk_freq(1'b0)); - + tb.power_down(); - + if (tb.chk_clk_err_cnt()) begin error_count++; $error("[%t] : Observed clock errors", $realtime); @@ -225,5 +225,5 @@ module test_clk_recipe(); $finish; end // initial begin - + endmodule // test_clk_recipe diff --git a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_ddr.sv b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_ddr.sv index a88d29008..b65f230ce 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_ddr.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_ddr.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + module test_ddr(); diff --git a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_ddr_peek_bdr_walking_ones.sv b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_ddr_peek_bdr_walking_ones.sv index b228282e9..9dc04c15d 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_ddr_peek_bdr_walking_ones.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_ddr_peek_bdr_walking_ones.sv @@ -1,6 +1,6 @@ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +12,9 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + + // This test shows example of backdoor loading DRAM micron memory and frontdoor reading through DMA. // The test covers valid rows, bank groups, banks and columns // The test also covers some row, bank group, bank and column combinations. @@ -24,6 +27,8 @@ module test_ddr_peek_bdr_walking_ones(); int fp; string file_name; + logic [63:0] addr = 64'h0; + initial begin `define BYTE_COUNT 64 `define BACKDOOR_DATA 512'h77777777777777776666666666666666555555555555555544444444444444443333333333333333222222222222222211111111111111110000000000000000 @@ -47,32 +52,44 @@ module test_ddr_peek_bdr_walking_ones(); //Write 8*64 bits of data starting at address 'h0 //Covers different columns $fdisplay(fp, "%0h %0h", 64'h0, `BACKDOOR_DATA); + addr = 64'h0; + tb.poke(.addr(addr), .data(`BACKDOOR_DATA), .size(DataSize::UINT512)); //Write 8*64 bits of data starting at address 'h100 //Covers different columns $fdisplay(fp, "%0h %0h", 64'h100, `BACKDOOR_DATA); + addr = 64'h100; + tb.poke(.addr(addr), .data(`BACKDOOR_DATA), .size(DataSize::UINT512)); //Write 8*64 bits of data starting at address 'h300 //Covers different columns $fdisplay(fp, "%0h %0h", 64'h300, `BACKDOOR_DATA); + addr = 64'h300; + tb.poke(.addr(addr), .data(`BACKDOOR_DATA), .size(DataSize::UINT512)); //Write 8*64 bits of data starting at address 'h1000 //Covers different columns $fdisplay(fp, "%0h %0h", 64'h1000, `BACKDOOR_DATA); + addr = 64'h1000; + tb.poke(.addr(addr), .data(`BACKDOOR_DATA), .size(DataSize::UINT512)); //Covers rows for ( int i=0; i<4; i++) begin $fdisplay(fp, "%0h %0h", 64'h2_0000 << i, `BACKDOOR_DATA); + addr = 64'h2_0000 << i; + tb.poke(.addr(addr), .data(`BACKDOOR_DATA), .size(DataSize::UINT512)); end //Covers some row, bank group, bank and column combinations for ( int i=0; i<4; i++) begin $fdisplay(fp, "%0h %0h", 64'h2_0040 << i, `BACKDOOR_DATA); + addr = 64'h2_0040 << i; + tb.poke(.slot_id(0), .addr(addr), .data(`BACKDOOR_DATA), .size(DataSize::UINT512)); end $fclose(fp); - tb.card.ddr_bdr_ld(file_name); + // Not using backdoor load (Errata #8) tb.nsec_delay(500); ddr_peeks(64'h0, 1, `BACKDOOR_DATA); @@ -105,8 +122,5 @@ module test_ddr_peek_bdr_walking_ones(); end end endtask // ddr_peeks - -endmodule // test_ddr_peek_bdr_walking_ones - - +endmodule // test_ddr_peek_bdr_walking_ones diff --git a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_ddr_peek_poke.sv b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_ddr_peek_poke.sv index 0752032fa..52ec25e53 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_ddr_peek_poke.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_ddr_peek_poke.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,7 +13,9 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. -// +// ============================================================================ + + // Description: This test is to catch the memory aliasing issues in DDR memory models. // The test walks through the DDR address range and tests the contents. @@ -29,11 +32,11 @@ module test_ddr_peek_poke(); tb.power_up(.clk_recipe_a(ClockRecipe::A0), .clk_recipe_b(ClockRecipe::B0), .clk_recipe_c(ClockRecipe::C0)); - initialize_ddr(); + initialize_ddr(); deselect_cl_tst_hw(); for ( int i=0; i<26; i++) begin -//Walk through DDR address range to check if any of the bits in DDR Rank are tied to 0. +//Walk through DDR address range to check if any of the bits in DDR Rank are tied to 0. addr = 'h40 << i; $display("Write to Addr %b", addr); tb.poke(.addr(addr), .data({512{1'b1}}), .size(DataSize::UINT512)); @@ -47,7 +50,7 @@ module test_ddr_peek_poke(); $error("Read Data mismatch for Addr %h: Exp %h, Act %h", addr, {512{1'b1}}, wide_read_data); error_count++; end -//Walk through DDR address range to check if two adjacent bits are wrongly wired. +//Walk through DDR address range to check if two adjacent bits are wrongly wired. addr = 'h40 << i; $display("Write to Addr %b", addr); tb.poke(.addr(addr), .data({512{1'b1}}), .size(DataSize::UINT512)); @@ -60,14 +63,14 @@ module test_ddr_peek_poke(); if (wide_read_data != {512{1'b1}}) begin $error("Read Data mismatch for Addr %h: Exp %h, Act %h", addr, {512{1'b1}}, wide_read_data); error_count++; - end - end - + end + end + tb.nsec_delay(500); // Power down tb.power_down(); - + report_pass_fail_status(); $finish; diff --git a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dma_pcim_concurrent.sv b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dma_pcim_concurrent.sv index 318624384..ae475cc0b 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dma_pcim_concurrent.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dma_pcim_concurrent.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,37 +13,39 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + // This test initiates dma and pcim traffic in parallel. module test_dma_pcim_concurrent(); - + import tb_type_defines_pkg::*; `include "base_test_utils.svh"; int len0 = 17; - + initial begin tb.power_up(.clk_recipe_a(ClockRecipe::A1), .clk_recipe_b(ClockRecipe::B0), .clk_recipe_c(ClockRecipe::C0)); - initialize_ddr(); + initialize_ddr(); fork begin - $display("[%t] : Initializing DDR buffers", $realtime); + $display("[%t] : Initializing DDR buffers", $realtime); load_host_memory(.chan(`DDR_CHANNEL), .host_addr(64'h0000), .cl_addr(`DDR_BASE_ADDR), .data_pattern(8'hAA), .num_bytes(len0)); - + $display("[%t] : Starting DDR H2C DMA channels ", $realtime); tb.start_que_to_cl(.chan(`DDR_CHANNEL)); wait_for_dma_transfer_from_buffer_to_cl(.chan(`DDR_CHANNEL)); - // DMA transfers are posted writes. The above code checks only if the dma transfer is setup and done. + // DMA transfers are posted writes. The above code checks only if the dma transfer is setup and done. // We need to wait for writes to finish to memory before issuing reads. $display("[%t] : Waiting for DDR DMA write transfers to complete", $realtime); #2us; - $display("[%t] : Transferring DDR data to host buffer", $realtime); + $display("[%t] : Transferring DDR data to host buffer", $realtime); `define DDR_HOST_MEM_BUFFER_ADDR_0 64'h0_0001_0800 tb.que_cl_to_buffer(.chan(`DDR_CHANNEL), .dst_addr(`DDR_HOST_MEM_BUFFER_ADDR_0), .cl_addr(`DDR_BASE_ADDR), .len(len0) ); tb.start_que_to_buffer(.chan(`DDR_CHANNEL)); @@ -54,14 +57,14 @@ module test_dma_pcim_concurrent(); $display("[%t] : Comparing DMA buffer from DDR sequence 0 with expected pattern", $realtime); check_host_memory(.addr(`DDR_HOST_MEM_BUFFER_ADDR_0), .expected_data_pattern(8'hAA), .num_bytes(len0)); end // fork begin - begin + begin #100ns; $display("[%t] : Programming cl_tst registers for PCIM", $realtime); program_cl_tst(.base_addr(64'h0000), .test_addr(64'h1234_0000), .enable_write(1'b1), .enable_read(1'b1), .axi_len(8'h07), .iter_mode(1'b0), .num_iter(0), .num_inst(16'h000f)); end - join + join #500ns; tb.power_down(); diff --git a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dma_pcis_concurrent.sv b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dma_pcis_concurrent.sv index 864e59cc6..d8cc795dd 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dma_pcis_concurrent.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dma_pcis_concurrent.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + //This test runs DMA and PCIS tests in parallel @@ -22,27 +25,27 @@ module test_dma_pcis_concurrent(); `include "base_test_utils.svh"; int len0 = 17; - + initial begin tb.power_up(.clk_recipe_a(ClockRecipe::A1), .clk_recipe_b(ClockRecipe::B0), .clk_recipe_c(ClockRecipe::C0)); - initialize_ddr(); + initialize_ddr(); fork begin - $display("[%t] : Initializing DDR buffers", $realtime); + $display("[%t] : Initializing DDR buffers", $realtime); load_host_memory(.chan(`DDR_CHANNEL), .host_addr(64'h0000), .cl_addr(`DDR_BASE_ADDR), .data_pattern(8'hAA), .num_bytes(len0)); - + $display("[%t] : Starting DDR H2C DMA channels ", $realtime); tb.start_que_to_cl(.chan(`DDR_CHANNEL)); wait_for_dma_transfer_from_buffer_to_cl(.chan(`DDR_CHANNEL)); - // DMA transfers are posted writes. The above code checks only if the dma transfer is setup and done. + // DMA transfers are posted writes. The above code checks only if the dma transfer is setup and done. // We need to wait for writes to finish to memory before issuing reads. $display("[%t] : Waiting for DDR DMA write transfers to complete", $realtime); #2us; - $display("[%t] : Transferring DDR data to host buffer", $realtime); + $display("[%t] : Transferring DDR data to host buffer", $realtime); `define DDR_HOST_MEM_BUFFER_ADDR_0 64'h0_0001_0800 tb.que_cl_to_buffer(.chan(`DDR_CHANNEL), .dst_addr(`DDR_HOST_MEM_BUFFER_ADDR_0), .cl_addr(`DDR_BASE_ADDR), .len(len0) ); tb.start_que_to_buffer(.chan(`DDR_CHANNEL)); @@ -54,7 +57,7 @@ module test_dma_pcis_concurrent(); $display("[%t] : Comparing DMA buffer from DDR sequence 0 with expected pattern", $realtime); check_host_memory(.addr(`DDR_HOST_MEM_BUFFER_ADDR_0), .expected_data_pattern(8'hAA), .num_bytes(len0)); end // fork begin - begin + begin #600ns; // Waitng for DMA transfer setup time @@ -64,7 +67,7 @@ module test_dma_pcis_concurrent(); $display("[%t] : Poke from DDR offset 24 GB", $realtime); check_peek_poke(.addr(`DDR_BASE_ADDR + `DDR_LEVEL_3), .data(64'h1), .size(DataSize::UINT64)); end - join + join // Power down #500ns; tb.power_down(); diff --git a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dma_sda_concurrent.sv b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dma_sda_concurrent.sv index b8b2935be..1551373e3 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dma_sda_concurrent.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dma_sda_concurrent.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,11 +13,13 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + // This test runs DMA and SDA tests in parallel module test_dma_sda_concurrent(); - + import tb_type_defines_pkg::*; `include "base_test_utils.svh"; @@ -34,21 +37,21 @@ module test_dma_sda_concurrent(); tb.power_up(.clk_recipe_a(ClockRecipe::A1), .clk_recipe_b(ClockRecipe::B0), .clk_recipe_c(ClockRecipe::C0)); - initialize_ddr(); - + initialize_ddr(); + fork begin - $display("[%t] : Initializing DDR buffers", $realtime); + $display("[%t] : Initializing DDR buffers", $realtime); load_host_memory(.chan(`DDR_CHANNEL), .host_addr(64'h0000), .cl_addr(`DDR_BASE_ADDR), .data_pattern(8'hAA), .num_bytes(len0)); - + $display("[%t] : Starting DDR H2C DMA channels ", $realtime); tb.start_que_to_cl(.chan(`DDR_CHANNEL)); wait_for_dma_transfer_from_buffer_to_cl(.chan(`DDR_CHANNEL)); - // DMA transfers are posted writes. The above code checks only if the dma transfer is setup and done. + // DMA transfers are posted writes. The above code checks only if the dma transfer is setup and done. // We need to wait for writes to finish to memory before issuing reads. $display("[%t] : Waiting for DDR DMA write transfers to complete", $realtime); #2us; - $display("[%t] : Transferring DDR data to host buffer", $realtime); + $display("[%t] : Transferring DDR data to host buffer", $realtime); `define DDR_HOST_MEM_BUFFER_ADDR_0 64'h0_0001_0800 tb.que_cl_to_buffer(.chan(`DDR_CHANNEL), .dst_addr(`DDR_HOST_MEM_BUFFER_ADDR_0), .cl_addr(`DDR_BASE_ADDR), .len(len0) ); tb.start_que_to_buffer(.chan(`DDR_CHANNEL)); @@ -60,13 +63,13 @@ module test_dma_sda_concurrent(); $display("[%t] : Comparing DMA buffer from DDR sequence 0 with expected pattern", $realtime); check_host_memory(.addr(`DDR_HOST_MEM_BUFFER_ADDR_0), .expected_data_pattern(8'hAA), .num_bytes(len0)); end // fork begin - begin + begin #100ns; //SDA test sda_addr = 'h0; for (int i=0; i<32; i=i+4) begin sda_addr = sda_addr + i; - + sda_data = $urandom(); tb.poke_sda(.addr(sda_addr), .data(sda_data)); @@ -86,14 +89,14 @@ module test_dma_sda_concurrent(); end #100ns; - + timeout_count = 0; $display("[%t] : Waiting for SDA write and read activity to complete", $realtime); end // for (int i=0; i<32; i=i+4) #1us; end - join + join #500ns; tb.power_down(); diff --git a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dram_dma.sv b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dram_dma.sv index 2adf8e1d0..8236f9bfd 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dram_dma.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dram_dma.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ module test_dram_dma(); diff --git a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dram_dma_4k_crossing.sv b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dram_dma_4k_crossing.sv index 892a146ed..3faaec635 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dram_dma_4k_crossing.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dram_dma_4k_crossing.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + // DMA 4k crossing test diff --git a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dram_dma_align_addr_4k.sv b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dram_dma_align_addr_4k.sv index 7b5e192b6..b40307ffd 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dram_dma_align_addr_4k.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dram_dma_align_addr_4k.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ module test_dram_dma_align_addr_4k(); diff --git a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dram_dma_axi_mstr.sv b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dram_dma_axi_mstr.sv index 8c91b2b31..b5bd8d881 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dram_dma_axi_mstr.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dram_dma_axi_mstr.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + module test_dram_dma_axi_mstr(); @@ -62,7 +65,7 @@ module test_dram_dma_axi_mstr(); // Set AXI Master Command Registers // addr = 0x1_a021f700, Write $display("[%t] : Setting DDR Base Address Command Registers ", $realtime);// addr = 0x1_a021f700 - tb.poke_ocl(.addr(AXI_MSTR_CAHR_ADDR), .data(DDR_BASE_HI_ADDR)); // Set High Address -- + tb.poke_ocl(.addr(AXI_MSTR_CAHR_ADDR), .data(DDR_BASE_HI_ADDR)); // Set High Address -- tb.poke_ocl(.addr(AXI_MSTR_CALR_ADDR), .data(DDR_BASE_LO_ADDR + i)); // Set Low Address tb.poke_ocl(.addr(AXI_MSTR_CWDR_ADDR), .data(DDR_BASE_DATA | i)); // Set Write Data tb.poke_ocl(.addr(AXI_MSTR_CCR_ADDR), .data(32'h0000_0001)); // Issue Write Command @@ -82,7 +85,7 @@ module test_dram_dma_axi_mstr(); end // for (int i = 0; i <= 12; i=i+4) //} for (int i = 0; i <= 12; i=i+4) begin //{ - tb.poke_ocl(.addr(AXI_MSTR_CAHR_ADDR), .data(DDR_BASE_HI_ADDR)); // Set High Address -- + tb.poke_ocl(.addr(AXI_MSTR_CAHR_ADDR), .data(DDR_BASE_HI_ADDR)); // Set High Address -- tb.poke_ocl(.addr(AXI_MSTR_CALR_ADDR), .data(DDR_BASE_LO_ADDR + i)); // Set Low Address tb.poke_ocl(.addr(AXI_MSTR_CWDR_ADDR), .data(DDR_BASE_DATA | i)); // Set Write Data @@ -190,7 +193,7 @@ for (int i = 0; i <= 12; i=i+4) begin //{ // Set AXI Master Command Registers // addr = 0x1_a021f700, Write $display("[%t] : Setting DDR Base Address Command Registers ", $realtime);// addr = 0x1_a021f700 - tb.poke_ocl(.addr(AXI_MSTR_CAHR_ADDR), .data(DDR_OFFSET_DDR_LEVEL_2_HI_ADDR)); // Set High Address -- + tb.poke_ocl(.addr(AXI_MSTR_CAHR_ADDR), .data(DDR_OFFSET_DDR_LEVEL_2_HI_ADDR)); // Set High Address -- tb.poke_ocl(.addr(AXI_MSTR_CALR_ADDR), .data(DDR_OFFSET_DDR_LEVEL_2_LO_ADDR + i)); // Set Low Address tb.poke_ocl(.addr(AXI_MSTR_CWDR_ADDR), .data(DDR_OFFSET_DDR_LEVEL_2_DATA | i)); // Set Write Data tb.poke_ocl(.addr(AXI_MSTR_CCR_ADDR), .data(32'h0000_0001)); // Issue Write Command @@ -210,7 +213,7 @@ for (int i = 0; i <= 12; i=i+4) begin //{ end // for (int i = 0; i <= 12; i=i+4) //} for (int i = 0; i <= 12; i=i+4) begin //{ - tb.poke_ocl(.addr(AXI_MSTR_CAHR_ADDR), .data(DDR_OFFSET_DDR_LEVEL_2_HI_ADDR)); // Set High Address -- + tb.poke_ocl(.addr(AXI_MSTR_CAHR_ADDR), .data(DDR_OFFSET_DDR_LEVEL_2_HI_ADDR)); // Set High Address -- tb.poke_ocl(.addr(AXI_MSTR_CALR_ADDR), .data(DDR_OFFSET_DDR_LEVEL_2_LO_ADDR + i)); // Set Low Address tb.poke_ocl(.addr(AXI_MSTR_CWDR_ADDR), .data(DDR_OFFSET_DDR_LEVEL_2_DATA | i)); // Set Write Data @@ -255,7 +258,7 @@ for (int i = 0; i <= 12; i=i+4) begin //{ // Set AXI Master Command Registers // addr = 0x1_a021f700, Write $display("[%t] : Setting DDR Base Address Command Registers ", $realtime);// addr = 0x1_a021f700 - tb.poke_ocl(.addr(AXI_MSTR_CAHR_ADDR), .data(DDR_OFFSET_DDR_LEVEL_3_HI_ADDR)); // Set High Address -- + tb.poke_ocl(.addr(AXI_MSTR_CAHR_ADDR), .data(DDR_OFFSET_DDR_LEVEL_3_HI_ADDR)); // Set High Address -- tb.poke_ocl(.addr(AXI_MSTR_CALR_ADDR), .data(DDR_OFFSET_DDR_LEVEL_3_LO_ADDR + i)); // Set Low Address tb.poke_ocl(.addr(AXI_MSTR_CWDR_ADDR), .data(DDR_OFFSET_DDR_LEVEL_3_DATA | i)); // Set Write Data tb.poke_ocl(.addr(AXI_MSTR_CCR_ADDR), .data(32'h0000_0001)); // Issue Write Command @@ -275,7 +278,7 @@ for (int i = 0; i <= 12; i=i+4) begin //{ end // for (int i = 0; i <= 12; i=i+4) //} for (int i = 0; i <= 12; i=i+4) begin //{ - tb.poke_ocl(.addr(AXI_MSTR_CAHR_ADDR), .data(DDR_OFFSET_DDR_LEVEL_3_HI_ADDR)); // Set High Address -- + tb.poke_ocl(.addr(AXI_MSTR_CAHR_ADDR), .data(DDR_OFFSET_DDR_LEVEL_3_HI_ADDR)); // Set High Address -- tb.poke_ocl(.addr(AXI_MSTR_CALR_ADDR), .data(DDR_OFFSET_DDR_LEVEL_3_LO_ADDR + i)); // Set Low Address tb.poke_ocl(.addr(AXI_MSTR_CWDR_ADDR), .data(DDR_OFFSET_DDR_LEVEL_3_DATA | i)); // Set Write Data @@ -321,4 +324,3 @@ end //} $finish; end // initial begin endmodule // test_dram_dma_axi_mstr - diff --git a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dram_dma_mem_model_bdr_rd.sv b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dram_dma_mem_model_bdr_rd.sv index b69a6446d..063ac4b57 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dram_dma_mem_model_bdr_rd.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dram_dma_mem_model_bdr_rd.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,9 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + + // This test bypasses Micron DDR models and uses AXI memory model. // Please refer to readme for more information about AXI memoryy model. // This test frontdoor writes and backdoor reads AXI memory model. @@ -30,7 +34,7 @@ module test_dram_dma_mem_model_bdr_rd(); int len2 = 6000; //transfer4 - length between 256 and 512 bytes. int len3 = 300; - + initial begin logic [63:0] ddr_addr_0, ddr_addr_1, ddr_addr_2, ddr_addr_3; @@ -40,9 +44,9 @@ module test_dram_dma_mem_model_bdr_rd(); .clk_recipe_c(ClockRecipe::C0)); initialize_ddr(); deselect_cl_tst_hw(); - + #10000ns; - + $display("[%t] : Initializing DDR buffers", $realtime); load_host_memory(.chan(`DDR_CHANNEL), .host_addr(64'h0000), .cl_addr(`DDR_BASE_ADDR), .data_pattern(8'hAA), .num_bytes(len0)); load_host_memory(.chan(`DDR_CHANNEL), .host_addr(64'h3000), .cl_addr(`DDR_BASE_ADDR + `DDR_LEVEL_1), .data_pattern(8'hBB), .num_bytes(len1)); @@ -53,7 +57,7 @@ module test_dram_dma_mem_model_bdr_rd(); tb.start_que_to_cl(.chan(`DDR_CHANNEL)); wait_for_dma_transfer_from_buffer_to_cl(.chan(`DDR_CHANNEL)); #1us; - + $display("Back door read memory from DDR Base Address \n"); ddr_addr_0 = `DDR_BASE_ADDR; for (int i = 0 ; i < len0 ; i++) begin @@ -87,7 +91,7 @@ module test_dram_dma_mem_model_bdr_rd(); end ddr_addr_2++; end - + $display("Back door read memory from DDR Offset 24 GB \n"); ddr_addr_3 = `DDR_BASE_ADDR + `DDR_LEVEL_3; for (int i = 0 ; i < len3 ; i++) begin @@ -108,4 +112,3 @@ module test_dram_dma_mem_model_bdr_rd(); end // initial begin endmodule // test_dram_dma_mem_model_bdr_rd - diff --git a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dram_dma_mem_model_bdr_wr.sv b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dram_dma_mem_model_bdr_wr.sv index 0bb044e22..c5b610729 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dram_dma_mem_model_bdr_wr.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dram_dma_mem_model_bdr_wr.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,9 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + + // This test bypasses Micron DDR models and uses AXI memory model. // Please refer to readme for more information about AXI memoryy model. // This test backdoor writes and front door reads AXI memory model. @@ -30,7 +34,7 @@ module test_dram_dma_mem_model_bdr_wr(); int len2 = 6000; //transfer4 - length between 256 and 512 bytes. int len3 = 300; - + initial begin logic [63:0] ddr_addr_0, ddr_addr_1, ddr_addr_2, ddr_addr_3; @@ -39,9 +43,9 @@ module test_dram_dma_mem_model_bdr_wr(); .clk_recipe_c(ClockRecipe::C0)); initialize_ddr(); deselect_cl_tst_hw(); - + #10000ns; - + $display("[%t] Back door load memory to DDR Base Address \n", $realtime); ddr_addr_0 = `DDR_BASE_ADDR; for (int i = 0 ; i < len0 ; i++) begin @@ -73,7 +77,7 @@ module test_dram_dma_mem_model_bdr_wr(); tb.card.fpga.CL.SH_DDR.u_mem_model.axi_mem_bdr_write(.addr(ddr_addr_3), .d(8'hDD)); ddr_addr_3++; end - + $display("[%t] : starting C2H DMA channels ", $realtime); `define DDR_HOST_MEM_BUFFER_ADDR_0 64'h0_0001_0800 `define DDR_HOST_MEM_BUFFER_ADDR_1 64'h0_0002_1800 @@ -101,7 +105,7 @@ module test_dram_dma_mem_model_bdr_wr(); $display("[%t] : Comparing DMA buffer from DDR sequence 3 with expected pattern", $realtime); check_host_memory(.addr(`DDR_HOST_MEM_BUFFER_ADDR_3), .expected_data_pattern(8'hDD), .num_bytes(len3)); - + #500ns; tb.power_down(); @@ -111,4 +115,3 @@ module test_dram_dma_mem_model_bdr_wr(); end // initial begin endmodule // test_dram_dma_mem_model_bdr_wr - diff --git a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dram_dma_rnd.sv b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dram_dma_rnd.sv index 826599c0b..62cbe408e 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dram_dma_rnd.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dram_dma_rnd.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ // DMA test with random lengths. diff --git a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dram_dma_single_beat_4k.sv b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dram_dma_single_beat_4k.sv index e95b917c3..cf10b133d 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dram_dma_single_beat_4k.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_dram_dma_single_beat_4k.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + // DMA test with lengths less than 64 byte module test_dram_dma_single_beat_4k(); diff --git a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_hbm.sv b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_hbm.sv index 789171fd4..ece819cf3 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_hbm.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_hbm.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2022 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + module test_hbm(); diff --git a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_int.sv b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_int.sv index b468ec1fe..e8e55dcd8 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_int.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_int.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,13 +13,15 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + module test_int(); import tb_type_defines_pkg::*; - + `include "base_test_utils.svh" - + logic [31:0] write_data; logic [31:0] read_data; diff --git a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_null.sv b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_null.sv index f19e442b8..e0ccbaca9 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_null.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_null.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,20 +13,22 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + module test_null(); initial begin int exit_code; - + tb.power_up(); tb.test_main(exit_code); - + #50ns; tb.power_down(); - + $finish; end diff --git a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_peek_poke.sv b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_peek_poke.sv index e7e3c4326..49e15aea8 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_peek_poke.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_peek_poke.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,11 +13,13 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + // This test initiates dma and pcim traffic in parallel. module test_peek_poke(); - + import tb_type_defines_pkg::*; `include "base_test_utils.svh" @@ -25,7 +28,7 @@ module test_peek_poke(); tb.power_up(); initialize_ddr(); - + $display("[%t] : Programming cl_tst registers for PCIM", $realtime); program_cl_tst(.base_addr(64'h0000), .test_addr(64'h1234_0000), .enable_write(1'b1), .enable_read(1'b1), .axi_len(8'h07), .iter_mode(1'b0), .num_iter(0), .num_inst(16'h000f)); diff --git a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_peek_poke_len.sv b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_peek_poke_len.sv index 3ab37dd9b..6482ad1f4 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_peek_poke_len.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_peek_poke_len.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + // PCIM test with different lengths for each write and read transfer @@ -19,15 +22,15 @@ module test_peek_poke_len(); import tb_type_defines_pkg::*; `include "base_test_utils.svh" - + logic [7:0] len; - + initial begin len = 0; - + tb.power_up(); initialize_ddr(); - + for(int addr =0; addr <=1023; addr = addr+64) begin $display("[%t] : Programming cl_tst registers for PCIe", $realtime); len = len+1; @@ -36,13 +39,12 @@ module test_peek_poke_len(); program_cl_tst(.base_addr(64'h0000), .test_addr(64'h1234_0000 + addr), .enable_write(1'b1), .enable_read(1'b1), .axi_len(len), .iter_mode(1'b0), .num_iter(0), .num_inst(16'h0001)); end // for (int addr =0; addr <=63; addr++) - + tb.power_down(); report_pass_fail_status(); - + $finish; end endmodule // test_peek_poke_len - diff --git a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_peek_poke_pcis_axsize.sv b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_peek_poke_pcis_axsize.sv index b24af026f..bdcea0068 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_peek_poke_pcis_axsize.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_peek_poke_pcis_axsize.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ module test_peek_poke_pcis_axsize(); @@ -25,16 +27,16 @@ module test_peek_poke_pcis_axsize(); bit [511:0] pcis_exp_data; bit [511:0] pcis_act_data; - int data; - + int data; + initial begin tb.power_up(); initialize_ddr(); deselect_cl_tst_hw(); - pcis_wr_data =0; - data =1; + pcis_wr_data =0; + data =1; for(int size =0; size <=6; size++) begin $display("[%t] : Size of peek/poke = %0d", $realtime, size); for(int addr =0; addr <=63; addr = addr+(2**size)) begin @@ -42,10 +44,10 @@ module test_peek_poke_pcis_axsize(); for (int num_bytes =0; num_bytes < 2**size; num_bytes++) begin pcis_wr_data[(num_bytes*8)+:8] = data; data ++; - end + end tb.poke(.addr(addr), .data(pcis_wr_data), .size(DataSize::DATA_SIZE'(size))); tb.peek(.addr(addr), .data(pcis_rd_data), .size(DataSize::DATA_SIZE'(size))); - for (int num_bytes =0; num_bytes < 2**size; num_bytes++) begin + for (int num_bytes =0; num_bytes < 2**size; num_bytes++) begin pcis_exp_data[((addr+num_bytes)*8)+:8] = pcis_wr_data[(num_bytes*8)+:8]; pcis_act_data[((addr+num_bytes)*8)+:8] = pcis_rd_data[(num_bytes*8)+:8]; end @@ -54,7 +56,7 @@ module test_peek_poke_pcis_axsize(); $display("[%t] : Clear the memory before next size iteration", $realtime); tb.poke(.addr(64'h0), .data(512'h0), .size(DataSize::DATA_SIZE'(3))); end - + $display("[%t] : Waiting for PCIS write and read activity to complete", $realtime); #500ns; diff --git a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_peek_poke_rnd_lengths.sv b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_peek_poke_rnd_lengths.sv index acba188a6..1e2da97e0 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_peek_poke_rnd_lengths.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_peek_poke_rnd_lengths.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + // PCIM test with random lengths for each transfer @@ -20,25 +23,25 @@ module test_peek_poke_rnd_lengths(); import tb_type_defines_pkg::*; `include "base_test_utils.svh" - + logic [7:0] len; - + initial begin - + tb.power_up(); initialize_ddr(); len = 0 ; - + for(int addr =0; addr <=1023; addr = addr+64) begin $display("[%t] : Programming cl_tst registers for PCIM", $realtime); len = $urandom_range(16, 1); $display("[%t] : Number of AXI data phases %d \n", $realtime, len); - + program_cl_tst(.base_addr(64'h0000), .test_addr(64'h1234_0000 + addr), .enable_write(1'b1), .enable_read(1'b1), .axi_len(len), .iter_mode(1'b0), .num_iter(0), .num_inst(16'h0001)); end // for (int addr =0; addr <=63; addr++) - + tb.power_down(); report_pass_fail_status(); @@ -47,4 +50,3 @@ module test_peek_poke_rnd_lengths(); end endmodule // test_peek_poke_rnd_lengths - diff --git a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_peek_poke_wc.sv b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_peek_poke_wc.sv index 319bfc85c..ead8e93e8 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_peek_poke_wc.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_peek_poke_wc.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,25 +13,28 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. -// This test is test multi DW pokes to CL. The poke_pcis_wc is a function that tests -// write combine feature. Test does pokes with multiple DWs and reads the data back +// ============================================================================ + + +// This test is test multi DW pokes to CL. The poke_pcis_wc is a function that tests +// write combine feature. Test does pokes with multiple DWs and reads the data back // and checks. module test_peek_poke_wc(); - import tb_type_defines_pkg::*; - + import tb_type_defines_pkg::*; + `include "base_test_utils.svh" - + logic [31:0] pcis_wr_data [$]; logic [511:0] pcis_rd_data; logic [511:0] pcis_exp_data; logic [511:0] pcis_act_data; - + int size; int dw_cnt; logic [31:0] addr; - + initial begin tb.power_up(); @@ -38,43 +42,35 @@ module test_peek_poke_wc(); size = 6; addr = 'h0; - + for (int cnt=0; cnt <4; cnt++) begin dw_cnt = $urandom_range(4, 10); addr = addr + 'h04; - + $display("[%t] : Address of peek/poke = %0h", $realtime, addr); - + for (int num_dw =0; num_dw < dw_cnt; num_dw++) begin pcis_wr_data[num_dw] = $urandom(); pcis_exp_data[(num_dw*32)+:32] = pcis_wr_data[num_dw]; end - + tb.poke_pcis_wc(.addr(addr), .data(pcis_wr_data), .size(DataSize::DATA_SIZE'(size))); tb.peek(.addr(addr), .data(pcis_rd_data), .size(DataSize::DATA_SIZE'(size))); - for (int num_dw =0; num_dw < dw_cnt; num_dw++) begin + for (int num_dw =0; num_dw < dw_cnt; num_dw++) begin pcis_act_data[(num_dw*32)+:32] = pcis_rd_data[(num_dw*32)+:32]; end - + compare_data(.act_data(pcis_act_data), .exp_data(pcis_exp_data), .addr(addr)); - + tb.nsec_delay(1000); end // for (int cnt=0; cnt <4; cnt++) - + tb.power_down(); - + report_pass_fail_status(); $finish; end // initial begin endmodule // test_peek_poke_wc - - - - - - - - diff --git a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_sda.sv b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_sda.sv index d4323fc2b..f1409bbba 100644 --- a/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_sda.sv +++ b/hdk/cl/examples/cl_dram_hbm_dma/verif/tests/test_sda.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,32 +13,34 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + // Test for SDA interface module test_sda(); import tb_type_defines_pkg::*; - + `include "base_test_utils.svh"; - + logic [63:0] sda_addr; logic [31:0] sda_data; logic [31:0] read_data; int timeout_count; - + initial begin tb.power_up(.clk_recipe_a(ClockRecipe::A0), .clk_recipe_b(ClockRecipe::B0), .clk_recipe_c(ClockRecipe::C0)); - initialize_ddr(); - + initialize_ddr(); + sda_addr = 'h0; for (int i=0; i<64; i=i+4) begin sda_addr = sda_addr + i; - + sda_data = $urandom(); tb.poke_sda(.addr(sda_addr), .data(sda_data)); @@ -57,10 +60,10 @@ module test_sda(); end #100ns; - + $display("[%t] : Waiting for SDA write and read activity to complete", $realtime); end // for (int i=0; i<63; i=i+4) - + #500ns; tb.power_down(); @@ -69,11 +72,3 @@ module test_sda(); $finish; end // initial begin endmodule // test_sda - - - - - - - - diff --git a/hdk/cl/examples/cl_mem_perf/README.md b/hdk/cl/examples/cl_mem_perf/README.md index 21ac628db..96fdd4406 100644 --- a/hdk/cl/examples/cl_mem_perf/README.md +++ b/hdk/cl/examples/cl_mem_perf/README.md @@ -4,34 +4,44 @@ ## Table of Content -1. [Introduction](#ancIntroduction) -2. [Architecture Overview](#ancArchitectureOverview) - 1. [Clocks and Reset](#ancClocksAndResets) - 2. [OCL](#ancOCL) - 3. [PCIM](#ancPCIM) - 4. [PCIS](#ancPCIS) - 5. [DDR](#ancDDR) - 6. [HBM](#ancHBM) - 7. [SDA](#ancSDA) - 8. [Interrupts](#ancInterrupts) - 9. [Virtual JTAG](#ancVirtualJtag) -3. [Address Space](#ancAddressSpace) - 1. [OCL Address Space](#ancOCLRegisterAddressSpace) - 2. [PCIS Memory Address Space](#ancPCISAddressSpace) - 3. [HBM Memory Address Space](#ancHBMMemoryAddressSpace) - 4. [CL_HBM_AXI4 Register Address Space](#ancHBMAxi4RegisterAddrSpace) - 5. [SDA Memory Address Space](#ancSDAAddressSpace) -4. [Simulations](#ancSimulations) -5. [Software](#ancSoftware) -6. [HBM Performance Tests](#ancHBMPerformanceTests) - - +- [CL\_MEM\_PERF Custom Logic Example](#cl_mem_perf-custom-logic-example) + - [Table of Content](#table-of-content) +- [Introduction](#introduction) +- [Architecture Overview](#architecture-overview) + - [Clocks and Reset](#clocks-and-reset) + - [OCL](#ocl) + - [PCIM](#pcim) + - [PCIS](#pcis) + - [DDR](#ddr) + - [HBM](#hbm) + - [SDA](#sda) + - [Interrupts](#interrupts) + - [Virtual JTAG](#virtual-jtag) +- [Address Space](#address-space) + - [OCL Address Space](#ocl-address-space) + - [PCIS Memory Address Space](#pcis-memory-address-space) + - [HBM Memory Address Space](#hbm-memory-address-space) + - [CL\_HBM\_AXI4 Register Address Space](#cl_hbm_axi4-register-address-space) + - [SDA Memory Address Space](#sda-memory-address-space) +- [Simulations](#simulations) +- [Software](#software) + - [test\_hbm\_perf32.c](#test_hbm_perf32c) + - [test\_dram\_hbm\_dma.c](#test_dram_hbm_dmac) + - [test\_hbm\_perf32.c](#test_hbm_perf32c-1) + - [test\_aws\_clk\_gen.c](#test_aws_clk_genc) + - [test\_clk\_freq.c](#test_clk_freqc) + - [Compile and run instructions](#compile-and-run-instructions) + - [test\_dram\_hbm\_dma\_hwsw\_cosim.c](#test_dram_hbm_dma_hwsw_cosimc) + - [Compile and run instructions](#compile-and-run-instructions-1) +- [HBM Performance Tests](#hbm-performance-tests) + - [Instructions to run HBM Performance Test](#instructions-to-run-hbm-performance-test) + # Introduction The CL_MEM_PERF is a customer reference design for F2 where the objective is to demonstrate fine tuned data paths to HBM and DDR to achieve maximum throughput to the memories. The example also demonstrates datapath connectivity between Host, AWS Shell, Custom Logic (CL) region in the FPGA, HBM and DDR DIMM on the FPGA card. Following are the major highlights of CL_MEM_PERF design: 1. Datapath to 64GB DDR and 16GB HBM through Shell’s PCIS Interface. DDR and HBM memories in the FPGFA are accessible from the Host on PF0-BAR4, as well as from the DMA engine in the XDMA_SHELL. Both these accesses show up as AXI4 transaction on PCIS interface which ultimately reach the targeted memory. -2. Demonstrate the use of PCIM interface for applications where CL is the PCIe Requestor to the Host. This can also be used to test peak PCIe transfer rates between Host and FPGA over PCIM interface. +2. Demonstrate the use of PCIM interface for applications where CL is the PCIe Requester to the Host. This can also be used to test peak PCIe transfer rates between Host and FPGA over PCIM interface. 3. Register access to various blocks through Shell’s OCL interface. 4. 1KB BRAM accessible through Shell’s SDA interface. 5. Supports user defined interrupts generated by the CL. @@ -43,13 +53,12 @@ The CL_MEM_PERF is a customer reference design for F2 where the objective is to Overall, CL_MEM_PERF enables customers to quickly integrate their CL accelerator designs to interface with various memories on the FPGA and to use as reference to fine tune their CL performance. - # Architecture Overview Figure below shows an architectural overview of CL_MEM_PERF design: ![Diagram](design/cl_mem_perf.png) -The interfaces between Shell and CL are accessible from the Host on the PF/BARs as stated in the table below. Please See [AWS_Fpga_Pcie_Memory_Map.md](../../../docs/AWS_Fpga_Pcie_Memory_Map.md) for more details on bar sizes, and [AWS_Shell_Interface_Specification.md](../../../docs/AWS_Shell_Interface_Specification.md) for available interfaces between Shell and CL. +All interfaces in this CL example are accessible from the Host on the PF/BARs as stated in the table below. Please See [PCIe Memory Map](../../../docs/AWS_Fpga_Pcie_Memory_Map.md) for more details on bar sizes, and [AWS Shell Interface Specification](../../../docs/AWS_Shell_Interface_Specification.md) for available interfaces between the Shell and the CL. | Interface | PF | BAR | |----------------------------------------------|----|-----| @@ -60,95 +69,84 @@ The interfaces between Shell and CL are accessible from the Host on the PF/BARs | Virtual JTAG | 1 | 2 | | SDA | 1 | 4 | - ## Clocks and Reset -* clk_main_a0 (250 MHz) from Shell for majority of the design except for HBM. -* rst_main_n from Shell sync’d to clk_main_a0. -* clk_hbm_ref (100 MHz) from Shell as reference clock for HBM IP. -* HBM AXI3 interface is clocked by the 450MHz clock generated from the [AWS_CLK_GEN](./../../../common/lib/aws_clk_gen.sv) block. + +- clk_main_a0 (250 MHz) from Shell for majority of the design except for HBM. +- rst_main_n from Shell sync’d to clk_main_a0. +- clk_hbm_ref (100 MHz) from Shell as reference clock for HBM IP. +- HBM AXI3 interface is clocked by the 450MHz clock generated from the [AWS_CLK_GEN](./../../../common/lib/aws_clk_gen.sv) block. The AWS_CLK_GEN block also generates several other clocks to match with the clock recipes supported in F1. Please refer to [AWS_CLK_GEN spec](./../../../docs/AWS_CLK_GEN_spec.md) for details on this block. The [Clock Recipes User Guide](./../../../docs/Clock_Recipes_User_Guide.md) describes various clock recipes available for F2 developers and options on configuring clocks dynamically. The user guide also describes porting of CL designs based on F1 clock recipes into F2. -* NOTE: There is a SW control register at [OCL offset 0x300](#ancHBMAxi4RegisterAddrSpace) to reset only the HBM IP core. This reset register does not reset the whole CL_HBM_AXI4 block. +- NOTE: There is a SW control register at [OCL offset 0x300](#hbm-memory-address-space) to reset only the HBM IP core. This reset register does not reset the whole CL_HBM_AXI4 block. - ## OCL -The [CL_MEM_OCL_DEC](design/cl_mem_ocl_dec.sv) module converts OCL 32-bit AXI-L Interface to simple config bus interface. It consists of an address decoder to access register space of various blocks. See [OCL Address Mapping](#ancOCLRegisterAddressSpace) for availble ranges. - +The [CL_MEM_OCL_DEC](design/cl_mem_ocl_dec.sv) module converts OCL 32-bit AXI-L Interface to simple config bus interface. It consists of an address decoder to access register space of various blocks. See [OCL Address Space](#ocl-address-space) for available ranges. + ## PCIM + The [CL_PCIM_MSTR](../cl_dram_hbm_dma/design/cl_pcim_mstr.sv) module is connected to the 512-bit AXI4 PCIM interface. It consists of AXI4 Traffic Generator capable of issuing Read/Write requests to the Host over the PCIe link. This block can also be used to test the peak PCIe transfer rates across the PCIe link. -While this block is essentially a traffic generator, CL designers could potentially swap this block with their custom Kernel that acts as a PCIe Requestor to the Host Memory. +While this block is essentially a traffic generator, CL designers could potentially swap this block with their custom Kernel that acts as a PCIe Requester to the Host Memory. - ## PCIS -The PCIS is a 512-bit AXI4 interface from the Shell which can be accessed either by Host over PF0-BAR4, or by the XDMA engine in the AWS Shell. The PCIS interface is used in CL_MEM_PERF example to provide datapaths to the DDR and HBM memories in the FPGA. The address range to access DDR and HBM memories is described in [PCIS Memory Address Space](#ancPCISAddressSpace). +The PCIS is a 512-bit AXI4 interface from the Shell which can be accessed either by Host over PF0-BAR4, or by the XDMA engine in the AWS Shell. The PCIS interface is used in CL_MEM_PERF example to provide datapaths to the DDR and HBM memories in the FPGA. The address range to access DDR and HBM memories is described in [PCIS Memory Address Space](#pcis-memory-address-space). -The [CL_AXI_MSTR](../cl_dram_hbm_dma/design/cl_dram_dma_axi_mstr.sv) module is another simple AXI4 traffic genertor whose traffic pattern and access length can be configured using the registers. The AXI4 interface from CL_AXI_MSTR and PCIS feed to CL_AXI_INTERCONNECT which ultimately connects to DDR and HBM based on the access address request. +The [CL_AXI_MSTR](../cl_dram_hbm_dma/design/cl_dram_dma_axi_mstr.sv) module is another simple AXI4 traffic generator whose traffic pattern and access length can be configured using the registers. The AXI4 interface from CL_AXI_MSTR and PCIS feed to CL_AXI_INTERCONNECT which ultimately connects to DDR and HBM based on the access address request. There are two MUXes - one along the datapath to DDR, and another MUX along datapath to HBM. These MUXes default to connecting CL_AXI_INTERCONNECT’s path to the target memories. However, setting these MUXes enables traffic from the ATGs to the target memories. PCIS path to the target memories is disabled when the MUXes are enabled. - ## DDR -AWS provides [SH_DDR](../../../common/shell_stable/design/sh_ddr/synth/sh_ddr.sv) that houses the DDR4 Controller specifically configured to the DDR DIMM on the FPGA Card. The SH_DDR is also connected to the Shell's sh_cl_ddr_stat_* ports to enable Shell to manage DDR calibration upon CL AFI loads. The SH_DDR exposes an AXI4 512-bit interface for the CL logic to perform Read/Write data tranfsers into DDR. - -**NOTE**: Currently SH_DDR supports both 32GB and 64GB dual rank DIMMs. Please refer to [Supported_DDR_Modes.md](./../../../docs/Supported_DDR_Modes.md) for details on supported DDR configurations in `sh_ddr.sv`. +AWS provides [SH_DDR](../../../common/shell_stable/design/sh_ddr/synth/sh_ddr.sv) that houses the DDR4 Controller specifically configured to the DDR DIMM on the FPGA Card. The SH_DDR is also connected to the Shell's sh_cl_ddr_stat_* ports to enable Shell to manage DDR calibration upon CL AFI loads. The SH_DDR exposes an AXI4 512-bit interface for the CL logic to perform Read/Write data transfers into DDR. Please refer to the [Supported DDR Modes](./../../../docs/Supported_DDR_Modes.md) for details on supported DDR configurations in `sh_ddr.sv`. - ## HBM -F2 FPGA has on-chip HBM with a maximum capacity of 16GiB, accessible through 32 AXI3 Channels running at a maximum clock speed of upto 450MHz. CL designs should leverage all the available channels and aim for achieving timing closure of the interface at 450MHz to get the best possible performance out of HBM. HBM offers theoretical max bandwidth of 460GB/s when traffic is active across all the 32 Channels with 450MHz clock. +F2 FPGA has on-chip HBM with a maximum capacity of 16GiB, accessible through 32 AXI3 Channels running at a maximum clock speed of up to 450MHz. CL designs should leverage all the available channels and aim for achieving timing closure of the interface at 450MHz to get the best possible performance out of HBM. HBM offers theoretical max bandwidth of 460GB/s when traffic is active across all the 32 Channels with 450MHz clock. The [CL_HBM_AXI4](design/cl_mem_hbm_axi4.sv) module demonstrates an use case for HBM traffic as shown in the block diagram below: ![Diagram](design/cl_hbm_kernel.png) -CL_HBM_AXI4 exposes an AXI4 512-bit interface and two Configuration Interfaces clocked using the 250MHz clk_main_a0. The Host (PCIS) can access HBM through this AXI4 Interface. The AXI4 interface then connects to 512-to-256 bit width convertor, clock crossing convertors between `clk_main_a0`(250 MHz) and HBM's AXI3 clock (max 450MHz), and AXI4-to-AXI3 protocol convertor to ultimately connect to HBM AXI Channel#0 +CL_HBM_AXI4 exposes an AXI4 512-bit interface and two configuration interfaces clocked using the 250MHz clk_main_a0. The Host (PCIS) can access HBM through this AXI4 Interface. The AXI4 interface then connects to 512-to-256 bit width converter, clock crossing converters between clk_main_a0 and HBM's AXI3 clock, and AXI4-to-AXI3 protocol converter to ultimately connect to HBM AXI Channel#0 The hbm_stat_bus is a simple config bus that connects to CL_HBM_WRAPPER and facilitates access to the Reset Register inside the CL_HBM_WRAPPER (mainly to reset HBM IP and check HBM read). The hbm_kern_cfg_bus is a simple config bus to configure the HBM Performance Kernels (CL_HBM_PERF_KERNEL) -In addition to providing a datapath from PCIS to HBM, the CL_HBM_AXI4 block also instantiates CL_HBM_PERF_KERNEL which is designed to maximize the available bandwidth from HBM. It demonstrates the microachitecture for Customer Kernels interfacing with HBM, supports multiple outstanding transactions in the queue across all 32 channels, with AXI3 interface running at 450MHz clock. This design provides clock domain crossing mechanism, performance measurememt counters along with floorplan and timing constraints to achieve easier timing cloure at 450 MHz. +In addition to providing a datapath from PCIS to HBM, the CL_HBM_AXI4 block also instantiates CL_HBM_PERF_KERNEL which is designed to maximize the available bandwidth from HBM. It demonstrates the microarchitecture for Customer Kernels interfacing with HBM, supports multiple outstanding transactions in the queue across all 32 channels, with AXI3 interface running at 450MHz clock. This design provides clock domain crossing mechanism, performance measurement counters along with floorplan and timing constraints to achieve easier timing closure at 450 MHz. CL_HBM_PERF_KERNEL consists of the following blocks: -* CL_KERNEL_CTL: This is the main controller for the Kernel. It is responsible for posting write/read requests and track pending transactions. The block is capable of producing write and read requests in parallel to saturate all the channels of HBM. Keeping the channels active is key for maximizing the available HBM bandwidth and CL_KERNEL_CTL achieves that by arbitrating and issues multiple outstanding requests. -* CL_KERNEL_REGS: Houses all the control and status registers including performance measurement counters. -* CL_KERNEL_REQ: This block is instantiated inside CL_KERNEL_CTL and is mainly responsible to perform Clock Domain Crossing of read/write requests from clk_main_a0 to clk_hbm domain. This block is replicated to server each channel of the HBM. -* CL_AXI_CTL: Contains the control logic and datapath required to serve the AXI3 read/write requests to the HBM core. This module accepts read/write requests from CL_KERNEL_REQ pipe and interface with HBM’s AXI3 interface. The entire block runs on clk_hbm domain. CL_AXI_CTL is replicated for each HBM channel. Note that, the AXI3 interface for channel#0 is muxed along with the AXI4 data path from the hbm_axi4_bus. Users should enable this mux such that the traffic from CL_AXI_CTL#0 drives into HBM Channel#0. Please see description for details. -* While the data is produced/consumed locally in this specific design, customers will be able to leverage the microarchitecture by feeding the data to/from CL_KERNEL_REQ and interfacing it to their data producer/consumer logic. - +- CL_KERNEL_CTL: This is the main controller for the Kernel. It is responsible for posting write/read requests and track pending transactions. The block is capable of producing write and read requests in parallel to saturate all the channels of HBM. Keeping the channels active is key for maximizing the available HBM bandwidth and CL_KERNEL_CTL achieves that by arbitrating and issues multiple outstanding requests. +- CL_KERNEL_REGS: Houses all the control and status registers including performance measurement counters. +- CL_KERNEL_REQ: This block is instantiated inside CL_KERNEL_CTL and is mainly responsible to perform Clock Domain Crossing of read/write requests from clk_main_a0 to clk_hbm domain. This block is replicated to server each channel of the HBM. +- CL_AXI_CTL: Contains the control logic and datapath required to serve the AXI3 read/write requests to the HBM core. This module accepts read/write requests from CL_KERNEL_REQ pipe and interface with HBM’s AXI3 interface. The entire block runs on clk_hbm domain. CL_AXI_CTL is replicated for each HBM channel. Note that, the AXI3 interface for channel#0 is muxed along with the AXI4 data path from the hbm_axi4_bus. Users should enable this mux such that the traffic from CL_AXI_CTL#0 drives into HBM Channel#0. Please see description for details. +- While the data is produced/consumed locally in this specific design, customers will be able to leverage the microarchitecture by feeding the data to/from CL_KERNEL_REQ and interfacing it to their data producer/consumer logic. CL_HBM_WRAPPER: -* The CL_HBM_WRAPPER block houses the main HBM IP configured in 16GiB capacity with 32- AXI3 Channels running at 450MHz clk_hbm clock. -* The hbm_stats_bus config interface provides access to reset the MMCM and check if the HBM is ready. See registers in CL_HBM_AXI4 Register Address Space for details. +- The CL_HBM_WRAPPER block houses the main HBM IP configured in 16GiB capacity with 32- AXI3 Channels running at 450MHz clk_hbm clock. +- The hbm_stats_bus config interface provides access to reset the MMCM and check if the HBM is ready. See registers in CL_HBM_AXI4 Register Address Space for details. -Please refer to [CL_HBM_AXI4 Register Address Space](#ancHBMAxi4RegisterAddrSpace) for details on register address space and HBM memory address space. +Please refer to [CL_HBM_AXI4 Register Address Space](#cl_hbm_axi4-register-address-space) for details on register address space and HBM memory address space. - ## SDA The SDA interface is shared between two modules: 1. The [CL_SDA_SLV](../cl_dram_hbm_dma/design/cl_sda_slv.sv) module provides access to a 1KB BRAM through SDA 32-bit AXI-L Interface. -2. The [AWS_CLK_GEN](./../../../common/lib/aws_clk_gen.sv) module generates all the required clocks for the design. Please refer to [AWS_CLK_GEN spec](./../../../docs/AWS_CLK_GEN_spec.md) for details on this block. The [Clock Recipes User Guide](./../../../docs/Clock_Recipes_User_Guide.md) describes various clock recipes available for F2 developers and options on configuring clocks dynamically. The user guide also describes porting of CL designs based on F1 clock recipes into F2. +2. The [AWS_CLK_GEN](./../../../common/lib/aws_clk_gen.sv) module generates all the required clocks for the design. Please refer to the [AWS_CLK_GEN specifiction](./../../../docs/AWS_CLK_GEN_spec.md) for details on this block. The [Clock Recipes User Guide](./../../../docs/Clock_Recipes_User_Guide.md) describes various clock recipes available for F2 developers and options on configuring clocks dynamically. The user guide also describes porting of CL designs based on F1 clock recipes into F2. - ## Interrupts The [CL_INT_SLV](../cl_dram_hbm_dma/design/cl_int_tst.sv) module implements simple mechanism to trigger MSIX interrupts to the host over sh_cl_apppf_irq_req/ack interface. SW can check the status of the interrupt triggers and also configure the interrupt masks. The `interrupt_example()` routine in [test_dram_hbm_dma.c](./software/runtime/test_dram_hbm_dma.c) demonstrates interrupts functionality. - ## Virtual JTAG The [CL_ILA](../cl_dram_hbm_dma/design/cl_ila.sv) instantiates the Debug Bridge IP required to support Virtual JTAG and the two example ILAs. One ILA snoops the PCIS bus, whereas second ILA snoops DDR-AXI4 bus. - # Address Space - ## OCL Address Space The OCL AXI-L is decoded into following address ranges for various design blocks: @@ -163,7 +161,6 @@ The OCL AXI-L is decoded into following address ranges for various design blocks | Clock Frequency Measurement| 0x0600 | 0x06FF | CL_CLK_FREQ Block | | Interrupt Generator | 0x0D00 | 0x0DFF | CL_INT_SLV Block | - ## PCIS Memory Address Space | Target Memory | Start Address | End Address | Range | @@ -172,19 +169,16 @@ The OCL AXI-L is decoded into following address ranges for various design blocks | HBM | 0x10_0000_0000 | 0x13_FFFF_FFFF | 16 GB | **NOTE**: Accessing memory beyond DDR and HBM’s range can potentially corrupt the data in either of the memories. -**NOTE**: Please refer to [Supported_DDR_Modes.md](./../../../docs/Supported_DDR_Modes.md) for details on supported DDR configurations in `sh_ddr.sv`. - ## HBM Memory Address Space HBM Memory Address Space is as shown in the [HBM User Guide](https://docs.xilinx.com/r/en-US/pg276-axi-hbm/Port-Descriptions) for 16GB capacity. Each CL_AXI_CTL instantiated in CL_HBM_PERG_KERNEL is mapped to serve the address range defined for each channel in the HBM user guide. For example: * Channel#0 | Start Address = 0x0000_0000 | End Address = 0x1FFF_FFFF * Channel#1 | Start Address = 0x2000_0000 | End Address = 0x3FFF_FFFF and so on... - ## CL_HBM_AXI4 Register Address Space -The table below describes the registers available in CL_HBM_AXI4 block. This includes resgisters inside CL_HBM_WRAPPER and CL_KERNEL_REGS: +The table below describes the registers available in CL_HBM_AXI4 block. This includes registers inside CL_HBM_WRAPPER and CL_KERNEL_REGS: | OCL Address offset | Register Name | Bits | Access | Default Value | Description | |--------------------|-------------------|------|--------|---------------|-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| @@ -193,12 +187,12 @@ The table below describes the registers available in CL_HBM_AXI4 block. This inc | | | 0 | RW | 0x0 | 1'b1 : Reset HBM IP | | | | | | | | | 0x400 | KERN_CFG_REG | 31:1 | RW | 0x0 | Reserved | -| | | 0 | RW | 0x0 | 1'b1 : Enable HBM Channel#0 MUX to drive AXI3 traffic from CL_AXI_CTL#0 to HBM. NOTE: This bit must be set inorder to use CL_HBM_PERF_KERNEL | +| | | 0 | RW | 0x0 | 1'b1 : Enable HBM Channel#0 MUX to drive AXI3 traffic from CL_AXI_CTL#0 to HBM. NOTE: This bit must be set in order to use CL_HBM_PERF_KERNEL | | 0x404 | CHANNEL_AVAIL_REG | 31:0 | RO | 0x20 | total number of HBM channels available for CL_HBM_PERF_KERNEL | | 0x408 | NUM_OT_REG | 31:0 | RO | 0x40 | Number of Outstanding Transactions supported | | 0x40C | CHNL_SEL_REG | 31:0 | RW | 0x0 | Select the Channel number to measure write and read latencies. This field is 0-based. Max Value = 31. | | 0x410 | AXLEN_REG | 31:0 | RW | 0x0 | AWLEN/ARLEN to use. This field is 0-based and the value will be used to drive axi_awlen and axi_arlen signals to HBM. | -| 0x414 | WDATA_PATTERN_REG | 31:0 | RW | 0x0 | Initial 32-bit data patten for writes | +| 0x414 | WDATA_PATTERN_REG | 31:0 | RW | 0x0 | Initial 32-bit data pattern for writes | | 0x418 | WR_CTL_REG | 31:0 | RW | 0x0 | Start write transactions on each channel. Each bit corresponds to a HBM channel. bit[0] = Start write transfers on HBM Channel#0 bit[1] = Start write transfers on HBM Channel#1 .. bit[31] = Start write transfers on HBM Channel#31 | | 0x41C | RD_CTL_REG | 31:0 | RW | 0x0 | Start Read transactions on each channel. Each bit corresponds to a HBM channel. bit[0] = Start Read transfers on HBM Channel#0 bit[1] = Start Read transfers on HBM Channel#1 .. bit[31] = Start Read transfers on HBM Channel#31 | | 0x430 | WR_CYC_CNT_LO_REG | 31:0 | RW | 0x0 | Total number of write requests to HBM aggregated across all HBM channels. LSB 32 bits. SW write 0 to clear. | @@ -207,29 +201,26 @@ The table below describes the registers available in CL_HBM_AXI4 block. This inc | 0x43C | WR_TIMER_HI_REG | 31:0 | RW | 0x0 | Timer during which Write requests were in progress. MSB 32 bits. SW write 0 to WR_TIMER_LO_REG to clear. | | 0x440 | WR_LATENCY_REG | 31:0 | RW | 0x0 | Measure latency between first AW request and B-response from HBM Channel specified in CHNL_SEL_REG | | 0x444 | WR_OT_REG | 31:0 | RO | 0x0 | Pending write requests in the queue. | -| 0x448 | BRESP_ERR_REG | 31:0 | RW | 0x0 | 1 : Bresp error ffrom HBM Channel# corresponding to that bit. SW writes 0 to clear the bit | +| 0x448 | BRESP_ERR_REG | 31:0 | RW | 0x0 | 1'b1 : Bresp error from HBM Channel# corresponding to that bit. SW writes 0 to clear the bit | | 0x450 | RD_CYC_CNT_LO_REG | 31:0 | RW | 0x0 | Total number of Read requests to HBM aggregated across all HBM channels. LSB 32 bits. SW write 0 to clear. | | 0x454 | RD_CYC_CNT_HI_REG | 31:0 | RW | 0x0 | Total number of Read requests to HBM aggregated across all HBM channels. MSB 32 bits. SW write 0 to RD_CYC_CNT_LO_REG to clear this reg. | | 0x458 | RD_TIMER_LO_REG | 31:0 | RW | 0x0 | Timer during which Read requests were in progress. LSB 32 bits. SW write 0 to clear. | | 0x45C | RD_TIMER_HI_REG | 31:0 | RW | 0x0 | Timer during which Read requests were in progress. MSB 32 bits. SW write 0 to RD_TIMER_LO_REG to clear. | | 0x460 | RD_LATENCY_REG | 31:0 | RW | 0x0 | Measure latency between first AR request and R-last response from HBM Channel specified in CHNL_SEL_REG | | 0x464 | RD_OT_REG | 31:0 | RO | 0x0 | Pending Read requests in the queue. | -| 0x468 | RRESP_ERR_REG | 31:0 | RW | 0x0 | 1 : Rresp error ffrom HBM Channel# corresponding to that bit. SW writes 0 to clear the bit | +| 0x468 | RRESP_ERR_REG | 31:0 | RW | 0x0 | 1'b1 : Rresp error from HBM Channel# corresponding to that bit. SW writes 0 to clear the bit | - ## SDA Memory Address Space | Target | Start Address | End Address | Notes | |---------------|---------------|---------------|--------------------------------------| -| SDA_SLV (BRAM)| 0x0 | 0x0004_FFFF | 1KiB BRAM. Upper address rolls over. | -| AWS_CLK_GEN | 0x0050_0000 | 0xFFFF_FFFF | | +| SDA_SLV (BRAM)| 0x0000_0000 | 0x0004_FFFF | 1KB BRAM. Upper address rolls over. | +| AWS_CLK_GEN | 0x0050_0000 | 0xFFFF_FFFF | [AWS_CLK_GEN specifiction](./../../../docs/AWS_CLK_GEN_spec.md)| - # Simulations Please see more details on running simulations in this [README](verif/README.md) - # Software DMA accesses rely on the [XDMA driver](https://github.com/Xilinx/dma_ip_drivers) @@ -257,13 +248,11 @@ This test uses [CL_CLK_FREQ](design/cl_clk_freq.sv) to measure the clock frequen This test uses AWS APIs to configure clock frequencies into [AWS_CLK_GEN](./../../../common/lib/aws_clk_gen.sv) block - ### Compile and run instructions + ```bash cd $CL_DIR/software/runtime - make all - sudo ./test_dram_hbm_dma ``` @@ -272,34 +261,37 @@ sudo ./test_dram_hbm_dma This test runs a software test with HW/SW co-simulation enabled with both DDR and HBM enabled. ### Compile and run instructions + ```bash cd $CL_DIR/software/runtime - make TEST=test_dram_hbm_dma_hwsw_cosim - sudo ./test_dram_hbm_dma_hwsw_cosim ``` + The test can be simulated with XSIM as follows. + ```bash cd $CL_DIR/verif/scripts - make C_TEST=test_dram_hbm_dma_hwsw_cosim ``` - # HBM Performance Tests + A runtime test is provided to measure HBM performance aggregated across all 32 HBM Channels. The runtime test should be run on a real machine consisting of F2 FPGA loaded with CL_MEM_PERF bitstreams. The runtime test [test_hbm_perf32.c](software/runtime/test_hbm_perf32.c) exercises [CL_HBM_PERF_KERNEL](design/cl_hbm_perf_kernel.sv) module to generate data across all 32 channels of the HBM running at 450MHz speeds. The test configures to run traffic across all 32 channels. There are config registers in CL_HBM_PERF_KERNEL that keep track of the number of write/read requests that were serviced and timers during which the CL_HBM_PERF_KERNEL was busy servicing the AXI3 Channels of HBM. The runtime test reads these transaction counters to compute the aggregate HBM performance across all the channels. ## Instructions to run HBM Performance Test -``` +Run the following commands to start the runtime test + +```bash cd $CL_DIR/software/runtime make all sudo ./test_hbm_perf32 ``` -Sample Output: -``` +Sample output: + +```bash =================================================== Running test_hbm_perf32 =================================================== diff --git a/hdk/cl/examples/cl_mem_perf/build/constraints/cl_synth_user.xdc b/hdk/cl/examples/cl_mem_perf/build/constraints/cl_synth_user.xdc index a9a115428..160f6090c 100644 --- a/hdk/cl/examples/cl_mem_perf/build/constraints/cl_synth_user.xdc +++ b/hdk/cl/examples/cl_mem_perf/build/constraints/cl_synth_user.xdc @@ -1,3 +1,21 @@ +# ============================================================================= +# Amazon FPGA Hardware Development Kit +# +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + + ############################################################################### # This contains the CL specific constraints for synthesis at the CL leve ############################################################################### diff --git a/hdk/cl/examples/cl_mem_perf/build/constraints/cl_timing_user.xdc b/hdk/cl/examples/cl_mem_perf/build/constraints/cl_timing_user.xdc index f0c7be3fb..6b20ae57f 100644 --- a/hdk/cl/examples/cl_mem_perf/build/constraints/cl_timing_user.xdc +++ b/hdk/cl/examples/cl_mem_perf/build/constraints/cl_timing_user.xdc @@ -1,3 +1,21 @@ +# ============================================================================= +# Amazon FPGA Hardware Development Kit +# +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + + ############################################################################### # This contains the CL specific timing constraints for CL ############################################################################### diff --git a/hdk/cl/examples/cl_mem_perf/build/constraints/small_shell_cl_pnr_user.xdc b/hdk/cl/examples/cl_mem_perf/build/constraints/small_shell_cl_pnr_user.xdc index 9cf3d025d..d901650b9 100644 --- a/hdk/cl/examples/cl_mem_perf/build/constraints/small_shell_cl_pnr_user.xdc +++ b/hdk/cl/examples/cl_mem_perf/build/constraints/small_shell_cl_pnr_user.xdc @@ -1,8 +1,18 @@ # ============================================================================= -# Copyright 2021 Amazon.com, Inc. or its affiliates. -# All Rights Reserved Worldwide. -# Amazon Confidential information -# Restricted NDA Material +# Amazon FPGA Hardware Development Kit +# +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. # ============================================================================= diff --git a/hdk/cl/examples/cl_mem_perf/build/constraints/xdma_shell_cl_pnr_user.xdc b/hdk/cl/examples/cl_mem_perf/build/constraints/xdma_shell_cl_pnr_user.xdc index 4894e5adc..fa44fae41 100644 --- a/hdk/cl/examples/cl_mem_perf/build/constraints/xdma_shell_cl_pnr_user.xdc +++ b/hdk/cl/examples/cl_mem_perf/build/constraints/xdma_shell_cl_pnr_user.xdc @@ -1,8 +1,18 @@ # ============================================================================= -# Copyright 2021 Amazon.com, Inc. or its affiliates. -# All Rights Reserved Worldwide. -# Amazon Confidential information -# Restricted NDA Material +# Amazon FPGA Hardware Development Kit +# +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. # ============================================================================= diff --git a/hdk/cl/examples/cl_mem_perf/build/scripts/encrypt.tcl b/hdk/cl/examples/cl_mem_perf/build/scripts/encrypt.tcl index 3b2cdf6d2..07e415bad 100644 --- a/hdk/cl/examples/cl_mem_perf/build/scripts/encrypt.tcl +++ b/hdk/cl/examples/cl_mem_perf/build/scripts/encrypt.tcl @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= + # TODO: # Add check if CL_DIR and HDK_SHELL_DIR directories exist diff --git a/hdk/cl/examples/cl_mem_perf/build/scripts/synth_cl_mem_perf.tcl b/hdk/cl/examples/cl_mem_perf/build/scripts/synth_cl_mem_perf.tcl index 944df6598..09c687407 100644 --- a/hdk/cl/examples/cl_mem_perf/build/scripts/synth_cl_mem_perf.tcl +++ b/hdk/cl/examples/cl_mem_perf/build/scripts/synth_cl_mem_perf.tcl @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= + # Common header diff --git a/hdk/cl/examples/cl_mem_perf/design/cl_axi_ctl.sv b/hdk/cl/examples/cl_mem_perf/design/cl_axi_ctl.sv index fb0eee7cf..53c217d54 100644 --- a/hdk/cl/examples/cl_mem_perf/design/cl_axi_ctl.sv +++ b/hdk/cl/examples/cl_mem_perf/design/cl_axi_ctl.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,9 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + + /////////////////////////////////////////////////////////////////////////////////////// // CL_AXI_CTL // ---------- diff --git a/hdk/cl/examples/cl_mem_perf/design/cl_clk_freq.sv b/hdk/cl/examples/cl_mem_perf/design/cl_clk_freq.sv index 9cd513082..a33e20180 100644 --- a/hdk/cl/examples/cl_mem_perf/design/cl_clk_freq.sv +++ b/hdk/cl/examples/cl_mem_perf/design/cl_clk_freq.sv @@ -1,7 +1,7 @@ -/////////////////////////////////////////////////////////////////////////////////// +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -13,6 +13,9 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + + /////////////////////////////////////////////////////////////////////////////////// // Module // ------- diff --git a/hdk/cl/examples/cl_mem_perf/design/cl_hbm_perf_kernel.sv b/hdk/cl/examples/cl_mem_perf/design/cl_hbm_perf_kernel.sv index 85651cf39..126b4a5fd 100644 --- a/hdk/cl/examples/cl_mem_perf/design/cl_hbm_perf_kernel.sv +++ b/hdk/cl/examples/cl_mem_perf/design/cl_hbm_perf_kernel.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,9 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + + /////////////////////////////////////////////////////////////////////////////////////// // CL_HBM_PERF_KERNEL // ------------------- diff --git a/hdk/cl/examples/cl_mem_perf/design/cl_id_defines.vh b/hdk/cl/examples/cl_mem_perf/design/cl_id_defines.vh index 0740b0808..2ddf9ee45 100644 --- a/hdk/cl/examples/cl_mem_perf/design/cl_id_defines.vh +++ b/hdk/cl/examples/cl_mem_perf/design/cl_id_defines.vh @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + // CL_SH_ID0 // - PCIe Vendor/Device ID Values diff --git a/hdk/cl/examples/cl_mem_perf/design/cl_kernel_ctl.sv b/hdk/cl/examples/cl_mem_perf/design/cl_kernel_ctl.sv index aa239e760..5956f75d4 100644 --- a/hdk/cl/examples/cl_mem_perf/design/cl_kernel_ctl.sv +++ b/hdk/cl/examples/cl_mem_perf/design/cl_kernel_ctl.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,9 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + + /////////////////////////////////////////////////////////////////////////////////////// // CL_KERNEL_CTL // -------------- diff --git a/hdk/cl/examples/cl_mem_perf/design/cl_kernel_regs.sv b/hdk/cl/examples/cl_mem_perf/design/cl_kernel_regs.sv index d8651757a..44ee059f9 100644 --- a/hdk/cl/examples/cl_mem_perf/design/cl_kernel_regs.sv +++ b/hdk/cl/examples/cl_mem_perf/design/cl_kernel_regs.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,9 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + + /////////////////////////////////////////////////////////////////////////////////////// // CL_KERNEL_REGS // -------------- diff --git a/hdk/cl/examples/cl_mem_perf/design/cl_kernel_req.sv b/hdk/cl/examples/cl_mem_perf/design/cl_kernel_req.sv index 948ae9ffb..2d2918d88 100644 --- a/hdk/cl/examples/cl_mem_perf/design/cl_kernel_req.sv +++ b/hdk/cl/examples/cl_mem_perf/design/cl_kernel_req.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,9 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + + /////////////////////////////////////////////////////////////////////////////////////// // CL_KERNEL_REQ // -------------- diff --git a/hdk/cl/examples/cl_mem_perf/design/cl_mem_hbm_axi4.sv b/hdk/cl/examples/cl_mem_perf/design/cl_mem_hbm_axi4.sv index b9d8cfb0d..5765d4c58 100644 --- a/hdk/cl/examples/cl_mem_perf/design/cl_mem_hbm_axi4.sv +++ b/hdk/cl/examples/cl_mem_perf/design/cl_mem_hbm_axi4.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + //============================================================================= // CL_MEM_HBM_AXI4 diff --git a/hdk/cl/examples/cl_mem_perf/design/cl_mem_hbm_wrapper.sv b/hdk/cl/examples/cl_mem_perf/design/cl_mem_hbm_wrapper.sv index 29076fca3..0426a12bd 100644 --- a/hdk/cl/examples/cl_mem_perf/design/cl_mem_hbm_wrapper.sv +++ b/hdk/cl/examples/cl_mem_perf/design/cl_mem_hbm_wrapper.sv @@ -1,7 +1,7 @@ -//------------------------------------------------------------------------------------------------------------------------------- +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -13,8 +13,9 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. -// Restricted NDA Material -//------------------------------------------------------------------------------------------------------------------------------- +// ============================================================================ + + //=============================================================================================================================== // HBM Wrapper // - Wraper for HBM IP diff --git a/hdk/cl/examples/cl_mem_perf/design/cl_mem_ocl_dec.sv b/hdk/cl/examples/cl_mem_perf/design/cl_mem_ocl_dec.sv index 4255199ca..c48e21950 100644 --- a/hdk/cl/examples/cl_mem_perf/design/cl_mem_ocl_dec.sv +++ b/hdk/cl/examples/cl_mem_perf/design/cl_mem_ocl_dec.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,9 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + + //=============================================================================================================================== // OCL Decode // pcim_tst_cfg_bus = 0x000 - 0x0FF diff --git a/hdk/cl/examples/cl_mem_perf/design/cl_mem_pcis_dec.sv b/hdk/cl/examples/cl_mem_perf/design/cl_mem_pcis_dec.sv index 223466bbb..329a4f501 100644 --- a/hdk/cl/examples/cl_mem_perf/design/cl_mem_pcis_dec.sv +++ b/hdk/cl/examples/cl_mem_perf/design/cl_mem_pcis_dec.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + //============================================================================= // PCIS Decode diff --git a/hdk/cl/examples/cl_mem_perf/design/cl_mem_perf.sv b/hdk/cl/examples/cl_mem_perf/design/cl_mem_perf.sv index 39920b60e..7fd4157b6 100644 --- a/hdk/cl/examples/cl_mem_perf/design/cl_mem_perf.sv +++ b/hdk/cl/examples/cl_mem_perf/design/cl_mem_perf.sv @@ -1,7 +1,7 @@ -//============================================================================= +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -13,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + //============================================================================= // Top level module file for CL_MEM_PERF diff --git a/hdk/cl/examples/cl_mem_perf/design/cl_mem_perf_defines.vh b/hdk/cl/examples/cl_mem_perf/design/cl_mem_perf_defines.vh index d92bf4d05..7d368bfae 100644 --- a/hdk/cl/examples/cl_mem_perf/design/cl_mem_perf_defines.vh +++ b/hdk/cl/examples/cl_mem_perf/design/cl_mem_perf_defines.vh @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + `ifndef CL_MEM_PERF_DEFINES `define CL_MEM_PERF_DEFINES diff --git a/hdk/cl/examples/cl_mem_perf/software/include/cl_dram_dma.h b/hdk/cl/examples/cl_mem_perf/software/include/cl_dram_dma.h index c35a76f66..7d7a29f97 100644 --- a/hdk/cl/examples/cl_mem_perf/software/include/cl_dram_dma.h +++ b/hdk/cl/examples/cl_mem_perf/software/include/cl_dram_dma.h @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -11,4 +12,5 @@ // or in the "license" file accompanying this file. This file is distributed on // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and -// limitations under the License. \ No newline at end of file +// limitations under the License. +// ============================================================================ diff --git a/hdk/cl/examples/cl_mem_perf/software/include/sh_dpi_tasks.h b/hdk/cl/examples/cl_mem_perf/software/include/sh_dpi_tasks.h index 9c7a39127..f74162e62 100644 --- a/hdk/cl/examples/cl_mem_perf/software/include/sh_dpi_tasks.h +++ b/hdk/cl/examples/cl_mem_perf/software/include/sh_dpi_tasks.h @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + #ifndef SH_DPI_TASKS #define SH_DPI_TASKS diff --git a/hdk/cl/examples/cl_mem_perf/software/runtime/Makefile b/hdk/cl/examples/cl_mem_perf/software/runtime/Makefile index fee640cac..be4dcd394 100644 --- a/hdk/cl/examples/cl_mem_perf/software/runtime/Makefile +++ b/hdk/cl/examples/cl_mem_perf/software/runtime/Makefile @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= + INCLUDES = -I$(SDK_DIR)/userspace/include diff --git a/hdk/cl/examples/cl_mem_perf/software/runtime/test_aws_clk_gen.c b/hdk/cl/examples/cl_mem_perf/software/runtime/test_aws_clk_gen.c index 91d647ae4..33c567d31 100644 --- a/hdk/cl/examples/cl_mem_perf/software/runtime/test_aws_clk_gen.c +++ b/hdk/cl/examples/cl_mem_perf/software/runtime/test_aws_clk_gen.c @@ -1,19 +1,21 @@ -/* - * Amazon FPGA Hardware Development Kit - * - * Copyright 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Licensed under the Amazon Software License (the "License"). You may not use - * this file except in compliance with the License. A copy of the License is - * located at - * - * http://aws.amazon.com/asl/ - * - * or in the "license" file accompanying this file. This file is distributed on - * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or - * implied. See the License for the specific language governing permissions and - * limitations under the License. - */ +// ============================================================================ +// Amazon FPGA Hardware Development Kit +// +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// +// Licensed under the Amazon Software License (the "License"). You may not use +// this file except in compliance with the License. A copy of the License is +// located at +// +// http://aws.amazon.com/asl/ +// +// or in the "license" file accompanying this file. This file is distributed on +// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +// implied. See the License for the specific language governing permissions and +// limitations under the License. +// ============================================================================ + + //-------------------------------------------------------------------------------------- // Measure frequency of clocks from AWS_CLK_GEN IP // NOTE: Works only on cl_dram_hbm_dma bitstreams diff --git a/hdk/cl/examples/cl_mem_perf/software/runtime/test_clk_freq.c b/hdk/cl/examples/cl_mem_perf/software/runtime/test_clk_freq.c index 3ff3a9e22..a3ab8b62a 100644 --- a/hdk/cl/examples/cl_mem_perf/software/runtime/test_clk_freq.c +++ b/hdk/cl/examples/cl_mem_perf/software/runtime/test_clk_freq.c @@ -1,19 +1,21 @@ -/* - * Amazon FPGA Hardware Development Kit - * - * Copyright 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Licensed under the Amazon Software License (the "License"). You may not use - * this file except in compliance with the License. A copy of the License is - * located at - * - * http://aws.amazon.com/asl/ - * - * or in the "license" file accompanying this file. This file is distributed on - * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or - * implied. See the License for the specific language governing permissions and - * limitations under the License. - */ +// ============================================================================ +// Amazon FPGA Hardware Development Kit +// +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// +// Licensed under the Amazon Software License (the "License"). You may not use +// this file except in compliance with the License. A copy of the License is +// located at +// +// http://aws.amazon.com/asl/ +// +// or in the "license" file accompanying this file. This file is distributed on +// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +// implied. See the License for the specific language governing permissions and +// limitations under the License. +// ============================================================================ + + //-------------------------------------------------------------------------------------- // Dynamically configure clock frequencies using AWS_CLK_GEN block // NOTE: Works only on cl_dram_hbm_dma bitstreams diff --git a/hdk/cl/examples/cl_mem_perf/software/runtime/test_dram_dma_common.c b/hdk/cl/examples/cl_mem_perf/software/runtime/test_dram_dma_common.c index 3591aaf3c..2c2fcd44e 100644 --- a/hdk/cl/examples/cl_mem_perf/software/runtime/test_dram_dma_common.c +++ b/hdk/cl/examples/cl_mem_perf/software/runtime/test_dram_dma_common.c @@ -1,19 +1,20 @@ -/* - * Amazon FPGA Hardware Development Kit - * - * Copyright 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Licensed under the Amazon Software License (the "License"). You may not use - * this file except in compliance with the License. A copy of the License is - * located at - * - * http://aws.amazon.com/asl/ - * - * or in the "license" file accompanying this file. This file is distributed on - * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or - * implied. See the License for the specific language governing permissions and - * limitations under the License. - */ +// ============================================================================ +// Amazon FPGA Hardware Development Kit +// +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// +// Licensed under the Amazon Software License (the "License"). You may not use +// this file except in compliance with the License. A copy of the License is +// located at +// +// http://aws.amazon.com/asl/ +// +// or in the "license" file accompanying this file. This file is distributed on +// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +// implied. See the License for the specific language governing permissions and +// limitations under the License. +// ============================================================================ + #include #include diff --git a/hdk/cl/examples/cl_mem_perf/software/runtime/test_dram_dma_common.h b/hdk/cl/examples/cl_mem_perf/software/runtime/test_dram_dma_common.h index 225cc4d0f..492950218 100644 --- a/hdk/cl/examples/cl_mem_perf/software/runtime/test_dram_dma_common.h +++ b/hdk/cl/examples/cl_mem_perf/software/runtime/test_dram_dma_common.h @@ -1,19 +1,20 @@ -/* - * Amazon FPGA Hardware Development Kit - * - * Copyright 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Licensed under the Amazon Software License (the "License"). You may not use - * this file except in compliance with the License. A copy of the License is - * located at - * - * http://aws.amazon.com/asl/ - * - * or in the "license" file accompanying this file. This file is distributed on - * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or - * implied. See the License for the specific language governing permissions and - * limitations under the License. - */ +// ============================================================================ +// Amazon FPGA Hardware Development Kit +// +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// +// Licensed under the Amazon Software License (the "License"). You may not use +// this file except in compliance with the License. A copy of the License is +// located at +// +// http://aws.amazon.com/asl/ +// +// or in the "license" file accompanying this file. This file is distributed on +// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +// implied. See the License for the specific language governing permissions and +// limitations under the License. +// ============================================================================ + #pragma once diff --git a/hdk/cl/examples/cl_mem_perf/software/runtime/test_dram_dma_hwsw_cosim.c b/hdk/cl/examples/cl_mem_perf/software/runtime/test_dram_dma_hwsw_cosim.c index 5444622af..fa95bb4c7 100644 --- a/hdk/cl/examples/cl_mem_perf/software/runtime/test_dram_dma_hwsw_cosim.c +++ b/hdk/cl/examples/cl_mem_perf/software/runtime/test_dram_dma_hwsw_cosim.c @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + #include #include @@ -62,7 +65,7 @@ int test_main(uint32_t *exit_code) #elif defined(SV_TEST) void test_main(uint32_t *exit_code) -#else +#else int main(int argc, char **argv) #endif diff --git a/hdk/cl/examples/cl_mem_perf/software/runtime/test_dram_hbm_dma.c b/hdk/cl/examples/cl_mem_perf/software/runtime/test_dram_hbm_dma.c index 40ce9893c..d3928d0ea 100644 --- a/hdk/cl/examples/cl_mem_perf/software/runtime/test_dram_hbm_dma.c +++ b/hdk/cl/examples/cl_mem_perf/software/runtime/test_dram_hbm_dma.c @@ -1,19 +1,20 @@ -/* - * Amazon FPGA Hardware Development Kit - * - * Copyright 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Licensed under the Amazon Software License (the "License"). You may not use - * this file except in compliance with the License. A copy of the License is - * located at - * - * http://aws.amazon.com/asl/ - * - * or in the "license" file accompanying this file. This file is distributed on - * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or - * implied. See the License for the specific language governing permissions and - * limitations under the License. - */ +// ============================================================================ +// Amazon FPGA Hardware Development Kit +// +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// +// Licensed under the Amazon Software License (the "License"). You may not use +// this file except in compliance with the License. A copy of the License is +// located at +// +// http://aws.amazon.com/asl/ +// +// or in the "license" file accompanying this file. This file is distributed on +// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +// implied. See the License for the specific language governing permissions and +// limitations under the License. +// ============================================================================ + #include #include diff --git a/hdk/cl/examples/cl_mem_perf/software/runtime/test_hbm_perf32.c b/hdk/cl/examples/cl_mem_perf/software/runtime/test_hbm_perf32.c index 2b9c01664..50b91790b 100644 --- a/hdk/cl/examples/cl_mem_perf/software/runtime/test_hbm_perf32.c +++ b/hdk/cl/examples/cl_mem_perf/software/runtime/test_hbm_perf32.c @@ -1,19 +1,21 @@ -/* - * Amazon FPGA Hardware Development Kit - * - * Copyright 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Licensed under the Amazon Software License (the "License"). You may not use - * this file except in compliance with the License. A copy of the License is - * located at - * - * http://aws.amazon.com/asl/ - * - * or in the "license" file accompanying this file. This file is distributed on - * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or - * implied. See the License for the specific language governing permissions and - * limitations under the License. - */ +// ============================================================================ +// Amazon FPGA Hardware Development Kit +// +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// +// Licensed under the Amazon Software License (the "License"). You may not use +// this file except in compliance with the License. A copy of the License is +// located at +// +// http://aws.amazon.com/asl/ +// +// or in the "license" file accompanying this file. This file is distributed on +// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +// implied. See the License for the specific language governing permissions and +// limitations under the License. +// ============================================================================ + + //-------------------------------------------------------------------------------------- // Measure HBM performance by enabling all the 32 channels in HBM // NOTE: Works only on cl_dram_hbm_dma bitstreams diff --git a/hdk/cl/examples/cl_mem_perf/software/src/test_dram_dma.c b/hdk/cl/examples/cl_mem_perf/software/src/test_dram_dma.c index 8b230ba34..acbb39c30 100644 --- a/hdk/cl/examples/cl_mem_perf/software/src/test_dram_dma.c +++ b/hdk/cl/examples/cl_mem_perf/software/src/test_dram_dma.c @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + #include #include diff --git a/hdk/cl/examples/cl_mem_perf/software/src/test_null.c b/hdk/cl/examples/cl_mem_perf/software/src/test_null.c index 13b81b3a6..04c278623 100644 --- a/hdk/cl/examples/cl_mem_perf/software/src/test_null.c +++ b/hdk/cl/examples/cl_mem_perf/software/src/test_null.c @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ #include diff --git a/hdk/cl/examples/cl_mem_perf/verif/README.md b/hdk/cl/examples/cl_mem_perf/verif/README.md index 8bc70a257..480972101 100644 --- a/hdk/cl/examples/cl_mem_perf/verif/README.md +++ b/hdk/cl/examples/cl_mem_perf/verif/README.md @@ -1,8 +1,51 @@ -This readme provides information about the simulation environment for the cl_mem_perf example. For more details about overall HDK simulation environment and CL bringup in simulation please refer to [RTL Simulation Guide for HDK Design Flow](../../../../docs/RTL_Simulation_Guide_for_HDK_Design_Flow.md). -# CL_MEM_PERF example simulation - -The system verilog simulation tests can be run from the [$CL_DIR/verif/scripts](scripts) directory with all supported simulators (HBM is only supported in VCS & QUESTA). You can run tests by calling the make target for that test located in [$CL_DIR/verif/scripts/Makefile.tests](Makefile.tests): +# CL_MEM_PERF Example Simulation + +## Table of Contents + +- [CL\_MEM\_PERF Example Simulation](#cl_mem_perf-example-simulation) + - [Table of Contents](#table-of-contents) + - [Overview](#overview) + - [Dump Waves](#dump-waves) + - [System Verilog Tests](#system-verliog-tests) + - [test\_aws\_clk\_gen\_recipe.sv (VCS and QUESTA only)](#test_aws_clk_gen_recipesv-vcs-and-questa-only) + - [test\_clk\_recipe.sv](#test_clk_recipesv) + - [test\_ddr\_peek\_poke.sv](#test_ddr_peek_pokesv) + - [test\_ddr.sv](#test_ddrsv) + - [test\_hbm.sv](#test_hbmsv) + - [test\_hbm\_perf32.sv](#test_hbm_perf32sv) + - [test\_hbm\_perf\_kernel\_cfg.sv](#test_hbm_perf_kernel_cfgsv) + - [test\_hbm\_perf\_random.sv](#test_hbm_perf_randomsv) + - [test\_dram\_dma.sv](#test_dram_dmasv) + - [test\_dram\_dma\_rnd.sv](#test_dram_dma_rndsv) + - [test\_dma\_pcim\_concurrent.sv](#test_dma_pcim_concurrentsv) + - [test\_dma\_pcis\_concurrent.sv](#test_dma_pcis_concurrentsv) + - [test\_dma\_sda\_concurrent.sv](#test_dma_sda_concurrentsv) + - [test\_dram\_dma\_4k\_crossing.sv](#test_dram_dma_4k_crossingsv) + - [test\_dram\_dma\_allgn\_addr\_4k.sv](#test_dram_dma_allgn_addr_4ksv) + - [test\_dram\_dma\_single\_beat\_4k.sv](#test_dram_dma_single_beat_4ksv) + - [test\_dram\_dma\_axi\_mstr.sv](#test_dram_dma_axi_mstrsv) + - [test\_int.sv](#test_intsv) + - [test\_peek\_poke.sv](#test_peek_pokesv) + - [test\_peek\_poke\_wc.sv](#test_peek_poke_wcsv) + - [test\_peek\_poke\_len.sv](#test_peek_poke_lensv) + - [test\_peek\_poke\_rnd\_lengths.sv](#test_peek_poke_rnd_lengthssv) + - [test\_peek\_poke\_pcis\_axsize.sv](#test_peek_poke_pcis_axsizesv) + - [test\_ddr\_peek\_bdr\_walking\_ones](#test_ddr_peek_bdr_walking_ones) + - [test\_sda.sv](#test_sdasv) + - [test\_null.sv](#test_nullsv) + - [AXI\_MEMORY\_MODEL Mode Simulations](#axi_memory_model-mode-simulations) + - [test\_dram\_dma\_mem\_model\_bdr\_wr](#test_dram_dma_mem_model_bdr_wr) + - [test\_dram\_dma\_mem\_model\_bdr\_rd](#test_dram_dma_mem_model_bdr_rd) + - [DDR Backdoor Loading](#ddr-backdoor-loading) + - [HW/SW Co-Simulation Test](#hwsw-co-simulation-test) + + +## Overview + +This readme provides information about the simulation environment for the `cl_mem_perf` example. For more details about overall HDK simulation environment and CL bringup in simulation please refer to [RTL Simulation Guide for HDK Design Flow](../../../../docs/RTL_Simulation_Guide_for_HDK_Design_Flow.md). + +The SystemVerilog (SV) simulation can be run from the `$CL_DIR/verif/scripts/` directory with all supported simulators (HBM simulation using VCS & QUESTA is strongly recommended). You can run tests by calling the make target for that test located in `$CL_DIR/verif/scripts/Makefile.tests`: ```bash make test_ddr # Runs with XSIM by default @@ -12,23 +55,13 @@ make test_ddr QUESTA=1 make test_hbm # Runs with VCS by default ``` -Alternatively, you can run each test by setting TEST= followed by the environment variables required to run that test. +Alternatively, you can run each test by setting `TEST=\` followed by the environment variables required to run that test. ```bash make TEST=test_dram_dma # Runs with XSIM by default make TEST=test_dram_dma VCS=1 make TEST=test_dram_dma QUESTA=1 -# To Run simulations with a 32 GB DDR DIMM (without user-controlled auto-precharge mode) -make TEST=test_dram_dma USE_32GB_DDR_DIMM=1 - -# To Run simulations with a 32 GB DDR DIMM (with user-controlled auto-precharge mode) -make TEST=test_dram_dma USE_AP_32GB_DDR_DIMM=1 - -# To Run simulations with a 64 GB DDR DIMM (without user-controlled auto-precharge mode) -# NOTE: CL_DRAM_HBM_DMA does not currently have a datapath to all 64 GB of DDR. Only first 32GB is accessible. -make TEST=test_dram_dma USE_64GB_DDR_DIMM=1 - # To Run simulations with a 64 GB DDR DIMM # With user-controlled auto-precharge mode make TEST=test_dram_dma USE_AP_64GB_DDR_DIMM=1 @@ -50,7 +83,7 @@ test_ddr_peek_bdr_walking_ones **NOTE**: Please refer to [Supported_DDR_Modes.md](./../../../../docs/Supported_DDR_Modes.md) for details on supported DDR configurations. -The HW/SW co-simulation tests can be run from the [verif/scripts](scripts) directory with all supported simulators: +The HW/SW co-simulation tests can be run from the `verif/scripts/` directory with all supported simulators: ```bash make C_TEST=test_dram_dma_hwsw_cosim # Runs with XSIM by default @@ -69,9 +102,9 @@ Note that the appropriate simulators must be installed. For information about how to dump waves with XSIM or VCS, please refer to [debugging-custom-logic-using-the-aws-hdk](../../../../docs/RTL_Simulation_Guide_for_HDK_Design_Flow.md#debugging-custom-logic-using-the-aws-hdk) -## System Verliog Tests +## System Verilog Tests -The system verilog tests are located at [verif/tests](tests). Most tests include `base_test_utils.svh` which includes common signals and tasks used across tests. Please refer to this file for the DPI-C tasks used. Information about each test can be found below. +The SystemVerilog tests are located at `verif/tests/`. Most tests include `base_test_utils.svh` which includes common signals and tasks used across tests. Please refer to this file for the DPI-C tasks used. Information about each test can be found below. ### test_aws_clk_gen_recipe.sv (VCS and QUESTA only) This test programs valid clock recipes to the CL and verifies the corresponding clock frequencies. @@ -89,10 +122,10 @@ This test programs the CL_TST (ATG) to generate traffic to access all four DDR c This test programs the CL_TST (ATG) to generate traffic to access both HBM stacks. ### test_hbm_perf32.sv -This test programs the HBM performance kernel to run all 32 channels for maximum bandiwdth. The kernel collects timer and bandwidth statistics and stores them in registers. At the end of the test, the performance is calculated and printed in the `sim.log`. +This test programs the HBM performance kernel to run all 32 channels for maximum bandwidth. The kernel collects timer and bandwidth statistics and stores them in registers. At the end of the test, the performance is calculated and printed in the `sim.log`. ### test_hbm_perf_kernel_cfg.sv -This test excercises each register in the HBM performance kernel configuration space. +This test exercises each register in the HBM performance kernel configuration space. ### test_hbm_perf_random.sv This test executes the same flow as `test_hbm_perf32.sv` except with a random axi length and a random number of channels. @@ -142,18 +175,6 @@ This test programs tester block to do PCIM reads and writes with random lengths ### test_peek_poke_pcis_axsize.sv This test does PCIS peek and poke with different sizes. Although shell model allows different size transfers on PCIS interface, Shell only supports transfer of size 6 on PCIS interface. -## _AXI_MEMORY_MODEL mode simulations_ -AXI_MEMORY_MODEL mode can be used for better simulation perfornmance. AXI_MEMORY_MODEL mode enables a test to run with AXI memory models instead of DDR memory. The documentation can be found in AXI memory model section at [RTL simulation guide](../../../../docs/RTL_Simulation_Guide_for_HDK_Design_Flow.md). Any test that accesses DDR memory can be run in AXI_MEMORY_MODEL mode. Below are some example tests for ECC and backdoor loading support features of AXI memory model. - -### test_dram_dma_mem_model_bdr_wr -This test backdoor writes AXI memory model, reads through frontdoor and checks that the data matches. - -### test_dram_dma_mem_model_bdr_rd -This test backdoor reads AXI memory model, writes through frontdoor and checks that the data matches. - -## _DDR backdoor loading_ -The tests below use backdoor loading to populate DDR memory. The description of DDR backdoor loading can be found in DDR backdoor loading support section at [RTL simulation guide](../../../../docs/RTL_Simulation_Guide_for_HDK_Design_Flow.md) - ### test_ddr_peek_bdr_walking_ones DDR test which uses backdoor loading to populate DDR memory. The test writes data(walking ones) for different addresses. The test backdoor loads DDR memory and reads through frontdoor and checks that the data matches. @@ -161,8 +182,22 @@ DDR test which uses backdoor loading to populate DDR memory. The test writes dat This test does transfers to different addresses on SDA AXIL interface. ### test_null.sv -test_null is not an actual test. This is a base system verilog file needed for HW/SW co-simulation +test_null is not an actual test. This is a base SystemVerilog file needed for HW/SW co-simulation + + +## AXI_MEMORY_MODEL Mode Simulations + +AXI_MEMORY_MODEL mode can be used for better simulation performance. AXI_MEMORY_MODEL mode enables a test to run with AXI memory models instead of DDR memory. The documentation can be found in AXI memory model section at [RTL simulation guide](../../../../docs/RTL_Simulation_Guide_for_HDK_Design_Flow.md). Any test that accesses DDR memory can be run in AXI_MEMORY_MODEL mode. Below are some example tests for ECC and backdoor loading support features of AXI memory model. + +### test_dram_dma_mem_model_bdr_wr +This test backdoor writes AXI memory model, reads through frontdoor and checks that the data matches. + +### test_dram_dma_mem_model_bdr_rd +This test backdoor reads AXI memory model, writes through frontdoor and checks that the data matches. + +## DDR Backdoor Loading +The description of DDR backdoor loading can be found in DDR backdoor loading support section at [RTL simulation guide](../../../../docs/RTL_Simulation_Guide_for_HDK_Design_Flow.md) -## HW/SW co-simulation Test +## HW/SW Co-Simulation Test -The software test with HW/SW co-simulation support [test_dram_dma_hwsw_cosim.c](../software/runtime/test_dram_dma_hwsw_cosim.c) can be found at [software/runtime](../software/runtime). For Information about how HW/SW co-simulation support can be added to a software test please refer to "Code changes to enable HW/SW co-simulation" section in [RTL simulation guide](../../../../docs/RTL_Simulation_Guide_for_HDK_Design_Flow.md) +The software test with HW/SW co-simulation support [test_dram_dma_hwsw_cosim.c](../software/runtime/test_dram_dma_hwsw_cosim.c) can be found at `software/runtime/`. For Information about how HW/SW co-simulation support can be added to a software test please refer to "Code changes to enable HW/SW co-simulation" section in [RTL simulation guide](../../../../docs/RTL_Simulation_Guide_for_HDK_Design_Flow.md) diff --git a/hdk/cl/examples/cl_mem_perf/verif/scripts/Makefile b/hdk/cl/examples/cl_mem_perf/verif/scripts/Makefile index 2f8667c36..0d3cc12a0 100644 --- a/hdk/cl/examples/cl_mem_perf/verif/scripts/Makefile +++ b/hdk/cl/examples/cl_mem_perf/verif/scripts/Makefile @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= + ifndef HDK_COMMON_DIR $(error Environment variable HDK_COMMON_DIR not set. Please source hdk_setup.sh) diff --git a/hdk/cl/examples/cl_mem_perf/verif/scripts/Makefile.questa b/hdk/cl/examples/cl_mem_perf/verif/scripts/Makefile.questa index a1dbd54a0..2ced9e239 100644 --- a/hdk/cl/examples/cl_mem_perf/verif/scripts/Makefile.questa +++ b/hdk/cl/examples/cl_mem_perf/verif/scripts/Makefile.questa @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2022 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= ################################################################## diff --git a/hdk/cl/examples/cl_mem_perf/verif/scripts/Makefile.tests b/hdk/cl/examples/cl_mem_perf/verif/scripts/Makefile.tests index b65f96f11..f4a676721 100644 --- a/hdk/cl/examples/cl_mem_perf/verif/scripts/Makefile.tests +++ b/hdk/cl/examples/cl_mem_perf/verif/scripts/Makefile.tests @@ -1,7 +1,25 @@ +# ============================================================================= +# Amazon FPGA Hardware Development Kit +# +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + + test_dram_dma_axi_mstr: TEST=test_dram_dma_axi_mstr test_dram_dma_axi_mstr: all -#Not supporting until XSIM related issues fixed +#Not supporting until XSIM related issues fixed test_dram_dma_4k_crossing: TEST=test_dram_dma_4k_crossing test_dram_dma_4k_crossing: check_xsim all @@ -41,15 +59,15 @@ test_dma_pcis_concurrent: all test_dma_sda_concurrent: TEST=test_dma_sda_concurrent test_dma_sda_concurrent: all -#Not supporting until XSIM related issues fixed +#Not supporting until XSIM related issues fixed test_dram_dma: TEST=test_dram_dma test_dram_dma: check_xsim all -#Not supporting until XSIM related issues fixed +#Not supporting until XSIM related issues fixed test_dram_dma_align_addr_4k: TEST=test_dram_dma_align_addr_4k test_dram_dma_align_addr_4k: check_xsim all -#Not supporting until XSIM related issues fixed +#Not supporting until XSIM related issues fixed test_dram_dma_single_beat_4k: TEST=test_dram_dma_single_beat_4k test_dram_dma_single_beat_4k: check_xsim all @@ -61,7 +79,7 @@ test_dram_dma_single_beat_4k: check_xsim all # test_dram_dma_mem_model_bdr_wr: DEFAULT_DEFINES += +define+NO_DDR+FAST_SIM_MODE # test_dram_dma_mem_model_bdr_wr: all -#Not supporting until XSIM related issues fixed +#Not supporting until XSIM related issues fixed test_dram_dma_rnd: TEST=test_dram_dma_rnd test_dram_dma_rnd: check_xsim all diff --git a/hdk/cl/examples/cl_mem_perf/verif/scripts/Makefile.vcs b/hdk/cl/examples/cl_mem_perf/verif/scripts/Makefile.vcs index 7e5dca668..7b9c1a6ef 100644 --- a/hdk/cl/examples/cl_mem_perf/verif/scripts/Makefile.vcs +++ b/hdk/cl/examples/cl_mem_perf/verif/scripts/Makefile.vcs @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,15 +13,16 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= ################################################################## ## Makefile For VCS compiles and simulations ## Step to run : -## 1. make create_libs VCS=1 -> To generate xilinx compile +## 1. make create_libs VCS=1 -> To generate xilinx compile ## libraries. This is a one time step ## 2. make all VCS=1 -> Runs the test -## +define+MODEL_DEBUG_MEMORY +define+MODEL_DEBUG_CMDS +## +define+MODEL_DEBUG_MEMORY +define+MODEL_DEBUG_CMDS ################################################################## FILTER_OUT_HBM_META_INJECTIONS = grep -v "\*\*\*Meta" | sed '/^$$/d' @@ -33,7 +35,7 @@ compile: $(COMPLIB_DIR) cd $(SIM_DIR) && vlogan -g -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog +systemverilogext+.sv +libext+.sv +libext+.v -full64 -lca -v2005 +v2k -l compile.vlogan.log -debug_all -f $(SCRIPTS_DIR)/top.$(SIMULATOR).f +define+VCS +define+DMA_TEST $(DEFAULT_DEFINES) +lint=TFIPC-L cd $(SIM_DIR) && touch bd_2e02_lmb_bram_I_0.mem bd_2e02_second_lmb_bram_I_0.mem cd $(SIM_DIR) && vcs tb $(TEST) $(C_FILES) +error+9999 glbl -debug_region=cell+encrypt +warn=noFCDCI,noFCICIO +note=noFCICIO -CFLAGS "-I$(C_SDK_USR_INC_DIR)" -CFLAGS "-I$(C_SDK_USR_UTILS_DIR) -std=gnu99" -CFLAGS "-I$(C_COMMON_DIR)/include" -CFLAGS "-I$(C_COMMON_DIR)/src" -CFLAGS "-DSV_TEST" -CFLAGS "-DSCOPE" -CFLAGS "-I$(C_INC_DIR)" "-I$(C_SRC_DIR)" -debug_all -M +lint=TFIPC-L -debug_all -debug_pp glbl -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog -full64 +memcbk -licqueue -lca -v2005 -l compile.vcs.log +plusarg_save +timeout=1ms - + run: ifeq ($(TEST),test_null) ifneq ($(C_TEST),test_null) diff --git a/hdk/cl/examples/cl_mem_perf/verif/scripts/Makefile.vivado b/hdk/cl/examples/cl_mem_perf/verif/scripts/Makefile.vivado index f0645161f..5719d3efe 100644 --- a/hdk/cl/examples/cl_mem_perf/verif/scripts/Makefile.vivado +++ b/hdk/cl/examples/cl_mem_perf/verif/scripts/Makefile.vivado @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= + ################################################################## ## Makefile For Vivado compiles and simulations diff --git a/hdk/cl/examples/cl_mem_perf/verif/scripts/top.questa.f b/hdk/cl/examples/cl_mem_perf/verif/scripts/top.questa.f index 67e60b6ff..59c1064d2 100644 --- a/hdk/cl/examples/cl_mem_perf/verif/scripts/top.questa.f +++ b/hdk/cl/examples/cl_mem_perf/verif/scripts/top.questa.f @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= + +define+CL_NAME=cl_mem_perf +define+DISABLE_VJTAG_DEBUG diff --git a/hdk/cl/examples/cl_mem_perf/verif/scripts/top.vcs.f b/hdk/cl/examples/cl_mem_perf/verif/scripts/top.vcs.f index 67e60b6ff..59c1064d2 100644 --- a/hdk/cl/examples/cl_mem_perf/verif/scripts/top.vcs.f +++ b/hdk/cl/examples/cl_mem_perf/verif/scripts/top.vcs.f @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= + +define+CL_NAME=cl_mem_perf +define+DISABLE_VJTAG_DEBUG diff --git a/hdk/cl/examples/cl_mem_perf/verif/scripts/top.vivado.f b/hdk/cl/examples/cl_mem_perf/verif/scripts/top.vivado.f index 5ea4a7298..83d9fc5ac 100644 --- a/hdk/cl/examples/cl_mem_perf/verif/scripts/top.vivado.f +++ b/hdk/cl/examples/cl_mem_perf/verif/scripts/top.vivado.f @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,9 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= + + --define CL_NAME=cl_mem_perf --define VIVADO_SIM diff --git a/hdk/cl/examples/cl_mem_perf/verif/scripts/top.xsim.f b/hdk/cl/examples/cl_mem_perf/verif/scripts/top.xsim.f index 0c6f88293..c594af995 100644 --- a/hdk/cl/examples/cl_mem_perf/verif/scripts/top.xsim.f +++ b/hdk/cl/examples/cl_mem_perf/verif/scripts/top.xsim.f @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= + -define CL_NAME=cl_mem_perf -define DISABLE_VJTAG_DEBUG diff --git a/hdk/cl/examples/cl_mem_perf/verif/scripts/waves.tcl b/hdk/cl/examples/cl_mem_perf/verif/scripts/waves.tcl index 4b14d0da6..584895d66 100644 --- a/hdk/cl/examples/cl_mem_perf/verif/scripts/waves.tcl +++ b/hdk/cl/examples/cl_mem_perf/verif/scripts/waves.tcl @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= + set curr_wave [current_wave_config] if { [string length $curr_wave] == 0 } { @@ -23,5 +26,5 @@ if { [string length $curr_wave] == 0 } { } } -run 200 us +run 200 us quit diff --git a/hdk/cl/examples/cl_mem_perf/verif/tests/base_test_utils.svh b/hdk/cl/examples/cl_mem_perf/verif/tests/base_test_utils.svh index dea13cda8..75f47c1c1 100644 --- a/hdk/cl/examples/cl_mem_perf/verif/tests/base_test_utils.svh +++ b/hdk/cl/examples/cl_mem_perf/verif/tests/base_test_utils.svh @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2023 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,27 +13,18 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. - +// ============================================================================ `include "common_base_test.svh" - `define DDR_BASE_ADDR 64'h0 -`ifdef AWS_SIM_32GB_DDR - `define DDR_LEVEL_1 `_8_GB - `define DDR_LEVEL_2 `_16_GB - `define DDR_LEVEL_3 `_24_GB - `define HBM_BASE_ADDR `_64_GB -`elsif AWS_SIM_64GB_DDR - `define DDR_LEVEL_1 `_16_GB - `define DDR_LEVEL_2 `_32_GB - `define DDR_LEVEL_3 `_48_GB - `define HBM_BASE_ADDR `_64_GB -`endif +`define DDR_LEVEL_1 `_16_GB +`define DDR_LEVEL_2 `_32_GB +`define DDR_LEVEL_3 `_48_GB +`define HBM_BASE_ADDR `_64_GB `include "aws_clk_gen_utils.svh" `include "cl_dram_hbm_dma_utils.svh" `include "cl_mem_perf_utils.svh" - diff --git a/hdk/cl/examples/cl_mem_perf/verif/tests/cl_mem_perf_utils.svh b/hdk/cl/examples/cl_mem_perf/verif/tests/cl_mem_perf_utils.svh index 58db2cf14..76011f6c5 100644 --- a/hdk/cl/examples/cl_mem_perf/verif/tests/cl_mem_perf_utils.svh +++ b/hdk/cl/examples/cl_mem_perf/verif/tests/cl_mem_perf_utils.svh @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2023 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,7 +13,7 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. - +// ============================================================================ task program_cl_hbm_perf_kernel(logic [31:0] selected_channel_for_latency_measurement = 32'd0, logic [3:0] axlen = 4'hf, logic [31:0] data_pattern = 32'hCAFE_FA15); diff --git a/hdk/cl/examples/cl_mem_perf/verif/tests/test_aws_clk_gen_recipe.sv b/hdk/cl/examples/cl_mem_perf/verif/tests/test_aws_clk_gen_recipe.sv index 30a05853d..596495729 100644 --- a/hdk/cl/examples/cl_mem_perf/verif/tests/test_aws_clk_gen_recipe.sv +++ b/hdk/cl/examples/cl_mem_perf/verif/tests/test_aws_clk_gen_recipe.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2023 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ module test_aws_clk_gen_recipe(); diff --git a/hdk/cl/examples/cl_mem_perf/verif/tests/test_dram_dma_axi_mstr.sv b/hdk/cl/examples/cl_mem_perf/verif/tests/test_dram_dma_axi_mstr.sv index 4b1c24428..8ec10ba10 100644 --- a/hdk/cl/examples/cl_mem_perf/verif/tests/test_dram_dma_axi_mstr.sv +++ b/hdk/cl/examples/cl_mem_perf/verif/tests/test_dram_dma_axi_mstr.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + module test_dram_dma_axi_mstr(); @@ -62,7 +65,7 @@ module test_dram_dma_axi_mstr(); // Set AXI Master Command Registers // addr = 0x1_a021f700, Write $display("[%t] : Setting DDR Base Address Command Registers ", $realtime);// addr = 0x1_a021f700 - tb.poke_ocl(.addr(AXI_MSTR_CAHR_ADDR), .data(DDR_BASE_HI_ADDR)); // Set High Address -- + tb.poke_ocl(.addr(AXI_MSTR_CAHR_ADDR), .data(DDR_BASE_HI_ADDR)); // Set High Address -- tb.poke_ocl(.addr(AXI_MSTR_CALR_ADDR), .data(DDR_BASE_LO_ADDR + i)); // Set Low Address tb.poke_ocl(.addr(AXI_MSTR_CWDR_ADDR), .data(DDR_BASE_DATA | i)); // Set Write Data tb.poke_ocl(.addr(AXI_MSTR_CCR_ADDR), .data(32'h0000_0001)); // Issue Write Command @@ -82,7 +85,7 @@ module test_dram_dma_axi_mstr(); end // for (int i = 0; i <= 12; i=i+4) //} for (int i = 0; i <= 12; i=i+4) begin //{ - tb.poke_ocl(.addr(AXI_MSTR_CAHR_ADDR), .data(DDR_BASE_HI_ADDR)); // Set High Address -- + tb.poke_ocl(.addr(AXI_MSTR_CAHR_ADDR), .data(DDR_BASE_HI_ADDR)); // Set High Address -- tb.poke_ocl(.addr(AXI_MSTR_CALR_ADDR), .data(DDR_BASE_LO_ADDR + i)); // Set Low Address tb.poke_ocl(.addr(AXI_MSTR_CWDR_ADDR), .data(DDR_BASE_DATA | i)); // Set Write Data @@ -190,7 +193,7 @@ for (int i = 0; i <= 12; i=i+4) begin //{ // Set AXI Master Command Registers // addr = 0x1_a021f700, Write $display("[%t] : Setting DDR Base Address Command Registers ", $realtime);// addr = 0x1_a021f700 - tb.poke_ocl(.addr(AXI_MSTR_CAHR_ADDR), .data(DDR_OFFSET_16_GB_HI_ADDR)); // Set High Address -- + tb.poke_ocl(.addr(AXI_MSTR_CAHR_ADDR), .data(DDR_OFFSET_16_GB_HI_ADDR)); // Set High Address -- tb.poke_ocl(.addr(AXI_MSTR_CALR_ADDR), .data(DDR_OFFSET_16_GB_LO_ADDR + i)); // Set Low Address tb.poke_ocl(.addr(AXI_MSTR_CWDR_ADDR), .data(DDR_OFFSET_16_GB_DATA | i)); // Set Write Data tb.poke_ocl(.addr(AXI_MSTR_CCR_ADDR), .data(32'h0000_0001)); // Issue Write Command @@ -210,7 +213,7 @@ for (int i = 0; i <= 12; i=i+4) begin //{ end // for (int i = 0; i <= 12; i=i+4) //} for (int i = 0; i <= 12; i=i+4) begin //{ - tb.poke_ocl(.addr(AXI_MSTR_CAHR_ADDR), .data(DDR_OFFSET_16_GB_HI_ADDR)); // Set High Address -- + tb.poke_ocl(.addr(AXI_MSTR_CAHR_ADDR), .data(DDR_OFFSET_16_GB_HI_ADDR)); // Set High Address -- tb.poke_ocl(.addr(AXI_MSTR_CALR_ADDR), .data(DDR_OFFSET_16_GB_LO_ADDR + i)); // Set Low Address tb.poke_ocl(.addr(AXI_MSTR_CWDR_ADDR), .data(DDR_OFFSET_16_GB_DATA | i)); // Set Write Data @@ -255,7 +258,7 @@ for (int i = 0; i <= 12; i=i+4) begin //{ // Set AXI Master Command Registers // addr = 0x1_a021f700, Write $display("[%t] : Setting DDR Base Address Command Registers ", $realtime);// addr = 0x1_a021f700 - tb.poke_ocl(.addr(AXI_MSTR_CAHR_ADDR), .data(DDR_OFFSET_24_GB_HI_ADDR)); // Set High Address -- + tb.poke_ocl(.addr(AXI_MSTR_CAHR_ADDR), .data(DDR_OFFSET_24_GB_HI_ADDR)); // Set High Address -- tb.poke_ocl(.addr(AXI_MSTR_CALR_ADDR), .data(DDR_OFFSET_24_GB_LO_ADDR + i)); // Set Low Address tb.poke_ocl(.addr(AXI_MSTR_CWDR_ADDR), .data(DDR_OFFSET_24_GB_DATA | i)); // Set Write Data tb.poke_ocl(.addr(AXI_MSTR_CCR_ADDR), .data(32'h0000_0001)); // Issue Write Command @@ -275,7 +278,7 @@ for (int i = 0; i <= 12; i=i+4) begin //{ end // for (int i = 0; i <= 12; i=i+4) //} for (int i = 0; i <= 12; i=i+4) begin //{ - tb.poke_ocl(.addr(AXI_MSTR_CAHR_ADDR), .data(DDR_OFFSET_24_GB_HI_ADDR)); // Set High Address -- + tb.poke_ocl(.addr(AXI_MSTR_CAHR_ADDR), .data(DDR_OFFSET_24_GB_HI_ADDR)); // Set High Address -- tb.poke_ocl(.addr(AXI_MSTR_CALR_ADDR), .data(DDR_OFFSET_24_GB_LO_ADDR + i)); // Set Low Address tb.poke_ocl(.addr(AXI_MSTR_CWDR_ADDR), .data(DDR_OFFSET_24_GB_DATA | i)); // Set Write Data @@ -321,4 +324,3 @@ end //} $finish; end // initial begin endmodule // test_dram_dma_axi_mstr - diff --git a/hdk/cl/examples/cl_mem_perf/verif/tests/test_hbm_perf32.sv b/hdk/cl/examples/cl_mem_perf/verif/tests/test_hbm_perf32.sv index 234513549..0323ece3c 100644 --- a/hdk/cl/examples/cl_mem_perf/verif/tests/test_hbm_perf32.sv +++ b/hdk/cl/examples/cl_mem_perf/verif/tests/test_hbm_perf32.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2022 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + module test_hbm_perf32(); diff --git a/hdk/cl/examples/cl_mem_perf/verif/tests/test_hbm_perf_kernel_cfg.sv b/hdk/cl/examples/cl_mem_perf/verif/tests/test_hbm_perf_kernel_cfg.sv index c19d9c5c2..90a6643f1 100644 --- a/hdk/cl/examples/cl_mem_perf/verif/tests/test_hbm_perf_kernel_cfg.sv +++ b/hdk/cl/examples/cl_mem_perf/verif/tests/test_hbm_perf_kernel_cfg.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2022 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + module test_hbm_perf_kernel_cfg(); diff --git a/hdk/cl/examples/cl_mem_perf/verif/tests/test_hbm_perf_random.sv b/hdk/cl/examples/cl_mem_perf/verif/tests/test_hbm_perf_random.sv index f1b82ca30..264165d25 100644 --- a/hdk/cl/examples/cl_mem_perf/verif/tests/test_hbm_perf_random.sv +++ b/hdk/cl/examples/cl_mem_perf/verif/tests/test_hbm_perf_random.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2022 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + module test_hbm_perf_random(); diff --git a/hdk/cl/examples/cl_sde/README.md b/hdk/cl/examples/cl_sde/README.md index 401dc9041..3e3841c54 100644 --- a/hdk/cl/examples/cl_sde/README.md +++ b/hdk/cl/examples/cl_sde/README.md @@ -5,26 +5,29 @@ 1. [Overview](#Overview) 2. [Functional Description](#FuncDesc) 3. [Interfaces and Address Range](#Interfaces) -3. [Software](#Software) -3. [Metadata](#Metadata) +4. [Software](#Software) +5. [Metadata](#Metadata) ⚠️**Note**: Please note that Virtual Ethernet/SDE is not supported by Vitis (XRT). - ## Overview -The CL_SDE example implements the FPGA custom logic used to generate the AFI to demonstrate the [Virtual Ethernet Application](../../../../sdk/apps/virtual-ethernet/doc/Virtual_Ethernet_Application_Guide.md). The CL_SDE demonstrates the following - + +The CL_SDE example implements the FPGA custom logic used to generate the AFI to demonstrate the [Virtual Ethernet Application](../../../../sdk/apps/virtual-ethernet/doc/Virtual_Ethernet_Application_Guide.md). The CL_SDE demonstrates the following: + 1. Using the [Streaming Data Engine](https://github.com/aws/aws-fpga/blob/-/sdk/apps/virtual-ethernet/doc/SDE_HW_Guide.md) (SDE) IP Block in your custom logic. 2. Connectivity between the [Virtual Ethernet Application](../../../../sdk/apps/virtual-ethernet/doc/Virtual_Ethernet_Application_Guide.md) and the SDE. 3. Connectivity between the Shell and the SDE. -3. Clocks and Resets for the SDE. -4. Floorplanning and Implemention with the SDE including pipelining for AXI buses, resets etc. +4. Clocks and Resets for the SDE. +5. Floorplanning and Implementation with the SDE including pipelining for AXI buses, resets etc. ### System Diagram + ![Diagram](./design/CL_SDE_Block_Diagram.jpg) - ## Functional Description -The following functionality is implemented in the CL_SDE - + +The following functionality is implemented in the CL_SDE: + 1. Capability to loopback from H2C and C2H. 2. Memory to store and read H2C packets for H2C functional testing 3. AXI Stream Traffic Generator for C2H functional and performance testing @@ -34,22 +37,26 @@ The following functionality is implemented in the CL_SDE - See [SDE HW Guide](https://github.com/aws/aws-fpga/blob/-/sdk/apps/virtual-ethernet/doc/SDE_HW_Guide.md) for details about the functional description of the SDE. - ## Interfaces and Address Range + ### Interfaces + CL_SDE uses three interfaces from the Shell. The PCIS interface is used to provide connectivity between the [Virtual Ethernet Application](../../../../sdk/apps/virtual-ethernet/doc/Virtual_Ethernet_Application_Guide.md) and the SDE. The OCL interface is used to provide connectivity between the host and all the test/control/utility blocks (except the SDE). The PCIM interfaces is used by the SDE to read and write to host memory. ### Address Range + #### PCIS + | Low Address | High Address | Description | |-------------|--------------|-------------| | 0x00_0000_0000 | 0x00_0000_3FFF | [SDE](https://github.com/aws/aws-fpga/blob/-/sdk/apps/virtual-ethernet/doc/SDE_HW_Guide.md) | | 0x00_0000_4000 | 0x1F_FFFF_FFFF | Unused | #### OCL + | Low Address | High Address | Description | |-------------|--------------|-------------| | 0x0000_0000 | 0x0000_017F | AXI-Stream Automatic Traffic Generator | @@ -60,13 +67,12 @@ The PCIM interfaces is used by the SDE to read and write to host memory. | 0x0000_2000 | 0x0000_2FFF | CL Reset and Control | | 0x0000_3000 | 0x0200_0000 | Unused | - - ## Software + The software is provided as part of the [Virtual Ethernet Application](../../../../sdk/apps/virtual-ethernet/doc/Virtual_Ethernet_Application_Guide.md). - ## Metadata + The following table displays information about the CL that is required to register it as an AFI with AWS. Alternatively, you can directly use a pre-generated AFI for this CL. | Key | Value | diff --git a/hdk/cl/examples/cl_sde/build/constraints/cl_synth_user.xdc b/hdk/cl/examples/cl_sde/build/constraints/cl_synth_user.xdc index 9b7250813..04c4c35a0 100644 --- a/hdk/cl/examples/cl_sde/build/constraints/cl_synth_user.xdc +++ b/hdk/cl/examples/cl_sde/build/constraints/cl_synth_user.xdc @@ -1,5 +1,21 @@ +# ============================================================================= +# Amazon FPGA Hardware Development Kit +# +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + + ## # This contains the CL specific constraints for synthesis at the CL level ## set_property MAX_FANOUT 50 [get_nets -of_objects [get_pins WRAPPER_INST/CL/SH_DDR/ddr_cores.DDR4_0/inst/div_clk_rst_r1_reg/Q]] ## set_property MAX_FANOUT 50 [get_nets -of_objects [get_pins WRAPPER_INST/CL/CL_PCIM_MSTR/CL_TST_PCI/sync_rst_n_reg/Q]] - - diff --git a/hdk/cl/examples/cl_sde/build/constraints/cl_timing_user.xdc b/hdk/cl/examples/cl_sde/build/constraints/cl_timing_user.xdc index 3ba545c8d..8565d98de 100644 --- a/hdk/cl/examples/cl_sde/build/constraints/cl_timing_user.xdc +++ b/hdk/cl/examples/cl_sde/build/constraints/cl_timing_user.xdc @@ -1,3 +1,21 @@ +# ============================================================================= +# Amazon FPGA Hardware Development Kit +# +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + + ############################################################################### # This contains the CL specific timing constraints for CL ############################################################################### diff --git a/hdk/cl/examples/cl_sde/build/constraints/small_shell_cl_pnr_user.xdc b/hdk/cl/examples/cl_sde/build/constraints/small_shell_cl_pnr_user.xdc index 9559e5c87..16765a6e9 100644 --- a/hdk/cl/examples/cl_sde/build/constraints/small_shell_cl_pnr_user.xdc +++ b/hdk/cl/examples/cl_sde/build/constraints/small_shell_cl_pnr_user.xdc @@ -1,8 +1,18 @@ # ============================================================================= -# Copyright 2021 Amazon.com, Inc. or its affiliates. -# All Rights Reserved Worldwide. -# Amazon Confidential information -# Restricted NDA Material +# Amazon FPGA Hardware Development Kit +# +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. # ============================================================================= diff --git a/hdk/cl/examples/cl_sde/build/constraints/xdma_shell_cl_pnr_user.xdc b/hdk/cl/examples/cl_sde/build/constraints/xdma_shell_cl_pnr_user.xdc index de912b64d..1e50a629f 100644 --- a/hdk/cl/examples/cl_sde/build/constraints/xdma_shell_cl_pnr_user.xdc +++ b/hdk/cl/examples/cl_sde/build/constraints/xdma_shell_cl_pnr_user.xdc @@ -1,8 +1,18 @@ # ============================================================================= -# Copyright 2021 Amazon.com, Inc. or its affiliates. -# All Rights Reserved Worldwide. -# Amazon Confidential information -# Restricted NDA Material +# Amazon FPGA Hardware Development Kit +# +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. # ============================================================================= diff --git a/hdk/cl/examples/cl_sde/build/scripts/encrypt.tcl b/hdk/cl/examples/cl_sde/build/scripts/encrypt.tcl index 7de76ed6b..6d3f24535 100644 --- a/hdk/cl/examples/cl_sde/build/scripts/encrypt.tcl +++ b/hdk/cl/examples/cl_sde/build/scripts/encrypt.tcl @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= set TARGET_DIR $scripts_dir/../src_post_encryption diff --git a/hdk/cl/examples/cl_sde/build/scripts/synth_cl_sde.tcl b/hdk/cl/examples/cl_sde/build/scripts/synth_cl_sde.tcl index 5355e9aee..73ce9b067 100644 --- a/hdk/cl/examples/cl_sde/build/scripts/synth_cl_sde.tcl +++ b/hdk/cl/examples/cl_sde/build/scripts/synth_cl_sde.tcl @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= # Common header diff --git a/hdk/cl/examples/cl_sde/design/axi_prot_chk.sv b/hdk/cl/examples/cl_sde/design/axi_prot_chk.sv index 78239fc46..b5c411da5 100644 --- a/hdk/cl/examples/cl_sde/design/axi_prot_chk.sv +++ b/hdk/cl/examples/cl_sde/design/axi_prot_chk.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016-2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ module axi_prot_chk #(parameter ID_WIDTH=16, @@ -27,12 +29,12 @@ module axi_prot_chk #(parameter ID_WIDTH=16, input cfg_chk_wr, input cfg_chk_rd, input [31:0] cfg_chk_wdata, - + output logic chk_cfg_ack, output logic [31:0] chk_cfg_rdata, output logic wr_last_error, - + input [ID_WIDTH-1:0] awid, input [ADDR_WIDTH-1:0] awaddr, input [LEN_WIDTH-1:0] awlen, @@ -88,7 +90,7 @@ module axi_prot_chk #(parameter ID_WIDTH=16, logic cfg_chk_rd_q; logic cfg_chk_wr_re; logic cfg_chk_rd_re; - + // Write registers always @(posedge clk) begin cfg_chk_wr_q <= cfg_chk_wr; @@ -99,13 +101,13 @@ module axi_prot_chk #(parameter ID_WIDTH=16, assign clr_wr_last_incomplete = cfg_chk_wr_re & (cfg_chk_addr == 12'h0) & cfg_chk_wdata[1]; assign clr_wr_last_early = cfg_chk_wr_re & (cfg_chk_addr == 12'h0) & cfg_chk_wdata[0]; - + // Read data & Ack always @(posedge clk) begin chk_cfg_ack <= (cfg_chk_wr || cfg_chk_rd); - chk_cfg_rdata <= (cfg_chk_addr == 12'h0) ? {wr_last_incomplete, wr_last_early} : + chk_cfg_rdata <= (cfg_chk_addr == 12'h0) ? {wr_last_incomplete, wr_last_early} : (cfg_chk_addr == 12'h4) ? err_addr[31:0] : - (cfg_chk_addr == 12'h8) ? err_addr[63:32] : + (cfg_chk_addr == 12'h8) ? err_addr[63:32] : err_id; end @@ -126,7 +128,7 @@ module axi_prot_chk #(parameter ID_WIDTH=16, ); assign aw_fifo_pop = aw_fifo_valid & wr_fifo_valid & wr_fifo_out_wlast; assign {aw_fifo_out_id, aw_fifo_out_len, aw_fifo_out_addr} = aw_fifo_pop_data; - + // Push W Channel into a FIFO ram_fifo_ft #(.WIDTH(1), .PIPELINE(0)) WR_FIFO @@ -142,12 +144,12 @@ module axi_prot_chk #(parameter ID_WIDTH=16, .wmark (wr_fifo_full) ); - assign wr_fifo_pop = wr_fifo_valid; + assign wr_fifo_pop = wr_fifo_valid; assign wr_fifo_out_wlast = wr_fifo_pop_data; assign set_wr_last_incomplete = ~(wr_last_incomplete || wr_last_early) & wr_fifo_valid & aw_fifo_valid & (aw_fifo_out_len == wr_beat) & ~wr_fifo_out_wlast; assign set_wr_last_early = ~(wr_last_incomplete || wr_last_early) & wr_fifo_valid & aw_fifo_valid & (aw_fifo_out_len != wr_beat) & wr_fifo_out_wlast; - + // Check number of wr beats always @(posedge clk) if (!rst_n) begin @@ -160,29 +162,22 @@ module axi_prot_chk #(parameter ID_WIDTH=16, end else begin wr_beat <= wr_fifo_out_wlast & wr_fifo_valid & aw_fifo_valid ? 0 : - wr_fifo_valid & aw_fifo_valid ? wr_beat + 1 : + wr_fifo_valid & aw_fifo_valid ? wr_beat + 1 : wr_beat; - + wr_last_incomplete <= set_wr_last_incomplete ? 1'b1 : clr_wr_last_incomplete ? 1'b0 : wr_last_incomplete; - + wr_last_early <= set_wr_last_early ? 1'b1 : clr_wr_last_early ? 1'b0 : wr_last_early; - + err_addr <= (set_wr_last_incomplete || set_wr_last_early) ? aw_fifo_out_addr : err_addr; err_id <= (set_wr_last_incomplete || set_wr_last_early) ? aw_fifo_out_id : err_id; wr_last_error <= wr_last_incomplete || wr_last_early; - - end // else: !if(!rst_n) - -endmodule // axi_prot_chk - - - + end // else: !if(!rst_n) - - +endmodule // axi_prot_chk diff --git a/hdk/cl/examples/cl_sde/design/cl_id_defines.vh b/hdk/cl/examples/cl_sde/design/cl_id_defines.vh index c34a7f0c4..cd2eaa8af 100644 --- a/hdk/cl/examples/cl_sde/design/cl_id_defines.vh +++ b/hdk/cl/examples/cl_sde/design/cl_id_defines.vh @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + // CL_SH_ID0 // - PCIe Vendor/Device ID Values @@ -29,5 +32,3 @@ // 15: 0: PCIe Subsystem Vendor ID // - A PCIe Subsystem/Subsystem Vendor ID of 0 (zero) is not valid `define CL_SH_ID1 32'h1D51_FEDC - - diff --git a/hdk/cl/examples/cl_sde/design/cl_pkt_tst.sv b/hdk/cl/examples/cl_sde/design/cl_pkt_tst.sv index 1b8da1050..4ca8550a4 100644 --- a/hdk/cl/examples/cl_sde/design/cl_pkt_tst.sv +++ b/hdk/cl/examples/cl_sde/design/cl_pkt_tst.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016-2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + `define CFG_ADDR_TX_CFG 8'h00 `define CFG_ADDR_TX_SEED0 8'h04 @@ -1083,4 +1086,3 @@ end // if (TX_ONLY == 0) endmodule // cl_pkt_tst - diff --git a/hdk/cl/examples/cl_sde/design/cl_sde.sv b/hdk/cl/examples/cl_sde/design/cl_sde.sv index a9525b3fa..ad7840b8e 100644 --- a/hdk/cl/examples/cl_sde/design/cl_sde.sv +++ b/hdk/cl/examples/cl_sde/design/cl_sde.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016-2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ // CL Streaming diff --git a/hdk/cl/examples/cl_sde/design/cl_sde_defines.vh b/hdk/cl/examples/cl_sde/design/cl_sde_defines.vh index 923b784a2..e990a3002 100644 --- a/hdk/cl/examples/cl_sde/design/cl_sde_defines.vh +++ b/hdk/cl/examples/cl_sde/design/cl_sde_defines.vh @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + `ifndef CL_SDE_DEFINES `define CL_SDE_DEFINES diff --git a/hdk/cl/examples/cl_sde/design/cl_sde_srm.sv b/hdk/cl/examples/cl_sde/design/cl_sde_srm.sv index e52c1d05f..357aa829d 100644 --- a/hdk/cl/examples/cl_sde/design/cl_sde_srm.sv +++ b/hdk/cl/examples/cl_sde/design/cl_sde_srm.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016-2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + //Registers // @@ -355,4 +358,3 @@ assign ots_keep = (cfg_lb_mode)? inp_lb_keep: tst_keep; assign ots_user = (cfg_lb_mode)? inp_lb_user: 0; endmodule - diff --git a/hdk/cl/examples/cl_sde/design/cl_tst.sv b/hdk/cl/examples/cl_sde/design/cl_tst.sv index dbc10afa1..6cd4a9d7f 100644 --- a/hdk/cl/examples/cl_sde/design/cl_tst.sv +++ b/hdk/cl/examples/cl_sde/design/cl_tst.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ module cl_tst #(parameter DATA_WIDTH=512, parameter NUM_RD_TAG=512) ( diff --git a/hdk/cl/examples/cl_sde/design/ila_axi4_wrapper.sv b/hdk/cl/examples/cl_sde/design/ila_axi4_wrapper.sv index c54e94446..3523d7ea7 100644 --- a/hdk/cl/examples/cl_sde/design/ila_axi4_wrapper.sv +++ b/hdk/cl/examples/cl_sde/design/ila_axi4_wrapper.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,9 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + + //--------------------------------------------------------------------------------- // NOTE: ila_axi4 core supports only Maximum DATA width = 32 on WDATA and RDATA // **** AXI_DATA_WIDTH <= 32 diff --git a/hdk/cl/examples/cl_sde/design/sde.sv b/hdk/cl/examples/cl_sde/design/sde.sv index 3edaf7bb3..aa2dd3360 100644 --- a/hdk/cl/examples/cl_sde/design/sde.sv +++ b/hdk/cl/examples/cl_sde/design/sde.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016-2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,12 +13,14 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + // SDE Top Level module sde #(parameter bit C2H_ONLY = 0, parameter bit H2C_ONLY = 0, - + parameter H2C_PCIM_MAX_RD_SIZE = 0, // 0 - 512B, 1 - 1KB, 2 - 2KB, 3 - 4KB parameter C2H_PCIM_MAX_WR_SIZE = 3, // 0 - 512B, 1 - 1KB, 2 - 2KB, 3 - 4KB @@ -27,36 +30,36 @@ module sde #(parameter bit C2H_ONLY = 0, parameter PCIM_ADDR_WIDTH = 64, parameter PCIM_NUM_OT_RD = 64, - + parameter PCIS_DATA_WIDTH = 512, parameter PCIS_ID_WIDTH = 16, parameter PCIS_LEN_WIDTH = 8, parameter PCIS_ADDR_WIDTH = 64, - + parameter bit C2H_DESC_TYPE = 0, // 0 - Regular, 1 - Compact - + parameter C2H_DESC_RAM_DEPTH = 64, - + parameter C2H_AXIS_DATA_WIDTH = 512, parameter C2H_USER_BIT_WIDTH = C2H_DESC_TYPE ? 1 : 64, - + parameter C2H_BUF_DEPTH = 512, - + parameter bit H2C_DESC_TYPE = 0, parameter H2C_DESC_RAM_DEPTH = 64, - + parameter H2C_AXIS_DATA_WIDTH = 512, parameter H2C_USER_BIT_WIDTH = H2C_DESC_TYPE ? 1 : 64, - + parameter H2C_BUF_DEPTH = 512, - + parameter H2C_PKT_SIZE_BYTES = 64, - - + + parameter C2H_PCIM_DM_AWID = 0, // This is the AWID used for write accesses from C2H Data Mover parameter C2H_PCIM_WB_AWID = 1, // This is the AWID used for write accesses from C2H Write Back Block parameter H2C_PCIM_WB_AWID = 2, // This is the AWID used for write accesses from H2C Write Back Block - + parameter C2H_PCIM_DESC_ARID = 0, // This is the ARID used for read access from the C2H Desc Block parameter H2C_PCIM_DESC_ARID = 1, // This is the ARID used for read access from the H2C Desc Block parameter H2C_PCIM_DM_ARID = 2 // This is the ARID used for write accesses from H2C Data Mover @@ -64,7 +67,7 @@ module sde #(parameter bit C2H_ONLY = 0, ( input clk, input rst_n, - + // PCIS Interface input [PCIS_ID_WIDTH-1:0] pcis_awid, input [PCIS_ADDR_WIDTH-1:0] pcis_awaddr, @@ -93,7 +96,7 @@ module sde #(parameter bit C2H_ONLY = 0, output logic pcis_rlast, output logic pcis_rvalid, input pcis_rready, - + // PCIM Interface output logic pcim_awvalid, output logic [PCIM_ID_WIDTH-1:0] pcim_awid, @@ -130,7 +133,7 @@ module sde #(parameter bit C2H_ONLY = 0, input [C2H_USER_BIT_WIDTH-1:0] c2h_axis_user, input c2h_axis_last, output logic c2h_axis_ready, - + // H2C AXI-Stream Interface output logic h2c_axis_valid, output logic [H2C_AXIS_DATA_WIDTH-1:0] h2c_axis_data, @@ -149,33 +152,33 @@ module sde #(parameter bit C2H_ONLY = 0, logic c2h_sync_rst_n; logic h2c_sync_rst_n; logic pm_sync_rst_n; - + logic c2h_ps_desc_wr_req; logic [C2H_DESC_WIDTH-1:0] c2h_ps_desc_wdata; logic c2h_ps_desc_ack; - + logic h2c_ps_desc_wr_req; logic [H2C_DESC_WIDTH-1:0] h2c_ps_desc_wdata; logic h2c_ps_desc_ack; - + logic h2c_ps_pkt_wr_req; logic [H2C_PKT_WIDTH-1:0] h2c_ps_pkt_wdata; logic h2c_ps_pkt_ack; - + logic pm_ps_cfg_wr_req; logic pm_ps_cfg_rd_req; logic [15:0] pm_ps_cfg_addr; logic [31:0] pm_ps_cfg_wdata; logic pm_ps_cfg_ack; logic [31:0] pm_ps_cfg_rdata; - + logic c2h_ps_cfg_wr_req; logic c2h_ps_cfg_rd_req; logic [15:0] c2h_ps_cfg_addr; logic [31:0] c2h_ps_cfg_wdata; logic c2h_ps_cfg_ack; logic [31:0] c2h_ps_cfg_rdata; - + logic c2h_desc_ooo_error; logic c2h_desc_unalin_error; @@ -205,7 +208,7 @@ module sde #(parameter bit C2H_ONLY = 0, logic [PCIM_LEN_WIDTH-1:0] c2h_dm_pm_awlen; logic [PCIM_ID_WIDTH-1:0] c2h_dm_pm_awid; logic c2h_pm_dm_awready; - + logic c2h_dm_pm_wvalid; logic [PCIM_DATA_WIDTH-1:0] c2h_dm_pm_wdata; logic [(PCIM_DATA_WIDTH>>3)-1:0] c2h_dm_pm_wstrb; @@ -221,7 +224,7 @@ module sde #(parameter bit C2H_ONLY = 0, logic [PCIM_LEN_WIDTH-1:0] c2h_wb_pm_awlen; logic [PCIM_ID_WIDTH-1:0] c2h_wb_pm_awid; logic c2h_pm_wb_awready; - + logic c2h_wb_pm_wvalid; logic [PCIM_DATA_WIDTH-1:0] c2h_wb_pm_wdata; logic [(PCIM_DATA_WIDTH>>3)-1:0] c2h_wb_pm_wstrb; @@ -242,7 +245,7 @@ module sde #(parameter bit C2H_ONLY = 0, logic [PCIM_DATA_WIDTH-1:0] h2c_pm_desc_rdata; logic h2c_pm_desc_rlast; logic h2c_desc_pm_rready; - + logic h2c_dm_pm_arvalid; logic [PCIM_ADDR_WIDTH-1:0] h2c_dm_pm_araddr; logic [PCIM_LEN_WIDTH-1:0] h2c_dm_pm_arlen; @@ -260,7 +263,7 @@ module sde #(parameter bit C2H_ONLY = 0, logic [PCIM_LEN_WIDTH-1:0] h2c_wb_pm_awlen; logic [PCIM_ID_WIDTH-1:0] h2c_wb_pm_awid; logic h2c_pm_wb_awready; - + logic h2c_wb_pm_wvalid; logic [PCIM_DATA_WIDTH-1:0] h2c_wb_pm_wdata; logic [(PCIM_DATA_WIDTH>>3)-1:0] h2c_wb_pm_wstrb; @@ -274,8 +277,8 @@ module sde #(parameter bit C2H_ONLY = 0, // Generate local copy of Reset always @(posedge clk) sync_rst_n <= rst_n; - - // PCIS Interface + + // PCIS Interface sde_ps #(.PCIS_DATA_WIDTH (PCIS_DATA_WIDTH), .PCIS_ID_WIDTH (PCIS_ID_WIDTH), .PCIS_LEN_WIDTH (PCIS_LEN_WIDTH), @@ -326,29 +329,29 @@ module sde #(parameter bit C2H_ONLY = 0, .c2h_ps_desc_wr_req (c2h_ps_desc_wr_req), .c2h_ps_desc_wdata (c2h_ps_desc_wdata ), .c2h_ps_desc_ack (c2h_ps_desc_ack ), - + .h2c_ps_desc_wr_req (h2c_ps_desc_wr_req), .h2c_ps_desc_wdata (h2c_ps_desc_wdata ), .h2c_ps_desc_ack (h2c_ps_desc_ack ), - + .h2c_ps_pkt_wr_req (h2c_ps_pkt_wr_req), .h2c_ps_pkt_wdata (h2c_ps_pkt_wdata ), .h2c_ps_pkt_ack (h2c_ps_pkt_ack ), - + .pm_ps_cfg_wr_req (pm_ps_cfg_wr_req), .pm_ps_cfg_rd_req (pm_ps_cfg_rd_req), .pm_ps_cfg_addr (pm_ps_cfg_addr ), .pm_ps_cfg_wdata (pm_ps_cfg_wdata ), .pm_ps_cfg_ack (pm_ps_cfg_ack ), .pm_ps_cfg_rdata (pm_ps_cfg_rdata ), - + .c2h_ps_cfg_wr_req (c2h_ps_cfg_wr_req), .c2h_ps_cfg_rd_req (c2h_ps_cfg_rd_req), .c2h_ps_cfg_addr (c2h_ps_cfg_addr ), .c2h_ps_cfg_wdata (c2h_ps_cfg_wdata ), .c2h_ps_cfg_ack (c2h_ps_cfg_ack ), .c2h_ps_cfg_rdata (c2h_ps_cfg_rdata ), - + .c2h_desc_ooo_error (c2h_desc_ooo_error), .c2h_desc_unalin_error (c2h_desc_unalin_error), @@ -363,7 +366,7 @@ module sde #(parameter bit C2H_ONLY = 0, .h2c_desc_unalin_error (h2c_desc_unalin_error) ); - + // PCIM Interface sde_pm #(.PCIM_DATA_WIDTH (PCIM_DATA_WIDTH ), .PCIM_ID_WIDTH (PCIM_ID_WIDTH ), @@ -373,7 +376,7 @@ module sde #(parameter bit C2H_ONLY = 0, .C2H_PCIM_DM_AWID (C2H_PCIM_DM_AWID), .C2H_PCIM_WB_AWID (C2H_PCIM_WB_AWID), .H2C_PCIM_WB_AWID (H2C_PCIM_WB_AWID), - + .C2H_PCIM_DESC_ARID(C2H_PCIM_DESC_ARID), .H2C_PCIM_DESC_ARID(H2C_PCIM_DESC_ARID), .H2C_PCIM_DM_ARID (H2C_PCIM_DM_ARID ) @@ -382,14 +385,14 @@ module sde #(parameter bit C2H_ONLY = 0, SDE_PCI_MSTR (.clk (clk), .rst_n (pm_sync_rst_n), - + .pm_ps_cfg_wr_req (pm_ps_cfg_wr_req), .pm_ps_cfg_rd_req (pm_ps_cfg_rd_req), .pm_ps_cfg_addr (pm_ps_cfg_addr ), .pm_ps_cfg_wdata (pm_ps_cfg_wdata ), .pm_ps_cfg_ack (pm_ps_cfg_ack ), .pm_ps_cfg_rdata (pm_ps_cfg_rdata ), - + .pcim_awvalid (pcim_awvalid ), .pcim_awid (pcim_awid ), .pcim_awaddr (pcim_awaddr ), @@ -442,7 +445,7 @@ module sde #(parameter bit C2H_ONLY = 0, .c2h_pm_dm_bresp (c2h_pm_dm_bresp ), .c2h_dm_pm_bready (c2h_dm_pm_bready ), - + .c2h_wb_pm_awvalid (c2h_wb_pm_awvalid), .c2h_wb_pm_awaddr (c2h_wb_pm_awaddr ), .c2h_wb_pm_awlen (c2h_wb_pm_awlen ), @@ -456,7 +459,7 @@ module sde #(parameter bit C2H_ONLY = 0, .c2h_pm_wb_bvalid (c2h_pm_wb_bvalid ), .c2h_pm_wb_bresp (c2h_pm_wb_bresp ), .c2h_wb_pm_bready (c2h_wb_pm_bready ), - + .h2c_desc_pm_arvalid (h2c_desc_pm_arvalid), .h2c_desc_pm_araddr (h2c_desc_pm_araddr ), .h2c_desc_pm_arlen (h2c_desc_pm_arlen ), @@ -466,7 +469,7 @@ module sde #(parameter bit C2H_ONLY = 0, .h2c_pm_desc_rdata (h2c_pm_desc_rdata ), .h2c_pm_desc_rlast (h2c_pm_desc_rlast ), .h2c_desc_pm_rready (h2c_desc_pm_rready), - + .h2c_dm_pm_arvalid (h2c_dm_pm_arvalid), .h2c_dm_pm_araddr (h2c_dm_pm_araddr ), .h2c_dm_pm_arlen (h2c_dm_pm_arlen ), @@ -476,7 +479,7 @@ module sde #(parameter bit C2H_ONLY = 0, .h2c_pm_dm_rdata (h2c_pm_dm_rdata ), .h2c_pm_dm_rlast (h2c_pm_dm_rlast ), .h2c_dm_pm_rready (h2c_dm_pm_rready), - + .h2c_wb_pm_awvalid (h2c_wb_pm_awvalid), .h2c_wb_pm_awaddr (h2c_wb_pm_awaddr ), .h2c_wb_pm_awlen (h2c_wb_pm_awlen ), @@ -492,26 +495,26 @@ module sde #(parameter bit C2H_ONLY = 0, .h2c_wb_pm_bready (h2c_wb_pm_bready ) ); - + // C2H if (H2C_ONLY == 0) begin - sde_c2h + sde_c2h #(.C2H_DESC_TYPE (C2H_DESC_TYPE), .C2H_DESC_WIDTH (C2H_DESC_WIDTH), - + .C2H_DESC_RAM_DEPTH (C2H_DESC_RAM_DEPTH), .C2H_PCIM_DM_AWID (C2H_PCIM_DM_AWID), .C2H_PCIM_WB_AWID (C2H_PCIM_WB_AWID), .C2H_PCIM_DESC_ARID (C2H_PCIM_DESC_ARID), - + .C2H_PCIM_MAX_WR_SIZE (C2H_PCIM_MAX_WR_SIZE), .PCIM_DATA_WIDTH (PCIM_DATA_WIDTH ), .PCIM_ID_WIDTH (PCIM_ID_WIDTH ), .PCIM_LEN_WIDTH (PCIM_LEN_WIDTH ), .PCIM_ADDR_WIDTH (PCIM_ADDR_WIDTH ), - + .C2H_AXIS_DATA_WIDTH (C2H_AXIS_DATA_WIDTH), .C2H_USER_BIT_WIDTH (C2H_USER_BIT_WIDTH), .C2H_BUF_DEPTH (C2H_BUF_DEPTH) @@ -523,14 +526,14 @@ module sde #(parameter bit C2H_ONLY = 0, .c2h_ps_desc_wr_req (c2h_ps_desc_wr_req), .c2h_ps_desc_wdata (c2h_ps_desc_wdata ), .c2h_ps_desc_ack (c2h_ps_desc_ack ), - + .c2h_ps_cfg_wr_req (c2h_ps_cfg_wr_req), .c2h_ps_cfg_rd_req (c2h_ps_cfg_rd_req), .c2h_ps_cfg_addr (c2h_ps_cfg_addr ), .c2h_ps_cfg_wdata (c2h_ps_cfg_wdata ), .c2h_ps_cfg_ack (c2h_ps_cfg_ack ), .c2h_ps_cfg_rdata (c2h_ps_cfg_rdata ), - + .c2h_desc_ooo_error (c2h_desc_ooo_error), .c2h_desc_unalin_error (c2h_desc_unalin_error), @@ -558,7 +561,7 @@ module sde #(parameter bit C2H_ONLY = 0, .c2h_pm_dm_bresp (c2h_pm_dm_bresp ), .c2h_dm_pm_bready (c2h_dm_pm_bready ), - + .c2h_wb_pm_awvalid (c2h_wb_pm_awvalid), .c2h_wb_pm_awaddr (c2h_wb_pm_awaddr ), .c2h_wb_pm_awlen (c2h_wb_pm_awlen ), @@ -574,16 +577,16 @@ module sde #(parameter bit C2H_ONLY = 0, .c2h_wb_pm_bready (c2h_wb_pm_bready ), .c2h_axis_valid (c2h_axis_valid ), - .c2h_axis_data (c2h_axis_data ), - .c2h_axis_keep (c2h_axis_keep ), - .c2h_axis_user (c2h_axis_user ), - .c2h_axis_last (c2h_axis_last ), + .c2h_axis_data (c2h_axis_data ), + .c2h_axis_keep (c2h_axis_keep ), + .c2h_axis_user (c2h_axis_user ), + .c2h_axis_last (c2h_axis_last ), .c2h_axis_ready (c2h_axis_ready ) ); end // if (H2C_ONLY == 0) else begin - assign + assign c2h_ps_desc_ack = 1'b1, c2h_ps_cfg_ack = 1'b1, c2h_ps_cfg_rdata = 32'd00, @@ -594,10 +597,10 @@ module sde #(parameter bit C2H_ONLY = 0, c2h_dm_pm_bready = 1'b1, c2h_axis_ready = 1'b0; end // else: !if(H2C_ONLY == 0) - + // H2C if (C2H_ONLY == 0) begin - sde_h2c + sde_h2c #(.H2C_DESC_TYPE (H2C_DESC_TYPE), .H2C_DESC_RAM_DEPTH (H2C_DESC_RAM_DEPTH), .H2C_PCIM_DM_ARID (H2C_PCIM_DM_ARID), @@ -606,12 +609,12 @@ module sde #(parameter bit C2H_ONLY = 0, .PCIM_NUM_OT_RD (PCIM_NUM_OT_RD ), .H2C_PCIM_MAX_RD_SIZE (H2C_PCIM_MAX_RD_SIZE), - + .PCIM_DATA_WIDTH (PCIM_DATA_WIDTH ), .PCIM_ID_WIDTH (PCIM_ID_WIDTH ), .PCIM_LEN_WIDTH (PCIM_LEN_WIDTH ), .PCIM_ADDR_WIDTH (PCIM_ADDR_WIDTH ), - + .H2C_AXIS_DATA_WIDTH (H2C_AXIS_DATA_WIDTH), .H2C_USER_BIT_WIDTH (H2C_USER_BIT_WIDTH), .H2C_BUF_DEPTH (H2C_BUF_DEPTH) @@ -623,14 +626,14 @@ module sde #(parameter bit C2H_ONLY = 0, .h2c_ps_desc_wr_req (h2c_ps_desc_wr_req), .h2c_ps_desc_wdata (h2c_ps_desc_wdata ), .h2c_ps_desc_ack (h2c_ps_desc_ack ), - + .h2c_ps_cfg_wr_req (h2c_ps_cfg_wr_req), .h2c_ps_cfg_rd_req (h2c_ps_cfg_rd_req), .h2c_ps_cfg_addr (h2c_ps_cfg_addr ), .h2c_ps_cfg_wdata (h2c_ps_cfg_wdata ), .h2c_ps_cfg_ack (h2c_ps_cfg_ack ), .h2c_ps_cfg_rdata (h2c_ps_cfg_rdata ), - + .h2c_desc_ooo_error (h2c_desc_ooo_error), .h2c_desc_unalin_error (h2c_desc_unalin_error), @@ -654,7 +657,7 @@ module sde #(parameter bit C2H_ONLY = 0, .h2c_pm_dm_rdata (h2c_pm_dm_rdata ), .h2c_pm_dm_rlast (h2c_pm_dm_rlast ), .h2c_dm_pm_rready (h2c_dm_pm_rready ), - + .h2c_wb_pm_awvalid (h2c_wb_pm_awvalid), .h2c_wb_pm_awaddr (h2c_wb_pm_awaddr ), .h2c_wb_pm_awlen (h2c_wb_pm_awlen ), @@ -670,16 +673,16 @@ module sde #(parameter bit C2H_ONLY = 0, .h2c_wb_pm_bready (h2c_wb_pm_bready ), .h2c_axis_valid (h2c_axis_valid), - .h2c_axis_data (h2c_axis_data ), - .h2c_axis_keep (h2c_axis_keep ), - .h2c_axis_user (h2c_axis_user ), - .h2c_axis_last (h2c_axis_last ), + .h2c_axis_data (h2c_axis_data ), + .h2c_axis_keep (h2c_axis_keep ), + .h2c_axis_user (h2c_axis_user ), + .h2c_axis_last (h2c_axis_last ), .h2c_axis_ready (h2c_axis_ready) ); end // if (C2H_ONLY == 0) else begin - assign + assign h2c_ps_desc_ack = 1'b1, h2c_ps_cfg_ack = 1'b1, h2c_ps_cfg_rdata = 32'd0, @@ -689,7 +692,7 @@ module sde #(parameter bit C2H_ONLY = 0, h2c_dm_pm_rready = 1'b1, h2c_axis_valid = 1'b0; end // else: !if(C2H_ONLY == 0) - + `ifndef NO_SDE_DEBUG_ILA // ila_axi4_wrapper #(.AXI_DATA_WIDTH(32)) PCIS_AXI4_ILA @@ -723,7 +726,7 @@ module sde #(parameter bit C2H_ONLY = 0, // .ila_rresp (pcis_rresp ), // .ila_rlast (pcis_rlast ) // ); -// +// // ila_axi4_wrapper #(.AXI_DATA_WIDTH(32)) PCIM_AXI4_ILA // (.aclk (clk), // .trig_disable (1'b0), @@ -754,7 +757,7 @@ module sde #(parameter bit C2H_ONLY = 0, // .ila_rdata (pcim_rdata ), // .ila_rresp (pcim_rresp ), // .ila_rlast (pcim_rlast ) -// ); +// ); ila_axis C2H_AXIS_ILA (.clk (clk), @@ -765,7 +768,7 @@ module sde #(parameter bit C2H_ONLY = 0, .probe4 (c2h_axis_user), .probe5 (c2h_axis_ready) ); - + ila_axis H2C_AXIS_ILA (.clk (clk), .probe0 (h2c_axis_valid), @@ -775,13 +778,9 @@ module sde #(parameter bit C2H_ONLY = 0, .probe4 (h2c_axis_user), .probe5 (h2c_axis_ready) ); - + `endif // `ifndef NO_SDE_DEBUG_ILA - - - -endmodule // sde - - + +endmodule // sde diff --git a/hdk/cl/examples/cl_sde/design/sde_c2h.sv b/hdk/cl/examples/cl_sde/design/sde_c2h.sv index 017d5478f..393683f57 100644 --- a/hdk/cl/examples/cl_sde/design/sde_c2h.sv +++ b/hdk/cl/examples/cl_sde/design/sde_c2h.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016-2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,15 +13,16 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ // C2H Top level module sde_c2h #(parameter bit C2H_DESC_TYPE = 0, // 0 - Regular, 1 - Compact parameter C2H_DESC_WIDTH = 128, - + parameter C2H_DESC_RAM_DEPTH = 64, - + parameter C2H_PCIM_DM_AWID = 0, // This is the AWID used for write accesses from Data Mover parameter C2H_PCIM_WB_AWID = 1, // This is the AWID used for write accesses from Write Back Block parameter C2H_PCIM_DESC_ARID = 2, // This is the ARID used for read access from the C2H Desc Block @@ -34,7 +36,7 @@ module sde_c2h #(parameter bit C2H_DESC_TYPE = 0, // 0 - Regular, 1 - Compact parameter C2H_AXIS_DATA_WIDTH = 512, parameter C2H_USER_BIT_WIDTH = C2H_DESC_TYPE ? 1 : 64, - + parameter C2H_BUF_DEPTH = 512 ) @@ -48,7 +50,7 @@ module sde_c2h #(parameter bit C2H_DESC_TYPE = 0, // 0 - Regular, 1 - Compact input c2h_ps_desc_wr_req, input [C2H_DESC_WIDTH-1:0] c2h_ps_desc_wdata, output logic c2h_ps_desc_ack, - + // PCIS to C2H CSR input c2h_ps_cfg_wr_req, input c2h_ps_cfg_rd_req, @@ -81,7 +83,7 @@ module sde_c2h #(parameter bit C2H_DESC_TYPE = 0, // 0 - Regular, 1 - Compact output logic [PCIM_LEN_WIDTH-1:0] c2h_dm_pm_awlen, output logic [PCIM_ID_WIDTH-1:0] c2h_dm_pm_awid, input c2h_pm_dm_awready, - + // Write Data to PCIM output logic c2h_dm_pm_wvalid, output logic [PCIM_DATA_WIDTH-1:0] c2h_dm_pm_wdata, @@ -101,7 +103,7 @@ module sde_c2h #(parameter bit C2H_DESC_TYPE = 0, // 0 - Regular, 1 - Compact output logic [PCIM_LEN_WIDTH-1:0] c2h_wb_pm_awlen, output logic [PCIM_ID_WIDTH-1:0] c2h_wb_pm_awid, input c2h_pm_wb_awready, - + // Write Data to PCIM output logic c2h_wb_pm_wvalid, output logic [PCIM_DATA_WIDTH-1:0] c2h_wb_pm_wdata, @@ -120,7 +122,7 @@ module sde_c2h #(parameter bit C2H_DESC_TYPE = 0, // 0 - Regular, 1 - Compact input [(C2H_AXIS_DATA_WIDTH>>3)-1:0] c2h_axis_keep, input [C2H_USER_BIT_WIDTH-1:0] c2h_axis_user, input c2h_axis_last, - output logic c2h_axis_ready + output logic c2h_axis_ready ); @@ -128,7 +130,7 @@ module sde_c2h #(parameter bit C2H_DESC_TYPE = 0, // 0 - Regular, 1 - Compact localparam BUF_ADDR_RAM_IDX_WIDTH = $clog2(C2H_BUF_DEPTH); localparam BUF_ADDR_WIDTH = PCIM_ADDR_BYTE_IDX_WIDTH + BUF_ADDR_RAM_IDX_WIDTH; localparam BUF_AUX_WIDTH = BUF_ADDR_WIDTH + C2H_USER_BIT_WIDTH; - + // Signals logic desc_dm_empty; @@ -137,7 +139,7 @@ module sde_c2h #(parameter bit C2H_DESC_TYPE = 0, // 0 - Regular, 1 - Compact logic desc_dm_desc_valid; logic dm_desc_cnt_inc; - + // Descriptor to Write Back Block logic desc_wb_limit_req; logic [31:0] desc_wb_limit; @@ -147,16 +149,16 @@ module sde_c2h #(parameter bit C2H_DESC_TYPE = 0, // 0 - Regular, 1 - Compact logic dm_wb_md_req; sde_pkg::c2h_reg_wb_t dm_wb_md; logic wb_dm_md_grant; - - // Data Mover to Buffer + + // Data Mover to Buffer logic buf_dm_aux_valid; logic [BUF_AUX_WIDTH-1:0] buf_dm_aux_data; logic dm_buf_aux_pop; - + logic [BUF_ADDR_WIDTH-1:0] dm_buf_rd_byte_addr; logic [BUF_ADDR_WIDTH:0] buf_dm_num_bytes; // Difference in pointers + plus num of bytes in last beat - + logic dm_buf_rd; logic [BUF_ADDR_RAM_IDX_WIDTH-1:0] dm_buf_addr; logic [PCIM_DATA_WIDTH-1:0] buf_dm_data; @@ -167,7 +169,7 @@ module sde_c2h #(parameter bit C2H_DESC_TYPE = 0, // 0 - Regular, 1 - Compact logic [C2H_USER_BIT_WIDTH-1:0] axis_buf_user; logic axis_buf_last; logic buf_axis_ready; - + logic axis_wb_pkt_cnt_req; logic [31:0] axis_wb_pkt_cnt; @@ -188,10 +190,10 @@ module sde_c2h #(parameter bit C2H_DESC_TYPE = 0, // 0 - Regular, 1 - Compact logic [C2H_DESC_WIDTH-1:0] cfg_desc_ram_wdata ; logic desc_cfg_ram_ack ; logic [C2H_DESC_WIDTH-1:0] desc_cfg_ram_rdata ; - + logic dm_cfg_bresp_err; logic dm_cfg_desc_len_err; - + logic cfg_wb_desc_cdt_en; logic cfg_wb_desc_cnt_en; logic cfg_wb_pkt_cnt_en; @@ -202,12 +204,12 @@ module sde_c2h #(parameter bit C2H_DESC_TYPE = 0, // 0 - Regular, 1 - Compact logic [15:0] cfg_wb_md_rd_ptr; logic [15:0] wb_cfg_md_wr_ptr; logic cfg_wb_clr_wr_ptr; - - logic cfg_wb_desc_error; - logic cfg_wb_dm_error ; + + logic cfg_wb_desc_error; + logic cfg_wb_dm_error ; logic cfg_wb_wb_error ; logic [31:0] wb_cfg_status_dw ; - + logic cfg_desc_cdt_wc_en; logic cfg_desc_cnt_wc_en; logic cfg_pkt_cnt_wc_en; @@ -215,10 +217,10 @@ module sde_c2h #(parameter bit C2H_DESC_TYPE = 0, // 0 - Regular, 1 - Compact logic [19:0] cfg_wc_tick_cnt; logic [3:0] cfg_wc_to_cnt; logic [5:0] cfg_wc_cnt_minus1; - + logic cfg_axis_clr_pkt_cnt; logic [31:0] axis_cfg_pkt_cnt; - + logic dm_num_beats_err; logic desc_cfg_oflow; @@ -228,7 +230,7 @@ module sde_c2h #(parameter bit C2H_DESC_TYPE = 0, // 0 - Regular, 1 - Compact logic wb_cfg_md_bresp_err ; logic wb_cfg_sts_bresp_err; - + logic buf_cfg_buf_oflow; logic buf_cfg_buf_uflow; logic buf_cfg_buf_full; @@ -237,24 +239,24 @@ module sde_c2h #(parameter bit C2H_DESC_TYPE = 0, // 0 - Regular, 1 - Compact logic [15:0] buf_cfg_buf_rd_addr; logic buf_cfg_aux_fifo_oflow; logic buf_cfg_aux_fifo_uflow; - logic buf_cfg_aux_fifo_full ; + logic buf_cfg_aux_fifo_full ; logic buf_cfg_aux_fifo_empty; logic [15:0] buf_cfg_aux_ram_wr_ptr; - logic [15:0] buf_cfg_aux_ram_rd_ptr; + logic [15:0] buf_cfg_aux_ram_rd_ptr; logic [15:0] buf_cfg_num_bytes; logic [31:0] buf_cfg_in_pkt_cnt; logic [31:0] buf_cfg_out_pkt_cnt; logic cfg_buf_clr_in_pkt_cnt; logic cfg_buf_clr_out_pkt_cnt; - + // Generate local copy of Reset logic sync_rst_n; always @(posedge clk) - if (!rst_n) + if (!rst_n) sync_rst_n <= 0; else sync_rst_n <= rst_n; - + // C2H CSR Block sde_c2h_cfg #( .DESC_TYPE (C2H_DESC_TYPE), @@ -264,7 +266,7 @@ module sde_c2h #(parameter bit C2H_DESC_TYPE = 0, // 0 - Regular, 1 - Compact SDE_C2H_CFG (.clk (clk), .rst_n (sync_rst_n), - + .c2h_ps_cfg_wr_req (c2h_ps_cfg_wr_req), .c2h_ps_cfg_rd_req (c2h_ps_cfg_rd_req), .c2h_ps_cfg_addr (c2h_ps_cfg_addr ), @@ -278,20 +280,20 @@ module sde_c2h #(parameter bit C2H_DESC_TYPE = 0, // 0 - Regular, 1 - Compact .cfg_desc_clr_desc_cnt (cfg_desc_clr_desc_cnt ), .cfg_desc_clr_cdt_limit (cfg_desc_clr_cdt_limit ), .cfg_desc_clr_cdt_consumed (cfg_desc_clr_cdt_consumed), - + .desc_cfg_cdt_consumed (desc_cfg_cdt_consumed), .desc_cfg_cdt_limit (desc_cfg_cdt_limit ), .desc_cfg_desc_cnt (desc_cfg_desc_cnt ), .desc_cfg_wr_ptr (desc_cfg_wr_ptr ), .desc_cfg_rd_ptr (desc_cfg_rd_ptr ), - + .cfg_desc_ram_wr_req (cfg_desc_ram_wr_req), .cfg_desc_ram_rd_req (cfg_desc_ram_rd_req), .cfg_desc_ram_addr (cfg_desc_ram_addr ), .cfg_desc_ram_wdata (cfg_desc_ram_wdata ), .desc_cfg_ram_ack (desc_cfg_ram_ack ), .desc_cfg_ram_rdata (desc_cfg_ram_rdata ), - + .desc_cfg_oflow (desc_cfg_oflow), .desc_cfg_uflow (desc_cfg_uflow), .desc_cfg_full (desc_cfg_full ), @@ -310,7 +312,7 @@ module sde_c2h #(parameter bit C2H_DESC_TYPE = 0, // 0 - Regular, 1 - Compact .cfg_wb_md_rd_ptr (cfg_wb_md_rd_ptr ), .wb_cfg_md_wr_ptr (wb_cfg_md_wr_ptr ), .cfg_wb_clr_wr_ptr (cfg_wb_clr_wr_ptr ), - + .cfg_desc_cdt_wc_en (cfg_desc_cdt_wc_en ), .cfg_desc_cnt_wc_en (cfg_desc_cnt_wc_en ), .cfg_pkt_cnt_wc_en (cfg_pkt_cnt_wc_en ), @@ -320,13 +322,13 @@ module sde_c2h #(parameter bit C2H_DESC_TYPE = 0, // 0 - Regular, 1 - Compact .cfg_wc_cnt_minus1 (cfg_wc_cnt_minus1 ), .wb_cfg_md_bresp_err (wb_cfg_md_bresp_err), - .wb_cfg_sts_bresp_err (wb_cfg_sts_bresp_err), + .wb_cfg_sts_bresp_err (wb_cfg_sts_bresp_err), - .cfg_wb_desc_error (cfg_wb_desc_error), - .cfg_wb_dm_error (cfg_wb_dm_error ), + .cfg_wb_desc_error (cfg_wb_desc_error), + .cfg_wb_dm_error (cfg_wb_dm_error ), .cfg_wb_wb_error (cfg_wb_wb_error ), .wb_cfg_status_dw (wb_cfg_status_dw ), - + .buf_cfg_buf_oflow (buf_cfg_buf_oflow ), .buf_cfg_buf_uflow (buf_cfg_buf_uflow ), .buf_cfg_buf_full (buf_cfg_buf_full ), @@ -335,56 +337,56 @@ module sde_c2h #(parameter bit C2H_DESC_TYPE = 0, // 0 - Regular, 1 - Compact .buf_cfg_buf_rd_addr (buf_cfg_buf_rd_addr ), .buf_cfg_aux_fifo_oflow (buf_cfg_aux_fifo_oflow ), .buf_cfg_aux_fifo_uflow (buf_cfg_aux_fifo_uflow ), - .buf_cfg_aux_fifo_full (buf_cfg_aux_fifo_full ), + .buf_cfg_aux_fifo_full (buf_cfg_aux_fifo_full ), .buf_cfg_aux_fifo_empty (buf_cfg_aux_fifo_empty ), .buf_cfg_aux_ram_wr_ptr (buf_cfg_aux_ram_wr_ptr ), - .buf_cfg_aux_ram_rd_ptr (buf_cfg_aux_ram_rd_ptr ), + .buf_cfg_aux_ram_rd_ptr (buf_cfg_aux_ram_rd_ptr ), .buf_cfg_num_bytes (buf_cfg_num_bytes ), .buf_cfg_in_pkt_cnt (buf_cfg_in_pkt_cnt ), .buf_cfg_out_pkt_cnt (buf_cfg_out_pkt_cnt ), .cfg_buf_clr_in_pkt_cnt (cfg_buf_clr_in_pkt_cnt ), .cfg_buf_clr_out_pkt_cnt (cfg_buf_clr_out_pkt_cnt), - + .cfg_axis_clr_pkt_cnt (cfg_axis_clr_pkt_cnt), .axis_cfg_pkt_cnt (axis_cfg_pkt_cnt ) ); - + // C2H Descriptor - sde_desc + sde_desc #(.H2C_N_C2H (0), - + .DESC_TYPE (C2H_DESC_TYPE), - .DESC_WIDTH (C2H_DESC_WIDTH), + .DESC_WIDTH (C2H_DESC_WIDTH), .DESC_RAM_DEPTH (C2H_DESC_RAM_DEPTH), - + .PCIM_DATA_WIDTH (PCIM_DATA_WIDTH ), .PCIM_ID_WIDTH (PCIM_ID_WIDTH ), .PCIM_LEN_WIDTH (PCIM_LEN_WIDTH ), .PCIM_ADDR_WIDTH (PCIM_ADDR_WIDTH ), .PCIM_DESC_ARID (C2H_PCIM_DESC_ARID) - ) - SDE_C2H_DESC + ) + SDE_C2H_DESC (.clk (clk), .rst_n (sync_rst_n), - + .ps_desc_wr_req (c2h_ps_desc_wr_req), .ps_desc_wdata (c2h_ps_desc_wdata), .ps_desc_ack (c2h_ps_desc_ack), - + .cfg_desc_ram_wr_req (cfg_desc_ram_wr_req), .cfg_desc_ram_rd_req (cfg_desc_ram_rd_req), .cfg_desc_ram_addr (cfg_desc_ram_addr ), .cfg_desc_ram_wdata (cfg_desc_ram_wdata ), .desc_cfg_ram_ack (desc_cfg_ram_ack ), .desc_cfg_ram_rdata (desc_cfg_ram_rdata ), - + .cfg_desc_clr_desc_cnt (cfg_desc_clr_desc_cnt ), .cfg_desc_clr_cdt_limit (cfg_desc_clr_cdt_limit ), .cfg_desc_clr_cdt_consumed (cfg_desc_clr_cdt_consumed), - + .desc_cfg_cdt_consumed (desc_cfg_cdt_consumed), .desc_cfg_cdt_limit (desc_cfg_cdt_limit ), .desc_cfg_desc_cnt (desc_cfg_desc_cnt ), @@ -402,8 +404,8 @@ module sde_c2h #(parameter bit C2H_DESC_TYPE = 0, // 0 - Regular, 1 - Compact .desc_dm_desc_valid (desc_dm_desc_valid), .dm_desc_cnt_inc (dm_desc_cnt_inc), - - .desc_wb_limit_req (desc_wb_limit_req), + + .desc_wb_limit_req (desc_wb_limit_req), .desc_wb_limit (desc_wb_limit), .desc_wb_cnt_req (desc_wb_cnt_req), .desc_wb_cnt (desc_wb_cnt), @@ -412,7 +414,7 @@ module sde_c2h #(parameter bit C2H_DESC_TYPE = 0, // 0 - Regular, 1 - Compact .desc_pm_araddr (c2h_desc_pm_araddr ), .desc_pm_arlen (c2h_desc_pm_arlen ), .pm_desc_arready (c2h_pm_desc_arready), - + .pm_desc_rvalid (c2h_pm_desc_rvalid), .pm_desc_rresp (c2h_pm_desc_rresp ), .pm_desc_rdata (c2h_pm_desc_rdata ), @@ -420,25 +422,25 @@ module sde_c2h #(parameter bit C2H_DESC_TYPE = 0, // 0 - Regular, 1 - Compact .desc_pm_rready (c2h_desc_pm_rready) ); - + // C2H Data Mover - sde_c2h_data + sde_c2h_data #(.DESC_TYPE (C2H_DESC_TYPE), - + .PCIM_DM_AWID (C2H_PCIM_DM_AWID), - + .PCIM_MAX_WR_SIZE (C2H_PCIM_MAX_WR_SIZE), - + .PCIM_DATA_WIDTH (PCIM_DATA_WIDTH ), .PCIM_ID_WIDTH (PCIM_ID_WIDTH ), .PCIM_LEN_WIDTH (PCIM_LEN_WIDTH ), .PCIM_ADDR_WIDTH (PCIM_ADDR_WIDTH ), - + .BUF_DEPTH (C2H_BUF_DEPTH), - + .USER_BIT_WIDTH (C2H_USER_BIT_WIDTH) ) - SDE_C2H_DATA + SDE_C2H_DATA (.clk (clk), .rst_n (sync_rst_n), @@ -446,14 +448,14 @@ module sde_c2h #(parameter bit C2H_DESC_TYPE = 0, // 0 - Regular, 1 - Compact .dm_cfg_bresp_err (dm_cfg_bresp_err), .dm_cfg_desc_len_err (dm_cfg_desc_len_err), .dm_num_beats_err (dm_num_beats_err), - + .desc_dm_empty (desc_dm_empty), .dm_desc_pop (dm_desc_pop), .desc_dm_desc (desc_dm_desc), .desc_dm_desc_valid (desc_dm_desc_valid), .dm_desc_cnt_inc (dm_desc_cnt_inc), - + .dm_pm_awvalid (c2h_dm_pm_awvalid), .dm_pm_awaddr (c2h_dm_pm_awaddr ), .dm_pm_awlen (c2h_dm_pm_awlen ), @@ -483,7 +485,7 @@ module sde_c2h #(parameter bit C2H_DESC_TYPE = 0, // 0 - Regular, 1 - Compact .dm_buf_addr (dm_buf_addr), .buf_dm_data (buf_dm_data) ); - + // C2H Write-Back sde_wb #(.H2C_N_C2H (0), @@ -491,7 +493,7 @@ module sde_c2h #(parameter bit C2H_DESC_TYPE = 0, // 0 - Regular, 1 - Compact .DESC_RAM_DEPTH (C2H_DESC_RAM_DEPTH), .PCIM_WB_AWID (C2H_PCIM_WB_AWID), - + .PCIM_DATA_WIDTH (PCIM_DATA_WIDTH ), .PCIM_ID_WIDTH (PCIM_ID_WIDTH ), .PCIM_LEN_WIDTH (PCIM_LEN_WIDTH ), @@ -511,7 +513,7 @@ module sde_c2h #(parameter bit C2H_DESC_TYPE = 0, // 0 - Regular, 1 - Compact .cfg_wb_md_rd_ptr (cfg_wb_md_rd_ptr ), .wb_cfg_md_wr_ptr (wb_cfg_md_wr_ptr ), .cfg_wb_clr_wr_ptr (cfg_wb_clr_wr_ptr ), - + .cfg_desc_cdt_wc_en (cfg_desc_cdt_wc_en ), .cfg_desc_cnt_wc_en (cfg_desc_cnt_wc_en ), .cfg_pkt_cnt_wc_en (cfg_pkt_cnt_wc_en ), @@ -519,20 +521,20 @@ module sde_c2h #(parameter bit C2H_DESC_TYPE = 0, // 0 - Regular, 1 - Compact .cfg_wc_tick_cnt (cfg_wc_tick_cnt ), .cfg_wc_to_cnt (cfg_wc_to_cnt ), .cfg_wc_cnt_minus1 (cfg_wc_cnt_minus1 ), - - .cfg_wb_desc_error (cfg_wb_desc_error), - .cfg_wb_dm_error (cfg_wb_dm_error ), + + .cfg_wb_desc_error (cfg_wb_desc_error), + .cfg_wb_dm_error (cfg_wb_dm_error ), .cfg_wb_wb_error (cfg_wb_wb_error ), .wb_cfg_status_dw (wb_cfg_status_dw ), .wb_cfg_md_bresp_err (wb_cfg_md_bresp_err), - .wb_cfg_sts_bresp_err (wb_cfg_sts_bresp_err), + .wb_cfg_sts_bresp_err (wb_cfg_sts_bresp_err), .cfg_desc_clr_desc_cnt (cfg_desc_clr_desc_cnt ), .cfg_desc_clr_cdt_limit (cfg_desc_clr_cdt_limit), .cfg_axis_clr_pkt_cnt (cfg_axis_clr_pkt_cnt), - - .desc_wb_limit_req (desc_wb_limit_req), + + .desc_wb_limit_req (desc_wb_limit_req), .desc_wb_limit (desc_wb_limit), .desc_wb_cnt_req (desc_wb_cnt_req), @@ -544,7 +546,7 @@ module sde_c2h #(parameter bit C2H_DESC_TYPE = 0, // 0 - Regular, 1 - Compact .axis_wb_pkt_cnt_req (axis_wb_pkt_cnt_req), .axis_wb_pkt_cnt (axis_wb_pkt_cnt), - + .wb_pm_awvalid (c2h_wb_pm_awvalid), .wb_pm_awaddr (c2h_wb_pm_awaddr ), .wb_pm_awlen (c2h_wb_pm_awlen ), @@ -560,13 +562,13 @@ module sde_c2h #(parameter bit C2H_DESC_TYPE = 0, // 0 - Regular, 1 - Compact .wb_pm_bready (c2h_wb_pm_bready ) ); - + // C2H Buffer sde_c2h_buf #(.DESC_TYPE (C2H_DESC_TYPE), .PCIM_DATA_WIDTH (PCIM_DATA_WIDTH ), - + .BUF_DEPTH (C2H_BUF_DEPTH), .USER_BIT_WIDTH (C2H_USER_BIT_WIDTH) @@ -584,21 +586,21 @@ module sde_c2h #(parameter bit C2H_DESC_TYPE = 0, // 0 - Regular, 1 - Compact .buf_cfg_buf_rd_addr (buf_cfg_buf_rd_addr ), .buf_cfg_aux_fifo_oflow (buf_cfg_aux_fifo_oflow ), .buf_cfg_aux_fifo_uflow (buf_cfg_aux_fifo_uflow ), - .buf_cfg_aux_fifo_full (buf_cfg_aux_fifo_full ), + .buf_cfg_aux_fifo_full (buf_cfg_aux_fifo_full ), .buf_cfg_aux_fifo_empty (buf_cfg_aux_fifo_empty ), .buf_cfg_aux_ram_wr_ptr (buf_cfg_aux_ram_wr_ptr ), - .buf_cfg_aux_ram_rd_ptr (buf_cfg_aux_ram_rd_ptr ), + .buf_cfg_aux_ram_rd_ptr (buf_cfg_aux_ram_rd_ptr ), .buf_cfg_num_bytes (buf_cfg_num_bytes ), .buf_cfg_in_pkt_cnt (buf_cfg_in_pkt_cnt ), .buf_cfg_out_pkt_cnt (buf_cfg_out_pkt_cnt ), .cfg_buf_clr_in_pkt_cnt (cfg_buf_clr_in_pkt_cnt ), .cfg_buf_clr_out_pkt_cnt (cfg_buf_clr_out_pkt_cnt), - - .axis_buf_valid (axis_buf_valid ), - .axis_buf_data (axis_buf_data ), - .axis_buf_keep (axis_buf_keep ), - .axis_buf_user (axis_buf_user ), - .axis_buf_last (axis_buf_last ), + + .axis_buf_valid (axis_buf_valid ), + .axis_buf_data (axis_buf_data ), + .axis_buf_keep (axis_buf_keep ), + .axis_buf_user (axis_buf_user ), + .axis_buf_last (axis_buf_last ), .buf_axis_ready (buf_axis_ready ), .buf_dm_aux_valid (buf_dm_aux_valid), @@ -612,7 +614,7 @@ module sde_c2h #(parameter bit C2H_DESC_TYPE = 0, // 0 - Regular, 1 - Compact .dm_buf_addr (dm_buf_addr), .buf_dm_data (buf_dm_data) ); - + // C2H AXI-Stream Interface sde_c2h_axis #(.DESC_TYPE (C2H_DESC_TYPE), @@ -625,34 +627,28 @@ module sde_c2h #(parameter bit C2H_DESC_TYPE = 0, // 0 - Regular, 1 - Compact SDE_C2H_AXIS (.clk (clk), .rst_n (sync_rst_n), - + .cfg_axis_clr_pkt_cnt (cfg_axis_clr_pkt_cnt), .axis_cfg_pkt_cnt (axis_cfg_pkt_cnt), - + .c2h_axis_valid (c2h_axis_valid ), - .c2h_axis_data (c2h_axis_data ), - .c2h_axis_keep (c2h_axis_keep ), - .c2h_axis_user (c2h_axis_user ), - .c2h_axis_last (c2h_axis_last ), + .c2h_axis_data (c2h_axis_data ), + .c2h_axis_keep (c2h_axis_keep ), + .c2h_axis_user (c2h_axis_user ), + .c2h_axis_last (c2h_axis_last ), .c2h_axis_ready (c2h_axis_ready ), - - .axis_buf_valid (axis_buf_valid ), - .axis_buf_data (axis_buf_data ), - .axis_buf_keep (axis_buf_keep ), - .axis_buf_user (axis_buf_user ), - .axis_buf_last (axis_buf_last ), + + .axis_buf_valid (axis_buf_valid ), + .axis_buf_data (axis_buf_data ), + .axis_buf_keep (axis_buf_keep ), + .axis_buf_user (axis_buf_user ), + .axis_buf_last (axis_buf_last ), .buf_axis_ready (buf_axis_ready ), .axis_wb_pkt_cnt_req (axis_wb_pkt_cnt_req), .axis_wb_pkt_cnt (axis_wb_pkt_cnt) - - ); - - -endmodule // sde_c2h - + ); - - +endmodule // sde_c2h diff --git a/hdk/cl/examples/cl_sde/design/sde_c2h_axis.sv b/hdk/cl/examples/cl_sde/design/sde_c2h_axis.sv index 415a5f976..1b57dfdf2 100644 --- a/hdk/cl/examples/cl_sde/design/sde_c2h_axis.sv +++ b/hdk/cl/examples/cl_sde/design/sde_c2h_axis.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016-2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + // C2H AXI-Stream Interface @@ -20,7 +23,7 @@ module sde_c2h_axis #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact parameter PCIM_DATA_WIDTH = 512, parameter AXIS_DATA_WIDTH = 512, - + parameter USER_BIT_WIDTH = DESC_TYPE ? 1 : 64 ) @@ -31,7 +34,7 @@ module sde_c2h_axis #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact // CSR to AXI-S Interface input cfg_axis_clr_pkt_cnt, output logic [31:0] axis_cfg_pkt_cnt, - + // AXI-S Interface to CL input c2h_axis_valid, input [AXIS_DATA_WIDTH-1:0] c2h_axis_data, @@ -39,7 +42,7 @@ module sde_c2h_axis #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact input [USER_BIT_WIDTH-1:0] c2h_axis_user, input c2h_axis_last, output logic c2h_axis_ready, - + // AXI-S Interface to Buf output logic axis_buf_valid, output logic [PCIM_DATA_WIDTH-1:0] axis_buf_data, @@ -51,7 +54,7 @@ module sde_c2h_axis #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact // AXI-S Interface to Write Back block for packet Count Update output logic axis_wb_pkt_cnt_req, output logic [31:0] axis_wb_pkt_cnt - + ); @@ -69,7 +72,7 @@ module sde_c2h_axis #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact assign c2h_axis_ready = buf_axis_ready; logic [31:0] axis_pkt_cnt; - + always @(posedge clk) if (!rst_n) begin axis_wb_pkt_cnt_req <= 0; @@ -77,7 +80,7 @@ module sde_c2h_axis #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact end else begin axis_wb_pkt_cnt_req <= c2h_axis_valid & c2h_axis_ready & c2h_axis_last; - axis_pkt_cnt <= cfg_axis_clr_pkt_cnt ? 0 : + axis_pkt_cnt <= cfg_axis_clr_pkt_cnt ? 0 : c2h_axis_valid & c2h_axis_ready & c2h_axis_last ? axis_pkt_cnt + 1 : axis_pkt_cnt; end @@ -86,9 +89,3 @@ module sde_c2h_axis #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact assign axis_cfg_pkt_cnt = axis_pkt_cnt; endmodule // sde_c2h_axis - - - - - - diff --git a/hdk/cl/examples/cl_sde/design/sde_c2h_buf.sv b/hdk/cl/examples/cl_sde/design/sde_c2h_buf.sv index e01c616d0..2fd56d1ce 100644 --- a/hdk/cl/examples/cl_sde/design/sde_c2h_buf.sv +++ b/hdk/cl/examples/cl_sde/design/sde_c2h_buf.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016-2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,11 +13,13 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + // C2H Buffer module sde_c2h_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact - + parameter PCIM_DATA_WIDTH = 512, parameter PCIM_ADDR_BYTE_IDX_WIDTH = $clog2(PCIM_DATA_WIDTH>>3), @@ -26,7 +29,7 @@ module sde_c2h_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact parameter USER_BIT_WIDTH = DESC_TYPE ? 1 : 64, parameter BUF_AUX_WIDTH = BUF_ADDR_WIDTH + USER_BIT_WIDTH, - + // These are internal FIFOs - Dont change unless absolutely required parameter BUF_AUX_FT_FIFO_DEPTH = 64 ) @@ -44,16 +47,16 @@ module sde_c2h_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact output logic [15:0] buf_cfg_buf_rd_addr, output logic buf_cfg_aux_fifo_oflow, output logic buf_cfg_aux_fifo_uflow, - output logic buf_cfg_aux_fifo_full , + output logic buf_cfg_aux_fifo_full , output logic buf_cfg_aux_fifo_empty, output logic [15:0] buf_cfg_aux_ram_wr_ptr, - output logic [15:0] buf_cfg_aux_ram_rd_ptr, + output logic [15:0] buf_cfg_aux_ram_rd_ptr, output logic [15:0] buf_cfg_num_bytes, output logic [31:0] buf_cfg_in_pkt_cnt, output logic [31:0] buf_cfg_out_pkt_cnt, input cfg_buf_clr_in_pkt_cnt, input cfg_buf_clr_out_pkt_cnt, - + // AXI-S Interface to Buf input axis_buf_valid, input [PCIM_DATA_WIDTH-1:0] axis_buf_data, @@ -61,17 +64,17 @@ module sde_c2h_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact input [USER_BIT_WIDTH-1:0] axis_buf_user, input axis_buf_last, output logic buf_axis_ready, - - + + // Buf to Data Mover output logic buf_dm_aux_valid, output logic [BUF_AUX_WIDTH-1:0] buf_dm_aux_data, input dm_buf_aux_pop, - + input [BUF_ADDR_WIDTH-1:0] dm_buf_rd_byte_addr, output logic [BUF_ADDR_WIDTH:0] buf_dm_num_bytes, // Difference in pointers + plus num of bytes in last beat - + input dm_buf_rd, input [BUF_ADDR_RAM_IDX_WIDTH-1:0] dm_buf_addr, output logic [PCIM_DATA_WIDTH-1:0] buf_dm_data @@ -87,14 +90,14 @@ module sde_c2h_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact logic [BUF_RAM_ADDR_WIDTH-1:0] buf_wr_ptr; logic [BUF_RAM_ADDR_WIDTH-1:0] buf_rd_ptr; logic [BUF_RAM_ADDR_WIDTH-1:0] buf_rd_ptr_q; - + logic buf_write_en; logic buf_full; logic buf_oflow; logic buf_uflow; logic buf_empty; - + logic buf_ram_wr; logic [BUF_RAM_ADDR_WIDTH-1:0] buf_ram_waddr; logic [PCIM_DATA_WIDTH-1:0] buf_ram_wdata; @@ -105,7 +108,7 @@ module sde_c2h_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact logic aux_ram_full; logic aux_ram_oflow; logic aux_fifo_uflow; - + assign buf_wr_ptr_next = (buf_wr_ptr >= BUF_DEPTH_MINUS1) ? 0 : buf_wr_ptr + 1; assign buf_rd_ptr = dm_buf_rd_byte_addr[PCIM_ADDR_BYTE_IDX_WIDTH +: BUF_ADDR_RAM_IDX_WIDTH]; @@ -118,11 +121,11 @@ module sde_c2h_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact buf_wr_ptr <= '{default:'0}; buf_full <= 0; buf_empty <= 0; - - buf_rd_ptr_q <= 0; + + buf_rd_ptr_q <= 0; buf_oflow <= 0; buf_uflow <= 0; - end + end else begin buf_wr_ptr <= buf_write_en ? buf_wr_ptr_next : buf_wr_ptr; buf_full <= buf_write_en ? (buf_wr_ptr_next == buf_rd_ptr) : @@ -130,7 +133,7 @@ module sde_c2h_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact buf_full; buf_empty <= ~buf_write_en & ~buf_full & (buf_wr_ptr == buf_rd_ptr) ? 1'b1 : buf_write_en ? 1'b0 : buf_empty; - + buf_rd_ptr_q <= buf_rd_ptr; buf_oflow <= buf_full & buf_write_en; buf_uflow <= buf_empty & (buf_rd_ptr_q != buf_rd_ptr); @@ -145,9 +148,9 @@ module sde_c2h_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact buf_cfg_buf_wr_ptr = buf_wr_ptr; buf_cfg_buf_rd_addr = dm_buf_rd_byte_addr; end - + assign buf_axis_ready = ~buf_full & ~aux_ram_full; - + // Buffer BRAM assign buf_ram_wr = buf_write_en; assign buf_ram_waddr = buf_wr_ptr; @@ -155,9 +158,9 @@ module sde_c2h_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact assign buf_ram_rd = dm_buf_rd; assign buf_ram_raddr = dm_buf_addr; - + // Desc RAM - Using 2 port RAM (1w1r) - bram_1w1r #(.WIDTH(PCIM_DATA_WIDTH), + bram_1w1r #(.WIDTH(PCIM_DATA_WIDTH), .ADDR_WIDTH(BUF_RAM_ADDR_WIDTH), .DEPTH(BUF_DEPTH) ) BUF_RAM (.clk (clk), @@ -172,7 +175,7 @@ module sde_c2h_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact ); assign buf_dm_data = buf_ram_rdata; - + // Buffer AUX FT FIFO localparam BUF_AUX_RAM_WIDTH = DESC_TYPE ? BUF_AUX_WIDTH - 1 : BUF_AUX_WIDTH; @@ -203,7 +206,7 @@ module sde_c2h_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact logic aux_ram_wr_ptr_msb; logic aux_ram_rd_ptr_msb; - + always_comb begin wr_last_byte_addr = 0; for (int byte_idx = 0; byte_idx < PCIM_DATA_WIDTH_BYTES; byte_idx++) begin @@ -211,15 +214,15 @@ module sde_c2h_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact wr_last_byte_addr = byte_idx; end end - + assign aux_ram_wr = buf_write_en & axis_buf_last; assign aux_ram_waddr = aux_ram_wr_ptr; - assign aux_ram_wdata = DESC_TYPE ? {buf_wr_ptr, wr_last_byte_addr} : + assign aux_ram_wdata = DESC_TYPE ? {buf_wr_ptr, wr_last_byte_addr} : {axis_buf_user, buf_wr_ptr, wr_last_byte_addr}; assign aux_ram_rd = aux_ram_pop; assign aux_ram_raddr = aux_ram_rd_ptr; - + // AUX RAM bram_1w1r #(.WIDTH(BUF_AUX_RAM_WIDTH), .ADDR_WIDTH(BUF_AUX_RAM_ADDR_WIDTH), @@ -229,13 +232,13 @@ module sde_c2h_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact .ena (aux_ram_wr), .addra (aux_ram_waddr), .da (aux_ram_wdata), - + .enb (aux_ram_rd), .addrb (aux_ram_raddr), .qb (aux_ram_rdata) ); - // Flow-through FIFO + // Flow-through FIFO ft_fifo #(.FIFO_WIDTH(BUF_AUX_RAM_WIDTH) ) AUX_FT_FIFO (.clk (clk), .rst_n (1'b1), @@ -243,7 +246,7 @@ module sde_c2h_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact .ram_fifo_empty (aux_ram_empty), .ram_fifo_data (aux_ram_rdata), .ram_pop (aux_ram_pop), - + .ft_pop (aux_ft_ff_pop), .ft_valid (aux_ft_ff_valid), .ft_data (aux_ft_ff_data) @@ -252,15 +255,15 @@ module sde_c2h_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact assign aux_ft_ff_pop = dm_buf_aux_pop; assign buf_dm_aux_valid = aux_ft_ff_valid; assign buf_dm_aux_data = DESC_TYPE ? {1'b0, aux_ft_ff_data} : aux_ft_ff_data; - - assign aux_ram_wr_ptr_next = (aux_ram_wr_ptr == BUF_AUX_RAM_DEPTH_MINUS1) ? ({BUF_AUX_RAM_ADDR_WIDTH{1'b0}}) : + + assign aux_ram_wr_ptr_next = (aux_ram_wr_ptr == BUF_AUX_RAM_DEPTH_MINUS1) ? ({BUF_AUX_RAM_ADDR_WIDTH{1'b0}}) : aux_ram_wr_ptr + 1; assign aux_ram_wr_ptr_msb_next = (aux_ram_wr_ptr == BUF_AUX_RAM_DEPTH_MINUS1) ? ~aux_ram_wr_ptr_msb : aux_ram_wr_ptr_msb; - + assign aux_ram_rd_ptr_next = (aux_ram_rd_ptr == BUF_AUX_RAM_DEPTH_MINUS1) ? ({BUF_AUX_RAM_ADDR_WIDTH{1'b0}}) : aux_ram_rd_ptr + 1; assign aux_ram_rd_ptr_msb_next = (aux_ram_rd_ptr == BUF_AUX_RAM_DEPTH_MINUS1) ? ~aux_ram_rd_ptr_msb : aux_ram_rd_ptr_msb; - + always @(posedge clk) if (!rst_n) begin aux_ram_wr_ptr <= 0; @@ -293,12 +296,12 @@ module sde_c2h_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact buf_cfg_aux_ram_wr_ptr = 0; buf_cfg_aux_ram_wr_ptr = aux_ram_wr_ptr; buf_cfg_aux_ram_wr_ptr[15] = aux_ram_wr_ptr_msb; - + buf_cfg_aux_ram_rd_ptr = 0; buf_cfg_aux_ram_rd_ptr = aux_ram_rd_ptr; buf_cfg_aux_ram_rd_ptr[15] = aux_ram_rd_ptr_msb; end - + // Number of bytes in the buffer localparam BUF_SIZE_BYTES = BUF_DEPTH * (PCIM_DATA_WIDTH>>3); @@ -326,21 +329,21 @@ module sde_c2h_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact buf_wr_ptr_q <= buf_wr_ptr; buf_wr_ptr_qq <= buf_wr_ptr_q; end - + // When EOP is not valid // This is difference between read and write pointer // assign buf_ptr_diff = (buf_wr_ptr > buf_rd_ptr) ? (buf_wr_ptr - buf_rd_ptr) : // (BUF_DEPTH + buf_wr_ptr - buf_rd_ptr); - + assign buf_wr_byte_addr = {buf_wr_ptr_qq, {PCIM_ADDR_BYTE_IDX_WIDTH{1'b0}}}; assign buf_wr_byte_addr_plus_depth = BUF_SIZE_BYTES + buf_wr_byte_addr; assign buf_byte_addr_diff = (buf_wr_byte_addr > buf_rd_byte_addr) ? ({1'b0, buf_wr_byte_addr} - {1'b0, buf_rd_byte_addr}) : (buf_wr_byte_addr_plus_depth - {1'b0, buf_rd_byte_addr}); - + assign num_bytes_no_eop = ~buf_full & (buf_wr_byte_addr == buf_rd_byte_addr) ? 0 : buf_byte_addr_diff; - + // When EOP is valid // This is the difference between the write and the first EOP pointer assign aux_first_eop_wr_byte_addr = aux_ft_ff_data[0 +: BUF_ADDR_WIDTH]; @@ -349,7 +352,7 @@ module sde_c2h_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact assign buf_aux_byte_addr_diff = (aux_first_eop_wr_byte_addr >= buf_rd_byte_addr) ? ({1'b0, aux_first_eop_wr_byte_addr} - {1'b0, buf_rd_byte_addr}) : (aux_first_eop_wr_byte_addr_plus_depth - {1'b0, buf_rd_byte_addr}); assign num_bytes_eop = buf_aux_byte_addr_diff + 1; - + // CANNOT FLOP// always @(posedge clk) // CANNOT FLOP// if (!rst_n) // CANNOT FLOP// buf_dm_num_bytes <= '{default:'0}; @@ -360,37 +363,37 @@ module sde_c2h_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact logic [31:0] buf_in_pkt_cnt; logic [31:0] buf_out_pkt_cnt; logic [BUF_ADDR_WIDTH:0] buf_dm_num_bytes_q; - + // Error detection // if buf_dm_num_bytes decreases by 24K, thats an error always @(posedge clk) if (!rst_n) begin buf_cfg_in_pkt_cnt <= 0; buf_cfg_out_pkt_cnt <= 0; - + buf_cfg_num_bytes <= 0; // buf_cfg_num_bytes_eop <= 0; // buf_cfg_num_bytes_no_eop <= 0; end else begin - buf_cfg_in_pkt_cnt <= cfg_buf_clr_in_pkt_cnt ? 0 : + buf_cfg_in_pkt_cnt <= cfg_buf_clr_in_pkt_cnt ? 0 : (axis_buf_valid & axis_buf_last & buf_axis_ready) ? buf_cfg_in_pkt_cnt + 1 : buf_cfg_in_pkt_cnt; buf_cfg_out_pkt_cnt <= cfg_buf_clr_out_pkt_cnt ? 0 : aux_ft_ff_valid & aux_ft_ff_pop ? buf_cfg_out_pkt_cnt + 1 : buf_cfg_out_pkt_cnt; - + buf_cfg_num_bytes <= buf_dm_num_bytes; // buf_cfg_num_bytes_eop <= num_bytes_eop; // buf_cfg_num_bytes_no_eop <= num_bytes_no_eop; end // else: !if(!rst_n) - + `ifndef NO_SDE_DEBUG_ILA - + // ILA Signals ila_sde_c2h_buf SDE_C2H_BUF_ILA ( .clk (clk), - + // 0 .probe0(buf_full ), .probe1(buf_wr_ptr_qq ), @@ -409,7 +412,7 @@ module sde_c2h_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact .probe13(buf_cfg_num_bytes_err ), .probe14(aux_ram_oflow ), .probe15(buf_oflow ), - + .probe16(buf_in_pkt_cnt ), .probe17(buf_out_pkt_cnt) @@ -417,7 +420,5 @@ module sde_c2h_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact `endif // `ifndef NO_SDE_DEBUG_ILA - -endmodule // sde_c2h_buf - +endmodule // sde_c2h_buf diff --git a/hdk/cl/examples/cl_sde/design/sde_c2h_cfg.sv b/hdk/cl/examples/cl_sde/design/sde_c2h_cfg.sv index 1c0d99993..4b282cb17 100644 --- a/hdk/cl/examples/cl_sde/design/sde_c2h_cfg.sv +++ b/hdk/cl/examples/cl_sde/design/sde_c2h_cfg.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016-2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + // C2H Config Access @@ -33,7 +36,7 @@ module sde_c2h_cfg #(parameter bit DESC_TYPE = 0, input desc_ooo_error, input desc_unalin_error, - + // Config to Desc output logic cfg_desc_clr_cdt_consumed, output logic cfg_desc_clr_cdt_limit, @@ -46,7 +49,7 @@ module sde_c2h_cfg #(parameter bit DESC_TYPE = 0, output logic [19:0] cfg_wc_tick_cnt, output logic [3:0] cfg_wc_to_cnt, output logic [5:0] cfg_wc_cnt_minus1, - + input [31:0] desc_cfg_cdt_consumed, input [31:0] desc_cfg_cdt_limit, input [31:0] desc_cfg_desc_cnt, @@ -67,7 +70,7 @@ module sde_c2h_cfg #(parameter bit DESC_TYPE = 0, input dm_cfg_bresp_err, input dm_cfg_desc_len_err, - + // Config to WB output logic cfg_wb_desc_cdt_en, output logic cfg_wb_desc_cnt_en, @@ -83,8 +86,8 @@ module sde_c2h_cfg #(parameter bit DESC_TYPE = 0, input wb_cfg_md_bresp_err , input wb_cfg_sts_bresp_err, - output logic cfg_wb_desc_error, - output logic cfg_wb_dm_error, + output logic cfg_wb_desc_error, + output logic cfg_wb_dm_error, output logic cfg_wb_wb_error, input [31:0] wb_cfg_status_dw, @@ -97,10 +100,10 @@ module sde_c2h_cfg #(parameter bit DESC_TYPE = 0, input [15:0] buf_cfg_buf_rd_addr, input buf_cfg_aux_fifo_oflow, input buf_cfg_aux_fifo_uflow, - input buf_cfg_aux_fifo_full , + input buf_cfg_aux_fifo_full , input buf_cfg_aux_fifo_empty, input [15:0] buf_cfg_aux_ram_wr_ptr, - input [15:0] buf_cfg_aux_ram_rd_ptr, + input [15:0] buf_cfg_aux_ram_rd_ptr, input [15:0] buf_cfg_num_bytes, input [31:0] buf_cfg_in_pkt_cnt, input [31:0] buf_cfg_out_pkt_cnt, @@ -114,14 +117,14 @@ module sde_c2h_cfg #(parameter bit DESC_TYPE = 0, localparam DESC_WIDTH_DW = DESC_WIDTH >> 5; localparam DESC_WIDTH_DW_MINUS1 = DESC_WIDTH_DW - 1; - + // Address range is 1.5KB (0x000 - 0x600) - + ///////////////////////////////////////////////// // C2H Global Control and Status (0x0000 - 0x00FC) ///////////////////////////////////////////////// // No registers yet - + ///////////////////////////////////////////////// // Desc Config and Status (0x0100 - 0x01FC) ///////////////////////////////////////////////// @@ -141,7 +144,7 @@ module sde_c2h_cfg #(parameter bit DESC_TYPE = 0, // 0x10 : Desc Address Registers (RW) // 15:0 - Desc RAM Address (RW) // 31:16 - Desc DW Index (W0C) (Auto increment) - + // 0x14 : Desc Read/Write Data (RW) // 0x18 : Desc Status @@ -156,7 +159,7 @@ module sde_c2h_cfg #(parameter bit DESC_TYPE = 0, // 0 - Descriptor Type (0 - Regular, 1 - Compact) (RO) // 15:1 - RSVD // 31:16 - Descriptor RAM Depth (Maximum number of descriptors) (RO) - + ///////////////////////////////////////////////// // Data Mover Config and Status (0x0200 - 0x02FC) ///////////////////////////////////////////////// @@ -167,7 +170,7 @@ module sde_c2h_cfg #(parameter bit DESC_TYPE = 0, // 0 - BRESP Error (RW1C) // 1 - Descriptor length Error (RW1C) // 31:2 - RSVD - + ///////////////////////////////////////////////// // Write Back Config and Status (0x0300 - 0x34FC) ///////////////////////////////////////////////// @@ -182,7 +185,7 @@ module sde_c2h_cfg #(parameter bit DESC_TYPE = 0, // 7 - Metadata Write-Pointer Write-Back Coalescing Enable // 13:8 - Write-Back Coalescing Count Minus 1 // 31:14 - RSVD - + // 0x04 : Status Write-Back Address Low (RW) // 0x08 : Status Write-back Address High (RW) @@ -193,15 +196,15 @@ module sde_c2h_cfg #(parameter bit DESC_TYPE = 0, // 31:24 - RSVD // 0x10 : TODO - Metadata Coalescing Control & Status Register (RW) - TODO - + // 0x14 : TODO - Metadata Write-Pointer Coalescing Control & Status Register (RW) - TODO - + // 0x18 : Metadata Ring Write-Back Base Address Low (RW) - + // 0x1C : Metadata Ring Write-Back Base Address High (RW) - + // 0x20 : Metadata Ring Size in Bytes (Should be integer multiple of WB size) (RW) - + // 0x24 : Metadata Read Pointer (RW) // 0x28 : Metadata Write Pointer (RWOC) @@ -210,13 +213,13 @@ module sde_c2h_cfg #(parameter bit DESC_TYPE = 0, // 0 - BRESP Error for Status Write // 1 - BRESP Error for Metadata Write // 31:2 - RSVD - + // 0x30 : Status DW // 0 - Desc Error // 1 - Data Mover Error // 2 - Write-Back Error // 31:3 - RSVD - + ///////////////////////////////////////////////// // Buffer Config and Status (0x0400 - 0x04FC) ///////////////////////////////////////////////// @@ -225,7 +228,7 @@ module sde_c2h_cfg #(parameter bit DESC_TYPE = 0, // 0x04 : Buf Status // 0 - Buffer Overflow (RW1C) - // 1 - Buffer Underflow (RW1C) + // 1 - Buffer Underflow (RW1C) // 2 - Aux FIFO Overflow (RW1C) // 3 - Aux FIFO Underflow (RW1C) // 4 - Buffer Full (RO) @@ -233,7 +236,7 @@ module sde_c2h_cfg #(parameter bit DESC_TYPE = 0, // 6 - Aux FIFO Full (RO) // 7 - Aux FIFO Valid (RO) // 31:8 - RSVD - + // 0x08 : Input Packet Count (RW0C) // 0x0C : Ouput Packet Count (RW0C) @@ -251,12 +254,12 @@ module sde_c2h_cfg #(parameter bit DESC_TYPE = 0, // 0x18 : Number of Bytes // 15:0 - Buffer Number of Bytes (RO) // 31:16 - RSVD - + ///////////////////////////////////////////////// // AXIS Config and Status (0x0500 - 0x05FC) ///////////////////////////////////////////////// // 0x00 : Packet Count (RW0C) - + logic cfg_wr_q; logic cfg_rd_q; logic cfg_wr_re; @@ -282,7 +285,7 @@ module sde_c2h_cfg #(parameter bit DESC_TYPE = 0, logic [31:0] rdata_range_4; logic [31:0] rdata_range_5; - + always @(posedge clk) if (!rst_n) begin cfg_wr_q <= 0; @@ -293,10 +296,10 @@ module sde_c2h_cfg #(parameter bit DESC_TYPE = 0, cfg_rd_q <= c2h_ps_cfg_rd_req; end assign cfg_wr_re = ~cfg_wr_q & c2h_ps_cfg_wr_req; - assign cfg_rd_re = ~cfg_rd_q & c2h_ps_cfg_rd_req; + assign cfg_rd_re = ~cfg_rd_q & c2h_ps_cfg_rd_req; assign cfg_wr_fe = cfg_wr_q & ~c2h_ps_cfg_wr_req; assign cfg_rd_fe = cfg_rd_q & ~c2h_ps_cfg_rd_req; - + // Decode Address ranges assign dec_range_0 = (c2h_ps_cfg_addr >= 16'h0000) & (c2h_ps_cfg_addr < 16'h0100); assign dec_range_1 = (c2h_ps_cfg_addr >= 16'h0100) & (c2h_ps_cfg_addr < 16'h0200); @@ -304,7 +307,7 @@ module sde_c2h_cfg #(parameter bit DESC_TYPE = 0, assign dec_range_3 = (c2h_ps_cfg_addr >= 16'h0300) & (c2h_ps_cfg_addr < 16'h0400); assign dec_range_4 = (c2h_ps_cfg_addr >= 16'h0400) & (c2h_ps_cfg_addr < 16'h0500); assign dec_range_5 = (c2h_ps_cfg_addr >= 16'h0500) & (c2h_ps_cfg_addr < 16'h0600); - + always @(posedge clk) if (!rst_n) begin c2h_ps_cfg_ack <= 0; @@ -325,20 +328,20 @@ module sde_c2h_cfg #(parameter bit DESC_TYPE = 0, dec_range_4 ? rdata_range_4 : dec_range_5 ? rdata_range_5 : 32'hbaad_3600; end // else: !if(!rst_n) - + ///////////////////////////////////////////////// // Range 0 (0x0000 - 0x00FC) ///////////////////////////////////////////////// // TODO: No registers in this range yet assign ack_range_0 = 1; assign rdata_range_0 = 32'hbaad_3000; - + ///////////////////////////////////////////////// // Range 1 (0x0100 - 0x01FC) ///////////////////////////////////////////////// logic ack_wr_range_1; logic ack_rd_range_1; - + logic clr_desc_ram_idx; logic inc_desc_ram_idx_wr; logic inc_desc_ram_idx_rd; @@ -361,7 +364,7 @@ module sde_c2h_cfg #(parameter bit DESC_TYPE = 0, logic clr_desc_oflow; logic clr_desc_ooo_error; logic clr_desc_unalin_error; - + assign ack_range_1 = c2h_ps_cfg_wr_req ? ack_wr_range_1 : ack_rd_range_1; // Register Writes @@ -373,7 +376,7 @@ module sde_c2h_cfg #(parameter bit DESC_TYPE = 0, end else if (c2h_ps_cfg_wr_req & dec_range_1) begin ack_wr_range_1 <= 0; - case (c2h_ps_cfg_addr[7:0]) + case (c2h_ps_cfg_addr[7:0]) 8'h10 : begin ack_wr_range_1 <= 1; cfg_desc_ram_addr <= c2h_ps_cfg_wdata; @@ -405,7 +408,7 @@ module sde_c2h_cfg #(parameter bit DESC_TYPE = 0, assign cfg_desc_type = DESC_TYPE; assign cfg_desc_ram_depth = DESC_RAM_DEPTH; - + // Read data and ack always @(posedge clk) if (!rst_n) begin @@ -459,19 +462,19 @@ module sde_c2h_cfg #(parameter bit DESC_TYPE = 0, assign inc_desc_ram_idx_rd = cfg_rd_fe & dec_range_1 & (c2h_ps_cfg_addr[7:0] == 8'h14); assign inc_desc_ram_idx = cfg_rd_q ? inc_desc_ram_idx_rd : inc_desc_ram_idx_wr; - always @(posedge clk) + always @(posedge clk) if (!rst_n) begin desc_ram_idx <= 4'd0; cfg_desc_ram_rd_dw <= 32'd0; cfg_desc_ram_data_q <= '{default:'0}; - + cfg_desc_ram_wr_ack <= 0; cfg_desc_ram_rd_ack <= 0; cfg_desc_ram_rd_ack_q <= 0; - + cfg_desc_ram_addr_reg_wr <= 0; cfg_desc_ram_data_reg_wr <= 0; - + cfg_desc_ram_data_reg_wr_last <= 0; cfg_desc_ram_wr_req <= 0; cfg_desc_ram_rd_req <= 0; @@ -482,29 +485,29 @@ module sde_c2h_cfg #(parameter bit DESC_TYPE = 0, inc_desc_ram_idx ? desc_ram_idx + 4'd1 : desc_ram_idx; for (int dw_idx = 0; dw_idx < DESC_WIDTH_DW; dw_idx++) - if (desc_ram_idx == dw_idx) + if (desc_ram_idx == dw_idx) cfg_desc_ram_rd_dw <= cfg_desc_ram_data_q[32*dw_idx +: 32]; - + if (desc_cfg_ram_ack) cfg_desc_ram_data_q <= desc_cfg_ram_rdata; - else + else for (int dw_idx = 0; dw_idx < DESC_WIDTH_DW; dw_idx++) - if (desc_ram_idx == dw_idx) + if (desc_ram_idx == dw_idx) cfg_desc_ram_data_q[32*dw_idx +: 32] <= cfg_desc_ram_data_reg_wr ? cfg_desc_ram_wr_dw : cfg_desc_ram_data_q[32*dw_idx +: 32]; - - + + cfg_desc_ram_wr_ack <= (desc_ram_idx == DESC_WIDTH_DW_MINUS1) ? desc_cfg_ram_ack : 1'b1; cfg_desc_ram_rd_ack <= (desc_ram_idx == 0) ? desc_cfg_ram_ack : 1'b1; cfg_desc_ram_rd_ack_q <= cfg_desc_ram_rd_ack; - + cfg_desc_ram_addr_reg_wr <= cfg_wr_re & dec_range_1 & (c2h_ps_cfg_addr[7:0] == 8'h10); cfg_desc_ram_data_reg_wr <= cfg_wr_re & dec_range_1 & (c2h_ps_cfg_addr[7:0] == 8'h14); - + cfg_desc_ram_data_reg_wr_last <= cfg_wr_re & dec_range_1 & (c2h_ps_cfg_addr[7:0] == 8'h14) & (desc_ram_idx == DESC_WIDTH_DW_MINUS1); cfg_desc_ram_wr_req <= cfg_desc_ram_data_reg_wr_last; cfg_desc_ram_rd_req <= cfg_rd_re & dec_range_1 & (c2h_ps_cfg_addr[7:0] == 8'h14) & (desc_ram_idx == 0); - + end // else: !if(!rst_n) assign cfg_desc_ram_wdata = cfg_desc_ram_data_q; @@ -522,7 +525,7 @@ module sde_c2h_cfg #(parameter bit DESC_TYPE = 0, cfg_desc_unalin_error <= desc_unalin_error ? 1'b1 : clr_desc_unalin_error ? 1'b0 : cfg_desc_unalin_error; end // else: !if(!rst_n) - + ///////////////////////////////////////////////// // Range 2 (0x0200 - 0x02FC) ///////////////////////////////////////////////// @@ -545,7 +548,7 @@ module sde_c2h_cfg #(parameter bit DESC_TYPE = 0, end else if (c2h_ps_cfg_wr_req & dec_range_2) begin ack_wr_range_2 <= 0; - case (c2h_ps_cfg_addr[7:0]) + case (c2h_ps_cfg_addr[7:0]) 8'h00 : begin ack_wr_range_2 <= 1; cfg_dm_ctl_reg0 <= c2h_ps_cfg_wdata; @@ -605,8 +608,8 @@ module sde_c2h_cfg #(parameter bit DESC_TYPE = 0, logic cfg_wb_sts_bresp_err; logic clr_wb_md_bresp_err; logic clr_wb_sts_bresp_err; - - + + assign ack_range_3 = c2h_ps_cfg_wr_req ? ack_wr_range_3 : ack_rd_range_3; // Register Writes @@ -623,7 +626,7 @@ module sde_c2h_cfg #(parameter bit DESC_TYPE = 0, end else if (c2h_ps_cfg_wr_req & dec_range_3) begin ack_wr_range_3 <= 0; - case (c2h_ps_cfg_addr[7:0]) + case (c2h_ps_cfg_addr[7:0]) 8'h00 : begin ack_wr_range_3 <= 1; cfg_wb_ctl_reg0 <= c2h_ps_cfg_wdata; @@ -660,7 +663,7 @@ module sde_c2h_cfg #(parameter bit DESC_TYPE = 0, ack_wr_range_3 <= 1; endcase // case (c2h_ps_cfg_addr[7:0]) end // if (c2h_ps_cfg_wr_req & dec_range_2) - + // Register Reads always @(posedge clk) if (!rst_n) begin @@ -731,7 +734,7 @@ module sde_c2h_cfg #(parameter bit DESC_TYPE = 0, assign clr_wb_sts_bresp_err = cfg_wr_re & dec_range_3 & (c2h_ps_cfg_addr[7:0] == 8'h2C) & c2h_ps_cfg_wdata[0]; assign clr_wb_md_bresp_err = cfg_wr_re & dec_range_3 & (c2h_ps_cfg_addr[7:0] == 8'h2C) & c2h_ps_cfg_wdata[1]; - + assign cfg_wb_desc_cnt_en = cfg_wb_ctl_reg0[0]; assign cfg_wb_pkt_cnt_en = cfg_wb_ctl_reg0[1]; assign cfg_wb_desc_cdt_en = cfg_wb_ctl_reg0[2]; @@ -763,7 +766,7 @@ module sde_c2h_cfg #(parameter bit DESC_TYPE = 0, logic ack_wr_range_4; logic ack_rd_range_4; logic [31:0] cfg_buf_ctl_reg0; - + assign ack_range_4 = c2h_ps_cfg_wr_req ? ack_wr_range_4 : ack_rd_range_4; // Register Writes @@ -774,7 +777,7 @@ module sde_c2h_cfg #(parameter bit DESC_TYPE = 0, end else if (c2h_ps_cfg_wr_req & dec_range_4) begin ack_wr_range_4 <= 0; - case (c2h_ps_cfg_addr[7:0]) + case (c2h_ps_cfg_addr[7:0]) 8'h00 : begin ack_wr_range_4 <= 1; cfg_buf_ctl_reg0 <= c2h_ps_cfg_wdata; @@ -856,7 +859,7 @@ module sde_c2h_cfg #(parameter bit DESC_TYPE = 0, else begin cfg_axis_clr_pkt_cnt <= cfg_wr_re & dec_range_5 & (c2h_ps_cfg_addr[7:0] == 8'h00) & (c2h_ps_cfg_wdata == 32'd0); end - + // Read data and ack always @(posedge clk) if (!rst_n) begin @@ -890,5 +893,5 @@ module sde_c2h_cfg #(parameter bit DESC_TYPE = 0, cfg_wb_dm_error <= cfg_dm_bresp_err | cfg_dm_desc_len_err; cfg_wb_wb_error <= cfg_wb_sts_bresp_err | cfg_wb_md_bresp_err; end - + endmodule // sde_c2h_cfg diff --git a/hdk/cl/examples/cl_sde/design/sde_c2h_data.sv b/hdk/cl/examples/cl_sde/design/sde_c2h_data.sv index 7c61f0d11..4954fd7c5 100644 --- a/hdk/cl/examples/cl_sde/design/sde_c2h_data.sv +++ b/hdk/cl/examples/cl_sde/design/sde_c2h_data.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016-2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + // C2H Data Mover @@ -105,16 +108,16 @@ module sde_c2h_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact localparam PCIM_MAX_WR_SIZE_BYTES_USER = PCIM_MAX_WR_SIZE == 0 ? 512 : PCIM_MAX_WR_SIZE == 1 ? 1024 : PCIM_MAX_WR_SIZE == 2 ? 2048 : 4096; - + localparam PCIM_MAX_WR_SIZE_BYTES_DATA_WIDTH = PCIM_DATA_WIDTH_BYTES == 64 ? 4096 : PCIM_DATA_WIDTH_BYTES == 32 ? 4096 : PCIM_DATA_WIDTH_BYTES == 16 ? 4096 : PCIM_DATA_WIDTH_BYTES == 8 ? 2048 : PCIM_DATA_WIDTH_BYTES == 4 ? 1024 : PCIM_DATA_WIDTH_BYTES == 2 ? 512 : 256; - + localparam PCIM_MAX_WR_SIZE_BYTES = PCIM_MAX_WR_SIZE_BYTES_DATA_WIDTH > PCIM_MAX_WR_SIZE_BYTES_USER ? PCIM_MAX_WR_SIZE_BYTES_USER : PCIM_MAX_WR_SIZE_BYTES_DATA_WIDTH; - + // Request FSM typedef enum logic [2:0] {REQ_IDLE = 0, REQ_GET_DESC = 1, @@ -171,7 +174,7 @@ module sde_c2h_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact logic dp_wb_ff_full; logic bresp_prealloc_avail; - + logic [BUF_ADDR_WIDTH:0] buf_dm_num_bytes_q; logic buf_dm_aux_valid_q; logic [BUF_AUX_WIDTH-1:0] buf_dm_aux_data_q ; @@ -282,11 +285,11 @@ module sde_c2h_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact //Optimize// curr_desc_dest_addr <= curr_desc_dest_addr; curr_desc_dest_addr <= curr_desc_dest_addr_d; // curr_desc_max_minus_dest_addr <= 13'h1000 - curr_desc_dest_addr_d[11:0]; - curr_desc_max_minus_dest_addr <= (PCIM_MAX_WR_SIZE_BYTES == 4096) ? 13'h1000 - curr_desc_dest_addr_d[11:0] : - (PCIM_MAX_WR_SIZE_BYTES == 2048) ? 13'h0800 - curr_desc_dest_addr_d[10:0] : - (PCIM_MAX_WR_SIZE_BYTES == 1024) ? 13'h0400 - curr_desc_dest_addr_d[ 9:0] : + curr_desc_max_minus_dest_addr <= (PCIM_MAX_WR_SIZE_BYTES == 4096) ? 13'h1000 - curr_desc_dest_addr_d[11:0] : + (PCIM_MAX_WR_SIZE_BYTES == 2048) ? 13'h0800 - curr_desc_dest_addr_d[10:0] : + (PCIM_MAX_WR_SIZE_BYTES == 1024) ? 13'h0400 - curr_desc_dest_addr_d[ 9:0] : (PCIM_MAX_WR_SIZE_BYTES == 512) ? 13'h0200 - curr_desc_dest_addr_d[ 8:0] : 13'h0100 - curr_desc_dest_addr_d[ 7:0]; - + // Length and Decrement after every Txn if ((req_state == REQ_IDLE) && desc_dm_desc_valid) curr_desc_len <= desc_dm_desc_in.len; @@ -689,7 +692,7 @@ module sde_c2h_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact // Case 1 - For all beats - Save (A - R) Bytes from 3 // Number of Bytes - assign stg4_dp_num_bytes_case1 = pl3_dp_first & pl3_dp_last ? (pl3_dp_num_bytes - curr_txn_num_bytes_fo) : + assign stg4_dp_num_bytes_case1 = pl3_dp_first & pl3_dp_last ? (pl3_dp_num_bytes - curr_txn_num_bytes_fo) : pl3_dp_first ? min_bytes_2(pl3_dp_num_bytes, curr_txn_num_bytes_sav) : pl3_dp_num_bytes - curr_txn_num_bytes_dw_minus_sav; @@ -1164,16 +1167,16 @@ module sde_c2h_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact logic bresp_prealloc_avail_cnt_inc; logic bresp_prealloc_avail_cnt_dec; logic [7:0] bresp_prealloc_avail_cnt; - + assign bresp_prealloc_avail_cnt_dec = (req_state == REQ_ADDR) & (req_state_next != REQ_ADDR); assign bresp_prealloc_avail_cnt_inc = dp_bresp_ff_pop; - + always @(posedge clk) if (!rst_n) bresp_prealloc_avail_cnt <= DP_DATA_BRESP_FIFO_DEPTH; else - bresp_prealloc_avail_cnt <= bresp_prealloc_avail_cnt_inc & ~bresp_prealloc_avail_cnt_dec ? bresp_prealloc_avail_cnt + 1 : - ~bresp_prealloc_avail_cnt_inc & bresp_prealloc_avail_cnt_dec ? bresp_prealloc_avail_cnt - 1 : + bresp_prealloc_avail_cnt <= bresp_prealloc_avail_cnt_inc & ~bresp_prealloc_avail_cnt_dec ? bresp_prealloc_avail_cnt + 1 : + ~bresp_prealloc_avail_cnt_inc & bresp_prealloc_avail_cnt_dec ? bresp_prealloc_avail_cnt - 1 : bresp_prealloc_avail_cnt; assign bresp_prealloc_avail = (bresp_prealloc_avail_cnt > 0); @@ -1315,4 +1318,3 @@ module sde_c2h_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact endmodule // sde_c2h_data - diff --git a/hdk/cl/examples/cl_sde/design/sde_desc.sv b/hdk/cl/examples/cl_sde/design/sde_desc.sv index 310f9c934..74c749c5e 100644 --- a/hdk/cl/examples/cl_sde/design/sde_desc.sv +++ b/hdk/cl/examples/cl_sde/design/sde_desc.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016-2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ // Module is common for H2C and C2H @@ -61,7 +63,7 @@ module sde_desc #(parameter bit H2C_N_C2H = 0, // 1 - H2C, 0 - C2H output logic desc_cfg_uflow, output logic desc_cfg_full, output logic desc_cfg_empty, - + // Descriptor to Data Mover output logic desc_dm_empty, input dm_desc_pop, @@ -69,7 +71,7 @@ module sde_desc #(parameter bit H2C_N_C2H = 0, // 1 - H2C, 0 - C2H output logic desc_dm_desc_valid, input dm_desc_cnt_inc, - + // Descriptor to Write Back Block output logic desc_wb_limit_req, output logic [31:0] desc_wb_limit, @@ -82,21 +84,21 @@ module sde_desc #(parameter bit H2C_N_C2H = 0, // 1 - H2C, 0 - C2H output logic [PCIM_ADDR_WIDTH-1:0] desc_pm_araddr, output logic [PCIM_LEN_WIDTH-1:0] desc_pm_arlen, input pm_desc_arready, - + // Read Data from PCIM input pm_desc_rvalid, input [1:0] pm_desc_rresp, input [PCIM_DATA_WIDTH-1:0] pm_desc_rdata, input pm_desc_rlast, output logic desc_pm_rready - + ); localparam DESC_RAM_WIDTH = ~DESC_TYPE & H2C_N_C2H ? $bits(sde_pkg::h2c_reg_sav_desc_t) : DESC_TYPE & H2C_N_C2H ? $bits(sde_pkg::h2c_comp_sav_desc_t) : ~DESC_TYPE & ~H2C_N_C2H ? $bits(sde_pkg::c2h_reg_sav_desc_t) : $bits(sde_pkg::c2h_comp_sav_desc_t); - + logic ps_desc_wr_req_q = 0; logic [DESC_RAM_WIDTH-1:0] ps_desc_wdata_q = 0; logic cfg_desc_ram_wr_req_q = 0; @@ -106,14 +108,14 @@ module sde_desc #(parameter bit H2C_N_C2H = 0, // 1 - H2C, 0 - C2H logic cfg_desc_ram_rd_req_winner_q = 0; logic cfg_desc_ram_wr_req_winner; logic cfg_desc_ram_rd_req_winner; - + logic desc_ram_wr; logic [DESC_RAM_WIDTH-1:0] desc_ram_wdata; logic [DESC_ADDR_WIDTH-1:0] desc_ram_waddr; logic desc_ram_rd; logic [DESC_RAM_WIDTH-1:0] desc_ram_rdata; logic [DESC_ADDR_WIDTH-1:0] desc_ram_raddr; - + logic [DESC_ADDR_WIDTH-1:0] desc_ram_wr_ptr; logic desc_ram_wr_ptr_msb; logic [DESC_ADDR_WIDTH-1:0] desc_ram_rd_ptr; @@ -125,13 +127,13 @@ module sde_desc #(parameter bit H2C_N_C2H = 0, // 1 - H2C, 0 - C2H logic desc_ram_pop; logic desc_ram_empty; logic desc_ram_full; - + logic desc_ram_oflow; logic desc_fifo_uflow; - + logic [DESC_RAM_WIDTH-1:0] desc_dm_desc_ff_out; logic [DESC_WIDTH-1:0] desc_dm_desc_ff_out_from_sav; - + // Pipeline the data into the descriptor RAM always @(posedge clk) if (!rst_n) begin @@ -151,10 +153,10 @@ module sde_desc #(parameter bit H2C_N_C2H = 0, // 1 - H2C, 0 - C2H else ps_desc_wdata_q <= ps_desc_wdata; end - + // PCIS has highest priority for write path assign ps_desc_ack = 1; - + // CSR Path to the Desc RAM always @(posedge clk) if (!rst_n) begin @@ -164,19 +166,19 @@ module sde_desc #(parameter bit H2C_N_C2H = 0, // 1 - H2C, 0 - C2H cfg_desc_ram_wdata_q <= 0; cfg_desc_ram_rd_req_winner_q <= 0; desc_cfg_ram_ack <= 0; - + end else begin - cfg_desc_ram_wr_req_q <= ~cfg_desc_ram_wr_req_q & cfg_desc_ram_wr_req ? 1'b1 : + cfg_desc_ram_wr_req_q <= ~cfg_desc_ram_wr_req_q & cfg_desc_ram_wr_req ? 1'b1 : cfg_desc_ram_wr_req_q & cfg_desc_ram_wr_req_winner ? 1'b0 : cfg_desc_ram_wr_req_q; - - cfg_desc_ram_rd_req_q <= ~cfg_desc_ram_rd_req_q & cfg_desc_ram_rd_req ? 1'b1 : + + cfg_desc_ram_rd_req_q <= ~cfg_desc_ram_rd_req_q & cfg_desc_ram_rd_req ? 1'b1 : cfg_desc_ram_rd_req_q & cfg_desc_ram_rd_req_winner ? 1'b0 : cfg_desc_ram_rd_req_q; cfg_desc_ram_addr_q <= cfg_desc_ram_addr; - + // cfg_desc_ram_wdata_q <= cfg_desc_ram_wdata; if (~DESC_TYPE & H2C_N_C2H) cfg_desc_ram_wdata_q <= h2c_cnv_desc_reg2sav(cfg_desc_ram_wdata); @@ -186,11 +188,11 @@ module sde_desc #(parameter bit H2C_N_C2H = 0, // 1 - H2C, 0 - C2H cfg_desc_ram_wdata_q <= c2h_cnv_desc_reg2sav(cfg_desc_ram_wdata); else if (DESC_TYPE & ~H2C_N_C2H) cfg_desc_ram_wdata_q <= c2h_cnv_desc_comp2sav(cfg_desc_ram_wdata); - else + else cfg_desc_ram_wdata_q <= cfg_desc_ram_wdata; - + cfg_desc_ram_rd_req_winner_q <= cfg_desc_ram_rd_req_winner; - + desc_cfg_ram_ack <= cfg_desc_ram_wr_req_q ? cfg_desc_ram_wr_req_winner : cfg_desc_ram_rd_req_winner_q; @@ -214,15 +216,15 @@ module sde_desc #(parameter bit H2C_N_C2H = 0, // 1 - H2C, 0 - C2H assign desc_ram_wdata = ps_desc_wr_req_q ? ps_desc_wdata_q : cfg_desc_ram_wdata_q; assign cfg_desc_ram_wr_req_winner = cfg_desc_ram_wr_req_q & ~ps_desc_wr_req_q; - + // Arbitrate between cfg read access and pcis reads assign desc_ram_rd = desc_ram_pop || cfg_desc_ram_rd_req_q; - assign desc_ram_raddr = cfg_desc_ram_rd_req_winner ? cfg_desc_ram_addr_q : + assign desc_ram_raddr = cfg_desc_ram_rd_req_winner ? cfg_desc_ram_addr_q : desc_ram_rd_ptr; assign cfg_desc_ram_rd_req_winner = cfg_desc_ram_rd_req_q & ~desc_ram_pop; - + // Desc RAM - Using 2 port RAM (1w1r) - bram_1w1r #(.WIDTH(DESC_RAM_WIDTH), + bram_1w1r #(.WIDTH(DESC_RAM_WIDTH), .ADDR_WIDTH(DESC_ADDR_WIDTH), .DEPTH (DESC_RAM_DEPTH) ) DESC_RAM (.clk (clk), @@ -238,7 +240,7 @@ module sde_desc #(parameter bit H2C_N_C2H = 0, // 1 - H2C, 0 - C2H // FLow-through FIFO logic - need to read 1 desc per clock localparam DESC_RAM_DEPTH_MINUS1 = DESC_RAM_DEPTH - 1; - + ft_fifo #(.FIFO_WIDTH(DESC_RAM_WIDTH) ) DESC_FT_FIFO (.clk (clk), .rst_n (1'b1), @@ -246,7 +248,7 @@ module sde_desc #(parameter bit H2C_N_C2H = 0, // 1 - H2C, 0 - C2H .ram_fifo_empty (desc_ram_empty), .ram_fifo_data (desc_ram_rdata), .ram_pop (desc_ram_pop), - + .ft_pop (dm_desc_pop), .ft_valid (desc_dm_desc_valid), .ft_data (desc_dm_desc_ff_out) @@ -257,19 +259,19 @@ module sde_desc #(parameter bit H2C_N_C2H = 0, // 1 - H2C, 0 - C2H (~DESC_TYPE & ~H2C_N_C2H) ? c2h_cnv_desc_sav2reg(desc_dm_desc_ff_out) : ( DESC_TYPE & ~H2C_N_C2H) ? c2h_cnv_desc_sav2comp(desc_dm_desc_ff_out) : desc_dm_desc_ff_out; - - assign desc_dm_desc = (~DESC_TYPE & H2C_N_C2H) ? sde_pkg::h2c_cnv_desc_reg2comm (desc_dm_desc_ff_out_from_sav) : - ( DESC_TYPE & H2C_N_C2H) ? sde_pkg::h2c_cnv_desc_comp2comm(desc_dm_desc_ff_out_from_sav) : + + assign desc_dm_desc = (~DESC_TYPE & H2C_N_C2H) ? sde_pkg::h2c_cnv_desc_reg2comm (desc_dm_desc_ff_out_from_sav) : + ( DESC_TYPE & H2C_N_C2H) ? sde_pkg::h2c_cnv_desc_comp2comm(desc_dm_desc_ff_out_from_sav) : (~DESC_TYPE & ~H2C_N_C2H) ? sde_pkg::c2h_cnv_desc_reg2comm (desc_dm_desc_ff_out_from_sav) : sde_pkg::c2h_cnv_desc_comp2comm (desc_dm_desc_ff_out_from_sav); - - assign desc_ram_wr_ptr_next = (desc_ram_wr_ptr == DESC_RAM_DEPTH_MINUS1) ? ({DESC_ADDR_WIDTH{1'b0}}) : + + assign desc_ram_wr_ptr_next = (desc_ram_wr_ptr == DESC_RAM_DEPTH_MINUS1) ? ({DESC_ADDR_WIDTH{1'b0}}) : desc_ram_wr_ptr + 1; assign desc_ram_wr_ptr_msb_next = (desc_ram_wr_ptr == DESC_RAM_DEPTH_MINUS1) ? ~desc_ram_wr_ptr_msb : desc_ram_wr_ptr_msb; - + assign desc_ram_rd_ptr_next = (desc_ram_rd_ptr == DESC_RAM_DEPTH_MINUS1) ? ({DESC_ADDR_WIDTH{1'b0}}) : desc_ram_rd_ptr + 1; assign desc_ram_rd_ptr_msb_next = (desc_ram_rd_ptr == DESC_RAM_DEPTH_MINUS1) ? ~desc_ram_rd_ptr_msb : desc_ram_rd_ptr_msb; - + always @(posedge clk) if (!rst_n) begin desc_ram_wr_ptr <= 0; @@ -286,7 +288,7 @@ module sde_desc #(parameter bit H2C_N_C2H = 0, // 1 - H2C, 0 - C2H desc_ram_empty <= ps_desc_wr_req_q && ~desc_ram_pop ? 1'b0 : ~ps_desc_wr_req_q && desc_ram_pop ? ({desc_ram_wr_ptr_msb, desc_ram_wr_ptr} == {desc_ram_rd_ptr_msb_next, desc_ram_rd_ptr_next}) : desc_ram_empty; - desc_ram_full <= ps_desc_wr_req_q && ~desc_ram_pop ? (desc_ram_wr_ptr_msb_next != desc_ram_rd_ptr_msb) && (desc_ram_wr_ptr_next == desc_ram_rd_ptr) : + desc_ram_full <= ps_desc_wr_req_q && ~desc_ram_pop ? (desc_ram_wr_ptr_msb_next != desc_ram_rd_ptr_msb) && (desc_ram_wr_ptr_next == desc_ram_rd_ptr) : ~ps_desc_wr_req_q && desc_ram_pop ? 1'b0 : desc_ram_full; desc_ram_oflow <= desc_ram_full & ps_desc_wr_req_q; desc_fifo_uflow <= ~desc_dm_desc_valid & dm_desc_pop; @@ -295,7 +297,7 @@ module sde_desc #(parameter bit H2C_N_C2H = 0, // 1 - H2C, 0 - C2H assign desc_cfg_uflow = desc_fifo_uflow; assign desc_cfg_empty = ~desc_dm_desc_valid; assign desc_cfg_full = desc_ram_full; - + always_comb begin desc_cfg_wr_ptr = 0; desc_cfg_wr_ptr = desc_ram_wr_ptr; @@ -304,12 +306,12 @@ module sde_desc #(parameter bit H2C_N_C2H = 0, // 1 - H2C, 0 - C2H desc_cfg_rd_ptr = desc_ram_rd_ptr; desc_cfg_rd_ptr[15] = desc_ram_rd_ptr_msb; end - + logic [31:0] cdt_consumed = 0; logic [31:0] cdt_limit = 0; - + // Credit Management - + always @(posedge clk) if (!rst_n) begin cdt_consumed <= 0; @@ -318,18 +320,18 @@ module sde_desc #(parameter bit H2C_N_C2H = 0, // 1 - H2C, 0 - C2H else begin // Consumed // Will be incremented on every write from PCIS - cdt_consumed <= cfg_desc_clr_cdt_consumed ? 0 : + cdt_consumed <= cfg_desc_clr_cdt_consumed ? 0 : ps_desc_wr_req_q ? cdt_consumed + 1 : cdt_consumed; - + // Limit // Will be incremented on every pop of the descriptor from PCIS - cdt_limit <= cfg_desc_clr_cdt_limit ? DESC_RAM_DEPTH : + cdt_limit <= cfg_desc_clr_cdt_limit ? DESC_RAM_DEPTH : dm_desc_pop ? cdt_limit + 1 : cdt_limit; - + end // else: !if(!rst_n) assign desc_cfg_cdt_consumed = cdt_consumed; assign desc_cfg_cdt_limit = cdt_limit; - + logic [31:0] num_compl_desc; // Credit counters always @(posedge clk) @@ -389,13 +391,13 @@ module sde_desc #(parameter bit H2C_N_C2H = 0, // 1 - H2C, 0 - C2H out_desc.dest_addr = in_desc_reg.dest_addr; out_desc.len = in_desc_reg.len; - c2h_cnv_desc_reg2sav = out_desc; + c2h_cnv_desc_reg2sav = out_desc; endfunction // c2h_cnv_desc_reg2sav - + function logic [DESC_WIDTH-1:0] h2c_cnv_desc_sav2reg (input [DESC_RAM_WIDTH-1:0] in_desc); sde_pkg::h2c_reg_desc_t out_desc; sde_pkg::h2c_reg_sav_desc_t in_desc_sav; - + out_desc = '{default:'0}; in_desc_sav = '{default:'0}; @@ -413,7 +415,7 @@ module sde_desc #(parameter bit H2C_N_C2H = 0, // 1 - H2C, 0 - C2H function logic [DESC_WIDTH-1:0] c2h_cnv_desc_sav2reg (input [DESC_RAM_WIDTH-1:0] in_desc); sde_pkg::c2h_reg_desc_t out_desc; sde_pkg::c2h_reg_sav_desc_t in_desc_sav; - + out_desc = '{default:'0}; in_desc_sav = '{default:'0}; @@ -454,13 +456,13 @@ module sde_desc #(parameter bit H2C_N_C2H = 0, // 1 - H2C, 0 - C2H out_desc.dest_addr = in_desc_comp.dest_addr; out_desc.len = in_desc_comp.len; - c2h_cnv_desc_comp2sav = out_desc; + c2h_cnv_desc_comp2sav = out_desc; endfunction // c2h_cnv_desc_comp2sav - + function logic [DESC_WIDTH-1:0] h2c_cnv_desc_sav2comp (input [DESC_RAM_WIDTH-1:0] in_desc); sde_pkg::h2c_comp_desc_t out_desc; sde_pkg::h2c_comp_sav_desc_t in_desc_sav; - + out_desc = '{default:'0}; in_desc_sav = '{default:'0}; @@ -477,7 +479,7 @@ module sde_desc #(parameter bit H2C_N_C2H = 0, // 1 - H2C, 0 - C2H function logic [DESC_WIDTH-1:0] c2h_cnv_desc_sav2comp (input [DESC_RAM_WIDTH-1:0] in_desc); sde_pkg::c2h_comp_desc_t out_desc; sde_pkg::c2h_comp_sav_desc_t in_desc_sav; - + out_desc = '{default:'0}; in_desc_sav = '{default:'0}; @@ -489,17 +491,7 @@ module sde_desc #(parameter bit H2C_N_C2H = 0, // 1 - H2C, 0 - C2H c2h_cnv_desc_sav2comp = out_desc; endfunction // c2h_cnv_desc_sav2comp - - - -endmodule // sde_desc - - - - - - - +endmodule // sde_desc diff --git a/hdk/cl/examples/cl_sde/design/sde_h2c.sv b/hdk/cl/examples/cl_sde/design/sde_h2c.sv index 55af0e3e6..22628b81f 100644 --- a/hdk/cl/examples/cl_sde/design/sde_h2c.sv +++ b/hdk/cl/examples/cl_sde/design/sde_h2c.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016-2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,20 +13,22 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + // H2C Top Level module sde_h2c #(parameter bit H2C_DESC_TYPE = 0, // 0 - Regular, 1 - Compact parameter H2C_DESC_WIDTH = H2C_DESC_TYPE ? 128 : 256, - + parameter H2C_DESC_RAM_DEPTH = 64, - + parameter H2C_PCIM_DM_ARID = 0, // This is the ARID used for write accesses from Data Mover parameter H2C_PCIM_WB_AWID = 1, // This is the AWID used for write accesses from Write Back Block parameter H2C_PCIM_DESC_ARID = 2, // This is the ARID used for read access from the H2C Desc Block parameter PCIM_NUM_OT_RD = 32, // Number of outstanding PCIM reads - + parameter H2C_PCIM_MAX_RD_SIZE = 0, // 0 - 512B, 1 - 1KB, 2 - 2KB, 3 - 4KB parameter PCIM_DATA_WIDTH = 512, @@ -35,7 +38,7 @@ module sde_h2c #(parameter bit H2C_DESC_TYPE = 0, // 0 - Regular, 1 - Compact parameter H2C_AXIS_DATA_WIDTH = 512, parameter H2C_USER_BIT_WIDTH = H2C_DESC_TYPE ? 1 : 64, - + parameter H2C_BUF_DEPTH = 512, parameter H2C_BUF_AUX_DEPTH = 64 @@ -48,7 +51,7 @@ module sde_h2c #(parameter bit H2C_DESC_TYPE = 0, // 0 - Regular, 1 - Compact input h2c_ps_desc_wr_req, input [H2C_DESC_WIDTH-1:0] h2c_ps_desc_wdata, output logic h2c_ps_desc_ack, - + // PCIS to H2C CSR input h2c_ps_cfg_wr_req, input h2c_ps_cfg_rd_req, @@ -81,7 +84,7 @@ module sde_h2c #(parameter bit H2C_DESC_TYPE = 0, // 0 - Regular, 1 - Compact output logic [PCIM_LEN_WIDTH-1:0] h2c_dm_pm_arlen, output logic [PCIM_ID_WIDTH-1:0] h2c_dm_pm_arid, input h2c_pm_dm_arready, - + // Read Data to PCIM input h2c_pm_dm_rvalid, input [1:0] h2c_pm_dm_rresp, @@ -96,7 +99,7 @@ module sde_h2c #(parameter bit H2C_DESC_TYPE = 0, // 0 - Regular, 1 - Compact output logic [PCIM_LEN_WIDTH-1:0] h2c_wb_pm_awlen, output logic [PCIM_ID_WIDTH-1:0] h2c_wb_pm_awid, input h2c_pm_wb_awready, - + // Write Data to PCIM output logic h2c_wb_pm_wvalid, output logic [PCIM_DATA_WIDTH-1:0] h2c_wb_pm_wdata, @@ -123,21 +126,21 @@ module sde_h2c #(parameter bit H2C_DESC_TYPE = 0, // 0 - Regular, 1 - Compact localparam BUF_ADDR_RAM_IDX_WIDTH = $clog2(H2C_BUF_DEPTH); localparam BUF_AUX_RAM_ADDR_WIDTH = $clog2(H2C_BUF_AUX_DEPTH); localparam BUF_ADDR_WIDTH = PCIM_ADDR_BYTE_IDX_WIDTH + BUF_ADDR_RAM_IDX_WIDTH; - + logic desc_dm_empty; logic dm_desc_pop; sde_pkg::comm_desc_t desc_dm_desc; logic desc_dm_desc_valid; logic dm_desc_cnt_inc; - + // Descriptor to Write Back Block logic desc_wb_limit_req; logic [31:0] desc_wb_limit; logic desc_wb_cnt_req; logic [31:0] desc_wb_cnt; - // Data Mover to Buffer + // Data Mover to Buffer // logic [BUF_ADDR_RAM_IDX_WIDTH-1:0] dm_buf_wr_ptr; logic [BUF_ADDR_WIDTH-1:0] dm_buf_wr_byte_addr; logic dm_buf_wr_ptr_msb; @@ -146,7 +149,7 @@ module sde_h2c #(parameter bit H2C_DESC_TYPE = 0, // 0 - Regular, 1 - Compact logic [BUF_AUX_RAM_ADDR_WIDTH-1:0] dm_buf_aux_wr_ptr; logic dm_buf_aux_wr_ptr_msb; logic buf_dm_aux_full; - + logic dm_buf_wr ; logic [PCIM_DATA_WIDTH-1:0] dm_buf_data; logic dm_buf_eop ; @@ -159,10 +162,10 @@ module sde_h2c #(parameter bit H2C_DESC_TYPE = 0, // 0 - Regular, 1 - Compact logic [H2C_USER_BIT_WIDTH-1:0] buf_axis_user; logic buf_axis_last; logic axis_buf_ready; - + logic axis_wb_pkt_cnt_req; logic [31:0] axis_wb_pkt_cnt; - + // Cfg block signals logic cfg_desc_clr_desc_cnt; logic cfg_desc_clr_cdt_limit; @@ -183,17 +186,17 @@ module sde_h2c #(parameter bit H2C_DESC_TYPE = 0, // 0 - Regular, 1 - Compact logic dm_cfg_rresp_err; logic dm_cfg_desc_len_err; - + logic cfg_wb_desc_cdt_en; logic cfg_wb_desc_cnt_en; logic cfg_wb_pkt_cnt_en; logic [47:0] cfg_wb_status_addr; - - logic cfg_wb_desc_error; - logic cfg_wb_dm_error ; + + logic cfg_wb_desc_error; + logic cfg_wb_dm_error ; logic cfg_wb_wb_error ; logic [31:0] wb_cfg_status_dw ; - + logic cfg_desc_cdt_wc_en; logic cfg_desc_cnt_wc_en; logic cfg_pkt_cnt_wc_en; @@ -203,7 +206,7 @@ module sde_h2c #(parameter bit H2C_DESC_TYPE = 0, // 0 - Regular, 1 - Compact logic cfg_axis_clr_pkt_cnt; logic [31:0] axis_cfg_pkt_cnt; - + logic desc_cfg_oflow; logic desc_cfg_uflow; logic desc_cfg_full ; @@ -219,10 +222,10 @@ module sde_h2c #(parameter bit H2C_DESC_TYPE = 0, // 0 - Regular, 1 - Compact logic [15:0] buf_cfg_buf_rd_ptr; logic buf_cfg_aux_fifo_oflow; logic buf_cfg_aux_fifo_uflow; - logic buf_cfg_aux_fifo_full ; + logic buf_cfg_aux_fifo_full ; logic buf_cfg_aux_fifo_empty; logic [15:0] buf_cfg_aux_ram_wr_ptr; - logic [15:0] buf_cfg_aux_ram_rd_ptr; + logic [15:0] buf_cfg_aux_ram_rd_ptr; logic [15:0] buf_cfg_dm_wr_ptr; logic [15:0] buf_cfg_dm_aux_wr_ptr; logic [15:0] buf_cfg_num_free_slots; @@ -234,11 +237,11 @@ module sde_h2c #(parameter bit H2C_DESC_TYPE = 0, // 0 - Regular, 1 - Compact // Generate local copy of Reset logic sync_rst_n; always @(posedge clk) - if (!rst_n) + if (!rst_n) sync_rst_n <= 0; else sync_rst_n <= rst_n; - + // H2C CSR Block sde_h2c_cfg #( .DESC_TYPE (H2C_DESC_TYPE), @@ -248,7 +251,7 @@ module sde_h2c #(parameter bit H2C_DESC_TYPE = 0, // 0 - Regular, 1 - Compact SDE_H2C_CFG (.clk (clk), .rst_n (sync_rst_n), - + .h2c_ps_cfg_wr_req (h2c_ps_cfg_wr_req), .h2c_ps_cfg_rd_req (h2c_ps_cfg_rd_req), .h2c_ps_cfg_addr (h2c_ps_cfg_addr ), @@ -262,20 +265,20 @@ module sde_h2c #(parameter bit H2C_DESC_TYPE = 0, // 0 - Regular, 1 - Compact .cfg_desc_clr_desc_cnt (cfg_desc_clr_desc_cnt ), .cfg_desc_clr_cdt_limit (cfg_desc_clr_cdt_limit ), .cfg_desc_clr_cdt_consumed (cfg_desc_clr_cdt_consumed), - + .desc_cfg_cdt_consumed (desc_cfg_cdt_consumed), .desc_cfg_cdt_limit (desc_cfg_cdt_limit ), .desc_cfg_desc_cnt (desc_cfg_desc_cnt ), .desc_cfg_wr_ptr (desc_cfg_wr_ptr ), .desc_cfg_rd_ptr (desc_cfg_rd_ptr ), - + .cfg_desc_ram_wr_req (cfg_desc_ram_wr_req), .cfg_desc_ram_rd_req (cfg_desc_ram_rd_req), .cfg_desc_ram_addr (cfg_desc_ram_addr ), .cfg_desc_ram_wdata (cfg_desc_ram_wdata ), .desc_cfg_ram_ack (desc_cfg_ram_ack ), .desc_cfg_ram_rdata (desc_cfg_ram_rdata ), - + .desc_cfg_oflow (desc_cfg_oflow), .desc_cfg_uflow (desc_cfg_uflow), .desc_cfg_full (desc_cfg_full ), @@ -283,12 +286,12 @@ module sde_h2c #(parameter bit H2C_DESC_TYPE = 0, // 0 - Regular, 1 - Compact .dm_cfg_rresp_err (dm_cfg_rresp_err), .dm_cfg_desc_len_err (dm_cfg_desc_len_err), - + .cfg_wb_desc_cdt_en (cfg_wb_desc_cdt_en ), .cfg_wb_desc_cnt_en (cfg_wb_desc_cnt_en ), .cfg_wb_pkt_cnt_en (cfg_wb_pkt_cnt_en ), .cfg_wb_status_addr (cfg_wb_status_addr ), - + .cfg_desc_cdt_wc_en (cfg_desc_cdt_wc_en ), .cfg_desc_cnt_wc_en (cfg_desc_cnt_wc_en ), .cfg_pkt_cnt_wc_en (cfg_pkt_cnt_wc_en ), @@ -296,10 +299,10 @@ module sde_h2c #(parameter bit H2C_DESC_TYPE = 0, // 0 - Regular, 1 - Compact .cfg_wc_to_cnt (cfg_wc_to_cnt ), .cfg_wc_cnt_minus1 (cfg_wc_cnt_minus1 ), - .wb_cfg_sts_bresp_err (wb_cfg_sts_bresp_err), + .wb_cfg_sts_bresp_err (wb_cfg_sts_bresp_err), - .cfg_wb_desc_error (cfg_wb_desc_error), - .cfg_wb_dm_error (cfg_wb_dm_error ), + .cfg_wb_desc_error (cfg_wb_desc_error), + .cfg_wb_dm_error (cfg_wb_dm_error ), .cfg_wb_wb_error (cfg_wb_wb_error ), .wb_cfg_status_dw (wb_cfg_status_dw ), @@ -311,10 +314,10 @@ module sde_h2c #(parameter bit H2C_DESC_TYPE = 0, // 0 - Regular, 1 - Compact .buf_cfg_buf_rd_ptr (buf_cfg_buf_rd_ptr ), .buf_cfg_aux_fifo_oflow (buf_cfg_aux_fifo_oflow ), .buf_cfg_aux_fifo_uflow (buf_cfg_aux_fifo_uflow ), - .buf_cfg_aux_fifo_full (buf_cfg_aux_fifo_full ), + .buf_cfg_aux_fifo_full (buf_cfg_aux_fifo_full ), .buf_cfg_aux_fifo_empty (buf_cfg_aux_fifo_empty ), .buf_cfg_aux_ram_wr_ptr (buf_cfg_aux_ram_wr_ptr ), - .buf_cfg_aux_ram_rd_ptr (buf_cfg_aux_ram_rd_ptr ), + .buf_cfg_aux_ram_rd_ptr (buf_cfg_aux_ram_rd_ptr ), .buf_cfg_dm_wr_ptr (buf_cfg_dm_wr_ptr ), .buf_cfg_dm_aux_wr_ptr (buf_cfg_dm_aux_wr_ptr ), .buf_cfg_num_free_slots (buf_cfg_num_free_slots ), @@ -327,41 +330,41 @@ module sde_h2c #(parameter bit H2C_DESC_TYPE = 0, // 0 - Regular, 1 - Compact .axis_cfg_pkt_cnt (axis_cfg_pkt_cnt ) ); - - + + // H2C Descriptor - sde_desc + sde_desc #(.H2C_N_C2H (1), - + .DESC_TYPE (H2C_DESC_TYPE), .DESC_RAM_DEPTH (H2C_DESC_RAM_DEPTH), - + .PCIM_DATA_WIDTH (PCIM_DATA_WIDTH ), .PCIM_ID_WIDTH (PCIM_ID_WIDTH ), .PCIM_LEN_WIDTH (PCIM_LEN_WIDTH ), .PCIM_ADDR_WIDTH (PCIM_ADDR_WIDTH ), .PCIM_DESC_ARID (H2C_PCIM_DESC_ARID) - ) - SDE_H2C_DESC + ) + SDE_H2C_DESC (.clk (clk), .rst_n (sync_rst_n), - + .ps_desc_wr_req (h2c_ps_desc_wr_req), .ps_desc_wdata (h2c_ps_desc_wdata), .ps_desc_ack (h2c_ps_desc_ack), - + .cfg_desc_ram_wr_req (cfg_desc_ram_wr_req), .cfg_desc_ram_rd_req (cfg_desc_ram_rd_req), .cfg_desc_ram_addr (cfg_desc_ram_addr ), .cfg_desc_ram_wdata (cfg_desc_ram_wdata ), .desc_cfg_ram_ack (desc_cfg_ram_ack ), .desc_cfg_ram_rdata (desc_cfg_ram_rdata ), - + .cfg_desc_clr_desc_cnt (cfg_desc_clr_desc_cnt ), .cfg_desc_clr_cdt_limit (cfg_desc_clr_cdt_limit ), .cfg_desc_clr_cdt_consumed (cfg_desc_clr_cdt_consumed), - + .desc_cfg_cdt_consumed (desc_cfg_cdt_consumed), .desc_cfg_cdt_limit (desc_cfg_cdt_limit ), .desc_cfg_desc_cnt (desc_cfg_desc_cnt ), @@ -379,8 +382,8 @@ module sde_h2c #(parameter bit H2C_DESC_TYPE = 0, // 0 - Regular, 1 - Compact .desc_dm_desc_valid (desc_dm_desc_valid), .dm_desc_cnt_inc (dm_desc_cnt_inc), - - .desc_wb_limit_req (desc_wb_limit_req), + + .desc_wb_limit_req (desc_wb_limit_req), .desc_wb_limit (desc_wb_limit), .desc_wb_cnt_req (desc_wb_cnt_req), .desc_wb_cnt (desc_wb_cnt), @@ -389,7 +392,7 @@ module sde_h2c #(parameter bit H2C_DESC_TYPE = 0, // 0 - Regular, 1 - Compact .desc_pm_araddr (h2c_desc_pm_araddr ), .desc_pm_arlen (h2c_desc_pm_arlen ), .pm_desc_arready (h2c_pm_desc_arready), - + .pm_desc_rvalid (h2c_pm_desc_rvalid), .pm_desc_rresp (h2c_pm_desc_rresp ), .pm_desc_rdata (h2c_pm_desc_rdata ), @@ -397,41 +400,41 @@ module sde_h2c #(parameter bit H2C_DESC_TYPE = 0, // 0 - Regular, 1 - Compact .desc_pm_rready (h2c_desc_pm_rready) ); - + // H2C Data Mover - sde_h2c_data + sde_h2c_data #(.DESC_TYPE (H2C_DESC_TYPE), .PCIM_NUM_OT_RD (PCIM_NUM_OT_RD), .PCIM_DM_ARID (H2C_PCIM_DM_ARID), .PCIM_MAX_RD_SIZE (H2C_PCIM_MAX_RD_SIZE), - + .PCIM_DATA_WIDTH (PCIM_DATA_WIDTH ), .PCIM_ID_WIDTH (PCIM_ID_WIDTH ), .PCIM_LEN_WIDTH (PCIM_LEN_WIDTH ), .PCIM_ADDR_WIDTH (PCIM_ADDR_WIDTH ), - + .BUF_DEPTH (H2C_BUF_DEPTH), .BUF_AUX_DEPTH (H2C_BUF_AUX_DEPTH), .USER_BIT_WIDTH (H2C_USER_BIT_WIDTH) ) - SDE_H2C_DATA + SDE_H2C_DATA (.clk (clk), .rst_n (sync_rst_n), - // TODO - CSRs + // TODO - CSRs .dm_cfg_rresp_err (dm_cfg_rresp_err), .dm_cfg_desc_len_err (dm_cfg_desc_len_err), - + .desc_dm_empty (desc_dm_empty), .dm_desc_pop (dm_desc_pop), .desc_dm_desc (desc_dm_desc), .desc_dm_desc_valid (desc_dm_desc_valid), .dm_desc_cnt_inc (dm_desc_cnt_inc), - + .dm_pm_arvalid (h2c_dm_pm_arvalid), .dm_pm_araddr (h2c_dm_pm_araddr ), .dm_pm_arlen (h2c_dm_pm_arlen ), @@ -442,16 +445,16 @@ module sde_h2c #(parameter bit H2C_DESC_TYPE = 0, // 0 - Regular, 1 - Compact .pm_dm_rdata (h2c_pm_dm_rdata ), .pm_dm_rlast (h2c_pm_dm_rlast ), .dm_pm_rready (h2c_dm_pm_rready), - + // .dm_buf_wr_ptr (dm_buf_wr_ptr), .dm_buf_wr_byte_addr (dm_buf_wr_byte_addr), .dm_buf_wr_ptr_msb (dm_buf_wr_ptr_msb), .buf_dm_num_bytes (buf_dm_num_bytes), - + .dm_buf_aux_wr_ptr (dm_buf_aux_wr_ptr), .dm_buf_aux_wr_ptr_msb (dm_buf_aux_wr_ptr_msb), .buf_dm_aux_full (buf_dm_aux_full), - + .dm_buf_wr (dm_buf_wr ), .dm_buf_data (dm_buf_data), .dm_buf_eop (dm_buf_eop ), @@ -467,7 +470,7 @@ module sde_h2c #(parameter bit H2C_DESC_TYPE = 0, // 0 - Regular, 1 - Compact .DESC_RAM_DEPTH (H2C_DESC_RAM_DEPTH), .PCIM_WB_AWID (H2C_PCIM_WB_AWID), - + .PCIM_DATA_WIDTH (PCIM_DATA_WIDTH ), .PCIM_ID_WIDTH (PCIM_ID_WIDTH ), .PCIM_LEN_WIDTH (PCIM_LEN_WIDTH ), @@ -482,11 +485,11 @@ module sde_h2c #(parameter bit H2C_DESC_TYPE = 0, // 0 - Regular, 1 - Compact .cfg_wb_pkt_cnt_en (cfg_wb_pkt_cnt_en), .cfg_wb_md_ptr_en (1'b0), .cfg_wb_status_addr (cfg_wb_status_addr), - + .cfg_desc_clr_desc_cnt (cfg_desc_clr_desc_cnt ), .cfg_desc_clr_cdt_limit (cfg_desc_clr_cdt_limit), .cfg_axis_clr_pkt_cnt (cfg_axis_clr_pkt_cnt), - + .cfg_desc_cdt_wc_en (cfg_desc_cdt_wc_en ), .cfg_desc_cnt_wc_en (cfg_desc_cnt_wc_en ), .cfg_pkt_cnt_wc_en (cfg_pkt_cnt_wc_en ), @@ -494,16 +497,16 @@ module sde_h2c #(parameter bit H2C_DESC_TYPE = 0, // 0 - Regular, 1 - Compact .cfg_wc_tick_cnt (cfg_wc_tick_cnt ), .cfg_wc_to_cnt (cfg_wc_to_cnt ), .cfg_wc_cnt_minus1 (cfg_wc_cnt_minus1 ), - + .wb_cfg_md_bresp_err (), - .wb_cfg_sts_bresp_err (wb_cfg_sts_bresp_err), + .wb_cfg_sts_bresp_err (wb_cfg_sts_bresp_err), - .cfg_wb_desc_error (cfg_wb_desc_error), - .cfg_wb_dm_error (cfg_wb_dm_error ), + .cfg_wb_desc_error (cfg_wb_desc_error), + .cfg_wb_dm_error (cfg_wb_dm_error ), .cfg_wb_wb_error (cfg_wb_wb_error ), .wb_cfg_status_dw (wb_cfg_status_dw ), - .desc_wb_limit_req (desc_wb_limit_req), + .desc_wb_limit_req (desc_wb_limit_req), .desc_wb_limit (desc_wb_limit), .desc_wb_cnt_req (desc_wb_cnt_req), @@ -515,7 +518,7 @@ module sde_h2c #(parameter bit H2C_DESC_TYPE = 0, // 0 - Regular, 1 - Compact .axis_wb_pkt_cnt_req (axis_wb_pkt_cnt_req), .axis_wb_pkt_cnt (axis_wb_pkt_cnt), - + .wb_pm_awvalid (h2c_wb_pm_awvalid), .wb_pm_awaddr (h2c_wb_pm_awaddr ), .wb_pm_awlen (h2c_wb_pm_awlen ), @@ -531,16 +534,16 @@ module sde_h2c #(parameter bit H2C_DESC_TYPE = 0, // 0 - Regular, 1 - Compact .wb_pm_bready (h2c_wb_pm_bready ) ); - + // H2C Buffer sde_h2c_buf #(.DESC_TYPE (H2C_DESC_TYPE), .PCIM_DATA_WIDTH (PCIM_DATA_WIDTH ), - + .BUF_DEPTH (H2C_BUF_DEPTH), .BUF_AUX_DEPTH (H2C_BUF_AUX_DEPTH), - + .USER_BIT_WIDTH (H2C_USER_BIT_WIDTH) ) @@ -556,10 +559,10 @@ module sde_h2c #(parameter bit H2C_DESC_TYPE = 0, // 0 - Regular, 1 - Compact .buf_cfg_buf_rd_ptr (buf_cfg_buf_rd_ptr ), .buf_cfg_aux_fifo_oflow (buf_cfg_aux_fifo_oflow ), .buf_cfg_aux_fifo_uflow (buf_cfg_aux_fifo_uflow ), - .buf_cfg_aux_fifo_full (buf_cfg_aux_fifo_full ), + .buf_cfg_aux_fifo_full (buf_cfg_aux_fifo_full ), .buf_cfg_aux_fifo_empty (buf_cfg_aux_fifo_empty ), .buf_cfg_aux_ram_wr_ptr (buf_cfg_aux_ram_wr_ptr ), - .buf_cfg_aux_ram_rd_ptr (buf_cfg_aux_ram_rd_ptr ), + .buf_cfg_aux_ram_rd_ptr (buf_cfg_aux_ram_rd_ptr ), .buf_cfg_dm_wr_ptr (buf_cfg_dm_wr_ptr ), .buf_cfg_dm_aux_wr_ptr (buf_cfg_dm_aux_wr_ptr ), .buf_cfg_num_free_slots (buf_cfg_num_free_slots ), @@ -567,12 +570,12 @@ module sde_h2c #(parameter bit H2C_DESC_TYPE = 0, // 0 - Regular, 1 - Compact .buf_cfg_out_pkt_cnt (buf_cfg_out_pkt_cnt ), .cfg_buf_clr_in_pkt_cnt (cfg_buf_clr_in_pkt_cnt ), .cfg_buf_clr_out_pkt_cnt (cfg_buf_clr_out_pkt_cnt), - - .buf_axis_valid (buf_axis_valid ), - .buf_axis_data (buf_axis_data ), - .buf_axis_keep (buf_axis_keep ), - .buf_axis_user (buf_axis_user ), - .buf_axis_last (buf_axis_last ), + + .buf_axis_valid (buf_axis_valid ), + .buf_axis_data (buf_axis_data ), + .buf_axis_keep (buf_axis_keep ), + .buf_axis_user (buf_axis_user ), + .buf_axis_last (buf_axis_last ), .axis_buf_ready (axis_buf_ready ), // .dm_buf_wr_ptr (dm_buf_wr_ptr), @@ -591,8 +594,8 @@ module sde_h2c #(parameter bit H2C_DESC_TYPE = 0, // 0 - Regular, 1 - Compact .dm_buf_num_bytes_minus1 (dm_buf_num_bytes_minus1) ); - - + + // H2C AXI-Stream Interface sde_h2c_axis #(.DESC_TYPE (H2C_DESC_TYPE), @@ -609,19 +612,19 @@ module sde_h2c #(parameter bit H2C_DESC_TYPE = 0, // 0 - Regular, 1 - Compact // TODO - CSRs .cfg_axis_clr_pkt_cnt (cfg_axis_clr_pkt_cnt), .axis_cfg_pkt_cnt (axis_cfg_pkt_cnt), - + .h2c_axis_valid (h2c_axis_valid ), - .h2c_axis_data (h2c_axis_data ), - .h2c_axis_keep (h2c_axis_keep ), - .h2c_axis_user (h2c_axis_user ), - .h2c_axis_last (h2c_axis_last ), + .h2c_axis_data (h2c_axis_data ), + .h2c_axis_keep (h2c_axis_keep ), + .h2c_axis_user (h2c_axis_user ), + .h2c_axis_last (h2c_axis_last ), .h2c_axis_ready (h2c_axis_ready ), - - .buf_axis_valid (buf_axis_valid ), - .buf_axis_data (buf_axis_data ), - .buf_axis_keep (buf_axis_keep ), - .buf_axis_user (buf_axis_user ), - .buf_axis_last (buf_axis_last ), + + .buf_axis_valid (buf_axis_valid ), + .buf_axis_data (buf_axis_data ), + .buf_axis_keep (buf_axis_keep ), + .buf_axis_user (buf_axis_user ), + .buf_axis_last (buf_axis_last ), .axis_buf_ready (axis_buf_ready ), .axis_wb_pkt_cnt_req (axis_wb_pkt_cnt_req), diff --git a/hdk/cl/examples/cl_sde/design/sde_h2c_axis.sv b/hdk/cl/examples/cl_sde/design/sde_h2c_axis.sv index dadf0eb54..80d0d0786 100644 --- a/hdk/cl/examples/cl_sde/design/sde_h2c_axis.sv +++ b/hdk/cl/examples/cl_sde/design/sde_h2c_axis.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016-2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ // H2C AXI-Stream Interface @@ -20,7 +22,7 @@ module sde_h2c_axis #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact parameter PCIM_DATA_WIDTH = 512, parameter AXIS_DATA_WIDTH = 512, - + parameter USER_BIT_WIDTH = DESC_TYPE ? 1 : 64 ) @@ -38,7 +40,7 @@ module sde_h2c_axis #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact output logic [USER_BIT_WIDTH-1:0] h2c_axis_user, output logic h2c_axis_last, input h2c_axis_ready, - + // AXI-S Interface to Buf input buf_axis_valid, input [PCIM_DATA_WIDTH-1:0] buf_axis_data, @@ -50,10 +52,10 @@ module sde_h2c_axis #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact // AXI-S Interface to Write Back block for packet Count Update output logic axis_wb_pkt_cnt_req, output logic [31:0] axis_wb_pkt_cnt - - + + ); - + // Do any width conversoin necessary @@ -75,14 +77,12 @@ module sde_h2c_axis #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact end else begin axis_wb_pkt_cnt_req <= h2c_axis_valid & h2c_axis_ready & h2c_axis_last; - axis_pkt_cnt <= cfg_axis_clr_pkt_cnt ? 0 : + axis_pkt_cnt <= cfg_axis_clr_pkt_cnt ? 0 : h2c_axis_valid & h2c_axis_ready & h2c_axis_last ? axis_pkt_cnt + 1 : axis_pkt_cnt; end - + assign axis_wb_pkt_cnt = axis_pkt_cnt; assign axis_cfg_pkt_cnt = axis_pkt_cnt; endmodule // sde_h2c_axis - - diff --git a/hdk/cl/examples/cl_sde/design/sde_h2c_buf.sv b/hdk/cl/examples/cl_sde/design/sde_h2c_buf.sv index 6abe90a64..df728c2c4 100644 --- a/hdk/cl/examples/cl_sde/design/sde_h2c_buf.sv +++ b/hdk/cl/examples/cl_sde/design/sde_h2c_buf.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016-2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,11 +13,13 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + // H2C Buffer module sde_h2c_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact - + parameter PCIM_DATA_WIDTH = 512, parameter PCIM_ADDR_BYTE_IDX_WIDTH = $clog2(PCIM_DATA_WIDTH>>3), @@ -28,7 +31,7 @@ module sde_h2c_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact parameter BUF_AUX_RAM_ADDR_WIDTH = $clog2(BUF_AUX_DEPTH), parameter USER_BIT_WIDTH = DESC_TYPE ? 1 : 64, - + // These are internal FIFOs - Dont change unless absolutely required parameter OP_OUTPUT_FIFO_DEPTH = 3 @@ -47,10 +50,10 @@ module sde_h2c_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact output logic [15:0] buf_cfg_buf_rd_ptr, output logic buf_cfg_aux_fifo_oflow, output logic buf_cfg_aux_fifo_uflow, - output logic buf_cfg_aux_fifo_full , + output logic buf_cfg_aux_fifo_full , output logic buf_cfg_aux_fifo_empty, output logic [15:0] buf_cfg_aux_ram_wr_ptr, - output logic [15:0] buf_cfg_aux_ram_rd_ptr, + output logic [15:0] buf_cfg_aux_ram_rd_ptr, output logic [15:0] buf_cfg_dm_wr_ptr, output logic [15:0] buf_cfg_dm_aux_wr_ptr, output logic [15:0] buf_cfg_num_free_slots, @@ -58,7 +61,7 @@ module sde_h2c_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact output logic [31:0] buf_cfg_out_pkt_cnt, input cfg_buf_clr_in_pkt_cnt, input cfg_buf_clr_out_pkt_cnt, - + // AXI-S Interface to Buf output logic buf_axis_valid, output logic [PCIM_DATA_WIDTH-1:0] buf_axis_data, @@ -66,8 +69,8 @@ module sde_h2c_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact output logic [USER_BIT_WIDTH-1:0] buf_axis_user, output logic buf_axis_last, input axis_buf_ready, - - + + // Buf to Data Mover // input logic [BUF_ADDR_RAM_IDX_WIDTH-1:0] dm_buf_wr_ptr, input logic [BUF_ADDR_WIDTH-1:0] dm_buf_wr_byte_addr, @@ -91,7 +94,7 @@ module sde_h2c_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact localparam BUF_SIZE_BYTES = BUF_DEPTH * (PCIM_DATA_WIDTH>>3); localparam BUF_DEPTH_MINUS1 = BUF_DEPTH - 1; localparam BUF_RAM_ADDR_WIDTH = BUF_ADDR_RAM_IDX_WIDTH; - + logic buf_wr_en; logic buf_rd_en; logic [BUF_ADDR_RAM_IDX_WIDTH-1:0] buf_wr_ptr; @@ -106,18 +109,18 @@ module sde_h2c_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact logic buf_full; logic buf_uflow; logic buf_oflow; - + assign buf_wr_en = dm_buf_wr; - + // Manage read and write addresses - assign buf_wr_ptr_next = (buf_wr_ptr == BUF_DEPTH_MINUS1) ? ({BUF_ADDR_RAM_IDX_WIDTH{1'b0}}) : + assign buf_wr_ptr_next = (buf_wr_ptr == BUF_DEPTH_MINUS1) ? ({BUF_ADDR_RAM_IDX_WIDTH{1'b0}}) : buf_wr_ptr + 1; assign buf_wr_ptr_msb_next = (buf_wr_ptr == BUF_DEPTH_MINUS1) ? ~buf_wr_ptr_msb : buf_wr_ptr_msb; - - assign buf_rd_ptr_next = (buf_rd_ptr == BUF_DEPTH_MINUS1) ? ({BUF_ADDR_RAM_IDX_WIDTH{1'b0}}) : + + assign buf_rd_ptr_next = (buf_rd_ptr == BUF_DEPTH_MINUS1) ? ({BUF_ADDR_RAM_IDX_WIDTH{1'b0}}) : buf_rd_ptr + 1; assign buf_rd_ptr_msb_next = (buf_rd_ptr == BUF_DEPTH_MINUS1) ? ~buf_rd_ptr_msb : buf_rd_ptr_msb; - + always @(posedge clk) if (!rst_n) begin buf_wr_ptr <= 0; @@ -160,7 +163,7 @@ module sde_h2c_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact logic buf_ram_rd; logic [BUF_ADDR_RAM_IDX_WIDTH-1:0] buf_ram_raddr; logic [PCIM_DATA_WIDTH-1:0] buf_ram_rdata; - + // Buffer BRAM assign buf_ram_wr = buf_wr_en; assign buf_ram_waddr = buf_wr_ptr; @@ -168,9 +171,9 @@ module sde_h2c_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact assign buf_ram_rd = buf_rd_en; assign buf_ram_raddr = buf_rd_ptr; - + // Desc RAM - Using 2 port RAM (1w1r) - bram_1w1r #(.WIDTH(PCIM_DATA_WIDTH), + bram_1w1r #(.WIDTH(PCIM_DATA_WIDTH), .ADDR_WIDTH(BUF_RAM_ADDR_WIDTH), .DEPTH(BUF_DEPTH) ) BUF_RAM (.clk (clk), @@ -201,7 +204,7 @@ module sde_h2c_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact logic aux_ram_pop; logic aux_ram_oflow; logic aux_fifo_uflow; - + logic aux_ft_ff_pop; logic aux_ft_ff_valid; logic [BUF_AUX_RAM_WIDTH-1:0] aux_ft_ff_data; @@ -217,18 +220,18 @@ module sde_h2c_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact logic [BUF_ADDR_RAM_IDX_WIDTH-1:0] aux_out_eop_wr_ptr; logic [PCIM_ADDR_BYTE_IDX_WIDTH-1:0] aux_out_num_bytes_minus1; logic aux_out_valid; - + logic op_stall; - - // AUX FT FIFO + + // AUX FT FIFO assign aux_ram_wr = buf_wr_en & dm_buf_eop; assign aux_ram_waddr = aux_ram_wr_ptr; - assign aux_ram_wdata = DESC_TYPE ? {buf_wr_ptr, dm_buf_num_bytes_minus1} : + assign aux_ram_wdata = DESC_TYPE ? {buf_wr_ptr, dm_buf_num_bytes_minus1} : {dm_buf_user, buf_wr_ptr, dm_buf_num_bytes_minus1}; assign aux_ram_rd = aux_ram_pop; assign aux_ram_raddr = aux_ram_rd_ptr; - + // AUX RAM bram_1w1r #(.WIDTH(BUF_AUX_RAM_WIDTH), .ADDR_WIDTH(BUF_AUX_RAM_ADDR_WIDTH), @@ -238,13 +241,13 @@ module sde_h2c_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact .ena (aux_ram_wr), .addra (aux_ram_waddr), .da (aux_ram_wdata), - + .enb (aux_ram_rd), .addrb (aux_ram_raddr), .qb (aux_ram_rdata) ); - // Flow-through FIFO + // Flow-through FIFO ft_fifo #(.FIFO_WIDTH(BUF_AUX_RAM_WIDTH) ) AUX_FT_FIFO (.clk (clk), .rst_n (1'b1), @@ -252,7 +255,7 @@ module sde_h2c_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact .ram_fifo_empty (aux_ram_empty), .ram_fifo_data (aux_ram_rdata), .ram_pop (aux_ram_pop), - + .ft_pop (aux_ft_ff_pop), .ft_valid (aux_ft_ff_valid), .ft_data (aux_ft_ff_data) @@ -261,11 +264,11 @@ module sde_h2c_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact assign aux_ram_wr_ptr_next = (aux_ram_wr_ptr == BUF_AUX_RAM_DEPTH_MINUS1) ? ({BUF_AUX_RAM_ADDR_WIDTH{1'b0}}) : aux_ram_wr_ptr + 1; assign aux_ram_wr_ptr_msb_next = (aux_ram_wr_ptr == BUF_AUX_RAM_DEPTH_MINUS1) ? ~aux_ram_wr_ptr_msb : aux_ram_wr_ptr_msb; - + assign aux_ram_rd_ptr_next = (aux_ram_rd_ptr == BUF_AUX_RAM_DEPTH_MINUS1) ? ({BUF_AUX_RAM_ADDR_WIDTH{1'b0}}) : aux_ram_rd_ptr + 1; assign aux_ram_rd_ptr_msb_next = (aux_ram_rd_ptr == BUF_AUX_RAM_DEPTH_MINUS1) ? ~aux_ram_rd_ptr_msb : aux_ram_rd_ptr_msb; - + always @(posedge clk) if (!rst_n) begin aux_ram_wr_ptr <= 0; @@ -286,7 +289,7 @@ module sde_h2c_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact aux_ram_full <= ~aux_ram_wr && aux_ram_pop ? 1'b0 : aux_ram_wr && ~aux_ram_pop ? (aux_ram_wr_ptr_msb_next != aux_ram_rd_ptr_msb) && (aux_ram_wr_ptr_next == aux_ram_rd_ptr) : aux_ram_full; - + aux_ram_oflow <= aux_ram_full & aux_ram_wr; aux_fifo_uflow <= ~aux_ft_ff_valid & aux_ft_ff_pop; end // else: !if(!rst_n) @@ -300,7 +303,7 @@ module sde_h2c_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact buf_cfg_aux_ram_wr_ptr = 0; buf_cfg_aux_ram_wr_ptr = aux_ram_wr_ptr; buf_cfg_aux_ram_wr_ptr[15] = aux_ram_wr_ptr_msb; - + buf_cfg_aux_ram_rd_ptr = 0; buf_cfg_aux_ram_rd_ptr = aux_ram_rd_ptr; buf_cfg_aux_ram_rd_ptr[15] = aux_ram_rd_ptr_msb; @@ -310,7 +313,7 @@ module sde_h2c_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact aux_out_eop_wr_ptr, aux_out_num_bytes_minus1} = aux_ft_ff_data; assign aux_out_valid = aux_ft_ff_valid; - + // Output Pipeline // Stage 0 // Read data from Buffer when buffer is not empty and no output stall @@ -320,7 +323,7 @@ module sde_h2c_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact logic [BUF_ADDR_RAM_IDX_WIDTH-1:0] stg0_op_buf_rd_addr; logic pl0_op_valid; logic [BUF_ADDR_RAM_IDX_WIDTH-1:0] pl0_op_buf_rd_addr; - + assign stg0_op_valid = buf_rd_en; assign stg0_op_buf_rd_addr = buf_rd_ptr; @@ -348,7 +351,7 @@ module sde_h2c_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact logic pl1_op_ovf; logic [PCIM_DATA_WIDTH-1:0] pl1_op_ovf_data; logic [BUF_ADDR_RAM_IDX_WIDTH-1:0] pl1_op_ovf_buf_rd_addr; - + assign stg1_op_valid = pl0_op_valid || pl1_op_ovf; assign stg1_op_data = pl1_op_ovf ? pl1_op_ovf_data : buf_ram_rdata; assign stg1_op_buf_rd_addr = pl1_op_ovf ? pl1_op_ovf_buf_rd_addr : pl0_op_buf_rd_addr; @@ -357,7 +360,7 @@ module sde_h2c_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact ~op_stall ? 1'b0 : pl1_op_ovf; assign stg1_op_ovf_data = pl0_op_valid & op_stall ? buf_ram_rdata : pl1_op_ovf_data; assign stg1_op_ovf_buf_rd_addr = pl0_op_valid & op_stall ? pl0_op_buf_rd_addr : pl1_op_ovf_buf_rd_addr; - + always @(posedge clk) if (!rst_n) begin pl1_op_valid <= 0; @@ -403,7 +406,7 @@ module sde_h2c_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact stg2_op_keep_last[byte_idx] = 1; end assign stg2_op_keep = stg2_op_eop ? stg2_op_keep_last : ({PCIM_DATA_WIDTH_BYTES{1'b1}}); - + assign aux_ft_ff_pop = aux_ft_ff_valid & stg2_op_valid & stg2_op_eop & ~op_stall; always @(posedge clk) @@ -423,21 +426,21 @@ module sde_h2c_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact end // else: !if(!rst_n) // Output FIFO - localparam OP_OUTPUT_FIFO_WIDTH = DESC_TYPE ? PCIM_DATA_WIDTH + 1 + PCIM_DATA_WIDTH_BYTES : + localparam OP_OUTPUT_FIFO_WIDTH = DESC_TYPE ? PCIM_DATA_WIDTH + 1 + PCIM_DATA_WIDTH_BYTES : PCIM_DATA_WIDTH + 1 + PCIM_DATA_WIDTH_BYTES + USER_BIT_WIDTH; localparam OP_OUTPUT_FIFO_DEPTH_MINUS1 = OP_OUTPUT_FIFO_DEPTH - 1; - + logic op_out_ff_push; logic [OP_OUTPUT_FIFO_WIDTH-1:0] op_out_ff_push_data; logic op_out_ff_pop; logic [OP_OUTPUT_FIFO_WIDTH-1:0] op_out_ff_pop_data; logic op_out_ff_full; logic op_out_ff_valid; - + assign op_out_ff_push = pl2_op_valid & ~op_stall; assign op_out_ff_push_data = DESC_TYPE ? {pl2_op_data, pl2_op_eop, pl2_op_keep} : {pl2_op_user, pl2_op_data, pl2_op_eop, pl2_op_keep}; - + flop_fifo #(.WIDTH(OP_OUTPUT_FIFO_WIDTH), .DEPTH(OP_OUTPUT_FIFO_DEPTH) ) OP_OUTPUT_FIFO (.clk (clk), @@ -463,7 +466,7 @@ module sde_h2c_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact {buf_axis_data, buf_axis_last, buf_axis_keep} = op_out_ff_pop_data; else {buf_axis_user, buf_axis_data, buf_axis_last, buf_axis_keep} = op_out_ff_pop_data; - + // Logic to compute num_bytes for dm // Difference between dm_buf_wr_byte_addr and buf_rd_ptr logic [BUF_ADDR_RAM_IDX_WIDTH-1:0] buf_wr_ptr_in; @@ -488,15 +491,15 @@ module sde_h2c_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact assign buf_ptr_eq = (buf_wr_ptr_in == buf_rd_ptr); assign buf_ptr_msb_eq = (buf_wr_ptr_msb_in == buf_rd_ptr_msb); - - // When pointers are not equal, for example - + + // When pointers are not equal, for example - // For case where rd_ptr is greater than wr_ptr, the actual ptr difference is // ptr_diff = rd_ptr - wr_ptr. // But the wr_ptr will not move even if the data mover writes less than 0x40 bytes. // Say, if the wr_byte_addr is at 0x10, the number of free bytes is equal to 0x30. // But the logic will report 0x40 with above logic. Therefore, subtracting by 1 to be safe. // ptr_diff = rd_ptr - wr_ptr - 1 - // When this is done, if the wr_byte_addr is 0x10, the number of free bytes reported will be 0x0 + // When this is done, if the wr_byte_addr is 0x10, the number of free bytes reported will be 0x0 assign buf_free_slots = buf_ptr_eq & buf_ptr_msb_eq ? BUF_DEPTH_MINUS1 : buf_ptr_eq & ~buf_ptr_msb_eq ? 0 : buf_ptr_diff - 1; @@ -507,7 +510,7 @@ module sde_h2c_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact logic [BUF_ADDR_WIDTH-1:0] buf_rd_byte_addr; logic [BUF_ADDR_WIDTH:0] buf_rd_byte_addr_plus_depth; logic [BUF_ADDR_WIDTH:0] buf_byte_addr_diff; - + assign buf_wr_byte_addr = dm_buf_wr_byte_addr; assign buf_rd_byte_addr = {buf_rd_ptr, {PCIM_ADDR_BYTE_IDX_WIDTH{1'b0}}}; assign buf_rd_byte_addr_plus_depth = {buf_rd_ptr_plus_depth, {PCIM_ADDR_BYTE_IDX_WIDTH{1'b0}}}; @@ -516,7 +519,7 @@ module sde_h2c_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact assign buf_dm_num_bytes = (buf_wr_byte_addr == buf_rd_byte_addr) & buf_ptr_msb_eq ? BUF_SIZE_BYTES : (buf_wr_byte_addr == buf_rd_byte_addr) & ~buf_ptr_msb_eq ? 0 : buf_byte_addr_diff; - + // Logic to compute aux fifo full assign buf_dm_aux_full = (dm_buf_aux_wr_ptr == aux_ram_rd_ptr) && (dm_buf_aux_wr_ptr_msb != aux_ram_rd_ptr_msb); @@ -540,22 +543,22 @@ module sde_h2c_buf #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact buf_cfg_num_free_slots = 0; buf_cfg_num_free_slots = buf_free_slots_q; end // always_comb - + always @(posedge clk) if (!rst_n) begin buf_cfg_in_pkt_cnt <= 0; buf_cfg_out_pkt_cnt <= 0; end else begin - buf_cfg_in_pkt_cnt <= cfg_buf_clr_in_pkt_cnt ? 0 : + buf_cfg_in_pkt_cnt <= cfg_buf_clr_in_pkt_cnt ? 0 : dm_buf_wr & dm_buf_eop ? buf_cfg_in_pkt_cnt + 1 : buf_cfg_in_pkt_cnt; buf_cfg_out_pkt_cnt <= cfg_buf_clr_out_pkt_cnt ? 0 : buf_axis_valid & buf_axis_last & axis_buf_ready ? buf_cfg_out_pkt_cnt + 1 : buf_cfg_out_pkt_cnt; end // else: !if(!rst_n) `ifndef NO_SDE_DEBUG_ILA - - + + ila_sde_h2c_buf ILA_SDE_H2C_BUF ( .clk (clk), @@ -590,7 +593,7 @@ ila_sde_h2c_buf ILA_SDE_H2C_BUF .probe22(aux_ram_rd_ptr_msb), .probe23(op_out_ff_full), - // 24 - 31 + // 24 - 31 .probe24(op_out_ff_valid), .probe25(buf_wr_ptr_in_plus_depth), .probe26(buf_rd_ptr_plus_depth), @@ -600,5 +603,5 @@ ila_sde_h2c_buf ILA_SDE_H2C_BUF ); `endif // `ifndef NO_SDE_DEBUG_ILA - + endmodule // sde_h2c_buf diff --git a/hdk/cl/examples/cl_sde/design/sde_h2c_cfg.sv b/hdk/cl/examples/cl_sde/design/sde_h2c_cfg.sv index 33521ccf7..e4b4056a0 100644 --- a/hdk/cl/examples/cl_sde/design/sde_h2c_cfg.sv +++ b/hdk/cl/examples/cl_sde/design/sde_h2c_cfg.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016-2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + // H2C Config Access @@ -33,7 +36,7 @@ module sde_h2c_cfg #(parameter bit DESC_TYPE = 0, input desc_ooo_error, input desc_unalin_error, - + // Config to Desc output logic cfg_desc_clr_cdt_consumed, output logic cfg_desc_clr_cdt_limit, @@ -45,7 +48,7 @@ module sde_h2c_cfg #(parameter bit DESC_TYPE = 0, output logic [19:0] cfg_wc_tick_cnt, output logic [3:0] cfg_wc_to_cnt, output logic [5:0] cfg_wc_cnt_minus1, - + input [31:0] desc_cfg_cdt_consumed, input [31:0] desc_cfg_cdt_limit, input [31:0] desc_cfg_desc_cnt, @@ -66,19 +69,19 @@ module sde_h2c_cfg #(parameter bit DESC_TYPE = 0, input dm_cfg_rresp_err, input dm_cfg_desc_len_err, - + output logic cfg_wb_desc_cdt_en, output logic cfg_wb_desc_cnt_en, output logic cfg_wb_pkt_cnt_en, output logic [47:0] cfg_wb_status_addr, - + input wb_cfg_sts_bresp_err, - output logic cfg_wb_desc_error, - output logic cfg_wb_dm_error, + output logic cfg_wb_desc_error, + output logic cfg_wb_dm_error, output logic cfg_wb_wb_error, input [31:0] wb_cfg_status_dw, - + // Config Buf input buf_cfg_buf_oflow, input buf_cfg_buf_uflow, @@ -88,10 +91,10 @@ module sde_h2c_cfg #(parameter bit DESC_TYPE = 0, input [15:0] buf_cfg_buf_rd_ptr, input buf_cfg_aux_fifo_oflow, input buf_cfg_aux_fifo_uflow, - input buf_cfg_aux_fifo_full , + input buf_cfg_aux_fifo_full , input buf_cfg_aux_fifo_empty, input [15:0] buf_cfg_aux_ram_wr_ptr, - input [15:0] buf_cfg_aux_ram_rd_ptr, + input [15:0] buf_cfg_aux_ram_rd_ptr, input [15:0] buf_cfg_dm_wr_ptr, input [15:0] buf_cfg_dm_aux_wr_ptr, input [15:0] buf_cfg_num_free_slots, @@ -106,14 +109,14 @@ module sde_h2c_cfg #(parameter bit DESC_TYPE = 0, localparam DESC_WIDTH_DW = DESC_WIDTH >> 5; localparam DESC_WIDTH_DW_MINUS1 = DESC_WIDTH_DW - 1; - + // Address range is 1.5KB (0x000 - 0x600) - + ///////////////////////////////////////////////// // H2C Global Control and Status (0x0000 - 0x00FC) ///////////////////////////////////////////////// // No registers yet - + ///////////////////////////////////////////////// // Desc Config and Status (0x0100 - 0x01FC) ///////////////////////////////////////////////// @@ -133,9 +136,9 @@ module sde_h2c_cfg #(parameter bit DESC_TYPE = 0, // 0x10 : Desc Address Registers (RW) // 15:0 - Desc RAM Address (RW) // 31:16 - Desc DW Index (W0C) (Auto increment) - + // 0x14 : Desc Read/Write Data (RW) - + // 0x18 : Desc Status // 0 - Desc Overflow (RW1C) // 1 - Desc Out of Order Error (RW1C) @@ -148,7 +151,7 @@ module sde_h2c_cfg #(parameter bit DESC_TYPE = 0, // 0 - Descriptor Type (0 - Regular, 1 - Compact) (RO) // 15:1 - RSVD // 31:16 - Descriptor RAM Depth (Maximum number of descriptors) (RO) - + ///////////////////////////////////////////////// // Data Mover Config and Status (0x0200 - 0x02FC) ///////////////////////////////////////////////// @@ -159,7 +162,7 @@ module sde_h2c_cfg #(parameter bit DESC_TYPE = 0, // 0 - RRESP Error (RW1C) // 1 - Descriptor length Error (RW1C) // 31:2 - RSVD - + ///////////////////////////////////////////////// // Write Back Config and Status (0x0300 - 0x34FC) ///////////////////////////////////////////////// @@ -174,7 +177,7 @@ module sde_h2c_cfg #(parameter bit DESC_TYPE = 0, // 7 - RSVD // 13:8 - Write-Back Coalescing Count Minus 1 // 31:14 - RSVD - + // 0x04 : Status Write-Back Address Low (RW) // 0x08 : Status Write-back Address High (RW) @@ -187,13 +190,13 @@ module sde_h2c_cfg #(parameter bit DESC_TYPE = 0, // 0x10 : Write Back Status Register // 0 - BRESP Error for Status Write // 31:1 - RSVD - + // 0x14 : Status DW // 0 - Desc Error // 1 - Data Mover Error // 2 - Write-Back Error // 31:3 - RSVD - + ///////////////////////////////////////////////// // Buffer & SPB Config and Status (0x0400 - 0x04FC) ///////////////////////////////////////////////// @@ -201,12 +204,12 @@ module sde_h2c_cfg #(parameter bit DESC_TYPE = 0, // 31:0 - RSVD (RW) // 0x04 : Buf Status - // 0 - Buffer Full (RO) - // 1 - Buffer Empty (RO) - // 2 - Aux FIFO Full (RO) + // 0 - Buffer Full (RO) + // 1 - Buffer Empty (RO) + // 2 - Aux FIFO Full (RO) // 3 - Aux FIFO Valid (RO) // 31:4 - RSVD - + // 0x08 : Input Packet Count (RW0C) // 0x0C : Ouput Packet Count (RW0C) @@ -224,18 +227,18 @@ module sde_h2c_cfg #(parameter bit DESC_TYPE = 0, // 0x18 : Number of Bytes // 15:0 - Buffer Number of Free Entries (RO) // 31:16 - RSVD - + // 0x1C : Data Mover In Buffer Pointers (RO) // 14:0 - Buffer Write Pointer // 15 - Buffer Write Pointer MSB // 30:16 - Aux FIFO Write Pointer // 31 - Aux FIFO Write Pointer MSB - + ///////////////////////////////////////////////// // AXIS Config and Status (0x0500 - 0x05FC) ///////////////////////////////////////////////// // 0x00 : Packet Count (RW0C) - + logic cfg_wr_q; logic cfg_rd_q; logic cfg_wr_re; @@ -261,7 +264,7 @@ module sde_h2c_cfg #(parameter bit DESC_TYPE = 0, logic [31:0] rdata_range_4; logic [31:0] rdata_range_5; - + always @(posedge clk) if (!rst_n) begin cfg_wr_q <= 0; @@ -275,7 +278,7 @@ module sde_h2c_cfg #(parameter bit DESC_TYPE = 0, assign cfg_rd_re = ~cfg_rd_q & h2c_ps_cfg_rd_req; assign cfg_wr_fe = cfg_wr_q & ~h2c_ps_cfg_wr_req; assign cfg_rd_fe = cfg_rd_q & ~h2c_ps_cfg_rd_req; - + // Decode Address ranges assign dec_range_0 = (h2c_ps_cfg_addr >= 16'h0000) & (h2c_ps_cfg_addr < 16'h0100); assign dec_range_1 = (h2c_ps_cfg_addr >= 16'h0100) & (h2c_ps_cfg_addr < 16'h0200); @@ -283,7 +286,7 @@ module sde_h2c_cfg #(parameter bit DESC_TYPE = 0, assign dec_range_3 = (h2c_ps_cfg_addr >= 16'h0300) & (h2c_ps_cfg_addr < 16'h0400); assign dec_range_4 = (h2c_ps_cfg_addr >= 16'h0400) & (h2c_ps_cfg_addr < 16'h0500); assign dec_range_5 = (h2c_ps_cfg_addr >= 16'h0500) & (h2c_ps_cfg_addr < 16'h0600); - + always @(posedge clk) if (!rst_n) begin h2c_ps_cfg_ack <= 0; @@ -296,7 +299,7 @@ module sde_h2c_cfg #(parameter bit DESC_TYPE = 0, dec_range_3 ? ack_range_3 : dec_range_4 ? ack_range_4 : dec_range_5 ? ack_range_5 : 1'b1); - + h2c_ps_cfg_rdata <= dec_range_0 ? rdata_range_0 : dec_range_1 ? rdata_range_1 : dec_range_2 ? rdata_range_2 : @@ -304,20 +307,20 @@ module sde_h2c_cfg #(parameter bit DESC_TYPE = 0, dec_range_4 ? rdata_range_4 : dec_range_5 ? rdata_range_5 : 32'hbaad_3600; end // else: !if(!rst_n) - + ///////////////////////////////////////////////// // Range 0 (0x0000 - 0x00FC) ///////////////////////////////////////////////// // TODO: No registers in this range yet assign ack_range_0 = 1; assign rdata_range_0 = 32'hbaad_3000; - + ///////////////////////////////////////////////// // Range 1 (0x0100 - 0x01FC) ///////////////////////////////////////////////// logic ack_wr_range_1; logic ack_rd_range_1; - + logic clr_desc_ram_idx; logic inc_desc_ram_idx_wr; logic inc_desc_ram_idx_rd; @@ -352,7 +355,7 @@ module sde_h2c_cfg #(parameter bit DESC_TYPE = 0, end else if (h2c_ps_cfg_wr_req & dec_range_1) begin ack_wr_range_1 <= 0; - case (h2c_ps_cfg_addr[7:0]) + case (h2c_ps_cfg_addr[7:0]) 8'h10 : begin ack_wr_range_1 <= 1; cfg_desc_ram_addr <= h2c_ps_cfg_wdata; @@ -438,19 +441,19 @@ module sde_h2c_cfg #(parameter bit DESC_TYPE = 0, assign inc_desc_ram_idx_rd = cfg_rd_fe & dec_range_1 & (h2c_ps_cfg_addr[7:0] == 8'h14); assign inc_desc_ram_idx = cfg_rd_q ? inc_desc_ram_idx_rd : inc_desc_ram_idx_wr; - always @(posedge clk) + always @(posedge clk) if (!rst_n) begin desc_ram_idx <= 4'd0; cfg_desc_ram_rd_dw <= 32'd0; cfg_desc_ram_data_q <= '{default:'0}; - + cfg_desc_ram_wr_ack <= 0; cfg_desc_ram_rd_ack <= 0; cfg_desc_ram_rd_ack_q <= 0; - + cfg_desc_ram_addr_reg_wr <= 0; cfg_desc_ram_data_reg_wr <= 0; - + cfg_desc_ram_data_reg_wr_last <= 0; cfg_desc_ram_wr_req <= 0; cfg_desc_ram_rd_req <= 0; @@ -461,32 +464,32 @@ module sde_h2c_cfg #(parameter bit DESC_TYPE = 0, inc_desc_ram_idx ? desc_ram_idx + 4'd1 : desc_ram_idx; for (int dw_idx = 0; dw_idx < DESC_WIDTH_DW; dw_idx++) - if (desc_ram_idx == dw_idx) + if (desc_ram_idx == dw_idx) cfg_desc_ram_rd_dw <= cfg_desc_ram_data_q[32*dw_idx +: 32]; - + if (desc_cfg_ram_ack) cfg_desc_ram_data_q <= desc_cfg_ram_rdata; - else + else for (int dw_idx = 0; dw_idx < DESC_WIDTH_DW; dw_idx++) - if (desc_ram_idx == dw_idx) + if (desc_ram_idx == dw_idx) cfg_desc_ram_data_q[32*dw_idx +: 32] <= cfg_desc_ram_data_reg_wr ? cfg_desc_ram_wr_dw : cfg_desc_ram_data_q[32*dw_idx +: 32]; - - + + cfg_desc_ram_wr_ack <= (desc_ram_idx == DESC_WIDTH_DW_MINUS1) ? desc_cfg_ram_ack : 1'b1; cfg_desc_ram_rd_ack <= (desc_ram_idx == 0) ? desc_cfg_ram_ack : 1'b1; cfg_desc_ram_rd_ack_q <= cfg_desc_ram_rd_ack; - + cfg_desc_ram_addr_reg_wr <= cfg_wr_re & dec_range_1 & (h2c_ps_cfg_addr[7:0] == 8'h10); cfg_desc_ram_data_reg_wr <= cfg_wr_re & dec_range_1 & (h2c_ps_cfg_addr[7:0] == 8'h14); - + cfg_desc_ram_data_reg_wr_last <= cfg_wr_re & dec_range_1 & (h2c_ps_cfg_addr[7:0] == 8'h14) & (desc_ram_idx == DESC_WIDTH_DW_MINUS1); cfg_desc_ram_wr_req <= cfg_desc_ram_data_reg_wr_last; cfg_desc_ram_rd_req <= cfg_rd_re & dec_range_1 & (h2c_ps_cfg_addr[7:0] == 8'h14) & (desc_ram_idx == 0); - + end // else: !if(!rst_n) assign cfg_desc_ram_wdata = cfg_desc_ram_data_q; - + always @(posedge clk) if (!rst_n) begin cfg_desc_oflow <= 0; @@ -513,7 +516,7 @@ module sde_h2c_cfg #(parameter bit DESC_TYPE = 0, logic clr_cfg_dm_rresp_err; logic cfg_dm_desc_len_err; logic clr_cfg_dm_desc_len_err; - + assign ack_range_2 = h2c_ps_cfg_wr_req ? ack_wr_range_2 : ack_rd_range_2; // Register Writes @@ -524,7 +527,7 @@ module sde_h2c_cfg #(parameter bit DESC_TYPE = 0, end else if (h2c_ps_cfg_wr_req & dec_range_2) begin ack_wr_range_2 <= 0; - case (h2c_ps_cfg_addr[7:0]) + case (h2c_ps_cfg_addr[7:0]) 8'h00 : begin ack_wr_range_2 <= 1; cfg_dm_ctl_reg0 <= h2c_ps_cfg_wdata; @@ -582,7 +585,7 @@ module sde_h2c_cfg #(parameter bit DESC_TYPE = 0, logic clr_wb_sts_bresp_err; logic cfg_wb_sts_bresp_err; - + assign ack_range_3 = h2c_ps_cfg_wr_req ? ack_wr_range_3 : ack_rd_range_3; // Register Writes @@ -596,7 +599,7 @@ module sde_h2c_cfg #(parameter bit DESC_TYPE = 0, end else if (h2c_ps_cfg_wr_req & dec_range_3) begin ack_wr_range_3 <= 0; - case (h2c_ps_cfg_addr[7:0]) + case (h2c_ps_cfg_addr[7:0]) 8'h00 : begin ack_wr_range_3 <= 1; cfg_wb_ctl_reg0 <= h2c_ps_cfg_wdata; @@ -617,7 +620,7 @@ module sde_h2c_cfg #(parameter bit DESC_TYPE = 0, ack_wr_range_3 <= 1; endcase // case (h2c_ps_cfg_addr[7:0]) end // if (h2c_ps_cfg_wr_req & dec_range_2) - + // Register Reads always @(posedge clk) if (!rst_n) begin @@ -656,9 +659,9 @@ module sde_h2c_cfg #(parameter bit DESC_TYPE = 0, end endcase // case (h2c_ps_cfg_addr[7:0]) end // else: !if(!rst_n) - + assign clr_wb_sts_bresp_err = cfg_wr_re & dec_range_3 & (h2c_ps_cfg_addr[7:0] == 8'h10) & h2c_ps_cfg_wdata[0]; - + assign cfg_wb_desc_cnt_en = cfg_wb_ctl_reg0[0]; assign cfg_wb_pkt_cnt_en = cfg_wb_ctl_reg0[1]; assign cfg_wb_desc_cdt_en = cfg_wb_ctl_reg0[2]; @@ -696,7 +699,7 @@ module sde_h2c_cfg #(parameter bit DESC_TYPE = 0, end else if (h2c_ps_cfg_wr_req & dec_range_4) begin ack_wr_range_4 <= 0; - case (h2c_ps_cfg_addr[7:0]) + case (h2c_ps_cfg_addr[7:0]) 8'h00 : begin ack_wr_range_4 <= 1; cfg_buf_ctl_reg0 <= h2c_ps_cfg_wdata; @@ -782,7 +785,7 @@ module sde_h2c_cfg #(parameter bit DESC_TYPE = 0, else begin cfg_axis_clr_pkt_cnt <= cfg_wr_re & dec_range_5 & (h2c_ps_cfg_addr[7:0] == 8'h00) & (h2c_ps_cfg_wdata == 32'd0); end - + // Read data and ack always @(posedge clk) if (!rst_n) begin @@ -816,5 +819,5 @@ module sde_h2c_cfg #(parameter bit DESC_TYPE = 0, cfg_wb_dm_error <= cfg_dm_rresp_err | cfg_dm_desc_len_err; cfg_wb_wb_error <= cfg_wb_sts_bresp_err; end - + endmodule // sde_h2c_cfg diff --git a/hdk/cl/examples/cl_sde/design/sde_h2c_data.sv b/hdk/cl/examples/cl_sde/design/sde_h2c_data.sv index 70e4f5ea6..343075f46 100644 --- a/hdk/cl/examples/cl_sde/design/sde_h2c_data.sv +++ b/hdk/cl/examples/cl_sde/design/sde_h2c_data.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016-2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ // H2C Data Mover @@ -22,13 +24,13 @@ module sde_h2c_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact parameter PCIM_DM_ARID = 0, // This is the ID used for read accesses from Data Mover parameter PCIM_MAX_RD_SIZE = 0, // 0 - 512B, 1 - 1KB, 2 - 2KB, 3 - 4KB - + parameter PCIM_DATA_WIDTH = 512, parameter PCIM_ID_WIDTH = 3, parameter PCIM_LEN_WIDTH = 8, parameter PCIM_ADDR_WIDTH = 64, parameter PCIM_ADDR_BYTE_IDX_WIDTH = $clog2(PCIM_DATA_WIDTH>>3), - + parameter BUF_DEPTH = 512, parameter BUF_ADDR_RAM_IDX_WIDTH = $clog2(BUF_DEPTH), parameter BUF_ADDR_WIDTH = PCIM_ADDR_BYTE_IDX_WIDTH + BUF_ADDR_RAM_IDX_WIDTH, @@ -41,18 +43,18 @@ module sde_h2c_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact // These are internal FIFOs - Dont change unless absolutely required parameter RD_TXN_TRK_FIFO_DEPTH = PCIM_NUM_OT_RD, parameter DP_DATA_OUTPUT_FIFO_DEPTH = 3 - - + + ) ( input clk, input rst_n, - + // CSR to Data Mover //TODO output logic dm_cfg_rresp_err, output logic dm_cfg_desc_len_err, - + // Desc to Data Mover input desc_dm_empty, output logic dm_desc_pop, @@ -81,11 +83,11 @@ module sde_h2c_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact output logic [BUF_ADDR_WIDTH-1:0] dm_buf_wr_byte_addr, output logic dm_buf_wr_ptr_msb, input [BUF_ADDR_WIDTH:0] buf_dm_num_bytes, - + output logic [BUF_AUX_RAM_ADDR_WIDTH-1:0] dm_buf_aux_wr_ptr, output logic dm_buf_aux_wr_ptr_msb, input buf_dm_aux_full, - + output logic dm_buf_wr, output logic [PCIM_DATA_WIDTH-1:0] dm_buf_data, output logic dm_buf_eop, @@ -93,7 +95,7 @@ module sde_h2c_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact output logic [PCIM_ADDR_BYTE_IDX_WIDTH-1:0] dm_buf_num_bytes_minus1 ); - + localparam PCIM_DATA_WIDTH_BYTES = PCIM_DATA_WIDTH >> 3; localparam BUF_SIZE_BYTES = BUF_DEPTH * (PCIM_DATA_WIDTH>>3); localparam BUF_DEPTH_MINUS1 = BUF_DEPTH - 1; @@ -101,17 +103,17 @@ module sde_h2c_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact localparam PCIM_MAX_RD_SIZE_BYTES_USER = PCIM_MAX_RD_SIZE == 0 ? 512 : PCIM_MAX_RD_SIZE == 1 ? 1024 : PCIM_MAX_RD_SIZE == 2 ? 2048 : 4096; - + localparam PCIM_MAX_RD_SIZE_BYTES_DATA_WIDTH = PCIM_DATA_WIDTH_BYTES == 64 ? 4096 : PCIM_DATA_WIDTH_BYTES == 32 ? 4096 : PCIM_DATA_WIDTH_BYTES == 16 ? 4096 : PCIM_DATA_WIDTH_BYTES == 8 ? 2048 : PCIM_DATA_WIDTH_BYTES == 4 ? 1024 : PCIM_DATA_WIDTH_BYTES == 2 ? 512 : 256; - + localparam PCIM_MAX_RD_SIZE_BYTES = PCIM_MAX_RD_SIZE_BYTES_DATA_WIDTH > PCIM_MAX_RD_SIZE_BYTES_USER ? PCIM_MAX_RD_SIZE_BYTES_USER : PCIM_MAX_RD_SIZE_BYTES_DATA_WIDTH; - - + + // Request FSM typedef enum logic [2:0] {REQ_IDLE = 0, REQ_GET_DESC = 1, @@ -164,18 +166,18 @@ module sde_h2c_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact logic curr_txn_space_avail; logic desc_req_done; logic rd_txn_trk_ff_full; - + logic rd_txn_done; logic data_rx_desc_done; logic data_rx_done_w_eop; - + // REQ FSM always @(posedge clk) - if (!rst_n) + if (!rst_n) req_state <= REQ_IDLE; else req_state <= req_state_next; - + // IDLE -> GET_DESC when desc_dm_desc_valid is true. // GET_DESC -> WAIT_DATA immediately. Here flop the required bits // ADDR : Send araddr, arlen, arid - wait until Grant - Also start data fetch from RAM @@ -207,7 +209,7 @@ module sde_h2c_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact req_state_next = REQ_WAIT_DATA; else req_state_next = REQ_ADDR; - + default: req_state_next = req_state; @@ -224,7 +226,7 @@ module sde_h2c_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact logic [12:0] curr_desc_max_minus_dest_addr; assign curr_desc_src_addr_d = ((req_state == REQ_IDLE) && desc_dm_desc_valid) ? desc_dm_desc_in.src_addr : desc_req_done ? curr_desc_src_addr + curr_txn_num_bytes : curr_desc_src_addr; - + // Save the descriptor and descriptor related stuff always @(posedge clk) if (!rst_n) begin @@ -251,16 +253,16 @@ module sde_h2c_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact //Optimize//else //Optimize// curr_desc_src_addr <= curr_desc_src_addr; curr_desc_src_addr<= curr_desc_src_addr_d; - - // curr_desc_max_minus_dest_addr <= (PCIM_MAX_RD_SIZE == 3) ? 13'h1000 - curr_desc_src_addr_d[11:0] : - // (PCIM_MAX_RD_SIZE == 2) ? 13'h0800 - curr_desc_src_addr_d[10:0] : + + // curr_desc_max_minus_dest_addr <= (PCIM_MAX_RD_SIZE == 3) ? 13'h1000 - curr_desc_src_addr_d[11:0] : + // (PCIM_MAX_RD_SIZE == 2) ? 13'h0800 - curr_desc_src_addr_d[10:0] : // (PCIM_MAX_RD_SIZE == 1) ? 13'h0400 - curr_desc_src_addr_d[ 9:0] : 13'h0200 - curr_desc_src_addr_d[8:0]; - - curr_desc_max_minus_dest_addr <= (PCIM_MAX_RD_SIZE_BYTES == 4096) ? 13'h1000 - curr_desc_src_addr_d[11:0] : - (PCIM_MAX_RD_SIZE_BYTES == 2048) ? 13'h0800 - curr_desc_src_addr_d[10:0] : - (PCIM_MAX_RD_SIZE_BYTES == 1024) ? 13'h0400 - curr_desc_src_addr_d[ 9:0] : + + curr_desc_max_minus_dest_addr <= (PCIM_MAX_RD_SIZE_BYTES == 4096) ? 13'h1000 - curr_desc_src_addr_d[11:0] : + (PCIM_MAX_RD_SIZE_BYTES == 2048) ? 13'h0800 - curr_desc_src_addr_d[10:0] : + (PCIM_MAX_RD_SIZE_BYTES == 1024) ? 13'h0400 - curr_desc_src_addr_d[ 9:0] : (PCIM_MAX_RD_SIZE_BYTES == 512) ? 13'h0200 - curr_desc_src_addr_d[ 8:0] : 13'h0100 - curr_desc_src_addr_d[ 7:0]; - + // Length and Decrement after every Txn if ((req_state == REQ_IDLE) && desc_dm_desc_valid) curr_desc_len <= desc_dm_desc_in.len; @@ -286,16 +288,16 @@ module sde_h2c_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact curr_desc_num_bytes <= curr_desc_num_bytes; end // else: !if(!rst_n) - - + + // Max Number of bytes // If source is SPB, the maximum bytes is 4K - //Optimize//assign curr_txn_max_bytes = (PCIM_MAX_RD_SIZE == 3) ? 13'h1000 - curr_desc_src_addr[11:0] : - //Optimize// (PCIM_MAX_RD_SIZE == 2) ? 13'h0800 - curr_desc_src_addr[10:0] : + //Optimize//assign curr_txn_max_bytes = (PCIM_MAX_RD_SIZE == 3) ? 13'h1000 - curr_desc_src_addr[11:0] : + //Optimize// (PCIM_MAX_RD_SIZE == 2) ? 13'h0800 - curr_desc_src_addr[10:0] : //Optimize// (PCIM_MAX_RD_SIZE == 1) ? 13'h0400 - curr_desc_src_addr[ 9:0] : 13'h0200 - curr_desc_src_addr[8:0]; assign curr_txn_max_bytes = curr_desc_max_minus_dest_addr; - // Number of bytes in the transaction + // Number of bytes in the transaction //Optimize//assign curr_txn_min_num_bytes = min_bytes_2 (curr_desc_len, curr_txn_max_bytes); assign curr_txn_min_num_bytes = (curr_desc_len[31:13] != 0) ? curr_txn_max_bytes : (curr_desc_len[12:0] > curr_txn_max_bytes[12:0]) ? curr_txn_max_bytes : curr_desc_len; @@ -316,35 +318,35 @@ module sde_h2c_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact assign buf_dm_num_bytes_ext = buf_dm_num_bytes; assign curr_txn_buf_space_avail = (buf_dm_num_bytes_ext >= curr_txn_min_num_bytes); end - + // Space Available assign curr_txn_space_avail = curr_txn_aux_space_avail & curr_txn_buf_space_avail; assign curr_buf_byte_wr_addr_plus_txn_num_bytes = curr_buf_byte_wr_addr + curr_txn_num_bytes; assign curr_buf_byte_wr_addr_plus_txn_num_bytes_rovr = curr_buf_byte_wr_addr_plus_txn_num_bytes - BUF_SIZE_BYTES; - + assign curr_buf_byte_wr_addr_next = curr_buf_byte_wr_addr_plus_txn_num_bytes >= BUF_SIZE_BYTES ? curr_buf_byte_wr_addr_plus_txn_num_bytes_rovr : curr_buf_byte_wr_addr_plus_txn_num_bytes; assign curr_buf_byte_wr_addr_msb_next = curr_buf_byte_wr_addr_plus_txn_num_bytes >= BUF_SIZE_BYTES ? ~curr_buf_wr_ptr_msb : curr_buf_wr_ptr_msb; - - assign curr_buf_ram_wr_addr_next = (curr_buf_byte_wr_addr_next[PCIM_ADDR_BYTE_IDX_WIDTH-1:0] == ({PCIM_ADDR_BYTE_IDX_WIDTH{1'b0}})) ? curr_buf_byte_wr_addr_next[PCIM_ADDR_BYTE_IDX_WIDTH +: BUF_ADDR_RAM_IDX_WIDTH] : - curr_buf_byte_wr_addr_next[PCIM_ADDR_BYTE_IDX_WIDTH +: BUF_ADDR_RAM_IDX_WIDTH] == BUF_DEPTH_MINUS1 ? ({BUF_ADDR_RAM_IDX_WIDTH{1'b0}}) : + + assign curr_buf_ram_wr_addr_next = (curr_buf_byte_wr_addr_next[PCIM_ADDR_BYTE_IDX_WIDTH-1:0] == ({PCIM_ADDR_BYTE_IDX_WIDTH{1'b0}})) ? curr_buf_byte_wr_addr_next[PCIM_ADDR_BYTE_IDX_WIDTH +: BUF_ADDR_RAM_IDX_WIDTH] : + curr_buf_byte_wr_addr_next[PCIM_ADDR_BYTE_IDX_WIDTH +: BUF_ADDR_RAM_IDX_WIDTH] == BUF_DEPTH_MINUS1 ? ({BUF_ADDR_RAM_IDX_WIDTH{1'b0}}) : curr_buf_byte_wr_addr_next[PCIM_ADDR_BYTE_IDX_WIDTH +: BUF_ADDR_RAM_IDX_WIDTH] + 1; - assign curr_buf_ram_wr_addr_msb_next = curr_buf_byte_wr_addr_plus_txn_num_bytes >= BUF_SIZE_BYTES ? ~curr_buf_wr_ptr_msb : - ((curr_buf_byte_wr_addr_next[PCIM_ADDR_BYTE_IDX_WIDTH +: BUF_ADDR_RAM_IDX_WIDTH] == BUF_DEPTH_MINUS1) && - (curr_buf_byte_wr_addr_next[PCIM_ADDR_BYTE_IDX_WIDTH-1:0] != ({PCIM_ADDR_BYTE_IDX_WIDTH{1'b0}}))) ? ~curr_buf_wr_ptr_msb : + assign curr_buf_ram_wr_addr_msb_next = curr_buf_byte_wr_addr_plus_txn_num_bytes >= BUF_SIZE_BYTES ? ~curr_buf_wr_ptr_msb : + ((curr_buf_byte_wr_addr_next[PCIM_ADDR_BYTE_IDX_WIDTH +: BUF_ADDR_RAM_IDX_WIDTH] == BUF_DEPTH_MINUS1) && + (curr_buf_byte_wr_addr_next[PCIM_ADDR_BYTE_IDX_WIDTH-1:0] != ({PCIM_ADDR_BYTE_IDX_WIDTH{1'b0}}))) ? ~curr_buf_wr_ptr_msb : curr_buf_wr_ptr_msb; - + assign curr_txn_num_bytes_adj = curr_txn_min_num_bytes + curr_desc_src_addr[PCIM_ADDR_BYTE_IDX_WIDTH-1:0]; assign curr_buf_aux_wr_ptr_next = (curr_buf_aux_wr_ptr == ({BUF_AUX_RAM_ADDR_WIDTH{1'b1}})) ? 0 : curr_buf_aux_wr_ptr + 1; assign curr_buf_aux_wr_ptr_msb_next = (curr_buf_aux_wr_ptr == ({BUF_AUX_RAM_ADDR_WIDTH{1'b1}})) ? ~curr_buf_aux_wr_ptr_msb : curr_buf_aux_wr_ptr_msb; - + assign curr_txn_arlen_2_extra_beats = (curr_txn_min_num_bytes[PCIM_ADDR_BYTE_IDX_WIDTH-1:0] + curr_desc_src_addr[PCIM_ADDR_BYTE_IDX_WIDTH-1:0]) > PCIM_DATA_WIDTH_BYTES; assign curr_txn_arlen_1_extra_beat = (|curr_txn_min_num_bytes[PCIM_ADDR_BYTE_IDX_WIDTH-1:0] || |curr_desc_src_addr[PCIM_ADDR_BYTE_IDX_WIDTH-1:0]); - // Save details to be used by the Txn transfered by the Data Transfer Pipe + // Save details to be used by the Txn transfered by the Data Transfer Pipe always @(posedge clk) if (!rst_n) begin curr_buf_byte_wr_addr <= '{default:'0}; @@ -352,7 +354,7 @@ module sde_h2c_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact curr_buf_aux_wr_ptr <= '{default:'0}; curr_buf_aux_wr_ptr_msb <= 0; - + curr_txn_src_addr <= '{default:'0}; curr_txn_num_bytes <= '{default:'0}; end @@ -385,7 +387,7 @@ module sde_h2c_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact curr_txn_src_addr <= curr_desc_src_addr; else curr_txn_src_addr <= curr_txn_src_addr; - + // Number of bytes per txn if ((req_state == REQ_WAIT_DATA) && ~rd_txn_trk_ff_full) //Optimize// curr_txn_num_bytes <= min_bytes_3 (curr_desc_len, curr_txn_max_bytes, buf_dm_num_bytes); @@ -394,14 +396,14 @@ module sde_h2c_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact curr_txn_num_bytes <= curr_txn_num_bytes; if ((req_state == REQ_WAIT_DATA) && ~rd_txn_trk_ff_full) - //Optimize//curr_txn_arlen <= (|curr_txn_num_bytes_adj[PCIM_ADDR_BYTE_IDX_WIDTH-1:0]) ? (curr_txn_num_bytes_adj >> PCIM_ADDR_BYTE_IDX_WIDTH) : + //Optimize//curr_txn_arlen <= (|curr_txn_num_bytes_adj[PCIM_ADDR_BYTE_IDX_WIDTH-1:0]) ? (curr_txn_num_bytes_adj >> PCIM_ADDR_BYTE_IDX_WIDTH) : //Optimize// (curr_txn_num_bytes_adj >> PCIM_ADDR_BYTE_IDX_WIDTH) - 1; curr_txn_arlen <= curr_txn_arlen_2_extra_beats ? (curr_txn_min_num_bytes[12:PCIM_ADDR_BYTE_IDX_WIDTH] + 1) : curr_txn_arlen_1_extra_beat ? curr_txn_min_num_bytes[12:PCIM_ADDR_BYTE_IDX_WIDTH] : (curr_txn_min_num_bytes[12:PCIM_ADDR_BYTE_IDX_WIDTH] - 1); else curr_txn_arlen <= curr_txn_arlen; - + end // else: !if(!rst_n) // PCIM AR Interface @@ -422,7 +424,7 @@ module sde_h2c_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact assign dm_buf_aux_wr_ptr = curr_buf_aux_wr_ptr; assign dm_buf_aux_wr_ptr_msb = curr_buf_aux_wr_ptr_msb; - + // Read Track FIFO - Used to save AXI TXN Information localparam RD_TXN_TRK_FIFO_WIDTH = $bits(rd_txn_trk_t); localparam RD_TXN_TRK_FIFO_DEPTH_MINUS1 = RD_TXN_TRK_FIFO_DEPTH - 1; @@ -433,7 +435,7 @@ module sde_h2c_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact logic [RD_TXN_TRK_FIFO_WIDTH-1:0] rd_txn_trk_ff_data_out; rd_txn_trk_t rd_txn_trk_ff_push_data, rd_txn_trk_ff_pop_data; logic [$clog2(RD_TXN_TRK_FIFO_DEPTH) : 0] rd_txn_trk_ff_cnt; - + assign rd_txn_trk_ff_push = dm_pm_arvalid & pm_dm_arready; assign rd_txn_trk_ff_push_data.txn_src_addr = curr_txn_src_addr[0 +: PCIM_ADDR_BYTE_IDX_WIDTH]; assign rd_txn_trk_ff_push_data.desc_spb = curr_desc.spb; @@ -442,9 +444,9 @@ module sde_h2c_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact assign rd_txn_trk_ff_push_data.txn_num_bytes = curr_txn_num_bytes[12:0]; assign rd_txn_trk_ff_push_data.txn_arlen = curr_txn_arlen; assign rd_txn_trk_ff_push_data.desc_user = curr_desc.user; - + // Read Transaction Track FIFO - + ram_fifo_ft #(.WIDTH (RD_TXN_TRK_FIFO_WIDTH), .PTR_WIDTH ($clog2(RD_TXN_TRK_FIFO_DEPTH)), .WATERMARK (RD_TXN_TRK_FIFO_DEPTH_MINUS1), @@ -459,7 +461,7 @@ module sde_h2c_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact .wmark (rd_txn_trk_ff_full) ); - + assign rd_txn_trk_ff_pop = rd_txn_done; assign rd_txn_trk_ff_pop_data = rd_txn_trk_ff_data_out; @@ -475,25 +477,25 @@ module sde_h2c_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact // Align Pipe logic dp_stall; logic fetch_stall; - + // Stage 2 - Mux the SPB Read Pipe or from PCIM // TODO: Not supporting SPB now logic stg2_dp_valid; logic [PCIM_DATA_WIDTH-1:0] stg2_dp_data; logic [1:0] stg2_dp_resp; logic stg2_dp_rlast; - + logic pl2_dp_valid; logic [PCIM_DATA_WIDTH-1:0] pl2_dp_data; logic [1:0] pl2_dp_resp; logic pl2_dp_rlast; - + assign stg2_dp_valid = pm_dm_rvalid; assign stg2_dp_data = pm_dm_rdata ; assign stg2_dp_resp = pm_dm_rresp ; assign stg2_dp_rlast = pm_dm_rlast ; assign dm_pm_rready = ~dp_stall; - + always @(posedge clk) if (!rst_n) begin pl2_dp_valid <= 0; @@ -522,7 +524,7 @@ module sde_h2c_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact logic [PCIM_DATA_WIDTH-1:0] stg3_dp_data; logic stg3_dp_valid; logic stg3_dp_desc_last_txn; - + logic pl3_dp_valid; logic [PCIM_DATA_WIDTH-1:0] pl3_dp_data; logic [1:0] pl3_dp_resp; @@ -534,30 +536,30 @@ module sde_h2c_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact logic pl3_dp_desc_last_txn; assign stg3_dp_valid = pl2_dp_valid; - - assign stg3_dp_num_bytes_first_slice = rd_txn_trk_ff_pop_data.desc_spb ? PCIM_DATA_WIDTH_BYTES: + + assign stg3_dp_num_bytes_first_slice = rd_txn_trk_ff_pop_data.desc_spb ? PCIM_DATA_WIDTH_BYTES: PCIM_DATA_WIDTH_BYTES - (rd_txn_trk_ff_pop_data.txn_src_addr[0 +: PCIM_ADDR_BYTE_IDX_WIDTH]); assign stg3_dp_num_bytes_last_slice = pl3_dp_num_bytes_remain; assign stg3_dp_first = pl3_dp_num_bytes_remain == 0; - + assign stg3_dp_last = (rd_txn_trk_ff_pop_data.txn_num_bytes <= stg3_dp_num_bytes_first_slice) || (pl3_dp_num_bytes_remain == stg3_dp_num_bytes_in); assign stg3_dp_eop = stg3_dp_last & rd_txn_trk_ff_pop_data.txn_eop; - + assign stg3_dp_num_bytes = ~stg3_dp_valid ? 0 : - stg3_dp_first ? min_bytes_2 (stg3_dp_num_bytes_first_slice, rd_txn_trk_ff_pop_data.txn_num_bytes) : + stg3_dp_first ? min_bytes_2 (stg3_dp_num_bytes_first_slice, rd_txn_trk_ff_pop_data.txn_num_bytes) : min_bytes_2(pl3_dp_num_bytes_remain, PCIM_DATA_WIDTH_BYTES); assign stg3_dp_num_bytes_in = stg3_dp_first ? min_bytes_2 (stg3_dp_num_bytes_first_slice, rd_txn_trk_ff_pop_data.txn_num_bytes) : min_bytes_2(pl3_dp_num_bytes_remain, PCIM_DATA_WIDTH_BYTES); - - assign stg3_dp_num_bytes_remain = ~stg3_dp_valid ? pl3_dp_num_bytes_remain : - stg3_dp_first ? rd_txn_trk_ff_pop_data.txn_num_bytes - stg3_dp_num_bytes_in : + + assign stg3_dp_num_bytes_remain = ~stg3_dp_valid ? pl3_dp_num_bytes_remain : + stg3_dp_first ? rd_txn_trk_ff_pop_data.txn_num_bytes - stg3_dp_num_bytes_in : pl3_dp_num_bytes_remain - stg3_dp_num_bytes_in; - + assign stg3_dp_data = stg3_dp_first ? (pl2_dp_data >> ({rd_txn_trk_ff_pop_data.txn_src_addr[0 +: PCIM_ADDR_BYTE_IDX_WIDTH], 3'd0})) : pl2_dp_data; - + always @(posedge clk) if (!rst_n) begin pl3_dp_valid <= 0; @@ -616,7 +618,7 @@ module sde_h2c_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact logic [PCIM_ADDR_BYTE_IDX_WIDTH+1:0] stg4_dp_num_bytes; logic stg4_dp_eop; logic [USER_BIT_WIDTH-1:0] stg4_dp_user; - + logic pl4_dp_valid; logic [PCIM_DATA_WIDTH-1:0] pl4_dp_data; logic pl4_dp_last; @@ -625,15 +627,15 @@ module sde_h2c_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact logic [PCIM_ADDR_BYTE_IDX_WIDTH:0] pl4_dp_num_bytes; logic [PCIM_ADDR_BYTE_IDX_WIDTH:0] pl4_dp_num_bytes_remain; logic [PCIM_ADDR_BYTE_IDX_WIDTH-1:0] pl4_dp_num_bytes_minus1; - + assign stg4_dp_num_bytes_comb = pl3_dp_num_bytes + pl4_dp_num_bytes; assign stg4_dp_num_bytes_gt_64 = stg4_dp_num_bytes_comb > PCIM_DATA_WIDTH_BYTES; assign stg4_dp_num_bytes_lt_64 = stg4_dp_num_bytes_comb < PCIM_DATA_WIDTH_BYTES; assign stg4_dp_num_bytes_eq_64 = stg4_dp_num_bytes_comb == PCIM_DATA_WIDTH_BYTES; - assign stg4_dp_copy = (pl4_dp_valid & pl4_dp_eop) || + assign stg4_dp_copy = (pl4_dp_valid & pl4_dp_eop) || (pl3_dp_valid & ~pl3_dp_eop & ~pl4_dp_valid & stg4_dp_num_bytes_lt_64); - + assign stg4_dp_clear = (~pl3_dp_valid & pl4_dp_valid & ~pl4_dp_eop & stg4_dp_num_bytes_eq_64) || (pl3_dp_valid & ~pl3_dp_eop & pl4_dp_valid & ~pl4_dp_eop & stg4_dp_num_bytes_eq_64) || (pl3_dp_valid & pl3_dp_eop & pl4_dp_valid & ~pl4_dp_eop & (stg4_dp_num_bytes_lt_64 || stg4_dp_num_bytes_eq_64)); @@ -643,47 +645,47 @@ module sde_h2c_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact assign stg4_dp_save_ovf = (pl3_dp_valid & ~pl3_dp_eop & pl4_dp_valid & ~pl4_dp_eop & stg4_dp_num_bytes_gt_64) || (pl3_dp_valid & pl3_dp_eop & pl4_dp_valid & ~pl4_dp_eop & stg4_dp_num_bytes_gt_64); - // Valid + // Valid assign stg4_dp_valid = stg4_dp_copy ? pl3_dp_valid : stg4_dp_clear ? 1'b0 : stg4_dp_accm || stg4_dp_save_ovf ? 1'b1 : pl4_dp_valid; - + // Overflow and Accumulate always_comb begin stg4_dp_data_accm_plus_ovf = '{default:'0}; for (int byte_idx = 0; byte_idx < (2*PCIM_DATA_WIDTH_BYTES); byte_idx++) if (byte_idx <= pl4_dp_num_bytes_minus1) stg4_dp_data_accm_plus_ovf [byte_idx*8 +: 8] = pl4_dp_data[byte_idx*8 +: 8]; - else + else stg4_dp_data_accm_plus_ovf [byte_idx*8 +: 8] = pl3_dp_data[(byte_idx - pl4_dp_num_bytes)*8 +: 8]; end // Accumulate assign stg4_dp_data_accm = stg4_dp_data_accm_plus_ovf[0 +: PCIM_DATA_WIDTH]; - + // Save Overflow assign stg4_dp_data_ovf = stg4_dp_data_accm_plus_ovf[PCIM_DATA_WIDTH +: PCIM_DATA_WIDTH]; // Data - assign stg4_dp_data = stg4_dp_copy ? pl3_dp_data : + assign stg4_dp_data = stg4_dp_copy ? pl3_dp_data : stg4_dp_accm ? stg4_dp_data_accm : stg4_dp_save_ovf ? stg4_dp_data_ovf : pl4_dp_data; // Number of bytes assign stg4_dp_num_bytes = stg4_dp_copy ? pl3_dp_num_bytes : - stg4_dp_clear ? 0 : - stg4_dp_accm ? stg4_dp_num_bytes_comb : + stg4_dp_clear ? 0 : + stg4_dp_accm ? stg4_dp_num_bytes_comb : stg4_dp_save_ovf ? stg4_dp_num_bytes_comb - PCIM_DATA_WIDTH_BYTES : pl4_dp_num_bytes; // EOP assign stg4_dp_eop = stg4_dp_copy ? pl3_dp_eop : - stg4_dp_clear || stg4_dp_accm ? 0 : + stg4_dp_clear || stg4_dp_accm ? 0 : stg4_dp_save_ovf ? pl3_dp_eop : pl4_dp_eop; // User Bits assign stg4_dp_user = stg4_dp_copy || stg4_dp_save_ovf ? pl3_dp_user : pl4_dp_user; - + always @(posedge clk) if (!rst_n) begin pl4_dp_valid <= 0; @@ -701,7 +703,7 @@ module sde_h2c_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact pl4_dp_num_bytes <= ~dp_stall ? stg4_dp_num_bytes : pl4_dp_num_bytes; pl4_dp_num_bytes_minus1 <= ~dp_stall ? (stg4_dp_num_bytes - 1) : pl4_dp_num_bytes_minus1; end - + // Stage 5 - Align logic stg5_dp_send_from_3; logic stg5_dp_send_from_4; @@ -721,19 +723,19 @@ module sde_h2c_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact logic [USER_BIT_WIDTH-1:0] pl5_dp_user; logic [PCIM_ADDR_BYTE_IDX_WIDTH:0] pl5_dp_num_bytes; logic [PCIM_ADDR_BYTE_IDX_WIDTH:0] pl5_dp_num_bytes_minus1; - - assign stg5_dp_send_from_3 = (pl3_dp_valid & ~pl3_dp_eop & ~pl4_dp_valid & stg4_dp_num_bytes_eq_64) || + + assign stg5_dp_send_from_3 = (pl3_dp_valid & ~pl3_dp_eop & ~pl4_dp_valid & stg4_dp_num_bytes_eq_64) || (pl3_dp_valid & pl3_dp_eop & ~pl4_dp_valid & (stg4_dp_num_bytes_lt_64 || stg4_dp_num_bytes_eq_64)); - - assign stg5_dp_send_from_4 = (~pl3_dp_valid & pl4_dp_valid & ~pl4_dp_eop & stg4_dp_num_bytes_eq_64) || + + assign stg5_dp_send_from_4 = (~pl3_dp_valid & pl4_dp_valid & ~pl4_dp_eop & stg4_dp_num_bytes_eq_64) || (pl4_dp_valid & pl4_dp_eop); - - assign stg5_dp_send_comb = (pl3_dp_valid & ~pl3_dp_eop & pl4_dp_valid & ~pl4_dp_eop & (stg4_dp_num_bytes_gt_64 | stg4_dp_num_bytes_eq_64)) || + + assign stg5_dp_send_comb = (pl3_dp_valid & ~pl3_dp_eop & pl4_dp_valid & ~pl4_dp_eop & (stg4_dp_num_bytes_gt_64 | stg4_dp_num_bytes_eq_64)) || (pl3_dp_valid & pl3_dp_eop & pl4_dp_valid & ~pl4_dp_eop); - - assign stg5_dp_bubble = (~pl3_dp_valid & ~pl4_dp_valid) || - (~pl3_dp_valid & pl4_dp_valid & ~pl4_dp_eop & stg4_dp_num_bytes_lt_64) || - ( pl3_dp_valid & ~pl3_dp_eop & ~pl4_dp_valid & stg4_dp_num_bytes_lt_64) || + + assign stg5_dp_bubble = (~pl3_dp_valid & ~pl4_dp_valid) || + (~pl3_dp_valid & pl4_dp_valid & ~pl4_dp_eop & stg4_dp_num_bytes_lt_64) || + ( pl3_dp_valid & ~pl3_dp_eop & ~pl4_dp_valid & stg4_dp_num_bytes_lt_64) || ( pl3_dp_valid & ~pl3_dp_eop & pl4_dp_valid & ~pl4_dp_eop & stg4_dp_num_bytes_lt_64); // Valid @@ -741,7 +743,7 @@ module sde_h2c_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact stg5_dp_send_from_4 ? pl4_dp_valid : stg5_dp_send_comb ? 1'b1 : stg5_dp_bubble ? 0 : pl5_dp_valid; - + // Data assign stg5_dp_data = stg5_dp_send_from_3 ? pl3_dp_data : stg5_dp_send_from_4 ? pl4_dp_data : @@ -752,16 +754,16 @@ module sde_h2c_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact assign stg5_dp_num_bytes = stg5_dp_send_from_3 ? pl3_dp_num_bytes : stg5_dp_send_from_4 ? pl4_dp_num_bytes : stg5_dp_send_comb ? min_bytes_2 (stg4_dp_num_bytes_comb, PCIM_DATA_WIDTH_BYTES) : - stg5_dp_bubble ? 0 : + stg5_dp_bubble ? 0 : pl5_dp_num_bytes; assign stg5_dp_num_bytes_minus1 = stg5_dp_num_bytes - 1; - + // EOP assign stg5_dp_eop = stg5_dp_send_from_3 ? pl3_dp_eop : stg5_dp_send_from_4 ? pl4_dp_eop : - stg5_dp_send_comb ? pl3_dp_eop & ~stg4_dp_num_bytes_gt_64 : + stg5_dp_send_comb ? pl3_dp_eop & ~stg4_dp_num_bytes_gt_64 : stg5_dp_bubble ? 0 : pl5_dp_eop; // User Bits @@ -785,10 +787,10 @@ module sde_h2c_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact pl5_dp_num_bytes <= ~dp_stall ? stg5_dp_num_bytes : pl5_dp_num_bytes; pl5_dp_num_bytes_minus1 <= ~dp_stall ? stg5_dp_num_bytes_minus1 : pl5_dp_num_bytes_minus1; end // else: !if(!rst_n) - + localparam DP_DATA_OUTPUT_FIFO_DEPTH_MINUS1 = DP_DATA_OUTPUT_FIFO_DEPTH - 1; localparam DP_DATA_OUTPUT_FIFO_WIDTH = PCIM_DATA_WIDTH + PCIM_ADDR_BYTE_IDX_WIDTH + USER_BIT_WIDTH + 1; - + logic dp_data_out_ff_push; logic dp_data_out_ff_pop; logic [DP_DATA_OUTPUT_FIFO_WIDTH-1:0] dp_data_out_ff_push_data; @@ -796,13 +798,13 @@ module sde_h2c_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact logic dp_data_out_ff_full; logic dp_data_out_ff_valid; logic [$clog2(DP_DATA_OUTPUT_FIFO_DEPTH):0] dp_data_out_ff_cnt; - + assign dp_data_out_ff_push = pl5_dp_valid & ~dp_stall; assign dp_data_out_ff_push_data = {pl5_dp_data, pl5_dp_eop, pl5_dp_user, pl5_dp_num_bytes_minus1[PCIM_ADDR_BYTE_IDX_WIDTH-1:0]}; - + // Output fifo for Write Data flop_fifo #(.WIDTH(DP_DATA_OUTPUT_FIFO_WIDTH), .DEPTH(DP_DATA_OUTPUT_FIFO_DEPTH) @@ -818,15 +820,15 @@ module sde_h2c_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact .watermark (dp_data_out_ff_full), .data_valid (dp_data_out_ff_valid) ); - + // Back-pressure to Data Pipeline assign dp_stall = dp_data_out_ff_full; assign dp_data_out_ff_pop = dp_data_out_ff_valid; - + assign dm_buf_wr = dp_data_out_ff_valid; assign {dm_buf_data, - dm_buf_eop, + dm_buf_eop, dm_buf_user, dm_buf_num_bytes_minus1} = dp_data_out_ff_pop_data; @@ -836,10 +838,10 @@ module sde_h2c_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact else dp_data_out_ff_cnt <= (dp_data_out_ff_push & ~dp_data_out_ff_pop) ? dp_data_out_ff_cnt + 1 : (~dp_data_out_ff_push & dp_data_out_ff_pop) ? dp_data_out_ff_cnt - 1 : dp_data_out_ff_cnt; - + // Descriptor data transfer is done assign dm_desc_cnt_inc = data_rx_desc_done; - + // Error detection always @(posedge clk) if (!rst_n) begin @@ -850,7 +852,7 @@ module sde_h2c_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact dm_cfg_rresp_err <= pl2_dp_valid & (pl2_dp_resp != 2'd0) & pl2_dp_rlast; dm_cfg_desc_len_err <= dm_desc_pop & (desc_dm_desc_in.len == 0); end - + function logic [31:0] min_bytes_2 (input logic [31:0] inp1, input logic [31:0] inp2); min_bytes_2 = inp1 > inp2 ? inp2 : inp1; endfunction // min_bytes_2 @@ -864,7 +866,7 @@ module sde_h2c_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact logic data_rx_desc_done_q; logic data_rx_desc_done_err; - + always @(posedge clk) if (rst_n) begin data_rx_desc_done_q <= 0; @@ -874,22 +876,22 @@ module sde_h2c_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact data_rx_desc_done_q <= data_rx_desc_done; data_rx_desc_done_err <= data_rx_desc_done_q & data_rx_desc_done; end - + always @(posedge clk) if (rst_n) assert (data_rx_desc_done_err != 1'b1) else begin $display("%m : *** ERROR ***: data_rx_desc_done_err asserted more than 1 clock. @%0t", $time); $finish; end - + //synopsys translate_on `ifndef NO_SDE_DEBUG_ILA - - ila_sde_h2c_dm SDE_H2C_DM_ILA - ( + + ila_sde_h2c_dm SDE_H2C_DM_ILA + ( .clk(clk), - + // 0 - 7 .probe0(desc_dm_empty), .probe1(dm_desc_pop), @@ -900,7 +902,7 @@ module sde_h2c_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact .probe6(dm_pm_arlen), .probe7(pm_dm_arready), - // 8 - 15 + // 8 - 15 .probe8(pm_dm_rvalid), .probe9(pm_dm_rlast), .probe10(dm_pm_rready), @@ -953,15 +955,10 @@ module sde_h2c_data #(parameter bit DESC_TYPE = 0, // 0 - Regular, 1 - Compact // 48-55 .probe48(dp_data_out_ff_valid), .probe49(dp_data_out_ff_cnt) - + ); `endif // `ifndef NO_SDE_DEBUG_ILA - - -endmodule // sde_h2c_data - - - +endmodule // sde_h2c_data diff --git a/hdk/cl/examples/cl_sde/design/sde_pkg.sv b/hdk/cl/examples/cl_sde/design/sde_pkg.sv index 6cb382de4..88cea24c2 100644 --- a/hdk/cl/examples/cl_sde/design/sde_pkg.sv +++ b/hdk/cl/examples/cl_sde/design/sde_pkg.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016-2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,7 +13,7 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. - +// ============================================================================ package sde_pkg; @@ -45,7 +46,7 @@ package sde_pkg; logic [31:0] len; } c2h_reg_desc_t; - // C2H Compact Mode Descriptor + // C2H Compact Mode Descriptor typedef struct packed { logic [47:0] rsvd; logic [47:0] dest_addr; @@ -64,7 +65,7 @@ package sde_pkg; logic [31:0] len; logic desc_type; } c2h_if_desc_t; - + // C2H Intermediate Format Descriptor Definition - Used in Descritor Engine typedef struct packed { logic [63:0] dest_addr; @@ -101,7 +102,7 @@ package sde_pkg; out_desc.h2c = 0; out_desc.desc_type = 1; - + out_desc.dest_addr = in_desc.dest_addr; out_desc.len = in_desc.len; @@ -111,27 +112,27 @@ package sde_pkg; // function c2h_reg_desc_t c2h_cnv_desc_comm2reg(comm_desc_t in_desc); // c2h_reg_desc_t out_desc; // out_desc = '{default:'0}; -// +// // out_desc.desc_type = in_desc.desc_type; // out_desc.dest_addr = in_desc.dest_addr; // out_desc.wb_addr = in_desc.wb_addr; // out_desc.len = in_desc.len; -// +// // c2h_cnv_desc_comm2reg = out_desc; // endfunction // c2h_cnv_desc_comm2reg -// +// // function c2h_comp_desc_t c2h_cnv_desc_comm2comp(comm_desc_t in_desc); // c2h_comp_desc_t out_desc; // out_desc = '{default:'0}; -// +// // out_desc.desc_type = in_desc.desc_type; // out_desc.dest_addr = in_desc.dest_addr; // out_desc.wb_addr = in_desc.wb_addr; // out_desc.len = in_desc.len; -// +// // c2h_cnv_desc_comm2comp = out_desc; // endfunction // c2h_cnv_desc_comm2comp - + function c2h_if_desc_t c2h_cnv_desc_comm2if(comm_desc_t in_desc); c2h_if_desc_t out_desc; out_desc = '{default:'0}; @@ -142,8 +143,8 @@ package sde_pkg; c2h_cnv_desc_comm2if = out_desc; endfunction // c2h_cnv_desc_reg2comm - - + + /////////////////////////////////////////////////////////////// // H2C Descriptors /////////////////////////////////////////////////////////////// @@ -179,7 +180,7 @@ package sde_pkg; logic [31:0] len; } h2c_reg_desc_t; - // H2C Compact Mode Descriptor + // H2C Compact Mode Descriptor typedef struct packed { logic [45:0] rsvd; logic spb; @@ -207,7 +208,7 @@ package sde_pkg; logic [31:0] len; } h2c_reg_sav_desc_t; - // H2C Compact Mode Descriptor + // H2C Compact Mode Descriptor typedef struct packed { logic spb; logic eop; @@ -236,7 +237,7 @@ package sde_pkg; out_desc.h2c = 1; out_desc.desc_type = 1; - + out_desc.src_addr = in_desc.src_addr; out_desc.len = in_desc.len; out_desc.eop = in_desc.eop; @@ -281,7 +282,7 @@ package sde_pkg; //------------------------|-----------|-----------|-----------|-----------|-----------|-----------| // Total Bits | 128 | | | 64 | | | //------------------------|-----------|-----------|-----------|-----------|-----------|-----------| - + // C2H Reg Mode Write-Back Metadata Definition (Including RSVD bits) typedef struct packed { logic [63:0] user; @@ -291,7 +292,7 @@ package sde_pkg; logic [31:0] len; } c2h_reg_wb_t; - // C2H Compact Mode Descriptor + // C2H Compact Mode Descriptor typedef struct packed { logic [29:0] rsvd; logic eop; @@ -316,8 +317,8 @@ package sde_pkg; virtual class RR_ARB #(parameter WINNER_WIDTH=2, parameter REQ_WIDTH = 32'h1 << WINNER_WIDTH ); - - static function logic [WINNER_WIDTH-1:0] do_arb (logic [REQ_WIDTH-1:0] req, + + static function logic [WINNER_WIDTH-1:0] do_arb (logic [REQ_WIDTH-1:0] req, logic [WINNER_WIDTH-1:0] curr_winner); logic [WINNER_WIDTH-1:0] start_idx; @@ -327,7 +328,7 @@ package sde_pkg; logic [WINNER_WIDTH-1:0] winner; start_idx = (curr_winner >= (REQ_WIDTH-1)) ? 0 : curr_winner + 1; - + req_req = {2{req}}; req_shifted = req_req >> start_idx; @@ -348,8 +349,6 @@ package sde_pkg; endfunction // do_arb endclass // RR_ARB - - + + endpackage // sde_pkg - - diff --git a/hdk/cl/examples/cl_sde/design/sde_pm.sv b/hdk/cl/examples/cl_sde/design/sde_pm.sv index 5a1085f3b..3fa5ab189 100644 --- a/hdk/cl/examples/cl_sde/design/sde_pm.sv +++ b/hdk/cl/examples/cl_sde/design/sde_pm.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016-2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + // PCIM Interface @@ -20,7 +23,7 @@ module sde_pm #(parameter PCIM_DATA_WIDTH = 512, parameter PCIM_LEN_WIDTH = 8, parameter PCIM_ADDR_WIDTH = 64, parameter PCIM_ADDR_BYTE_IDX_WIDTH = $clog2(PCIM_DATA_WIDTH>>3), - + // IDs for Write Channels parameter C2H_PCIM_DM_AWID = 0, parameter C2H_PCIM_WB_AWID = 1, @@ -32,10 +35,10 @@ module sde_pm #(parameter PCIM_DATA_WIDTH = 512, parameter H2C_PCIM_DM_ARID = 2, // These are internal FIFOs - Dont change unless absolutely required - parameter PM_WR_WINNER_FIFO_DEPTH = 32 - + parameter PM_WR_WINNER_FIFO_DEPTH = 32 + ) - ( + ( input clk, input rst_n, @@ -46,7 +49,7 @@ module sde_pm #(parameter PCIM_DATA_WIDTH = 512, input [31:0] pm_ps_cfg_wdata, output pm_ps_cfg_ack, output [31:0] pm_ps_cfg_rdata, - + // PCIM Interface output logic pcim_awvalid, @@ -55,25 +58,25 @@ module sde_pm #(parameter PCIM_DATA_WIDTH = 512, output logic [PCIM_LEN_WIDTH-1:0] pcim_awlen, output logic [2:0] pcim_awsize, input pcim_awready, - + output logic pcim_wvalid, output logic [PCIM_DATA_WIDTH-1:0] pcim_wdata, output logic [(PCIM_DATA_WIDTH>>3)-1:0] pcim_wstrb, output logic pcim_wlast, input pcim_wready, - + input logic pcim_bvalid, input logic [PCIM_ID_WIDTH-1:0] pcim_bid, input logic [1:0] pcim_bresp, output logic pcim_bready, - + output logic pcim_arvalid, output logic [PCIM_ID_WIDTH-1:0] pcim_arid, output logic [PCIM_ADDR_WIDTH-1:0] pcim_araddr, output logic [PCIM_LEN_WIDTH-1:0] pcim_arlen, output logic [2:0] pcim_arsize, input pcim_arready, - + input pcim_rvalid, input [PCIM_ID_WIDTH-1:0] pcim_rid, input [PCIM_DATA_WIDTH-1:0] pcim_rdata, @@ -105,7 +108,7 @@ module sde_pm #(parameter PCIM_DATA_WIDTH = 512, input [PCIM_LEN_WIDTH-1:0] c2h_dm_pm_awlen, input [PCIM_ID_WIDTH-1:0] c2h_dm_pm_awid, output logic c2h_pm_dm_awready, - + // Write Data to PCIM input c2h_dm_pm_wvalid, input [PCIM_DATA_WIDTH-1:0] c2h_dm_pm_wdata, @@ -125,7 +128,7 @@ module sde_pm #(parameter PCIM_DATA_WIDTH = 512, input [PCIM_LEN_WIDTH-1:0] c2h_wb_pm_awlen, input [PCIM_ID_WIDTH-1:0] c2h_wb_pm_awid, output logic c2h_pm_wb_awready, - + // Write Data to PCIM input c2h_wb_pm_wvalid, input [PCIM_DATA_WIDTH-1:0] c2h_wb_pm_wdata, @@ -152,7 +155,7 @@ module sde_pm #(parameter PCIM_DATA_WIDTH = 512, output logic [PCIM_DATA_WIDTH-1:0] h2c_pm_desc_rdata, output logic h2c_pm_desc_rlast, input h2c_desc_pm_rready, - + // H2C Data Mover to PCIM Interface // Read Address to PCIM input h2c_dm_pm_arvalid, @@ -167,7 +170,7 @@ module sde_pm #(parameter PCIM_DATA_WIDTH = 512, output logic h2c_pm_dm_rlast, input h2c_dm_pm_rready, - + // H2C Write-Back Block to PCIM Interface // Write Address to PCIM input h2c_wb_pm_awvalid, @@ -175,7 +178,7 @@ module sde_pm #(parameter PCIM_DATA_WIDTH = 512, input [PCIM_LEN_WIDTH-1:0] h2c_wb_pm_awlen, input [PCIM_ID_WIDTH-1:0] h2c_wb_pm_awid, output logic h2c_pm_wb_awready, - + // Write Data to PCIM input h2c_wb_pm_wvalid, input [PCIM_DATA_WIDTH-1:0] h2c_wb_pm_wdata, @@ -187,12 +190,12 @@ module sde_pm #(parameter PCIM_DATA_WIDTH = 512, output logic h2c_pm_wb_bvalid, output logic [1:0] h2c_pm_wb_bresp, input h2c_wb_pm_bready - + ); localparam PCIM_AXSIZE = PCIM_ADDR_BYTE_IDX_WIDTH; localparam WR_WINNER_WIDTH = 2; - + logic [WR_WINNER_WIDTH-1:0] wr_arb_out; logic wr_do_arb; @@ -213,16 +216,16 @@ module sde_pm #(parameter PCIM_DATA_WIDTH = 512, // assign wr_arb_out = sde_pkg::RR_ARB#(.WINNER_WIDTH(WR_WINNER_WIDTH), // .REQ_WIDTH(3))::do_arb({h2c_wb_pm_awvalid, c2h_wb_pm_awvalid, c2h_dm_pm_awvalid}, // wr_winner); - + // Save the winner always @(posedge clk) - if (!rst_n) + if (!rst_n) wr_winner <= 0; else wr_winner <= ~aw_pipe_stall ? wr_arb_out : wr_winner; assign aw_pipe_stall = pcim_awvalid & ~pcim_awready & ~pm_wr_winner_ff_full; - + always @(posedge clk) if (!rst_n) begin pcim_awvalid <= 0; @@ -248,14 +251,14 @@ module sde_pm #(parameter PCIM_DATA_WIDTH = 512, end // else: !if(~aw_pipe_stall) end // else: !if(!rst_n) assign pcim_awsize = PCIM_AXSIZE; - + assign c2h_pm_dm_awready = (wr_arb_out == 0) & ~aw_pipe_stall; assign c2h_pm_wb_awready = (wr_arb_out == 1) & ~aw_pipe_stall; assign h2c_pm_wb_awready = (wr_arb_out == 2) & ~aw_pipe_stall; assign wr_do_arb = (h2c_wb_pm_awvalid | c2h_wb_pm_awvalid | c2h_dm_pm_awvalid) & ~aw_pipe_stall; - - + + localparam PM_WR_WINNER_FIFO_DEPTH_MINUS1 = PM_WR_WINNER_FIFO_DEPTH - 1; localparam PM_WR_WINNER_FIFO_WIDTH = WR_WINNER_WIDTH; @@ -268,8 +271,8 @@ module sde_pm #(parameter PCIM_DATA_WIDTH = 512, logic requester_wvalid; logic requester_wlast; logic requester_wready; - - + + flop_fifo #(.WIDTH(PM_WR_WINNER_FIFO_WIDTH), .DEPTH(PM_WR_WINNER_FIFO_DEPTH) ) PM_WR_WINNER_FIFO (.clk (clk), @@ -283,16 +286,16 @@ module sde_pm #(parameter PCIM_DATA_WIDTH = 512, .half_full (), .watermark (pm_wr_winner_ff_full), .data_valid (pm_wr_winner_ff_valid) - + ); assign pm_wr_winner_ff_push = pcim_awvalid & pcim_awready & ~pm_wr_winner_ff_full; assign pm_wr_winner_ff_pop = requester_wvalid & requester_wlast & ~wdata_pipe_stall & pm_wr_winner_ff_valid; - + // Write Data Channel Pipeline - + assign wdata_pipe_stall = pcim_wvalid & ~pcim_wready; - + // Pop Winner from FIFO and Send Write Data // FIFO output is valid, means that there is write data to be sent always @(posedge clk) @@ -320,13 +323,13 @@ module sde_pm #(parameter PCIM_DATA_WIDTH = 512, end // else: !if(!rst_n) assign requester_wvalid = pm_wr_winner_ff_valid & ((pm_wr_winner_ff_pop_data == 0) ? c2h_dm_pm_wvalid : - (pm_wr_winner_ff_pop_data == 1) ? c2h_wb_pm_wvalid : + (pm_wr_winner_ff_pop_data == 1) ? c2h_wb_pm_wvalid : h2c_wb_pm_wvalid); assign requester_wlast = pm_wr_winner_ff_valid & ((pm_wr_winner_ff_pop_data == 0) ? c2h_dm_pm_wlast : - (pm_wr_winner_ff_pop_data == 1) ? c2h_wb_pm_wlast : + (pm_wr_winner_ff_pop_data == 1) ? c2h_wb_pm_wlast : h2c_wb_pm_wlast); assign requester_wready = ~wdata_pipe_stall; - + assign c2h_pm_dm_wready = pm_wr_winner_ff_valid & (pm_wr_winner_ff_pop_data == 0) & requester_wready; assign c2h_pm_wb_wready = pm_wr_winner_ff_valid & (pm_wr_winner_ff_pop_data == 1) & requester_wready; assign h2c_pm_wb_wready = pm_wr_winner_ff_valid & (pm_wr_winner_ff_pop_data == 2) & requester_wready; @@ -336,7 +339,7 @@ module sde_pm #(parameter PCIM_DATA_WIDTH = 512, logic c2h_wb_bresp_pipe_stall; logic h2c_wb_bresp_pipe_stall; logic [1:0] pcim_bresp_q; - + // C2H DM BRESP Pipe assign c2h_dm_bresp_pipe_stall = c2h_pm_dm_bvalid & ~c2h_dm_pm_bready; always @(posedge clk) @@ -354,7 +357,7 @@ module sde_pm #(parameter PCIM_DATA_WIDTH = 512, // c2h_pm_dm_bresp <= c2h_pm_dm_bresp; end end // else: !if(!rst_n) - + // C2H WB BRESP Pipe assign c2h_wb_bresp_pipe_stall = c2h_pm_wb_bvalid & ~c2h_wb_pm_bready; always @(posedge clk) @@ -390,16 +393,16 @@ module sde_pm #(parameter PCIM_DATA_WIDTH = 512, // h2c_pm_wb_bresp <= h2c_pm_wb_bresp; end end // else: !if(!rst_n) - + always @(posedge clk) - if (!rst_n) + if (!rst_n) pcim_bresp_q <= 0; else if (((pcim_bid == C2H_PCIM_DM_AWID) & ~c2h_dm_bresp_pipe_stall) || ((pcim_bid == C2H_PCIM_WB_AWID) & ~c2h_wb_bresp_pipe_stall) || ((pcim_bid == H2C_PCIM_WB_AWID) & ~h2c_wb_bresp_pipe_stall)) pcim_bresp_q <= pcim_bresp; - + assign c2h_pm_dm_bresp = pcim_bresp_q; assign c2h_pm_wb_bresp = pcim_bresp_q; assign h2c_pm_wb_bresp = pcim_bresp_q; @@ -411,8 +414,8 @@ module sde_pm #(parameter PCIM_DATA_WIDTH = 512, assign pcim_bready = (pcim_bid == C2H_PCIM_DM_AWID) ? ~c2h_dm_bresp_pipe_stall : (pcim_bid == C2H_PCIM_WB_AWID) ? ~c2h_wb_bresp_pipe_stall : (pcim_bid == H2C_PCIM_WB_AWID) ? ~h2c_wb_bresp_pipe_stall : 1'b0; - - + + // Do Round Robin among those requesting read on AR Channel // Round Robin arbiter localparam RD_WINNER_WIDTH = 2; @@ -427,21 +430,21 @@ module sde_pm #(parameter PCIM_DATA_WIDTH = 512, ); logic [RD_WINNER_WIDTH-1:0] rd_winner; logic ar_pipe_stall; -// +// // assign rd_arb_out = sde_pkg::RR_ARB#(.WINNER_WIDTH(RD_WINNER_WIDTH), // .REQ_WIDTH(3))::do_arb({c2h_desc_pm_arvalid, h2c_desc_pm_arvalid, h2c_dm_pm_arvalid}, // rd_winner); - - + + // Save the winner always @(posedge clk) - if (!rst_n) + if (!rst_n) rd_winner <= 0; else rd_winner <= ~ar_pipe_stall ? rd_arb_out : rd_winner; assign ar_pipe_stall = pcim_arvalid & ~pcim_arready; - + always @(posedge clk) if (!rst_n) begin pcim_arvalid <= 0; @@ -473,7 +476,7 @@ module sde_pm #(parameter PCIM_DATA_WIDTH = 512, assign c2h_pm_desc_arready = (rd_arb_out == 2) & ~ar_pipe_stall; assign rd_do_arb = (c2h_desc_pm_arvalid | h2c_desc_pm_arvalid | h2c_dm_pm_arvalid) & ~ar_pipe_stall; - + // For the read data, look at ID and send to appropriate requester logic c2h_desc_rresp_pipe_stall; @@ -482,7 +485,7 @@ module sde_pm #(parameter PCIM_DATA_WIDTH = 512, logic [1:0] pcim_rresp_q; logic [PCIM_DATA_WIDTH-1:0] pcim_rdata_q; logic pcim_rlast_q; - + // C2H DM RRESP Pipe assign c2h_desc_rresp_pipe_stall = c2h_pm_desc_rvalid & ~c2h_desc_pm_rready; always @(posedge clk) @@ -506,7 +509,7 @@ module sde_pm #(parameter PCIM_DATA_WIDTH = 512, // c2h_dm_desc_rlast <= c2h_dm_desc_rlast; end end // else: !if(!rst_n) - + // C2H WB RRESP Pipe assign h2c_desc_rresp_pipe_stall = h2c_pm_desc_rvalid & ~h2c_desc_pm_rready; always @(posedge clk) @@ -554,7 +557,7 @@ module sde_pm #(parameter PCIM_DATA_WIDTH = 512, // h2c_dm_dm_rlast <= h2c_dm_dm_rlast; end end // else: !if(!rst_n) - + always @(posedge clk) if (!rst_n) begin pcim_rresp_q <= 0; @@ -569,7 +572,7 @@ module sde_pm #(parameter PCIM_DATA_WIDTH = 512, pcim_rdata_q <=pcim_rdata; pcim_rlast_q <= pcim_rlast; end - + assign c2h_pm_desc_rresp = pcim_rresp_q; assign h2c_pm_desc_rresp = pcim_rresp_q; assign h2c_pm_dm_rresp = pcim_rresp_q; @@ -585,19 +588,16 @@ module sde_pm #(parameter PCIM_DATA_WIDTH = 512, // assign c2h_pm_desc_rid = C2H_PCIM_DESC_ARID; // assign h2c_pm_desc_rid = H2C_PCIM_DESC_ARID; // assign h2c_pm_dm_rid = H2C_PCIM_DM_ARID; - + assign pcim_rready = (pcim_rid == C2H_PCIM_DESC_ARID) ? ~c2h_desc_rresp_pipe_stall : (pcim_rid == H2C_PCIM_DESC_ARID) ? ~h2c_desc_rresp_pipe_stall : (pcim_rid == H2C_PCIM_DM_ARID) ? ~h2c_dm_rresp_pipe_stall : 1'b0; - + // Local Config Registers // TODO: // Temporarily no registers assign pm_ps_cfg_ack = 1; assign pm_ps_cfg_rdata = 32'hbaad_1000; - -endmodule // sde_pm - - +endmodule // sde_pm diff --git a/hdk/cl/examples/cl_sde/design/sde_ps.sv b/hdk/cl/examples/cl_sde/design/sde_ps.sv index e5646deea..28d940555 100644 --- a/hdk/cl/examples/cl_sde/design/sde_ps.sv +++ b/hdk/cl/examples/cl_sde/design/sde_ps.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016-2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,12 +13,14 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + // Data Engine PCIS Interface module sde_ps #(parameter bit C2H_ONLY = 0, parameter bit H2C_ONLY = 0, - + parameter PCIS_DATA_WIDTH = 512, parameter PCIS_ID_WIDTH = 5, parameter PCIS_LEN_WIDTH = 8, @@ -25,9 +28,9 @@ module sde_ps #(parameter bit C2H_ONLY = 0, parameter bit C2H_DESC_TYPE = 0, parameter C2H_DESC_WIDTH = C2H_DESC_TYPE ? 128 : 256, - + parameter PCIS_VALID_ADDR_WIDTH = 14, // This represents the address bits required for the 16KB window - + parameter C2H_PCIS_DESC_APERTURE = 14'h1000, parameter H2C_PCIS_DESC_APERTURE = 14'h1000, parameter H2C_PCIS_PKT_APERTURE = 14'h1000, @@ -36,11 +39,11 @@ module sde_ps #(parameter bit C2H_ONLY = 0, parameter PM_PCIS_CFG_APERTURE = 14'h0200, parameter C2H_PCIS_CFG_APERTURE = 14'h0600, parameter H2C_PCIS_CFG_APERTURE = 14'h0600, - + parameter bit H2C_DESC_TYPE = 0, parameter H2C_DESC_WIDTH = H2C_DESC_TYPE ? 128 : 256, - - + + parameter H2C_PKT_SIZE_BYTES = 64, parameter H2C_PKT_WIDTH = H2C_PKT_SIZE_BYTES*8, @@ -84,22 +87,22 @@ module sde_ps #(parameter bit C2H_ONLY = 0, output logic c2h_sync_rst_n, output logic h2c_sync_rst_n, output logic pm_sync_rst_n, - + // PCIS to C2H Descriptor output logic c2h_ps_desc_wr_req, output logic [C2H_DESC_WIDTH-1:0] c2h_ps_desc_wdata, input c2h_ps_desc_ack, - + // PCIS to H2C Descriptor output logic h2c_ps_desc_wr_req, output logic [H2C_DESC_WIDTH-1:0] h2c_ps_desc_wdata, input h2c_ps_desc_ack, - + // PCIS to H2C Small Pkt Buffer output logic h2c_ps_pkt_wr_req, output logic [H2C_PKT_WIDTH-1:0] h2c_ps_pkt_wdata, input h2c_ps_pkt_ack, - + // PCIS to PM Config Interface output logic pm_ps_cfg_wr_req, output logic pm_ps_cfg_rd_req, @@ -107,7 +110,7 @@ module sde_ps #(parameter bit C2H_ONLY = 0, output logic [31:0] pm_ps_cfg_wdata, input pm_ps_cfg_ack, input [31:0] pm_ps_cfg_rdata, - + // PCIS to C2H Config Interface output logic c2h_ps_cfg_wr_req, @@ -120,7 +123,7 @@ module sde_ps #(parameter bit C2H_ONLY = 0, output logic c2h_desc_ooo_error, output logic c2h_desc_unalin_error, - + // PCIS to H2C Config Interface output logic h2c_ps_cfg_wr_req, output logic h2c_ps_cfg_rd_req, @@ -128,11 +131,11 @@ module sde_ps #(parameter bit C2H_ONLY = 0, output logic [31:0] h2c_ps_cfg_wdata, input h2c_ps_cfg_ack, input [31:0] h2c_ps_cfg_rdata, - + output logic h2c_desc_ooo_error, output logic h2c_desc_unalin_error - + ); // Remove these flops to save area (but timing will be tight) @@ -142,7 +145,7 @@ module sde_ps #(parameter bit C2H_ONLY = 0, logic pcis_wlast_q; logic pcis_wvalid_q; logic pcis_wready_q; - + // PCIS FSM typedef enum logic [3:0] { PCIS_REQ_IDLE = 4'd0, @@ -172,11 +175,11 @@ module sde_ps #(parameter bit C2H_ONLY = 0, logic pcis_req_h2c_cfg; logic pcis_req_rd_dummy; logic pcis_req_wr_dummy; - + logic c2h_pcis_desc_wready; logic h2c_pcis_desc_wready; logic h2c_pcis_pkt_wready; - + logic pm_pcis_cfg_wready; logic pm_pcis_cfg_rvalid; logic [31:0] pm_pcis_cfg_rdata; @@ -192,14 +195,14 @@ module sde_ps #(parameter bit C2H_ONLY = 0, logic h2c_pcis_cfg_wready; logic h2c_pcis_cfg_rvalid; logic [31:0] h2c_pcis_cfg_rdata; - + logic ps_ps_cfg_wr_req; logic ps_ps_cfg_rd_req; logic [15:0] ps_ps_cfg_addr; logic [31:0] ps_ps_cfg_wdata; logic ps_ps_cfg_ack; logic [31:0] ps_ps_cfg_rdata; - + localparam WR_CH_IN_FIFO_WIDTH = PCIS_DATA_WIDTH + 1 + (PCIS_DATA_WIDTH>>3); localparam WR_CH_IN_FIFO_DEPTH_MINUS1 = WR_CH_IN_FIFO_DEPTH - 1; logic [WR_CH_IN_FIFO_WIDTH-1:0] wr_ch_in_ff_pop_data; @@ -227,35 +230,35 @@ module sde_ps #(parameter bit C2H_ONLY = 0, // .watermark (wr_ch_in_ff_full), // .data_valid (wr_ch_in_ff_valid) // ); -// +// // assign wr_ch_in_ff_pop = wr_ch_in_ff_valid & pcis_wready_q; // assign {pcis_wlast_q, pcis_wstrb_q, pcis_wdata_q} = wr_ch_in_ff_pop_data; // assign pcis_wvalid_q = wr_ch_in_ff_valid; // assign pcis_wready = ~wr_ch_in_ff_full; assign {pcis_wvalid_q, pcis_wlast_q, pcis_wstrb_q, pcis_wdata_q} = {pcis_wvalid, pcis_wlast, pcis_wstrb, pcis_wdata}; - assign pcis_wready = pcis_wready_q; - + assign pcis_wready = pcis_wready_q; + always @(posedge clk) if (!rst_n) pcis_req_state <= PCIS_REQ_IDLE; - else + else pcis_req_state <= pcis_req_state_next; always_comb begin pcis_req_state_next = pcis_req_state; case (pcis_req_state) - + PCIS_REQ_IDLE: if (pcis_awvalid || pcis_arvalid) pcis_req_state_next = PCIS_REQ_AW_AR; else pcis_req_state_next = PCIS_REQ_IDLE; - + PCIS_REQ_AW_AR: pcis_req_state_next = PCIS_REQ_DEC; - + PCIS_REQ_DEC: if (pcis_req_c2h_wr_desc || pcis_req_h2c_wr_desc) pcis_req_state_next = PCIS_REQ_WR_DESC; @@ -265,9 +268,9 @@ module sde_ps #(parameter bit C2H_ONLY = 0, pcis_req_state_next = PCIS_REQ_CFG; else if (pcis_req_rd_n_wr) pcis_req_state_next = PCIS_REQ_RESP; - else + else pcis_req_state_next = PCIS_REQ_WR_DUMMY; - + PCIS_REQ_CFG: if ((pcis_req_pm_cfg & ((pcis_req_rd_n_wr & pm_pcis_cfg_rvalid ) || (~pcis_req_rd_n_wr & pm_pcis_cfg_wready ))) || (pcis_req_ps_cfg & ((pcis_req_rd_n_wr & ps_pcis_cfg_rvalid ) || (~pcis_req_rd_n_wr & ps_pcis_cfg_wready ))) || @@ -284,13 +287,13 @@ module sde_ps #(parameter bit C2H_ONLY = 0, pcis_req_state_next = PCIS_REQ_RESP; else pcis_req_state_next = PCIS_REQ_WR_DESC; - + PCIS_REQ_WR_PKT: if (pcis_wvalid_q & pcis_wlast_q & pcis_req_h2c_wr_pkt & h2c_pcis_pkt_wready) pcis_req_state_next = PCIS_REQ_RESP; else pcis_req_state_next = PCIS_REQ_WR_PKT; - + PCIS_REQ_WR_DUMMY: if (pcis_wvalid_q & pcis_wlast_q) pcis_req_state_next = PCIS_REQ_RESP; @@ -307,17 +310,17 @@ module sde_ps #(parameter bit C2H_ONLY = 0, pcis_req_state_next = PCIS_REQ_IDLE; else pcis_req_state_next = PCIS_REQ_RESP; - + default: pcis_req_state_next = pcis_req_state; - + endcase // case pcis_req_state end // else: !if(!rst_n) // Save request info always @(posedge clk) - if (!rst_n) + if (!rst_n) {pcis_req_id, pcis_req_size, pcis_req_len, pcis_req_addr, pcis_req_rd_n_wr} <= '{default:'0}; else begin if ((pcis_req_state == PCIS_REQ_IDLE) && pcis_awvalid) @@ -346,16 +349,16 @@ module sde_ps #(parameter bit C2H_ONLY = 0, localparam PS_PCIS_CFG_ADDR_START = H2C_PCIS_PKT_ADDR_END; localparam PS_PCIS_CFG_ADDR_END = PS_PCIS_CFG_ADDR_START + PS_PCIS_CFG_APERTURE; - + localparam PM_PCIS_CFG_ADDR_START = PS_PCIS_CFG_ADDR_END; localparam PM_PCIS_CFG_ADDR_END = PM_PCIS_CFG_ADDR_START + PM_PCIS_CFG_APERTURE; - + localparam C2H_PCIS_CFG_ADDR_START = PM_PCIS_CFG_ADDR_END; localparam C2H_PCIS_CFG_ADDR_END = C2H_PCIS_CFG_ADDR_START + C2H_PCIS_CFG_APERTURE; - + localparam H2C_PCIS_CFG_ADDR_START = C2H_PCIS_CFG_ADDR_END; localparam H2C_PCIS_CFG_ADDR_END = H2C_PCIS_CFG_ADDR_START + H2C_PCIS_CFG_APERTURE; - + // Decode addresses always @(posedge clk) if (!rst_n) begin @@ -371,24 +374,24 @@ module sde_ps #(parameter bit C2H_ONLY = 0, end else begin if (pcis_req_state == PCIS_REQ_AW_AR) begin - pcis_req_c2h_wr_desc <= ~pcis_req_rd_n_wr && + pcis_req_c2h_wr_desc <= ~pcis_req_rd_n_wr && (pcis_req_addr >= C2H_PCIS_DESC_ADDR_START) && (pcis_req_addr < C2H_PCIS_DESC_ADDR_END); - - pcis_req_h2c_wr_desc <= ~pcis_req_rd_n_wr && + + pcis_req_h2c_wr_desc <= ~pcis_req_rd_n_wr && (pcis_req_addr >= H2C_PCIS_DESC_ADDR_START) && (pcis_req_addr < H2C_PCIS_DESC_ADDR_END); - pcis_req_h2c_wr_pkt <= ~pcis_req_rd_n_wr && + pcis_req_h2c_wr_pkt <= ~pcis_req_rd_n_wr && ((pcis_req_addr >= H2C_PCIS_PKT_ADDR_START) && (pcis_req_addr < H2C_PCIS_PKT_ADDR_END)); pcis_req_ps_cfg <= (pcis_req_addr >= PS_PCIS_CFG_ADDR_START ) && (pcis_req_addr < PS_PCIS_CFG_ADDR_END ); pcis_req_pm_cfg <= (pcis_req_addr >= PM_PCIS_CFG_ADDR_START ) && (pcis_req_addr < PM_PCIS_CFG_ADDR_END ); pcis_req_c2h_cfg <= (pcis_req_addr >= C2H_PCIS_CFG_ADDR_START) && (pcis_req_addr < C2H_PCIS_CFG_ADDR_END); pcis_req_h2c_cfg <= (pcis_req_addr >= H2C_PCIS_CFG_ADDR_START) && (pcis_req_addr < H2C_PCIS_CFG_ADDR_END); - - pcis_req_rd_dummy <= pcis_req_rd_n_wr && + + pcis_req_rd_dummy <= pcis_req_rd_n_wr && ((pcis_req_addr < C2H_PCIS_DESC_ADDR_START) || (pcis_req_addr >= H2C_PCIS_CFG_ADDR_END) || ((pcis_req_addr >= C2H_PCIS_DESC_ADDR_START) && (pcis_req_addr < H2C_PCIS_PKT_ADDR_END))); - + pcis_req_wr_dummy <= ~pcis_req_rd_n_wr && ((pcis_req_addr < C2H_PCIS_DESC_ADDR_START) || (pcis_req_addr >= H2C_PCIS_CFG_ADDR_END)); end // if (pcis_req_state == PCIS_REQ_AW_AR) @@ -403,9 +406,9 @@ module sde_ps #(parameter bit C2H_ONLY = 0, pcis_req_rd_dummy <= pcis_req_rd_dummy ; pcis_req_wr_dummy <= pcis_req_wr_dummy ; end // else: !if(pcis_req_state == PCIS_REQ_AW_AR) - + end // else: !if(!rst_n) - + // AW & AR Channel always @(posedge clk) if (!rst_n) begin @@ -417,7 +420,7 @@ module sde_ps #(parameter bit C2H_ONLY = 0, pcis_arready <= pcis_req_rd_n_wr & (pcis_req_state == PCIS_REQ_AW_AR); end - assign pcis_wready_q = (pcis_req_c2h_wr_desc & c2h_pcis_desc_wready) || + assign pcis_wready_q = (pcis_req_c2h_wr_desc & c2h_pcis_desc_wready) || (pcis_req_h2c_wr_desc & h2c_pcis_desc_wready) || (pcis_req_h2c_wr_pkt & h2c_pcis_pkt_wready) || (pcis_req_ps_cfg & ps_pcis_cfg_wready ) || @@ -425,7 +428,7 @@ module sde_ps #(parameter bit C2H_ONLY = 0, (pcis_req_c2h_cfg & c2h_pcis_cfg_wready) || (pcis_req_h2c_cfg & h2c_pcis_cfg_wready) || pcis_req_wr_dummy; - + // B Channel always @(posedge clk) if (!rst_n) begin @@ -438,14 +441,14 @@ module sde_ps #(parameter bit C2H_ONLY = 0, end assign pcis_bid = pcis_req_id; assign pcis_bresp = 2'b00; - + // R Channel logic [PCIS_LEN_WIDTH-1:0] pcis_req_read_len; logic [31:0] cfg_pcis_rdata; - - assign cfg_pcis_rdata = pcis_req_ps_cfg ? ps_pcis_cfg_rdata : - pcis_req_pm_cfg ? pm_pcis_cfg_rdata : - pcis_req_c2h_cfg ? c2h_pcis_cfg_rdata : + + assign cfg_pcis_rdata = pcis_req_ps_cfg ? ps_pcis_cfg_rdata : + pcis_req_pm_cfg ? pm_pcis_cfg_rdata : + pcis_req_c2h_cfg ? c2h_pcis_cfg_rdata : pcis_req_h2c_cfg ? h2c_pcis_cfg_rdata : 32'hbaad_0000; always @(posedge clk) if (!rst_n) begin @@ -456,19 +459,19 @@ module sde_ps #(parameter bit C2H_ONLY = 0, pcis_req_read_len <= 0; end else begin - pcis_rvalid <= pcis_rvalid && pcis_rready && (pcis_req_read_len == 0) ? 1'b0 : - (pcis_req_state == PCIS_REQ_RESP) && pcis_req_rd_n_wr ? 1'b1 : + pcis_rvalid <= pcis_rvalid && pcis_rready && (pcis_req_read_len == 0) ? 1'b0 : + (pcis_req_state == PCIS_REQ_RESP) && pcis_req_rd_n_wr ? 1'b1 : pcis_rvalid; pcis_rdata <= cfg_pcis_rdata << {pcis_req_addr[5:2], 5'd0}; pcis_rlast <= (pcis_req_state == PCIS_REQ_RESP) && pcis_req_rd_n_wr && (pcis_req_read_len == 0); - + pcis_req_read_len <= pcis_arvalid & pcis_arready ? pcis_arlen : pcis_rvalid & pcis_rready ? pcis_req_read_len - 1 : pcis_req_read_len; end // else: !if(!rst_n) assign pcis_rid = pcis_req_id; assign pcis_rresp = 2'b00; - + // W Channel to C2H Descriptor logic c2h_pcis_req_wr_desc; assign c2h_pcis_req_wr_desc = pcis_req_active & pcis_req_c2h_wr_desc; @@ -493,7 +496,7 @@ module sde_ps #(parameter bit C2H_ONLY = 0, .acc_wdata (c2h_ps_desc_wdata), .acc_ack (c2h_ps_desc_ack) ); - + // W Channel to H2C Descriptor logic h2c_pcis_req_wr_desc; assign h2c_pcis_req_wr_desc = pcis_req_active & pcis_req_h2c_wr_desc; @@ -518,7 +521,7 @@ module sde_ps #(parameter bit C2H_ONLY = 0, .acc_wdata (h2c_ps_desc_wdata), .acc_ack (h2c_ps_desc_ack) ); - + // // W Channel to H2C Pkt Buffer // logic h2c_pcis_req_wr_pkt; // assign h2c_pcis_req_wr_pkt = pcis_req_active & pcis_req_h2c_wr_pkt; @@ -541,11 +544,11 @@ module sde_ps #(parameter bit C2H_ONLY = 0, // .acc_wdata (h2c_ps_pkt_wdata), // .acc_ack (h2c_ps_pkt_ack) // ); -// +// assign h2c_pcis_pkt_wready = 0; assign h2c_ps_pkt_wr_req = 0; assign h2c_ps_pkt_wdata = ({H2C_PKT_WIDTH{1'b0}}); - + // W Channel to PM Cfg // R Channel from PM Cfg always @(posedge clk) @@ -554,7 +557,7 @@ module sde_ps #(parameter bit C2H_ONLY = 0, pm_ps_cfg_rd_req <= 0; pm_ps_cfg_addr <= '{default:'0}; pm_ps_cfg_wdata <= '{default:'0}; - pm_pcis_cfg_wready <= 0; + pm_pcis_cfg_wready <= 0; pm_pcis_cfg_rvalid <= 0; pm_pcis_cfg_rdata <= '{default:'0}; end @@ -570,7 +573,7 @@ module sde_ps #(parameter bit C2H_ONLY = 0, pm_ps_cfg_addr <= ~(pm_ps_cfg_wr_req || pm_ps_cfg_rd_req) ? pcis_req_addr - PM_PCIS_CFG_ADDR_START : pm_ps_cfg_addr; pm_ps_cfg_wdata <= ~(pm_ps_cfg_wr_req || pm_ps_cfg_rd_req) ? (pcis_wdata_q >> {pcis_req_addr[5:2], 5'd0}) : pm_ps_cfg_wdata; - + pm_pcis_cfg_wready <= pm_ps_cfg_wr_req & pm_ps_cfg_ack; pm_pcis_cfg_rvalid <= pm_ps_cfg_rd_req & pm_ps_cfg_ack; @@ -578,7 +581,7 @@ module sde_ps #(parameter bit C2H_ONLY = 0, pm_pcis_cfg_rdata <= pm_ps_cfg_rd_req & pm_ps_cfg_ack ? pm_ps_cfg_rdata : pm_pcis_cfg_rdata; end // else: !if(!rst_n) - + // W Channel to PS Cfg // R Channel from PS Cfg always @(posedge clk) @@ -587,7 +590,7 @@ module sde_ps #(parameter bit C2H_ONLY = 0, ps_ps_cfg_rd_req <= 0; ps_ps_cfg_addr <= '{default:'0}; ps_ps_cfg_wdata <= '{default:'0}; - ps_pcis_cfg_wready <= 0; + ps_pcis_cfg_wready <= 0; ps_pcis_cfg_rvalid <= 0; ps_pcis_cfg_rdata <= '{default:'0}; end @@ -603,7 +606,7 @@ module sde_ps #(parameter bit C2H_ONLY = 0, ps_ps_cfg_addr <= ~(ps_ps_cfg_wr_req || ps_ps_cfg_rd_req) ? pcis_req_addr - PS_PCIS_CFG_ADDR_START : ps_ps_cfg_addr; ps_ps_cfg_wdata <= ~(ps_ps_cfg_wr_req || ps_ps_cfg_rd_req) ? (pcis_wdata_q >> {pcis_req_addr[5:2], 5'd0}) : ps_ps_cfg_wdata; - + ps_pcis_cfg_wready <= ps_ps_cfg_wr_req & ps_ps_cfg_ack; ps_pcis_cfg_rvalid <= ps_ps_cfg_rd_req & ps_ps_cfg_ack; @@ -620,7 +623,7 @@ module sde_ps #(parameter bit C2H_ONLY = 0, c2h_ps_cfg_rd_req <= 0; c2h_ps_cfg_addr <= '{default:'0}; c2h_ps_cfg_wdata <= '{default:'0}; - c2h_pcis_cfg_wready <= 0; + c2h_pcis_cfg_wready <= 0; c2h_pcis_cfg_rvalid <= 0; c2h_pcis_cfg_rdata <= '{default:'0}; end @@ -636,7 +639,7 @@ module sde_ps #(parameter bit C2H_ONLY = 0, c2h_ps_cfg_addr <= ~(c2h_ps_cfg_wr_req || c2h_ps_cfg_rd_req) ? pcis_req_addr - C2H_PCIS_CFG_ADDR_START : c2h_ps_cfg_addr; c2h_ps_cfg_wdata <= ~(c2h_ps_cfg_wr_req || c2h_ps_cfg_rd_req) ? (pcis_wdata_q >> {pcis_req_addr[5:2], 5'd0}) : c2h_ps_cfg_wdata; - + c2h_pcis_cfg_wready <= c2h_ps_cfg_wr_req & c2h_ps_cfg_ack; c2h_pcis_cfg_rvalid <= c2h_ps_cfg_rd_req & c2h_ps_cfg_ack; @@ -644,7 +647,7 @@ module sde_ps #(parameter bit C2H_ONLY = 0, c2h_pcis_cfg_rdata <= c2h_ps_cfg_rd_req & c2h_ps_cfg_ack ? c2h_ps_cfg_rdata : c2h_pcis_cfg_rdata; end // else: !if(!rst_n) - + // W Channel to H2C Cfg // R Channel from H2C Cfg always @(posedge clk) @@ -653,7 +656,7 @@ module sde_ps #(parameter bit C2H_ONLY = 0, h2c_ps_cfg_rd_req <= 0; h2c_ps_cfg_addr <= '{default:'0}; h2c_ps_cfg_wdata <= '{default:'0}; - h2c_pcis_cfg_wready <= 0; + h2c_pcis_cfg_wready <= 0; h2c_pcis_cfg_rvalid <= 0; h2c_pcis_cfg_rdata <= '{default:'0}; end @@ -669,7 +672,7 @@ module sde_ps #(parameter bit C2H_ONLY = 0, h2c_ps_cfg_addr <= ~(h2c_ps_cfg_wr_req || h2c_ps_cfg_rd_req) ? pcis_req_addr - H2C_PCIS_CFG_ADDR_START : h2c_ps_cfg_addr; h2c_ps_cfg_wdata <= ~(h2c_ps_cfg_wr_req || h2c_ps_cfg_rd_req) ? (pcis_wdata_q >> {pcis_req_addr[5:2], 5'd0}) : h2c_ps_cfg_wdata; - + h2c_pcis_cfg_wready <= h2c_ps_cfg_wr_req & h2c_ps_cfg_ack; h2c_pcis_cfg_rvalid <= h2c_ps_cfg_rd_req & h2c_ps_cfg_ack; @@ -681,11 +684,11 @@ module sde_ps #(parameter bit C2H_ONLY = 0, // Local Config Registers // TODO: // Temporarily no registers - + logic ps_ps_cfg_rd_ack; logic ps_ps_cfg_wr_ack; logic cfg_ps_reset; - + assign ps_ps_cfg_ack = ps_ps_cfg_wr_req ? ps_ps_cfg_wr_ack : ps_ps_cfg_rd_ack; ///////////////////////////////////////////////// @@ -701,7 +704,7 @@ module sde_ps #(parameter bit C2H_ONLY = 0, // 15:1 - RSVD // 16 - H2C Present // 31:17 - RSVD - + // Register Writes always @(posedge clk) if (!rst_n) begin @@ -709,7 +712,7 @@ module sde_ps #(parameter bit C2H_ONLY = 0, cfg_ps_reset <= 0; end else if (ps_ps_cfg_wr_req) begin - case (c2h_ps_cfg_addr[8:0]) + case (c2h_ps_cfg_addr[8:0]) 9'h000 : begin ps_ps_cfg_wr_ack <= 1; cfg_ps_reset <= ps_ps_cfg_wdata; @@ -719,7 +722,7 @@ module sde_ps #(parameter bit C2H_ONLY = 0, end endcase // case (c2h_ps_cfg_addr[8:0]) end // if (ps_ps_cfg_wr_req) - + logic [15:0] cfg_c2h_present; logic [15:0] cfg_h2c_present; logic h2c_only; @@ -727,10 +730,10 @@ module sde_ps #(parameter bit C2H_ONLY = 0, assign h2c_only = H2C_ONLY; assign c2h_only = C2H_ONLY; - + assign cfg_c2h_present = {15'd0, ~h2c_only}; assign cfg_h2c_present = {15'd0, ~c2h_only}; - + // Signals based on writes always @(posedge clk) if (!rst_n) begin @@ -765,10 +768,10 @@ module sde_ps #(parameter bit C2H_ONLY = 0, h2c_sync_rst_n <= ~cfg_ps_reset; pm_sync_rst_n <= ~cfg_ps_reset; end // else: !if(!rst_n) - - + + // `ifndef NO_SDE_DEBUG_ILA -// +// // ila_sde_ps SDE_PS_ILA (.clk (clk), // .probe0 (c2h_ps_desc_wr_req ), // .probe1 (c2h_ps_desc_wdata ), @@ -816,11 +819,10 @@ module sde_ps #(parameter bit C2H_ONLY = 0, // .probe43 (pcis_req_wr_dummy ), // .probe44 (c2h_pcis_req_wr_desc ), // .probe45 (h2c_pcis_req_wr_desc ), -// .probe46 (h2c_pcis_req_wr_pkt ) +// .probe46 (h2c_pcis_req_wr_pkt ) // ); -// +// // `endif // `ifndef NO_SDE_DEBUG_ILA - - -endmodule // sde_ps + +endmodule // sde_ps diff --git a/hdk/cl/examples/cl_sde/design/sde_ps_acc.sv b/hdk/cl/examples/cl_sde/design/sde_ps_acc.sv index b4e8b6a17..00f8e15d6 100644 --- a/hdk/cl/examples/cl_sde/design/sde_ps_acc.sv +++ b/hdk/cl/examples/cl_sde/design/sde_ps_acc.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016-2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + // SDE PCIS Accumulator diff --git a/hdk/cl/examples/cl_sde/design/sde_wb.sv b/hdk/cl/examples/cl_sde/design/sde_wb.sv index 12eb10cb2..a394c2cf7 100644 --- a/hdk/cl/examples/cl_sde/design/sde_wb.sv +++ b/hdk/cl/examples/cl_sde/design/sde_wb.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016-2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + // Write Back @@ -20,7 +23,7 @@ module sde_wb #(parameter bit H2C_N_C2H = 0, // 0 - C2H, 1 - H2C parameter PCIM_WB_AWID = 1, // This is the ID used for write accesses from Write Back Block parameter DESC_RAM_DEPTH = 64, - + parameter PCIM_DATA_WIDTH = 512, parameter PCIM_ID_WIDTH = 3, parameter PCIM_LEN_WIDTH = 8, @@ -47,11 +50,11 @@ module sde_wb #(parameter bit H2C_N_C2H = 0, // 0 - C2H, 1 - H2C output logic [15:0] wb_cfg_md_wr_ptr, input cfg_wb_clr_wr_ptr, - input cfg_wb_desc_error, - input cfg_wb_dm_error, + input cfg_wb_desc_error, + input cfg_wb_dm_error, input cfg_wb_wb_error, output logic [31:0] wb_cfg_status_dw, - + input cfg_desc_clr_cdt_limit, input cfg_desc_clr_desc_cnt, input cfg_axis_clr_pkt_cnt, @@ -63,12 +66,12 @@ module sde_wb #(parameter bit H2C_N_C2H = 0, // 0 - C2H, 1 - H2C input [19:0] cfg_wc_tick_cnt, input [3:0] cfg_wc_to_cnt, input [5:0] cfg_wc_cnt_minus1, - + output logic wb_cfg_md_bresp_err, output logic wb_cfg_sts_bresp_err, - + output logic [63:0] wb_cfg_bresp_err_addr, - + // Desc to Write-Back input desc_wb_limit_req, input [31:0] desc_wb_limit, @@ -79,7 +82,7 @@ module sde_wb #(parameter bit H2C_N_C2H = 0, // 0 - C2H, 1 - H2C // AXIS to Write-Back input axis_wb_pkt_cnt_req, input [31:0] axis_wb_pkt_cnt, - + // Data Mover to Write-Block Request input dm_wb_md_req, input sde_pkg::c2h_reg_wb_t dm_wb_md, // Used for C2H Only @@ -91,7 +94,7 @@ module sde_wb #(parameter bit H2C_N_C2H = 0, // 0 - C2H, 1 - H2C output logic [PCIM_LEN_WIDTH-1:0] wb_pm_awlen, output logic [PCIM_ID_WIDTH-1:0] wb_pm_awid, input pm_wb_awready, - + // Write Data to PCIM output logic wb_pm_wvalid, output logic [PCIM_DATA_WIDTH-1:0] wb_pm_wdata, @@ -117,15 +120,15 @@ module sde_wb #(parameter bit H2C_N_C2H = 0, // 0 - C2H, 1 - H2C localparam WB_STATUS_NUM_BYTES = H2C_N_C2H ? (4*4) : (5*4); // 5 DWs for C2H, 4 DWs for H2C localparam MD_PTR_WIDTH = 16; // This dictates the maximum buffer size for Write-Back Metadata - // For example, - // With MD_PTR_WIDTH = 16, the maximum number of metadata entries = 65536. + // For example, + // With MD_PTR_WIDTH = 16, the maximum number of metadata entries = 65536. // for regular type write-back metadata (16B), maximum WB buffer size = 16B * 65536 = 1MB // for compact type write-back metadata (8B) , maximum WB buffer size = 8B * 65536 = 512KB localparam WDATA_TO_SEND_WIDTH = WB_STATUS_NUM_BYTES*8 > WB_MD_WIDTH ? WB_STATUS_NUM_BYTES*8 : WB_MD_WIDTH; localparam WSTRB_TO_SEND_WIDTH = WDATA_TO_SEND_WIDTH >> 3; - - typedef enum logic [REQUESTER_WIDTH-1:0] + + typedef enum logic [REQUESTER_WIDTH-1:0] { WB_STATUS = 0, WB_METADATA = 1 @@ -140,7 +143,7 @@ module sde_wb #(parameter bit H2C_N_C2H = 0, // 0 - C2H, 1 - H2C logic md_wr_ptr_req; logic start_new_req; - + logic bresp_prealloc_avail; logic wr_done; logic do_arb; @@ -201,7 +204,7 @@ module sde_wb #(parameter bit H2C_N_C2H = 0, // 0 - C2H, 1 - H2C logic [MD_PTR_WIDTH:0] md_wr_ptr_plus1_rovr; logic md_ring_full; logic [63:0] md_wr_addr; - + logic [31:0] status_dw; logic [31:0] status_dw_q; logic [31:0] status_dw_sent; @@ -209,57 +212,57 @@ module sde_wb #(parameter bit H2C_N_C2H = 0, // 0 - C2H, 1 - H2C // Status DW Definition // 0 - Descriptor Error // 1 - Data Mover Error - // 2 - Write Back Error + // 2 - Write Back Error assign status_dw = {cfg_wb_wb_error, cfg_wb_dm_error, cfg_wb_desc_error}; assign wb_cfg_status_dw = status_dw; - + if (~H2C_N_C2H) begin - + always @(posedge clk) - if (!rst_n) + if (!rst_n) num_md_in_ring <= 0; else num_md_in_ring <= cfg_wb_md_ring_size >> WB_MD_WIDTH_BYTES_LOG2; - + assign md_wr_ptr_next_inc = md_wr_ptr + 1; assign md_wr_ptr_next_inc_rovr = md_wr_ptr_next_inc - num_md_in_ring; assign md_wr_ptr_next = md_wr_ptr_next_inc >= num_md_in_ring ? md_wr_ptr_next_inc_rovr : md_wr_ptr_next_inc; - + // assign md_wr_ptr_next_plus1 = md_wr_ptr_next + 1; // assign md_wr_ptr_next_plus1_rovr = md_wr_ptr_next_plus1 >= num_md_in_ring ? 0 : md_wr_ptr_next_plus1; - - + + // Move write pointer always @(posedge clk) if (!rst_n) begin md_wr_ptr <= 0; md_wr_ptr_req <= 0; - + // md_ring_full <= 0; end else begin - md_wr_ptr <= cfg_wb_clr_wr_ptr ? 0 : + md_wr_ptr <= cfg_wb_clr_wr_ptr ? 0 : wr_done & (req_winner == WB_METADATA) ? md_wr_ptr_next : md_wr_ptr; md_wr_ptr_req <= wr_done & (req_winner == WB_METADATA); - - // md_ring_full <= wr_done & (req_winner == WB_METADATA) ? (md_wr_ptr_next_plus1_rovr == cfg_wb_md_rd_ptr) : + + // md_ring_full <= wr_done & (req_winner == WB_METADATA) ? (md_wr_ptr_next_plus1_rovr == cfg_wb_md_rd_ptr) : // (md_wr_ptr_plus1 >= num_md_in_ring); end // else: !if(!rst_n) - + assign wb_cfg_md_wr_ptr = md_wr_ptr; - + // assign md_wr_addr = (md_wr_ptr << $clog2(WB_MD_WIDTH_BYTES)) + cfg_wb_md_ring_addr; assign md_wr_addr[WB_MD_WIDTH_BYTES_LOG2-1:0] = cfg_wb_md_ring_addr[WB_MD_WIDTH_BYTES_LOG2-1:0]; assign md_wr_addr[47:WB_MD_WIDTH_BYTES_LOG2] = md_wr_ptr + cfg_wb_md_ring_addr[47:WB_MD_WIDTH_BYTES_LOG2]; assign md_wr_addr[63:48] = 16'd0; - - + + assign md_wr_ptr_plus1 = md_wr_ptr + 1; assign md_wr_ptr_plus1_rovr = (md_wr_ptr_plus1 >= num_md_in_ring) ? 0 : md_wr_ptr_plus1; assign md_ring_full = (md_wr_ptr_plus1_rovr == cfg_wb_md_rd_ptr); end // if (~H2C_N_C2H) - + else begin assign num_md_in_ring = 0; assign md_wr_ptr = 0; @@ -299,7 +302,7 @@ end // if (~H2C_N_C2H) logic [31:0] desc_wb_cnt_diff; logic [31:0] axis_wb_pkt_cnt_diff; logic [MD_PTR_WIDTH-1:0] md_wr_ptr_diff; - + assign cfg_desc_cdt_wc_to_cnt = cfg_desc_cdt_wc_en ? cfg_wc_to_cnt : 0; assign cfg_desc_cnt_wc_to_cnt = cfg_desc_cnt_wc_en ? cfg_wc_to_cnt : 0; assign cfg_pkt_cnt_wc_to_cnt = cfg_pkt_cnt_wc_en ? cfg_wc_to_cnt : 0; @@ -309,17 +312,17 @@ end // if (~H2C_N_C2H) assign cfg_desc_cnt_wc_cnt_m1 = cfg_desc_cnt_wc_en ? cfg_wc_cnt_minus1 : 0; assign cfg_pkt_cnt_wc_cnt_m1 = cfg_pkt_cnt_wc_en ? cfg_wc_cnt_minus1 : 0; assign cfg_md_wr_ptr_wc_cnt_m1 = cfg_md_wr_ptr_wc_en ? cfg_wc_cnt_minus1 : 0; - + assign desc_wb_limit_diff = (desc_wb_limit - desc_wb_limit_q); assign desc_wb_cnt_diff = desc_wb_cnt - desc_wb_cnt_q; assign axis_wb_pkt_cnt_diff = axis_wb_pkt_cnt - axis_wb_pkt_cnt_q; - assign md_wr_ptr_diff = (md_wr_ptr >= md_wr_ptr_q) ? md_wr_ptr - md_wr_ptr_q : + assign md_wr_ptr_diff = (md_wr_ptr >= md_wr_ptr_q) ? md_wr_ptr - md_wr_ptr_q : md_wr_ptr_q - md_wr_ptr; - + always @(posedge clk) if (!rst_n) begin wc_to_tick_cnt <= 0; - + desc_cdt_req_wc_cnt <= 0; desc_cnt_req_wc_cnt <= 0; pkt_cnt_req_wc_cnt <= 0; @@ -332,19 +335,19 @@ end // if (~H2C_N_C2H) end else begin wc_to_tick_cnt <= (wc_to_tick_cnt == 0) ? cfg_wc_tick_cnt : wc_to_tick_cnt - 1; - + desc_cdt_req_wc_cnt <= desc_wb_limit_diff; - + desc_cnt_req_wc_cnt <= desc_wb_cnt_diff; - + pkt_cnt_req_wc_cnt <= axis_wb_pkt_cnt_diff; - + md_wr_ptr_req_wc_cnt <= md_wr_ptr_diff; desc_cdt_req_wc_to_cnt <= desc_wb_limit_wc_req ? 0 : (desc_cdt_req_wc_cnt > 0) & (wc_to_tick_cnt == 0) & (desc_cdt_req_wc_to_cnt < 4'hF) ? desc_cdt_req_wc_to_cnt + 1 : desc_cdt_req_wc_to_cnt; - + desc_cnt_req_wc_to_cnt <= desc_wb_cnt_wc_req ? 0 : (desc_cnt_req_wc_cnt > 0) & (wc_to_tick_cnt == 0) & (desc_cnt_req_wc_to_cnt < 4'hF) ? desc_cnt_req_wc_to_cnt + 1 : desc_cnt_req_wc_to_cnt; @@ -352,19 +355,19 @@ end // if (~H2C_N_C2H) pkt_cnt_req_wc_to_cnt <= axis_wb_pkt_cnt_wc_req ? 0 : (pkt_cnt_req_wc_cnt > 0) & (wc_to_tick_cnt == 0) & (pkt_cnt_req_wc_to_cnt < 4'hF) ? pkt_cnt_req_wc_to_cnt + 1 : pkt_cnt_req_wc_to_cnt; - - md_wr_ptr_req_wc_to_cnt <= md_wr_ptr_wc_req ? 0 : + + md_wr_ptr_req_wc_to_cnt <= md_wr_ptr_wc_req ? 0 : (md_wr_ptr_req_wc_cnt > 0) & (wc_to_tick_cnt == 0) & (md_wr_ptr_req_wc_to_cnt < 4'hF) ? md_wr_ptr_req_wc_to_cnt + 1 : md_wr_ptr_req_wc_to_cnt; - + end // else: !if(!rst_n) assign desc_wb_limit_wc_req = ((desc_cdt_req_wc_to_cnt >= cfg_wc_to_cnt) || (desc_cdt_req_wc_cnt > cfg_desc_cdt_wc_cnt_m1 )) & (desc_cdt_req_wc_cnt > 0); assign desc_wb_cnt_wc_req = ((desc_cnt_req_wc_to_cnt >= cfg_wc_to_cnt) || (desc_cnt_req_wc_cnt > cfg_desc_cnt_wc_cnt_m1 )) & (desc_cnt_req_wc_cnt > 0); assign axis_wb_pkt_cnt_wc_req = ((pkt_cnt_req_wc_to_cnt >= cfg_wc_to_cnt) || (pkt_cnt_req_wc_cnt > cfg_pkt_cnt_wc_cnt_m1 )) & (pkt_cnt_req_wc_cnt > 0); assign md_wr_ptr_wc_req = ((md_wr_ptr_req_wc_to_cnt >= cfg_wc_to_cnt) || (md_wr_ptr_req_wc_cnt > cfg_md_wr_ptr_wc_cnt_m1)) & (md_wr_ptr_req_wc_cnt > 0); - - // Request Pending + + // Request Pending always @(posedge clk) if (!rst_n) begin dm_wb_md_req_pend <= 0; @@ -375,22 +378,22 @@ end // if (~H2C_N_C2H) md_wr_ptr_req_pend <= 0; end else begin - dm_wb_md_req_pend <= wr_done & (req_winner == WB_METADATA) ? 1'b0 : + dm_wb_md_req_pend <= wr_done & (req_winner == WB_METADATA) ? 1'b0 : dm_wb_md_req & ~(md_ring_full & cfg_wb_md_ptr_en) ? 1'b1 : dm_wb_md_req_pend; status_dw_req_pend <= wr_done & (req_winner == WB_STATUS) ? 1'b0 : (status_dw_sent != status_dw) ? 1'b1 : status_dw_req_pend; - desc_cdt_req_pend <= wr_done & (req_winner == WB_STATUS) ? 1'b0 : - desc_wb_limit_wc_req & cfg_wb_desc_cdt_en & (desc_wb_limit_sent != desc_wb_limit) ? 1'b1 : + desc_cdt_req_pend <= wr_done & (req_winner == WB_STATUS) ? 1'b0 : + desc_wb_limit_wc_req & cfg_wb_desc_cdt_en & (desc_wb_limit_sent != desc_wb_limit) ? 1'b1 : desc_cdt_req_pend; - desc_cnt_req_pend <= wr_done & (req_winner == WB_STATUS) ? 1'b0 : - desc_wb_cnt_wc_req & cfg_wb_desc_cnt_en & (desc_wb_cnt_sent != desc_wb_cnt) ? 1'b1 : + desc_cnt_req_pend <= wr_done & (req_winner == WB_STATUS) ? 1'b0 : + desc_wb_cnt_wc_req & cfg_wb_desc_cnt_en & (desc_wb_cnt_sent != desc_wb_cnt) ? 1'b1 : desc_cnt_req_pend; - pkt_cnt_req_pend <= wr_done & (req_winner == WB_STATUS) ? 1'b0 : - axis_wb_pkt_cnt_wc_req & cfg_wb_pkt_cnt_en & (axis_wb_pkt_cnt_sent != axis_wb_pkt_cnt) ? 1'b1 : + pkt_cnt_req_pend <= wr_done & (req_winner == WB_STATUS) ? 1'b0 : + axis_wb_pkt_cnt_wc_req & cfg_wb_pkt_cnt_en & (axis_wb_pkt_cnt_sent != axis_wb_pkt_cnt) ? 1'b1 : pkt_cnt_req_pend; - md_wr_ptr_req_pend <= wr_done & (req_winner == WB_STATUS) ? 1'b0 : - md_wr_ptr_wc_req & cfg_wb_md_ptr_en & (md_wr_ptr_sent != md_wr_ptr) ? 1'b1 : + md_wr_ptr_req_pend <= wr_done & (req_winner == WB_STATUS) ? 1'b0 : + md_wr_ptr_wc_req & cfg_wb_md_ptr_en & (md_wr_ptr_sent != md_wr_ptr) ? 1'b1 : md_wr_ptr_req_pend; end // else: !if(!rst_n) @@ -403,7 +406,7 @@ end // if (~H2C_N_C2H) // Arbitrate between 2 requests // Round Robin arbiter assign requester_arb_in = {dm_wb_md_req_pend, status_req_pend}; - + rr_arb #(.WINNER_WIDTH(REQUESTER_WIDTH), .REQ_WIDTH (NUM_REQUESTER), .DO_ARB_IS_CHANGE_STATE(1)) REQUESTER_RR_ARB (.clk (clk), @@ -413,13 +416,13 @@ end // if (~H2C_N_C2H) .winner (requester_arb_out) ); end // else: !if(H2C_N_C2H) - + assign accept_new_wb_req = ~start_new_req & ~wr_active & ~addr_active & bresp_prealloc_avail; assign new_wb_req = dm_wb_md_req_pend || status_req_pend; - + assign do_arb = ~addr_active & start_new_req; - + always @(posedge clk) if (!rst_n) begin start_new_req <= 0; @@ -427,43 +430,43 @@ end // if (~H2C_N_C2H) req_winner <= requester_t'(0); // status_req_qual <= 0; - + // md_req_qual <= 0; end else begin start_new_req <= accept_new_wb_req & new_wb_req; - - addr_active <= addr_active & addr_done ? 1'b0 : + + addr_active <= addr_active & addr_done ? 1'b0 : start_new_req ? 1'b1 : addr_active; - + req_winner <= start_new_req ? requester_t'(requester_arb_out) : req_winner; // status_req_qual <= start_new_req ? ((desc_cdt_req_pend & (desc_wb_limit_sent != desc_wb_limit)) || // (desc_cnt_req_pend & (desc_wb_cnt_sent != desc_wb_cnt) ) || // (pkt_cnt_req_pend & (axis_wb_pkt_cnt_sent != axis_wb_pkt_cnt)) || -// (md_wr_ptr_req_pend & (md_wr_ptr_sent != md_wr_ptr))) : +// (md_wr_ptr_req_pend & (md_wr_ptr_sent != md_wr_ptr))) : // status_req_qual; // md_req_qual <= start_new_req ? (dm_wb_md_req_pend & ~(md_ring_full & cfg_wb_md_ptr_en)) : md_req_qual; end // else: !if(!rst_n) assign status_req_qual = 1; - + assign md_req_qual = 1; - + assign req_qual = (req_winner == WB_STATUS) ? status_req_qual : md_req_qual; - + assign addr_done = addr_active & (~req_qual || (wb_pm_awvalid && pm_wb_awready)); - + assign addr_pipe_write_addr = (req_winner == WB_STATUS) ? cfg_wb_status_addr : md_wr_addr; assign addr_pipe_num_bytes = (req_winner == WB_METADATA) ? WB_MD_WIDTH_BYTES : WB_STATUS_NUM_BYTES; assign addr_pipe_num_bytes_adj = addr_pipe_num_bytes + addr_pipe_write_addr[PCIM_ADDR_BYTE_IDX_WIDTH-1:0]; - assign addr_pipe_num_beats_minus1 = (|addr_pipe_num_bytes_adj[0 +: PCIM_ADDR_BYTE_IDX_WIDTH]) ? (addr_pipe_num_bytes_adj >> PCIM_ADDR_BYTE_IDX_WIDTH) : + assign addr_pipe_num_beats_minus1 = (|addr_pipe_num_bytes_adj[0 +: PCIM_ADDR_BYTE_IDX_WIDTH]) ? (addr_pipe_num_bytes_adj >> PCIM_ADDR_BYTE_IDX_WIDTH) : (addr_pipe_num_bytes_adj >> PCIM_ADDR_BYTE_IDX_WIDTH) - 1; - - always @(posedge clk) + + always @(posedge clk) if (!rst_n) begin wb_pm_awvalid <= 0; wb_pm_awaddr <= '{default:'0}; @@ -478,7 +481,7 @@ end // if (~H2C_N_C2H) wb_pm_awlen <= addr_active & req_qual ? addr_pipe_num_beats_minus1 : wb_pm_awlen; wb_pm_awid <= PCIM_WB_AWID; end // else: !if(!rst_n) - + // Write Pipe // Decide if data has to be sent // Latch new data to send @@ -491,10 +494,10 @@ end // if (~H2C_N_C2H) wr_active_re_q <= 0; end else begin - wr_active <= wr_active & wr_done ? 1'b0 : + wr_active <= wr_active & wr_done ? 1'b0 : start_new_req ? 1'b1 : wr_active; - + // req_winner <= start_new_req ? 0 : // req_winner; @@ -503,9 +506,9 @@ end // if (~H2C_N_C2H) end // else: !if(!rst_n) assign wr_active_re = wr_active & ~wr_active_q; - + // Write Data FSM - // WR_IDLE + // WR_IDLE // WR_GET_DATA // WR_REQ typedef enum logic [1:0] {WR_IDLE = 0, @@ -513,7 +516,7 @@ end // if (~H2C_N_C2H) WR_REQ = 2} wr_state_t; wr_state_t wr_state, wr_state_next; always @(posedge clk) - if (!rst_n) + if (!rst_n) wr_state <= WR_IDLE; else wr_state <= wr_state_next; @@ -522,7 +525,7 @@ end // if (~H2C_N_C2H) wr_state_next = wr_state; case (wr_state) WR_IDLE : - if (wr_active & req_qual) + if (wr_active & req_qual) wr_state_next = WR_REQ ; // WR_GET_DATA; else wr_state_next = WR_IDLE; @@ -540,14 +543,14 @@ end // if (~H2C_N_C2H) end // always_comb // Data to send - always @(posedge clk) + always @(posedge clk) if (!rst_n) begin status_dw_q <= 0; desc_wb_limit_q <= DESC_RAM_DEPTH; desc_wb_cnt_q <= 0; axis_wb_pkt_cnt_q <= 0; md_wr_ptr_q <= 0; - + // desc_wb_limit_sent <= 0; // desc_wb_cnt_sent <= 0; // axis_wb_pkt_cnt_sent <= 0; @@ -555,18 +558,18 @@ end // if (~H2C_N_C2H) else begin status_dw_q <= (req_winner == WB_STATUS) & wr_active_re & req_qual ? status_dw : status_dw_q; - desc_wb_limit_q <= cfg_desc_clr_cdt_limit ? 0 : + desc_wb_limit_q <= cfg_desc_clr_cdt_limit ? 0 : (req_winner == WB_STATUS) & wr_active_re & req_qual ? desc_wb_limit : desc_wb_limit_q; - desc_wb_cnt_q <= cfg_desc_clr_desc_cnt ? 0 : + desc_wb_cnt_q <= cfg_desc_clr_desc_cnt ? 0 : (req_winner == WB_STATUS) & wr_active_re & req_qual ? desc_wb_cnt : desc_wb_cnt_q; - axis_wb_pkt_cnt_q <= cfg_axis_clr_pkt_cnt ? 0 : + axis_wb_pkt_cnt_q <= cfg_axis_clr_pkt_cnt ? 0 : (req_winner == WB_STATUS) & wr_active_re & req_qual ? axis_wb_pkt_cnt : axis_wb_pkt_cnt_q; - md_wr_ptr_q <= cfg_wb_clr_wr_ptr ? 0 : + md_wr_ptr_q <= cfg_wb_clr_wr_ptr ? 0 : (req_winner == WB_STATUS) & wr_active_re & req_qual ? md_wr_ptr : md_wr_ptr_q; - + // desc_wb_limit_sent <= (req_winner == WB_STATUS) & (wr_state == WR_REQ) & wr_done ? desc_wb_limit_q : // desc_wb_limit_sent; // desc_wb_cnt_sent <= (req_winner == WB_STATUS) & (wr_state == WR_REQ) & wr_done ? desc_wb_cnt_q : @@ -580,28 +583,28 @@ end // if (~H2C_N_C2H) assign desc_wb_cnt_sent = desc_wb_cnt_q; assign axis_wb_pkt_cnt_sent = axis_wb_pkt_cnt_q; assign md_wr_ptr_sent = md_wr_ptr_q; - + assign dm_wb_md_comp = sde_pkg::c2h_conv_wb_reg2comp(dm_wb_md); // assign wr_pipe_num_bytes = (req_winner == WB_METADATA) ? WB_MD_WIDTH_BYTES : 4; // assign wr_pipe_num_bytes_adj = wr_pipe_num_bytes + wr_pipe_lwr_addr; -// assign wr_pipe_num_beats_minus1 = (|wr_pipe_num_bytes_adj[0 +: PCIM_WR_BYTE_IDX_WIDTH]) ? (wr_pipe_num_bytes_adj >> PCIM_WR_BYTE_IDX_WIDTH) : +// assign wr_pipe_num_beats_minus1 = (|wr_pipe_num_bytes_adj[0 +: PCIM_WR_BYTE_IDX_WIDTH]) ? (wr_pipe_num_bytes_adj >> PCIM_WR_BYTE_IDX_WIDTH) : // (wr_pipe_num_bytes_adj >> PCIM_WR_BYTE_IDX_WIDTH) - 1; assign wr_pipe_num_beats_minus1 = addr_pipe_num_beats_minus1; - + // assign wr_pipe_addr = (req_winner == WB_STATUS) ? cfg_wb_status_addr : dm_wb_md_addr; assign wr_pipe_addr = addr_pipe_write_addr; - + assign wr_pipe_lwr_addr = wr_pipe_addr[0 +: PCIM_ADDR_BYTE_IDX_WIDTH]; - - assign wb_wr_max_bytes = wr_active_re_q & req_qual ? (PCIM_DATA_WIDTH_BYTES) - wr_pipe_lwr_addr[0 +: PCIM_ADDR_BYTE_IDX_WIDTH] : + + assign wb_wr_max_bytes = wr_active_re_q & req_qual ? (PCIM_DATA_WIDTH_BYTES) - wr_pipe_lwr_addr[0 +: PCIM_ADDR_BYTE_IDX_WIDTH] : PCIM_DATA_WIDTH_BYTES; assign wb_wr_num_bytes_total = (req_winner == WB_METADATA) ? WB_MD_WIDTH_BYTES : WB_STATUS_NUM_BYTES; assign wb_wr_num_bytes_remain = wb_wr_num_bytes_total - wb_wr_num_bytes_sent; - + assign wb_wr_num_bytes_to_send = wb_wr_num_bytes_remain < wb_wr_max_bytes ? wb_wr_num_bytes_remain : wb_wr_max_bytes; // always_comb begin @@ -612,7 +615,7 @@ end // if (~H2C_N_C2H) // end // end - if (DESC_TYPE) + if (DESC_TYPE) assign wb_wr_md = dm_wb_md_comp; else assign wb_wr_md = dm_wb_md; @@ -620,52 +623,52 @@ end // if (~H2C_N_C2H) assign wb_wr_data_to_send = (req_winner == WB_STATUS) ? {md_wr_ptr_q, axis_wb_pkt_cnt_q, desc_wb_cnt_q, desc_wb_limit_q, status_dw_q} : wb_wr_md; assign wb_wr_strb_to_send = (req_winner == WB_STATUS) ? {WB_STATUS_NUM_BYTES{1'b1}} : {WB_MD_WIDTH_BYTES{1'b1}}; - + always @(posedge clk) if (!rst_n) begin wb_wr_idx <= 0; wb_wr_num_bytes_sent <= 0; - + wb_pm_wvalid <= 0; wb_pm_wdata <= '{default:'0}; wb_pm_wstrb <= '{default:'0}; wb_pm_wlast <= 0; end else begin - wb_wr_idx <= wr_active_re_q & req_qual ? 0 : + wb_wr_idx <= wr_active_re_q & req_qual ? 0 : wb_pm_wvalid & pm_wb_wready ? wb_wr_idx + 1 : wb_wr_idx; wb_wr_num_bytes_sent <= wr_active_re_q & req_qual ? wb_wr_num_bytes_to_send : - wb_pm_wvalid & wb_pm_wlast & pm_wb_wready ? 0 : + wb_pm_wvalid & wb_pm_wlast & pm_wb_wready ? 0 : wb_pm_wvalid & pm_wb_wready ? wb_wr_num_bytes_sent + wb_wr_num_bytes_to_send : wb_wr_num_bytes_sent; - + wb_pm_wvalid <= wb_pm_wvalid & pm_wb_wready & (wb_wr_idx >= wr_pipe_num_beats_minus1) ? 1'b0 : wr_active_re_q & req_qual ? 1'b1 : wb_pm_wvalid; - wb_pm_wdata <= wr_active_re_q & req_qual ? wb_wr_data_to_send << ({wr_pipe_lwr_addr, 3'd0}) : + wb_pm_wdata <= wr_active_re_q & req_qual ? wb_wr_data_to_send << ({wr_pipe_lwr_addr, 3'd0}) : wb_pm_wvalid & pm_wb_wready ? wb_wr_data_to_send >> ({wb_wr_num_bytes_sent, 3'd0}) : wb_pm_wdata; wb_pm_wstrb <= wr_active_re_q & req_qual ? wb_wr_strb_to_send << wr_pipe_lwr_addr : - wb_pm_wvalid & pm_wb_wready ? wb_wr_strb_to_send >> wb_wr_num_bytes_sent : + wb_pm_wvalid & pm_wb_wready ? wb_wr_strb_to_send >> wb_wr_num_bytes_sent : wb_pm_wstrb; - - + + wb_pm_wlast <= wr_active_re_q & req_qual ? (wr_pipe_num_beats_minus1 == 0) : - wb_pm_wvalid & pm_wb_wready ? (wb_wr_idx >= (wr_pipe_num_beats_minus1 - 1)) : + wb_pm_wvalid & pm_wb_wready ? (wb_wr_idx >= (wr_pipe_num_beats_minus1 - 1)) : wb_pm_wlast; end // else: !if(!rst_n) - + assign wr_done = wr_active & (~req_qual || (wb_pm_wvalid && wb_pm_wlast && pm_wb_wready)); assign wb_dm_md_grant = wr_done & (req_winner == WB_METADATA); - + // BRESP track FIFO - // Need room for 2 BRESP + // Need room for 2 BRESP localparam WB_BRESP_TRK_FIFO_DEPTH_MINUS1 = WB_BRESP_TRK_FIFO_DEPTH - 1; localparam WB_BRESP_TRK_FIFO_WIDTH = REQUESTER_WIDTH + PCIM_ADDR_WIDTH; @@ -677,7 +680,7 @@ end // if (~H2C_N_C2H) logic wb_bresp_trk_ff_full; logic [REQUESTER_WIDTH-1:0] wb_bresp_trk_ff_pop_requester; logic [PCIM_ADDR_WIDTH-1:0] wb_bresp_trk_ff_pop_addr; - + flop_fifo_in #(.WIDTH(WB_BRESP_TRK_FIFO_WIDTH), .DEPTH(WB_BRESP_TRK_FIFO_DEPTH) ) WB_BRESP_TRK_FIFO (.clk (clk), @@ -695,7 +698,7 @@ end // if (~H2C_N_C2H) assign wb_bresp_trk_ff_push = wr_active & wr_done & req_qual & ~wb_bresp_trk_ff_full; assign wb_bresp_trk_ff_push_data = {req_winner, wr_pipe_addr}; - + assign wb_bresp_trk_ff_pop = wb_bresp_trk_ff_valid & pm_wb_bvalid; assign {wb_bresp_trk_ff_pop_requester, wb_bresp_trk_ff_pop_addr} = wb_bresp_trk_ff_pop_data; @@ -703,16 +706,16 @@ end // if (~H2C_N_C2H) logic bresp_prealloc_avail_cnt_inc; logic bresp_prealloc_avail_cnt_dec; logic [7:0] bresp_prealloc_avail_cnt; - + assign bresp_prealloc_avail_cnt_dec = start_new_req; assign bresp_prealloc_avail_cnt_inc = wb_bresp_trk_ff_pop; - + always @(posedge clk) if (!rst_n) bresp_prealloc_avail_cnt <= WB_BRESP_TRK_FIFO_DEPTH; else - bresp_prealloc_avail_cnt <= bresp_prealloc_avail_cnt_inc & ~bresp_prealloc_avail_cnt_dec ? bresp_prealloc_avail_cnt + 1 : - ~bresp_prealloc_avail_cnt_inc & bresp_prealloc_avail_cnt_dec ? bresp_prealloc_avail_cnt - 1 : + bresp_prealloc_avail_cnt <= bresp_prealloc_avail_cnt_inc & ~bresp_prealloc_avail_cnt_dec ? bresp_prealloc_avail_cnt + 1 : + ~bresp_prealloc_avail_cnt_inc & bresp_prealloc_avail_cnt_dec ? bresp_prealloc_avail_cnt - 1 : bresp_prealloc_avail_cnt; assign bresp_prealloc_avail = (bresp_prealloc_avail_cnt > 0); @@ -728,54 +731,54 @@ end // if (~H2C_N_C2H) wb_cfg_md_bresp_err <= wb_bresp_trk_ff_pop & (wb_bresp_trk_ff_pop_requester == WB_METADATA) & (pm_wb_bresp != 2'd0); wb_cfg_sts_bresp_err <= wb_bresp_trk_ff_pop & (wb_bresp_trk_ff_pop_requester == WB_STATUS) & (pm_wb_bresp != 2'd0); end // else: !if(!rst_n) - + assign wb_pm_bready = 1; - + //Simulation checks //synopsys translate_off logic [6:0] cfg_wc_cnt; logic wr_done_q; - + assign cfg_wc_cnt = cfg_wc_cnt_minus1 + 1; - + always @(posedge clk) if (rst_n) begin wr_done_q <= wr_done; - + if (cfg_wb_desc_cnt_en & cfg_desc_cdt_wc_en & (desc_wb_limit_q != 32'h0) & ~wr_done_q & ~desc_cdt_req_pend) assert (desc_wb_limit - desc_wb_limit_q <= (cfg_wc_cnt * 2)) else begin $display("%m: *** ERROR ***: Desc Limit Write Coalesce Error. desc_wb_limit = 0x%x, desc_wb_limit_q = 0x%x, cfg_wc_cnt = 0x%x. @ %0t", desc_wb_limit, desc_wb_limit_q, cfg_wc_cnt, $time); $finish; end - + if (cfg_wb_desc_cnt_en & cfg_desc_cnt_wc_en & ~wr_done_q & ~desc_cnt_req_pend) assert (desc_wb_cnt - desc_wb_cnt_q <= (cfg_wc_cnt * 2)) else begin $display("%m: *** ERROR ***: Desc Cnt Write Coalesce Error. desc_wb_cnt = 0x%x, desc_wb_cnt_q = 0x%x, cfg_wc_cnt = 0x%x. @ %0t", desc_wb_cnt, desc_wb_cnt_q, cfg_wc_cnt, $time); $finish; end - + if (cfg_wb_pkt_cnt_en & cfg_pkt_cnt_wc_en & ~wr_done_q & ~pkt_cnt_req_pend) assert (axis_wb_pkt_cnt - axis_wb_pkt_cnt_q <= (cfg_wc_cnt * 2)) else begin $display("%m: *** ERROR ***: AXIS Pkt Count Write Coalesce Error. axis_wb_pkt_cnt = 0x%x, axis_wb_pkt_cnt_q = 0x%x, cfg_wc_cnt = 0x%x. @ %0t", axis_wb_pkt_cnt, axis_wb_pkt_cnt_q, cfg_wc_cnt, $time); $finish; end - + if (cfg_wb_md_ptr_en & cfg_md_wr_ptr_wc_en && (md_wr_ptr >= md_wr_ptr_q) & ~wr_done_q & ~md_wr_ptr_req_pend) assert (md_wr_ptr - md_wr_ptr_q <= (cfg_wc_cnt * 2)) else begin $display("%m: *** ERROR ***: Desc Limit Write Coalesce Error. md_wr_ptr = 0x%x, md_wr_ptr_q = 0x%x, cfg_wc_cnt = 0x%x. @ %0t", md_wr_ptr, md_wr_ptr_q, cfg_wc_cnt, $time); $finish; end - + end // if (rst_n) - + //synopsys translate_on `ifndef NO_SDE_DEBUG_ILA - + ila_sde_wb SDE_WB_ILA - ( + ( .clk(clk), - + // 0 - 7 .probe0(desc_wb_limit_req), .probe1(desc_wb_limit), @@ -785,8 +788,8 @@ end // if (~H2C_N_C2H) .probe5(axis_wb_pkt_cnt), .probe6(dm_wb_md_req), .probe7(wb_dm_md_grant), - - // 8 - 15 + + // 8 - 15 .probe8(wb_pm_awvalid), .probe9(wb_pm_awaddr), .probe10(pm_wb_awready), @@ -825,7 +828,7 @@ end // if (~H2C_N_C2H) .probe37(desc_cdt_req_wc_cnt), .probe38(desc_cnt_req_wc_cnt), .probe39(pkt_cnt_req_wc_cnt), - + // 40-47 .probe40(md_wr_ptr_req_wc_cnt), .probe41(desc_cdt_req_wc_to_cnt), @@ -835,16 +838,16 @@ end // if (~H2C_N_C2H) .probe45(desc_wb_limit_wc_req ), .probe46(desc_wb_cnt_wc_req ), .probe47(axis_wb_pkt_cnt_wc_req), - + // 48-55 .probe48(md_wr_ptr_wc_req ) ); - + `endif // `ifndef NO_SDE_DEBUG_ILA - - - + + + endmodule // sde_wb diff --git a/hdk/cl/examples/cl_sde/software/include/sh_dpi_tasks.h b/hdk/cl/examples/cl_sde/software/include/sh_dpi_tasks.h index 9c7a39127..f74162e62 100644 --- a/hdk/cl/examples/cl_sde/software/include/sh_dpi_tasks.h +++ b/hdk/cl/examples/cl_sde/software/include/sh_dpi_tasks.h @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + #ifndef SH_DPI_TASKS #define SH_DPI_TASKS diff --git a/hdk/cl/examples/cl_sde/software/runtime/Makefile b/hdk/cl/examples/cl_sde/software/runtime/Makefile index 04f9bd9d4..4b3a74dd9 100644 --- a/hdk/cl/examples/cl_sde/software/runtime/Makefile +++ b/hdk/cl/examples/cl_sde/software/runtime/Makefile @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= + export TEST ?= test_sde_loopback diff --git a/hdk/cl/examples/cl_sde/software/src/test_null.c b/hdk/cl/examples/cl_sde/software/src/test_null.c index 708f5fc61..fd202fcda 100644 --- a/hdk/cl/examples/cl_sde/software/src/test_null.c +++ b/hdk/cl/examples/cl_sde/software/src/test_null.c @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ #include diff --git a/hdk/cl/examples/cl_sde/verif/README.md b/hdk/cl/examples/cl_sde/verif/README.md index 27da2cd5c..0db03cb42 100644 --- a/hdk/cl/examples/cl_sde/verif/README.md +++ b/hdk/cl/examples/cl_sde/verif/README.md @@ -1,8 +1,17 @@ -This readme provides information about the simulation environment for the cl_sde example. For more details about overall HDK simulation environment and CL bringup in simulation please refer to [RTL Simulation Guide for HDK Design Flow](../../../../docs/RTL_Simulation_Guide_for_HDK_Design_Flow.md). +# SDE CL Example Simulation -# SDE CL example simulation +## Table of Contents -The system verilog simulation tests can be run from the [$CL_DIR/verif/scripts](scripts) directory with all supported simulators. You can run each test by setting TEST=. +- [SDE CL Example Simulation](#sde-cl-example-simulation) + - [Table of Contents](#table-of-contents) + - [Overview](#overview) + - [Dump Waves](#dump-waves) + +## Overview + +This readme provides information about the simulation environment for the `cl_sde` example. For more details about overall HDK simulation environment and CL bringup in simulation please refer to [RTL Simulation Guide for HDK Design Flow](../../../../docs/RTL_Simulation_Guide_for_HDK_Design_Flow.md). + +The system verilog simulation tests can be run from the `$CL_DIR/verif/scripts/` directory with all supported simulators. You can run each test by setting `TEST=\`. ```bash cd aws-fpga @@ -11,6 +20,7 @@ cd hdk/cl/examples/cl_sde export CL_DIR=$(pwd) cd ${CL_DIR}/verif/scripts ``` + Run the tests ```bash @@ -24,6 +34,6 @@ make TEST=test_simple_h2c QUESTA=1 make TEST=test_simple_c2h QUESTA=1 ``` -# Dump Waves +## Dump Waves For information about how to dump waves with XSIM or VCS, please refer to [debugging-custom-logic-using-the-aws-hdk](../../../../docs/RTL_Simulation_Guide_for_HDK_Design_Flow.md#debugging-custom-logic-using-the-aws-hdk) diff --git a/hdk/cl/examples/cl_sde/verif/scripts/Makefile b/hdk/cl/examples/cl_sde/verif/scripts/Makefile index 71fb01491..8026c7749 100644 --- a/hdk/cl/examples/cl_sde/verif/scripts/Makefile +++ b/hdk/cl/examples/cl_sde/verif/scripts/Makefile @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= + ifndef HDK_COMMON_DIR $(error Environment variable HDK_COMMON_DIR not set. Please source hdk_setup.sh) diff --git a/hdk/cl/examples/cl_sde/verif/scripts/Makefile.tests b/hdk/cl/examples/cl_sde/verif/scripts/Makefile.tests index 6eaf62c08..067a09d91 100644 --- a/hdk/cl/examples/cl_sde/verif/scripts/Makefile.tests +++ b/hdk/cl/examples/cl_sde/verif/scripts/Makefile.tests @@ -1,3 +1,21 @@ +# ============================================================================= +# Amazon FPGA Hardware Development Kit +# +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + + test_simple_h2c: TEST=test_simple_h2c test_simple_h2c: all diff --git a/hdk/cl/examples/cl_sde/verif/scripts/top.questa.f b/hdk/cl/examples/cl_sde/verif/scripts/top.questa.f index 8bdeb5ee1..e019f523d 100644 --- a/hdk/cl/examples/cl_sde/verif/scripts/top.questa.f +++ b/hdk/cl/examples/cl_sde/verif/scripts/top.questa.f @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= + +define+CL_NAME=cl_sde +define+NO_SDE_DEBUG_ILA diff --git a/hdk/cl/examples/cl_sde/verif/scripts/top.vcs.f b/hdk/cl/examples/cl_sde/verif/scripts/top.vcs.f index 8bdeb5ee1..e019f523d 100644 --- a/hdk/cl/examples/cl_sde/verif/scripts/top.vcs.f +++ b/hdk/cl/examples/cl_sde/verif/scripts/top.vcs.f @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= + +define+CL_NAME=cl_sde +define+NO_SDE_DEBUG_ILA diff --git a/hdk/cl/examples/cl_sde/verif/scripts/top.xsim.f b/hdk/cl/examples/cl_sde/verif/scripts/top.xsim.f index 2447c4a76..b6df94a4c 100644 --- a/hdk/cl/examples/cl_sde/verif/scripts/top.xsim.f +++ b/hdk/cl/examples/cl_sde/verif/scripts/top.xsim.f @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= + -define CL_NAME=cl_sde -define NO_SDE_DEBUG_ILA diff --git a/hdk/cl/examples/cl_sde/verif/scripts/waves.tcl b/hdk/cl/examples/cl_sde/verif/scripts/waves.tcl index 4b14d0da6..584895d66 100644 --- a/hdk/cl/examples/cl_sde/verif/scripts/waves.tcl +++ b/hdk/cl/examples/cl_sde/verif/scripts/waves.tcl @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= + set curr_wave [current_wave_config] if { [string length $curr_wave] == 0 } { @@ -23,5 +26,5 @@ if { [string length $curr_wave] == 0 } { } } -run 200 us +run 200 us quit diff --git a/hdk/cl/examples/cl_sde/verif/tests/test_base.inc b/hdk/cl/examples/cl_sde/verif/tests/test_base.inc index 7f00e2d3c..f9902f1de 100644 --- a/hdk/cl/examples/cl_sde/verif/tests/test_base.inc +++ b/hdk/cl/examples/cl_sde/verif/tests/test_base.inc @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + `include "common_base_test.svh" @@ -102,11 +105,11 @@ int cfg_err_cnt_finish = 1; //How many errors before kill simulatino bit cfg_perf_mon; logic [5:0] cfg_wc_cnt = 6'd0; -logic cfg_md_wr_ptr_wc_en = 1; -logic cfg_pkt_cnt_wc_en = 1; -logic cfg_desc_cnt_wc_en = 1; -logic cfg_desc_cdt_wc_en = 1; -logic [3:0] cfg_wc_to_cnt = 4'd0; +logic cfg_md_wr_ptr_wc_en = 1; +logic cfg_pkt_cnt_wc_en = 1; +logic cfg_desc_cnt_wc_en = 1; +logic cfg_desc_cdt_wc_en = 1; +logic [3:0] cfg_wc_to_cnt = 4'd0; logic [19:0] cfg_wc_to_rsln = 20'd0; logic [3:0] cfg_wc_cnt_min = 6'd0; @@ -165,14 +168,14 @@ begin if (exp_c2h_pkt_q.size()==0) begin $display($time,,,"TB_C2H_AutoCheck: ***FATAL*** Got a C2H packet in host, but expect queue is empty"); - end + end else begin cur_c2h_stream_pkt = exp_c2h_pkt_q.pop_front(); cur_c2h_stream_pkt_user = exp_c2h_pkt_user_q.pop_front(); $display($time,,,"C2H Auto Check, RXPkt:Length=0x%0x, Data=0x%0x, ExpQ:Length=0x%0x, ExpQ:Data=0x%0x, ExpQ:User=0x%x", cur_c2h_host_pkt.data.size(), {cur_c2h_host_pkt.data[3], cur_c2h_host_pkt.data[2], cur_c2h_host_pkt.data[1], cur_c2h_host_pkt.data[0]}, cur_c2h_stream_pkt.data.size(), {cur_c2h_stream_pkt.data[3], cur_c2h_stream_pkt.data[2], cur_c2h_stream_pkt.data[1], cur_c2h_stream_pkt.data[0]}, cur_c2h_host_pkt_user); - c2h_err_cnt += cur_c2h_host_pkt.compare(cur_c2h_stream_pkt); + c2h_err_cnt += cur_c2h_host_pkt.compare(cur_c2h_stream_pkt); if ((cfg_desc_type==0) && (cur_c2h_stream_pkt_user != cur_c2h_host_pkt_user)) begin @@ -183,7 +186,7 @@ begin //begin // $display($time,,,"C2H Auto Check: user OK. Expected=0x%x, Actual=0x%x", cur_c2h_stream_pkt_user, cur_c2h_host_pkt_user); //end - + end end end @@ -196,7 +199,7 @@ end //--------------------------------- //Auto checking of H2C packets -always +always begin:h2c_auto_check logic[31:0] rdata; automatic logic[15:0] srm_inp_wr_ptr = 0; @@ -213,7 +216,7 @@ begin:h2c_auto_check logic[63:0] exp_rx_user; - + logic[(1 + 64 + 64 + 512)-1:0] ins_fifo_data; @@ -309,15 +312,15 @@ begin:h2c_auto_check srm_inp_rd_ptr = (srm_inp_rd_ptr + 1) & ((1 << `SRM_PATH.INP_PTR_WIDTH) - 1); end end - end + end end end // End H2C self checking //---------------------------- - + //----------------------------------------------------------------------------------------------- -// Random descriptor class, this will randomize offset/length of descriptor based on +// Random descriptor class, this will randomize offset/length of descriptor based on // test setup. //----------------------------------------------------------------------------------------------- class rnd_desc; @@ -329,13 +332,13 @@ class rnd_desc; int max_offset; int min_length; int max_length; - + int page_size; int pkt_length; int accum_length; - constraint default_c { + constraint default_c { offset + length <= page_size; offset + length <= pkt_length - accum_length; offset >= min_offset; @@ -348,7 +351,7 @@ class rnd_desc; eop == ((accum_length + length) == pkt_length); } - + function new (int min_offset=cfg_desc_offset_min, int max_offset=cfg_desc_offset_max, int min_length=cfg_desc_length_min, int max_length=cfg_desc_length_max, int page_size=cfg_page_size, int pkt_length=0, int accum_length=0); @@ -368,7 +371,7 @@ class rnd_desc; endclass //---------------------------------------- -// Thread to send H2C packets +// Thread to send H2C packets //---------------------------------------- task post_h2c_desc_thread; @@ -437,7 +440,7 @@ begin end $display($time,,,"TX_PKT[%0d]: Length=0x%0x (%0d), User=0x%x", pkt_count, cur_pkt_length, cur_pkt_length, cur_pkt_user); - + desc_count = 0; accum_length = 0; @@ -445,7 +448,7 @@ begin rd.accum_length = accum_length; //Create descriptors for the packet. Accum length of the descriptors until satisfy packet length - while (accum_length> 1)-1)]; assign watermark = fifo_valid[cfg_watermark]; - -endmodule - +endmodule diff --git a/hdk/common/lib/flop_fifo_in.sv b/hdk/common/lib/flop_fifo_in.sv index 165cbd389..7551b3920 100644 --- a/hdk/common/lib/flop_fifo_in.sv +++ b/hdk/common/lib/flop_fifo_in.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ // flop_fifo_in : Flops the input data right away @@ -61,13 +63,13 @@ module flop_fifo_in #(// -------------------------------------------------- localparam LESS_RST_LOCAL = 1; `else localparam LESS_RST_LOCAL = LESS_RST; -`endif - +`endif + // For every push, keep pushing data into the ff_fifo array // For pop's there is no change generate if (LESS_RST_LOCAL == 1) begin - + always @(posedge clk) begin for (int i = 0; i < DEPTH; i++) begin if (push) begin @@ -81,9 +83,9 @@ module flop_fifo_in #(// -------------------------------------------------- end // for (int i = 0; i < DEPTH; i++) end // always @ (posedge clk) end // if (LESS_RST_LOCAL == 1) - + else begin - + always @(posedge clk or negedge rst_n) if (!rst_n) begin ff_fifo <= '{default:'0}; @@ -103,18 +105,18 @@ module flop_fifo_in #(// -------------------------------------------------- ff_fifo[i] <= ff_fifo[i]; end // for (int i = 0; i < DEPTH; i++) end // else: !if(!rst_n) - + end // if !(LESS_RST_LOCAL == 1) endgenerate - + // For push & ~pop, valid[0] gets 1. every thing else shifts. // For ~push & pop, the most significant valid gets invalidated // For push & pop, valid array stays the same generate - + if (LESS_RST_LOCAL == 1) begin - + always @(posedge clk) if (!rst_n || !sync_rst_n) begin ff_valid <= '{default:'0}; @@ -139,9 +141,9 @@ module flop_fifo_in #(// -------------------------------------------------- end // else: !if(!rst_n) end // if (LESS_RST_LOCAL == 1) - + else begin - + always @(posedge clk or negedge rst_n) if (!rst_n) begin ff_valid <= '{default:'0}; @@ -171,16 +173,16 @@ module flop_fifo_in #(// -------------------------------------------------- end // else: !if(LESS_RST_LOCAL == 1) endgenerate - + // Output data is the most significant data (oldest data) always_comb begin ss_pop_data = ({WIDTH{1'b0}}); for (int i = 0; i < DEPTH; i++) begin - if (ff_valid[i]) + if (ff_valid[i]) ss_pop_data = ff_fifo[i]; end end - + // Data is valid as long as entry 0 is valid assign ss_data_valid = ff_valid[0]; @@ -198,7 +200,7 @@ module flop_fifo_in #(// -------------------------------------------------- end ff_pop_data <= ss_pop_data; end - + end // if (LESS_RST_LOCAL == 1) else begin @@ -232,5 +234,3 @@ module flop_fifo_in #(// -------------------------------------------------- assign watermark = ff_valid[cfg_watermark]; endmodule // epipe_flop_fifo - - diff --git a/hdk/common/lib/ft_fifo.v b/hdk/common/lib/ft_fifo.v index 146d312b4..eb03407d9 100644 --- a/hdk/common/lib/ft_fifo.v +++ b/hdk/common/lib/ft_fifo.v @@ -1,28 +1,24 @@ -//---------------------------------------------------------------------------------- -//Copyright (c) 2014 +// ============================================================================ +// Amazon FPGA Hardware Development Kit // -//Permission is hereby granted, free of charge, to any person obtaining a copy -//of this software and associated documentation files (the "Software"), to deal -//in the Software without restriction, including without limitation the rights -//to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -//copies of the Software, and to permit persons to whom the Software is -//furnished to do so, subject to the following conditions: +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // -//The above copyright notice and this permission notice shall be included in -//all copies or substantial portions of the Software. +// Licensed under the Amazon Software License (the "License"). You may not use +// this file except in compliance with the License. A copy of the License is +// located at // -//THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -//IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -//FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -//AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -//LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -//OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -//THE SOFTWARE. -//---------------------------------------------------------------------------------- +// http://aws.amazon.com/asl/ +// +// or in the "license" file accompanying this file. This file is distributed on +// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +// implied. See the License for the specific language governing permissions and +// limitations under the License. +// ============================================================================ + //------------------------------------------------------------------------------ -// Description : -// +// Description : +// // This is a flow-through FIFO that converts a RAM-based FIFO (1 clock // latency on the RAM) to what looks like a flop based FIFO. There is // no delay between pop and getting the next data. This sometimes simplifies @@ -49,7 +45,7 @@ module ft_fifo ( parameter FIFO_WIDTH = 32; parameter LESS_RST = 0; - + input clk; //Global clock input rst_n; //Global reset @@ -79,20 +75,20 @@ assign ram_pop = !ram_fifo_empty && (!ft1_valid||ft_pop) && (!ft0_valid||!ram_po if (LESS_RST == 1) begin always @(posedge clk) - ram_pop_q <= ram_pop; + ram_pop_q <= ram_pop; end else begin - + always @(negedge rst_n or posedge clk) if (!rst_n) - ram_pop_q <= 0; + ram_pop_q <= 0; else - ram_pop_q <= ram_pop; + ram_pop_q <= ram_pop; end // else: !if(LESS_RST) endgenerate - + assign nxt_ft0 = (ram_pop_q && !ft0_valid)? {1'b1, ram_fifo_data}: ft0; assign nxt_ft1 = (ram_pop_q && ft0_valid )? {1'b1, ram_fifo_data}: ft1; @@ -100,7 +96,7 @@ always @(negedge rst_n or posedge clk) if (!rst_n) begin ft0[FIFO_WIDTH] <= 'h0; - ft1[FIFO_WIDTH] <= 'h0; + ft1[FIFO_WIDTH] <= 'h0; end else if (!sync_rst_n) begin @@ -113,14 +109,14 @@ always @(negedge rst_n or posedge clk) ft1[FIFO_WIDTH] <= 'h0; end else - begin + begin ft0[FIFO_WIDTH] <= nxt_ft0[FIFO_WIDTH]; ft1[FIFO_WIDTH] <= nxt_ft1[FIFO_WIDTH]; end generate if (LESS_RST == 1) begin - + always @(posedge clk) if (ft_pop) begin @@ -128,20 +124,20 @@ always @(negedge rst_n or posedge clk) ft1[FIFO_WIDTH-1:0] <= ft1[FIFO_WIDTH-1:0]; end else - begin + begin ft0[FIFO_WIDTH-1:0] <= nxt_ft0[FIFO_WIDTH-1:0]; ft1[FIFO_WIDTH-1:0] <= nxt_ft1[FIFO_WIDTH-1:0]; end end // if (LESS_RST) - + else begin - + always @(negedge rst_n or posedge clk) if (!rst_n) begin ft0[FIFO_WIDTH-1:0] <= 'h0; - ft1[FIFO_WIDTH-1:0] <= 'h0; + ft1[FIFO_WIDTH-1:0] <= 'h0; end else if (!sync_rst_n) begin @@ -154,16 +150,15 @@ always @(negedge rst_n or posedge clk) ft1[FIFO_WIDTH-1:0] <= ft1[FIFO_WIDTH-1:0]; end else - begin + begin ft0[FIFO_WIDTH-1:0] <= nxt_ft0[FIFO_WIDTH-1:0]; ft1[FIFO_WIDTH-1:0] <= nxt_ft1[FIFO_WIDTH-1:0]; end end // else: !if(LESS_RST) endgenerate - - + + assign {ft_valid, ft_data} = ft0; endmodule - diff --git a/hdk/common/lib/ft_fifo_p.v b/hdk/common/lib/ft_fifo_p.v index e92a442a2..59a5f4fb1 100644 --- a/hdk/common/lib/ft_fifo_p.v +++ b/hdk/common/lib/ft_fifo_p.v @@ -1,28 +1,24 @@ -//---------------------------------------------------------------------------------- -//Copyright (c) 2014 +// ============================================================================ +// Amazon FPGA Hardware Development Kit // -//Permission is hereby granted, free of charge, to any person obtaining a copy -//of this software and associated documentation files (the "Software"), to deal -//in the Software without restriction, including without limitation the rights -//to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -//copies of the Software, and to permit persons to whom the Software is -//furnished to do so, subject to the following conditions: +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // -//The above copyright notice and this permission notice shall be included in -//all copies or substantial portions of the Software. +// Licensed under the Amazon Software License (the "License"). You may not use +// this file except in compliance with the License. A copy of the License is +// located at // -//THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -//IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -//FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -//AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -//LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -//OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -//THE SOFTWARE. -//---------------------------------------------------------------------------------- +// http://aws.amazon.com/asl/ +// +// or in the "license" file accompanying this file. This file is distributed on +// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +// implied. See the License for the specific language governing permissions and +// limitations under the License. +// ============================================================================ + //------------------------------------------------------------------------------ -// Description : -// +// Description : +// // This is a flow-through FIFO that converts a RAM-based FIFO (2 clock // latency on the RAM) to what looks like a flop based FIFO. There is // no delay between pop and getting the next data. This sometimes simplifies @@ -52,7 +48,7 @@ module ft_fifo_p ( parameter FIFO_WIDTH = 32; parameter LESS_RST = 0; - + input clk; //Global clock input rst_n; //Global reset @@ -98,40 +94,40 @@ always @(negedge rst_n or posedge clk) endcase end - generate + generate if (LESS_RST == 1) begin always @(posedge clk) begin - ram_pop_q <= ram_pop; + ram_pop_q <= ram_pop; ram_pop_qq <= ram_pop_q; end end // if (LESS_RST) - + else begin - + always @(negedge rst_n or posedge clk) if (!rst_n) begin - ram_pop_q <= 0; + ram_pop_q <= 0; ram_pop_qq <= 0; end else begin - ram_pop_q <= ram_pop; + ram_pop_q <= ram_pop; ram_pop_qq <= ram_pop_q; end - + end // else: !if(LESS_RST) endgenerate - + assign nxt_ft0 = (ram_pop_qq && !ft0_valid)? {1'b1, ram_fifo_data}: ft0; assign nxt_ft1 = (ram_pop_qq && ft0_valid && !ft1_valid )? {1'b1, ram_fifo_data}: ft1; assign nxt_ft2 = (ram_pop_qq && ft1_valid && !ft2_valid )? {1'b1, ram_fifo_data}: ft2; generate - + if (LESS_RST == 1) begin @@ -139,8 +135,8 @@ assign nxt_ft2 = (ram_pop_qq && ft1_valid && !ft2_valid )? {1'b1, ram_fifo_data} if (!rst_n) begin ft0[FIFO_WIDTH] <= 'h0; - ft1[FIFO_WIDTH] <= 'h0; - ft2[FIFO_WIDTH] <= 'h0; + ft1[FIFO_WIDTH] <= 'h0; + ft2[FIFO_WIDTH] <= 'h0; end else if (!sync_rst_n) begin @@ -155,12 +151,12 @@ assign nxt_ft2 = (ram_pop_qq && ft1_valid && !ft2_valid )? {1'b1, ram_fifo_data} ft2[FIFO_WIDTH] <= 'h0; end else - begin + begin ft0[FIFO_WIDTH] <= nxt_ft0[FIFO_WIDTH]; ft1[FIFO_WIDTH] <= nxt_ft1[FIFO_WIDTH]; ft2[FIFO_WIDTH] <= nxt_ft2[FIFO_WIDTH]; end - + always @(posedge clk) if (qual_ft_pop) begin @@ -169,22 +165,22 @@ assign nxt_ft2 = (ram_pop_qq && ft1_valid && !ft2_valid )? {1'b1, ram_fifo_data} ft2[FIFO_WIDTH-1:0] <= ft2[FIFO_WIDTH-1:0]; end else - begin + begin ft0[FIFO_WIDTH-1:0] <= nxt_ft0[FIFO_WIDTH-1:0]; ft1[FIFO_WIDTH-1:0] <= nxt_ft1[FIFO_WIDTH-1:0]; ft2[FIFO_WIDTH-1:0] <= nxt_ft2[FIFO_WIDTH-1:0]; end end // if (LESS_RST) - + else begin always @(negedge rst_n or posedge clk) if (!rst_n) begin ft0 <= 0; - ft1 <= 0; - ft2 <= 0; + ft1 <= 0; + ft2 <= 0; end else if (!sync_rst_n) begin @@ -199,7 +195,7 @@ assign nxt_ft2 = (ram_pop_qq && ft1_valid && !ft2_valid )? {1'b1, ram_fifo_data} ft2 <= 0; end else - begin + begin ft0 <= nxt_ft0; ft1 <= nxt_ft1; ft2 <= nxt_ft2; @@ -208,7 +204,7 @@ assign nxt_ft2 = (ram_pop_qq && ft1_valid && !ft2_valid )? {1'b1, ram_fifo_data} end // else: !if(LESS_RST) endgenerate - + assign {ft_valid, ft_data} = ft0; @@ -220,7 +216,7 @@ assign {ft_valid, ft_data} = ft0; `ifdef DESIGN_ERROR `include "design_error.inc" reg[1:0] num_valid_q; - + always @(posedge clk) begin if (!ft0_valid && ft_pop) begin @@ -241,4 +237,3 @@ end //synopsys translate_on endmodule - diff --git a/hdk/common/lib/hbm_wrapper.sv b/hdk/common/lib/hbm_wrapper.sv index 9b68f0364..08413d9a2 100644 --- a/hdk/common/lib/hbm_wrapper.sv +++ b/hdk/common/lib/hbm_wrapper.sv @@ -1,7 +1,7 @@ -//------------------------------------------------------------------------------------------------------------------------------- +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -13,9 +13,9 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. -// Restricted NDA Material -//------------------------------------------------------------------------------------------------------------------------------- -//=============================================================================================================================== +// ============================================================================ + + // HBM Wrapper // - Wrapper for HBM IP // - Implements an MMCM to generate 100MHz and 450MHz clock for the HBM IP. @@ -35,8 +35,6 @@ // // Poll for lock // poll bits[3:1] = 3'b111 @ addr 0x00 // -// -//=============================================================================================================================== module hbm_wrapper #( diff --git a/hdk/common/lib/interfaces.sv b/hdk/common/lib/interfaces.sv index 9dca2718f..ca0679b1b 100644 --- a/hdk/common/lib/interfaces.sv +++ b/hdk/common/lib/interfaces.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ // Interfaces diff --git a/hdk/common/lib/lib_pipe.sv b/hdk/common/lib/lib_pipe.sv index 41466ee20..ffc39c59b 100644 --- a/hdk/common/lib/lib_pipe.sv +++ b/hdk/common/lib/lib_pipe.sv @@ -1,24 +1,20 @@ -//---------------------------------------------------------------------------------- -//Copyright (c) 2014 +// ============================================================================ +// Amazon FPGA Hardware Development Kit // -//Permission is hereby granted, free of charge, to any person obtaining a copy -//of this software and associated documentation files (the "Software"), to deal -//in the Software without restriction, including without limitation the rights -//to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -//copies of the Software, and to permit persons to whom the Software is -//furnished to do so, subject to the following conditions: +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // -//The above copyright notice and this permission notice shall be included in -//all copies or substantial portions of the Software. +// Licensed under the Amazon Software License (the "License"). You may not use +// this file except in compliance with the License. A copy of the License is +// located at // -//THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -//IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -//FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -//AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -//LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -//OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -//THE SOFTWARE. -//---------------------------------------------------------------------------------- +// http://aws.amazon.com/asl/ +// +// or in the "license" file accompanying this file. This file is distributed on +// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +// implied. See the License for the specific language governing permissions and +// limitations under the License. +// ============================================================================ + //simple pipeline diff --git a/hdk/common/lib/macros.svh b/hdk/common/lib/macros.svh index 83b0d5f46..bb6045502 100644 --- a/hdk/common/lib/macros.svh +++ b/hdk/common/lib/macros.svh @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + `ifndef _MACROS_SVH_ `define _MACROS_SVH_ @@ -596,7 +599,7 @@ ``master``user = ``slave``user; \ \ ``slave``ack = ``master``ack; \ - ``slave``rdata = ``master``rdata; + ``slave``rdata = ``master``rdata; //bus_name is the port on the instace, if_name is the interface name to connect to `define EXP_CONNECT_AXI_BUS(port_name, if_name) \ diff --git a/hdk/common/lib/ram_fifo_ft.sv b/hdk/common/lib/ram_fifo_ft.sv index 23322cd82..62a3891c4 100644 --- a/hdk/common/lib/ram_fifo_ft.sv +++ b/hdk/common/lib/ram_fifo_ft.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ //-------------------------------------------------------------------------------------------- @@ -35,7 +37,7 @@ module ram_fifo_ft #(parameter WIDTH=32, parameter PTR_WIDTH=7, parameter WATERM output logic oflow, output logic empty //Because of ft_fifo empty is different than !valid. Should only be used - // to see if FIFO is not + // to see if FIFO is not ); parameter[31:0] NUM_LOC = 1'b1 << PTR_WIDTH; @@ -48,7 +50,7 @@ logic[PTR_WIDTH:0] wptr = 0; logic[PTR_WIDTH:0] rptr = 0; logic[PTR_WIDTH:0] num_entries; //Tracks entries in the combined RAM/FT FIFOs -logic[PTR_WIDTH:0] num_entries_nxt; +logic[PTR_WIDTH:0] num_entries_nxt; wire[PTR_WIDTH:0] ptr_diff = wptr - rptr; @@ -74,7 +76,7 @@ always_comb begin if (!rst_n) num_entries_nxt = 0; - else + else num_entries_nxt = num_entries + (push & !fifo_full) - (pop & valid); end @@ -111,7 +113,7 @@ ft_fifo_p #(.FIFO_WIDTH(WIDTH), .LESS_RST(LESS_RST)) FT_FIFO ( .ft_pop(pop), .ram_pop(ram_pop), - + .ft_valid(valid), .ft_data(pop_data) ); @@ -128,11 +130,11 @@ ft_fifo #(.FIFO_WIDTH(WIDTH), .LESS_RST(LESS_RST)) FT_FIFO ( .ft_pop(pop), .ram_pop(ram_pop), - + .ft_valid(valid), .ft_data(pop_data) ); - + always @(negedge rst_n or posedge clk) if (!rst_n) oflow <= 0; @@ -140,5 +142,3 @@ always @(negedge rst_n or posedge clk) oflow <= 1; endmodule - - diff --git a/hdk/common/lib/rr_arb.sv b/hdk/common/lib/rr_arb.sv index 42df12a23..e3f985308 100644 --- a/hdk/common/lib/rr_arb.sv +++ b/hdk/common/lib/rr_arb.sv @@ -1,24 +1,20 @@ -//---------------------------------------------------------------------------------- -//Copyright (c) 2014 +// ============================================================================ +// Amazon FPGA Hardware Development Kit // -//Permission is hereby granted, free of charge, to any person obtaining a copy -//of this software and associated documentation files (the "Software"), to deal -//in the Software without restriction, including without limitation the rights -//to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -//copies of the Software, and to permit persons to whom the Software is -//furnished to do so, subject to the following conditions: +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // -//The above copyright notice and this permission notice shall be included in -//all copies or substantial portions of the Software. +// Licensed under the Amazon Software License (the "License"). You may not use +// this file except in compliance with the License. A copy of the License is +// located at // -//THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -//IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -//FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -//AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -//LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -//OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -//THE SOFTWARE. -//---------------------------------------------------------------------------------- +// http://aws.amazon.com/asl/ +// +// or in the "license" file accompanying this file. This file is distributed on +// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +// implied. See the License for the specific language governing permissions and +// limitations under the License. +// ============================================================================ + //------------------------------------------------------------- // This is a simple round robin arbiter. Runs every clock @@ -39,7 +35,7 @@ module rr_arb #( parameter WINNER_WIDTH=3, //Number of bi -wire[WINNER_WIDTH-1:0] hi_pri; //Next hi priority +wire[WINNER_WIDTH-1:0] hi_pri; //Next hi priority wire[REQ_WIDTH-1:0] req_shifted; //Shift request based on hi_pri reg[WINNER_WIDTH-1:0] winner_q; @@ -90,5 +86,3 @@ always_ff @(negedge rst_n or posedge clk) assign hi_pri = (winner_q==(REQ_WIDTH-1))? 0: winner_q + 1; endmodule - - diff --git a/hdk/common/lib/srl_fifo.sv b/hdk/common/lib/srl_fifo.sv index ac227f63d..99fa82560 100644 --- a/hdk/common/lib/srl_fifo.sv +++ b/hdk/common/lib/srl_fifo.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,7 +13,7 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. - +// ============================================================================ // Descriptions: @@ -157,6 +158,3 @@ module srl_fifo #(parameter WIDTH = 64, endmodule // srl_fifo - - - diff --git a/hdk/common/lib/xpm_fifo.sv b/hdk/common/lib/xpm_fifo.sv index 294153f73..33f295fbb 100644 --- a/hdk/common/lib/xpm_fifo.sv +++ b/hdk/common/lib/xpm_fifo.sv @@ -1,12 +1,24 @@ -//============================================================================= -// Copyright 2022 Amazon.com, Inc. or its affiliates. -// All Rights Reserved Worldwide. -// Amazon Confidential information -// Restricted NDA Material -//============================================================================= +// ============================================================================ +// Amazon FPGA Hardware Development Kit +// +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// +// Licensed under the Amazon Software License (the "License"). You may not use +// this file except in compliance with the License. A copy of the License is +// located at +// +// http://aws.amazon.com/asl/ +// +// or in the "license" file accompanying this file. This file is distributed on +// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +// implied. See the License for the specific language governing permissions and +// limitations under the License. +// ============================================================================ + // Synchronous clock FIFO + module xpm_fifo #( parameter DATA_WIDTH = 32, diff --git a/hdk/common/shell_stable/build/constraints/bitstream_physical.xdc b/hdk/common/shell_stable/build/constraints/bitstream_physical.xdc index 148f368ff..47a9ed6e9 100644 --- a/hdk/common/shell_stable/build/constraints/bitstream_physical.xdc +++ b/hdk/common/shell_stable/build/constraints/bitstream_physical.xdc @@ -1,8 +1,18 @@ # ============================================================================= -# Copyright 2021 Amazon.com, Inc. or its affiliates. -# All Rights Reserved Worldwide. -# Amazon Confidential information -# Restricted NDA Material +# Amazon FPGA Hardware Development Kit +# +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. # ============================================================================= diff --git a/hdk/common/shell_stable/build/constraints/cl_ddr_timing_aws.xdc b/hdk/common/shell_stable/build/constraints/cl_ddr_timing_aws.xdc index 72bdc673f..e3ff29fef 100644 --- a/hdk/common/shell_stable/build/constraints/cl_ddr_timing_aws.xdc +++ b/hdk/common/shell_stable/build/constraints/cl_ddr_timing_aws.xdc @@ -1,3 +1,21 @@ +# ============================================================================= +# Amazon FPGA Hardware Development Kit +# +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + + ############################################################################### # This contains the specific constraints required by AWS ############################################################################### diff --git a/hdk/common/shell_stable/build/constraints/cl_pins.xdc b/hdk/common/shell_stable/build/constraints/cl_pins.xdc index 732463845..38c599abe 100644 --- a/hdk/common/shell_stable/build/constraints/cl_pins.xdc +++ b/hdk/common/shell_stable/build/constraints/cl_pins.xdc @@ -1,8 +1,18 @@ # ============================================================================= -# Copyright 2021 Amazon.com, Inc. or its affiliates. -# All Rights Reserved Worldwide. -# Amazon Confidential information -# Restricted NDA Material +# Amazon FPGA Hardware Development Kit +# +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. # ============================================================================= diff --git a/hdk/common/shell_stable/build/constraints/mmcm_cascade.xdc b/hdk/common/shell_stable/build/constraints/mmcm_cascade.xdc index 875e71534..2ba2fb3ae 100644 --- a/hdk/common/shell_stable/build/constraints/mmcm_cascade.xdc +++ b/hdk/common/shell_stable/build/constraints/mmcm_cascade.xdc @@ -1,10 +1,21 @@ # ============================================================================= -# Copyright 2021 Amazon.com, Inc. or its affiliates. -# All Rights Reserved Worldwide. -# Amazon Confidential information -# Restricted NDA Material +# Amazon FPGA Hardware Development Kit +# +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. # ============================================================================= + ############################################################################### # Need this as a workaround for MMCM cascading when using AWS_CLK_GEN IP ############################################################################### diff --git a/hdk/common/shell_stable/build/constraints/small_shell_level_1_fp_cl.xdc b/hdk/common/shell_stable/build/constraints/small_shell_level_1_fp_cl.xdc index 9e2f9f2e6..1d7fa1ca2 100644 --- a/hdk/common/shell_stable/build/constraints/small_shell_level_1_fp_cl.xdc +++ b/hdk/common/shell_stable/build/constraints/small_shell_level_1_fp_cl.xdc @@ -1,8 +1,18 @@ # ============================================================================= -# Copyright 2021 Amazon.com, Inc. or its affiliates. -# All Rights Reserved Worldwide. -# Amazon Confidential information -# Restricted NDA Material +# Amazon FPGA Hardware Development Kit +# +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. # ============================================================================= diff --git a/hdk/common/shell_stable/build/constraints/xdma_shell_level_1_fp_cl.xdc b/hdk/common/shell_stable/build/constraints/xdma_shell_level_1_fp_cl.xdc index 24779b6e0..b016e35fd 100644 --- a/hdk/common/shell_stable/build/constraints/xdma_shell_level_1_fp_cl.xdc +++ b/hdk/common/shell_stable/build/constraints/xdma_shell_level_1_fp_cl.xdc @@ -1,8 +1,18 @@ # ============================================================================= -# Copyright 2021 Amazon.com, Inc. or its affiliates. -# All Rights Reserved Worldwide. -# Amazon Confidential information -# Restricted NDA Material +# Amazon FPGA Hardware Development Kit +# +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. # ============================================================================= diff --git a/hdk/common/shell_stable/build/scripts/aws_build_dcp_from_cl.py b/hdk/common/shell_stable/build/scripts/aws_build_dcp_from_cl.py index 4791cbfb4..9d4357808 100755 --- a/hdk/common/shell_stable/build/scripts/aws_build_dcp_from_cl.py +++ b/hdk/common/shell_stable/build/scripts/aws_build_dcp_from_cl.py @@ -1,8 +1,9 @@ #!/usr/bin/env python3 +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2022 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -14,6 +15,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= + from optparse import OptionParser import datetime diff --git a/hdk/common/shell_stable/build/scripts/aws_clock_properties.tcl b/hdk/common/shell_stable/build/scripts/aws_clock_properties.tcl index 43b70c35a..ef49af3dc 100755 --- a/hdk/common/shell_stable/build/scripts/aws_clock_properties.tcl +++ b/hdk/common/shell_stable/build/scripts/aws_clock_properties.tcl @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= + ##################################################################### # diff --git a/hdk/common/shell_stable/build/scripts/aws_gen_clk_constraints.tcl b/hdk/common/shell_stable/build/scripts/aws_gen_clk_constraints.tcl index faf27335c..0daa82e8b 100755 --- a/hdk/common/shell_stable/build/scripts/aws_gen_clk_constraints.tcl +++ b/hdk/common/shell_stable/build/scripts/aws_gen_clk_constraints.tcl @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= # Clock Group A diff --git a/hdk/common/shell_stable/build/scripts/build_all.tcl b/hdk/common/shell_stable/build/scripts/build_all.tcl index 4c56f5c68..42fccf028 100644 --- a/hdk/common/shell_stable/build/scripts/build_all.tcl +++ b/hdk/common/shell_stable/build/scripts/build_all.tcl @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2022 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= ############################################################################### diff --git a/hdk/common/shell_stable/build/scripts/build_level_1_cl.tcl b/hdk/common/shell_stable/build/scripts/build_level_1_cl.tcl index fd295edcd..cb60d403e 100644 --- a/hdk/common/shell_stable/build/scripts/build_level_1_cl.tcl +++ b/hdk/common/shell_stable/build/scripts/build_level_1_cl.tcl @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2022 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= # Common CL Implementation Tcl Script diff --git a/hdk/common/shell_stable/build/scripts/check_ddr_bram.tcl b/hdk/common/shell_stable/build/scripts/check_ddr_bram.tcl index 2705c1e82..4de00ab8b 100644 --- a/hdk/common/shell_stable/build/scripts/check_ddr_bram.tcl +++ b/hdk/common/shell_stable/build/scripts/check_ddr_bram.tcl @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2022 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= # Check if the tool loaded calibration_ddr.elf file into DDR Controller BRAMs diff --git a/hdk/common/shell_stable/build/scripts/ddr_io_train.tcl b/hdk/common/shell_stable/build/scripts/ddr_io_train.tcl index 3be8b0cdd..c854f7e84 100644 --- a/hdk/common/shell_stable/build/scripts/ddr_io_train.tcl +++ b/hdk/common/shell_stable/build/scripts/ddr_io_train.tcl @@ -1,8 +1,18 @@ # ============================================================================= -# Copyright 2021 Amazon.com, Inc. or its affiliates. -# All Rights Reserved Worldwide. -# Amazon Confidential information -# Restricted NDA Material +# Amazon FPGA Hardware Development Kit +# +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. # ============================================================================= diff --git a/hdk/common/shell_stable/build/scripts/encrypt.tcl b/hdk/common/shell_stable/build/scripts/encrypt.tcl index c767ed0c1..4792e482b 100644 --- a/hdk/common/shell_stable/build/scripts/encrypt.tcl +++ b/hdk/common/shell_stable/build/scripts/encrypt.tcl @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= # Remove any previously encrypted files, that may no longer be used diff --git a/hdk/common/shell_stable/build/scripts/placement_fix_v22_1.tcl b/hdk/common/shell_stable/build/scripts/placement_fix_v22_1.tcl index 1bad020b0..204fe6874 100644 --- a/hdk/common/shell_stable/build/scripts/placement_fix_v22_1.tcl +++ b/hdk/common/shell_stable/build/scripts/placement_fix_v22_1.tcl @@ -1,10 +1,21 @@ # ============================================================================= -# Copyright 2021 Amazon.com, Inc. or its affiliates. -# All Rights Reserved Worldwide. -# Amazon Confidential information -# Restricted NDA Material +# Amazon FPGA Hardware Development Kit +# +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. # ============================================================================= + # This is a workaround for Vivado 2022.1 placement hang issue set DDR_CELL [get_cells WRAPPER/CL/SH_DDR/genblk1.IS_DDR_PRESENT.DDR4_0] if {$DDR_CELL != ""} { diff --git a/hdk/common/shell_stable/build/scripts/synth_cl_footer.tcl b/hdk/common/shell_stable/build/scripts/synth_cl_footer.tcl index 0b076233d..2b5f5a054 100644 --- a/hdk/common/shell_stable/build/scripts/synth_cl_footer.tcl +++ b/hdk/common/shell_stable/build/scripts/synth_cl_footer.tcl @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2022 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= # Common CL Synthesis Tcl Script Footer diff --git a/hdk/common/shell_stable/build/scripts/synth_cl_header.tcl b/hdk/common/shell_stable/build/scripts/synth_cl_header.tcl index c1d8c5f1f..c4874304f 100644 --- a/hdk/common/shell_stable/build/scripts/synth_cl_header.tcl +++ b/hdk/common/shell_stable/build/scripts/synth_cl_header.tcl @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2022 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= # Common CL Synthesis Tcl Script Header diff --git a/hdk/common/shell_stable/design/interfaces/cl_ports.vh b/hdk/common/shell_stable/design/interfaces/cl_ports.vh index 27b8381dd..f4f963d93 100644 --- a/hdk/common/shell_stable/design/interfaces/cl_ports.vh +++ b/hdk/common/shell_stable/design/interfaces/cl_ports.vh @@ -1,9 +1,19 @@ -//============================================================================= -// Copyright 2022 Amazon.com, Inc. or its affiliates. -// All Rights Reserved Worldwide. -// Amazon Confidential information -// Restricted NDA Material -//============================================================================= +// ============================================================================ +// Amazon FPGA Hardware Development Kit +// +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// +// Licensed under the Amazon Software License (the "License"). You may not use +// this file except in compliance with the License. A copy of the License is +// located at +// +// http://aws.amazon.com/asl/ +// +// or in the "license" file accompanying this file. This file is distributed on +// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +// implied. See the License for the specific language governing permissions and +// limitations under the License. +// ============================================================================ //---------------------------------------- diff --git a/hdk/common/shell_stable/design/interfaces/unused_apppf_irq_template.inc b/hdk/common/shell_stable/design/interfaces/unused_apppf_irq_template.inc index d02ebe062..884dd26af 100644 --- a/hdk/common/shell_stable/design/interfaces/unused_apppf_irq_template.inc +++ b/hdk/common/shell_stable/design/interfaces/unused_apppf_irq_template.inc @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ //------------------------------------ @@ -19,4 +21,3 @@ //------------------------------------ assign cl_sh_apppf_irq_req = 16'b0; - diff --git a/hdk/common/shell_stable/design/interfaces/unused_cl_sda_template.inc b/hdk/common/shell_stable/design/interfaces/unused_cl_sda_template.inc index 20d89b14a..e76fe4603 100644 --- a/hdk/common/shell_stable/design/interfaces/unused_cl_sda_template.inc +++ b/hdk/common/shell_stable/design/interfaces/unused_cl_sda_template.inc @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + // PCIe Slave (sda) Interface from SH to CL assign cl_sda_awready = 1'b0; diff --git a/hdk/common/shell_stable/design/interfaces/unused_ddr_template.inc b/hdk/common/shell_stable/design/interfaces/unused_ddr_template.inc index 81a9fac19..00ca7f5d9 100644 --- a/hdk/common/shell_stable/design/interfaces/unused_ddr_template.inc +++ b/hdk/common/shell_stable/design/interfaces/unused_ddr_template.inc @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + // Only the DDR pins are connected. The AXI and stats interfaces are tied-off. diff --git a/hdk/common/shell_stable/design/interfaces/unused_dma_pcis_template.inc b/hdk/common/shell_stable/design/interfaces/unused_dma_pcis_template.inc index 471309eac..28e4a5f30 100644 --- a/hdk/common/shell_stable/design/interfaces/unused_dma_pcis_template.inc +++ b/hdk/common/shell_stable/design/interfaces/unused_dma_pcis_template.inc @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ // PCIe Slave (pcis) Interface from SH to CL @@ -34,4 +36,3 @@ // CL DMA Full Signals assign cl_sh_dma_wr_full = 1'b0; assign cl_sh_dma_rd_full = 1'b0; - diff --git a/hdk/common/shell_stable/design/interfaces/unused_flr_template.inc b/hdk/common/shell_stable/design/interfaces/unused_flr_template.inc index 54240f101..8e1dd1381 100644 --- a/hdk/common/shell_stable/design/interfaces/unused_flr_template.inc +++ b/hdk/common/shell_stable/design/interfaces/unused_flr_template.inc @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ - assign cl_sh_flr_done = 1'b0; + assign cl_sh_flr_done = 1'b0; diff --git a/hdk/common/shell_stable/design/interfaces/unused_pcim_template.inc b/hdk/common/shell_stable/design/interfaces/unused_pcim_template.inc index 8d9179673..b713e0d18 100644 --- a/hdk/common/shell_stable/design/interfaces/unused_pcim_template.inc +++ b/hdk/common/shell_stable/design/interfaces/unused_pcim_template.inc @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + // PCIe Master (pcim) Interface from CL to SH assign cl_sh_pcim_awid = 16'b0; @@ -36,4 +39,3 @@ assign cl_sh_pcim_arvalid = 1'b0; assign cl_sh_pcim_rready = 1'b0; - diff --git a/hdk/common/shell_stable/design/interfaces/unused_sh_ocl_template.inc b/hdk/common/shell_stable/design/interfaces/unused_sh_ocl_template.inc index 421cf2006..85ccf6384 100644 --- a/hdk/common/shell_stable/design/interfaces/unused_sh_ocl_template.inc +++ b/hdk/common/shell_stable/design/interfaces/unused_sh_ocl_template.inc @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + // PCIe Slave (ocl) Interface from SH to CL assign cl_ocl_awready = 1'b0; diff --git a/hdk/common/shell_stable/design/sh_ddr/sh_ddr.stub.sv b/hdk/common/shell_stable/design/sh_ddr/sh_ddr.stub.sv index 2c2743130..6ea929571 100644 --- a/hdk/common/shell_stable/design/sh_ddr/sh_ddr.stub.sv +++ b/hdk/common/shell_stable/design/sh_ddr/sh_ddr.stub.sv @@ -1,7 +1,7 @@ -//------------------------------------------------------------------------------ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -13,8 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. -// Restricted NDA Material -//------------------------------------------------------------------------------ +// ============================================================================ + module sh_ddr #( diff --git a/hdk/common/shell_stable/design/sh_ddr/sim/axi4_slave_bfm.sv b/hdk/common/shell_stable/design/sh_ddr/sim/axi4_slave_bfm.sv index e0520d4e0..e9bacd9d4 100755 --- a/hdk/common/shell_stable/design/sh_ddr/sim/axi4_slave_bfm.sv +++ b/hdk/common/shell_stable/design/sh_ddr/sim/axi4_slave_bfm.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,13 +13,15 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + module axi4_slave_bfm #( parameter ECC_EN = 0, parameter ECC_ADDR_HI = 'h410, parameter ECC_ADDR_LO = 'h400, parameter RND_ECC_EN = 0, parameter RND_ECC_WEIGHT = 100) ( input clk_core, input rst_n, - + //------------------------------------------------------ // DDR-4 Interface from CL (AXI-4) //------------------------------------------------------ @@ -67,7 +70,7 @@ module axi4_slave_bfm #( parameter ECC_EN = 0, parameter ECC_ADDR_HI = 'h410, pa AXI_Command cl_sh_rd_cmds[$]; AXI_Command sh_cl_rd_data[$]; AXI_Command sh_cl_b_resps[$]; - + logic [31:0] model_memory[*]; int wr_cmd_cnt[0:3]; @@ -139,15 +142,15 @@ module axi4_slave_bfm #( parameter ECC_EN = 0, parameter ECC_ADDR_HI = 'h410, pa automatic int awready_cnt = 0; `else int awready_cnt = 0; -`endif +`endif if (cl_sh_ddr_awvalid && sh_cl_ddr_awready) begin cmd.addr = cl_sh_ddr_awaddr; cmd.id = cl_sh_ddr_awid; cmd.len = cl_sh_ddr_awlen; cmd.size = cl_sh_ddr_awsize; cmd.last = 0; - - cl_sh_wr_cmds.push_back(cmd); + + cl_sh_wr_cmds.push_back(cmd); sh_cl_b_resps.push_back(cmd); mem_wr_que.push_back(cmd); end @@ -171,10 +174,10 @@ module axi4_slave_bfm #( parameter ECC_EN = 0, parameter ECC_ADDR_HI = 'h410, pa `ifdef QUESTA_SIM automatic int wready_cnt = 0; automatic int wready_nonzero_wait = 0; -`else +`else int wready_cnt = 0; int wready_nonzero_wait = 0; -`endif +`endif if (sh_cl_ddr_wready && cl_sh_ddr_wvalid) begin wr_data.data = cl_sh_ddr_wdata; wr_data.strb = cl_sh_ddr_wstrb; @@ -184,9 +187,9 @@ module axi4_slave_bfm #( parameter ECC_EN = 0, parameter ECC_ADDR_HI = 'h410, pa if (wr_data.last == 1) wr_last_cnt += 1; - + end // if (sh_cl_ddr_wready && cl_sh_ddr_wvalid) - + if ((cl_sh_wr_data.size() > 64) || (wready_cnt > 0)) begin sh_cl_ddr_wready <= 1'b0; wready_cnt--; @@ -224,7 +227,7 @@ module axi4_slave_bfm #( parameter ECC_EN = 0, parameter ECC_ADDR_HI = 'h410, pa end else sh_cl_ddr_bvalid <= 1'b0; - + end // always @ (posedge clk_core) // @@ -233,7 +236,7 @@ module axi4_slave_bfm #( parameter ECC_EN = 0, parameter ECC_ADDR_HI = 'h410, pa always @(posedge clk_core) begin AXI_Command cmd; -`ifdef QUESTA_SIM +`ifdef QUESTA_SIM automatic int arready_cnt = 0; `else int arready_cnt = 0; @@ -260,14 +263,14 @@ module axi4_slave_bfm #( parameter ECC_EN = 0, parameter ECC_ADDR_HI = 'h410, pa end // always @ (posedge clk_core) - + //================================================= // // cl->sh PCIeM Interface // //================================================= - - + + always @(posedge clk_core) begin if (mem_wr_que.size() > 0) begin @@ -287,13 +290,13 @@ module axi4_slave_bfm #( parameter ECC_EN = 0, parameter ECC_ADDR_HI = 'h410, pa word = model_memory[{wr_addr[63:2], 2'b00}]; else word = 32'hffff_ffff; // return a default value - - + + for(int j=0; j<4; j++) begin logic [7:0] c; int index; index = j + (i * 4); - + if (cl_sh_wr_data[0].strb[index]) begin c = cl_sh_wr_data[0].data >> (index * 8); //FIX partial DW order word = {c, word[31:8]}; @@ -302,7 +305,7 @@ module axi4_slave_bfm #( parameter ECC_EN = 0, parameter ECC_ADDR_HI = 'h410, pa end // for (int j=0; j<4; j++) model_memory[{wr_addr[63:2], 2'b00}] = word; - + wr_addr += 4; end if (cl_sh_wr_data[0].last == 1) begin @@ -311,9 +314,9 @@ module axi4_slave_bfm #( parameter ECC_EN = 0, parameter ECC_ADDR_HI = 'h410, pa if (debug) begin $display("[%t] - DEBUG reseting...", $realtime); end - + end - + cl_sh_wr_data.pop_front(); end // if (cl_sh_wr_data.size() > 0) end // if (mem_wr_que.size() > 0) @@ -324,7 +327,7 @@ module axi4_slave_bfm #( parameter ECC_EN = 0, parameter ECC_ADDR_HI = 'h410, pa // logic first_rd_beat; logic [63:0] rd_addr, rd_addr_t; - + always @(posedge clk_core) begin AXI_Command rd_cmd; logic [511:0] beat; @@ -338,7 +341,7 @@ module axi4_slave_bfm #( parameter ECC_EN = 0, parameter ECC_ADDR_HI = 'h410, pa sh_cl_ddr_rlast <= (sh_cl_rd_data[0].len == 0) ? 1'b1 : (sh_cl_rd_data[0].len == 1) && sh_cl_ddr_rvalid && cl_sh_ddr_rready ? 1'b1 : 1'b0; - + if (first_rd_beat == 1'b1) begin rd_addr = sh_cl_rd_data[0].addr; first_rd_beat = 1'b0; @@ -346,19 +349,19 @@ module axi4_slave_bfm #( parameter ECC_EN = 0, parameter ECC_ADDR_HI = 'h410, pa if (!sh_cl_ddr_rvalid || (sh_cl_ddr_rvalid && cl_sh_ddr_rready)) begin - beat = {512{1'b1}}; + beat = {512{1'b1}}; for(int i=rd_addr[5:2]; i<16; i++) begin logic [31:0] c; if (debug) begin $display("[%t] : DEBUG reading addr 0x%016x", $realtime, rd_addr); end - + if (model_memory.exists({rd_addr[63:2], 2'b00})) c = model_memory[{rd_addr[63:2], 2'b00}]; else c = 32'hffffffff; - + beat = {c, beat[511:32]}; rd_addr +=4; end @@ -372,7 +375,7 @@ module axi4_slave_bfm #( parameter ECC_EN = 0, parameter ECC_ADDR_HI = 'h410, pa end else begin sh_cl_ddr_rvalid <= 1'b0; - sh_cl_ddr_rlast <= 1'b0; + sh_cl_ddr_rlast <= 1'b0; first_rd_beat = 1'b1; end @@ -384,11 +387,11 @@ module axi4_slave_bfm #( parameter ECC_EN = 0, parameter ECC_ADDR_HI = 'h410, pa end else begin - sh_cl_rd_data[0].len--; + sh_cl_rd_data[0].len--; end end - + end // always @ (posedge clk_core) function void axi_mem_bdr_write(input longint unsigned addr, byte d); @@ -399,7 +402,7 @@ module axi4_slave_bfm #( parameter ECC_EN = 0, parameter ECC_ADDR_HI = 'h410, pa end else t = 32'hffff_ffff; - + t = t & ~(32'h0000_00ff << (addr[1:0] * 8) ); t = t | ({24'h000000, d} << (addr[1:0] * 8) ); model_memory[{addr[63:2], 2'b00}] = t; @@ -418,5 +421,5 @@ module axi4_slave_bfm #( parameter ECC_EN = 0, parameter ECC_ADDR_HI = 'h410, pa d = 'hff; return d; endfunction // axi_mem_bdr_read - + endmodule diff --git a/hdk/common/shell_stable/design/sh_ddr/sim/axi_bfm_defines.svh b/hdk/common/shell_stable/design/sh_ddr/sim/axi_bfm_defines.svh index e8e8209dc..6b773f8e7 100755 --- a/hdk/common/shell_stable/design/sh_ddr/sim/axi_bfm_defines.svh +++ b/hdk/common/shell_stable/design/sh_ddr/sim/axi_bfm_defines.svh @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,7 +13,7 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. - +// ============================================================================ typedef struct { @@ -23,11 +24,10 @@ typedef struct { logic [1:0] resp; logic last; } AXI_Command; - + typedef struct { logic [511:0] data; logic [63:0] strb; logic [15:0] id; logic last; } AXI_Data; - diff --git a/hdk/common/shell_stable/design/sh_ddr/sim/axi_mem_model.sv b/hdk/common/shell_stable/design/sh_ddr/sim/axi_mem_model.sv index fa4b9f6b9..fa4ece3ce 100755 --- a/hdk/common/shell_stable/design/sh_ddr/sim/axi_mem_model.sv +++ b/hdk/common/shell_stable/design/sh_ddr/sim/axi_mem_model.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,12 +13,15 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + + module axi_mem_model #( parameter NUM_MEM = 3, parameter ECC_EN = 0, parameter ECC_ADDR_HI = 'h410, parameter ECC_ADDR_LO = 'h400, parameter RND_ECC_EN = 0, parameter RND_ECC_WEIGHT = 100) ( input clk_core, input rst_n, - + input[15:0] cl_sh_ddr_awid[NUM_MEM-1:0], input[63:0] cl_sh_ddr_awaddr[NUM_MEM-1:0], input[7:0] cl_sh_ddr_awlen[NUM_MEM-1:0], @@ -79,7 +83,7 @@ module axi_mem_model #( parameter NUM_MEM = 3, parameter ECC_EN = 0, parameter E .cl_sh_ddr_wlast(cl_sh_ddr_wlast[gi]), .cl_sh_ddr_wvalid(cl_sh_ddr_wvalid[gi]), .sh_cl_ddr_wready(sh_cl_ddr_wready[gi]), - + .sh_cl_ddr_bid(sh_cl_ddr_bid[gi]), .sh_cl_ddr_bresp(sh_cl_ddr_bresp[gi]), .sh_cl_ddr_bvalid(sh_cl_ddr_bvalid[gi]), diff --git a/hdk/common/software/include/cl_utils.h b/hdk/common/software/include/cl_utils.h index 3545afdd4..8d611d5da 100644 --- a/hdk/common/software/include/cl_utils.h +++ b/hdk/common/software/include/cl_utils.h @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ void sv_printf(char *msg); diff --git a/hdk/common/software/include/fpga_pci_sv.h b/hdk/common/software/include/fpga_pci_sv.h index 0de0bc983..8c998434f 100644 --- a/hdk/common/software/include/fpga_pci_sv.h +++ b/hdk/common/software/include/fpga_pci_sv.h @@ -1,20 +1,23 @@ -/* - * Copyright 2015-2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. A copy of the - * License is located at - * - * http://aws.amazon.com/apache2.0/ - * - * or in the "license" file accompanying this file. This file is distributed - * on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either - * express or implied. See the License for the specific language governing - * permissions and limitations under the License. - */ +// ============================================================================ +// Amazon FPGA Hardware Development Kit +// +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// +// Licensed under the Amazon Software License (the "License"). You may not use +// this file except in compliance with the License. A copy of the License is +// located at +// +// http://aws.amazon.com/asl/ +// +// or in the "license" file accompanying this file. This file is distributed on +// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +// implied. See the License for the specific language governing permissions and +// limitations under the License. +// ============================================================================ + /* - * This file is a SV wrapper header file for fpga_pci.h. + * This file is a SV wrapper header file for fpga_pci.h. */ #ifndef FPGA_PCI_SV_H_ #define FPGA_PCI_SV_H_ diff --git a/hdk/common/software/include/pcie_utils.h b/hdk/common/software/include/pcie_utils.h index 5e079bdc6..8d68bab72 100644 --- a/hdk/common/software/include/pcie_utils.h +++ b/hdk/common/software/include/pcie_utils.h @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ #include diff --git a/hdk/common/software/include/xdma_utils.h b/hdk/common/software/include/xdma_utils.h index 46fb237fd..3efa02c78 100644 --- a/hdk/common/software/include/xdma_utils.h +++ b/hdk/common/software/include/xdma_utils.h @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ #include diff --git a/hdk/common/software/src/cl_utils.c b/hdk/common/software/src/cl_utils.c index 29527a66b..b9d2d1667 100644 --- a/hdk/common/software/src/cl_utils.c +++ b/hdk/common/software/src/cl_utils.c @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,41 +13,41 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ #include #include #include -void +void sv_printf(char *msg) { printf("%s\n", msg); } -void +void sv_map_host_memory(uint8_t *memory) { // Does nothing on EC2 instance } -void +void cl_peek(uint64_t addr, uint32_t *data) { *data = peek((uint32_t) (addr & 0xffffffff)); } -void +void cl_poke(uint64_t addr, uint32_t data) { poke((uint32_t) (addr & 0xffffffff), data); } -void +void sv_pause(uint32_t x) { usleep(x); } - diff --git a/hdk/common/software/src/fpga_pci_sv.c b/hdk/common/software/src/fpga_pci_sv.c index 88b922ad5..1244406c4 100644 --- a/hdk/common/software/src/fpga_pci_sv.c +++ b/hdk/common/software/src/fpga_pci_sv.c @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + #include diff --git a/hdk/common/software/src/main.c b/hdk/common/software/src/main.c index 8827b6a31..ca53f249b 100644 --- a/hdk/common/software/src/main.c +++ b/hdk/common/software/src/main.c @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + #include #include diff --git a/hdk/common/software/src/pcie_utils.c b/hdk/common/software/src/pcie_utils.c index 1dab67703..68ce9d965 100644 --- a/hdk/common/software/src/pcie_utils.c +++ b/hdk/common/software/src/pcie_utils.c @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + #include #include @@ -132,7 +135,7 @@ pcie_find_all(char *ids[], int max) } } } - closedir(d); + closedir(d); return count; } @@ -158,7 +161,7 @@ pcie_find_first(void) return de.d_name; } } - closedir(d); + closedir(d); return NULL; } @@ -173,7 +176,7 @@ pcie_mmap(char *id, bool verify) if (fd < 0) { return false; } - + lseek(fd, 0x10, SEEK_SET); read(fd, &t_bar0, sizeof(t_bar0)); if (t_bar0 == 0) { @@ -195,7 +198,7 @@ pcie_mmap(char *id, bool verify) perror("/dev/mem"); return false; } - + t_base = (uintptr_t) mmap(0, MAP_SIZE, PROT_READ|PROT_WRITE, MAP_SHARED, fd, t_bar0); if (t_base == (uintptr_t) MAP_FAILED) { perror("mmap"); diff --git a/hdk/common/software/src/sh_dpi_tasks.c b/hdk/common/software/src/sh_dpi_tasks.c index cff043434..58afa2682 100644 --- a/hdk/common/software/src/sh_dpi_tasks.c +++ b/hdk/common/software/src/sh_dpi_tasks.c @@ -1,17 +1,20 @@ -/* - * Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. A copy of the - * License is located at - * - * http://aws.amazon.com/apache2.0/ - * - * or in the "license" file accompanying this file. This file is distributed - * on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either - * express or implied. See the License for the specific language governing - * permissions and limitations under the License. - */ +// ============================================================================ +// Amazon FPGA Hardware Development Kit +// +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// +// Licensed under the Amazon Software License (the "License"). You may not use +// this file except in compliance with the License. A copy of the License is +// located at +// +// http://aws.amazon.com/asl/ +// +// or in the "license" file accompanying this file. This file is distributed on +// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +// implied. See the License for the specific language governing permissions and +// limitations under the License. +// ============================================================================ + #include @@ -25,20 +28,20 @@ uint8_t host_memory_getc(uint64_t addr) { return *(uint8_t *)addr; } -void cosim_printf(const char *format, ...) -{ - static char sv_msg_buffer[256]; - va_list args; +void cosim_printf(const char *format, ...) +{ + static char sv_msg_buffer[256]; + va_list args; - va_start(args, format); - vsprintf(sv_msg_buffer, format, args); + va_start(args, format); + vsprintf(sv_msg_buffer, format, args); #ifdef SV_TEST - sv_printf(sv_msg_buffer); + sv_printf(sv_msg_buffer); #else - printf(sv_msg_buffer); + printf(sv_msg_buffer); #endif - va_end(args); + va_end(args); } void int_handler(uint32_t int_num) diff --git a/hdk/common/software/src/test_null.c b/hdk/common/software/src/test_null.c index b481d2a2e..4e0d4834a 100644 --- a/hdk/common/software/src/test_null.c +++ b/hdk/common/software/src/test_null.c @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ #include diff --git a/hdk/common/software/src/xdma_utils.c b/hdk/common/software/src/xdma_utils.c index 8cb96fe2d..dfa20f997 100644 --- a/hdk/common/software/src/xdma_utils.c +++ b/hdk/common/software/src/xdma_utils.c @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + #include "xdma_utils.h" @@ -27,9 +30,9 @@ void que_buffer_to_cl(int chan, uint8_t *buf, size_t len) { // setup descriptor table if this is first call if (h2c_desc_index == 0) { h2c_desc_table = (XDMA_DESC *)memalign(4096, 4096); // allocate 4k aligned to a 4k boundary - + sv_map_host_memory(h2c_desc_table); - + } h2c_desc_table[h2c_desc_index].header.word = 0; // make sure reserved bits and unused bits are 0 diff --git a/hdk/common/verif/include/aws_clk_gen_utils.svh b/hdk/common/verif/include/aws_clk_gen_utils.svh index 1d297753a..40fbcaa07 100644 --- a/hdk/common/verif/include/aws_clk_gen_utils.svh +++ b/hdk/common/verif/include/aws_clk_gen_utils.svh @@ -1,3 +1,20 @@ +// ============================================================================ +// Amazon FPGA Hardware Development Kit +// +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// +// Licensed under the Amazon Software License (the "License"). You may not use +// this file except in compliance with the License. A copy of the License is +// located at +// +// http://aws.amazon.com/asl/ +// +// or in the "license" file accompanying this file. This file is distributed on +// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +// implied. See the License for the specific language governing permissions and +// limitations under the License. +// ============================================================================ + // START SDA OFFSETS diff --git a/hdk/common/verif/include/cl_common_defines.vh b/hdk/common/verif/include/cl_common_defines.vh index 18bec62d6..207ce42e7 100644 --- a/hdk/common/verif/include/cl_common_defines.vh +++ b/hdk/common/verif/include/cl_common_defines.vh @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2023 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,7 +13,7 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. - +// ============================================================================ int error_count = 0; diff --git a/hdk/common/verif/include/common_base_test.svh b/hdk/common/verif/include/common_base_test.svh index 3947a0bf3..1ecbca75d 100644 --- a/hdk/common/verif/include/common_base_test.svh +++ b/hdk/common/verif/include/common_base_test.svh @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2023 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,7 +13,7 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. - +// ============================================================================ `define DDR_CHANNEL 0 `define HBM_CHANNEL 1 @@ -25,15 +26,7 @@ `define _64_GB 64'h0010_0000_0000 -`ifdef USE_32GB_DDR_DIMM - `define AWS_SIM_32GB_DDR -`elsif USE_AP_32GB_DDR_DIMM - `define AWS_SIM_32GB_DDR -`elsif USE_64GB_DDR_DIMM - `define AWS_SIM_64GB_DDR -`elsif USE_AP_64GB_DDR_DIMM - `define AWS_SIM_64GB_DDR -`endif +`define AWS_SIM_64GB_DDR int error_count = 0; @@ -63,4 +56,3 @@ task compare_data(logic [511:0] act_data, exp_data, logic [63:0] addr); $display("[%t]: Data Matched Addr: %0h. Actual Data:%0h <==> Expected Data: %0h", $realtime, addr, act_data, exp_data); end endtask - diff --git a/hdk/common/verif/include/sh_dpi_tasks.svh b/hdk/common/verif/include/sh_dpi_tasks.svh index 3dd6fc34f..44f70617f 100755 --- a/hdk/common/verif/include/sh_dpi_tasks.svh +++ b/hdk/common/verif/include/sh_dpi_tasks.svh @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + `ifndef SV_SH_DPI_TASKS `define SV_SH_DPI_TASKS @@ -33,7 +36,7 @@ import tb_type_defines_pkg::*; `endif `endif - + export "DPI-C" task sv_printf; export "DPI-C" task sv_map_host_memory; export "DPI-C" task cl_peek; @@ -46,10 +49,10 @@ import tb_type_defines_pkg::*; export "DPI-C" task sv_fpga_start_buffer_to_cl; export "DPI-C" task sv_fpga_start_cl_to_buffer; `endif - + static int h2c_desc_index = 0; static int c2h_desc_index = 0; - + task sv_printf(input string msg); $display("%S", msg); endtask @@ -61,7 +64,7 @@ import tb_type_defines_pkg::*; task cl_peek(input longint unsigned addr, output int unsigned data); tb.card.fpga.sh.peek(.addr(addr), .data(data), .intf(AxiPort::PORT_OCL)); endtask - + task cl_poke(input longint unsigned addr, int unsigned data); tb.card.fpga.sh.poke(.addr(addr), .data(data), .intf(AxiPort::PORT_OCL)); endtask @@ -69,7 +72,7 @@ import tb_type_defines_pkg::*; task sv_int_ack(input int unsigned int_num); tb.card.fpga.sh.set_ack_bit(int_num); endtask - + task sv_pause(input int x); repeat (x) #1us; endtask @@ -77,11 +80,11 @@ import tb_type_defines_pkg::*; task sv_fpga_pci_peek(input int handle, input longint unsigned offset, output int unsigned value); tb.card.fpga.sh.peek(.addr(offset), .data(value), .intf(AxiPort::PORT_OCL)); endtask - + task sv_fpga_pci_poke(input int handle, input longint unsigned addr, int unsigned data); tb.card.fpga.sh.poke(.addr(addr), .data(data), .intf(AxiPort::PORT_OCL)); - endtask - + endtask + function void hm_put_byte(input longint unsigned addr, byte d); if (tb.use_c_host_memory) host_memory_putc(addr, d); @@ -93,7 +96,7 @@ import tb_type_defines_pkg::*; end else t = 32'hffff_ffff; - + t = t & ~(32'h0000_00ff << (addr[1:0] * 8) ); t = t | ({24'h000000, d} << (addr[1:0] * 8) ); tb.sv_host_memory[{addr[63:2], 2'b00}] = t; @@ -115,7 +118,7 @@ import tb_type_defines_pkg::*; d = 'hff; end end - + return d; endfunction @@ -222,7 +225,7 @@ end for (int i = 0 ; i < buf_size ; i++) begin tb.hm_put_byte(.addr(host_memory_buffer_address), .d(tb.host_memory_getc(host_memory_ptr))); if(debug) begin - $display("[%t] : host_memory_address = %0x wr_buffer[%d] = %0x", $realtime, host_memory_buffer_address, i, tb.host_memory_getc(host_memory_ptr)); + $display("[%t] : host_memory_address = %0x wr_buffer[%d] = %0x", $realtime, host_memory_buffer_address, i, tb.host_memory_getc(host_memory_ptr)); end host_memory_ptr++ ; host_memory_buffer_address++; @@ -235,13 +238,13 @@ end #10ns; timeout_count++; end while ((status[chan] != 1) && (timeout_count < 4000)); // UNMATCHED !! - + if (timeout_count >= 4000) begin $display("[%t] : *** ERROR *** Timeout waiting for dma transfers to cl", $realtime); error_count++; end endtask // sv_fpga_start_buffer_to_cl - + //DPI task to transfer CL to HOST data. task sv_fpga_start_cl_to_buffer(input int slot_id = 0, input int chan, input int buf_size, input longint unsigned rd_buffer_addr, input longint unsigned cl_addr); int timeout_count, status, error_count; @@ -260,7 +263,7 @@ end for (int i = 0 ; i < buf_size ; i++) begin tb.hm_put_byte(.addr(host_memory_buffer_address + i), .d(tb.host_memory_getc(host_memory_ptr))); if(debug) begin - $display("[%t] : host_memory_address = %0x rd_buffer[%d] = %0x", $realtime, host_memory_buffer_address + i, i, tb.host_memory_getc(host_memory_ptr)); + $display("[%t] : host_memory_address = %0x rd_buffer[%d] = %0x", $realtime, host_memory_buffer_address + i, i, tb.host_memory_getc(host_memory_ptr)); end host_memory_ptr++ ; end @@ -274,7 +277,7 @@ end #10ns; timeout_count++; end while ((status[chan] != 1) && (timeout_count < 4000)); // UNMATCHED !! - + if (timeout_count >= 4000) begin $display("[%t] : *** ERROR *** Timeout waiting for dma transfers from cl", $realtime); error_count++; @@ -284,15 +287,15 @@ end for (int i = 0 ; i < buf_size ; i++) begin tb.host_memory_putc(host_memory_ptr, tb.hm_get_byte(host_memory_buffer_address + i)); if(debug) begin - $display("[%t] : host_memory_address = %0x rd_buffer[%d] = %0x", $realtime, host_memory_buffer_address + i, i, tb.hm_get_byte(host_memory_buffer_address + i)); + $display("[%t] : host_memory_address = %0x rd_buffer[%d] = %0x", $realtime, host_memory_buffer_address + i, i, tb.hm_get_byte(host_memory_buffer_address + i)); end host_memory_ptr++ ; end endtask // sv_fpga_start_cl_to_buffer `endif - - task power_up(input int slot_id = 0, + + task power_up(input int slot_id = 0, ClockRecipe::A_RECIPE clk_recipe_a = ClockRecipe::A0, ClockRecipe::B_RECIPE clk_recipe_b = ClockRecipe::B0, ClockRecipe::C_RECIPE clk_recipe_c = ClockRecipe::C0); @@ -372,11 +375,11 @@ end // //================================================= task poke(input int slot_id = 0, - logic [63:0] addr, - logic [511:0] data, - logic [5:0] id = 6'h0, - DataSize::DATA_SIZE size = DataSize::UINT32, - AxiPort::AXI_PORT intf = AxiPort::PORT_DMA_PCIS); + logic [63:0] addr, + logic [511:0] data, + logic [5:0] id = 6'h0, + DataSize::DATA_SIZE size = DataSize::UINT32, + AxiPort::AXI_PORT intf = AxiPort::PORT_DMA_PCIS); `SLOT_MACRO_TASK(poke(.addr(addr), .data(data), .id(id), .size(size), .intf(intf))) endtask @@ -389,10 +392,10 @@ end // //================================================= task poke_pcis(input int slot_id = 0, - logic [63:0] addr, - logic [511:0] data, - logic [63:0] strb, - logic [5:0] id = 6'h0); + logic [63:0] addr, + logic [511:0] data, + logic [63:0] strb, + logic [5:0] id = 6'h0); `SLOT_MACRO_TASK(poke_pcis(.addr(addr), .data(data), .id(id), .strb(strb))) endtask @@ -409,8 +412,8 @@ end // //========================================================================== task poke_pcis_wc(input int slot_id = 0, - input logic [63:0] addr, - logic [31:0] data [$], + input logic [63:0] addr, + logic [31:0] data [$], logic [5:0] id = 6'h0, logic [2:0] size = 3'd6 ); @@ -436,11 +439,11 @@ end // //================================================= task peek(input int slot_id = 0, - logic [63:0] addr, - output logic [511:0] data, - input logic [5:0] id = 6'h0, - DataSize::DATA_SIZE size = DataSize::UINT32, - AxiPort::AXI_PORT intf = AxiPort::PORT_DMA_PCIS); + logic [63:0] addr, + output logic [511:0] data, + input logic [5:0] id = 6'h0, + DataSize::DATA_SIZE size = DataSize::UINT32, + AxiPort::AXI_PORT intf = AxiPort::PORT_DMA_PCIS); `SLOT_MACRO_TASK(peek(.addr(addr), .data(data), .id(id), .size(size), .intf(intf))) endtask @@ -453,8 +456,8 @@ end // //================================================= task peek_pcis(input int slot_id = 0, - logic [63:0] addr, - output logic [511:0] data, + logic [63:0] addr, + output logic [511:0] data, input logic [5:0] id = 6'h0); `SLOT_MACRO_TASK(peek_pcis(.addr(addr), .data(data), .id(id))) endtask @@ -508,9 +511,9 @@ end // //================================================= task poke_ocl(input int slot_id = 0, - logic [63:0] addr, - logic [31:0] data, - logic [5:0] id = 6'h0); + logic [63:0] addr, + logic [31:0] data, + logic [5:0] id = 6'h0); `SLOT_MACRO_TASK(poke(.addr(addr), .data({32'h0, data}), .id(id), .size(DataSize::UINT32), .intf(AxiPort::PORT_OCL))) endtask @@ -526,9 +529,9 @@ end // //================================================= task peek_ocl(input int slot_id = 0, - logic [63:0] addr, - output logic [63:0] data, - input logic [5:0] id = 6'h0); + logic [63:0] addr, + output logic [63:0] data, + input logic [5:0] id = 6'h0); logic [63:0] tmp; `SLOT_MACRO_TASK(peek(.addr(addr), .data(tmp), .id(id), .size(DataSize::UINT32), .intf(AxiPort::PORT_OCL))) data = {32'h0, tmp[31:0]}; @@ -546,8 +549,8 @@ end // //================================================= task poke_sda(input int slot_id = 0, - logic [63:0] addr, - logic [31:0] data, + logic [63:0] addr, + logic [31:0] data, logic [5:0] id = 6'h00); `SLOT_MACRO_TASK(poke(.addr(addr), .data({32'h0, data}), .id(id), .size(DataSize::UINT32), .intf(AxiPort::PORT_SDA))) endtask @@ -564,9 +567,9 @@ end // //================================================= task peek_sda(input int slot_id = 0, - logic [63:0] addr, - output logic [63:0] data, - input logic [5:0] id = 6'h0); + logic [63:0] addr, + output logic [63:0] data, + input logic [5:0] id = 6'h0); logic [63:0] tmp; `SLOT_MACRO_TASK(peek(.addr(addr), .data(tmp), .id(id), .size(DataSize::UINT32), .intf(AxiPort::PORT_SDA))) @@ -574,13 +577,13 @@ end endtask function bit is_dma_to_cl_done(input int slot_id = 0, input int chan); - `SLOT_MACRO_FUNC(is_dma_to_cl_done(chan)) + `SLOT_MACRO_FUNC(is_dma_to_cl_done(chan)) endfunction // is_dma_to_cl_done function int get_ecc_err_cnt(input int slot_id = 0); - `SLOT_MACRO_FUNC(get_ecc_err_cnt()) + `SLOT_MACRO_FUNC(get_ecc_err_cnt()) endfunction // is_dma_to_cl_done - + function bit is_dma_to_buffer_done(input int slot_id = 0, input int chan); `SLOT_MACRO_FUNC(is_dma_to_buffer_done(chan)) endfunction // is_dma_to_buffer_done @@ -588,7 +591,7 @@ end function bit is_ddr_ready(input int slot_id = 0); `SLOT_MACRO_TASK(is_ddr_ready()) endfunction // is_dma_to_buffer_done - + task poke_stat(input int slot_id = 0, input logic [7:0] addr, string intf, logic[31:0] data); `SLOT_MACRO_TASK(poke_stat(.addr(addr), .intf(intf), .data(data))) @@ -635,7 +638,7 @@ end task wait_clock( input int count, int slot_id = 0 - ); + ); `SLOT_MACRO_TASK(wait_clock(.count(count))) endtask : wait_clock @@ -650,7 +653,7 @@ end function void set_chk_clk_freq(input int slot_id = 0, logic chk_freq = 1'b1); `SLOT_MACRO_TASK(set_chk_clk_freq(chk_freq)) endfunction // chk_clk_freq - + //================================================= // // chk_prot_err_stat @@ -674,7 +677,7 @@ end function logic chk_clk_err_cnt(input int slot_id = 0); `SLOT_MACRO_FUNC(chk_clk_err_cnt()); endfunction // chk_clk_err_cnt - + //================================================= // // get_global_counter_0 @@ -698,5 +701,5 @@ end function logic [63:0] get_global_counter_1(input int slot_id = 0); `SLOT_MACRO_FUNC(get_global_counter_1()); endfunction // get_global_counter_1 - + `endif diff --git a/hdk/common/verif/models/base/gen_buf_t.sv b/hdk/common/verif/models/base/gen_buf_t.sv index addd93f87..5cf133dfc 100644 --- a/hdk/common/verif/models/base/gen_buf_t.sv +++ b/hdk/common/verif/models/base/gen_buf_t.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ //************************************************************************************* @@ -27,7 +29,7 @@ `define __DEFINED_GEN_BUF_T__ class gen_buf_t; - + logic[7:0] data[$]; bit print_ok_compare = 0; @@ -35,11 +37,11 @@ //Input size of buffer in bytes -- assume address of all f's is "null" function new (); endfunction - + //Initialization with incrementing data. Note this assumes empty array (queue), and adds entries to the array virtual function void init_inc(input[31:0] first_data, input int length = 4); bit[31:0] tmp_data; - + tmp_data = first_data; for (int i=0; i> 4; data_fp[i+1][(j*4+3) -: 4] = data_t[3:0];//7-4 data_t = data >> 8; data = data_t; end // for (int j=0; j<8; j++) - + $fdisplay(fp[i], "%0h %0h %0h %0h %h", bank_group_a, bank_a, row_a, col_a, data_fp[i] [31:0]); $fdisplay(fp[i+1], "%0h %0h %0h %0h %h", bank_group_a, bank_a, row_a, col_a, data_fp[i+1][31:0]); @@ -204,14 +207,14 @@ $fdisplay(fp[i+1], "%0h %0h %0h %0h %h", bank_group_b, bank_b, row_b, col_b, data_fp[i+1][31:0]); end - //ECC + //ECC $fdisplay(fp[14], "%0h %0h %0h %0h %h", bank_group_a, bank_a, row_a, col_a, 'h0); $fdisplay(fp[15], "%0h %0h %0h %0h %h", bank_group_a, bank_a, row_a, col_a, 'h0); //ECC $fdisplay(fp[14], "%0h %0h %0h %0h %h", bank_group_b, bank_b, row_b, col_b, 'h0); $fdisplay(fp[15], "%0h %0h %0h %0h %h", bank_group_b, bank_b, row_b, col_b, 'h0); - + for (int i=16; i<18; i=i+2) begin data_t = data; //Each device is 32-bits wide. 64-bit data is loaded as below. @@ -230,13 +233,13 @@ $fdisplay(fp[i], "%0h %0h %0h %0h %h", bank_group_b, bank_b, row_b, col_b, data_fp[i] [31:0]); $fdisplay(fp[i+1], "%0h %0h %0h %0h %h", bank_group_b, bank_b, row_b, col_b, data_fp[i+1][31:0]); end // for (int i=16; i<18; i=i+2) - + for (int i=8; i<13; i=i+2) begin data_t = data; //Each device is 32-bits wide. 64-bit data is loaded as below. for (int j=0; j<8; j++) begin data_fp[i][(j*4+3) -: 4] = data_t[3:0]; - + data_t = data >> 4; data_fp[i+1][(j*4+3) -: 4] = data_t[3:0]; @@ -249,13 +252,13 @@ $fdisplay(fp[i], "%0h %0h %0h %0h %h", bank_group_b, bank_b, row_b, col_b, data_fp[i] [31:0]); $fdisplay(fp[i+1], "%0h %0h %0h %0h %h", bank_group_b, bank_b, row_b, col_b, data_fp[i+1][31:0]); end // for (int i=8; i<13; i=i+2) - + endtask // write_bdr_ld_data_to_file task write_bdr_ld_raw_data_to_file(int ddr_file, logic [16:0] row_a, logic [1:0] bank_a, logic [9:0] col_a, logic [1:0] bank_group_a, logic [31:0] data); $fdisplay(ddr_file, "%0d %0d %0d %0d %h", bank_group_a, bank_a, row_a, col_a, data); endtask // write_bdr_ld_raw_data_to_file - + task ddr_bdr_ld(string file_name); logic [63:0] addr; logic [511:0] data; @@ -265,9 +268,9 @@ // Line buffer reg [12*100:1] line; int c; - + axi_fp = $fopen(file_name, "r"); - + for (int i=0; i<18; i++) begin ddr_name[i] = $sformatf("ddr4_ddr_%0d.mem", i); $display("ddr_name is %0s \n", ddr_name[i]); @@ -276,7 +279,7 @@ $display("Could not open file %s", ddr_name[i]); end end - //Config information for memory. + //Config information for memory. for (int i=0; i<18; i++) begin write_cfg_info_to_file(fp[i]); end @@ -297,7 +300,7 @@ end device_bdr_ld(); endtask // ddr_bdr_ld - + task device_bdr_ld(); for (int i=0; i<18; i++) begin ddr_name[i] = $sformatf("ddr4_ddr_%0d.mem", i); @@ -326,4 +329,3 @@ endtask // device_bdr_ld `endif//NO_DDR - diff --git a/hdk/common/verif/models/sh_bfm/axi_bfm_defines.svh b/hdk/common/verif/models/sh_bfm/axi_bfm_defines.svh index e8e8209dc..6b773f8e7 100644 --- a/hdk/common/verif/models/sh_bfm/axi_bfm_defines.svh +++ b/hdk/common/verif/models/sh_bfm/axi_bfm_defines.svh @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,7 +13,7 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. - +// ============================================================================ typedef struct { @@ -23,11 +24,10 @@ typedef struct { logic [1:0] resp; logic last; } AXI_Command; - + typedef struct { logic [511:0] data; logic [63:0] strb; logic [15:0] id; logic last; } AXI_Data; - diff --git a/hdk/common/verif/models/sh_bfm/axil_bfm.sv b/hdk/common/verif/models/sh_bfm/axil_bfm.sv index dcf17dc82..9baa44ff6 100644 --- a/hdk/common/verif/models/sh_bfm/axil_bfm.sv +++ b/hdk/common/verif/models/sh_bfm/axil_bfm.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,13 +13,15 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ -module axil_bfm + +module axil_bfm ( input axil_clk, input axil_rst_n, output logic axil_awvalid, - output logic [31:0] axil_awaddr, + output logic [31:0] axil_awaddr, input axil_awready, //Write data @@ -26,34 +29,34 @@ module axil_bfm output logic [31:0] axil_wdata, output logic [3:0] axil_wstrb, input axil_wready, - + //Write response input axil_bvalid, input [1:0] axil_bresp, output logic axil_bready, - + //Read address output logic axil_arvalid, output logic [31:0] axil_araddr, input axil_arready, - + //Read data/response input axil_rvalid, input [31:0] axil_rdata, input [1:0] axil_rresp, - + output logic axil_rready ); `include "axi_bfm_defines.svh" - + AXI_Command axil_wr_cmds[$]; AXI_Data axil_wr_data[$]; AXI_Command axil_rd_cmds[$]; AXI_Data axil_rd_data[$]; AXI_Command axil_b_resps[$]; - + bit debug; initial begin @@ -82,10 +85,10 @@ module axil_bfm if (axil_wr_cmds.size() != 0) begin axil_awaddr <= axil_wr_cmds[0].addr[31:0]; - + axil_awvalid <= !axil_awvalid ? 1'b1 : !axil_awready ? 1'b1 : 1'b0; - + if (axil_awready && axil_awvalid) begin if (debug) begin $display("[%t] : DEBUG popping cmd fifo - %d", $realtime, axil_wr_cmds.size()); @@ -109,17 +112,17 @@ module axil_bfm axil_wdata <= axil_wr_data[0].data[31:0]; axil_wstrb <= axil_wr_data[0].strb[3:0]; - + axil_wvalid <= !axil_wvalid ? 1'b1 : !axil_wready ? 1'b1 : 1'b0; - + if (axil_wready && axil_wvalid) begin if (debug) begin $display("[%t] : DEBUG popping wr data fifo - %d", $realtime, axil_wr_data.size()); end axil_wr_data.pop_front(); end - + end else axil_wvalid <= 1'b0; @@ -152,10 +155,10 @@ module axil_bfm if (axil_rd_cmds.size() != 0) begin axil_araddr <= axil_rd_cmds[0].addr[31:0]; - + axil_arvalid <= !axil_arvalid ? 1'b1 : !axil_arready ? 1'b1 : 1'b0; - + if (axil_arready && axil_arvalid) begin if (debug) begin $display("[%t] : DEBUG popping cmd fifo - %d", $realtime, axil_rd_cmds.size()); @@ -186,19 +189,19 @@ module axil_bfm $display("[%t] - DEBUG read data [%2d]: 0x%08h", $realtime, i, axil_rdata[(i*32)+:32]); end end - + axil_rd_data.push_back(data); end end - + task poke(input logic [31:0] addr, logic [31:0] data, int size = 2); AXI_Command axi_cmd; AXI_Data axi_data; - logic [1:0] resp; + logic [1:0] resp; logic [63:0] strb; axi_cmd.addr[31:0] = addr; @@ -222,19 +225,19 @@ module axil_bfm axi_data.last = 1'b1; #20ns axil_wr_data.push_back(axi_data); - + while (axil_b_resps.size() == 0) #20ns; - + resp = axil_b_resps[0].resp; axil_b_resps.pop_front(); - + endtask // poke task peek(input logic [31:0] addr, output logic [31:0] data, input int size = 2); AXI_Command axi_cmd; logic [31:0] mask; - + axi_cmd.addr[31:0] = addr; axi_cmd.len = 0; @@ -257,7 +260,7 @@ module axil_bfm data &= mask; axil_rd_data.pop_front(); - + endtask // peek diff --git a/hdk/common/verif/models/sh_bfm/axis_bfm.sv b/hdk/common/verif/models/sh_bfm/axis_bfm.sv index a094dfd64..46dee0058 100644 --- a/hdk/common/verif/models/sh_bfm/axis_bfm.sv +++ b/hdk/common/verif/models/sh_bfm/axis_bfm.sv @@ -1,7 +1,7 @@ -//------------------------------------------------------------------------------ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -13,16 +13,17 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. -//------------------------------------------------------------------------------ +// ============================================================================ + `include "anp_base_macros.svh" //------------------------------------------------------------------------------ // Module: axis_bfm // Main AXIS BFM module. Both of Master and Slave mode are implemented. -// Shall set the IS_MASTER parameter as below to selet the mode during +// Shall set the IS_MASTER parameter as below to selet the mode during // instantiation. -// Master mode -> IS_MASTER=1 +// Master mode -> IS_MASTER=1 // Slave mode -> IS_MASTER=0 //------------------------------------------------------------------------------ module axis_bfm #( @@ -36,7 +37,7 @@ module axis_bfm #( input wire axis_clk, input wire axis_rst_n, inout wire axis_valid, - inout wire [DATA_WIDTH-1:0] axis_data, + inout wire [DATA_WIDTH-1:0] axis_data, inout wire axis_last, inout wire [KEEP_WIDTH-1:0] axis_keep, inout wire [USER_WIDTH-1:0] axis_user, @@ -49,7 +50,7 @@ module axis_bfm #( // Local variables //--------------------------------------------------------------------------- logic m_axis_valid; - logic [DATA_WIDTH-1:0] m_axis_data; + logic [DATA_WIDTH-1:0] m_axis_data; logic m_axis_last; logic [KEEP_WIDTH-1:0] m_axis_keep; logic [USER_WIDTH-1:0] m_axis_user; @@ -123,7 +124,7 @@ module axis_bfm #( //--------------------------------------------------------------------------- // Drive Output signals //--------------------------------------------------------------------------- - generate + generate if (IS_MASTER == 1) begin : MASTER_MODE assign axis_valid = m_axis_valid; @@ -146,13 +147,13 @@ module axis_bfm #( generate if (IS_MASTER) begin : MASTER - - initial + + initial begin : READ_TEXT_STIMULUS string fname; - + wait (mbx_created_e.triggered); - + if (FILE_NAME == "") begin fname = {hdl_path, ".in"}; end @@ -164,7 +165,7 @@ module axis_bfm #( if (fp_i != 0) begin : OPENED read_file = 1; `anp_info( - {"read_stim: Driving master packet using stimulus file ", fname}, + {"read_stim: Driving master packet using stimulus file ", fname}, MSG_ID) axis_bfm_pkg::read_stim( @@ -173,17 +174,17 @@ module axis_bfm #( .msg_id (MSG_ID)); end : OPENED - + stim_done = 1; `anp_info("drive_stim: Done", MSG_ID) end : READ_TEXT_STIMULUS - - initial + + initial begin : DRIVE_TEXT_STIMULUS string fname; - + wait_out_of_reset($sformatf("drive_stim(%0d)", `__LINE__)); - + forever begin axis_bfm_pkt pkt; stim_mbx.get(pkt); @@ -191,7 +192,7 @@ module axis_bfm #( wait_clock(pkt.delay); drive_packet(pkt.data); end - + end : DRIVE_TEXT_STIMULUS end : MASTER @@ -313,10 +314,10 @@ module axis_bfm #( delay++; end - `anp_debug($sformatf("monitor_packet: Looking for next packet#%0d", + `anp_debug($sformatf("monitor_packet: Looking for next packet#%0d", packets), MSG_ID) - while ((axis_valid & axis_ready & axis_last) !== 1'b1) + while ((axis_valid & axis_ready & axis_last) !== 1'b1) begin : SAMPLE if ((axis_valid & axis_ready) === 1'b1) begin sampling <= 1; @@ -325,7 +326,7 @@ module axis_bfm #( pkt.data.push_back(axis_data[i*8+:8]); end end - `anp_debug($sformatf("monitor_packet: Sampling packet#%0d", + `anp_debug($sformatf("monitor_packet: Sampling packet#%0d", packets), MSG_ID) @ (posedge axis_clk); #1ns; @@ -355,7 +356,7 @@ module axis_bfm #( pkt.dump(fp_o, delay); end - `anp_info($sformatf("monitor_packet: Complete Sampling packet#%0d. %0s", + `anp_info($sformatf("monitor_packet: Complete Sampling packet#%0d. %0s", packets, pkt.print), MSG_ID) packets++; @@ -394,7 +395,7 @@ module axis_bfm #( drive_mbx .get(exp); monitor_mbx.get(act); void'(exp.compare( - .rhs (act), + .rhs (act), .message ($sformatf("%0s-SELF-CHECK Pkt-%0d", MSG_ID, packets)))); packets++; end @@ -402,4 +403,3 @@ module axis_bfm #( end endmodule : axis_bfm - diff --git a/hdk/common/verif/models/sh_bfm/axis_bfm_pkg.sv b/hdk/common/verif/models/sh_bfm/axis_bfm_pkg.sv index 89b7670f0..db0a69c56 100644 --- a/hdk/common/verif/models/sh_bfm/axis_bfm_pkg.sv +++ b/hdk/common/verif/models/sh_bfm/axis_bfm_pkg.sv @@ -1,7 +1,7 @@ -//------------------------------------------------------------------------------ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -13,7 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. -//------------------------------------------------------------------------------ +// ============================================================================ + `include "anp_base_macros.svh" @@ -47,11 +48,11 @@ package axis_bfm_pkg; //--------------------------------------------------------------------------- // Function: read_stim - // Common function to read the stimulus file that matched the AXIS packet + // Common function to read the stimulus file that matched the AXIS packet // stimulus format //--------------------------------------------------------------------------- task automatic read_stim( - axis_mbx_t mbx_h, + axis_mbx_t mbx_h, int fp, string msg_id ); @@ -60,11 +61,11 @@ package axis_bfm_pkg; int delay; _eof = 0; - + while (!_eof) begin string _line; int _line_ret; - + _line_ret = $fgets(_line, fp); _eof = $feof(fp); @@ -102,7 +103,7 @@ package axis_bfm_pkg; else if (first != "SOP" && first != "IDLE") begin int str_len; str_len = first.len(); - + if (str_len % 2) begin `anp_fatal({ "read_stim: Detected HEX data length which is not aligned with format. ", @@ -114,7 +115,7 @@ package axis_bfm_pkg; int data_value; data_value = first.substr(b, b+1).atohex(); data_tmp.push_back(data_value); - `anp_debug($sformatf("read_stim: Pushed 0x%02H into data_tmp. data_tmp.size=%0d", + `anp_debug($sformatf("read_stim: Pushed 0x%02H into data_tmp. data_tmp.size=%0d", data_value, data_tmp.size()), msg_id) end @@ -221,7 +222,7 @@ package axis_bfm_pkg; end else begin `anp_info($sformatf( - "compare: (%0s) Passed! PacketLength=%0d", + "compare: (%0s) Passed! PacketLength=%0d", message, rhs_size)) end return result; @@ -239,4 +240,3 @@ package axis_bfm_pkg; endclass : axis_bfm_pkt endpackage : axis_bfm_pkg - diff --git a/hdk/common/verif/models/sh_bfm/axis_sim/clean.sh b/hdk/common/verif/models/sh_bfm/axis_sim/clean.sh index a44211034..d126450bd 100755 --- a/hdk/common/verif/models/sh_bfm/axis_sim/clean.sh +++ b/hdk/common/verif/models/sh_bfm/axis_sim/clean.sh @@ -1,5 +1,23 @@ #!/bin/bash +# ============================================================================= +# Amazon FPGA Hardware Development Kit +# +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + + rm -rf csrc rm -rf *.out rm -rf *.in @@ -10,4 +28,3 @@ rm -rf *.vpd rm -rf passed rm -rf failed rm -rf DVEfiles - diff --git a/hdk/common/verif/models/sh_bfm/axis_sim/genstim.sh b/hdk/common/verif/models/sh_bfm/axis_sim/genstim.sh index c4c2834ff..35fb13adb 100755 --- a/hdk/common/verif/models/sh_bfm/axis_sim/genstim.sh +++ b/hdk/common/verif/models/sh_bfm/axis_sim/genstim.sh @@ -1,5 +1,23 @@ #!/bin/bash +# ============================================================================= +# Amazon FPGA Hardware Development Kit +# +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + + ./runme.sh +GEN_STIM +AXIS_DUMP_PACKET +AXIS_DUMP_PACKET_WITH_IDLE +ntb_random_seed=9 +PACKETS=50 +MIN_LEN=20 +MAX_LEN=1516 cp -rf master.out $CL_DIR/verif/scripts/stimulus/mac0_tx.in @@ -10,4 +28,3 @@ cp -rf master.out $CL_DIR/verif/scripts/stimulus/mac1_tx.in cp -rf master.out $CL_DIR/verif/scripts/stimulus/h2c.in ./clean.sh - diff --git a/hdk/common/verif/models/sh_bfm/axis_sim/runme.sh b/hdk/common/verif/models/sh_bfm/axis_sim/runme.sh index fc4b7deb0..5daa8280a 100755 --- a/hdk/common/verif/models/sh_bfm/axis_sim/runme.sh +++ b/hdk/common/verif/models/sh_bfm/axis_sim/runme.sh @@ -1,5 +1,23 @@ #!/bin/bash +# ============================================================================= +# Amazon FPGA Hardware Development Kit +# +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + + vcs -R -sverilog +vcs+lic+wait\ -timescale=1ns/1ns\ -debug_access+all\ @@ -12,5 +30,4 @@ vcs -R -sverilog +vcs+lic+wait\ +ANP_MSG_SHOW_FILE_INFO\ +AXIS_DUMP_MONITORED_PACKET\ -l sim.log\ - $* - + $* diff --git a/hdk/common/verif/models/sh_bfm/axis_sim/test.sv b/hdk/common/verif/models/sh_bfm/axis_sim/test.sv index fae2576c4..83c4367fe 100644 --- a/hdk/common/verif/models/sh_bfm/axis_sim/test.sv +++ b/hdk/common/verif/models/sh_bfm/axis_sim/test.sv @@ -1,3 +1,21 @@ +// ============================================================================ +// Amazon FPGA Hardware Development Kit +// +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// +// Licensed under the Amazon Software License (the "License"). You may not use +// this file except in compliance with the License. A copy of the License is +// located at +// +// http://aws.amazon.com/asl/ +// +// or in the "license" file accompanying this file. This file is distributed on +// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +// implied. See the License for the specific language governing permissions and +// limitations under the License. +// ============================================================================ + + module test(); import axis_bfm_pkg::*; @@ -9,12 +27,12 @@ module test(); logic axis_clk; logic axis_rst_n; wire axis_valid; - wire [DATA_WIDTH-1:0] axis_data; + wire [DATA_WIDTH-1:0] axis_data; wire axis_last; wire [KEEP_WIDTH-1:0] axis_keep; wire [USER_WIDTH-1:0] axis_user; wire axis_ready; - + axis_bfm #( .FILE_NAME ("master"), .DATA_WIDTH (DATA_WIDTH), @@ -70,7 +88,7 @@ module test(); for (int i = 0; i < size; i++) begin if (i < size) data[i] = tmp_data[8*i[1:0]+:8]; if (i[1:0] == 2'b11) tmp_data++; - end + end c.data = data; master.drive_packet(c.data); end @@ -91,4 +109,3 @@ module test(); final anp_base_pkg::end_of_test(); endmodule : test - diff --git a/hdk/common/verif/models/sh_bfm/axis_sim/testme.sh b/hdk/common/verif/models/sh_bfm/axis_sim/testme.sh index 066093768..af6d0c534 100755 --- a/hdk/common/verif/models/sh_bfm/axis_sim/testme.sh +++ b/hdk/common/verif/models/sh_bfm/axis_sim/testme.sh @@ -1,5 +1,23 @@ #!/bin/bash +# ============================================================================= +# Amazon FPGA Hardware Development Kit +# +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + + ./runme.sh\ +AXIS_CHECK_DRIVE_AND_MONITOR +AXIS_RAND_READY\ +GEN_STIM +AXIS_DUMP_PACKET +AXIS_DUMP_PACKET_WITH_IDLE\ @@ -11,4 +29,3 @@ cp -rf master.out master.in +AXIS_CHECK_DRIVE_AND_MONITOR +AXIS_RAND_READY ./clean.sh - diff --git a/hdk/common/verif/models/sh_bfm/sh_bfm.sv b/hdk/common/verif/models/sh_bfm/sh_bfm.sv index 48a8ac3fe..1cf83eb9f 100644 --- a/hdk/common/verif/models/sh_bfm/sh_bfm.sv +++ b/hdk/common/verif/models/sh_bfm/sh_bfm.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + `ifndef TB_TOP `define TB_TOP tb diff --git a/hdk/common/verif/models/sh_bfm/sh_bfm_defines.svh b/hdk/common/verif/models/sh_bfm/sh_bfm_defines.svh index 1d523ac0e..1ec01f9ca 100644 --- a/hdk/common/verif/models/sh_bfm/sh_bfm_defines.svh +++ b/hdk/common/verif/models/sh_bfm/sh_bfm_defines.svh @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + `ifndef SH_BFM_DEFINES `define SH_BFM_DEFINES diff --git a/hdk/common/verif/models/stream_bfm/stream_bfm.sv b/hdk/common/verif/models/stream_bfm/stream_bfm.sv index 2ca02d36a..7c92edf9f 100644 --- a/hdk/common/verif/models/stream_bfm/stream_bfm.sv +++ b/hdk/common/verif/models/stream_bfm/stream_bfm.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + //Note KEEP_WIDTH is same as number of bytes in data bus module stream_bfm #(parameter DATA_WIDTH=512, parameter KEEP_WIDTH=DATA_WIDTH/8, parameter USER_WIDTH=64)( @@ -24,13 +27,13 @@ module stream_bfm #(parameter DATA_WIDTH=512, parameter KEEP_WIDTH=DATA_WIDTH/8, input ins_last, input[USER_WIDTH-1:0] ins_user, output logic ins_ready, - + output logic[DATA_WIDTH-1:0] ots_data, output logic[KEEP_WIDTH-1:0] ots_keep, output logic[USER_WIDTH-1:0] ots_user, output logic ots_valid, output logic ots_last, - input ots_ready + input ots_ready ); gen_buf_t tx_pkt_q[$]; @@ -86,14 +89,14 @@ endfunction // Get RX Packet Queue size //---------------------------------- function int get_rx_pkt_q_size(); - get_rx_pkt_q_size = rx_pkt_q.size(); + get_rx_pkt_q_size = rx_pkt_q.size(); endfunction //---------------------------------- // Get TX Packet Queue size //---------------------------------- function int get_tx_pkt_q_size(); - get_tx_pkt_q_size = tx_pkt_q.size(); + get_tx_pkt_q_size = tx_pkt_q.size(); endfunction //--------------------------------------- @@ -121,7 +124,7 @@ endfunction //---------------------------------------------------------------------- //---------------------------------------------------------------------- -// BFM functionality +// BFM functionality //---------------------------------------------------------------------- //---------------------------------------------------------------------- @@ -150,7 +153,7 @@ task tx_pkt_thread; for (int i=0; i<4; i++) if (cur_pkt.data.size() > i) data[8*i+:8] = cur_pkt.data[i]; - + num_phases = cur_pkt.data.size()/(KEEP_WIDTH); if ((cur_pkt.data.size() % KEEP_WIDTH) != 0) begin @@ -208,7 +211,7 @@ task rx_pkt_thread; gen_buf_t cur_pkt; - bit pkt_inp; + bit pkt_inp; logic[31:0] tmp_data; @@ -222,7 +225,7 @@ task rx_pkt_thread; //If not currently receiving a packet create a new packet if (!pkt_inp) begin - cur_pkt = new(); + cur_pkt = new(); pkt_inp = 1; end @@ -238,10 +241,10 @@ task rx_pkt_thread; rx_pkt_q.push_back(cur_pkt); rx_pkt_user_q.push_back(ins_user); end - + pkt_inp = 0; - - //Get first DW of data for display + + //Get first DW of data for display tmp_data = 0; for (int i=0; i<4; i++) if (cur_pkt.data.size() > i) @@ -265,7 +268,7 @@ task ins_bp_thread; int dly; - forever + forever begin while (!ins_bp_en) @(posedge clk); @@ -284,7 +287,7 @@ task ins_bp_thread; end endtask - + //-------------------------------------------------------------------------- // Reaset thread //-------------------------------------------------------------------------- @@ -305,7 +308,7 @@ endtask initial begin - fork + fork rst_thread; tx_pkt_thread; rx_pkt_thread; @@ -314,4 +317,3 @@ begin end endmodule - diff --git a/hdk/common/verif/packages/anp_base_macros.svh b/hdk/common/verif/packages/anp_base_macros.svh index 57c52fc32..68c99ef12 100644 --- a/hdk/common/verif/packages/anp_base_macros.svh +++ b/hdk/common/verif/packages/anp_base_macros.svh @@ -1,7 +1,7 @@ -//------------------------------------------------------------------------------ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -13,7 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. -//------------------------------------------------------------------------------ +// ============================================================================ + `ifndef __ANP_BASE_MACROS_SVH__ `define __ANP_BASE_MACROS_SVH__ @@ -118,4 +119,3 @@ `define anp_base_urm_cov_parg(MSG_ID=msg_id) `endif//__ANP_BASE_MACROS_SVH__ - diff --git a/hdk/common/verif/packages/anp_base_pkg.sv b/hdk/common/verif/packages/anp_base_pkg.sv index 800bf8cfc..d04ef2c85 100644 --- a/hdk/common/verif/packages/anp_base_pkg.sv +++ b/hdk/common/verif/packages/anp_base_pkg.sv @@ -1,7 +1,7 @@ -//------------------------------------------------------------------------------ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -13,7 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. -//------------------------------------------------------------------------------ +// ============================================================================ + package anp_base_pkg; @@ -64,5 +65,3 @@ package anp_base_pkg; endfunction : end_of_test endpackage : anp_base_pkg - - diff --git a/hdk/common/verif/scripts/cl_ports_gen.pl b/hdk/common/verif/scripts/cl_ports_gen.pl index 8a891816a..09bda7f78 100755 --- a/hdk/common/verif/scripts/cl_ports_gen.pl +++ b/hdk/common/verif/scripts/cl_ports_gen.pl @@ -1,8 +1,9 @@ #!/usr/bin/env perl -#------------------------------------------------------------------------------- + +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -14,7 +15,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. -#------------------------------------------------------------------------------- +# ============================================================================= + #=============================================================================== # Perl libs to be used in this script. diff --git a/hdk/common/verif/scripts/compile_cl_ips.py b/hdk/common/verif/scripts/compile_cl_ips.py index bd59629f1..e9fb75886 100755 --- a/hdk/common/verif/scripts/compile_cl_ips.py +++ b/hdk/common/verif/scripts/compile_cl_ips.py @@ -1,8 +1,9 @@ #!/usr/bin/env python3 +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2023 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -14,6 +15,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= + import os import sys diff --git a/hdk/common/verif/scripts/convert_eth_stim_type0.pl b/hdk/common/verif/scripts/convert_eth_stim_type0.pl index 54843f711..2371cbcc3 100755 --- a/hdk/common/verif/scripts/convert_eth_stim_type0.pl +++ b/hdk/common/verif/scripts/convert_eth_stim_type0.pl @@ -1,8 +1,9 @@ #!/usr/bin/env perl -#------------------------------------------------------------------------------- + +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -14,7 +15,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. -#------------------------------------------------------------------------------- +# ============================================================================= + #=============================================================================== # Perl libs to be used in this script. @@ -131,4 +133,3 @@ sub debug { my $s = shift; print "-D- $s\n" if defined $ENV{DEBUG_PRINT}; } - diff --git a/hdk/common/verif/scripts/convert_eth_stim_type1.pl b/hdk/common/verif/scripts/convert_eth_stim_type1.pl index d29fb1128..9ef3ce004 100755 --- a/hdk/common/verif/scripts/convert_eth_stim_type1.pl +++ b/hdk/common/verif/scripts/convert_eth_stim_type1.pl @@ -1,8 +1,9 @@ #!/usr/bin/env perl -#------------------------------------------------------------------------------- + +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -14,7 +15,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. -#------------------------------------------------------------------------------- +# ============================================================================= + #=============================================================================== # Perl libs to be used in this script. @@ -135,4 +137,3 @@ sub debug { my $s = shift; print "-D- $s\n" if defined $ENV{DEBUG_PRINT}; } - diff --git a/hdk/common/verif/scripts/generate_sim_file_list.py b/hdk/common/verif/scripts/generate_sim_file_list.py index 18181d808..828fc2bf1 100755 --- a/hdk/common/verif/scripts/generate_sim_file_list.py +++ b/hdk/common/verif/scripts/generate_sim_file_list.py @@ -1,13 +1,22 @@ #!/usr/bin/env python3 # ============================================================================= -# Copyright 2023 Amazon.com, Inc. or its affiliates. -# All Rights Reserved Worldwide. -# Amazon Confidential information -# Restricted NDA Material +# Amazon FPGA Hardware Development Kit +# +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. # ============================================================================= - import os import fileinput from glob import glob @@ -29,7 +38,7 @@ def get_generated_file_list(cl_dir, simulator): all_file_objects: list[str] = glob(f'{cl_dir}/design/**', recursive=True) all_file_paths = [obj for obj in all_file_objects if os.path.isfile(obj)] all_dir_paths = [obj for obj in all_file_objects if os.path.isdir(obj)] - + generated_file_list = [''] for dir_path in all_dir_paths: generated_file_list.append(INCLUDE_SYNTAX[simulator.lower()] + dir_path.replace(cl_dir, '$CL_DIR')) @@ -51,7 +60,7 @@ def update_sim_file_list(cl_dir, simulator, generated_file_list): print(line, end='') for generated_line in generated_file_list: print(generated_line, end='\n') - + if IN_GENERATE_BLOCK and "END AUTO-GENERATE" in line: IN_GENERATE_BLOCK = False diff --git a/hdk/common/verif/scripts/log_regression_results.py b/hdk/common/verif/scripts/log_regression_results.py index 57dbe97ce..e5809829e 100755 --- a/hdk/common/verif/scripts/log_regression_results.py +++ b/hdk/common/verif/scripts/log_regression_results.py @@ -1,8 +1,9 @@ #!/usr/bin/env python3 +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2023 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -14,6 +15,7 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= import os @@ -90,7 +92,7 @@ def warn_of_test_count_mismatch(self) -> None: num_test_results: int = len(self.test_results.values()) if num_test_results != len(expected_test_list): found_tests: List[str] = list(self.test_results.keys()) - raise Exception(f""" + print(f""" WARNING: Found {num_test_results} test results in 'sim' directory, but found {len(expected_test_list)} in {self.makefile_testlist_path}. EXPECTED: {expected_test_list} diff --git a/hdk/common/verif/tb/filelists/cl_verif_files.vh b/hdk/common/verif/tb/filelists/cl_verif_files.vh index 9f4616bd6..1eeac7f2f 100644 --- a/hdk/common/verif/tb/filelists/cl_verif_files.vh +++ b/hdk/common/verif/tb/filelists/cl_verif_files.vh @@ -1,7 +1,7 @@ -//------------------------------------------------------------------------------ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -13,7 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. -//------------------------------------------------------------------------------ +// ============================================================================ + // File: cl_verif_files.vh // File that includes all of the CL common testbench sources. @@ -33,4 +34,3 @@ `include "verif/tb/sv/tb.sv" `endif//__CL_VERIF_FILES_VH__ - diff --git a/hdk/common/verif/tb/filelists/tb.questa.f b/hdk/common/verif/tb/filelists/tb.questa.f index 2856c6933..be93482e8 100644 --- a/hdk/common/verif/tb/filelists/tb.questa.f +++ b/hdk/common/verif/tb/filelists/tb.questa.f @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2023 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= + +define+QUESTA_SIM +define+CARD_1=card diff --git a/hdk/common/verif/tb/filelists/tb.vcs.f b/hdk/common/verif/tb/filelists/tb.vcs.f index 3c09ec1d1..dd9f598ba 100644 --- a/hdk/common/verif/tb/filelists/tb.vcs.f +++ b/hdk/common/verif/tb/filelists/tb.vcs.f @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2023 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= + +define+VCS_SIM +define+CARD_1=card diff --git a/hdk/common/verif/tb/filelists/tb.xsim.f b/hdk/common/verif/tb/filelists/tb.xsim.f index 72f0ef27f..3bc30764b 100644 --- a/hdk/common/verif/tb/filelists/tb.xsim.f +++ b/hdk/common/verif/tb/filelists/tb.xsim.f @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2023 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= + -define VIVADO_SIM -define CARD_1=card diff --git a/hdk/common/verif/tb/scripts/Makefile b/hdk/common/verif/tb/scripts/Makefile index 548a15236..3252237f8 100644 --- a/hdk/common/verif/tb/scripts/Makefile +++ b/hdk/common/verif/tb/scripts/Makefile @@ -1,7 +1,7 @@ -#------------------------------------------------------------------------------- +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -13,7 +13,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. -#------------------------------------------------------------------------------- +# ============================================================================= + include $(HDK_COMMON_DIR)/verif/tb/scripts/Makefile.ip_gen models: $(HDK_COMMON_DIR)/verif/scripts/.done diff --git a/hdk/common/verif/tb/scripts/Makefile.common.inc b/hdk/common/verif/tb/scripts/Makefile.common.inc index e1e920fa2..9c9fc0397 100644 --- a/hdk/common/verif/tb/scripts/Makefile.common.inc +++ b/hdk/common/verif/tb/scripts/Makefile.common.inc @@ -1,7 +1,7 @@ -#------------------------------------------------------------------------------- +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -13,9 +13,10 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. -#------------------------------------------------------------------------------- +# ============================================================================= -all: change_simulated_dimm_size make_sim_dir compile run + +all: make_sim_dir compile run define \n @@ -39,9 +40,7 @@ help: ## Display this help $(info $(\t)QUESTA - Set this to use the Modelsim Questa simulator) $(info ) $(info SH_DDR Configuration: "make USE_64GB_DDR_DIMM=1") - $(info $(\t)USE_32GB_DDR_DIMM (DEFAULT) - Set this to use a 32GB DDR DIMM for simulations) - $(info $(\t)USE_64GB_DDR_DIMM - Set this to use a 64GB DDR DIMM for simulations) - $(info $(\t)USE_AP_32GB_DDR_DIMM - Set this to use a 32GB DDR DIMM with user-controlled Auto Precharge for simulations) + $(info $(\t)USE_64GB_DDR_DIMM (DEFAULT) - Set this to use a 64GB DDR DIMM for simulations) $(info $(\t)USE_AP_64GB_DDR_DIMM - Set this to use a 64GB DDR DIMM with user-controlled Auto Precharge for simulations) $(info $(\n)) @@ -89,28 +88,12 @@ PLUSARGS += +plusarg_save +timeout=1ms DDR4_RDIMM_WRAPPER = $(HDK_COMMON_DIR)/verif/models/ddr4_rdimm_wrapper/ddr4_rdimm_wrapper.sv DIMM_REPLACEMENT = "NONE" -ifeq ($(USE_64GB_DDR_DIMM), 1) - DEFAULT_DEFINES += $(call define, USE_64GB_DDR_DIMM=1) - DIMM_REPLACEMENT = sed -i s/_8G/_16G/g $(DDR4_RDIMM_WRAPPER) +ifeq ($(USE_AP_64GB_DDR_DIMM), 1) + DEFAULT_DEFINES += $(call define, USE_AP_64GB_DDR_DIMM=1) else - ifeq ($(USE_AP_64GB_DDR_DIMM), 1) - DEFAULT_DEFINES += $(call define, USE_AP_64GB_DDR_DIMM=1) - DIMM_REPLACEMENT = sed -i s/_8G/_16G/g $(DDR4_RDIMM_WRAPPER) - else - ifeq ($(USE_AP_32GB_DDR_DIMM), 1) - DEFAULT_DEFINES += $(call define, USE_AP_32GB_DDR_DIMM=1) - DIMM_REPLACEMENT = sed -i s/_16G/_8G/g $(DDR4_RDIMM_WRAPPER) - else - DEFAULT_DEFINES += $(call define, USE_32GB_DDR_DIMM=1) - DIMM_REPLACEMENT = sed -i s/_16G/_8G/g $(DDR4_RDIMM_WRAPPER) - endif - endif + DEFAULT_DEFINES += $(call define, USE_64GB_DDR_DIMM=1) endif -change_simulated_dimm_size: - $(DIMM_REPLACEMENT) - echo "Updating simulated DIMM configuration: $(DIMM_REPLACEMENT)" - # Simulation variables and directory name changes ifeq ($(C_TEST),test_null) diff --git a/hdk/common/verif/tb/scripts/Makefile.header.inc b/hdk/common/verif/tb/scripts/Makefile.header.inc index fa7c1f7c2..f08622765 100644 --- a/hdk/common/verif/tb/scripts/Makefile.header.inc +++ b/hdk/common/verif/tb/scripts/Makefile.header.inc @@ -1,3 +1,21 @@ +# ============================================================================= +# Amazon FPGA Hardware Development Kit +# +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + + ifndef VIVADO_TOOL_VERSION $(error Environment variable VIVADO_TOOL_VERSION not set. Please source hdk_setup.sh) else diff --git a/hdk/common/verif/tb/scripts/Makefile.ip_gen b/hdk/common/verif/tb/scripts/Makefile.ip_gen index 1579f4830..d6eba4a3b 100644 --- a/hdk/common/verif/tb/scripts/Makefile.ip_gen +++ b/hdk/common/verif/tb/scripts/Makefile.ip_gen @@ -1,7 +1,7 @@ -#------------------------------------------------------------------------------- +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -13,7 +13,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. -#------------------------------------------------------------------------------- +# ============================================================================= + # # Command wrapper API source diff --git a/hdk/common/verif/tb/scripts/Makefile.questa.inc b/hdk/common/verif/tb/scripts/Makefile.questa.inc index 263a0bada..081e33036 100644 --- a/hdk/common/verif/tb/scripts/Makefile.questa.inc +++ b/hdk/common/verif/tb/scripts/Makefile.questa.inc @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2022 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= clean: diff --git a/hdk/common/verif/tb/scripts/Makefile.vcs.inc b/hdk/common/verif/tb/scripts/Makefile.vcs.inc index 7111238a9..f99cb0df9 100644 --- a/hdk/common/verif/tb/scripts/Makefile.vcs.inc +++ b/hdk/common/verif/tb/scripts/Makefile.vcs.inc @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= clean: @@ -47,4 +49,3 @@ ifeq ($(TEST),test_null) else cd $(SIM_DIR) && ./simv -l $(TEST).log $(PLUSARGS) +ntb_random_seed_automatic +vpdfile+$(TEST).vpd | $(FILTER_OUT_HBM_META_INJECTIONS) endif - diff --git a/hdk/common/verif/tb/scripts/Makefile.xsim.inc b/hdk/common/verif/tb/scripts/Makefile.xsim.inc index c6a08d224..43ccb6780 100644 --- a/hdk/common/verif/tb/scripts/Makefile.xsim.inc +++ b/hdk/common/verif/tb/scripts/Makefile.xsim.inc @@ -1,6 +1,7 @@ +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -12,6 +13,7 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. +# ============================================================================= clean: diff --git a/hdk/common/verif/tb/scripts/simapi.sh b/hdk/common/verif/tb/scripts/simapi.sh index 7b32515ea..c651f4a9e 100755 --- a/hdk/common/verif/tb/scripts/simapi.sh +++ b/hdk/common/verif/tb/scripts/simapi.sh @@ -1,8 +1,9 @@ #!/bin/bash -#------------------------------------------------------------------------------- + +# ============================================================================= # Amazon FPGA Hardware Development Kit # -# Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. # # Licensed under the Amazon Software License (the "License"). You may not use # this file except in compliance with the License. A copy of the License is @@ -14,7 +15,8 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. -#------------------------------------------------------------------------------- +# ============================================================================= + if [ ! -z "$SIMSCR_DEBUG" ] then @@ -136,4 +138,3 @@ function post_ip_gen () { . $dir/post_gen.sh rm -f $dir/post_gen.sh } # post_ip_gen - diff --git a/hdk/common/verif/tb/sv/dma_classes.sv b/hdk/common/verif/tb/sv/dma_classes.sv index e69a60b8a..66fc9144d 100644 --- a/hdk/common/verif/tb/sv/dma_classes.sv +++ b/hdk/common/verif/tb/sv/dma_classes.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + // This has DMA helper classes //-------------------------------------- @@ -1347,4 +1350,3 @@ task post_c2h_desc_thread(input int max_num_desc=64); endtask endclass - diff --git a/hdk/common/verif/tb/sv/tb.sv b/hdk/common/verif/tb/sv/tb.sv index 277fdac69..f66e07ba4 100644 --- a/hdk/common/verif/tb/sv/tb.sv +++ b/hdk/common/verif/tb/sv/tb.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,6 +13,8 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + module tb(); import "DPI-C" function string getenv(input string env_name); diff --git a/hdk/common/verif/tb/sv/tb_type_defines_pkg.sv b/hdk/common/verif/tb/sv/tb_type_defines_pkg.sv index 24827a1bb..fb71ad707 100644 --- a/hdk/common/verif/tb/sv/tb_type_defines_pkg.sv +++ b/hdk/common/verif/tb/sv/tb_type_defines_pkg.sv @@ -1,6 +1,7 @@ +// ============================================================================ // Amazon FPGA Hardware Development Kit // -// Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. +// Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. // // Licensed under the Amazon Software License (the "License"). You may not use // this file except in compliance with the License. A copy of the License is @@ -12,31 +13,34 @@ // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or // implied. See the License for the specific language governing permissions and // limitations under the License. +// ============================================================================ + + `define MAXWAITS 100000 package tb_type_defines_pkg; // clk_main_a0 clk_extra_a1 clk_extra_a2 clk_extra_a3 // Recipe A0 (Default) 125 62.5 187.5 250 // Recipe A1 250 125 375 500 // Recipe A2 15.625 15.625 125 62.5 -// Recipe A3 62.5 31.25 250 125 -// Recipe A4 225 112.5 337.5 450 -// Recipe A5 200 100 300 400 - -// clk_extra_b0 clk_extra_b1 -// Recipe B0 (Default) 250 125 -// Recipe B1 125 62.5 +// Recipe A3 62.5 31.25 250 125 +// Recipe A4 225 112.5 337.5 450 +// Recipe A5 200 100 300 400 + +// clk_extra_b0 clk_extra_b1 +// Recipe B0 (Default) 250 125 +// Recipe B1 125 62.5 // Recipe B2 450 225 // Recipe B3 250 62.5 // Recipe B4 300 75 // Recipe B5 400 100 // Recipe B6 350 87.5 - -// clk_extra_c0 clk_extra_c1 -// Recipe C0 (Default) 300 400 -// Recipe C1 150 200 + +// clk_extra_c0 clk_extra_c1 +// Recipe C0 (Default) 300 400 +// Recipe C1 150 200 // Recipe C2 75 100 // Recipe C3 200 266.67 - + virtual class ClockRecipe; typedef enum integer {A0=0, A1=1, A2=2, A3=3, A4=4, A5=5} A_RECIPE; typedef enum integer {B0=0, B1=1, B2=2, B3=3, B4=4, B5=5, B6=6} B_RECIPE; @@ -46,9 +50,9 @@ package tb_type_defines_pkg; virtual class DataSize; typedef enum integer {UINT8=0, UINT16=1, UINT32=2, UINT64=3, UINT128=4, UINT256=5, UINT512=6} DATA_SIZE; endclass // DataSize - + virtual class AxiPort; typedef enum integer {PORT_DMA_PCIS=0, PORT_SDA=1, PORT_OCL=2, PORT_BAR1=3} AXI_PORT; endclass // AxiPort - + endpackage diff --git a/hdk/docs/AWS_CLK_GEN_spec.md b/hdk/docs/AWS_CLK_GEN_spec.md index 059a5c380..b8aad494a 100644 --- a/hdk/docs/AWS_CLK_GEN_spec.md +++ b/hdk/docs/AWS_CLK_GEN_spec.md @@ -1,8 +1,8 @@ -# AWS_CLK_GEN - CL Clock Generator Block +# AWS_CLK_GEN - CL Clock Generator ## Table of Contents -- [AWS\_CLK\_GEN - CL Clock Generator Block](#aws_clk_gen---cl-clock-generator-block) +- [AWS\_CLK\_GEN - CL Clock Generator](#aws_clk_gen---cl-clock-generator) - [Table of Contents](#table-of-contents) - [Introduction](#introduction) - [Architecture Overview](#architecture-overview) @@ -17,13 +17,13 @@ F1 Shell provides eight clocks to the CL and supports multiple [clock recipes](https://github.com/aws/aws-fpga/blob/master/hdk/docs/clock_recipes.csv) to choose from at the time of CL builds. It also allows to scale clock frequencies during runtime (or after AFI/bitstream is loaded into FPGA) using [dynamic_clock_config](https://github.com/aws/aws-fpga/blob/master/hdk/docs/dynamic_clock_config.md). While this architecture provides multiple clock choices for customer designs, it locks up the global clock routing resources in the CL region. This can pose limitations for customers who do not require all the clocks provided from Shell to the CL. -Therefore, F2 Shell provides only two clocks - `clk_main_a0` and `clk_hbm_ref` - to the CL resulting in efficient use of global routing resources. The `clk_main_a0` is currently a fixed frequency 250MHz clock (:exclamation: multiple clock recipes support and dynamic scaling of frequency as F1 using the SW APIs are coming soon). The `clk_hbm_ref` is a fixed frequency 100MHz clock which can be used by customer as a reference clock for their MMCMs. This scheme provides flexibility for customers to devise their own clocking mechanisms with desired number of clocks. +Therefore, F2 Shell provides only two clocks - `clk_main_a0` and `clk_hbm_ref` - to the CL resulting in efficient use of global routing resources. The `clk_main_a0` is currently a fixed frequency 250MHz clock (:exclamation: dynamic scaling of frequency as F1 using the SW APIs will be added in a future release). The `clk_hbm_ref` is a fixed frequency 100MHz clock which can be used by customer as a reference clock for their MMCMs. This scheme provides flexibility for customers to devise their own clocking mechanisms with desired number of clocks. -In order to provide F1’s clock recipes in F2, as well as support Vitis development in F2, AWS offers Clock Generator Block called as AWS_CLK_GEN. AWS_CLK_GEN block provides various clocks to the CL design and supports dynamic frequency scaling. The Vitis XSA for F2 relies on AWS_CLK_GEN IP for all the clocking needs in the design. This document details the Microarchitecture Specifictaion for AWS_CLK_GEN IP. +In order to provide F1’s clock recipes in F2, as well as support Vitis development in F2, AWS offers the Clock Generator (AWS_CLK_GEN) IP. AWS_CLK_GEN provides various clocks to the CL design and supports dynamic frequency scaling. The Vitis XSA for F2 relies on AWS_CLK_GEN for all the clocking needs in the design. This document details the Microarchitecture Specification for AWS_CLK_GEN. -:warning: The AWS_CLK_GEN block instantiation **must** be named to `AWS_CLK_GEN` and located in the CL top module. +:warning: The AWS_CLK_GEN instantiation **must** be named to `AWS_CLK_GEN` and located in the CL top module. -:warning: The AWS_CLK_GEN block is optional for CL designs that do not require same clocking scheme as F1. This block is not required if the CL designs use only `clk_main_a0` and/or `clk_hbm_ref`. +:warning: The AWS_CLK_GEN is optional for CL designs that do not require same clocking scheme as F1. This block is not required if the CL designs use only `clk_main_a0` and/or `clk_hbm_ref`. ## Architecture Overview @@ -35,7 +35,7 @@ Figure 1 below shows an overview of the AWS_CLK_GEN IP. It primarily consists of 3. AXI-Lite address decoder. -4. AXI-Lite clock convertor. +4. AXI-Lite clock converter. 5. AXI-Lite interface to connect to the AWS Shell or user defined address space. @@ -43,9 +43,9 @@ Figure 1 below shows an overview of the AWS_CLK_GEN IP. It primarily consists of ## Clock and Reset -The AWS_CLK_GEN block requires following primary clocks and resets as inputs: +The AWS_CLK_GEN IP requires following primary clocks and resets as inputs: -1. clk_hbm_ref : This is fixed frequency 100MHz clock from the Shell. This is used as primary clock for the entire AWS_CLK_GEN IP block including the MMCMs and AWS_REGS. +1. clk_hbm_ref : This is fixed frequency 100MHz clock from the Shell. This is used as primary clock for the entire IP block including the MMCMs and AWS_REGS. 2. clk_main_a0 : This is interface clock from Shell whose frequency is scaled by the Shell but maxes out at 250MHz. 3. rst_main_n : Active low reset from Shell. @@ -53,12 +53,12 @@ The AWS_CLK_GEN block requires following primary clocks and resets as inputs: | **Port Name** | **Direction** | **Description** | |--------------------|------------------------------|-----------------------------------------------------------------------------------------------------------------------------------| -| i_clk_hbm_ref | input | HBM ref clock from Shell. Fixed Frequency of 100MHz. | -| i_clk_main_a0 | input | clk_main_a0 from Shell | -| i_rst_main_n | input | rst_main_n from Shell sync'ed to clk_main_a0 from Shell | -| s_sh_cl_cctrl_axil | AXI-L Consumer (s) interface | AXI-Lite interface to access address space of the IP. Recommend connecting this interface to AXI-Lite on PF1-BAR4 from the Shell. | -| clk_hbm_ref | output | pass through of input clk_hbm_ref from Shell. | -| clk_main_a0 | output | pass through of input clk_main_a0 from Shell. | +| i_clk_hbm_ref | input | HBM ref clock from the Shell. Fixed frequency of 100MHz. | +| i_clk_main_a0 | input | clk_main_a0 from the Shell | +| i_rst_main_n | input | rst_main_n from Shell sync'ed to clk_main_a0 | +| s_sh_cl_cctrl_axil | AXI-L Consumer interface | AXI-Lite interface to access address space of the IP. Recommend connecting this interface to AXI-Lite on PF1-BAR4 from the Shell. | +| clk_hbm_ref | output | Pass-through of input clk_hbm_ref from the Shell. | +| clk_main_a0 | output | Pass-through of input clk_main_a0 from the Shell. | | clk_extra_a1 | output | Max frequency = 125 MHz | | clk_extra_a2 | output | Max frequency = 375 MHz | | clk_extra_a3 | output | Max frequency = 500 MHz | @@ -92,30 +92,30 @@ The AXI-Lite address space is decoded as shown in the table below: **NOTES**: -1. Refer to the clkgen CLIs in [FPGA Management Tools](./../../sdk/userspace/fpga_mgmt_tools/README.md) for setting the output clock frequency of AWS_CLK_GEN IP. +1. Refer to the `_clkgen` CLIs in [FPGA Management Tools](./../../sdk/userspace/fpga_mgmt_tools/README.md) for setting the output clock frequencies of AWS_CLK_GEN IP. 2. Write access to undefined address space is ignored. Reading from undefined address space returns 0xDEAD_DEC0. Reading from undefined address space within MMCM results in MMCM’s default behavior. AWS_CLK_GEN IP does not have any protection against illegal use of MMCMs. User discretion is recommended regarding such accesses. ## Register Definitions -Following registers are housed inside AWS_CLK_REGS block and are accessible from the AXIL interface from base address = BASE_REG as described in [Address Space](#ancAddressSpace) +Following registers are housed inside AWS_CLK_REGS component and are accessible from the AXIL interface from base address = `BASE_REG` as described in [Address Space](#ancAddressSpace) -| **Address offset** | **Register Name** | **Bits** | **Access** | **Default Value** | **Description** | +| **Address Offset** | **Register Name** | **Bits** | **Access** | **Default Value** | **Description** | |--------------------|-------------------|----------|------------|-------------------|-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| -| 0x00 | ID_REG | 31:0 | RO | 0x9048_1D0F | 32 bit value to uniquely identify AWS_CLK_GEN IP | +| 0x00 | ID_REG | 31:0 | RO | 0x9048_1D0F | 32-bit value to uniquely identify the AWS_CLK_GEN IP | | 0x04 | VER_REG | 31:0 | RO | 0x0201_0000 | Version Register | | 0x08 | BUILD_REG | 31:0 | RO | 0x0923_2223 | build timestamp in 0xMM_DD_YY_HH format | | | | | | | | | 0x0C | CLKS_AVAIL_REG | 31:9 | RO | 0x0 | Reserved | -| | | 8 | RO | 0x1 | 1 = clk_hbm_axi available \| 0 = clock unavilable | -| | | 7 | RO | 0x1 | 1 = clk_extra_c1 available \| 0 = clock unavilable | -| | | 6 | RO | 0x1 | 1 = clk_extra_c0 available \| 0 = clock unavilable | -| | | 5 | RO | 0x1 | 1 = clk_extra_b1 available \| 0 = clock unavilable | -| | | 4 | RO | 0x1 | 1 = clk_extra_b0 available \| 0 = clock unavilable | -| | | 3 | RO | 0x1 | 1 = clk_extra_a3 available \| 0 = clock unavilable | -| | | 2 | RO | 0x1 | 1 = clk_extra_a2 available \| 0 = clock unavilable | -| | | 1 | RO | 0x1 | 1 = clk_extra_a1 available \| 0 = clock unavilable | -| | | 0 | RO | 0x1 | 1 = clk_main_a0 available \| 0 = clock unavilable | +| | | 8 | RO | 0x1 | 1 = clk_hbm_axi available \| 0 = clock unavailable | +| | | 7 | RO | 0x1 | 1 = clk_extra_c1 available \| 0 = clock unavailable | +| | | 6 | RO | 0x1 | 1 = clk_extra_c0 available \| 0 = clock unavailable | +| | | 5 | RO | 0x1 | 1 = clk_extra_b1 available \| 0 = clock unavailable | +| | | 4 | RO | 0x1 | 1 = clk_extra_b0 available \| 0 = clock unavailable | +| | | 3 | RO | 0x1 | 1 = clk_extra_a3 available \| 0 = clock unavailable | +| | | 2 | RO | 0x1 | 1 = clk_extra_a2 available \| 0 = clock unavailable | +| | | 1 | RO | 0x1 | 1 = clk_extra_a1 available \| 0 = clock unavailable | +| | | 0 | RO | 0x1 | 1 = clk_main_a0 available \| 0 = clock unavailable | | | | | | | | | 0x10 | G_RST_REG | 31:0 | RW | 0x0 | Write 0xFFFF_FFFF to globally reset AWS_CLK_GEN IP. Following blocks are affected: - Assert reset to all MMCMs - Assert reset to SYS_RST and its output to CL Write 0x0000_0000 to de-assert global resets | | | | | | | | @@ -146,7 +146,7 @@ Following registers are housed inside AWS_CLK_REGS block and are accessible from | | | 1 | RO | 0x0 | Reserved | | | | 0 | RO | 0x0 | 1 = MMCM_BASE_A locked | -*NOTE*: Write access to undefined address space is ignored. Reading from undefined address space returns 0xDEAD_DEC0. +**NOTE**: Write access to undefined address space is ignored. Reading from undefined address space returns `0xDEAD_DEC0`. ## Clock Recipes User Guide diff --git a/hdk/docs/AWS_Shell_ERRATA.md b/hdk/docs/AWS_Shell_ERRATA.md index 21f509a40..1821e0084 100644 --- a/hdk/docs/AWS_Shell_ERRATA.md +++ b/hdk/docs/AWS_Shell_ERRATA.md @@ -17,7 +17,6 @@ ## Unsupported Features -- End-to-End virtual ethernet example with live traffic currently not supported in F2 - HBM metrics not yet supported ## Known Bugs/Issues diff --git a/hdk/docs/AWS_Shell_Interface_Specification.md b/hdk/docs/AWS_Shell_Interface_Specification.md index 8f5dacd87..6b6fc26ff 100644 --- a/hdk/docs/AWS_Shell_Interface_Specification.md +++ b/hdk/docs/AWS_Shell_Interface_Specification.md @@ -16,19 +16,19 @@ - [DDR4 AXI](#ddr4-axi) - [DMA](#dma) - [Interfaces between Shell and CL](#interfaces-between-shell-and-cl) - - [CL/Shell AXI Interfaces (AXI-4 and AXI-Lite)](#clshell-axi-interfaces-axi-4-and-axi-lite) + - [CL/Shell AXI Interfaces](#clshell-axi-interfaces) - [Clocks and Reset](#clocks-and-reset) - [Clocks](#clocks) - [Reset](#reset) - - [PCIS Interface -- AXI-4 for Inbound PCIe Transactions (Shell is Requester, CL is Completer, 512-bit)](#pcis-interface----axi-4-for-inbound-pcie-transactions-shell-is-requester-cl-is-completer-512-bit) + - [PCIS Interface](#pcis-interface) - [PCIS Interface Timeout Details](#pcis-interface-timeout-details) - - [PCIM interface -- AXI-4 for Outbound PCIe Transactions (CL is Requester, Shell is Completer, 512-bit)](#pcim-interface----axi-4-for-outbound-pcie-transactions-cl-is-requester-shell-is-completer-512-bit) + - [PCIM interface](#pcim-interface) - [Outbound PCIe AXI-4 Interface Restrictions](#outbound-pcie-axi-4-interface-restrictions) - [Byte Enable Rules](#byte-enable-rules) - [AXI4 Error Handling for CL outbound Transactions](#axi4-error-handling-for-cl-outbound-transactions) - - [AXI-Lite Interfaces for Register Access -- (SDA, OCL)](#axi-lite-interfaces-for-register-access----sda-ocl) - - [AXI Completer (AXI-Lite/PCIS) CL Error Reporting](#axi-completer-axi-litepcis-cl-error-reporting) - - [Accessing Aligned/Unaligned Addresses from PCIe (Shell is Requester, CL is Completer)](#accessing-alignedunaligned-addresses-from-pcie-shell-is-requester-cl-is-completer) + - [SDA/OCL AXI-Lite Interfaces for Register Access](#sdaocl-axi-lite-interfaces-for-register-access) + - [CL AXI Completer Error Reporting](#cl-axi-completer-error-reporting) + - [Accessing Aligned/Unaligned Addresses from PCIe](#accessing-alignedunaligned-addresses-from-pcie) - [Interrupts](#interrupts) - [HBM Monitor Interface](#hbm-monitor-interface) - [Miscellaneous Signals](#miscellaneous-signals) @@ -88,8 +88,8 @@ The following diagram and table summarize the various interfaces between the She | OCL | The OCL Interface is an AXI-Lite interface associated with AppPF and BAR0. Please refer to the [AXI-Lite Interfaces](#axi-lite-interfaces-for-register-access----sda-ocl) for more information. | | Miscellaneous | There are various generic signals, such as ID's, status, counters, etc., between the Shell and CL that are described in the [Miscellaneous Signals](#miscellaneous-signals) section. | | SDA | The SDA Interface is an AXI-Lite interface associated with MgmtPF and BAR4. Please refer to the [AXI-Lite Interfaces](#axi-lite-interfaces-for-register-access----sda-ocl) for more information. | -| HBM MON APB | The HBM monitor interfaces. Customers using HBM IP are required to connect these interfacse to the HBM IP. Refer to the [HBM monitor interface](#hbm-monitor-interface) for more information| -| DDR4 Stats | This is the control interface from the Shell to the DDR4 Controller in the CL. Shell uses this interface to calibrate the DDR core. Refer to the [DDR4 DRAM](#ddr4-dram) section for more information. Refer to [HBM Monitor Interface](#hbm-monitor-interface) section for more information. | +| HBM MON APB | The HBM monitor interfaces. Customers using HBM IP are required to connect these interfaces to the HBM IP. Refer to the [HBM monitor interface](#hbm-monitor-interface) for more information.| +| DDR4 Stats | This is the control interface from the Shell to the DDR4 Controller in the CL. Shell uses this interface to calibrate the DDR core. Refer to the [DDR4 DRAM](#ddr4-dram) section for more information.| | Interrupts | There are 16 user interrupts available. Refer to the [Interrupts](#interrupts) section for more information. | ## External FPGA Interfaces @@ -146,9 +146,9 @@ The Developer can write drivers for the AppPF or leverage the reference driver p The PCIe interface connecting the FPGA to the instance is in the Shell, and the CL can access it through two AXI-4 interfaces: -- [PCI Completer (PCIS)](#pcis-interface----axi-4-for-inbound-pcie-transactions-shell-is-requester-cl-is-completer-512-bit) +- [PCI Completer (PCIS)](#pcis-interface) -- [PCI Requester (PCIM)](#pcim-interface----axi-4-for-outbound-pcie-transactions-cl-is-requester-shell-is-completer-512-bit) +- [PCI Requester (PCIM)](#pcim-interface) ### DDR4 DRAM @@ -179,9 +179,9 @@ There is an integrated DMA controller inside the XDMA Shell (Xilinx DMA, not sup ## Interfaces between Shell and CL -### CL/Shell AXI Interfaces (AXI-4 and AXI-Lite) +### CL/Shell AXI Interfaces -All interfaces use the AXI-4 or AXI-Lite protocol. The AXI-L buses are for register access use cases, and can access lower speed control interfaces that use the AXI-Lite protocol. +All AXI interfaces use the AXI-4 or AXI-Lite protocol. The AXI-L buses are for register access use cases, and can access lower speed control interfaces that use the AXI-Lite protocol. For bulk data transfer, wide AXI-4 buses are used. AXI-4 on the CL/Shell interfaces have the following restrictions: @@ -211,23 +211,22 @@ The Shell provides 250MHz `clk_main_a0` and 100MHz `hbm_ref_clk` from shell-to-C Please note that the extensive list of clocks and resets, as compared to F1 shell, are removed from Shell-CL interface. This improves overall routability for the CL designs that do not require all those multiple clocks from the Shell. However, AWS offers [AWS_CLK_GEN](./AWS_CLK_GEN_spec.md) IP that supports multiple clocks, resets and clock recipes similar to F1. The AWS_CLK_GEN IP can be optionally instantiated in the CL for an easier migration of designs from F1 involving multiple clocks. [CL_MEM_PERF](./../cl/examples/cl_mem_perf/design/cl_mem_perf.sv) demonstrates integration of [AWS_CLK_GEN IP](../common/lib/aws_clk_gen.sv) into CL design. -Please refer to [Clock_Recipes_User_Guide.md](./Clock_Recipes_User_Guide.md) for details on supported clock recipes in F2, dynamic clock reconfiguration and specifying clock recipes during the build time. +Please refer to the [Clock_Recipes_User_Guide.md](./Clock_Recipes_User_Guide.md) for details on supported clock recipes in F2, dynamic clock reconfiguration and specifying clock recipes during the build time. -Similar to F1, the `clk_main_a0` in F2 also supports multiple clock recipes and the frequency can be scaled using SW APIs at the time of AFI loads. +Similar to F1, the `clk_main_a0` in F2 also supports multiple clock recipes and the frequency can be scaled using SW APIs at the time of AFI loads (this feature is currently not available and will be added in a future +release). #### Reset The shell provides an active-low reset signal synchronous to clk_main_a0: rst_main_n. This is an active low reset signal, and combines the board reset and PCIe link-level reset conditions. -### PCIS Interface -- AXI-4 for Inbound PCIe Transactions (Shell is Requester, CL is Completer, 512-bit) +### PCIS Interface -This AXI-4 bus is used for: +This an 512-bit wide AXI-4 interface for Inbound PCIe Transactions (Shell is Requester, CL is Completer). It is used for: - PCIe transactions initiated by the instance and targeting AppPF BAR4 (PCIS) - DMA transactions (if enabled) (XDMA) -It is a 512-bit wide AXI-4 interface. - A read or write request on this AXI-4 bus that is not acknowledged by the CL within a certain time window, will be internally terminated by the Shell. If the time-out error happens on a read, the Shell will return `0xFFFFFFFF` data back to the instance. This error is reported through the Management PF and can be retrieved by the AFI Management Tools metric reporting APIs. The AXI ID can be used to determine the source of the transaction: @@ -247,15 +246,16 @@ The PCIS interface multiplexes the XDMA requests and PCIS requests. Each type o Transactions on the PCIS interface must complete before the associated timeout time or the SH will timeout the transactions and complete the transactions on behalf of the CL (BVALID/RVALID). Each "issued" transaction has an independent timeout counter. For example if 4 transactions are issued from the PCIS interface "simultaneously" (i.e. back-to-back cycles), then all 4 must complete within 8us. A transaction is considered "issued" when the AxVALID is asserted for the transaction by the Timeout Detection block. AxREADY does not have to be asserted for the transaction to be considered "issued". Note there is a 16 deep clock crossing FIFO between the Timeout Detection block and the CL logic. So if the CL is asserting backpressure (de-asserting AxVALID) there can still be 16 transactions issued by the Timeout Detection block. The SH supports a maximum of 32 transactions outstanding for each type (read/write). It is advisable for the CL to implement enough buffering for 32 transactions per type so that it is aware of all issued transactions. -Once a transaction is issued, it must fully be completed within the timeout time (Address, Data, Ready). Any transaction that does not completed in time will be terminated by the shell. This means write data will be accepted and thrown away, and default data (0xffffffff) will be returned for reads. +Once a transaction is issued, it must fully be completed within the timeout time (Address, Data, Ready). Any transaction that does not completed in time will be terminated by the shell. This means write data will be accepted and thrown away, and default data `0xFFFFFFFF` will be returned for reads. If a timeout occurs, the Shell will timeout all further transactions in 16ns for a moderation time (4ms). -**WARNING**: If a timeout happens the DMA/PCIS interface may no longer be functional and the AFI/Shell must be re-loaded. This can be done by adding the "-F" option to fpga-load-local-image. +**WARNING**: If a timeout happens, the DMA/PCIS interface may no longer be functional and the AFI/Shell must be re-loaded. This can be done by adding the "-F" option to `fpga-load-local-image`. -### PCIM interface -- AXI-4 for Outbound PCIe Transactions (CL is Requester, Shell is Completer, 512-bit) +### PCIM interface -This is a 512-bit wide AXI-4 interface for the CL to initiate cycles to the PCIe bus. This can be used, for example, to push data from the CL to instance memory, or read from the instance memory. +This is an 512-bit wide AXI-4 interface for Outbound PCIe Transactions (CL is +Requester, Shell is Completer). It is used by the CL to initiate cycles to the PCIe bus, for example, to push data from the CL to instance memory, or read from the instance memory. :warning: **The CL must use physical addresses, and developers must be careful not to use userspace/virtual addresses.** @@ -313,50 +313,51 @@ Transactions on AXI4 interface will be terminated and reported as SLVERR on the :warning: **If a timeout occurs, the PCIM bus will no longer be functional. This can be cleared by clearing/re-loading the AFI.** -### AXI-Lite Interfaces for Register Access -- (SDA, OCL) +### SDA/OCL AXI-Lite Interfaces for Register Access -There are three AXI-L requester interfaces (Shell is requester) that can be used for register access interfaces. Each interface is sourced from a different PCIe PF/BAR. Breaking this into multiple interfaces allows for different software entities to have a control interface into the CL: +There are two AXI-L requester interfaces (Shell is Requester) that can be used for register access interfaces. Each interface is sourced from a different PCIe PF/BAR. Breaking this into multiple interfaces allows for different software entities to have a control interface into the CL: -- SDA AXI-L: Associated with MgmtPF, BAR4. If the developer is using AWS OpenCL runtime Lib (as in SDAccel case), this interface will be used for performance monitors etc. -- OCL AXI-L: Associated with AppPF, BAR0. If the developer is using AWS OpenCL runtime lib(as in SDAccel case), this interface will be used for openCL Kernel access +- OCL AXI-L: Associated with AppPF, BAR0. If the developer is using AWS OpenCL runtime lib(as in SDAccel case), this interface will be used for OpenCL Kernel access -Please refer to [PCI Address map](./AWS_Fpga_Pcie_Memory_Map.md) for a more detailed view of the address map. +- SDA AXI-L: Associated with MgmtPF, BAR4. If the developer is using AWS OpenCL runtime Lib (as in SDAccel case), this interface will be used for performance monitors etc. This interface is also used for accessing the [AWS_CLK_GEN IP](./AWS_CLK_GEN_spec.md) for CL clock management. + +Please refer to [PCI Address Map](./AWS_Fpga_Pcie_Memory_Map.md) for a more detailed view of the address map. -#### AXI Completer (AXI-Lite/PCIS) CL Error Reporting +#### CL AXI Completer Error Reporting -Each AXI (AXI-4/AXI-L) transaction is terminated with a response (BRESP/RRESP). The AXI responses may signal an error such as Completer Error, or Decode Error. PCIe also has error reporting for non-posted requests (Unsupported Requests/Completer Abort). The shell does not propagate the AXI-4 error responses to the PCIe bus. All PCIe cycles are terminated with non-errored responses. The AXI-4 errors are reported through the Management PF and can be retrieved by the AFI Management Tools metric reporting APIs. +Each AXI (AXI-4/AXI-L) transaction is terminated with a response (BRESP/RRESP). The AXI responses may signal an error such as Completer Error, or Decode Error. PCIe also has error reporting for non-posted requests (Unsupported Requests/Completer Abort). The shell does not propagate the AXI-4 error responses to the PCIe bus. All PCIe cycles are terminated with non-error responses. The AXI-4 errors are reported through the Management PF and can be retrieved by the AFI Management Tools metric reporting APIs. -### Accessing Aligned/Unaligned Addresses from PCIe (Shell is Requester, CL is Completer) +### Accessing Aligned/Unaligned Addresses from PCIe -The Shell supports DW aligned and unaligned transfers from PCIe (address is aligned/not aligned to DW-4byte boundary) +The Shell (Requester) supports DW aligned and unaligned transfers from PCIe (address is aligned/unaligned to DW-4byte boundary) -Following are a few examples of how aligned and Unaligned access from PCIe to CL on PCIS interface work: +Following are a few examples of how aligned and unaligned access from PCIe to CL on PCIS interface work: 1) Writing 8 bytes to DW aligned address through PCIe on AXI4 Interface(PCIS 512-bit interface): If the transaction on the PCIe is as follows: - Addr : 0x0000002000000000 - dw_cnt : 2 - first_be : 4’b1111 - last_be : 4’b1111 + - Addr : 0x0000002000000000 + - dw_cnt : 2 + - first_be : 4’b1111 + - last_be : 4’b1111 Then the transaction on the AXI4 interface will have the following AXI attributes: - awaddr 64’h0000_0000_0000_0000 - awlen = 0 - wstrb = 64’h0000_0000_0000_00ff + - awaddr 64’h0000_0000_0000_0000 + - awlen = 0 + - wstrb = 64’h0000_0000_0000_00ff - 2) Writing 8 bytes to DW un-aligned address on AXI4 Interface(PCIS 512-bit interface): + 2) Writing 8 bytes to DW unaligned address on AXI4 Interface(PCIS 512-bit interface): If the transaction on the PCIe is as follows: - Addr : 0x0000002000000001 - dw_cnt : 3 - first_be : 4’b1110 - last_be : 4’b0001 + - Addr : 0x0000002000000001 + - dw_cnt : 3 + - first_be : 4’b1110 + - last_be : 4’b0001 Then the transaction on the AXI4 interface will have the following AXI attributes: - awddr = 64’h0000_0000_0000_0001 - awlen = 0 - wstrb = 64’h0000_0000_0000_01fe + - awaddr = 64’h0000_0000_0000_0001 + - awlen = 0 + - wstrb = 64’h0000_0000_0000_01fe The addresses for the Read transactions will work similar to writes. @@ -364,9 +365,9 @@ The addresses for the Read transactions will work similar to writes. If a transaction from PCIe is initiated on AXI-Lite (SDA/OCL) interfaces with dw_cnt greater than 1, i.e. >32bits, the transaction is split into multiple 32-bit transactions by the Shell. -Following are a few examples of how aligned and Unaligned access from PCIe to CL on SDA/OCL/BAR1 AXI-Lite interfaces work: +Following are a few examples of how aligned and Unaligned access from PCIe to CL on SDA/OCL AXI-Lite interfaces work: -1. Writing 8 bytes to DW aligned address on AXI Lite interface (SDA/OCL/BAR1 32-bit interface): +1. Writing 8 bytes to DW aligned address on AXI Lite interface (SDA/OCL 32-bit interface): If the transaction on the PCIe is as follows: Addr : 0x0000000002000000 @@ -377,31 +378,36 @@ Following are a few examples of how aligned and Unaligned access from PCIe to CL Then the transaction on the AXI-Lite interface will be split and will have the following AXI attributes: Transaction is split into 2 transfers. - 1st transfer awaddr = 32’h0000_0000 - wstrb = 4’hf + 1st transfer + - awaddr = 32’h0000_0000 + - wstrb = 4’hf - 2nd transfer awaddr = 32’h0000_0004 - wstrb = 4’hf + 2nd transfer + - awaddr = 32’h0000_0004 + - wstrb = 4’hf -2. Writing 64 bits to DW un aligned address on AXI Lite interface (SDA/OCL/BAR1 32-bit interface): +1. Writing 64 bits to DW unaligned address on AXI Lite interface (SDA/OCL 32-bit interface): - If the transaction on the PCIe is as follows: - Addr : 0x0000000002000001 - dw_cnt : 3 - first_be : 4’b1110 - last_be : 4’b0001 + If the transaction on the PCIe is as follows: + -Addr : 0x0000000002000001 + -dw_cnt : 3 + -first_be : 4’b1110 + -last_be : 4’b0001 Transaction on AXI-Lite interface will be split and will have the following AXI attributes: Transaction is split into 3 transfers. - 1st transfer awaddr = 32’h0000_0001 - wstrb = 4’he + 1st transfer + - awaddr = 32’h0000_0001 + - wstrb = 4’he - 2nd transfer awaddr = 32’h0000_0004 - wstrb = 4’hf + 2nd transfer + - awaddr = 32’h0000_0004 + - wstrb = 4’hf - 3rd transfer awaddr = 32’h0000_0008 - wstrb = 4’h1 + 3rd transfer + - awaddr = 32’h0000_0008 + - wstrb = 4’h1 The transaction splitting and addresses for the Read transactions will work similar to writes. @@ -424,7 +430,7 @@ When the interfaces are connected to the HBM IP properly, the shell monitors the The active-low `hbm_apb_preset` signal connected to each HBM rack remains at logic-high during power-on and normal operation. This allows the HBM to initialize and communicate with the rest of the CL logic. If an HBM access violation (i.e., an APB transaction to an undefined address space) occurs, the shell will pull the `hbm_apb_preset` signal low to force a reset of the HBM rack. Subsequent usage of this rack is blocked. The customer must reload the AFI to get it recovered from this blocked state. -These steps must be followed to properly conect the monitor interfaces to HBM: +These steps must be followed to properly connect the monitor interfaces to HBM: 1. Expose the HBM monitor I/Os on the HBM IP by running the following Tcl commands in the Vivado IP management project: @@ -434,9 +440,9 @@ These steps must be followed to properly conect the monitor interfaces to HBM: true ``` - **NOTE:** This step can be skipped if the customer uses the `CL_HBM` IP from the [CL examples](./../README.md#cl-examples). This IP has the `MON_APB` interface enabled and is ready to be integrated to a customer design as-is. + **NOTE:** This step can be skipped if the customer uses the `CL_HBM` IP from the [CL examples](./../../hdk/common/ip/cl_ip/). This IP has the `MON_APB` interface enabled and is ready to be integrated to a customer design as-is. -2. Connect the HBM monitor interface from the shell to the HBM IP. The customer can leave the interface floating if the corresponding HBM rack is not used. For example, the `hbm_apb_p_1` signals can be left unconnected if HBM 1 is unused. +2. Connect the HBM monitor interface from the shell to the HBM IP. The customer can leave the interface floating if the corresponding HBM rack is not used. For example, the `hbm_apb_p_1` signals can be left unconnected if HBM rack 1 is unused. 3. All the HBM monitor interfaces are synchronized to the 100MHz `clk_hbm_ref` clock. @@ -529,45 +535,46 @@ It is ideal to place logic that interfaces to the shell in the same SLR as the S - MID SLR: - PCIM - OCL - - BAR1 - SDA - MID/BOTTOM - - HBM Mon APB + - HBM MON APB -Please see [shell_floorplan.md](./shell_floorplan.md) for additional details on Shell-CL interface placements in SMALL_SHELL. +Please see the [Shell Floorplan](./shell_floorplan.md) for additional details on Shell-CL interface placements in SMALL_SHELL. For the interfaces that are in both the MID/BOTTOM the recommendation is to use flops for pipelining, but don’t constrain to an SLR. You can constrain logic to a particular SLR by creating PBLOCKs (one per SLR), and assigning logic to the PBLOCKs (refer to cl_dram_hbm_dma example [small_shell_cl_pnr_user.xdc](../cl/examples/cl_dram_hbm_dma/build/constraints/small_shell_cl_pnr_user.xdc)). Dataflow should be mapped so that SLR crossing is minimized (for example a pipeline should be organized such that successive stages are mostly in the same SLR). -Here’s an example post on the Xilinx forum which points to some documentation related to solving this: - - -There are some good timing closure tips in this methodology doc pointed to by the Xilinx forum post: - +There are some good timing closure tips in this [UltraFast Design Methodology Guide](https://docs.amd.com/r/2024.1-English/ug949-vivado-design-methodology/Introduction) ### Logic Levels You can report all paths that are greater than a certain number of logic levels. This can be used to iterate on timing in synthesis rather than waiting for place and route. For example at 250MHz a general rule of thumb is try to keep logic levels to around 10. The following commands report on all paths that have more than 10 logic levels: -- report_design_analysis -logic_level_distribution -of [get_timing_paths -max_paths 10000 -filter {LOGIC_LEVELS > **10**}] -- foreach gtp [get_timing_paths -max_paths 5000 ?nworst 100 -filter {LOGIC_LEVELS > **10**}] {puts "[get_property STARTPOINT_PIN $gtp] [get_property ENDPOINT_PIN $gtp] [get_property SLACK $gtp] [get_propert LOGIC_LEVELS $gtp]"} +``` Tcl +report_design_analysis -logic_level_distribution -of [get_timing_paths -max_paths 10000 -filter {LOGIC_LEVELS > **10**}] + +foreach gtp [get_timing_paths -max_paths 5000 ?nworst 100 -filter {LOGIC_LEVELS > **10**}] { + puts "[get_property STARTPOINT_PIN $gtp] + [get_property ENDPOINT_PIN $gtp] [get_property SLACK $gtp] + [get_propert LOGIC_LEVELS $gtp]" +``` ### Reset Reset fanout can be minimized in an FPGA. This helps with routing congestion. Flops can be initialized in their declaration and generally do not require resets: ```verilog - logic[3:0] my_flops = 4’ha; + logic[3:0] my_flops = 4'ha; ``` If logic must have a reset, use synchronous resets rather than asynchronous resets: ```verilog always @(posedge clk) - if (reset) - my_flop <= 4’ha; - else - my_flop <= nxt_my_flop; + if (reset) + my_flop <= 4'ha; + else + my_flop <= nxt_my_flop; ``` If there is still significant fanout of reset, it should be replicated and pipelined. For example each major block could have its own pipelined version of reset. @@ -591,4 +598,4 @@ Vivado has some nice analysis capabilities: - physical implementation analysis (placement, routing) - linked timing/schematic/physical views - +Refer to [Vivado Design Suite User Guide](https://docs.amd.com/r/en-US/ug906-vivado-design-analysis/Routing-Analysis) for more information. diff --git a/hdk/docs/Clock_Recipes_User_Guide.md b/hdk/docs/Clock_Recipes_User_Guide.md index 69c1d5851..4c04f62e0 100644 --- a/hdk/docs/Clock_Recipes_User_Guide.md +++ b/hdk/docs/Clock_Recipes_User_Guide.md @@ -5,7 +5,7 @@ - [F2 Clock Recipes User Guide](#f2-clock-recipes-user-guide) - [Table of Content](#table-of-content) - [Introduction](#introduction) - - [F2 Clock Recipe Table](#f2-clock-recipe-table) + - [F2 Clock Recipe Tables](#f2-clock-recipe-tables) - [How to Specify Clock Recipe During Build Time](#how-to-specify-clock-recipe-during-build-time) - [How to Dynamically Configure Clocks during Runtime](#how-to-dynamically-configure-clocks-during-runtime) - [Clock Consideration When Porting CL Designs from F1 into F2](#clock-consideration-when-porting-cl-designs-from-f1-into-f2) @@ -13,26 +13,26 @@ ## Introduction -F2 Shell offers two clocks - `clk_main_a0` and `clk_hbm_ref` to the CL. This is different from F1 Shell, which offers total of 8 clocks from Shell to the CL as described in [F1 Shell Interface Spec](https://github.com/aws/aws-fpga/blob/master/hdk/docs/AWS_Shell_Interface_Specification.md#clocks). Offering fewer clocks from the Shell to CL is beneficial because it does not lock up the routing resources for customers who do not require all the clocks from Shell. +F2 Shell offers two clocks - `clk_main_a0` and `clk_hbm_ref` to the CL. This is different from F1 Shell, which offers total of 8 clocks from Shell to the CL as described in [F1 Shell Interface Spec](https://github.com/aws/aws-fpga/blob/master/hdk/docs/AWS_Shell_Interface_Specification.md#clocks). Offering fewer clocks from the Shell to CL is beneficial because it does not lock up the routing resources for customers who do not require all the clocks from the Shell. The `clk_main_a0` defaults to 250MHz. Dynamic reconfiguration of the frequency for `clk_main_a0` is currently NOT supported. However, this will be supported in future. The `clk_hbm_ref` is a fixed frequency 100MHz clock required for the HBM IP to clock the APB interface. -F2 Developer Kit provides a clocking IP [AWS_CLK_GEN](./AWS_CLK_GEN_spec.md) for customers who desire to have same clocks and clock recipe support as F1. [Table](./Clock_Recipes_User_Guide.md#f2-clock-recipe-table) shows the clock recipes supported in F2. +F2 Developer Kit provides a clocking IP [AWS_CLK_GEN](./AWS_CLK_GEN_spec.md) for customers who desire to have same clocks and clock recipe support as F1. [Table](./Clock_Recipes_User_Guide.md#f2-clock-recipe-table) below shows the clock recipes supported in F2. -## F2 Clock Recipe Table +## F2 Clock Recipe Tables | **Clock Group A** | | | | | | |---------------------------|------------------|------------------|------------------|------------------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | **Recipe Number** | **clk_main_a0** | **clk_extra_a1** | **clk_extra_a2** | **clk_extra_a3** | **Notes** | -| A0 | 250 | 62.5 | 187.5 | 250 | AWS_CLK_GEN is not required in the CL design for clk_main_a0 recipes. clk_extra_a0/a1/a2 clocks require AWS_CLK_GEN block instantiated in CL design. | +| A0 | 250 | 62.5 | 187.5 | 250 | AWS_CLK_GEN is not required in the CL design for clk_main_a0 recipes. clk_extra_a0/a1/a2 clocks require AWS_CLK_GEN IP instantiated in CL design. | | A1 | 250 | 125 | 375 | 500 | | | A2 | 250 | 15.625 | 125 | 62.5 | | | | | | | | | | **Clock Group B** | | | | | | | **Recipe Number** | **clk_extra_b0** | **clk_extra_b1** | | | **Notes** | -| B0 | 250 | 125 | | | clk_extra_b0/b1 require AWS_CLK_GEN block instantiated in the CL design. | +| B0 | 250 | 125 | | | clk_extra_b0/b1 require AWS_CLK_GEN IP instantiated in the CL design. | | B1 | 125 | 62.5 | | | | | B2 | 450 | 225 | | | | | B3 | 250 | 62.5 | | | | @@ -56,7 +56,7 @@ F2 Developer Kit provides a clocking IP [AWS_CLK_GEN](./AWS_CLK_GEN_spec.md) for | | | | | | | | **Reference Clock Group** | | | | | | | **Recipe Number** | **clk_hbm_ref** | | | | **Notes** | -| - | 100 | | | | Fixed frequency 100MHz reference clock from Shell for HBM. | +| - | 100 | | | | Fixed frequency 100MHz reference clock from the Shell for HBM IP. | **NOTE:** `clk_main_a0` supports A0, A1 and A2 clock recipes without requiring AWS_CLK_GEN IP instantiated in the CL design. All other clocks and their respective clock recipes require AWS_CLK_GEN IP instantiated in the CL design and interfaced to the SDA interface from the Shell. [CL_MEM_PERF](./../cl/examples/cl_mem_perf/design/cl_mem_perf.sv) demonstrates how [AWS_CLK_GEN](./../common/lib/aws_clk_gen.sv) is integrated into CL design. @@ -71,9 +71,9 @@ cd $CL_DIR/build/scripts/ ./aws_build_dcp_from_cl.py --cl=cl_mem_perf --clock_recipe_a=A0 --clock_recipe_b=B3 --clock_recipe_c=C3 --clock_recipe_hbm=H4 ``` -When the clock_recipe switch is not explicitly specified, `aws_build_dcp_from_cl.py` defaults to `--clock_recipe_a=A1 --clock_recipe_b=B2 --clock_recipe_c=C0 --clock_recipe_hbm=H2` +When the clock recipe options are not explicitly specified, `aws_build_dcp_from_cl.py` defaults to `--clock_recipe_a=A1 --clock_recipe_b=B2 --clock_recipe_c=C0 --clock_recipe_hbm=H2` -**NOTE:** If AWS_CLK_GEN IP is not instantiated in the CL design, the recipes for AWS_CLK_GEN clocks will be ignored. Users may see CRITICAL WARNING related to missing AWS_CLK_GEN block during builds. +**NOTE:** If AWS_CLK_GEN IP is not instantiated in the CL design, the recipes for AWS_CLK_GEN clocks will be ignored. Users may see CRITICAL WARNING related to missing AWS_CLK_GEN instantiation during builds. ## How to Dynamically Configure Clocks during Runtime @@ -81,7 +81,7 @@ Support for SW API to do clock frequency dynamic configuration is available usin ## Clock Consideration When Porting CL Designs from F1 into F2 -1. The `clk_main_a0` is now fixed at 250MHz. It does not support clock recipes or dynamic frequecny reconfiguration. However, the will be supported in future. +1. The `clk_main_a0` is now fixed at 250MHz. It does not support clock recipes or dynamic frequency reconfiguration. However, they will be supported in future. 2. F1 designs that relied on additional clocks such as `clk_extra_*` will now have two options in F2: diff --git a/hdk/docs/Supported_DDR_Modes.md b/hdk/docs/Supported_DDR_Modes.md index d950a3e01..0a7a253ae 100644 --- a/hdk/docs/Supported_DDR_Modes.md +++ b/hdk/docs/Supported_DDR_Modes.md @@ -1,9 +1,9 @@ # Supported DDR configurations in [sh_ddr.sv](./../common/shell_stable/design/sh_ddr/sh_ddr.stub.sv) -## Table of Content +## Table of Contents - [Supported DDR configurations in sh\_ddr.sv](#supported-ddr-configurations-in-sh_ddrsv) - - [Table of Content](#table-of-content) + - [Table of Contents](#table-of-contents) - [Overview](#overview) - [Required RTL Modifications](#required-rtl-modifications) - [Required Verification Modifications](#required-verification-modifications) @@ -14,7 +14,7 @@ The [sh_ddr.sv](./../common/shell_stable/design/sh_ddr/sh_ddr.stub.sv) now supports following configurations for DDR Controller IPs: - DDR Core for 64 GB DIMM. -- DDR Core for 64 GB DIMM with user-controlled Auto-Precharge mode. This feature allows user designs to issue DDR Auto-Precharge command by asserting `cl_sh_ddr_axi_awuser=1` or `cl_sh_ddr_axi_aruser=1` alongside their corresponding valid control signals. Please refer to [PG150-User Guide](https://www.xilinx.com/content/dam/xilinx/support/documents/ip_documentation/ultrascale_memory_ip/v1_4/pg150-ultrascale-memory-ip.pdf) for details on user-controlled (app_autoprecharge) Auto-Precharge mode. +- DDR Core for 64 GB DIMM with user-controlled Auto-Precharge mode. This feature allows user designs to issue DDR Auto-Precharge command by asserting `cl_sh_ddr_axi_awuser=1` or `cl_sh_ddr_axi_aruser=1` alongside their corresponding valid control signals. Please refer to [PG150-User Guide](https://www.xilinx.com/content/dam/xilinx/support/documents/ip_documentation/ultrascale_memory_ip/v1_4/pg150-ultrascale-memory-ip.pdf) for details on user-controlled (app_auto-precharge) Auto-Precharge mode. - If DDR core is not required in the CL design, then users still have to instantiate `sh_ddr.sv` in top level CL, with parameter tied off to `.DDR_PRESENT(0)`. Failing to do so may result in errors during synthesis/implementation. ## Required RTL Modifications diff --git a/hdk/docs/Virtual_JTAG_XVC.md b/hdk/docs/Virtual_JTAG_XVC.md index 9a023fc0d..eec56ff0a 100644 --- a/hdk/docs/Virtual_JTAG_XVC.md +++ b/hdk/docs/Virtual_JTAG_XVC.md @@ -18,7 +18,7 @@ Amazon EC2 F2 instances offer debugging capabilities through Virtual JTAG. This The Virtual JTAG solution consists of three main elements: -- [A] Debug cores and a debug bridge that must be implemented and connected properly in the CL design. Refer to the [cl_dram_hbm_dma](../cl/examples/cl_dram_hbm_dma) example design for details. +- [A] Debug cores and a debug bridge that must be implemented and connected properly in the CL design. Refer to the [cl_dram_hbm_dma](../cl/examples/cl_dram_hbm_dma/README.md) example design for details. - [B] A Virtual-JTAG service acting as an XVC server that runs on the target F2 instance. - [C] A local or remote Vivado application for interactive debugging. @@ -117,7 +117,7 @@ To begin debugging a CL design, the developer must first install the XVC driver ## Connect to target FPGA via Virtual JTAG -With a XVC server up and running, a Virutal JTAG cable connection to the target FPGA is ready to be built in Vivado. +With a XVC server up and running, a Virtual JTAG cable connection to the target FPGA is ready to be built in Vivado. - Prior to executing Vivado, verify that the `.LTX` probe file from the CL design DCP tarball is saved on the instance. @@ -146,11 +146,11 @@ With a XVC server up and running, a Virutal JTAG cable connection to the target ![vjtag_4](./images/VJTAG_images/vjtag_4.jpg) -- The debug bridge in the target design should be detected and listed in "Hardware Targets". Click "Next" and "Finish" to finish setting up the Virutal JTAG connection. +- The debug bridge in the target design should be detected and listed in "Hardware Targets". Click "Next" and "Finish" to finish setting up the Virtual JTAG connection. ![vjtag_5](./images/VJTAG_images/vjtag_5.jpg) -- All the debug cores embedded in the CL design should be now listed under `debug_bridge_0`. Highlight `debug_bridge_0` and add the CL design `.LTX` probe file to "Probes file" in the "Hardware Device Properties" window. After the probe file gets loaded, the waveform and configuration windows will be avaliable for each debug core in Vivado. The CL design at this point is ready to be debugged. +- All the debug cores embedded in the CL design should be now listed under `debug_bridge_0`. Highlight `debug_bridge_0` and add the CL design `.LTX` probe file to "Probes file" in the "Hardware Device Properties" window. After the probe file gets loaded, the waveform and configuration windows will be available for each debug core in Vivado. The CL design at this point is ready to be debugged. ![vjtag_6](./images/VJTAG_images/vjtag_6.jpg) @@ -184,7 +184,7 @@ The [CL_Debug_Bridge](./../common/ip/cl_ip/cl_ip.srcs/sources_1/ip/cl_debug_brid ); ``` -All debug cores within the Compute Logic (CL) must be connected to the `CL_Debug_Bridge`. These connections can be automatically inserted during the design synthesis process. For an example implementation, please refer to the [synth_cl_dram_hbm_dma.tcl script](./../cl/examples/cl_dram_hbm_dma/build/scripts/synth_cl_dram_hbm_dma.tcl) in the cl_dram_hbm_dma example. +All debug cores within the CL must be connected to the `CL_Debug_Bridge`. These connections can be automatically inserted during the design synthesis process. For an example implementation, please refer to the [synth_cl_dram_hbm_dma.tcl script](./../cl/examples/cl_dram_hbm_dma/build/scripts/synth_cl_dram_hbm_dma.tcl) in the cl_dram_hbm_dma example. ``` bash AWS FPGA: (12:35:47): Connecting debug network @@ -206,7 +206,7 @@ connect_debug_cores: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB) **Q: Do I need full Vivado installation to run Virtual JTAG debug on a F2 instance?** -A: No. If you are utilizing the AWS FPGA developler AMI, you can leverge the built-in Vivado. If you using a different runtime AMI, you can download the standalone Vivado Lab Solutions from [AMD website](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools.html) and use that for free. +A: No. If you are utilizing the AWS FPGA developer AMI, you can leverage the built-in Vivado. If you using a different runtime AMI, you can download the standalone Vivado Lab Solutions from [AMD website](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools.html) and use that for free. **Q: Do I need a Vivado license to use Virtual JTAG and Xilinx VIO/LIA debug capabilities?** diff --git a/release_version.txt b/release_version.txt index aec47f042..e9c9ad360 100644 --- a/release_version.txt +++ b/release_version.txt @@ -1 +1 @@ -RELEASE_VERSION=2.0.0 +RELEASE_VERSION=2.0.1 diff --git a/sdk/apps/virtual-ethernet/doc/SDE_HW_Guide.md b/sdk/apps/virtual-ethernet/doc/SDE_HW_Guide.md index 7217b52d4..7902db7c8 100644 --- a/sdk/apps/virtual-ethernet/doc/SDE_HW_Guide.md +++ b/sdk/apps/virtual-ethernet/doc/SDE_HW_Guide.md @@ -40,16 +40,16 @@ # Overview -The Streaming Data Engine (SDE) provides high-performance packet streaming connectivity between the Custom Logic (CL) and the host application. The SDE provides a streaming interface to the CL and uses the shell's PCIM AXI4 interface to move packets between the CL and the host application. The SDE is a parametrizable, soft IP block that is intended to be instanciated within the CL. Each instance of the SDE provides two AXI streaming compliant interfaces viz. one Card-to-Host (C2H) and one Host-to-Card (H2C) channel. +The Streaming Data Engine (SDE) provides high-performance packet streaming connectivity between the Custom Logic (CL) and the host application. The SDE provides a streaming interface to the CL and uses the shell's PCIM AXI4 interface to move packets between the CL and the host application. The SDE is a parameterizable, soft IP block that is intended to be instantiated within the CL. Each instance of the SDE provides two AXI streaming compliant interfaces viz. one Card-to-Host (C2H) and one Host-to-Card (H2C) channel. # Feature List 1. High Performance PPS for C2H and H2C. 2. 12GB/s Bandwidth per channel for C2H and H2C (4KB packet at 250MHz). 3. AXI Stream compliant on the CL facing side. -4. AXI Stream supports parametrizable data widths 64, 128, 256 and 512 bits (Current version supports 512 bits only). +4. AXI Stream supports parameterizable data widths 64, 128, 256 and 512 bits (Current version supports 512 bits only). 5. AXI4 complaint on the shell facing side. -6. AXI4 supports parametrizable data widths 64, 128, 256 and 512 bits (Current version supports 512 bits only). +6. AXI4 supports parameterizable data widths 64, 128, 256 and 512 bits (Current version supports 512 bits only). 7. User bits on the RX and TX streaming interfaces. 8. Multiple descriptor types (Normal and Compact). 9. Multiple descriptors per packet. @@ -1288,7 +1288,7 @@ Design parameters C2H_ONLY and H2C_ONLY can be used to get what is required and With the current version of the SDE, if more than 1 full duplex channel is needed, multiple SDEs have to be instanced and AXI crossbars have to be used to connect the PCIS and PCIM buses to/from the corresponding SDEs. Similarly, if more than 1 C2H or more than 1 H2C channel is required, multiple SDEs have to be used. ### Q. Is there a maximum number of SDEs that can be instanced in a CL? -There is no theoritecal maximum. There is a practical limitation based on the number of resources in the CL. +There is no theoretical maximum. There is a practical limitation based on the number of resources in the CL. ### Q. What kind of software/Driver is required to use the SDE. A userspace or kernel poll-mode driver is required to use the SDE. @@ -1322,7 +1322,7 @@ The maximum throughput for H2C is 12 GB/s and the maximum throughput for C2h is 4KB is the minimum packet size required for maximum throughput. ### Q. My application uses PCIS and PCIM interfaces for other purposes in the CL. Can I still use the SDE? -Yes, the SDE can still be used. However, appropriate AXI Crossbars/Fabric needs to be used in the CL in order to provide connectivity for PCIS and PCIM buses to the SDE. Additionally, address and ARID/AWIDs should be appropriately configured/parametrized in the software and the SDE respectively. +Yes, the SDE can still be used. However, appropriate AXI Crossbars/Fabric needs to be used in the CL in order to provide connectivity for PCIS and PCIM buses to the SDE. Additionally, address and ARID/AWIDs should be appropriately configured/parameterized in the software and the SDE respectively. ### Q. My accelerator/CL cannot transmit/receive data at 512bits per clock. Can SDE transmit/receive less than 512 bits per clock on the H2C/C2H Streaming Interfaces? The current version of the SDE can only transmit/receive data at 512 bits per clock. The CL developer can use Xilinx AXI-S width converters to achieve width conversion from any bit width to 512 bits. @@ -1339,6 +1339,3 @@ AWS only supports SDE implemented at a maximum of 250MHz. ### Q. Should the SDE be constrained to a single SLR? AWS recommends that the all the logic in the SDE be constrained to a single SLR. Additionally, AWS recommends adding pipelining on the PCIM and PCIS interfaces from the shell leading up to the SDE. - - - diff --git a/sdk/apps/virtual-ethernet/doc/Virtual_Ethernet_Application_Guide.md b/sdk/apps/virtual-ethernet/doc/Virtual_Ethernet_Application_Guide.md index e2e2b986b..070ef0689 100644 --- a/sdk/apps/virtual-ethernet/doc/Virtual_Ethernet_Application_Guide.md +++ b/sdk/apps/virtual-ethernet/doc/Virtual_Ethernet_Application_Guide.md @@ -143,13 +143,13 @@ The number of supported TX and RX descriptors per SPP queue pair is parameterize The SDE may be built with regular or compact descriptor types (see the C2H_DESC_TYPE and H2C_DESC_TYPE in the Design Parameters section [here](./SDE_HW_Guide.md)). The SPP PMD also supports regular or compact descriptor types at compile time via the SPP_USE_COMPACT_DESCS define within spp_defs.h. The default descriptor type for the SDE and SPP is `regular` to support the full 64-bit DMA addressing. If there is a mismatch between the SDE and SPP descriptor type build options, the SPP driver will log an error similar to the following: -Mismatched build options: SDE descriptor type is `regular`, SPP PMD decriptor type is `compact`. +Mismatched build options: SDE descriptor type is `regular`, SPP PMD descriptor type is `compact`. ``` PMD: spp_dev_cap_get(): SDE C2H Desc Info(0x00400000), type=regular, is not supported ``` -Mismatched build options: SDE descriptor type is `compact`, SPP PMD decriptor type is `regular`. +Mismatched build options: SDE descriptor type is `compact`, SPP PMD descriptor type is `regular`. ``` PMD: spp_dev_cap_get(): SDE C2H Desc Info(0x00800001), type=compact, is not supported diff --git a/sdk/userspace/fpga_mgmt_tools/README.md b/sdk/userspace/fpga_mgmt_tools/README.md index ffac1b1d5..4808dfd7e 100644 --- a/sdk/userspace/fpga_mgmt_tools/README.md +++ b/sdk/userspace/fpga_mgmt_tools/README.md @@ -18,7 +18,7 @@ AWS provides the following set of command-line tools for Amazon FPGA Image (AFI) * Starts a Virtual JTAG XVC server, to debug tools like Vivado Lab Edition Hardware Manager to access debug cores inside the AFI. Please refer to [Virtual JTAG userguide](../../../hdk/docs/Virtual_JTAG_XVC.md). * **`fpga-get-virtual-led`** - * Returns a bit-map representating the state (1/0) the Virtual LEDs exposed by the Custom Logic (CL) part of the AFI. + * Returns a bit-map representing the state (1/0) the Virtual LEDs exposed by the Custom Logic (CL) part of the AFI. * **`fpga-get-virtual-dip-switch`** * Returns a bit-map representing the current setting for the Virtual DIP Switches that drives the Custom Logic (CL) part of the AFI. @@ -89,7 +89,7 @@ sudo fpga-describe-local-image-slots -H * The DeviceId is the PCIe Configuration space Device ID, with 0x9048 being the default. -* The DBDF is the common PCIe bus topology representating the Domain:Bus#:Device#:Function#. +* The DBDF is the common PCIe bus topology representing the Domain:Bus#:Device#:Function#. ** NOTE: ** *While each FPGA has more than one PCIe Physical Function, the AFI Management Tools will present the VendorId and DeviceId of the first PF only*. @@ -111,7 +111,7 @@ sudo fpga-describe-local-image -S 0 -H ### Synchronous AFI Load and Clear Operations #### Synchronously Loading an AFI to a Specific FPGA Slot -To load the AFI, use the FPGA slot number and Amazon Global FPGA Image ID parameters (see FAQ for AGFI). In synchronous mode, this command will wait for the AFI to transition to the "loaded" state, perform a PCI device remove and recan in order to expose the unique AFI Vendor and Device Id, and display the final state for the given FPGA slot number. +To load the AFI, use the FPGA slot number and Amazon Global FPGA Image ID parameters (see FAQ for AGFI). In synchronous mode, this command will wait for the AFI to transition to the "loaded" state, perform a PCI device remove and rescan in order to expose the unique AFI Vendor and Device Id, and display the final state for the given FPGA slot number. ```bash sudo fpga-load-local-image -S 0 -I agfi-0fedcba9876543210 -H @@ -126,7 +126,7 @@ sudo fpga-load-local-image -S 0 -I agfi-0fedcba9876543210 -H #### Synchronously Clearing the FPGA Image on Specific Slot -The following command will clear the FPGA image, including internal and external memories. In synchronous mode, this command will wait for the AFI to transition to the "cleared" state, perform a PCI device remove and recan in order to expose the default AFI Vendor and Device Id, and display the final state for the given FPGA slot number. +The following command will clear the FPGA image, including internal and external memories. In synchronous mode, this command will wait for the AFI to transition to the "cleared" state, perform a PCI device remove and rescan in order to expose the default AFI Vendor and Device Id, and display the final state for the given FPGA slot number. ```bash sudo fpga-clear-local-image -S 0 -H @@ -150,7 +150,7 @@ sudo fpga-load-local-image -S 0 -I agfi-0fedcba9876543210 -A #### Describing the AFI content loaded on a specific FPGA slot after an asynchronous AFI load -Displays the current state for the given FPGA slot number. The output shows the FPGA in the “loaded” state after the FPGA image "load" operation. **_The "-R" option performs a PCI device remove and recan in order to expose the unique AFI Vendor and Device Id._** +Displays the current state for the given FPGA slot number. The output shows the FPGA in the “loaded” state after the FPGA image "load" operation. **_The "-R" option performs a PCI device remove and rescan in order to expose the unique AFI Vendor and Device Id._** ```bash sudo fpga-describe-local-image -S 0 -R -H @@ -173,7 +173,7 @@ sudo fpga-clear-local-image -S 0 -A #### Describing the AFI content loaded on a specific FPGA slot after an asynchronous AFI clear -The following command displays the current state for the given FPGA slot number. It shows that the FPGA is in the “cleared” state after the FPGA image "clear" operation. **_The "-R" option performs a PCI device remove and recan in order to expose the default AFI Vendor and Device Id._** +The following command displays the current state for the given FPGA slot number. It shows that the FPGA is in the “cleared” state after the FPGA image "clear" operation. **_The "-R" option performs a PCI device remove and rescan in order to expose the default AFI Vendor and Device Id._** ```bash sudo fpga-describe-local-image -S 0 -R -H diff --git a/sdk/userspace/fpga_mgmt_tools/src/fpga_local_cmd_parse.c b/sdk/userspace/fpga_mgmt_tools/src/fpga_local_cmd_parse.c index 4d5fe9f96..eb5658afe 100644 --- a/sdk/userspace/fpga_mgmt_tools/src/fpga_local_cmd_parse.c +++ b/sdk/userspace/fpga_mgmt_tools/src/fpga_local_cmd_parse.c @@ -97,7 +97,7 @@ static const char *describe_afi_usage[] = { " Examples: FPGA PCI and DDR metrics.", " -L, --clear-cache", " Return FPGA image hardware metrics (clear afi cache on read).", - " Examples: agfi-", + " Examples: FPGA status bits and DDR metrics.", " -R, --rescan", " Rescan the AFIDEVICE to update the per-AFI PCI VendorId and", " DeviceId that may be dynamically modified due to a", diff --git a/shared/bin/check_doc_links.py b/shared/bin/check_doc_links.py new file mode 100644 index 000000000..410f4d151 --- /dev/null +++ b/shared/bin/check_doc_links.py @@ -0,0 +1,176 @@ +#!/usr/bin/env python3 + +# ============================================================================= +# Amazon FPGA Hardware Development Kit +# +# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + +from codecs import strict_errors +from collections import defaultdict +from email.policy import default +import os +import pathlib +import glob +import re +import requests +import signal +import subprocess +import sys +from termcolor import colored +from time import sleep +from typing import Dict, List, Match + +def get_repo_root_dir() -> str: + repo_root_dir = subprocess.run("git rev-parse --show-toplevel".split(), capture_output=True, cwd=os.path.dirname(__file__), check=True).stdout.decode("utf-8").strip() + return repo_root_dir + + +def get_link_to_self_html(rst_f: str) -> str: + repo_root_dir = get_repo_root_dir() + rst_to_html = rst_f.replace(".rst", ".html") + rst_to_html = rst_to_html.replace("docs-rtd/source/", "") + rst_to_html = rst_to_html.replace(f"{repo_root_dir}", ".") + return rst_to_html + + +def perform_request(link_body: str, rst_f: str, preamble: str) -> int: + default_request = "http://localhost:3000" + is_external_link = link_body.startswith("http") + is_internal_section_link = link_body.startswith("#") + try: + if is_external_link: + response = requests.get( + link_body, + timeout=2, + headers={"User-Agent": "Mozilla/5.0"}, + allow_redirects=True + ) + elif is_internal_section_link: + link_to_self = get_link_to_self_html(rst_f) + internal_link = f"{link_to_self}{link_body}" + response = requests.head(f"{default_request}/{internal_link}") + else: + file_or_directory_link = f"{default_request}/{link_body}" + response = requests.head(file_or_directory_link) + + return_code = response.status_code + if return_code != 200: + raise requests.RequestException(response) + print(preamble + colored(f" OK, {return_code}", "green")) + return 0 + except requests.RequestException as re: + return_code = 404 + print(preamble + colored(f"ERROR, {return_code}", "red")) + return 1 + + +def navigate_to_rtd_build_html_dir() -> None: + repo_root_dir = get_repo_root_dir() + rtd_build_html_dir = "docs-rtd/build/html" + os.chdir(f"{repo_root_dir}/{rtd_build_html_dir}") + + +def check_links(files_links_dict: Dict[str, List[List[str]]]) -> None: + navigate_to_rtd_build_html_dir() + print(os.getcwd()) + link_server = subprocess.Popen( + [sys.executable, "-m", "http.server", "3000"], + stdout=subprocess.PIPE, + stderr=subprocess.PIPE, + ) + sleep(1) + + total_links_in_error = 0 + try: + for rst_f, link_info in files_links_dict.items(): + print(f"Now testing links from: {rst_f}") + for link in link_info: + link_text = link[0] + link_body = link[1] + skip_link = any([ + "mailto" in link_body, + "|" in link_body + ]) + if skip_link: + continue + preamble = f"\t{link_text}, {link_body}: " + total_links_in_error += perform_request(link_body, rst_f, preamble) + print() + finally: + link_server.send_signal(signal.SIGTERM) + print("Shutting down http server") + print(f"Total Links in Error: {total_links_in_error}") + link_server.wait() + + +def get_link_text_and_link(link_match: Match[str]) -> List[str]: + link_text = "".join([f"{word} " if word != "|" else "" for word in link_match.group(1).split()]).strip() + link_body = "".join([word if word != "|" else "" for word in link_match.group(2).split()]) + link_text_link_body = [link_text, link_body] + return link_text_link_body + + +def process_file(rst_f: str, files_links_dict: Dict[str, List[List[str]]]) -> None: + # Link looks like `Text that you would click on `__ + # Emphasized text is ``text``, so we don't want to be tricked by this. + ignore_double_backtick = r"(?]+)>`__" + link_pattern_regex = r''.join([ + ignore_double_backtick, + back_tick_that_starts_link, + gets_link_text, + gets_actual_link + ]) + compiled_link_pattern = re.compile(link_pattern_regex, re.DOTALL) + + file_contents = "" + with open(rst_f, "r", encoding="utf-8") as f: + file_contents = f.read() + + for link_match in compiled_link_pattern.finditer(file_contents): + files_links_dict[rst_f].append( + get_link_text_and_link(link_match) + ) + + +def get_links_from_files(rst_files: List[str]) -> Dict[str, List[List[str]]]: + files_links_dict: Dict[str, List[List[str]]] = defaultdict(list) + for rst_f in rst_files: + process_file(rst_f, files_links_dict) + return files_links_dict + + +def navigate_to_rtd_sources_dir() -> None: + repo_root_dir = get_repo_root_dir() + rtd_sources_dir = "docs-rtd/source" + os.chdir(f"{repo_root_dir}/{rtd_sources_dir}") + + +def gather_file_names() -> List[str]: + navigate_to_rtd_sources_dir() + rst_file_ext = ".rst" + rst_files = glob.glob(os.getcwd() + f"/**/*{rst_file_ext}", recursive=True) + return rst_files + + +def main(): + rst_files = gather_file_names() + files_links_dict = get_links_from_files(rst_files) + check_links(files_links_dict) + +if __name__ == "__main__": + main() \ No newline at end of file diff --git a/vitis/README.md b/vitis/README.md index 8d93e9cdf..e7b3fb8a0 100644 --- a/vitis/README.md +++ b/vitis/README.md @@ -7,7 +7,7 @@ This quick start guide will utilize a simple `hello_world` Vitis example to get 1. [Overview](#1-overview) 2. [Prerequisites](#2-prerequisites) * 2.1 [AWS Account and F2/EC2 Instances](#21-aws-account-and-f2ec2-instances) - * 2.2 [Github and Environment Setup](#22-github-and-environment-setup) + * 2.2 [GitHub and Environment Setup](#22-github-and-environment-setup) 3. [Design Emulation and Synthesis](#3-emulating-your-code) * 3.1 [Emulate the code](#31-emulation) * 3.1.1 [Hardware Emulation](#311-hardware-hw-emulation) @@ -30,7 +30,7 @@ This quick start guide will utilize a simple `hello_world` Vitis example to get * FPGA developer AMI (2024.1) - available for on-cloud F2 development with AMD tools pre-installed and free to use on AWS EC2 for F2 development. Customers can use this AMI to design, simulate, and build their designs. Given the large size of the FPGA used for F2, AMD tools work best with at least 4 vCPU's and 32GiB Memory. We recommend Compute Optimized and Memory Optimized instance types to successfully run the synthesis of acceleration code. Developers may start coding and run simulations on low-cost General Purpose instances types. Launch an instance using a pre-installed with Vitis and required licenses. -## 2.2 Github and Environment Setup +## 2.2 GitHub and Environment Setup * Clone this github repository, export your AWS IAM credentials, and source the *vitis_setup.sh* script: ``` cd aws-fpga @@ -62,7 +62,7 @@ INFO: Vitis Setup PASSED. # 3. Emulating Your Code -This section will walk you through creating, emulating, and compiling your host application and FPGA binary. FPGA binaries are used to create an AFI (Amazon FPGA Image) for use alongside the XRT. +Vitis hardware emulation is a cycle-accurate emulation of your accelerator design. This section will walk you through the emulation process. ## 3.1 Emulation @@ -88,7 +88,7 @@ Prior to starting a hardware emulation run, run the `hw_file_check` command to i The most critical file in each example directory is the `Makefile`. Some examples will have sub-examples, whose `Makefiles` are located in the associated subdirectory. -Note the presence of the `Makefile` in this subdirectory. Some examples will hav sub-examples, whose `Makefiles` are located in the associated subdirectory. +Note the presence of the `Makefile` in this subdirectory. Some examples will have sub-examples, whose `Makefiles` are located in the associated subdirectory. > [!WARNING] > A Makefile is required in order to run hardware emulation for all designs/examples diff --git a/vitis/tools/create_vitis_afi.sh b/vitis/tools/create_vitis_afi.sh deleted file mode 100755 index dc2f007bb..000000000 --- a/vitis/tools/create_vitis_afi.sh +++ /dev/null @@ -1,287 +0,0 @@ -#!/bin/bash - -# Amazon FPGA Hardware Development Kit -# -# Copyright 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. -# -# Licensed under the Amazon Software License (the "License"). You may not use -# this file except in compliance with the License. A copy of the License is -# located at -# -# http://aws.amazon.com/asl/ -# -# or in the "license" file accompanying this file. This file is distributed on -# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or -# implied. See the License for the specific language governing permissions and -# limitations under the License. - -set -e - -script=${BASH_SOURCE[0]} -full_script=$(readlink -f $script) -script_name=$(basename $full_script) - -if ! source $AWS_FPGA_REPO_DIR/shared/bin/set_common_functions.sh; then - echo "Couldn't set up common functions from withn sub-shell!" - exit 1 -fi - -if [[ -z $AWS_FPGA_REPO_DIR ]]; then - err_msg "\$AWS_FPGA_REPO_DIR not set! Please source vitis_setup.sh from this repository's root directory" - exit 1 -fi - -script_dir=$(dirname $full_script) -debug=0 - -function usage { - echo "USAGE: $script_name [-h|-help] [-s3_bucket=] [-s3_dcp_key=] [-s3_logs_key=] [-xclbin=] [-o=] [-aws_profile_name=]" -} - -function help { - info_msg "$script_name" - info_msg " " - info_msg "Vitis AFI Creation" - info_msg " " - info_msg "create_vitis_afi.sh assumes you have:" - info_msg " (*) Read the README on Github and understand the Vitis workflow (Vitis/README.md)" - info_msg " (*) Generated an XCLBIN using the Vitis Build flow" - info_msg " (*) Ready to create an AFI and test on F2. Your kernel has been validated using HW Emulation." - info_msg "create_vitis_afi.sh will:" - info_msg " (1) Extract three parts from your XCLBIN: DCP (.dcp) , clocks data(.json) and build metadata (.json)" - info_msg " (2) Generate a Manifest file for AFI creation that sets the clocks based on your achieved target freq from your build" - info_msg " (3) Prepare tar file for AFI creation process" - info_msg " (4) Call aws ec2 create-fpga-image" - info_msg " (5) Create new XCLBIN (called AWSXCLBIN) using Metadata and AGFI-ID" - echo " " - usage -} - -if [ -z "$1" ]; then - err_msg "Invalid usage" - usage - exit 1 -fi - -while [ "$1" != "" ]; do - PARAM=$(echo $1 | awk -F= '{print $1}') - VALUE=$(echo $1 | awk -F= '{print $2}') - case $PARAM in - -h | --help) - help - exit - ;; - -xclbin) - xclbin=$VALUE - ;; - -o) - awsxclbin=$VALUE - ;; - -aws_profile_name) - aws_profile_name=$VALUE - ;; - -s3_bucket) - s3_bucket=$VALUE - ;; - -s3_logs_key) - s3_logs=$VALUE - ;; - -s3_dcp_key) - s3_dcps=$VALUE - ;; - *) - err_msg "Unknown parameter \"$PARAM\"" - usage - exit 1 - ;; - esac - shift -done - -if [ -z "$RELEASE_VER" ]; then - err_msg "Env variable RELEASE_VER not set, did you source vitis_setup.sh?" - exit 1 -fi - -if [[ -e "$xclbin" ]]; then - info_msg "Found xclbin '$xclbin'" -else - err_msg "File '$xclbin' not found" - exit 1 -fi - -stripped_xclbin=$(basename $xclbin) -ext_xclbin=${stripped_xclbin##*.} -stripped_xclbin=${stripped_xclbin%.*} - -info_msg "$stripped_xclbin" - -if [ -z "$awsxclbin" ]; then - awsxclbin=$stripped_xclbin -fi - -if [ "$awsxclbin" != "$stripped_xclbin" ]; then - warn_msg "$awsxclbin does not match $stripped_xclbin" - warn_msg "For github examples, -o must be equal to $stripped_xclbin" -fi - -if [[ -e "$awsxclbin" ]]; then - err_msg "File '$awsxclbin' already exists" - exit 1 -fi - -if [ ":$s3_bucket" == ":" ]; then - err_msg "Invalid s3_bucket" - usage - exit 1 -fi - -# s3 logs is not required -# s3 dcp key is required -if [ -z "$s3_dcps" ]; then - err_msg "Invalid s3_dcps key" - usage - exit 1 -fi - -timestamp=$(date +"%Y_%m_%d-%H%M%S") - -#Steps -#1. Strip XCLBIN to get DCP for ingestion -#2. Create Manifest file -#3. Prepare ingestion tar file -#4. Call create-fpga-image -#5. Manipulate the AFI ID -#6. Create awsxclbin - -#STEP 1 -#Strip XCLBIN to get DCP for ingestion -#/opt/xilinx/xrt/bin/xclbinsplit -o ${timestamp} $xclbin -/opt/xilinx/xrt/bin/xclbinutil --dump-section BUILD_METADATA:JSON:${timestamp}_build.json --dump-section CLOCK_FREQ_TOPOLOGY:JSON:${timestamp}_clocks.json --dump-section BITSTREAM:RAW:${timestamp}_SH_CL_routed.dcp -i $xclbin - -if [[ -e "${timestamp}_SH_CL_routed.dcp" ]]; then - info_msg "Split DCP from xclbin: ${timestamp}_SH_CL_routed.dcp" -else - err_msg "File ${timestamp}_SH_CL_routed.dcp not found" - exit 1 -fi - -if [[ -e "${timestamp}_build.json" ]]; then - info_msg "The build Metadata from xclbin: ${timestamp}_build.json" -else - err_msg "File ${timestamp}_build.json not found" - exit 1 -fi - -if [[ -e "${timestamp}_clocks.json" ]]; then - info_msg "The clocks Metadata from xclbin: ${timestamp}_clocks.json" -else - err_msg "File ${timestamp}_clocks.json not found" - exit 1 -fi - -if [[ -d "to_aws" ]]; then - err_msg "Directory to_aws already exists" - exit 1 -fi - -mkdir to_aws -cp ${timestamp}_SH_CL_routed.dcp ./to_aws/ - -#STEP 2 -# Create Manifest file -build_dir_name=$(dirname "${xclbin}") -strategy=DEFAULT -hdk_version=$(grep 'HDK_VERSION' $script_dir/../../hdk/hdk_version.txt | sed 's/=/ /g' | awk '{print $2}') -shell_version=0x10162423 -tool_version=v$RELEASE_VER -device_id=0xF010 -vendor_id=0x1D0F -subsystem_id=0x1D51 -subsystem_vendor_id=0xFEDD - -# Get XSA info from build metadata -vendor=$(echo $(grep -A 6 dsa ./${timestamp}_build.json | grep vendor | sed 's/.*: "//g' | sed 's/",//')) -board_id=$(echo $(grep -A 6 dsa ./${timestamp}_build.json | grep board_id | sed 's/.*: "//g' | sed 's/",//')) -plat_name=$(echo $(grep -A 6 dsa ./${timestamp}_build.json | grep name | sed 's/.*: "//g' | sed 's/",//')) -major=$(echo $(grep -A 6 dsa ./${timestamp}_build.json | grep major | sed 's/.*: "//g' | sed 's/",//')) -minor=$(echo $(grep -A 6 dsa ./${timestamp}_build.json | grep minor | sed 's/.*: "//g' | sed 's/",//')) - -# Get clock info from clock metadata -read -a clock_main_a0 <<<"$(echo $(grep -B 1 SYSTEM ${timestamp}_clocks.json | grep -o -e '[0-9]*'))" -clock_main_a0=$(echo ${clock_main_a0[0]}) -clock_extra_b0=$(echo $(grep -B 2 DATA_CLK ${timestamp}_clocks.json | grep freq | grep -o -e '[0-9]*')) -clock_extra_c0=$(echo $(grep -B 2 KERNEL_CLK ${timestamp}_clocks.json | grep -o -e '[0-9]*')) - -if [[ "$vendor" != "xilinx" && "$board_id" != "aws-vu47p-f2" && "$plat_name" != "xdma-shell-v10162423" && "$major" != "202410" && "$minor" != "1" ]]; then - err_msg "Platform ${vendor}_${board_id}_${plat_name}_${major}_${minor} used to create xclbin is not correct, you should be using xilinx_aws-vu47p-f2_xdma-shell-v10162423_202410_1" - exit -fi - -# Write Manifest File here -hash=$(sha256sum to_aws/${timestamp}_SH_CL_routed.dcp | awk '{ print $1 }') -manifest_file="${timestamp}_manifest.txt" -exec 3<>$manifest_file -echo "manifest_format_version=2" >&3 -echo "pci_vendor_id=$vendor_id" >&3 -echo "pci_device_id=$device_id" >&3 -echo "pci_subsystem_id=$subsystem_id" >&3 -echo "pci_subsystem_vendor_id=$subsystem_vendor_id" >&3 -echo "dcp_hash=$hash" >&3 -echo "shell_version=$shell_version" >&3 -echo "dcp_file_name=${timestamp}_SH_CL_routed.dcp" >&3 -echo "hdk_version=$hdk_version" >&3 -echo "tool_version=$tool_version" >&3 -echo "date=$timestamp" >&3 -echo "clock_main_a0=$clock_main_a0" >&3 -echo "clock_extra_b0=$clock_extra_b0" >&3 -echo "clock_extra_c0=$clock_extra_c0" >&3 -exec 3>&- -exec 3>&- - -if [[ -e "$manifest_file" ]]; then - info_msg "Generated manifest file '$manifest_file'" -else - err_msg "File '$manifest_file' not found" - exit 1 -fi - -cp $manifest_file to_aws/$manifest_file - -#STEP 3 -#Prepare ingestion -tar -cf ${timestamp}_Developer_Vitis_Kernel.tar to_aws/${timestamp}_SH_CL_routed.dcp to_aws/${timestamp}_manifest.txt - -#STEP 4 -#Call create-fpga-image -profile_text="" -if [ "$aws_profile_name" != "" ]; then - profile_text="--profile ${aws_profile_name}" -fi - -log_storage_text="" -if [ "${s3_logs}" != "" ]; then - log_storage_text="--logs-storage-location Bucket=${s3_bucket},Key=${s3_logs}" -fi - -if ! aws s3 ${profile_text} cp ${timestamp}_Developer_Vitis_Kernel.tar s3://${s3_bucket}/${s3_dcps}/; then - err_msg "Couldn't copy files to s3://${s3_bucket}/${s3_dcps}/" - exit 1 -fi - -if ! aws ec2 ${profile_text} create-fpga-image --name ${stripped_xclbin} --description ${stripped_xclbin} --input-storage-location Bucket=${s3_bucket},Key=${s3_dcps}/${timestamp}_Developer_Vitis_Kernel.tar ${log_storage_text} >${timestamp}_afi_id.txt; then - err_msg "Failed to create AFI from .xclbin file!" - exit 1 -fi - -#STEP 5 -#Manipulate the AFI ID -test=$(grep agfi ${timestamp}_afi_id.txt | awk -F: '{print $2}' | sed 's/ \"//g' | sed 's/\".*//g' | sed ':a;N;$!ba;s/\n/ /g') -echo -n $test >${timestamp}_agfi_id.txt -echo ${timestamp}_agfi_id.txt - -#STEP 6 -#Create .awsxclbin -if [[ "$RELEASE_VER" == "2024.1" ]]; then - /opt/xilinx/xrt/bin/xclbinutil -i $xclbin --remove-section PARTITION_METADATA --replace-section BITSTREAM:RAW:${timestamp}_agfi_id.txt -o ${awsxclbin}.awsxclbin -fi diff --git a/vitis_setup.sh b/vitis_setup.sh index a91f9f9b9..4fa3c6128 100644 --- a/vitis_setup.sh +++ b/vitis_setup.sh @@ -347,6 +347,113 @@ function setup_xsa { } +function xrt_install_check { + + xrt_path=/opt/xilinx/xrt + if [[ -n $(lsmod | grep "xocl") ]]; then + info_msg "###############################################################################" + info_msg "# XRT install detected! #" + info_msg "# If XRT was installed using the devkit, run 'source /opt/xilinx/xrt/setup.sh #" + info_msg "# Otherwise, please source your XRT setup script, 'setup.sh' #" + info_msg "# To reinstall, run 'install_xrt -f'! #" + info_msg "###############################################################################" + return 2 + fi + info_msg "###########################################################################" + info_msg "# No XRT install detected! #" + info_msg "# To install the XRT for Vitis runtime support, run 'install_xrt' #" + info_msg "###########################################################################" + return 0 +} + +function install_xrt { + xrt_path=/opt/xilinx/xrt + xrt_dpkg_install_path=$xrt_path/XRT/build/Release + + xrt_repo_name=XRT + xrt_repo_url=https://github.com/Xilinx/XRT.git + xrt_branch=2024.1 + xrt_2024_1_working_commit_hash=ea9e7d2d88719e08575dca15d2ca2c1ce624e800 + xrt_deps_script_path=src/runtime_src/tools/scripts/xrtdeps.sh + xrt_build_script_run="build/build.sh -noert" + xrt_build_release_dir="build/Release" + xrt_setup_script_path=$xrt_path/setup.sh + + if [[ -z $AWS_FPGA_REPO_DIR ]]; then + err_msg "\$AWS_FPGA_REPO_DIR not defined when trying to install XRT!" + cd $AWS_FPGA_REPO_DIR && return 1 + fi + + xrt_install_check + if [[ $? -eq 0 || $1 == "-f" || $1 == "--force" ]]; then + if [[ -n $(echo $PATH | grep "cmake-3.3.2") ]]; then + export PATH="/usr/bin:$PATH" + fi + + cd $HOME + if [[ ! -d $xrt_repo_name ]]; then + info_msg "Cloning XRT repo into home directory: $HOME" + info_msg "This directory may be moved to any destination, once the XRT install is complete!" + if ! git clone $xrt_repo_url --recurse-submodules; then + err_msg "Couldn't clone XRT repository!" + cd $AWS_FPGA_REPO_DIR && return 1 + fi + else + info_msg "XRT repo found in $HOME" + fi + + cd $xrt_repo_name + if ! git fetch; then + err_msg "Couldn't fetch updated references for XRT repo!" + cd $AWS_FPGA_REPO_DIR && return 1 + fi + + if ! git checkout $xrt_branch; then + err_msg "Couldn't checkout branch: $xrt_branch!" + cd $AWS_FPGA_REPO_DIR && return 1 + fi + + if ! git checkout $xrt_2024_1_working_commit_hash; then + err_msg "Couldn't checkout compatible commit: $xrt_2024_1_working_commit_hash!" + cd $AWS_FPGA_REPO_DIR && return 1 + fi + + if ! sudo ./$xrt_deps_script_path; then + err_msg "Couldn't install XRT dependencies!" + cd $AWS_FPGA_REPO_DIR && return 1 + fi + + if ! ./$xrt_build_script_run; then + err_msg "Couldn't build XRT dpkgs!" + cd $AWS_FPGA_REPO_DIR && return 1 + fi + + cd $xrt_build_release_dir + + # Base XRT install first + for file in $(ls *amd64-xrt.deb); do + sudo dpkg -i $file + done + + # AWS extension install + for file in $(ls *amd64-aws.deb); do + sudo dpkg -i $file + done + + if ! source $xrt_setup_script_path; then + err_msg "Couldn't setup XRT after install!" + cd $AWS_FPGA_REPO_DIR && return 1 + fi + + info_msg "XRT installation complete!" + cd $AWS_FPGA_REPO_DIR + return 0 + fi + info_msg "XRT already installed!" + info_msg "Nothing to do!" + return 0 +} + function hw_file_check { required_files=("Makefile" "README.rst" "description.json" "details.rst" "makefile_us_alveo.mk" "qor.json" "utils.mk" "xrt.ini") missing_a_file=0 @@ -385,9 +492,10 @@ if [[ ! -e vitis/aws_platform/$xsa_name/$platform_file_name ]]; then fi fi -# Make the Vitis AFI creation a little easier. -if [[ -z $(cat ~/.bashrc | grep "create_vitis_afi") ]]; then - alias create_vitis_afi='${AWS_FPGA_REPO_DIR}/vitis/tools/create_vitis_afi.sh' +xrt_install_check +if [[ $? -eq 1 ]]; then + err_msg "!!! Vitis Setup FAILED !!!" + return $? fi info_msg "Vitis Setup PASSED"

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