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Hotfix v1.2.5
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10 files changed

+75
-22
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RELEASE_NOTES.md

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,10 @@ See [Errata](./ERRATA.md) for additional documentation of unsupported features a
2727
* 1 DDR controller implemented in the SH (always available)
2828
* 3 DDR controllers implemented in the CL (configurable number of implemented controllers allowed)
2929

30+
# Release 1.2.5
31+
* Improved tool checks in hdk_setup
32+
* Fixed simulation model and test bench bugs
33+
3034
# Release 1.2.4
3135
* AWS SDK API `aws ec2 describe-fpga-images` released. See [describe-fpga-images](./hdk/docs/describe_fpga_images.md) document for details on how to use this API. Requires Developer AMI 1.2.4 or awscli upgrade: `pip install --upgrade --user awscli`
3236
* Fix cl_dram_dam debug probes (.ltx) generation in build scripts

hdk/cl/examples/cl_hello_world/software/verif_rtl/src/test_hello_world.c

Lines changed: 7 additions & 7 deletions
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@@ -18,34 +18,34 @@
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#include <stdint.h>
1919

2020
// Vivado does not support svGetScopeFromName
21-
#ifdef INCLUDE_DPI_CALLS
21+
//#ifdef INCLUDE_DPI_CALLS
2222
#ifndef VIVADO_SIM
2323
#include "svdpi.h"
2424
#endif
25-
#endif
25+
//#endif
2626

2727
#include "sh_dpi_tasks.h"
2828

29-
#define HELLO_WORLD_REG_ADDR UINT64_C(0x00)
29+
#define HELLO_WORLD_REG_ADDR UINT64_C(0x500)
3030

3131
void test_main(uint32_t *exit_code) {
3232

3333
// Vivado does not support svGetScopeFromName
34-
#ifdef INCLUDE_DPI_CALLS
34+
//#ifdef INCLUDE_DPI_CALLS
3535
#ifndef VIVADO_SIM
3636
svScope scope;
3737
#endif
38-
#endif
38+
//#endif
3939

4040
uint32_t rdata;
4141

4242
// Vivado does not support svGetScopeFromName
43-
#ifdef INCLUDE_DPI_CALLS
43+
//#ifdef INCLUDE_DPI_CALLS
4444
#ifndef VIVADO_SIM
4545
scope = svGetScopeFromName("tb");
4646
svSetScope(scope);
4747
#endif
48-
#endif
48+
//#endif
4949

5050
log_printf("Writing 0xDEAD_BEEF to address 0x%x", HELLO_WORLD_REG_ADDR);
5151
cl_poke(HELLO_WORLD_REG_ADDR, 0xDEADBEEF);

hdk/cl/examples/cl_hello_world/verif/scripts/top.questa.f

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -14,20 +14,22 @@
1414
# limitations under the License.
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1616
+define+QUESTA_SIM
17-
17+
+define+CARD_1=card
1818
+libext+.v
1919
+libext+.sv
2020
+libext+.svh
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2222
-y ${CL_ROOT}/../common/design
2323
-y ${CL_ROOT}/design
24+
-y ${CL_ROOT}/verif/sv
2425
-y ${SH_LIB_DIR}
2526
-y ${SH_INF_DIR}
2627
-y ${SH_SH_DIR}
2728
-y ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/hdl
2829
-y ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/sim
2930

3031
+incdir+${CL_ROOT}/../common/design
32+
+incdir+${CL_ROOT}/design
3133
+incdir+${CL_ROOT}/verif/sv
3234
+incdir+${SH_LIB_DIR}
3335
+incdir+${SH_INF_DIR}
@@ -52,10 +54,11 @@
5254
${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/sim/axi_register_slice_light.v
5355
${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl/axi_register_slice_v2_1_vl_rfs.v
5456
${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl/axi_infrastructure_v1_1_vl_rfs.v
55-
${CL_ROOT}/design/cl_hello_world.sv
5657
${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice/sim/axi_register_slice.v
5758
${HDK_SHELL_DESIGN_DIR}/ip/axi_clock_converter_0/sim/axi_clock_converter_0.v
5859

60+
${CL_ROOT}/design/cl_hello_world.sv
61+
5962
-f ${HDK_COMMON_DIR}/verif/tb/filelists/tb.${SIMULATOR}.f
6063

6164
${TEST_NAME}

hdk/cl/examples/cl_hello_world/verif/scripts/top.vivado.f

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,7 @@
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2222
-sourcelibdir ${CL_ROOT}/../common/design
2323
-sourcelibdir ${CL_ROOT}/design
24+
-sourcelibdir ${CL_ROOT}/verif/sv
2425
-sourcelibdir ${SH_LIB_DIR}
2526
-sourcelibdir ${SH_INF_DIR}
2627
-sourcelibdir ${SH_SH_DIR}

hdk/common/verif/include/sh_dpi_tasks.svh

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -42,11 +42,11 @@ import tb_type_defines_pkg::*;
4242
endtask
4343

4444
task cl_peek(input longint unsigned addr, output int unsigned data);
45-
tb.card.fpga.sh.peek(addr, data);
45+
tb.card.fpga.sh.peek(.addr(addr), .data(data), .intf(AxiPort::PORT_OCL));
4646
endtask
4747

4848
task cl_poke(input longint unsigned addr, int unsigned data);
49-
tb.card.fpga.sh.poke(addr, data);
49+
tb.card.fpga.sh.poke(.addr(addr), .data(data), .intf(AxiPort::PORT_OCL));
5050
endtask
5151

5252
task sv_int_ack(input int unsigned int_num);

hdk/common/verif/models/sh_bfm/sh_bfm.sv

Lines changed: 16 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1445,7 +1445,7 @@ module sh_bfm #(
14451445
ClockRecipe::A2: begin
14461446
MAIN_A0_DLY = 32ns;
14471447
CORE_DLY = 32ns;
1448-
EXTRA_A1_DLY = 64ns;
1448+
EXTRA_A1_DLY = 32ns;
14491449
EXTRA_A2_DLY = 4ns;
14501450
EXTRA_A3_DLY = 8ns;
14511451
end
@@ -1894,7 +1894,7 @@ module sh_bfm #(
18941894
last_beat = 0;
18951895
start_addr = 0;
18961896
aligned = 0;
1897-
1897+
18981898
for (int chan = 0; chan < 4; chan++) begin
18991899
if ((h2c_dma_started[chan] != 1'b0) && (h2c_dma_list[chan].size() > 0)) begin
19001900
dop = h2c_dma_list[chan].pop_front();
@@ -1909,7 +1909,8 @@ module sh_bfm #(
19091909
for(int burst_cnt=0; burst_cnt < num_of_data_beats; ) begin
19101910
if(burst_cnt == 0) begin // if first data beat
19111911
axi_cmd.addr = dop.cl_addr;
1912-
axi_cmd.len = aligned ? (num_of_data_beats - 1 - last_beat) : 0;
1912+
axi_cmd.len = (num_of_data_beats==1) ? 0 :
1913+
aligned ? (num_of_data_beats - 1 - last_beat) : 0;
19131914
// handle the condition if addr is crossing 4k page boundry
19141915
if(aligned && (dop.cl_addr[11:0] + ((axi_cmd.len + 1) * 64) > 4095)) begin
19151916
axi_cmd.len = ((4096 - dop.cl_addr[11:0])/64) - 1;
@@ -1938,9 +1939,17 @@ module sh_bfm #(
19381939
axi_data.strb = 64'b0;
19391940
axi_data.id = chan;
19401941
last_data_beat = (((num_of_data_beats - 1) - burst_cnt) == 0) ? 1 : 0;
1941-
num_bytes = last_beat ? (dop.len + dop.cl_addr[5:0])%64 : 64;
1942+
num_bytes = last_beat ? (dop.len + dop.cl_addr[5:0])%64 : 64;
19421943
axi_data.last = (j == axi_cmd.len) ? 1 : 0;
1943-
if(last_data_beat) begin
1944+
if(num_of_data_beats == 1) begin
1945+
num_bytes = (dop.len)%64;
1946+
for(int i=start_addr[5:0]; i < (num_bytes+start_addr[5:0]); i++) begin
1947+
axi_data.data = axi_data.data | tb.hm_get_byte(.addr(dop.buffer + byte_cnt)) << 8*i;
1948+
axi_data.strb = axi_data.strb | 1 << i;
1949+
byte_cnt++;
1950+
end
1951+
end
1952+
else if(last_data_beat) begin
19441953
for(int i=0; i < num_bytes; i++) begin
19451954
axi_data.data = axi_data.data | tb.hm_get_byte(.addr(dop.buffer + byte_cnt)) << 8*i;
19461955
axi_data.strb = axi_data.strb | 1 << i;
@@ -2040,7 +2049,8 @@ module sh_bfm #(
20402049
for(int burst_cnt=0; burst_cnt < num_of_data_beats; ) begin
20412050
if(burst_cnt == 0) begin // if first data beat
20422051
axi_cmd.addr = dop.cl_addr;
2043-
axi_cmd.len = aligned ? (num_of_data_beats - 1 - last_beat) : 0;
2052+
axi_cmd.len = (num_of_data_beats==1) ? 0 :
2053+
aligned ? (num_of_data_beats - 1 - last_beat) : 0;
20442054
// handle the condition if addr is crossing 4k page boundry
20452055
if(aligned && (dop.cl_addr[11:0] + ((axi_cmd.len + 1) * 64) > 4095)) begin
20462056
axi_cmd.len = ((4096 - dop.cl_addr[11:0])/64) - 1;

hdk/common/verif/tb/sv/tb_type_defines_pkg.sv

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ package tb_type_defines_pkg;
1818
// clk_main_a0 clk_extra_a1 clk_extra_a2 clk_extra_a3
1919
// Recipe A0 (Default) 125 62.5 187.5 250
2020
// Recipe A1 250 125 375 500
21-
// Recipe A2 15.625 7.8125 125 62.5
21+
// Recipe A2 15.625 15.625 125 62.5
2222

2323
// clk_extra_b0 clk_extra_b1
2424
// Recipe B0 (Default) 250 125

hdk/hdk_version.txt

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1 +1 @@
1-
HDK_VERSION=1.2.4
1+
HDK_VERSION=1.2.5

hdk/tests/dcp_generation_tests/gen_dcp.sh

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -61,6 +61,15 @@ if [ ! -d $HDK_DIR/cl/examples/$test/build/checkpoints/to_aws ]; then
6161
exit 1
6262
fi
6363

64+
cd $HDK_DIR/cl/examples/$test/build/checkpoints
65+
66+
echo "INFO: Checking that a non zero size ltx file exists in the folder"
67+
non_zero_ltx=$(find . -name '*.ltx' -type f ! -size 0)
68+
if [ "$non_zero_ltx" = "" ]; then
69+
echo -e >&2 "ERROR: LTX file not found or is of 0 byte size\n"
70+
exit 1
71+
fi
72+
6473
cd $HDK_DIR/cl/examples/$test/build/checkpoints/to_aws
6574

6675
echo "INFO: Checking that a non zero size manifest file exists in the folder"

hdk_setup.sh

Lines changed: 29 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,20 @@ script_dir=$(dirname $full_script)
2929

3030
debug=0
3131

32+
# This function checks if an environment module exists
33+
# Returns 0 if it exists, and returns 1 if it doesn't
34+
function does_module_exist() {
35+
36+
output=`/usr/bin/ls /usr/local/Modules/$MODULE_VERSION/modulefiles | grep $1`
37+
38+
if [[ $output == "$1" ]]; then
39+
return 0;
40+
else
41+
return 1;
42+
fi
43+
}
44+
45+
3246
function info_msg {
3347
echo -e "INFO: $1"
3448
}
@@ -102,9 +116,21 @@ debug_msg "Checking for Vivado install:"
102116
if [ -e /usr/local/Modules/$MODULE_VERSION/bin/modulecmd ]; then
103117
# Module command is installed.
104118
# Load and unload the modules just to make sure have the environment set correctly
105-
module unload vivado
106-
module unload sdx
107-
module load vivado
119+
120+
# We want to make sure sdx exists before calling the unload function
121+
if does_module_exist sdx; then
122+
module unload sdx
123+
fi
124+
125+
if does_module_exist vivado; then
126+
# First unload and then load it back.
127+
module unload vivado
128+
module load vivado
129+
else
130+
err_msg "The modulefile to set the environment variables for Vivado does not exist!"
131+
err_msg " Please source the hdk_setup script on the correct AMI from the marketplace"
132+
return 1
133+
fi
108134
fi
109135

110136
# before going too far make sure Vivado is available

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