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core.scala
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core.scala
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//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISC-V Processor Core
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// BOOM has the following (conceptual) stages:
// if0 - Instruction Fetch 0 (next-pc select)
// if1 - Instruction Fetch 1 (I$ access)
// if2 - Instruction Fetch 2 (instruction return)
// if3 - Instruction Fetch 3 (enqueue to fetch buffer)
// if4 - Instruction Fetch 4 (redirect from bpd)
// dec - Decode
// ren - Rename1
// dis - Rename2/Dispatch
// iss - Issue
// rrd - Register Read
// exe - Execute
// mem - Memory
// sxt - Sign-extend
// wb - Writeback
// com - Commit
package boom.exu
import java.nio.file.{Paths}
import chisel3._
import chisel3.util._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket.{Causes, PRV}
import freechips.rocketchip.util.{Str, UIntIsOneOf, CoreMonitorBundle}
import freechips.rocketchip.devices.tilelink.{PLICConsts, CLINTConsts}
import testchipip.{ExtendedTracedInstruction}
import boom.common._
import boom.ifu.{GlobalHistory, HasBoomFrontendParameters}
import boom.exu.FUConstants._
import boom.util._
/**
* Top level core object that connects the Frontend to the rest of the pipeline.
*/
class BoomCore(usingTrace: Boolean)(implicit p: Parameters) extends BoomModule
with HasBoomFrontendParameters // TODO: Don't add this trait
{
val io = new freechips.rocketchip.tile.CoreBundle
{
val hartid = Input(UInt(hartIdLen.W))
val interrupts = Input(new freechips.rocketchip.tile.CoreInterrupts())
val ifu = new boom.ifu.BoomFrontendIO
val ptw = Flipped(new freechips.rocketchip.rocket.DatapathPTWIO())
val rocc = Flipped(new freechips.rocketchip.tile.RoCCCoreIO())
val lsu = Flipped(new boom.lsu.LSUCoreIO)
val ptw_tlb = new freechips.rocketchip.rocket.TLBPTWIO()
val trace = Output(Vec(coreParams.retireWidth, new ExtendedTracedInstruction))
val fcsr_rm = UInt(freechips.rocketchip.tile.FPConstants.RM_SZ.W)
}
//**********************************
// construct all of the modules
// Only holds integer-registerfile execution units.
val exe_units = new boom.exu.ExecutionUnits(fpu=false)
val jmp_unit_idx = exe_units.jmp_unit_idx
val jmp_unit = exe_units(jmp_unit_idx)
// Meanwhile, the FP pipeline holds the FP issue window, FP regfile, and FP arithmetic units.
var fp_pipeline: FpPipeline = null
if (usingFPU) fp_pipeline = Module(new FpPipeline)
// ********************************************************
// Clear fp_pipeline before use
if (usingFPU) {
fp_pipeline.io.ll_wports := DontCare
fp_pipeline.io.wb_valids := DontCare
fp_pipeline.io.wb_pdsts := DontCare
}
val numIrfWritePorts = exe_units.numIrfWritePorts + memWidth
val numLlIrfWritePorts = exe_units.numLlIrfWritePorts
val numIrfReadPorts = exe_units.numIrfReadPorts
val numFastWakeupPorts = exe_units.count(_.bypassable)
val numAlwaysBypassable = exe_units.count(_.alwaysBypassable)
val numIntIssueWakeupPorts = numIrfWritePorts + numFastWakeupPorts - numAlwaysBypassable // + memWidth for ll_wb
val numIntRenameWakeupPorts = numIntIssueWakeupPorts
val numFpWakeupPorts = if (usingFPU) fp_pipeline.io.wakeups.length else 0
val decode_units = for (w <- 0 until decodeWidth) yield { val d = Module(new DecodeUnit); d }
val dec_brmask_logic = Module(new BranchMaskGenerationLogic(coreWidth))
val rename_stage = Module(new RenameStage(coreWidth, numIntPhysRegs, numIntRenameWakeupPorts, false))
val fp_rename_stage = if (usingFPU) Module(new RenameStage(coreWidth, numFpPhysRegs, numFpWakeupPorts, true)) else null
val pred_rename_stage = Module(new PredRenameStage(coreWidth, ftqSz, 1))
val rename_stages = if (usingFPU) Seq(rename_stage, fp_rename_stage, pred_rename_stage) else Seq(rename_stage, pred_rename_stage)
val mem_iss_unit = Module(new IssueUnitCollapsing(memIssueParam, numIntIssueWakeupPorts))
mem_iss_unit.suggestName("mem_issue_unit")
val int_iss_unit = Module(new IssueUnitCollapsing(intIssueParam, numIntIssueWakeupPorts))
int_iss_unit.suggestName("int_issue_unit")
val issue_units = Seq(mem_iss_unit, int_iss_unit)
val dispatcher = Module(new BasicDispatcher)
val iregfile = Module(new RegisterFileSynthesizable(
numIntPhysRegs,
numIrfReadPorts,
numIrfWritePorts,
xLen,
Seq.fill(memWidth) {true} ++ exe_units.bypassable_write_port_mask)) // bypassable ll_wb
val pregfile = Module(new RegisterFileSynthesizable(
ftqSz,
exe_units.numIrfReaders,
1,
1,
Seq(true))) // The jmp unit is always bypassable
pregfile.io := DontCare // Only use the IO if enableSFBOpt
// wb arbiter for the 0th ll writeback
// TODO: should this be a multi-arb?
val ll_wbarb = Module(new Arbiter(new ExeUnitResp(xLen), 1 +
(if (usingFPU) 1 else 0) +
(if (usingRoCC) 1 else 0)))
val iregister_read = Module(new RegisterRead(
issue_units.map(_.issueWidth).sum,
exe_units.withFilter(_.readsIrf).map(_.supportedFuncUnits),
numIrfReadPorts,
exe_units.withFilter(_.readsIrf).map(x => 2),
exe_units.numTotalBypassPorts,
jmp_unit.numBypassStages,
xLen))
val rob = Module(new Rob(
numIrfWritePorts + numFpWakeupPorts, // +memWidth for ll writebacks
numFpWakeupPorts))
// Used to wakeup registers in rename and issue. ROB needs to listen to something else.
val int_iss_wakeups = Wire(Vec(numIntIssueWakeupPorts, Valid(new ExeUnitResp(xLen))))
val int_ren_wakeups = Wire(Vec(numIntRenameWakeupPorts, Valid(new ExeUnitResp(xLen))))
val pred_wakeup = Wire(Valid(new ExeUnitResp(1)))
require (exe_units.length == issue_units.map(_.issueWidth).sum)
//***********************************
// Pipeline State Registers and Wires
// Decode/Rename1 Stage
val dec_valids = Wire(Vec(coreWidth, Bool())) // are the decoded instruction valid? It may be held up though.
val dec_uops = Wire(Vec(coreWidth, new MicroOp()))
val dec_fire = Wire(Vec(coreWidth, Bool())) // can the instruction fire beyond decode?
// (can still be stopped in ren or dis)
val dec_ready = Wire(Bool())
val dec_xcpts = Wire(Vec(coreWidth, Bool()))
val ren_stalls = Wire(Vec(coreWidth, Bool()))
// Rename2/Dispatch stage
val dis_valids = Wire(Vec(coreWidth, Bool()))
val dis_uops = Wire(Vec(coreWidth, new MicroOp))
val dis_fire = Wire(Vec(coreWidth, Bool()))
val dis_ready = Wire(Bool())
// Issue Stage/Register Read
val iss_valids = Wire(Vec(exe_units.numIrfReaders, Bool()))
val iss_uops = Wire(Vec(exe_units.numIrfReaders, new MicroOp()))
val bypasses = Wire(Vec(exe_units.numTotalBypassPorts, Valid(new ExeUnitResp(xLen))))
val pred_bypasses = Wire(Vec(jmp_unit.numBypassStages, Valid(new ExeUnitResp(1))))
require(jmp_unit.bypassable)
// --------------------------------------
// Dealing with branch resolutions
// The individual branch resolutions from each ALU
val brinfos = Reg(Vec(coreWidth, new BrResolutionInfo()))
// "Merged" branch update info from all ALUs
// brmask contains masks for rapidly clearing mispredicted instructions
// brindices contains indices to reset pointers for allocated structures
// brindices is delayed a cycle
val brupdate = Wire(new BrUpdateInfo)
val b1 = Wire(new BrUpdateMasks)
val b2 = Reg(new BrResolutionInfo)
brupdate.b1 := b1
brupdate.b2 := b2
for ((b, a) <- brinfos zip exe_units.alu_units) {
b := a.io.brinfo
b.valid := a.io.brinfo.valid && !rob.io.flush.valid
}
b1.resolve_mask := brinfos.map(x => x.valid << x.uop.br_tag).reduce(_|_)
b1.mispredict_mask := brinfos.map(x => (x.valid && x.mispredict) << x.uop.br_tag).reduce(_|_)
// Find the oldest mispredict and use it to update indices
var mispredict_val = false.B
var oldest_mispredict = brinfos(0)
for (b <- brinfos) {
val use_this_mispredict = !mispredict_val ||
b.valid && b.mispredict && IsOlder(b.uop.rob_idx, oldest_mispredict.uop.rob_idx, rob.io.rob_head_idx)
mispredict_val = mispredict_val || (b.valid && b.mispredict)
oldest_mispredict = Mux(use_this_mispredict, b, oldest_mispredict)
}
b2.mispredict := mispredict_val
b2.cfi_type := oldest_mispredict.cfi_type
b2.taken := oldest_mispredict.taken
b2.pc_sel := oldest_mispredict.pc_sel
b2.uop := UpdateBrMask(brupdate, oldest_mispredict.uop)
b2.jalr_target := RegNext(jmp_unit.io.brinfo.jalr_target)
b2.target_offset := oldest_mispredict.target_offset
val oldest_mispredict_ftq_idx = oldest_mispredict.uop.ftq_idx
assert (!((brupdate.b1.mispredict_mask =/= 0.U || brupdate.b2.mispredict)
&& rob.io.commit.rollback), "Can't have a mispredict during rollback.")
io.ifu.brupdate := brupdate
for (eu <- exe_units) {
eu.io.brupdate := brupdate
}
if (usingFPU) {
fp_pipeline.io.brupdate := brupdate
}
// Load/Store Unit & ExeUnits
val mem_units = exe_units.memory_units
val mem_resps = mem_units.map(_.io.ll_iresp)
for (i <- 0 until memWidth) {
mem_units(i).io.lsu_io <> io.lsu.exe(i)
}
//-------------------------------------------------------------
// Uarch Hardware Performance Events (HPEs)
val perfEvents = new freechips.rocketchip.rocket.EventSets(Seq(
new freechips.rocketchip.rocket.EventSet((mask, hits) => (mask & hits).orR, Seq(
("exception", () => rob.io.com_xcpt.valid),
("nop", () => false.B),
("nop", () => false.B),
("nop", () => false.B))),
new freechips.rocketchip.rocket.EventSet((mask, hits) => (mask & hits).orR, Seq(
// ("I$ blocked", () => icache_blocked),
("nop", () => false.B),
// ("branch misprediction", () => br_unit.brinfo.mispredict),
// ("control-flow target misprediction", () => br_unit.brinfo.mispredict &&
// br_unit.brinfo.cfi_type === CFI_JALR),
("flush", () => rob.io.flush.valid)
//("branch resolved", () => br_unit.brinfo.valid)
)),
new freechips.rocketchip.rocket.EventSet((mask, hits) => (mask & hits).orR, Seq(
("I$ miss", () => io.ifu.perf.acquire),
("D$ miss", () => io.lsu.perf.acquire),
("D$ release", () => io.lsu.perf.release),
("ITLB miss", () => io.ifu.perf.tlbMiss),
("DTLB miss", () => io.lsu.perf.tlbMiss),
("L2 TLB miss", () => io.ptw.perf.l2miss)))))
val csr = Module(new freechips.rocketchip.rocket.CSRFile(perfEvents, boomParams.customCSRs.decls))
csr.io.inst foreach { c => c := DontCare }
csr.io.rocc_interrupt := io.rocc.interrupt
val custom_csrs = Wire(new BoomCustomCSRs)
(custom_csrs.csrs zip csr.io.customCSRs).map { case (lhs, rhs) => lhs := rhs }
//val icache_blocked = !(io.ifu.fetchpacket.valid || RegNext(io.ifu.fetchpacket.valid))
val icache_blocked = false.B
csr.io.counters foreach { c => c.inc := RegNext(perfEvents.evaluate(c.eventSel)) }
//****************************************
// Time Stamp Counter & Retired Instruction Counter
// (only used for printf and vcd dumps - the actual counters are in the CSRFile)
val debug_tsc_reg = RegInit(0.U(xLen.W))
val debug_irt_reg = RegInit(0.U(xLen.W))
val debug_brs = Reg(Vec(4, UInt(xLen.W)))
val debug_jals = Reg(Vec(4, UInt(xLen.W)))
val debug_jalrs = Reg(Vec(4, UInt(xLen.W)))
for (j <- 0 until 4) {
debug_brs(j) := debug_brs(j) + PopCount(VecInit((0 until coreWidth) map {i =>
rob.io.commit.arch_valids(i) &&
(rob.io.commit.uops(i).debug_fsrc === j.U) &&
rob.io.commit.uops(i).is_br
}))
debug_jals(j) := debug_jals(j) + PopCount(VecInit((0 until coreWidth) map {i =>
rob.io.commit.arch_valids(i) &&
(rob.io.commit.uops(i).debug_fsrc === j.U) &&
rob.io.commit.uops(i).is_jal
}))
debug_jalrs(j) := debug_jalrs(j) + PopCount(VecInit((0 until coreWidth) map {i =>
rob.io.commit.arch_valids(i) &&
(rob.io.commit.uops(i).debug_fsrc === j.U) &&
rob.io.commit.uops(i).is_jalr
}))
}
dontTouch(debug_brs)
dontTouch(debug_jals)
dontTouch(debug_jalrs)
debug_tsc_reg := debug_tsc_reg + 1.U
debug_irt_reg := debug_irt_reg + PopCount(rob.io.commit.arch_valids.asUInt)
dontTouch(debug_tsc_reg)
dontTouch(debug_irt_reg)
//****************************************
// Print-out information about the machine
val issStr =
if (enableAgePriorityIssue) " (Age-based Priority)"
else " (Unordered Priority)"
// val btbStr =
// if (enableBTB) ("" + boomParams.btb.nSets * boomParams.btb.nWays + " entries (" + boomParams.btb.nSets + " x " + boomParams.btb.nWays + " ways)")
// else 0
val btbStr = ""
val fpPipelineStr =
if (usingFPU) fp_pipeline.toString
else ""
override def toString: String =
(BoomCoreStringPrefix("====Overall Core Params====") + "\n"
+ exe_units.toString + "\n"
+ fpPipelineStr + "\n"
+ rob.toString + "\n"
+ BoomCoreStringPrefix(
"===Other Core Params===",
"Fetch Width : " + fetchWidth,
"Decode Width : " + coreWidth,
"Issue Width : " + issueParams.map(_.issueWidth).sum,
"ROB Size : " + numRobEntries,
"Issue Window Size : " + issueParams.map(_.numEntries) + issStr,
"Load/Store Unit Size : " + numLdqEntries + "/" + numStqEntries,
"Num Int Phys Registers: " + numIntPhysRegs,
"Num FP Phys Registers: " + numFpPhysRegs,
"Max Branch Count : " + maxBrCount)
+ iregfile.toString + "\n"
+ BoomCoreStringPrefix(
"Num Slow Wakeup Ports : " + numIrfWritePorts,
"Num Fast Wakeup Ports : " + exe_units.count(_.bypassable),
"Num Bypass Ports : " + exe_units.numTotalBypassPorts) + "\n"
+ BoomCoreStringPrefix(
"DCache Ways : " + dcacheParams.nWays,
"DCache Sets : " + dcacheParams.nSets,
"DCache nMSHRs : " + dcacheParams.nMSHRs,
"ICache Ways : " + icacheParams.nWays,
"ICache Sets : " + icacheParams.nSets,
"D-TLB Ways : " + dcacheParams.nTLBWays,
"I-TLB Ways : " + icacheParams.nTLBWays,
"Paddr Bits : " + paddrBits,
"Vaddr Bits : " + vaddrBits) + "\n"
+ BoomCoreStringPrefix(
"Using FPU Unit? : " + usingFPU.toString,
"Using FDivSqrt? : " + usingFDivSqrt.toString,
"Using VM? : " + usingVM.toString) + "\n")
//-------------------------------------------------------------
//-------------------------------------------------------------
// **** Fetch Stage/Frontend ****
//-------------------------------------------------------------
//-------------------------------------------------------------
io.ifu.redirect_val := false.B
io.ifu.redirect_flush := false.B
// Breakpoint info
io.ifu.status := csr.io.status
io.ifu.bp := csr.io.bp
io.ifu.mcontext := csr.io.mcontext
io.ifu.scontext := csr.io.scontext
io.ifu.flush_icache := (0 until coreWidth).map { i =>
(rob.io.commit.arch_valids(i) && rob.io.commit.uops(i).is_fencei) ||
(RegNext(dec_valids(i) && dec_uops(i).is_jalr && csr.io.status.debug))
}.reduce(_||_)
// TODO FIX THIS HACK
// The below code works because of two quirks with the flush mechanism
// 1 ) All flush_on_commit instructions are also is_unique,
// In the future, this constraint will be relaxed.
// 2 ) We send out flush signals one cycle after the commit signal. We need to
// mux between one/two cycle delay for the following cases:
// ERETs are reported to the CSR two cycles before we send the flush
// Exceptions are reported to the CSR on the cycle we send the flush
// This discrepency should be resolved elsewhere.
when (RegNext(rob.io.flush.valid)) {
io.ifu.redirect_val := true.B
io.ifu.redirect_flush := true.B
val flush_typ = RegNext(rob.io.flush.bits.flush_typ)
// Clear the global history when we flush the ROB (exceptions, AMOs, unique instructions, etc.)
val new_ghist = WireInit((0.U).asTypeOf(new GlobalHistory))
new_ghist.current_saw_branch_not_taken := true.B
new_ghist.ras_idx := io.ifu.get_pc(0).entry.ras_idx
io.ifu.redirect_ghist := new_ghist
when (FlushTypes.useCsrEvec(flush_typ)) {
io.ifu.redirect_pc := Mux(flush_typ === FlushTypes.eret,
RegNext(RegNext(csr.io.evec)),
csr.io.evec)
} .otherwise {
val flush_pc = (AlignPCToBoundary(io.ifu.get_pc(0).pc, icBlockBytes)
+ RegNext(rob.io.flush.bits.pc_lob)
- Mux(RegNext(rob.io.flush.bits.edge_inst), 2.U, 0.U))
val flush_pc_next = flush_pc + Mux(RegNext(rob.io.flush.bits.is_rvc), 2.U, 4.U)
io.ifu.redirect_pc := Mux(FlushTypes.useSamePC(flush_typ),
flush_pc, flush_pc_next)
}
io.ifu.redirect_ftq_idx := RegNext(rob.io.flush.bits.ftq_idx)
} .elsewhen (brupdate.b2.mispredict && !RegNext(rob.io.flush.valid)) {
val block_pc = AlignPCToBoundary(io.ifu.get_pc(1).pc, icBlockBytes)
val uop_maybe_pc = block_pc | brupdate.b2.uop.pc_lob
val npc = uop_maybe_pc + Mux(brupdate.b2.uop.is_rvc || brupdate.b2.uop.edge_inst, 2.U, 4.U)
val jal_br_target = Wire(UInt(vaddrBitsExtended.W))
jal_br_target := (uop_maybe_pc.asSInt + brupdate.b2.target_offset +
(Fill(vaddrBitsExtended-1, brupdate.b2.uop.edge_inst) << 1).asSInt).asUInt
val bj_addr = Mux(brupdate.b2.cfi_type === CFI_JALR, brupdate.b2.jalr_target, jal_br_target)
val mispredict_target = Mux(brupdate.b2.pc_sel === PC_PLUS4, npc, bj_addr)
io.ifu.redirect_val := true.B
io.ifu.redirect_pc := mispredict_target
io.ifu.redirect_flush := true.B
io.ifu.redirect_ftq_idx := brupdate.b2.uop.ftq_idx
val use_same_ghist = (brupdate.b2.cfi_type === CFI_BR &&
!brupdate.b2.taken &&
bankAlign(block_pc) === bankAlign(npc))
val ftq_entry = io.ifu.get_pc(1).entry
val cfi_idx = (brupdate.b2.uop.pc_lob ^
Mux(ftq_entry.start_bank === 1.U, 1.U << log2Ceil(bankBytes), 0.U))(log2Ceil(fetchWidth), 1)
val ftq_ghist = io.ifu.get_pc(1).ghist
val next_ghist = ftq_ghist.update(
ftq_entry.br_mask.asUInt,
brupdate.b2.taken,
brupdate.b2.cfi_type === CFI_BR,
cfi_idx,
true.B,
io.ifu.get_pc(1).pc,
ftq_entry.cfi_is_call && ftq_entry.cfi_idx.bits === cfi_idx,
ftq_entry.cfi_is_ret && ftq_entry.cfi_idx.bits === cfi_idx)
io.ifu.redirect_ghist := Mux(
use_same_ghist,
ftq_ghist,
next_ghist)
io.ifu.redirect_ghist.current_saw_branch_not_taken := use_same_ghist
} .elsewhen (rob.io.flush_frontend || brupdate.b1.mispredict_mask =/= 0.U) {
io.ifu.redirect_flush := true.B
}
// Tell the FTQ it can deallocate entries by passing youngest ftq_idx.
val youngest_com_idx = (coreWidth-1).U - PriorityEncoder(rob.io.commit.valids.reverse)
io.ifu.commit.valid := rob.io.commit.valids.reduce(_|_) || rob.io.com_xcpt.valid
io.ifu.commit.bits := Mux(rob.io.com_xcpt.valid,
rob.io.com_xcpt.bits.ftq_idx,
rob.io.commit.uops(youngest_com_idx).ftq_idx)
assert(!(rob.io.commit.valids.reduce(_|_) && rob.io.com_xcpt.valid),
"ROB can't commit and except in same cycle!")
for (i <- 0 until memWidth) {
when (RegNext(io.lsu.exe(i).req.bits.sfence.valid)) {
io.ifu.sfence := RegNext(io.lsu.exe(i).req.bits.sfence)
}
}
//-------------------------------------------------------------
//-------------------------------------------------------------
// **** Branch Prediction ****
//-------------------------------------------------------------
//-------------------------------------------------------------
//-------------------------------------------------------------
//-------------------------------------------------------------
// **** Decode Stage ****
//-------------------------------------------------------------
//-------------------------------------------------------------
// track mask of finished instructions in the bundle
// use this to mask out insts coming from FetchBuffer that have been finished
// for example, back pressure may cause us to only issue some instructions from FetchBuffer
// but on the next cycle, we only want to retry a subset
val dec_finished_mask = RegInit(0.U(coreWidth.W))
//-------------------------------------------------------------
// Pull out instructions and send to the Decoders
io.ifu.fetchpacket.ready := dec_ready
val dec_fbundle = io.ifu.fetchpacket.bits
//-------------------------------------------------------------
// Decoders
for (w <- 0 until coreWidth) {
dec_valids(w) := io.ifu.fetchpacket.valid && dec_fbundle.uops(w).valid &&
!dec_finished_mask(w)
decode_units(w).io.enq.uop := dec_fbundle.uops(w).bits
decode_units(w).io.status := csr.io.status
decode_units(w).io.csr_decode <> csr.io.decode(w)
decode_units(w).io.interrupt := csr.io.interrupt
decode_units(w).io.interrupt_cause := csr.io.interrupt_cause
dec_uops(w) := decode_units(w).io.deq.uop
}
//-------------------------------------------------------------
// FTQ GetPC Port Arbitration
val jmp_pc_req = Wire(Decoupled(UInt(log2Ceil(ftqSz).W)))
val xcpt_pc_req = Wire(Decoupled(UInt(log2Ceil(ftqSz).W)))
val flush_pc_req = Wire(Decoupled(UInt(log2Ceil(ftqSz).W)))
val ftq_arb = Module(new Arbiter(UInt(log2Ceil(ftqSz).W), 3))
// Order by the oldest. Flushes come from the oldest instructions in pipe
// Decoding exceptions come from youngest
ftq_arb.io.in(0) <> flush_pc_req
ftq_arb.io.in(1) <> jmp_pc_req
ftq_arb.io.in(2) <> xcpt_pc_req
// Hookup FTQ
io.ifu.get_pc(0).ftq_idx := ftq_arb.io.out.bits
ftq_arb.io.out.ready := true.B
// Branch Unit Requests (for JALs) (Should delay issue of JALs if this not ready)
jmp_pc_req.valid := RegNext(iss_valids(jmp_unit_idx) && iss_uops(jmp_unit_idx).fu_code === FU_JMP)
jmp_pc_req.bits := RegNext(iss_uops(jmp_unit_idx).ftq_idx)
jmp_unit.io.get_ftq_pc := DontCare
jmp_unit.io.get_ftq_pc.pc := io.ifu.get_pc(0).pc
jmp_unit.io.get_ftq_pc.entry := io.ifu.get_pc(0).entry
jmp_unit.io.get_ftq_pc.next_val := io.ifu.get_pc(0).next_val
jmp_unit.io.get_ftq_pc.next_pc := io.ifu.get_pc(0).next_pc
// Frontend Exception Requests
val xcpt_idx = PriorityEncoder(dec_xcpts)
xcpt_pc_req.valid := dec_xcpts.reduce(_||_)
xcpt_pc_req.bits := dec_uops(xcpt_idx).ftq_idx
//rob.io.xcpt_fetch_pc := RegEnable(io.ifu.get_pc.fetch_pc, dis_ready)
rob.io.xcpt_fetch_pc := io.ifu.get_pc(0).pc
flush_pc_req.valid := rob.io.flush.valid
flush_pc_req.bits := rob.io.flush.bits.ftq_idx
// Mispredict requests (to get the correct target)
io.ifu.get_pc(1).ftq_idx := oldest_mispredict_ftq_idx
//-------------------------------------------------------------
// Decode/Rename1 pipeline logic
dec_xcpts := dec_uops zip dec_valids map {case (u,v) => u.exception && v}
val dec_xcpt_stall = dec_xcpts.reduce(_||_) && !xcpt_pc_req.ready
// stall fetch/dcode because we ran out of branch tags
val branch_mask_full = Wire(Vec(coreWidth, Bool()))
val dec_hazards = (0 until coreWidth).map(w =>
dec_valids(w) &&
( !dis_ready
|| rob.io.commit.rollback
|| dec_xcpt_stall
|| branch_mask_full(w)
|| brupdate.b1.mispredict_mask =/= 0.U
|| brupdate.b2.mispredict
|| io.ifu.redirect_flush))
val dec_stalls = dec_hazards.scanLeft(false.B) ((s,h) => s || h).takeRight(coreWidth)
dec_fire := (0 until coreWidth).map(w => dec_valids(w) && !dec_stalls(w))
// all decoders are empty and ready for new instructions
dec_ready := dec_fire.last
when (dec_ready || io.ifu.redirect_flush) {
dec_finished_mask := 0.U
} .otherwise {
dec_finished_mask := dec_fire.asUInt | dec_finished_mask
}
//-------------------------------------------------------------
// Branch Mask Logic
dec_brmask_logic.io.brupdate := brupdate
dec_brmask_logic.io.flush_pipeline := RegNext(rob.io.flush.valid)
for (w <- 0 until coreWidth) {
dec_brmask_logic.io.is_branch(w) := !dec_finished_mask(w) && dec_uops(w).allocate_brtag
dec_brmask_logic.io.will_fire(w) := dec_fire(w) &&
dec_uops(w).allocate_brtag // ren, dis can back pressure us
dec_uops(w).br_tag := dec_brmask_logic.io.br_tag(w)
dec_uops(w).br_mask := dec_brmask_logic.io.br_mask(w)
}
branch_mask_full := dec_brmask_logic.io.is_full
//-------------------------------------------------------------
//-------------------------------------------------------------
// **** Register Rename Stage ****
//-------------------------------------------------------------
//-------------------------------------------------------------
// Inputs
for (rename <- rename_stages) {
rename.io.kill := io.ifu.redirect_flush
rename.io.brupdate := brupdate
rename.io.debug_rob_empty := rob.io.empty
rename.io.dec_fire := dec_fire
rename.io.dec_uops := dec_uops
rename.io.dis_fire := dis_fire
rename.io.dis_ready := dis_ready
rename.io.com_valids := rob.io.commit.valids
rename.io.com_uops := rob.io.commit.uops
rename.io.rbk_valids := rob.io.commit.rbk_valids
rename.io.rollback := rob.io.commit.rollback
}
// Outputs
dis_uops := rename_stage.io.ren2_uops
dis_valids := rename_stage.io.ren2_mask
ren_stalls := rename_stage.io.ren_stalls
/**
* TODO This is a bit nasty, but it's currently necessary to
* split the INT/FP rename pipelines into separate instantiations.
* Won't have to do this anymore with a properly decoupled FP pipeline.
*/
for (w <- 0 until coreWidth) {
val i_uop = rename_stage.io.ren2_uops(w)
val f_uop = if (usingFPU) fp_rename_stage.io.ren2_uops(w) else NullMicroOp
val p_uop = if (enableSFBOpt) pred_rename_stage.io.ren2_uops(w) else NullMicroOp
val f_stall = if (usingFPU) fp_rename_stage.io.ren_stalls(w) else false.B
val p_stall = if (enableSFBOpt) pred_rename_stage.io.ren_stalls(w) else false.B
// lrs1 can "pass through" to prs1. Used solely to index the csr file.
dis_uops(w).prs1 := Mux(dis_uops(w).lrs1_rtype === RT_FLT, f_uop.prs1,
Mux(dis_uops(w).lrs1_rtype === RT_FIX, i_uop.prs1, dis_uops(w).lrs1))
dis_uops(w).prs2 := Mux(dis_uops(w).lrs2_rtype === RT_FLT, f_uop.prs2, i_uop.prs2)
dis_uops(w).prs3 := f_uop.prs3
dis_uops(w).ppred := p_uop.ppred
dis_uops(w).pdst := Mux(dis_uops(w).dst_rtype === RT_FLT, f_uop.pdst,
Mux(dis_uops(w).dst_rtype === RT_FIX, i_uop.pdst,
p_uop.pdst))
dis_uops(w).stale_pdst := Mux(dis_uops(w).dst_rtype === RT_FLT, f_uop.stale_pdst, i_uop.stale_pdst)
dis_uops(w).prs1_busy := i_uop.prs1_busy && (dis_uops(w).lrs1_rtype === RT_FIX) ||
f_uop.prs1_busy && (dis_uops(w).lrs1_rtype === RT_FLT)
dis_uops(w).prs2_busy := i_uop.prs2_busy && (dis_uops(w).lrs2_rtype === RT_FIX) ||
f_uop.prs2_busy && (dis_uops(w).lrs2_rtype === RT_FLT)
dis_uops(w).prs3_busy := f_uop.prs3_busy && dis_uops(w).frs3_en
dis_uops(w).ppred_busy := p_uop.ppred_busy && dis_uops(w).is_sfb_shadow
ren_stalls(w) := rename_stage.io.ren_stalls(w) || f_stall || p_stall
}
//-------------------------------------------------------------
//-------------------------------------------------------------
// **** Dispatch Stage ****
//-------------------------------------------------------------
//-------------------------------------------------------------
//-------------------------------------------------------------
// Rename2/Dispatch pipeline logic
val dis_prior_slot_valid = dis_valids.scanLeft(false.B) ((s,v) => s || v)
val dis_prior_slot_unique = (dis_uops zip dis_valids).scanLeft(false.B) {case (s,(u,v)) => s || v && u.is_unique}
val wait_for_empty_pipeline = (0 until coreWidth).map(w => (dis_uops(w).is_unique || custom_csrs.disableOOO) &&
(!rob.io.empty || !io.lsu.fencei_rdy || dis_prior_slot_valid(w)))
val rocc_shim_busy = if (usingRoCC) !exe_units.rocc_unit.io.rocc.rxq_empty else false.B
val wait_for_rocc = (0 until coreWidth).map(w =>
(dis_uops(w).is_fence || dis_uops(w).is_fencei) && (io.rocc.busy || rocc_shim_busy))
val rxq_full = if (usingRoCC) exe_units.rocc_unit.io.rocc.rxq_full else false.B
val block_rocc = (dis_uops zip dis_valids).map{case (u,v) => v && u.uopc === uopROCC}.scanLeft(rxq_full)(_||_)
val dis_rocc_alloc_stall = (dis_uops.map(_.uopc === uopROCC) zip block_rocc) map {case (p,r) =>
if (usingRoCC) p && r else false.B}
val dis_hazards = (0 until coreWidth).map(w =>
dis_valids(w) &&
( !rob.io.ready
|| ren_stalls(w)
|| io.lsu.ldq_full(w) && dis_uops(w).uses_ldq
|| io.lsu.stq_full(w) && dis_uops(w).uses_stq
|| !dispatcher.io.ren_uops(w).ready
|| wait_for_empty_pipeline(w)
|| wait_for_rocc(w)
|| dis_prior_slot_unique(w)
|| dis_rocc_alloc_stall(w)
|| brupdate.b1.mispredict_mask =/= 0.U
|| brupdate.b2.mispredict
|| io.ifu.redirect_flush))
io.lsu.fence_dmem := (dis_valids zip wait_for_empty_pipeline).map {case (v,w) => v && w} .reduce(_||_)
val dis_stalls = dis_hazards.scanLeft(false.B) ((s,h) => s || h).takeRight(coreWidth)
dis_fire := dis_valids zip dis_stalls map {case (v,s) => v && !s}
dis_ready := !dis_stalls.last
//-------------------------------------------------------------
// LDQ/STQ Allocation Logic
for (w <- 0 until coreWidth) {
// Dispatching instructions request load/store queue entries when they can proceed.
dis_uops(w).ldq_idx := io.lsu.dis_ldq_idx(w)
dis_uops(w).stq_idx := io.lsu.dis_stq_idx(w)
}
//-------------------------------------------------------------
// Rob Allocation Logic
rob.io.enq_valids := dis_fire
rob.io.enq_uops := dis_uops
rob.io.enq_partial_stall := dis_stalls.last // TODO come up with better ROB compacting scheme.
rob.io.debug_tsc := debug_tsc_reg
rob.io.csr_stall := csr.io.csr_stall
// Minor hack: ecall and breaks need to increment the FTQ deq ptr earlier than commit, since
// they write their PC into the CSR the cycle before they commit.
// Since these are also unique, increment the FTQ ptr when they are dispatched
when (RegNext(dis_fire.reduce(_||_) && dis_uops(PriorityEncoder(dis_fire)).is_sys_pc2epc)) {
io.ifu.commit.valid := true.B
io.ifu.commit.bits := RegNext(dis_uops(PriorityEncoder(dis_valids)).ftq_idx)
}
for (w <- 0 until coreWidth) {
// note: this assumes uops haven't been shifted - there's a 1:1 match between PC's LSBs and "w" here
// (thus the LSB of the rob_idx gives part of the PC)
if (coreWidth == 1) {
dis_uops(w).rob_idx := rob.io.rob_tail_idx
} else {
dis_uops(w).rob_idx := Cat(rob.io.rob_tail_idx >> log2Ceil(coreWidth).U,
w.U(log2Ceil(coreWidth).W))
}
}
//-------------------------------------------------------------
// RoCC allocation logic
if (usingRoCC) {
for (w <- 0 until coreWidth) {
// We guarantee only decoding 1 RoCC instruction per cycle
dis_uops(w).rxq_idx := exe_units.rocc_unit.io.rocc.rxq_idx(w)
}
}
//-------------------------------------------------------------
// Dispatch to issue queues
// Get uops from rename2
for (w <- 0 until coreWidth) {
dispatcher.io.ren_uops(w).valid := dis_fire(w)
dispatcher.io.ren_uops(w).bits := dis_uops(w)
}
var iu_idx = 0
// Send dispatched uops to correct issue queues
// Backpressure through dispatcher if necessary
for (i <- 0 until issueParams.size) {
if (issueParams(i).iqType == IQT_FP.litValue) {
fp_pipeline.io.dis_uops <> dispatcher.io.dis_uops(i)
} else {
issue_units(iu_idx).io.dis_uops <> dispatcher.io.dis_uops(i)
iu_idx += 1
}
}
//-------------------------------------------------------------
//-------------------------------------------------------------
// **** Issue Stage ****
//-------------------------------------------------------------
//-------------------------------------------------------------
require (issue_units.map(_.issueWidth).sum == exe_units.length)
var iss_wu_idx = 1
var ren_wu_idx = 1
// The 0th wakeup port goes to the ll_wbarb
int_iss_wakeups(0).valid := ll_wbarb.io.out.fire && ll_wbarb.io.out.bits.uop.dst_rtype === RT_FIX
int_iss_wakeups(0).bits := ll_wbarb.io.out.bits
int_ren_wakeups(0).valid := ll_wbarb.io.out.fire && ll_wbarb.io.out.bits.uop.dst_rtype === RT_FIX
int_ren_wakeups(0).bits := ll_wbarb.io.out.bits
for (i <- 1 until memWidth) {
int_iss_wakeups(i).valid := mem_resps(i).valid && mem_resps(i).bits.uop.dst_rtype === RT_FIX
int_iss_wakeups(i).bits := mem_resps(i).bits
int_ren_wakeups(i).valid := mem_resps(i).valid && mem_resps(i).bits.uop.dst_rtype === RT_FIX
int_ren_wakeups(i).bits := mem_resps(i).bits
iss_wu_idx += 1
ren_wu_idx += 1
}
// loop through each issue-port (exe_units are statically connected to an issue-port)
for (i <- 0 until exe_units.length) {
if (exe_units(i).writesIrf) {
val fast_wakeup = Wire(Valid(new ExeUnitResp(xLen)))
val slow_wakeup = Wire(Valid(new ExeUnitResp(xLen)))
fast_wakeup := DontCare
slow_wakeup := DontCare
val resp = exe_units(i).io.iresp
assert(!(resp.valid && resp.bits.uop.rf_wen && resp.bits.uop.dst_rtype =/= RT_FIX))
// Fast Wakeup (uses just-issued uops that have known latencies)
fast_wakeup.bits.uop := iss_uops(i)
fast_wakeup.valid := iss_valids(i) &&
iss_uops(i).bypassable &&
iss_uops(i).dst_rtype === RT_FIX &&
iss_uops(i).ldst_val &&
!(io.lsu.ld_miss && (iss_uops(i).iw_p1_poisoned || iss_uops(i).iw_p2_poisoned))
// Slow Wakeup (uses write-port to register file)
slow_wakeup.bits.uop := resp.bits.uop
slow_wakeup.valid := resp.valid &&
resp.bits.uop.rf_wen &&
!resp.bits.uop.bypassable &&
resp.bits.uop.dst_rtype === RT_FIX
if (exe_units(i).bypassable) {
int_iss_wakeups(iss_wu_idx) := fast_wakeup
iss_wu_idx += 1
}
if (!exe_units(i).alwaysBypassable) {
int_iss_wakeups(iss_wu_idx) := slow_wakeup
iss_wu_idx += 1
}
if (exe_units(i).bypassable) {
int_ren_wakeups(ren_wu_idx) := fast_wakeup
ren_wu_idx += 1
}
if (!exe_units(i).alwaysBypassable) {
int_ren_wakeups(ren_wu_idx) := slow_wakeup
ren_wu_idx += 1
}
}
}
require (iss_wu_idx == numIntIssueWakeupPorts)
require (ren_wu_idx == numIntRenameWakeupPorts)
require (iss_wu_idx == ren_wu_idx)
// jmp unit performs fast wakeup of the predicate bits
require (jmp_unit.bypassable)
pred_wakeup.valid := (iss_valids(jmp_unit_idx) &&
iss_uops(jmp_unit_idx).is_sfb_br &&
!(io.lsu.ld_miss && (iss_uops(jmp_unit_idx).iw_p1_poisoned || iss_uops(jmp_unit_idx).iw_p2_poisoned))
)
pred_wakeup.bits.uop := iss_uops(jmp_unit_idx)
pred_wakeup.bits.fflags := DontCare
pred_wakeup.bits.data := DontCare
pred_wakeup.bits.predicated := DontCare
// Perform load-hit speculative wakeup through a special port (performs a poison wake-up).
issue_units map { iu =>
iu.io.spec_ld_wakeup := io.lsu.spec_ld_wakeup
}
// Connect the predicate wakeup port
issue_units map { iu =>
iu.io.pred_wakeup_port.valid := false.B
iu.io.pred_wakeup_port.bits := DontCare
}
if (enableSFBOpt) {
int_iss_unit.io.pred_wakeup_port.valid := pred_wakeup.valid
int_iss_unit.io.pred_wakeup_port.bits := pred_wakeup.bits.uop.pdst
}
// ----------------------------------------------------------------
// Connect the wakeup ports to the busy tables in the rename stages
for ((renport, intport) <- rename_stage.io.wakeups zip int_ren_wakeups) {
renport <> intport
}
if (usingFPU) {
for ((renport, fpport) <- fp_rename_stage.io.wakeups zip fp_pipeline.io.wakeups) {
renport <> fpport
}
}
if (enableSFBOpt) {
pred_rename_stage.io.wakeups(0) := pred_wakeup
} else {
pred_rename_stage.io.wakeups := DontCare
}
// If we issue loads back-to-back endlessly (probably because we are executing some tight loop)
// the store buffer will never drain, breaking the memory-model forward-progress guarantee
// If we see a large number of loads saturate the LSU, pause for a cycle to let a store drain
val loads_saturating = (mem_iss_unit.io.iss_valids(0) && mem_iss_unit.io.iss_uops(0).uses_ldq)
val saturating_loads_counter = RegInit(0.U(5.W))
when (loads_saturating) { saturating_loads_counter := saturating_loads_counter + 1.U }
.otherwise { saturating_loads_counter := 0.U }
val pause_mem = RegNext(loads_saturating) && saturating_loads_counter === ~(0.U(5.W))
var iss_idx = 0
var int_iss_cnt = 0
var mem_iss_cnt = 0
for (w <- 0 until exe_units.length) {
var fu_types = exe_units(w).io.fu_types
val exe_unit = exe_units(w)
if (exe_unit.readsIrf) {
if (exe_unit.supportedFuncUnits.muld) {
// Supress just-issued divides from issuing back-to-back, since it's an iterative divider.
// But it takes a cycle to get to the Exe stage, so it can't tell us it is busy yet.
val idiv_issued = iss_valids(iss_idx) && iss_uops(iss_idx).fu_code_is(FU_DIV)
fu_types = fu_types & RegNext(~Mux(idiv_issued, FU_DIV, 0.U))
}
if (exe_unit.hasMem) {
iss_valids(iss_idx) := mem_iss_unit.io.iss_valids(mem_iss_cnt)
iss_uops(iss_idx) := mem_iss_unit.io.iss_uops(mem_iss_cnt)
mem_iss_unit.io.fu_types(mem_iss_cnt) := Mux(pause_mem, 0.U, fu_types)
mem_iss_cnt += 1
} else {
iss_valids(iss_idx) := int_iss_unit.io.iss_valids(int_iss_cnt)
iss_uops(iss_idx) := int_iss_unit.io.iss_uops(int_iss_cnt)
int_iss_unit.io.fu_types(int_iss_cnt) := fu_types
int_iss_cnt += 1
}
iss_idx += 1
}
}
require(iss_idx == exe_units.numIrfReaders)
issue_units.map(_.io.tsc_reg := debug_tsc_reg)
issue_units.map(_.io.brupdate := brupdate)
issue_units.map(_.io.flush_pipeline := RegNext(rob.io.flush.valid))
// Load-hit Misspeculations
require (mem_iss_unit.issueWidth <= 2)
issue_units.map(_.io.ld_miss := io.lsu.ld_miss)
mem_units.map(u => u.io.com_exception := RegNext(rob.io.flush.valid))
// Wakeup (Issue & Writeback)
for {
iu <- issue_units
(issport, wakeup) <- iu.io.wakeup_ports zip int_iss_wakeups
}{
issport.valid := wakeup.valid
issport.bits.pdst := wakeup.bits.uop.pdst
issport.bits.poisoned := wakeup.bits.uop.iw_p1_poisoned || wakeup.bits.uop.iw_p2_poisoned
require (iu.io.wakeup_ports.length == int_iss_wakeups.length)
}
//-------------------------------------------------------------
//-------------------------------------------------------------
// **** Register Read Stage ****
//-------------------------------------------------------------
//-------------------------------------------------------------
// Register Read <- Issue (rrd <- iss)
iregister_read.io.rf_read_ports <> iregfile.io.read_ports
iregister_read.io.prf_read_ports := DontCare
if (enableSFBOpt) {
iregister_read.io.prf_read_ports <> pregfile.io.read_ports
}
for (w <- 0 until exe_units.numIrfReaders) {
iregister_read.io.iss_valids(w) :=
iss_valids(w) && !(io.lsu.ld_miss && (iss_uops(w).iw_p1_poisoned || iss_uops(w).iw_p2_poisoned))
}
iregister_read.io.iss_uops := iss_uops
iregister_read.io.iss_uops map { u => u.iw_p1_poisoned := false.B; u.iw_p2_poisoned := false.B }
iregister_read.io.brupdate := brupdate
iregister_read.io.kill := RegNext(rob.io.flush.valid)
iregister_read.io.bypass := bypasses
iregister_read.io.pred_bypass := pred_bypasses
//-------------------------------------------------------------
// Privileged Co-processor 0 Register File
// Note: Normally this would be bad in that I'm writing state before
// committing, so to get this to work I stall the entire pipeline for
// CSR instructions so I never speculate these instructions.
val csr_exe_unit = exe_units.csr_unit
// for critical path reasons, we aren't zero'ing this out if resp is not valid
val csr_rw_cmd = csr_exe_unit.io.iresp.bits.uop.ctrl.csr_cmd
val wb_wdata = csr_exe_unit.io.iresp.bits.data
csr.io.rw.addr := csr_exe_unit.io.iresp.bits.uop.csr_addr
csr.io.rw.cmd := freechips.rocketchip.rocket.CSR.maskCmd(csr_exe_unit.io.iresp.valid, csr_rw_cmd)
csr.io.rw.wdata := wb_wdata