From 7df2bc455c7fd5f501afc0e1157e3663d50b83a5 Mon Sep 17 00:00:00 2001 From: napowderly Date: Sun, 18 Feb 2024 22:40:06 -0800 Subject: [PATCH 01/10] adding half bridge to generics --- mosfets.ato | 37 +++++++++++++++++++++++++++++++++---- 1 file changed, 33 insertions(+), 4 deletions(-) diff --git a/mosfets.ato b/mosfets.ato index 4fb3810..2a2789b 100644 --- a/mosfets.ato +++ b/mosfets.ato @@ -1,7 +1,9 @@ -import Power from "generics/interfaces.ato" -import Load from "generics/interfaces.ato" -import Resistor from "generics/interfaces.ato" -import Diode from "generics/diodes.ato" +import Power from "interfaces.ato" +import Pair from "interfaces.ato" +import DiffPair from "interfaces.ato" +import Load from "interfaces.ato" +import Resistor from "interfaces.ato" +import Diode from "diodes.ato" component NFET: signal gate @@ -21,6 +23,33 @@ component PFET: type = "mosfet" polarity = "P Channel" +module HalfBridge: + power = new Power + gate_high = new Pair + gate_low = new Pair + shunt_output = new DiffPair + output = new Pair + + # Components + nfet_high = new NFET + nfet_low = new NFET + shunt = new Resistor + + # Connect power + power.vcc ~ nfet_high.drain + output ~ nfe_high.source + output ~ nfet_low.drain + power.gnd ~ shunt.2; shunt.1 ~ nfet_high.source + + # Connect the gates + gate_high.io ~ nfet_high.gate + gate_low.io ~ nfet_low.gate + + # Connect the gnds + output.gnd ~ power.gnd + gate_high.gnd ~ power.gnd + gate_low.gnd ~ power.gnd + module LowSideSwitch: fet = new Mosfet_nchannel gate_resistor = new Resistor From db8be8bbc22b714756bb50b27ce04174191685a2 Mon Sep 17 00:00:00 2001 From: napowderly Date: Sun, 18 Feb 2024 22:42:34 -0800 Subject: [PATCH 02/10] half bridge to generics --- mosfets.ato | 37 +++++++++++++++++++++++++++++++++---- 1 file changed, 33 insertions(+), 4 deletions(-) diff --git a/mosfets.ato b/mosfets.ato index 4fb3810..2a2789b 100644 --- a/mosfets.ato +++ b/mosfets.ato @@ -1,7 +1,9 @@ -import Power from "generics/interfaces.ato" -import Load from "generics/interfaces.ato" -import Resistor from "generics/interfaces.ato" -import Diode from "generics/diodes.ato" +import Power from "interfaces.ato" +import Pair from "interfaces.ato" +import DiffPair from "interfaces.ato" +import Load from "interfaces.ato" +import Resistor from "interfaces.ato" +import Diode from "diodes.ato" component NFET: signal gate @@ -21,6 +23,33 @@ component PFET: type = "mosfet" polarity = "P Channel" +module HalfBridge: + power = new Power + gate_high = new Pair + gate_low = new Pair + shunt_output = new DiffPair + output = new Pair + + # Components + nfet_high = new NFET + nfet_low = new NFET + shunt = new Resistor + + # Connect power + power.vcc ~ nfet_high.drain + output ~ nfe_high.source + output ~ nfet_low.drain + power.gnd ~ shunt.2; shunt.1 ~ nfet_high.source + + # Connect the gates + gate_high.io ~ nfet_high.gate + gate_low.io ~ nfet_low.gate + + # Connect the gnds + output.gnd ~ power.gnd + gate_high.gnd ~ power.gnd + gate_low.gnd ~ power.gnd + module LowSideSwitch: fet = new Mosfet_nchannel gate_resistor = new Resistor From 3dcad315470d6e18dc7d3e2c5718e48966f26107 Mon Sep 17 00:00:00 2001 From: napowderly Date: Sun, 18 Feb 2024 22:44:12 -0800 Subject: [PATCH 03/10] fix import --- mosfets.ato | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mosfets.ato b/mosfets.ato index 2a2789b..5777e0a 100644 --- a/mosfets.ato +++ b/mosfets.ato @@ -2,7 +2,7 @@ import Power from "interfaces.ato" import Pair from "interfaces.ato" import DiffPair from "interfaces.ato" import Load from "interfaces.ato" -import Resistor from "interfaces.ato" +import Resistor from "resistors.ato" import Diode from "diodes.ato" component NFET: From 8364b08bd69bf13b0eec7023eb89a570cc3c7d5f Mon Sep 17 00:00:00 2001 From: napowderly Date: Tue, 20 Feb 2024 14:56:46 -0800 Subject: [PATCH 04/10] fix opamps --- opamps.ato | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/opamps.ato b/opamps.ato index 5069e8e..1d6a065 100644 --- a/opamps.ato +++ b/opamps.ato @@ -1,7 +1,7 @@ component Opamp: power = new Power - signal inverting_input - signal noninverting_input + signal inverting + signal noninverting signal output designator_prefix = "U" @@ -19,7 +19,7 @@ module VoltageFollower: opamp.inverting_input ~ opamp.output output ~ opamp.output -import vdiv from "StandardCircuits.ato" +# import vdiv from "StandardCircuits.ato" module Amplifier: power = new Power opamp = new Opamp @@ -28,7 +28,7 @@ module Amplifier: power ~ opamp.power # TODO: add equation for gain - gain = unknown\ + gain = unknown vdiv.r_top.value = unknown vdiv.r_bottom.value = unknown From a44fb6c25e29a465a908ee615e37e41a6327d618 Mon Sep 17 00:00:00 2001 From: Timothee Peter Date: Wed, 21 Feb 2024 00:33:53 +0000 Subject: [PATCH 05/10] Add I2S --- interfaces.ato | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/interfaces.ato b/interfaces.ato index c0129aa..762dae8 100644 --- a/interfaces.ato +++ b/interfaces.ato @@ -131,4 +131,10 @@ interface Pair: interface Analog: signal io - signal gnd \ No newline at end of file + signal gnd + +interface I2S: + signal ws + signal sck + signal sd + signal gnd From 1b2bab01c4ee699f902f82dc68f824276ed1cbef Mon Sep 17 00:00:00 2001 From: Timot05 Date: Tue, 20 Feb 2024 16:43:00 -0800 Subject: [PATCH 06/10] add I2S --- interfaces.ato | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/interfaces.ato b/interfaces.ato index deb1926..5eb73af 100644 --- a/interfaces.ato +++ b/interfaces.ato @@ -133,4 +133,10 @@ interface Pair: interface Analog: signal io - signal gnd \ No newline at end of file + signal gnd + +interface I2S: + signal ws + signal sck + signal sd + signal gnd From b533d8c5f3e3f61433b1d5c7758fff2c992eb915 Mon Sep 17 00:00:00 2001 From: napowderly Date: Wed, 21 Feb 2024 15:20:29 -0800 Subject: [PATCH 07/10] updated opamps --- buttons.ato | 27 +++++++++++++++++++++++--- diodes.ato | 7 ++++++- filters.ato | 29 +++++++++++++++++++++++++--- mosfets.ato | 33 ++++++++++++++++---------------- opamps.ato | 51 +++++++++++++++++++++++++------------------------ oscillators.ato | 0 regulators.ato | 4 ++++ vdivs.ato | 15 ++++++++++++--- 8 files changed, 115 insertions(+), 51 deletions(-) create mode 100644 oscillators.ato diff --git a/buttons.ato b/buttons.ato index 356b0f4..086bb70 100644 --- a/buttons.ato +++ b/buttons.ato @@ -1,6 +1,5 @@ -import Power from "generics/interfaces.ato" -import Resistor from "generics/resistors.ato" - +from "interfaces.ato" import Pair, Power +from "resistors.ato" import Resistor module NoButton: """ @@ -48,6 +47,9 @@ component _ButtonSKTDLDE010: mpn = "C115365" module ButtonSKTDLDE010 from NoButton: + """ + Small SMD right angle button + """ btn = new _ButtonSKTDLDE010 in ~ btn.in out ~ btn.out @@ -55,6 +57,7 @@ module ButtonSKTDLDE010 from NoButton: module ButtonPullup: btn = new NoButton signal out + output = new Pair power = new Power pullup = new Resistor pullup.value = 10kohms +/- 20% @@ -63,5 +66,23 @@ module ButtonPullup: power.vcc ~ pullup.p1; pullup.p2 ~ btn.in; btn.out ~ power.gnd out ~ btn.in + output.io ~ out + output.gnd ~ power.gnd + +module ButtonPulldown: + btn = new NoButton + signal out + output = new Pair + power = new Power + pulldown = new Resistor + pulldown.value = 10kohms +/- 20% + pulldown.package = "0402" + + power.gnd ~ pulldown.p1; pulldown.p2 ~ btn.in; btn.out ~ power.vcc + out ~ btn.in + + output.io ~ out + output.gnd ~ power.gnd + module ButtonPullup90Degree from ButtonPullup: btn -> _1TS003B_1400_3500A \ No newline at end of file diff --git a/diodes.ato b/diodes.ato index 77e10b3..732e8fa 100644 --- a/diodes.ato +++ b/diodes.ato @@ -22,10 +22,15 @@ component RectifierDiode from Diode: import Power from "interfaces.ato" module PowerDiodeOr: + """ + A diode or gate that combines two power rails, only dropping the + """ diode = new ShottkyDiode - power_in = new Power + power_in1 = new Power + power_in2 = new Power power_out = new Power + power_in2 ~ power_out power_in.vcc ~ diode.anode; diode.cathode ~ power_out.vcc power_in.gnd ~ power_out.gnd diff --git a/filters.ato b/filters.ato index 6802eb8..0027a41 100644 --- a/filters.ato +++ b/filters.ato @@ -1,7 +1,30 @@ import Power from "interfaces.ato" -import Capacitor from "capacitors.ato" -import CapacitorElectrolytic from "capacitors.ato" -import Inductor from "inductors.ato" +from "interfaces.ato" import Power, Pair +from "capacitors.ato" import Capacitor, CapacitorElectrolytic +from "inductors.ato" import Inductor +from "resistors.ato" import Resistor + + +module LowPassFilter: + # Interfaces + input = new Pair + output = new Pair + + # Components + capacitor = new Capacitor + resistor = new Resistor + + # Default values + capacitor.package = "0402" + resistor.package = "0402" + + # Connections + input.io ~ resistor.1 + output.io ~ resistor.2 + output.io ~ capacitor.1 + output.gnd ~ capacitor.2 + input.gnd ~ output.gnd + module LowPassPiFilter: C1 = new CapacitorElectrolytic diff --git a/mosfets.ato b/mosfets.ato index 2a2789b..1ae3f09 100644 --- a/mosfets.ato +++ b/mosfets.ato @@ -30,25 +30,26 @@ module HalfBridge: shunt_output = new DiffPair output = new Pair - # Components - nfet_high = new NFET - nfet_low = new NFET - shunt = new Resistor + # this doesnt work until we have replace with instance. + # # Components + # nfet_high = new NFET + # nfet_low = new NFET + # shunt = new Resistor - # Connect power - power.vcc ~ nfet_high.drain - output ~ nfe_high.source - output ~ nfet_low.drain - power.gnd ~ shunt.2; shunt.1 ~ nfet_high.source + # # Connect power + # power.vcc ~ nfet_high.drain + # output ~ nfe_high.source + # output ~ nfet_low.drain + # power.gnd ~ shunt.2; shunt.1 ~ nfet_high.source - # Connect the gates - gate_high.io ~ nfet_high.gate - gate_low.io ~ nfet_low.gate + # # Connect the gates + # gate_high.io ~ nfet_high.gate + # gate_low.io ~ nfet_low.gate - # Connect the gnds - output.gnd ~ power.gnd - gate_high.gnd ~ power.gnd - gate_low.gnd ~ power.gnd + # # Connect the gnds + # output.gnd ~ power.gnd + # gate_high.gnd ~ power.gnd + # gate_low.gnd ~ power.gnd module LowSideSwitch: fet = new Mosfet_nchannel diff --git a/opamps.ato b/opamps.ato index 5069e8e..fe63bed 100644 --- a/opamps.ato +++ b/opamps.ato @@ -1,7 +1,7 @@ component Opamp: power = new Power - signal inverting_input - signal noninverting_input + signal inverting + signal non_inverting signal output designator_prefix = "U" @@ -15,11 +15,12 @@ module VoltageFollower: signal input signal output - input ~ opamp.noninverting_input - opamp.inverting_input ~ opamp.output + input ~ opamp.non_inverting + opamp.inverting ~ opamp.output output ~ opamp.output -import vdiv from "StandardCircuits.ato" +# import vdiv from "StandardCircuits.ato" + module Amplifier: power = new Power opamp = new Opamp @@ -28,7 +29,7 @@ module Amplifier: power ~ opamp.power # TODO: add equation for gain - gain = unknown\ + gain = unknown vdiv.r_top.value = unknown vdiv.r_bottom.value = unknown @@ -36,11 +37,11 @@ module Amplifier: signal output input ~ vdiv.input - vdiv.output ~ opamp.inverting_input + vdiv.output ~ opamp.inverting output ~ opamp.output output ~ vdiv.gnd - inverting_input ~ power.gnd + inverting ~ power.gnd # Inverting Amplifier: Amplifies and inverts the input signal. # The gain is determined by the resistor values. @@ -53,9 +54,9 @@ module InvertingAmplifier: signal input signal output - input ~ opamp.inverting_input + input ~ opamp.inverting output ~ opamp.output - opamp.noninverting_input ~ power.gnd + opamp.non_inverting ~ power.gnd module SummingAmplifier: @@ -68,10 +69,10 @@ module SummingAmplifier: signal input2 signal output - input1 ~ opamp.inverting_input - input2 ~ opamp.inverting_input + input1 ~ opamp.inverting + input2 ~ opamp.inverting output ~ opamp.output - opamp.noninverting_input ~ power.gnd + opamp.non_inverting ~ power.gnd module DifferentialAmplifier: power = new Power @@ -83,8 +84,8 @@ module DifferentialAmplifier: signal input_negative signal output - input_positive ~ opamp.noninverting_input - input_negative ~ opamp.inverting_input + input_positive ~ opamp.non_inverting + input_negative ~ opamp.inverting output ~ opamp.output module Integrator: @@ -96,9 +97,9 @@ module Integrator: signal input signal output - input ~ opamp.inverting_input + input ~ opamp.inverting output ~ opamp.output - # Note: Needs a capacitor between inverting_input and output for integration + # Note: Needs a capacitor between inverting and output for integration module Differentiator: power = new Power @@ -109,7 +110,7 @@ module Differentiator: signal input signal output - input ~ opamp.inverting_input + input ~ opamp.inverting output ~ opamp.output # Note: Needs a capacitor at the input for differentiation @@ -123,8 +124,8 @@ module Comparator: signal input_negative signal output - input_positive ~ opamp.noninverting_input - input_negative ~ opamp.inverting_input + input_positive ~ opamp.non_inverting + input_negative ~ opamp.inverting output ~ opamp.output module InstrumentationAmplifier: @@ -141,10 +142,10 @@ module InstrumentationAmplifier: signal input_negative signal output - input_positive ~ opamp1.noninverting_input - input_negative ~ opamp2.inverting_input - opamp1.output ~ opamp3.inverting_input - opamp2.output ~ opamp3.noninverting_input + input_positive ~ opamp1.non_inverting + input_negative ~ opamp2.inverting + opamp1.output ~ opamp3.inverting + opamp2.output ~ opamp3.non_inverting output ~ opamp3.output module ActiveFilter: @@ -156,6 +157,6 @@ module ActiveFilter: signal input signal output - input ~ opamp.inverting_input + input ~ opamp.inverting output ~ opamp.output # Note: Specific filter components (capacitors, resistors) needed around opamp diff --git a/oscillators.ato b/oscillators.ato new file mode 100644 index 0000000..e69de29 diff --git a/regulators.ato b/regulators.ato index 588aa5a..9afa365 100644 --- a/regulators.ato +++ b/regulators.ato @@ -18,6 +18,10 @@ module Boost from AdjustableRegulator: # regulator parameters type = "Boost" +module LDO from Regulator: + # regulator parameters + type = "LDO" + module AdjustableLDO from AdjustableRegulator: # regulator parameters type = "AdjustableLDO" diff --git a/vdivs.ato b/vdivs.ato index a8c223f..c5ec75a 100644 --- a/vdivs.ato +++ b/vdivs.ato @@ -1,4 +1,5 @@ import Resistor from "resistors.ato" +import Capacitor from "capacitors.ato" import Power from "interfaces.ato" import Pair from "interfaces.ato" @@ -11,9 +12,11 @@ module VDiv: output.io ~ out output.gnd ~ bottom - in = new Power - in.vcc ~ top - in.gnd ~ bottom + in = new Power # legacy + power = new Power + in ~ power + power.vcc ~ top + power.gnd ~ bottom r_top = new Resistor r_bottom = new Resistor @@ -22,3 +25,9 @@ module VDiv: top ~ r_top.1; r_top.2 ~ r_bottom.1; r_bottom.2 ~ bottom r_top.2 ~ out + +module VDivLowPassFilter from VDiv: + cap = new Capacitor + cap.package = "0402" + + out ~ cap.1; cap.2 ~ bottom \ No newline at end of file From c927746a5d6039e67e2255d5511c6311e7c99f3b Mon Sep 17 00:00:00 2001 From: Sebastian Bergt Date: Sun, 25 Feb 2024 10:07:49 +0100 Subject: [PATCH 08/10] Update interfaces.ato --- interfaces.ato | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/interfaces.ato b/interfaces.ato index 5eb73af..53cdca1 100644 --- a/interfaces.ato +++ b/interfaces.ato @@ -23,6 +23,10 @@ interface STEPPER_MOTOR: signal b1 signal b2 +interface DcMotor + signal a + signal b + interface GPIO: signal io signal gnd From fafb337ae9df466d4be8ddf1837bd80dc02e02fd Mon Sep 17 00:00:00 2001 From: Sebastian Bergt Date: Sun, 25 Feb 2024 10:12:36 +0100 Subject: [PATCH 09/10] Update interfaces.ato --- interfaces.ato | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/interfaces.ato b/interfaces.ato index 53cdca1..8e038fc 100644 --- a/interfaces.ato +++ b/interfaces.ato @@ -23,7 +23,7 @@ interface STEPPER_MOTOR: signal b1 signal b2 -interface DcMotor +interface DcMotor: signal a signal b From fc10c5538fb49ea703c97db649872ae8665b1173 Mon Sep 17 00:00:00 2001 From: napowderly Date: Wed, 28 Feb 2024 09:33:19 -0800 Subject: [PATCH 10/10] updating connectors --- connectors.ato | 74 +++++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 64 insertions(+), 10 deletions(-) diff --git a/connectors.ato b/connectors.ato index 1dacdf8..121dc1f 100644 --- a/connectors.ato +++ b/connectors.ato @@ -1,17 +1,71 @@ -import WJ15EDGRC_3_81_2P from "elec/src/WJ15EDGRC_3_81_2P.ato" +component Connector2Pin: + signal p1 + signal p2 + +component Connector3Pin: + signal p1 + signal p2 + signal p3 -component Header2Pin: +component Connector4Pin: signal p1 signal p2 + signal p3 + signal p4 -component PluggableHeader2Pin from _WJ15EDGRC_3_81_2P: +component Connector5Pin: signal p1 signal p2 + signal p3 + signal p4 + signal p5 -component _WJ15EDGRC_3_81_2P: - # component WJ15EDGRC-3.81-2P - footprint = "CONN-TH_2P-P3.81_WJ15EDGRC-3.81-2P" - lcsc_id = "C8387" - # pins - signal p1 ~ pin 1 - signal p2 ~ pin 2 \ No newline at end of file +component Connector6Pin: + signal p1 + signal p2 + signal p3 + signal p4 + signal p5 + signal p6 + +component Connector7Pin: + signal p1 + signal p2 + signal p3 + signal p4 + signal p5 + signal p6 + signal p7 + +component Connector8Pin: + signal p1 + signal p2 + signal p3 + signal p4 + signal p5 + signal p6 + signal p7 + signal p8 + +component Connector9Pin: + signal p1 + signal p2 + signal p3 + signal p4 + signal p5 + signal p6 + signal p7 + signal p8 + signal p9 + +component Connector10Pin: + signal p1 + signal p2 + signal p3 + signal p4 + signal p5 + signal p6 + signal p7 + signal p8 + signal p9 + signal p10