From e6e8ef807c2d2a2c2c4c908d4f69e7ec46eb8b4a Mon Sep 17 00:00:00 2001 From: ruben-iteng <94007802+ruben-iteng@users.noreply.github.com> Date: Thu, 24 Oct 2024 10:54:47 +0200 Subject: [PATCH 1/4] Fix logic reference connection --- src/faebryk/library/PowerSwitchStatic.py | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/faebryk/library/PowerSwitchStatic.py b/src/faebryk/library/PowerSwitchStatic.py index 40c2f8e6..f0f46afe 100644 --- a/src/faebryk/library/PowerSwitchStatic.py +++ b/src/faebryk/library/PowerSwitchStatic.py @@ -20,5 +20,10 @@ def __init__(self) -> None: def __preinit__(self): self.power_in.connect(self.switched_power_out) - self.logic_in.reference.connect(self.power_in) - self.logic_in.set(True) + if self._normally_closed: + self.logic_in.reference.hv.connect(self.power_in.hv) + self.logic_in.signal.connect(self.power_in.lv) + else: + self.logic_in.reference.lv.connect(self.power_in.lv) + self.logic_in.signal.connect(self.power_in.hv) + self.logic_in.reference.voltage.merge(self.power_in.voltage) From 60d60a661182ef347b03461f3344c06d22b7c888 Mon Sep 17 00:00:00 2001 From: ruben-iteng <94007802+ruben-iteng@users.noreply.github.com> Date: Thu, 31 Oct 2024 17:24:13 +0100 Subject: [PATCH 2/4] Add RP Pico design (WIP) --- src/faebryk/library/RaspberryPiPico.py | 130 +++++++++++++++++++++++++ src/faebryk/library/_F.py | 1 + 2 files changed, 131 insertions(+) create mode 100644 src/faebryk/library/RaspberryPiPico.py diff --git a/src/faebryk/library/RaspberryPiPico.py b/src/faebryk/library/RaspberryPiPico.py new file mode 100644 index 00000000..613237c2 --- /dev/null +++ b/src/faebryk/library/RaspberryPiPico.py @@ -0,0 +1,130 @@ +# This file is part of the faebryk project +# SPDX-License-Identifier: MIT + +import logging + +import faebryk.library._F as F # noqa: F401 +from faebryk.core.module import Module +from faebryk.exporters.pcb.layout.heuristic_decoupling import ( + LayoutHeuristicElectricalClosenessDecouplingCaps, +) +from faebryk.exporters.pcb.layout.heuristic_pulls import ( + LayoutHeuristicElectricalClosenessPullResistors, +) +from faebryk.libs.library import L # noqa: F401 +from faebryk.libs.units import P # noqa: F401 + +logger = logging.getLogger(__name__) + + +class RaspberryPiPico(Module): + """ + Raspberry Pi Pico clone. + """ + + # ---------------------------------------- + # modules, interfaces, parameters + # ---------------------------------------- + base: F.RaspberryPiPicoBase_ReferenceDesign + header = L.list_f_field(2, F.Header)(horizonal_pin_count=20, vertical_pin_count=1) + usb_connector: F.USB_Type_C_Receptacle_16_pin + # ---------------------------------------- + # traits + # ---------------------------------------- + datasheet = L.f_field(F.has_datasheet_defined)( + "https://datasheets.raspberrypi.com/pico/pico-datasheet.pdf" + ) + + @L.rt_field + def designator_prefix(self): + return F.has_designator_prefix_defined(F.has_designator_prefix.Prefix.MOD) + + @L.rt_field + def pcb_layout(self): + from faebryk.exporters.pcb.layout.absolute import LayoutAbsolute + from faebryk.exporters.pcb.layout.extrude import LayoutExtrude + from faebryk.exporters.pcb.layout.typehierarchy import LayoutTypeHierarchy + + Point = F.has_pcb_position.Point + L = F.has_pcb_position.layer_type + LVL = LayoutTypeHierarchy.Level + + layout = F.has_pcb_layout_defined( + layout=LayoutTypeHierarchy( + layouts=[ + LVL( + mod_type=F.RaspberryPiPicoBase_ReferenceDesign, + layout=LayoutAbsolute( + Point((0, 0, 0, L.NONE)), + ), + ), + LVL( + mod_type=F.Header, + layout=LayoutExtrude( + base=Point((0, 0, L.NONE)), vector=(17.78, 0) + ), + ), + LVL( + mod_type=F.USB_Type_C_Receptacle_16_pin, + layout=LayoutAbsolute( + Point((17.78 / 2, 0, L.NONE)), + ), + ), + ] + ) + ) + + LayoutHeuristicElectricalClosenessDecouplingCaps.add_to_all_suitable_modules( + self + ) + LayoutHeuristicElectricalClosenessPullResistors.add_to_all_suitable_modules( + self + ) + + return layout + + def __preinit__(self): + # ------------------------------------ + # connections + # ------------------------------------ + power_3v3 = self.base.ldo.power_out + gnd = power_3v3.lv + + pin_count = 0 + for pin in self.header[0].contact: + if pin in [2, 7, 12, 17]: + pin.connect(gnd) + else: + pin.connect(self.base.rp2040.gpio[pin_count].signal) + self.base.rp2040.pinmux.enable(self.base.rp2040.gpio[pin_count]) + pin_count += 1 + pin_count = 16 + for pin in self.header[1].contact: + if pin in [2, 7, 12, 17]: + pin.connect(gnd) + elif pin == 9: + pin.connect(self.base.rp2040.run.signal) + elif pin == 14: + ... # TODO: ADC_VREF is not implemented + elif pin == 15: + pin.connect(power_3v3.hv) + elif pin == 16: + pin.connect(self.base.ldo.enable.signal) + elif pin == 18: + pin.connect(self.base.ldo.power_in.hv) + elif pin == 19: + pin.connect(self.base.usb.usb_if.buspower.hv) + else: + pin.connect(self.base.rp2040.gpio[pin_count].signal) + self.base.rp2040.pinmux.enable(self.base.rp2040.gpio[pin_count]) + pin_count += 1 + + # ------------------------------------ + # parametrization + # ------------------------------------ + for header in self.header: + header.pin_pitch.merge(2.54 * P.mm) + header.mating_pin_lenght.merge(F.Range.from_center_rel(6 * P.mm, 0.1)) + header.pad_type.merge(F.Header.PadType.THROUGH_HOLE) + header.pin_type.merge(F.Header.PinType.MALE) + header.angle.merge(F.Header.Angle.STRAIGHT) diff --git a/src/faebryk/library/_F.py b/src/faebryk/library/_F.py index 0f129e78..fd8d80cb 100644 --- a/src/faebryk/library/_F.py +++ b/src/faebryk/library/_F.py @@ -256,3 +256,4 @@ from faebryk.library.CH344Q_ReferenceDesign import CH344Q_ReferenceDesign from faebryk.library.RaspberryPiPicoBase_ReferenceDesign import RaspberryPiPicoBase_ReferenceDesign from faebryk.library.USB2514B_ReferenceDesign import USB2514B_ReferenceDesign +from faebryk.library.RaspberryPiPico import RaspberryPiPico From 5ddce0315f04b57e47db26c26765270408ef594e Mon Sep 17 00:00:00 2001 From: ruben-iteng <94007802+ruben-iteng@users.noreply.github.com> Date: Sat, 2 Nov 2024 18:27:11 +0100 Subject: [PATCH 3/4] Fix pin connection --- src/faebryk/library/RaspberryPiPico.py | 37 +++++++++++++------------- 1 file changed, 19 insertions(+), 18 deletions(-) diff --git a/src/faebryk/library/RaspberryPiPico.py b/src/faebryk/library/RaspberryPiPico.py index 613237c2..3d8adf64 100644 --- a/src/faebryk/library/RaspberryPiPico.py +++ b/src/faebryk/library/RaspberryPiPico.py @@ -90,34 +90,35 @@ def __preinit__(self): power_3v3 = self.base.ldo.power_out gnd = power_3v3.lv - pin_count = 0 - for pin in self.header[0].contact: - if pin in [2, 7, 12, 17]: + gpio_count = 0 + for i, pin in enumerate(self.header[0].contact): + if i in [2, 7, 12, 17]: pin.connect(gnd) else: - pin.connect(self.base.rp2040.gpio[pin_count].signal) - self.base.rp2040.pinmux.enable(self.base.rp2040.gpio[pin_count]) - pin_count += 1 - pin_count = 16 - for pin in self.header[1].contact: - if pin in [2, 7, 12, 17]: + pin.connect(self.base.rp2040.gpio[gpio_count].signal) + self.base.rp2040.pinmux.enable(self.base.rp2040.gpio[gpio_count]) + gpio_count += 1 + for i, pin in enumerate(self.header[1].contact): + if i in [2, 7, 12, 17]: pin.connect(gnd) - elif pin == 9: + elif i == 9: pin.connect(self.base.rp2040.run.signal) - elif pin == 14: + elif i == 14: ... # TODO: ADC_VREF is not implemented - elif pin == 15: + elif i == 15: pin.connect(power_3v3.hv) - elif pin == 16: + elif i == 16: pin.connect(self.base.ldo.enable.signal) - elif pin == 18: + elif i == 18: pin.connect(self.base.ldo.power_in.hv) - elif pin == 19: + elif i == 19: pin.connect(self.base.usb.usb_if.buspower.hv) else: - pin.connect(self.base.rp2040.gpio[pin_count].signal) - self.base.rp2040.pinmux.enable(self.base.rp2040.gpio[pin_count]) - pin_count += 1 + if gpio_count == 23: + gpio_count += 3 # skip 23, 24, 25 + pin.connect(self.base.rp2040.gpio[gpio_count].signal) + self.base.rp2040.pinmux.enable(self.base.rp2040.gpio[gpio_count]) + gpio_count += 1 # ------------------------------------ # parametrization From d0f41ee101614d711e9e7ca67c0dbc7ad8c5126b Mon Sep 17 00:00:00 2001 From: ruben-iteng <94007802+ruben-iteng@users.noreply.github.com> Date: Sat, 2 Nov 2024 18:48:00 +0100 Subject: [PATCH 4/4] Fix switch and traits --- src/faebryk/library/PANASONIC_AQY212EHAX.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/faebryk/library/PANASONIC_AQY212EHAX.py b/src/faebryk/library/PANASONIC_AQY212EHAX.py index c9bf0217..5993a696 100644 --- a/src/faebryk/library/PANASONIC_AQY212EHAX.py +++ b/src/faebryk/library/PANASONIC_AQY212EHAX.py @@ -21,7 +21,7 @@ class PANASONIC_AQY212EHAX(Module): # modules, interfaces, parameters # ---------------------------------------- led: F.LED - switch = L.f_field(F.Switch)(interface_type=F.Electrical) + switch = L.f_field(F.Switch(F.Electrical))() # ---------------------------------------- # traits @@ -57,8 +57,8 @@ def __preinit__(self): # ------------------------------------ # connections # ------------------------------------ - self.led.add_trait(has_part_picked_remove()) - self.switch.add_trait(has_part_picked_remove()) + self.led.add(has_part_picked_remove()) + self.switch.add(has_part_picked_remove()) # ------------------------------------ # parametrization