diff --git a/examples/iterative_design_nand.py b/examples/iterative_design_nand.py index f8ae891e..305c2f15 100644 --- a/examples/iterative_design_nand.py +++ b/examples/iterative_design_nand.py @@ -37,7 +37,7 @@ class PowerSource(Module): class XOR_with_NANDS(F.LogicGates.XOR): - nands = L.node_list(4, lambda: F.LogicGates.NAND(F.Constant(2))) + nands = L.list_field(4, lambda: F.LogicGates.NAND(F.Constant(2))) def __init__(self): super().__init__(F.Constant(2)) diff --git a/examples/route.py b/examples/route.py index 5c36ad71..862f5efe 100644 --- a/examples/route.py +++ b/examples/route.py @@ -26,8 +26,8 @@ class SubArray(Module): - unnamed = L.node_list(2, F.Electrical) - resistors = L.node_list(2, F.Resistor) + unnamed = L.list_field(2, F.Electrical) + resistors = L.list_field(2, F.Resistor) def __init__(self, extrude_y: float): super().__init__() @@ -99,7 +99,7 @@ def pcb_routing_stategy_manual(self): class ResistorArray(Module): - unnamed = L.node_list(2, F.Electrical) + unnamed = L.list_field(2, F.Electrical) @L.rt_field def resistors(self): diff --git a/new_holders_flat.py b/new_holders_flat.py index 2b3fda33..568ebc5c 100644 --- a/new_holders_flat.py +++ b/new_holders_flat.py @@ -69,7 +69,7 @@ def __preinit__(self): class LED2_WITHEXTRAT_IFS(LED2): extra: list[F.Electrical] = field(default_factory=lambda: times(2, F.Electrical)) - extra2: list[F.Electrical] = L.node_list(2, F.Electrical) + extra2: list[F.Electrical] = L.list_field(2, F.Electrical) @L.rt_field def bridge(self): diff --git a/src/faebryk/core/node.py b/src/faebryk/core/node.py index fb16d74a..bcb87660 100644 --- a/src/faebryk/core/node.py +++ b/src/faebryk/core/node.py @@ -5,6 +5,7 @@ from typing import TYPE_CHECKING, Any, Callable, Iterable, Type, get_args, get_origin from deprecated import deprecated +from more_itertools import partition from faebryk.core.core import ID_REPR, FaebrykLibObject from faebryk.core.graphinterface import ( @@ -21,7 +22,6 @@ times, try_avoid_endless_recursion, ) -from more_itertools import partition if TYPE_CHECKING: from faebryk.core.trait import Trait, TraitImpl @@ -41,10 +41,8 @@ class FieldContainerError(FieldError): pass -def node_list[T: Node](n: int, if_type: type[T]) -> list[T]: - out = d_field(lambda: times(n, if_type)) - out.type = if_type - return out +def list_field[T: Node](n: int, if_type: Callable[[], T]) -> list[T]: + return d_field(lambda: times(n, if_type)) class fab_field: @@ -71,11 +69,10 @@ def __get__(self, instance: T, owner: type | None = None) -> Any: class _d_field[T](fab_field): def __init__(self, default_factory: Callable[[], T]) -> None: - self.type = None self.default_factory = default_factory def __repr__(self) -> str: - return f"{super().__repr__()}({self.type=}, {self.default_factory=})" + return f"{super().__repr__()}{self.default_factory=})" def d_field[T](default_factory: Callable[[], T]) -> T: @@ -89,9 +86,7 @@ def _(*args: P.args, **kwargs: P.kwargs) -> Callable[[], T]: def __() -> T: return con(*args, **kwargs) - out = _d_field(__) - out.type = con - return out + return _d_field(__) return _ @@ -120,6 +115,9 @@ def __init__(self, node: "Node", other: "Node", *args: object) -> None: ) +class NodeNoParent(NodeException): ... + + class Node(FaebrykLibObject, metaclass=PostInitCaller): runtime_anon: list["Node"] runtime: dict[str, "Node"] @@ -203,9 +201,6 @@ def all_anno(cls): annos = all_anno(cls) vars_ = all_vars(cls) - for name, obj in vars_.items(): - if isinstance(obj, _d_field) and obj.type is None: - obj.type = annos[name] def is_node_field(obj): def is_genalias_node(obj): @@ -229,12 +224,7 @@ def is_genalias_node(obj): return issubclass(obj, LL_Types) if isinstance(obj, _d_field): - t = obj.type - if isinstance(t, type): - return issubclass(t, LL_Types) - - if get_origin(t): - return is_genalias_node(t) + return True if get_origin(obj): return is_genalias_node(obj) @@ -267,9 +257,12 @@ def is_genalias_node(obj): # "| {type(obj)}" # ) + added_objects: dict[str, Node | GraphInterface] = {} objects: dict[str, Node | GraphInterface] = {} def handle_add(name, obj): + del objects[name] + added_objects[name] = obj if isinstance(obj, GraphInterface): self._handle_add_gif(name, obj) elif isinstance(obj, Node): @@ -307,22 +300,8 @@ def setup_gen_alias(name, obj): return if isinstance(obj, _d_field): - t = obj.type - - if isinstance(obj, _d_field): - inst = append(name, obj.default_factory()) - setattr(self, name, inst) - return - - if isinstance(t, type): - setattr(self, name, append(name, t())) - return - - if get_origin(t): - setup_gen_alias(name, t) - return - - raise NotImplementedError() + setattr(self, name, append(name, obj.default_factory())) + return if isinstance(obj, type): setattr(self, name, append(name, obj())) @@ -338,19 +317,17 @@ def setup_gen_alias(name, obj): for name, obj in nonrt: setup_field(name, obj) - for name, obj in objects.items(): + for name, obj in list(objects.items()): handle_add(name, obj) - obj_old = dict(objects) # rt fields depend on full self for name, obj in rt: setup_field(name, obj) - for name, obj in objects.items(): - if name not in obj_old: + for name, obj in list(objects.items()): handle_add(name, obj) - return objects, clsfields + return added_objects, clsfields def __new__(cls, *args, **kwargs): out = super().__new__(cls) @@ -424,7 +401,7 @@ def get_parent(self): def get_name(self): p = self.get_parent() if not p: - raise Exception("Parent required for name") + raise NodeNoParent(self, "Parent required for name") return p[1] def get_hierarchy(self) -> list[tuple["Node", str]]: diff --git a/src/faebryk/exporters/pcb/kicad/transformer.py b/src/faebryk/exporters/pcb/kicad/transformer.py index 5462dc5d..65fedc49 100644 --- a/src/faebryk/exporters/pcb/kicad/transformer.py +++ b/src/faebryk/exporters/pcb/kicad/transformer.py @@ -516,7 +516,7 @@ def mark(node: R) -> R: def insert(self, obj: Any): self._insert(obj) - def _get_pcb_node_list(self, node: R, prefix: str = "") -> list[R]: + def _get_pcb_list_field(self, node: R, prefix: str = "") -> list[R]: root = self.pcb key = prefix + type(node).__name__.removeprefix("C_") + "s" @@ -529,10 +529,10 @@ def _get_pcb_node_list(self, node: R, prefix: str = "") -> list[R]: def _insert(self, obj: Any, prefix: str = ""): obj = PCB_Transformer.mark(obj) - self._get_pcb_node_list(obj, prefix=prefix).append(obj) + self._get_pcb_list_field(obj, prefix=prefix).append(obj) def _delete(self, obj: Any, prefix: str = ""): - self._get_pcb_node_list(obj, prefix=prefix).remove(obj) + self._get_pcb_list_field(obj, prefix=prefix).remove(obj) def insert_via( self, coord: tuple[float, float], net: str, size_drill: tuple[float, float] diff --git a/src/faebryk/library/B4B_ZR_SM4_TF.py b/src/faebryk/library/B4B_ZR_SM4_TF.py index a2391a9e..b44f6f52 100644 --- a/src/faebryk/library/B4B_ZR_SM4_TF.py +++ b/src/faebryk/library/B4B_ZR_SM4_TF.py @@ -7,8 +7,8 @@ class B4B_ZR_SM4_TF(Module): - pin = L.node_list(4, F.Electrical) - mount = L.node_list(2, F.Electrical) + pin = L.list_field(4, F.Electrical) + mount = L.list_field(2, F.Electrical) datasheet = L.f_field(F.has_datasheet_defined)( "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2304140030_BOOMELE-Boom-Precision-Elec-1-5-4P_C145997.pdf" diff --git a/src/faebryk/library/Button.py b/src/faebryk/library/Button.py index 85d7d8be..0a47e77c 100644 --- a/src/faebryk/library/Button.py +++ b/src/faebryk/library/Button.py @@ -11,7 +11,7 @@ class Button(Module): - unnamed = L.node_list(2, F.Electrical) + unnamed = L.list_field(2, F.Electrical) designator_prefix = L.f_field(F.has_designator_prefix_defined)("S") diff --git a/src/faebryk/library/CBM9002A_56ILG.py b/src/faebryk/library/CBM9002A_56ILG.py index ea40cbc2..438dbbe4 100644 --- a/src/faebryk/library/CBM9002A_56ILG.py +++ b/src/faebryk/library/CBM9002A_56ILG.py @@ -16,17 +16,17 @@ class CBM9002A_56ILG(Module): # ---------------------------------------- # modules, interfaces, parameters # ---------------------------------------- - PA = L.node_list(8, F.ElectricLogic) - PB = L.node_list(8, F.ElectricLogic) - PD = L.node_list(8, F.ElectricLogic) + PA = L.list_field(8, F.ElectricLogic) + PB = L.list_field(8, F.ElectricLogic) + PD = L.list_field(8, F.ElectricLogic) usb: F.USB2_0 i2c: F.I2C avcc: F.ElectricPower vcc: F.ElectricPower - rdy = L.node_list(2, F.ElectricLogic) - ctl = L.node_list(3, F.ElectricLogic) + rdy = L.list_field(2, F.ElectricLogic) + ctl = L.list_field(3, F.ElectricLogic) reset: F.ElectricLogic wakeup: F.ElectricLogic diff --git a/src/faebryk/library/CBM9002A_56ILG_Reference_Design.py b/src/faebryk/library/CBM9002A_56ILG_Reference_Design.py index ee0d2088..cfe0694f 100644 --- a/src/faebryk/library/CBM9002A_56ILG_Reference_Design.py +++ b/src/faebryk/library/CBM9002A_56ILG_Reference_Design.py @@ -20,17 +20,17 @@ class CBM9002A_56ILG_Reference_Design(Module): reset_lowpass_cap: F.Capacitor oscillator: F.Crystal_Oscillator - PA = L.node_list(8, F.ElectricLogic) - PB = L.node_list(8, F.ElectricLogic) - PD = L.node_list(8, F.ElectricLogic) + PA = L.list_field(8, F.ElectricLogic) + PB = L.list_field(8, F.ElectricLogic) + PD = L.list_field(8, F.ElectricLogic) usb: F.USB2_0 i2c: F.I2C avcc: F.ElectricPower vcc: F.ElectricPower - rdy = L.node_list(2, F.ElectricLogic) - ctl = L.node_list(3, F.ElectricLogic) + rdy = L.list_field(2, F.ElectricLogic) + ctl = L.list_field(3, F.ElectricLogic) reset: F.ElectricLogic wakeup: F.ElectricLogic diff --git a/src/faebryk/library/Capacitor.py b/src/faebryk/library/Capacitor.py index a84cf4fd..3e4e6244 100644 --- a/src/faebryk/library/Capacitor.py +++ b/src/faebryk/library/Capacitor.py @@ -23,7 +23,7 @@ class TemperatureCoefficient(IntEnum): X8R = auto() C0G = auto() - unnamed = L.node_list(2, F.Electrical) + unnamed = L.list_field(2, F.Electrical) capacitance: F.TBD[Quantity] rated_voltage: F.TBD[Quantity] diff --git a/src/faebryk/library/Common_Mode_Filter.py b/src/faebryk/library/Common_Mode_Filter.py index 16dcbdc2..5f60bbda 100644 --- a/src/faebryk/library/Common_Mode_Filter.py +++ b/src/faebryk/library/Common_Mode_Filter.py @@ -11,7 +11,7 @@ class Common_Mode_Filter(Module): - c_a = L.node_list(2, F.Electrical) - c_b = L.node_list(2, F.Electrical) + c_a = L.list_field(2, F.Electrical) + c_b = L.list_field(2, F.Electrical) designator_prefix = L.f_field(F.has_designator_prefix_defined)("FL") diff --git a/src/faebryk/library/Crystal.py b/src/faebryk/library/Crystal.py index f4b6ace8..3a43b905 100644 --- a/src/faebryk/library/Crystal.py +++ b/src/faebryk/library/Crystal.py @@ -21,7 +21,7 @@ class Crystal(Module): load_impedance: F.TBD[Quantity] gnd: F.Electrical - unnamed = L.node_list(2, F.Electrical) + unnamed = L.list_field(2, F.Electrical) # ---------------------------------------- # parameters diff --git a/src/faebryk/library/Crystal_Oscillator.py b/src/faebryk/library/Crystal_Oscillator.py index 085582ff..bf5b3023 100644 --- a/src/faebryk/library/Crystal_Oscillator.py +++ b/src/faebryk/library/Crystal_Oscillator.py @@ -15,7 +15,7 @@ class Crystal_Oscillator(Module): # modules, interfaces, parameters # ---------------------------------------- crystal: F.Crystal - capacitors = L.node_list(2, F.Capacitor) + capacitors = L.list_field(2, F.Capacitor) power: F.ElectricPower p: F.Electrical diff --git a/src/faebryk/library/DIP.py b/src/faebryk/library/DIP.py index cfc5f392..e628d359 100644 --- a/src/faebryk/library/DIP.py +++ b/src/faebryk/library/DIP.py @@ -31,7 +31,7 @@ def get_kicad_footprint() -> str: longpads="_LongPads" if self.long_pads else "", ) - return _has_kicad_footprint + return _has_kicad_footprint() equal_pins_in_ifs: F.has_equal_pins_in_ifs attach_via_pinmap: F.can_attach_via_pinmap_equal diff --git a/src/faebryk/library/EEPROM.py b/src/faebryk/library/EEPROM.py index d0624bb7..a14f0e26 100644 --- a/src/faebryk/library/EEPROM.py +++ b/src/faebryk/library/EEPROM.py @@ -30,7 +30,7 @@ def set_address(self, addr: int): power: F.ElectricPower i2c: F.I2C write_protect: F.ElectricLogic - address = L.node_list(3, F.ElectricLogic) + address = L.list_field(3, F.ElectricLogic) # ---------------------------------------- # traits diff --git a/src/faebryk/library/ESP32.py b/src/faebryk/library/ESP32.py index 222ef533..a9f5c7a2 100644 --- a/src/faebryk/library/ESP32.py +++ b/src/faebryk/library/ESP32.py @@ -27,15 +27,15 @@ def CHANNELS(self): class _ESP_SDIO(ModuleInterface): - DATA = L.node_list(4, F.Electrical) + DATA = L.list_field(4, F.Electrical) CLK: F.Electrical CMD: F.Electrical GND: F.Electrical class _ESP32_EMAC(ModuleInterface): - TXD = L.node_list(4, F.Electrical) - RXD = L.node_list(4, F.Electrical) + TXD = L.list_field(4, F.Electrical) + RXD = L.list_field(4, F.Electrical) TX_CLK: F.Electrical RX_CLK: F.Electrical TX_EN: F.Electrical @@ -123,14 +123,14 @@ class ESP32(Module): GND: F.Electrical # High Level Functions - F.I2C = L.node_list(2, F.I2C) + F.I2C = L.list_field(2, F.I2C) SDIO_SLAVE: _ESP_SDIO - SDIO_HOST = L.node_list(2, _ESP_SDIO) + SDIO_HOST = L.list_field(2, _ESP_SDIO) UART: F.UART_Base JTAG: F.JTAG - TOUCH = L.node_list(10, F.Electrical) - GPIO = L.node_list(40 - 6, F.Electrical) - RTC_GPIO = L.node_list(18, F.Electrical) + TOUCH = L.list_field(10, F.Electrical) + GPIO = L.list_field(40 - 6, F.Electrical) + RTC_GPIO = L.list_field(18, F.Electrical) ADC = L.d_field( lambda: ( None, @@ -138,7 +138,7 @@ class ESP32(Module): _ESP_ADC(channel_count=10), ) ) - SPI = L.node_list(4, _ESP32_SPI) + SPI = L.list_field(4, _ESP32_SPI) EMAC: _ESP32_EMAC # Power diff --git a/src/faebryk/library/ESP32_C3.py b/src/faebryk/library/ESP32_C3.py index a054bf29..3942495d 100644 --- a/src/faebryk/library/ESP32_C3.py +++ b/src/faebryk/library/ESP32_C3.py @@ -23,11 +23,11 @@ class ESP32_C3(Module): enable: F.ElectricLogic xtal_p: F.Electrical xtal_n: F.Electrical - gpio = L.node_list(22, F.ElectricLogic) + gpio = L.list_field(22, F.ElectricLogic) # TODO: map peripherals to GPIOs with pinmux usb: F.USB2_0 i2c: F.I2C - uart = L.node_list(2, F.UART_Base) + uart = L.list_field(2, F.UART_Base) # ... etc designator_prefix = L.f_field(F.has_designator_prefix_defined)("U") diff --git a/src/faebryk/library/ESP32_C3_MINI_1.py b/src/faebryk/library/ESP32_C3_MINI_1.py index fca437d4..07ab53aa 100644 --- a/src/faebryk/library/ESP32_C3_MINI_1.py +++ b/src/faebryk/library/ESP32_C3_MINI_1.py @@ -18,7 +18,7 @@ class ESP32_C3_MINI_1(Module): rf_output: F.Electrical chip_enable: F.ElectricLogic - gpio = L.node_list( + gpio = L.list_field( 22, F.ElectricLogic ) # TODO: Only GPIO 0 to 10 and 18, 19 are exposed uart: F.UART_Base diff --git a/src/faebryk/library/ElectricLogicGate.py b/src/faebryk/library/ElectricLogicGate.py index c99d714a..a27f0ef4 100644 --- a/src/faebryk/library/ElectricLogicGate.py +++ b/src/faebryk/library/ElectricLogicGate.py @@ -18,12 +18,12 @@ def __init__( output_cnt: F.Constant[int], *functions: TraitImpl, ) -> None: - from faebryk.core.util import specialize_interface - - super().__init__(input_cnt, output_cnt, *functions) - self.input_cnt = input_cnt self.output_cnt = output_cnt + super().__init__(input_cnt, output_cnt, *functions) + + def __preinit__(self): + from faebryk.core.util import specialize_interface self_logic = self diff --git a/src/faebryk/library/Fuse.py b/src/faebryk/library/Fuse.py index 861d8142..27cbd851 100644 --- a/src/faebryk/library/Fuse.py +++ b/src/faebryk/library/Fuse.py @@ -21,7 +21,7 @@ class ResponseType(Enum): SLOW = auto() FAST = auto() - unnamed = L.node_list(2, F.Electrical) + unnamed = L.list_field(2, F.Electrical) fuse_type: F.TBD[FuseType] response_type: F.TBD[ResponseType] trip_current: F.TBD[Quantity] diff --git a/src/faebryk/library/GenericBusProtection.py b/src/faebryk/library/GenericBusProtection.py index 894c9fbc..ba7865bb 100644 --- a/src/faebryk/library/GenericBusProtection.py +++ b/src/faebryk/library/GenericBusProtection.py @@ -45,7 +45,7 @@ def get_mifs[U: ModuleInterface](bus: T, mif_type: type[U]) -> set[U]: ) ) - fuse = L.node_list(len(power), F.Fuse) + fuse = L.list_field(len(power), F.Fuse) # Pass through except hv for power_unprotected, power_protected in power: diff --git a/src/faebryk/library/Inductor.py b/src/faebryk/library/Inductor.py index c40eb9aa..727b4ac4 100644 --- a/src/faebryk/library/Inductor.py +++ b/src/faebryk/library/Inductor.py @@ -9,7 +9,7 @@ class Inductor(Module): - unnamed = L.node_list(2, F.Electrical) + unnamed = L.list_field(2, F.Electrical) inductance: F.TBD[Quantity] self_resonant_frequency: F.TBD[Quantity] diff --git a/src/faebryk/library/M24C08_FMN6TP.py b/src/faebryk/library/M24C08_FMN6TP.py index b99ad729..c331f51d 100644 --- a/src/faebryk/library/M24C08_FMN6TP.py +++ b/src/faebryk/library/M24C08_FMN6TP.py @@ -16,7 +16,7 @@ class M24C08_FMN6TP(Module): power: F.ElectricPower data: F.I2C nwc: F.ElectricLogic - e = L.node_list(3, F.ElectricLogic) + e = L.list_field(3, F.ElectricLogic) @L.rt_field def attach_to_footprint(self): diff --git a/src/faebryk/library/MCP2221A.py b/src/faebryk/library/MCP2221A.py index 00972f07..349ff3e4 100644 --- a/src/faebryk/library/MCP2221A.py +++ b/src/faebryk/library/MCP2221A.py @@ -15,7 +15,7 @@ class MCP2221A(Module): power_vusb: F.ElectricPower uart: F.UART_Base i2c: F.I2C - gpio = L.node_list(4, F.Electrical) + gpio = L.list_field(4, F.Electrical) reset: F.ElectricLogic usb: F.USB2_0 diff --git a/src/faebryk/library/Potentiometer.py b/src/faebryk/library/Potentiometer.py index 09047a6f..587859d6 100644 --- a/src/faebryk/library/Potentiometer.py +++ b/src/faebryk/library/Potentiometer.py @@ -8,10 +8,10 @@ class Potentiometer(Module): - resistors_ifs = L.node_list(2, F.Electrical) + resistors_ifs = L.list_field(2, F.Electrical) wiper: F.Electrical total_resistance: F.TBD[Quantity] - resistors = L.node_list(2, F.Resistor) + resistors = L.list_field(2, F.Resistor) def __preinit__(self): for i, resistor in enumerate(self.resistors): diff --git a/src/faebryk/library/RJ45_Receptacle.py b/src/faebryk/library/RJ45_Receptacle.py index 55ccd2e6..fe311f50 100644 --- a/src/faebryk/library/RJ45_Receptacle.py +++ b/src/faebryk/library/RJ45_Receptacle.py @@ -15,7 +15,7 @@ class Mounting(Enum): # interfaces - pin = L.node_list(8, F.Electrical) + pin = L.list_field(8, F.Electrical) shield: F.Electrical designator_prefix = L.f_field(F.has_designator_prefix_defined)("J") diff --git a/src/faebryk/library/RP2040.py b/src/faebryk/library/RP2040.py index daf1db79..be8d03ce 100644 --- a/src/faebryk/library/RP2040.py +++ b/src/faebryk/library/RP2040.py @@ -17,7 +17,7 @@ class RP2040(Module): vreg_in: F.ElectricPower vreg_out: F.ElectricPower power_vusb: F.ElectricPower - gpio = L.node_list(30, F.Electrical) + gpio = L.list_field(30, F.Electrical) run: F.ElectricLogic usb: F.USB2_0 qspi = L.f_field(F.MultiSPI)(data_lane_count=4) diff --git a/src/faebryk/library/RP2040_Reference_Design.py b/src/faebryk/library/RP2040_Reference_Design.py index 907c0399..fa1b0145 100644 --- a/src/faebryk/library/RP2040_Reference_Design.py +++ b/src/faebryk/library/RP2040_Reference_Design.py @@ -26,7 +26,7 @@ class RP2040_Reference_Design(Module): rp2040: F.RP2040 flash: F.SPIFlash led: F.PoweredLED - usb_current_limit_resistor = L.node_list(2, F.Resistor) + usb_current_limit_resistor = L.list_field(2, F.Resistor) # TODO: add crystal oscillator # TODO: add voltage divider with switch # TODO: add boot button diff --git a/src/faebryk/library/RS485_Bus_Protection.py b/src/faebryk/library/RS485_Bus_Protection.py index 2f652768..7f9f5216 100644 --- a/src/faebryk/library/RS485_Bus_Protection.py +++ b/src/faebryk/library/RS485_Bus_Protection.py @@ -34,11 +34,11 @@ def __init__(self, termination: bool = True, polarization: bool = True) -> None: gdt: F.GDT tvs: F.TVS - current_limmiter_resistors = L.node_list(2, F.Resistor) + current_limmiter_resistors = L.list_field(2, F.Resistor) common_mode_filter: F.Common_Mode_Filter gnd_couple_resistor: F.Resistor gnd_couple_capacitor: F.Capacitor - clamping_diodes = L.node_list(2, F.Diode) + clamping_diodes = L.list_field(2, F.Diode) power: F.ElectricPower rs485_in: F.RS485 rs485_out: F.RS485 diff --git a/src/faebryk/library/Resistor.py b/src/faebryk/library/Resistor.py index b392423a..465e3328 100644 --- a/src/faebryk/library/Resistor.py +++ b/src/faebryk/library/Resistor.py @@ -12,7 +12,7 @@ class Resistor(Module): - unnamed = L.node_list(2, F.Electrical) + unnamed = L.list_field(2, F.Electrical) resistance: F.TBD[Quantity] rated_power: F.TBD[Quantity] diff --git a/src/faebryk/library/Resistor_Voltage_Divider.py b/src/faebryk/library/Resistor_Voltage_Divider.py index a402d1ad..cc7dd64a 100644 --- a/src/faebryk/library/Resistor_Voltage_Divider.py +++ b/src/faebryk/library/Resistor_Voltage_Divider.py @@ -12,8 +12,8 @@ class Resistor_Voltage_Divider(Module): - resistor = L.node_list(2, F.Resistor) - node = L.node_list(3, F.Electrical) + resistor = L.list_field(2, F.Resistor) + node = L.list_field(3, F.Electrical) ratio: F.TBD[Quantity] max_current: F.TBD[Quantity] diff --git a/src/faebryk/library/SMDTwoPin.py b/src/faebryk/library/SMDTwoPin.py index c960b1c4..03a4e29e 100644 --- a/src/faebryk/library/SMDTwoPin.py +++ b/src/faebryk/library/SMDTwoPin.py @@ -24,7 +24,7 @@ def __init__(self, type: Type) -> None: super().__init__() self._type = type - pins = L.node_list(2, F.Pad) + pins = L.list_field(2, F.Pad) class _has_kicad_footprint(F.has_kicad_footprint_equal_ifs): def get_kicad_footprint(self) -> str: diff --git a/src/faebryk/library/SNx4LVC541A.py b/src/faebryk/library/SNx4LVC541A.py index e097440c..3cbf9df2 100644 --- a/src/faebryk/library/SNx4LVC541A.py +++ b/src/faebryk/library/SNx4LVC541A.py @@ -17,12 +17,12 @@ class SNx4LVC541A(Module): # ---------------------------------------- # modules, interfaces, parameters # ---------------------------------------- - A = L.node_list(8, F.ElectricLogic) - Y = L.node_list(8, F.ElectricLogic) + A = L.list_field(8, F.ElectricLogic) + Y = L.list_field(8, F.ElectricLogic) power: F.ElectricPower - OE = L.node_list(2, F.ElectricLogic) + OE = L.list_field(2, F.ElectricLogic) # ---------------------------------------- # traits diff --git a/src/faebryk/library/Sercom.py b/src/faebryk/library/Sercom.py index a8623915..ca3b42df 100644 --- a/src/faebryk/library/Sercom.py +++ b/src/faebryk/library/Sercom.py @@ -7,7 +7,7 @@ class Sercom(ModuleInterface): - unnamed = L.node_list(4, F.ElectricLogic) + unnamed = L.list_field(4, F.ElectricLogic) @L.rt_field def single_electric_reference(self): diff --git a/src/faebryk/library/Switch.py b/src/faebryk/library/Switch.py index fbd990dd..a18eda04 100644 --- a/src/faebryk/library/Switch.py +++ b/src/faebryk/library/Switch.py @@ -29,7 +29,7 @@ def __init__(self) -> None: designator_prefix = L.f_field(F.has_designator_prefix_defined)("SW") attach_to_footprint: F.can_attach_to_footprint_symmetrically - unnamed = L.node_list(2, interface_type) + unnamed = L.list_field(2, interface_type) @L.rt_field def can_bridge(self): diff --git a/src/faebryk/library/TXS0102DCUR.py b/src/faebryk/library/TXS0102DCUR.py index ec63c335..2fa0bf11 100644 --- a/src/faebryk/library/TXS0102DCUR.py +++ b/src/faebryk/library/TXS0102DCUR.py @@ -29,7 +29,7 @@ def can_bridge(self): voltage_b_power: F.ElectricPower n_oe: F.ElectricLogic - shifters = L.node_list(2, _BidirectionalLevelShifter) + shifters = L.list_field(2, _BidirectionalLevelShifter) def __preinit__(self): gnd = self.voltage_a_power.lv diff --git a/src/faebryk/library/USB2514B.py b/src/faebryk/library/USB2514B.py index 966b3195..6dd50c6a 100644 --- a/src/faebryk/library/USB2514B.py +++ b/src/faebryk/library/USB2514B.py @@ -26,7 +26,7 @@ class InterfaceConfiguration(Enum): VBUS_DET: F.Electrical - usb_downstream = L.node_list(4, F.DifferentialPair) + usb_downstream = L.list_field(4, F.DifferentialPair) usb_upstream = F.DifferentialPair XTALIN: F.Electrical @@ -36,18 +36,18 @@ class InterfaceConfiguration(Enum): SUSP_IND: F.ElectricLogic RESET_N: F.Electrical RBIAS: F.Electrical - NON_REM = L.node_list(2, F.ElectricLogic) + NON_REM = L.list_field(2, F.ElectricLogic) LOCAL_PWR: F.Electrical CLKIN: F.Electrical - CFG_SEL = L.node_list(2, F.ElectricLogic) + CFG_SEL = L.list_field(2, F.ElectricLogic) HS_IND: F.ElectricLogic - PRTPWR = L.node_list(4, F.ElectricLogic) - PRT_DIS_P = L.node_list(4, F.ElectricLogic) - PRT_DIS_M = L.node_list(4, F.ElectricLogic) - OCS_N = L.node_list(4, F.ElectricLogic) - BC_EN = L.node_list(4, F.ElectricLogic) + PRTPWR = L.list_field(4, F.ElectricLogic) + PRT_DIS_P = L.list_field(4, F.ElectricLogic) + PRT_DIS_M = L.list_field(4, F.ElectricLogic) + OCS_N = L.list_field(4, F.ElectricLogic) + BC_EN = L.list_field(4, F.ElectricLogic) i2c: F.I2C gnd: F.Electrical diff --git a/src/faebryk/library/USB2_0_ESD_Protection.py b/src/faebryk/library/USB2_0_ESD_Protection.py index 436b171a..295c2c02 100644 --- a/src/faebryk/library/USB2_0_ESD_Protection.py +++ b/src/faebryk/library/USB2_0_ESD_Protection.py @@ -12,7 +12,7 @@ class USB2_0_ESD_Protection(Module): - usb = L.node_list(2, F.USB2_0) + usb = L.list_field(2, F.USB2_0) vbus_esd_protection: F.TBD[bool] data_esd_protection: F.TBD[bool] diff --git a/src/faebryk/library/USB_C_5V_PSU.py b/src/faebryk/library/USB_C_5V_PSU.py index 265fcd3d..f4b91241 100644 --- a/src/faebryk/library/USB_C_5V_PSU.py +++ b/src/faebryk/library/USB_C_5V_PSU.py @@ -13,7 +13,7 @@ class USB_C_5V_PSU(Module): usb: F.USB_C # components - configuration_resistors = L.node_list( + configuration_resistors = L.list_field( 2, lambda: F.Resistor().builder( lambda r: r.resistance.merge(F.Constant(5.1 * P.kohm)) diff --git a/src/faebryk/library/USB_C_PSU_Vertical.py b/src/faebryk/library/USB_C_PSU_Vertical.py index e0f688ce..02626e07 100644 --- a/src/faebryk/library/USB_C_PSU_Vertical.py +++ b/src/faebryk/library/USB_C_PSU_Vertical.py @@ -15,7 +15,7 @@ class USB_C_PSU_Vertical(Module): # components usb_connector: F.USB_Type_C_Receptacle_14_pin_Vertical # TODO: make generic - configuration_resistors = L.node_list(2, F.Resistor) + configuration_resistors = L.list_field(2, F.Resistor) gnd_resistor: F.Resistor gnd_capacitor: F.Capacitor esd: F.USB2_0_ESD_Protection diff --git a/src/faebryk/library/USB_RS485.py b/src/faebryk/library/USB_RS485.py index ae98f0f1..3c5cb885 100644 --- a/src/faebryk/library/USB_RS485.py +++ b/src/faebryk/library/USB_RS485.py @@ -15,7 +15,7 @@ class USB_RS485(Module): usb_uart: F.CH340x uart_rs485: F.UART_RS485 termination: F.Resistor - polarization = L.node_list(2, F.Resistor) + polarization = L.list_field(2, F.Resistor) usb: F.USB2_0 rs485: F.RS485 diff --git a/src/faebryk/library/USB_Type_C_Receptacle_24_pin.py b/src/faebryk/library/USB_Type_C_Receptacle_24_pin.py index 92192bbd..a0b0774d 100644 --- a/src/faebryk/library/USB_Type_C_Receptacle_24_pin.py +++ b/src/faebryk/library/USB_Type_C_Receptacle_24_pin.py @@ -16,8 +16,8 @@ class USB_Type_C_Receptacle_24_pin(Module): sbu2: F.Electrical shield: F.Electrical # power - gnd = L.node_list(4, F.Electrical) - vbus = L.node_list(4, F.Electrical) + gnd = L.list_field(4, F.Electrical) + vbus = L.list_field(4, F.Electrical) # diffpairs: p, n rx1: F.DifferentialPair rx2: F.DifferentialPair diff --git a/src/faebryk/library/pf_533984002.py b/src/faebryk/library/pf_533984002.py index 42c6bfbb..df90b1ff 100644 --- a/src/faebryk/library/pf_533984002.py +++ b/src/faebryk/library/pf_533984002.py @@ -8,8 +8,8 @@ class pf_533984002(Module): # interfaces - pin = L.node_list(2, F.Electrical) - mount = L.node_list(2, F.Electrical) + pin = L.list_field(2, F.Electrical) + mount = L.list_field(2, F.Electrical) @L.rt_field def attach_to_footprint(self): diff --git a/src/faebryk/libs/library/L.py b/src/faebryk/libs/library/L.py index 452f080e..bc331c4e 100644 --- a/src/faebryk/libs/library/L.py +++ b/src/faebryk/libs/library/L.py @@ -8,7 +8,7 @@ Node, d_field, f_field, - node_list, + list_field, rt_field, ) diff --git a/test/core/test_core.py b/test/core/test_core.py index a7aadd6b..c7bb67be 100644 --- a/test/core/test_core.py +++ b/test/core/test_core.py @@ -216,7 +216,7 @@ def test_fab_ll_simple_hierarchy(self): class N(Node): SN1: Node SN2: Node - SN3 = L.node_list(2, Node) + SN3 = L.list_field(2, Node) @L.rt_field def SN4(self): diff --git a/test/core/test_hierarchy_connect.py b/test/core/test_hierarchy_connect.py index 9ddef5b1..4784b0bb 100644 --- a/test/core/test_hierarchy_connect.py +++ b/test/core/test_hierarchy_connect.py @@ -85,11 +85,11 @@ def test_bridge(self): # R -------- R ----- R -------- R class Buffer(Module): - ins = L.node_list(2, F.Electrical) - outs = L.node_list(2, F.Electrical) + ins = L.list_field(2, F.Electrical) + outs = L.list_field(2, F.Electrical) - ins_l = L.node_list(2, F.ElectricLogic) - outs_l = L.node_list(2, F.ElectricLogic) + ins_l = L.list_field(2, F.ElectricLogic) + outs_l = L.list_field(2, F.ElectricLogic) def __preinit__(self) -> None: self_.assertIs( diff --git a/test/core/test_performance.py b/test/core/test_performance.py index 90612ce8..e380aed1 100644 --- a/test/core/test_performance.py +++ b/test/core/test_performance.py @@ -47,7 +47,7 @@ class TestPerformance(unittest.TestCase): def test_get_all(self): def _factory_simple_resistors(count: int): class App(Module): - resistors = L.node_list(count, F.Resistor) + resistors = L.list_field(count, F.Resistor) def __init__(self, timings: Times) -> None: super().__init__() @@ -60,7 +60,7 @@ def __preinit__(self): def _factory_interconnected_resistors(count: int): class App(Module): - resistors = L.node_list(count, F.Resistor) + resistors = L.list_field(count, F.Resistor) def __init__(self, timings: Times) -> None: super().__init__()