From c95a8ee6fbde8f70e85dd1317dbe09be6b0769d5 Mon Sep 17 00:00:00 2001
From: ruben-iteng <94007802+ruben-iteng@users.noreply.github.com>
Date: Thu, 5 Sep 2024 19:13:19 +0200
Subject: [PATCH] Add: missing module interfaces

---
 src/faebryk/library/RS232.py | 6 ++++++
 src/faebryk/library/UART.py  | 2 ++
 2 files changed, 8 insertions(+)

diff --git a/src/faebryk/library/RS232.py b/src/faebryk/library/RS232.py
index 33fad49f..2b82dd83 100644
--- a/src/faebryk/library/RS232.py
+++ b/src/faebryk/library/RS232.py
@@ -9,6 +9,12 @@
 class RS232(ModuleInterface):
     tx: F.ElectricLogic
     rx: F.ElectricLogic
+    dtr: F.ElectricLogic
+    dcd: F.ElectricLogic
+    dsr: F.ElectricLogic
+    ri: F.ElectricLogic
+    rts: F.ElectricLogic
+    cts: F.ElectricLogic
 
     @L.rt_field
     def single_electric_reference(self):
diff --git a/src/faebryk/library/UART.py b/src/faebryk/library/UART.py
index 8d7975c2..ce06605e 100644
--- a/src/faebryk/library/UART.py
+++ b/src/faebryk/library/UART.py
@@ -11,3 +11,5 @@ class UART(ModuleInterface):
     cts: F.ElectricLogic
     dtr: F.ElectricLogic
     dsr: F.ElectricLogic
+    dcd: F.ElectricLogic
+    ri: F.ElectricLogic