diff --git a/examples/iterative_design_nand.py b/examples/iterative_design_nand.py index 36489f0c..f8ae891e 100644 --- a/examples/iterative_design_nand.py +++ b/examples/iterative_design_nand.py @@ -37,7 +37,7 @@ class PowerSource(Module): class XOR_with_NANDS(F.LogicGates.XOR): - nands = L.if_list(4, lambda: F.LogicGates.NAND(F.Constant(2))) + nands = L.node_list(4, lambda: F.LogicGates.NAND(F.Constant(2))) def __init__(self): super().__init__(F.Constant(2)) diff --git a/examples/route.py b/examples/route.py index f4a74e91..5c36ad71 100644 --- a/examples/route.py +++ b/examples/route.py @@ -26,8 +26,8 @@ class SubArray(Module): - unnamed = L.if_list(2, F.Electrical) - resistors = L.if_list(2, F.Resistor) + unnamed = L.node_list(2, F.Electrical) + resistors = L.node_list(2, F.Resistor) def __init__(self, extrude_y: float): super().__init__() @@ -70,8 +70,8 @@ def pcb_routing_stategy_manual(self): [ (0, 0), (2.5, 0), - (2.5, extrude_y), - (0, extrude_y), + (2.5, self._extrude_y), + (0, self._extrude_y), ], ), ] @@ -87,8 +87,8 @@ def pcb_routing_stategy_manual(self): [ (0, 0), (-2.5, 0), - (-2.5, extrude_y), - (0, extrude_y), + (-2.5, self._extrude_y), + (0, self._extrude_y), ], ), ] @@ -99,8 +99,11 @@ def pcb_routing_stategy_manual(self): class ResistorArray(Module): - unnamed = L.if_list(2, F.Electrical) - resistors = L.if_list(2, F.Resistor) + unnamed = L.node_list(2, F.Electrical) + + @L.rt_field + def resistors(self): + return times(self._count, lambda: SubArray(self._extrude_y[1])) def __init__(self, count: int, extrude_y: tuple[float, float]): super().__init__() diff --git a/new_holders_flat.py b/new_holders_flat.py index 936ea129..2b3fda33 100644 --- a/new_holders_flat.py +++ b/new_holders_flat.py @@ -69,7 +69,7 @@ def __preinit__(self): class LED2_WITHEXTRAT_IFS(LED2): extra: list[F.Electrical] = field(default_factory=lambda: times(2, F.Electrical)) - extra2: list[F.Electrical] = L.if_list(2, F.Electrical) + extra2: list[F.Electrical] = L.node_list(2, F.Electrical) @L.rt_field def bridge(self): diff --git a/src/faebryk/core/node.py b/src/faebryk/core/node.py index aa55d496..fb16d74a 100644 --- a/src/faebryk/core/node.py +++ b/src/faebryk/core/node.py @@ -41,7 +41,7 @@ class FieldContainerError(FieldError): pass -def if_list[T: Node](n: int, if_type: type[T]) -> list[T]: +def node_list[T: Node](n: int, if_type: type[T]) -> list[T]: out = d_field(lambda: times(n, if_type)) out.type = if_type return out diff --git a/src/faebryk/exporters/pcb/routing/util.py b/src/faebryk/exporters/pcb/routing/util.py index 824a3868..3e395df6 100644 --- a/src/faebryk/exporters/pcb/routing/util.py +++ b/src/faebryk/exporters/pcb/routing/util.py @@ -98,10 +98,11 @@ def __init__( path: Path | None = None, ): super().__init__() - self.path = path or Path() + self._pads = pads - for pad in pads: + def __preinit__(self): + for pad in self._pads: self.pcb.connect(pad.pcb) self.net_.connect(pad.net) @@ -110,6 +111,8 @@ def add(self, obj: Path.Obj): @property def net(self): + from faebryk.core.util import get_net + net = get_net(self.net_) assert net return net diff --git a/src/faebryk/library/B4B_ZR_SM4_TF.py b/src/faebryk/library/B4B_ZR_SM4_TF.py index 5aaf64ad..a2391a9e 100644 --- a/src/faebryk/library/B4B_ZR_SM4_TF.py +++ b/src/faebryk/library/B4B_ZR_SM4_TF.py @@ -7,8 +7,8 @@ class B4B_ZR_SM4_TF(Module): - pin = L.if_list(4, F.Electrical) - mount = L.if_list(2, F.Electrical) + pin = L.node_list(4, F.Electrical) + mount = L.node_list(2, F.Electrical) datasheet = L.f_field(F.has_datasheet_defined)( "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2304140030_BOOMELE-Boom-Precision-Elec-1-5-4P_C145997.pdf" diff --git a/src/faebryk/library/Button.py b/src/faebryk/library/Button.py index 6a41d491..85d7d8be 100644 --- a/src/faebryk/library/Button.py +++ b/src/faebryk/library/Button.py @@ -11,7 +11,7 @@ class Button(Module): - unnamed = L.if_list(2, F.Electrical) + unnamed = L.node_list(2, F.Electrical) designator_prefix = L.f_field(F.has_designator_prefix_defined)("S") diff --git a/src/faebryk/library/CBM9002A_56ILG.py b/src/faebryk/library/CBM9002A_56ILG.py index 81ab71f9..ea40cbc2 100644 --- a/src/faebryk/library/CBM9002A_56ILG.py +++ b/src/faebryk/library/CBM9002A_56ILG.py @@ -16,17 +16,17 @@ class CBM9002A_56ILG(Module): # ---------------------------------------- # modules, interfaces, parameters # ---------------------------------------- - PA = L.if_list(8, F.ElectricLogic) - PB = L.if_list(8, F.ElectricLogic) - PD = L.if_list(8, F.ElectricLogic) + PA = L.node_list(8, F.ElectricLogic) + PB = L.node_list(8, F.ElectricLogic) + PD = L.node_list(8, F.ElectricLogic) usb: F.USB2_0 i2c: F.I2C avcc: F.ElectricPower vcc: F.ElectricPower - rdy = L.if_list(2, F.ElectricLogic) - ctl = L.if_list(3, F.ElectricLogic) + rdy = L.node_list(2, F.ElectricLogic) + ctl = L.node_list(3, F.ElectricLogic) reset: F.ElectricLogic wakeup: F.ElectricLogic diff --git a/src/faebryk/library/CBM9002A_56ILG_Reference_Design.py b/src/faebryk/library/CBM9002A_56ILG_Reference_Design.py index 7e6edc1f..ee0d2088 100644 --- a/src/faebryk/library/CBM9002A_56ILG_Reference_Design.py +++ b/src/faebryk/library/CBM9002A_56ILG_Reference_Design.py @@ -20,17 +20,17 @@ class CBM9002A_56ILG_Reference_Design(Module): reset_lowpass_cap: F.Capacitor oscillator: F.Crystal_Oscillator - PA = L.if_list(8, F.ElectricLogic) - PB = L.if_list(8, F.ElectricLogic) - PD = L.if_list(8, F.ElectricLogic) + PA = L.node_list(8, F.ElectricLogic) + PB = L.node_list(8, F.ElectricLogic) + PD = L.node_list(8, F.ElectricLogic) usb: F.USB2_0 i2c: F.I2C avcc: F.ElectricPower vcc: F.ElectricPower - rdy = L.if_list(2, F.ElectricLogic) - ctl = L.if_list(3, F.ElectricLogic) + rdy = L.node_list(2, F.ElectricLogic) + ctl = L.node_list(3, F.ElectricLogic) reset: F.ElectricLogic wakeup: F.ElectricLogic diff --git a/src/faebryk/library/Capacitor.py b/src/faebryk/library/Capacitor.py index 9519b01d..a84cf4fd 100644 --- a/src/faebryk/library/Capacitor.py +++ b/src/faebryk/library/Capacitor.py @@ -23,7 +23,7 @@ class TemperatureCoefficient(IntEnum): X8R = auto() C0G = auto() - unnamed = L.if_list(2, F.Electrical) + unnamed = L.node_list(2, F.Electrical) capacitance: F.TBD[Quantity] rated_voltage: F.TBD[Quantity] diff --git a/src/faebryk/library/Common_Mode_Filter.py b/src/faebryk/library/Common_Mode_Filter.py index f85c1466..16dcbdc2 100644 --- a/src/faebryk/library/Common_Mode_Filter.py +++ b/src/faebryk/library/Common_Mode_Filter.py @@ -11,7 +11,7 @@ class Common_Mode_Filter(Module): - c_a = L.if_list(2, F.Electrical) - c_b = L.if_list(2, F.Electrical) + c_a = L.node_list(2, F.Electrical) + c_b = L.node_list(2, F.Electrical) designator_prefix = L.f_field(F.has_designator_prefix_defined)("FL") diff --git a/src/faebryk/library/Crystal.py b/src/faebryk/library/Crystal.py index 8a1963bc..f4b6ace8 100644 --- a/src/faebryk/library/Crystal.py +++ b/src/faebryk/library/Crystal.py @@ -21,7 +21,7 @@ class Crystal(Module): load_impedance: F.TBD[Quantity] gnd: F.Electrical - unnamed = L.if_list(2, F.Electrical) + unnamed = L.node_list(2, F.Electrical) # ---------------------------------------- # parameters diff --git a/src/faebryk/library/Crystal_Oscillator.py b/src/faebryk/library/Crystal_Oscillator.py index 53954d25..085582ff 100644 --- a/src/faebryk/library/Crystal_Oscillator.py +++ b/src/faebryk/library/Crystal_Oscillator.py @@ -15,7 +15,7 @@ class Crystal_Oscillator(Module): # modules, interfaces, parameters # ---------------------------------------- crystal: F.Crystal - capacitors = L.if_list(2, F.Capacitor) + capacitors = L.node_list(2, F.Capacitor) power: F.ElectricPower p: F.Electrical diff --git a/src/faebryk/library/EEPROM.py b/src/faebryk/library/EEPROM.py index f2a885e1..d0624bb7 100644 --- a/src/faebryk/library/EEPROM.py +++ b/src/faebryk/library/EEPROM.py @@ -30,7 +30,7 @@ def set_address(self, addr: int): power: F.ElectricPower i2c: F.I2C write_protect: F.ElectricLogic - address = L.if_list(3, F.ElectricLogic) + address = L.node_list(3, F.ElectricLogic) # ---------------------------------------- # traits diff --git a/src/faebryk/library/ESP32.py b/src/faebryk/library/ESP32.py index 4b684736..222ef533 100644 --- a/src/faebryk/library/ESP32.py +++ b/src/faebryk/library/ESP32.py @@ -27,15 +27,15 @@ def CHANNELS(self): class _ESP_SDIO(ModuleInterface): - DATA = L.if_list(4, F.Electrical) + DATA = L.node_list(4, F.Electrical) CLK: F.Electrical CMD: F.Electrical GND: F.Electrical class _ESP32_EMAC(ModuleInterface): - TXD = L.if_list(4, F.Electrical) - RXD = L.if_list(4, F.Electrical) + TXD = L.node_list(4, F.Electrical) + RXD = L.node_list(4, F.Electrical) TX_CLK: F.Electrical RX_CLK: F.Electrical TX_EN: F.Electrical @@ -123,14 +123,14 @@ class ESP32(Module): GND: F.Electrical # High Level Functions - F.I2C = L.if_list(2, F.I2C) + F.I2C = L.node_list(2, F.I2C) SDIO_SLAVE: _ESP_SDIO - SDIO_HOST = L.if_list(2, _ESP_SDIO) + SDIO_HOST = L.node_list(2, _ESP_SDIO) UART: F.UART_Base JTAG: F.JTAG - TOUCH = L.if_list(10, F.Electrical) - GPIO = L.if_list(40 - 6, F.Electrical) - RTC_GPIO = L.if_list(18, F.Electrical) + TOUCH = L.node_list(10, F.Electrical) + GPIO = L.node_list(40 - 6, F.Electrical) + RTC_GPIO = L.node_list(18, F.Electrical) ADC = L.d_field( lambda: ( None, @@ -138,7 +138,7 @@ class ESP32(Module): _ESP_ADC(channel_count=10), ) ) - SPI = L.if_list(4, _ESP32_SPI) + SPI = L.node_list(4, _ESP32_SPI) EMAC: _ESP32_EMAC # Power diff --git a/src/faebryk/library/ESP32_C3.py b/src/faebryk/library/ESP32_C3.py index 86896a10..a054bf29 100644 --- a/src/faebryk/library/ESP32_C3.py +++ b/src/faebryk/library/ESP32_C3.py @@ -23,11 +23,11 @@ class ESP32_C3(Module): enable: F.ElectricLogic xtal_p: F.Electrical xtal_n: F.Electrical - gpio = L.if_list(22, F.ElectricLogic) + gpio = L.node_list(22, F.ElectricLogic) # TODO: map peripherals to GPIOs with pinmux usb: F.USB2_0 i2c: F.I2C - uart = L.if_list(2, F.UART_Base) + uart = L.node_list(2, F.UART_Base) # ... etc designator_prefix = L.f_field(F.has_designator_prefix_defined)("U") diff --git a/src/faebryk/library/ESP32_C3_MINI_1.py b/src/faebryk/library/ESP32_C3_MINI_1.py index f65d6b60..fca437d4 100644 --- a/src/faebryk/library/ESP32_C3_MINI_1.py +++ b/src/faebryk/library/ESP32_C3_MINI_1.py @@ -18,7 +18,7 @@ class ESP32_C3_MINI_1(Module): rf_output: F.Electrical chip_enable: F.ElectricLogic - gpio = L.if_list( + gpio = L.node_list( 22, F.ElectricLogic ) # TODO: Only GPIO 0 to 10 and 18, 19 are exposed uart: F.UART_Base diff --git a/src/faebryk/library/Fuse.py b/src/faebryk/library/Fuse.py index c24203ed..861d8142 100644 --- a/src/faebryk/library/Fuse.py +++ b/src/faebryk/library/Fuse.py @@ -21,7 +21,7 @@ class ResponseType(Enum): SLOW = auto() FAST = auto() - unnamed = L.if_list(2, F.Electrical) + unnamed = L.node_list(2, F.Electrical) fuse_type: F.TBD[FuseType] response_type: F.TBD[ResponseType] trip_current: F.TBD[Quantity] diff --git a/src/faebryk/library/GenericBusProtection.py b/src/faebryk/library/GenericBusProtection.py index 07dc46f4..894c9fbc 100644 --- a/src/faebryk/library/GenericBusProtection.py +++ b/src/faebryk/library/GenericBusProtection.py @@ -45,7 +45,7 @@ def get_mifs[U: ModuleInterface](bus: T, mif_type: type[U]) -> set[U]: ) ) - fuse = L.if_list(len(power), F.Fuse) + fuse = L.node_list(len(power), F.Fuse) # Pass through except hv for power_unprotected, power_protected in power: diff --git a/src/faebryk/library/Inductor.py b/src/faebryk/library/Inductor.py index c624adf3..c40eb9aa 100644 --- a/src/faebryk/library/Inductor.py +++ b/src/faebryk/library/Inductor.py @@ -9,7 +9,7 @@ class Inductor(Module): - unnamed = L.if_list(2, F.Electrical) + unnamed = L.node_list(2, F.Electrical) inductance: F.TBD[Quantity] self_resonant_frequency: F.TBD[Quantity] diff --git a/src/faebryk/library/LogicGate.py b/src/faebryk/library/LogicGate.py index 731741ee..d9917341 100644 --- a/src/faebryk/library/LogicGate.py +++ b/src/faebryk/library/LogicGate.py @@ -56,7 +56,7 @@ def __init__( super().__init__() self._input_cnt = input_cnt self._output_cnt = output_cnt - self._functions = functions + self._functions = list(functions) @L.rt_field def functions(self): diff --git a/src/faebryk/library/M24C08_FMN6TP.py b/src/faebryk/library/M24C08_FMN6TP.py index 5751c6af..b99ad729 100644 --- a/src/faebryk/library/M24C08_FMN6TP.py +++ b/src/faebryk/library/M24C08_FMN6TP.py @@ -16,7 +16,7 @@ class M24C08_FMN6TP(Module): power: F.ElectricPower data: F.I2C nwc: F.ElectricLogic - e = L.if_list(3, F.ElectricLogic) + e = L.node_list(3, F.ElectricLogic) @L.rt_field def attach_to_footprint(self): diff --git a/src/faebryk/library/MCP2221A.py b/src/faebryk/library/MCP2221A.py index 20751227..00972f07 100644 --- a/src/faebryk/library/MCP2221A.py +++ b/src/faebryk/library/MCP2221A.py @@ -15,7 +15,7 @@ class MCP2221A(Module): power_vusb: F.ElectricPower uart: F.UART_Base i2c: F.I2C - gpio = L.if_list(4, F.Electrical) + gpio = L.node_list(4, F.Electrical) reset: F.ElectricLogic usb: F.USB2_0 diff --git a/src/faebryk/library/Potentiometer.py b/src/faebryk/library/Potentiometer.py index 568775e4..09047a6f 100644 --- a/src/faebryk/library/Potentiometer.py +++ b/src/faebryk/library/Potentiometer.py @@ -8,10 +8,10 @@ class Potentiometer(Module): - resistors_ifs = L.if_list(2, F.Electrical) + resistors_ifs = L.node_list(2, F.Electrical) wiper: F.Electrical total_resistance: F.TBD[Quantity] - resistors = L.if_list(2, F.Resistor) + resistors = L.node_list(2, F.Resistor) def __preinit__(self): for i, resistor in enumerate(self.resistors): diff --git a/src/faebryk/library/RJ45_Receptacle.py b/src/faebryk/library/RJ45_Receptacle.py index 47a619e5..55ccd2e6 100644 --- a/src/faebryk/library/RJ45_Receptacle.py +++ b/src/faebryk/library/RJ45_Receptacle.py @@ -15,7 +15,7 @@ class Mounting(Enum): # interfaces - pin = L.if_list(8, F.Electrical) + pin = L.node_list(8, F.Electrical) shield: F.Electrical designator_prefix = L.f_field(F.has_designator_prefix_defined)("J") diff --git a/src/faebryk/library/RP2040.py b/src/faebryk/library/RP2040.py index 08574d76..daf1db79 100644 --- a/src/faebryk/library/RP2040.py +++ b/src/faebryk/library/RP2040.py @@ -17,7 +17,7 @@ class RP2040(Module): vreg_in: F.ElectricPower vreg_out: F.ElectricPower power_vusb: F.ElectricPower - gpio = L.if_list(30, F.Electrical) + gpio = L.node_list(30, F.Electrical) run: F.ElectricLogic usb: F.USB2_0 qspi = L.f_field(F.MultiSPI)(data_lane_count=4) diff --git a/src/faebryk/library/RP2040_Reference_Design.py b/src/faebryk/library/RP2040_Reference_Design.py index ec027400..907c0399 100644 --- a/src/faebryk/library/RP2040_Reference_Design.py +++ b/src/faebryk/library/RP2040_Reference_Design.py @@ -26,7 +26,7 @@ class RP2040_Reference_Design(Module): rp2040: F.RP2040 flash: F.SPIFlash led: F.PoweredLED - usb_current_limit_resistor = L.if_list(2, F.Resistor) + usb_current_limit_resistor = L.node_list(2, F.Resistor) # TODO: add crystal oscillator # TODO: add voltage divider with switch # TODO: add boot button diff --git a/src/faebryk/library/RS485_Bus_Protection.py b/src/faebryk/library/RS485_Bus_Protection.py index 7744ebb6..2f652768 100644 --- a/src/faebryk/library/RS485_Bus_Protection.py +++ b/src/faebryk/library/RS485_Bus_Protection.py @@ -34,11 +34,11 @@ def __init__(self, termination: bool = True, polarization: bool = True) -> None: gdt: F.GDT tvs: F.TVS - current_limmiter_resistors = L.if_list(2, F.Resistor) + current_limmiter_resistors = L.node_list(2, F.Resistor) common_mode_filter: F.Common_Mode_Filter gnd_couple_resistor: F.Resistor gnd_couple_capacitor: F.Capacitor - clamping_diodes = L.if_list(2, F.Diode) + clamping_diodes = L.node_list(2, F.Diode) power: F.ElectricPower rs485_in: F.RS485 rs485_out: F.RS485 diff --git a/src/faebryk/library/Resistor.py b/src/faebryk/library/Resistor.py index 7f6a5a1e..b392423a 100644 --- a/src/faebryk/library/Resistor.py +++ b/src/faebryk/library/Resistor.py @@ -12,7 +12,7 @@ class Resistor(Module): - unnamed = L.if_list(2, F.Electrical) + unnamed = L.node_list(2, F.Electrical) resistance: F.TBD[Quantity] rated_power: F.TBD[Quantity] diff --git a/src/faebryk/library/Resistor_Voltage_Divider.py b/src/faebryk/library/Resistor_Voltage_Divider.py index 0d589288..a402d1ad 100644 --- a/src/faebryk/library/Resistor_Voltage_Divider.py +++ b/src/faebryk/library/Resistor_Voltage_Divider.py @@ -12,8 +12,8 @@ class Resistor_Voltage_Divider(Module): - resistor = L.if_list(2, F.Resistor) - node = L.if_list(3, F.Electrical) + resistor = L.node_list(2, F.Resistor) + node = L.node_list(3, F.Electrical) ratio: F.TBD[Quantity] max_current: F.TBD[Quantity] diff --git a/src/faebryk/library/SMDTwoPin.py b/src/faebryk/library/SMDTwoPin.py index 5d95833a..c960b1c4 100644 --- a/src/faebryk/library/SMDTwoPin.py +++ b/src/faebryk/library/SMDTwoPin.py @@ -24,7 +24,7 @@ def __init__(self, type: Type) -> None: super().__init__() self._type = type - pins = L.if_list(2, F.Pad) + pins = L.node_list(2, F.Pad) class _has_kicad_footprint(F.has_kicad_footprint_equal_ifs): def get_kicad_footprint(self) -> str: diff --git a/src/faebryk/library/SNx4LVC541A.py b/src/faebryk/library/SNx4LVC541A.py index b6869fd4..e097440c 100644 --- a/src/faebryk/library/SNx4LVC541A.py +++ b/src/faebryk/library/SNx4LVC541A.py @@ -17,12 +17,12 @@ class SNx4LVC541A(Module): # ---------------------------------------- # modules, interfaces, parameters # ---------------------------------------- - A = L.if_list(8, F.ElectricLogic) - Y = L.if_list(8, F.ElectricLogic) + A = L.node_list(8, F.ElectricLogic) + Y = L.node_list(8, F.ElectricLogic) power: F.ElectricPower - OE = L.if_list(2, F.ElectricLogic) + OE = L.node_list(2, F.ElectricLogic) # ---------------------------------------- # traits diff --git a/src/faebryk/library/Sercom.py b/src/faebryk/library/Sercom.py index 11d8f1ca..a8623915 100644 --- a/src/faebryk/library/Sercom.py +++ b/src/faebryk/library/Sercom.py @@ -7,7 +7,7 @@ class Sercom(ModuleInterface): - unnamed = L.if_list(4, F.ElectricLogic) + unnamed = L.node_list(4, F.ElectricLogic) @L.rt_field def single_electric_reference(self): diff --git a/src/faebryk/library/Switch.py b/src/faebryk/library/Switch.py index c3f8cb28..fbd990dd 100644 --- a/src/faebryk/library/Switch.py +++ b/src/faebryk/library/Switch.py @@ -29,7 +29,7 @@ def __init__(self) -> None: designator_prefix = L.f_field(F.has_designator_prefix_defined)("SW") attach_to_footprint: F.can_attach_to_footprint_symmetrically - unnamed = L.if_list(2, interface_type) + unnamed = L.node_list(2, interface_type) @L.rt_field def can_bridge(self): diff --git a/src/faebryk/library/TXS0102DCUR.py b/src/faebryk/library/TXS0102DCUR.py index f0789fdf..ec63c335 100644 --- a/src/faebryk/library/TXS0102DCUR.py +++ b/src/faebryk/library/TXS0102DCUR.py @@ -29,7 +29,7 @@ def can_bridge(self): voltage_b_power: F.ElectricPower n_oe: F.ElectricLogic - shifters = L.if_list(2, _BidirectionalLevelShifter) + shifters = L.node_list(2, _BidirectionalLevelShifter) def __preinit__(self): gnd = self.voltage_a_power.lv diff --git a/src/faebryk/library/USB2514B.py b/src/faebryk/library/USB2514B.py index 1eed0cab..966b3195 100644 --- a/src/faebryk/library/USB2514B.py +++ b/src/faebryk/library/USB2514B.py @@ -26,7 +26,7 @@ class InterfaceConfiguration(Enum): VBUS_DET: F.Electrical - usb_downstream = L.if_list(4, F.DifferentialPair) + usb_downstream = L.node_list(4, F.DifferentialPair) usb_upstream = F.DifferentialPair XTALIN: F.Electrical @@ -36,18 +36,18 @@ class InterfaceConfiguration(Enum): SUSP_IND: F.ElectricLogic RESET_N: F.Electrical RBIAS: F.Electrical - NON_REM = L.if_list(2, F.ElectricLogic) + NON_REM = L.node_list(2, F.ElectricLogic) LOCAL_PWR: F.Electrical CLKIN: F.Electrical - CFG_SEL = L.if_list(2, F.ElectricLogic) + CFG_SEL = L.node_list(2, F.ElectricLogic) HS_IND: F.ElectricLogic - PRTPWR = L.if_list(4, F.ElectricLogic) - PRT_DIS_P = L.if_list(4, F.ElectricLogic) - PRT_DIS_M = L.if_list(4, F.ElectricLogic) - OCS_N = L.if_list(4, F.ElectricLogic) - BC_EN = L.if_list(4, F.ElectricLogic) + PRTPWR = L.node_list(4, F.ElectricLogic) + PRT_DIS_P = L.node_list(4, F.ElectricLogic) + PRT_DIS_M = L.node_list(4, F.ElectricLogic) + OCS_N = L.node_list(4, F.ElectricLogic) + BC_EN = L.node_list(4, F.ElectricLogic) i2c: F.I2C gnd: F.Electrical diff --git a/src/faebryk/library/USB2_0_ESD_Protection.py b/src/faebryk/library/USB2_0_ESD_Protection.py index d6c58f7d..436b171a 100644 --- a/src/faebryk/library/USB2_0_ESD_Protection.py +++ b/src/faebryk/library/USB2_0_ESD_Protection.py @@ -12,7 +12,7 @@ class USB2_0_ESD_Protection(Module): - usb = L.if_list(2, F.USB2_0) + usb = L.node_list(2, F.USB2_0) vbus_esd_protection: F.TBD[bool] data_esd_protection: F.TBD[bool] diff --git a/src/faebryk/library/USB_C_5V_PSU.py b/src/faebryk/library/USB_C_5V_PSU.py index 2f0950b9..265fcd3d 100644 --- a/src/faebryk/library/USB_C_5V_PSU.py +++ b/src/faebryk/library/USB_C_5V_PSU.py @@ -13,7 +13,7 @@ class USB_C_5V_PSU(Module): usb: F.USB_C # components - configuration_resistors = L.if_list( + configuration_resistors = L.node_list( 2, lambda: F.Resistor().builder( lambda r: r.resistance.merge(F.Constant(5.1 * P.kohm)) diff --git a/src/faebryk/library/USB_C_PSU_Vertical.py b/src/faebryk/library/USB_C_PSU_Vertical.py index c58cf23a..e0f688ce 100644 --- a/src/faebryk/library/USB_C_PSU_Vertical.py +++ b/src/faebryk/library/USB_C_PSU_Vertical.py @@ -15,7 +15,7 @@ class USB_C_PSU_Vertical(Module): # components usb_connector: F.USB_Type_C_Receptacle_14_pin_Vertical # TODO: make generic - configuration_resistors = L.if_list(2, F.Resistor) + configuration_resistors = L.node_list(2, F.Resistor) gnd_resistor: F.Resistor gnd_capacitor: F.Capacitor esd: F.USB2_0_ESD_Protection diff --git a/src/faebryk/library/USB_RS485.py b/src/faebryk/library/USB_RS485.py index 5d37a8e6..ae98f0f1 100644 --- a/src/faebryk/library/USB_RS485.py +++ b/src/faebryk/library/USB_RS485.py @@ -15,7 +15,7 @@ class USB_RS485(Module): usb_uart: F.CH340x uart_rs485: F.UART_RS485 termination: F.Resistor - polarization = L.if_list(2, F.Resistor) + polarization = L.node_list(2, F.Resistor) usb: F.USB2_0 rs485: F.RS485 diff --git a/src/faebryk/library/USB_Type_C_Receptacle_24_pin.py b/src/faebryk/library/USB_Type_C_Receptacle_24_pin.py index 418f0c4d..92192bbd 100644 --- a/src/faebryk/library/USB_Type_C_Receptacle_24_pin.py +++ b/src/faebryk/library/USB_Type_C_Receptacle_24_pin.py @@ -16,8 +16,8 @@ class USB_Type_C_Receptacle_24_pin(Module): sbu2: F.Electrical shield: F.Electrical # power - gnd = L.if_list(4, F.Electrical) - vbus = L.if_list(4, F.Electrical) + gnd = L.node_list(4, F.Electrical) + vbus = L.node_list(4, F.Electrical) # diffpairs: p, n rx1: F.DifferentialPair rx2: F.DifferentialPair diff --git a/src/faebryk/library/pf_533984002.py b/src/faebryk/library/pf_533984002.py index 627af979..42c6bfbb 100644 --- a/src/faebryk/library/pf_533984002.py +++ b/src/faebryk/library/pf_533984002.py @@ -8,8 +8,8 @@ class pf_533984002(Module): # interfaces - pin = L.if_list(2, F.Electrical) - mount = L.if_list(2, F.Electrical) + pin = L.node_list(2, F.Electrical) + mount = L.node_list(2, F.Electrical) @L.rt_field def attach_to_footprint(self): diff --git a/src/faebryk/libs/library/L.py b/src/faebryk/libs/library/L.py index 16f40cf9..452f080e 100644 --- a/src/faebryk/libs/library/L.py +++ b/src/faebryk/libs/library/L.py @@ -8,7 +8,7 @@ Node, d_field, f_field, - if_list, + node_list, rt_field, ) diff --git a/test/core/test_core.py b/test/core/test_core.py index ab99dad4..a7aadd6b 100644 --- a/test/core/test_core.py +++ b/test/core/test_core.py @@ -216,7 +216,7 @@ def test_fab_ll_simple_hierarchy(self): class N(Node): SN1: Node SN2: Node - SN3 = L.if_list(2, Node) + SN3 = L.node_list(2, Node) @L.rt_field def SN4(self): diff --git a/test/core/test_hierarchy_connect.py b/test/core/test_hierarchy_connect.py index ed9e78b9..9ddef5b1 100644 --- a/test/core/test_hierarchy_connect.py +++ b/test/core/test_hierarchy_connect.py @@ -85,11 +85,11 @@ def test_bridge(self): # R -------- R ----- R -------- R class Buffer(Module): - ins = L.if_list(2, F.Electrical) - outs = L.if_list(2, F.Electrical) + ins = L.node_list(2, F.Electrical) + outs = L.node_list(2, F.Electrical) - ins_l = L.if_list(2, F.ElectricLogic) - outs_l = L.if_list(2, F.ElectricLogic) + ins_l = L.node_list(2, F.ElectricLogic) + outs_l = L.node_list(2, F.ElectricLogic) def __preinit__(self) -> None: self_.assertIs( diff --git a/test/core/test_performance.py b/test/core/test_performance.py index 106b0f3d..90612ce8 100644 --- a/test/core/test_performance.py +++ b/test/core/test_performance.py @@ -47,7 +47,7 @@ class TestPerformance(unittest.TestCase): def test_get_all(self): def _factory_simple_resistors(count: int): class App(Module): - resistors = L.if_list(count, F.Resistor) + resistors = L.node_list(count, F.Resistor) def __init__(self, timings: Times) -> None: super().__init__() @@ -60,7 +60,7 @@ def __preinit__(self): def _factory_interconnected_resistors(count: int): class App(Module): - resistors = L.if_list(count, F.Resistor) + resistors = L.node_list(count, F.Resistor) def __init__(self, timings: Times) -> None: super().__init__()