From 22bdbd696fa3807e3df5c62e47194afb5dd5d6cd Mon Sep 17 00:00:00 2001 From: Ioannis Papamanoglou Date: Wed, 11 Sep 2024 18:01:10 +0200 Subject: [PATCH] Library: Remove Constant for physical params (#53) --- .../CBM9002A_56ILG_Reference_Design.py | 42 +++++++++++-------- src/faebryk/library/QWIIC.py | 2 +- src/faebryk/library/RS485_Bus_Protection.py | 30 ++++++++----- src/faebryk/library/SCD40.py | 13 ++++-- src/faebryk/library/USB_C_5V_PSU.py | 2 +- src/faebryk/library/USB_C_PSU_Vertical.py | 2 +- src/faebryk/library/XL_3528RGBW_WS2812B.py | 13 +++--- 7 files changed, 65 insertions(+), 39 deletions(-) diff --git a/src/faebryk/library/CBM9002A_56ILG_Reference_Design.py b/src/faebryk/library/CBM9002A_56ILG_Reference_Design.py index 00573d34..5225937a 100644 --- a/src/faebryk/library/CBM9002A_56ILG_Reference_Design.py +++ b/src/faebryk/library/CBM9002A_56ILG_Reference_Design.py @@ -12,13 +12,31 @@ class CBM9002A_56ILG_Reference_Design(Module): Minimal working example for the CBM9002A_56ILG """ + class ResetCircuit(Module): + """low-pass and protection for reset""" + + diode: F.Diode + cap: F.Capacitor + logic: F.ElectricLogic + + def __preinit__(self): + self.logic.signal.connect_via(self.diode, self.logic.reference.hv) + self.logic.pulled.pull(up=True) + self.logic.signal.connect_via(self.cap, self.logic.reference.lv) + + self.cap.capacitance.merge(F.Range.from_center_rel(1 * P.uF, 0.05)) + + self.diode.forward_voltage.merge(F.Range(715 * P.mV, 1.5 * P.V)) + self.diode.reverse_leakage_current.merge(F.Range.upper_bound(1 * P.uA)) + self.diode.current.merge(F.Range.from_center_rel(300 * P.mA, 0.05)) + self.diode.max_current.merge(F.Range.lower_bound(1 * P.A)) + # ---------------------------------------- # modules, interfaces, parameters # ---------------------------------------- mcu: F.CBM9002A_56ILG - reset_diode: F.Diode - reset_lowpass_cap: F.Capacitor oscillator: F.Crystal_Oscillator + reset_circuit: ResetCircuit PA = L.list_field(8, F.ElectricLogic) PB = L.list_field(8, F.ElectricLogic) @@ -47,32 +65,22 @@ class CBM9002A_56ILG_Reference_Design(Module): # connections # ---------------------------------------- def __preinit__(self): - gnd = self.vcc.lv self.connect_interfaces_by_name(self.mcu, allow_partial=True) - self.reset.signal.connect_via( - self.reset_lowpass_cap, gnd - ) # TODO: should come from a low pass for electric logic - self.reset.pulled.pull(up=True) - self.reset.signal.connect_via(self.reset_diode, self.vcc.hv) - # crystal oscillator self.oscillator.power.connect(self.vcc) self.oscillator.n.connect(self.xtalin) self.oscillator.p.connect(self.xtalout) + self.reset_circuit.logic.connect(self.mcu.reset) + # ---------------------------------------- # Parameters # ---------------------------------------- - self.reset_lowpass_cap.capacitance.merge(F.Constant(1 * P.uF)) - self.oscillator.crystal.frequency.merge(F.Constant(24 * P.Mhertz)) + self.oscillator.crystal.frequency.merge( + F.Range.from_center_rel(24 * P.Mhertz, 0.05) + ) self.oscillator.crystal.frequency_tolerance.merge( F.Range.upper_bound(20 * P.ppm) ) - - # TODO: just set to a 1N4148 - self.reset_diode.forward_voltage.merge(715 * P.mV) - self.reset_diode.reverse_leakage_current.merge(1 * P.uA) - self.reset_diode.current.merge(300 * P.mA) - self.reset_diode.max_current.merge(1 * P.A) diff --git a/src/faebryk/library/QWIIC.py b/src/faebryk/library/QWIIC.py index a2ae539c..ea476f4c 100644 --- a/src/faebryk/library/QWIIC.py +++ b/src/faebryk/library/QWIIC.py @@ -19,7 +19,7 @@ class QWIIC(Module): def __preinit__(self): # set constraints - self.power.voltage.merge(F.Constant(3.3 * P.V)) + self.power.voltage.merge(F.Range.from_center_rel(3.3 * P.V, 0.05)) # TODO: self.power.source_current.merge(F.Constant(226 * P.mA)) designator_prefix = L.f_field(F.has_designator_prefix_defined)("J") diff --git a/src/faebryk/library/RS485_Bus_Protection.py b/src/faebryk/library/RS485_Bus_Protection.py index 35505630..82089a6d 100644 --- a/src/faebryk/library/RS485_Bus_Protection.py +++ b/src/faebryk/library/RS485_Bus_Protection.py @@ -47,7 +47,9 @@ def __init__(self, termination: bool = True, polarization: bool = True) -> None: def __preinit__(self): if self._termination: termination_resistor = self.add(F.Resistor(), name="termination_resistor") - termination_resistor.resistance.merge(F.Constant(120 * P.ohm)) + termination_resistor.resistance.merge( + F.Range.from_center_rel(120 * P.ohm, 0.05) + ) self.rs485_out.diff_pair.p.connect_via( termination_resistor, self.rs485_out.diff_pair.n ) @@ -67,23 +69,31 @@ def __preinit__(self): polarization_resistors[1], self.power.lv ) - self.current_limmiter_resistors[0].resistance.merge(F.Constant(2.7 * P.ohm)) + self.current_limmiter_resistors[0].resistance.merge( + F.Range.from_center_rel(2.7 * P.ohm, 0.05) + ) # TODO: set power dissipation of resistor to 2W - self.current_limmiter_resistors[1].resistance.merge(F.Constant(2.7 * P.ohm)) + self.current_limmiter_resistors[1].resistance.merge( + F.Range.from_center_rel(2.7 * P.ohm, 0.05) + ) # TODO: set power dissipation of resistor to 2W - self.gnd_couple_resistor.resistance.merge(F.Constant(1 * P.Mohm)) - self.gnd_couple_capacitor.capacitance.merge(F.Constant(1 * P.uF)) + self.gnd_couple_resistor.resistance.merge( + F.Range.from_center_rel(1 * P.Mohm, 0.05) + ) + self.gnd_couple_capacitor.capacitance.merge( + F.Range.from_center_rel(1 * P.uF, 0.05) + ) self.gnd_couple_capacitor.rated_voltage.merge(F.Range.lower_bound(2 * P.kV)) - self.tvs.reverse_working_voltage.merge(F.Constant(8.5 * P.V)) - # self.tvs.max_current.merge(F.Constant(41.7*P.A)) + self.tvs.reverse_working_voltage.merge(F.Range.from_center_rel(8.5 * P.V, 0.05)) + # self.tvs.max_current.merge(F.Range.from_center_rel(41.7*P.A, 0.05)) # self.tvs.forward_voltage.merge(F.Range(9.44*P.V, 10.40*P.V)) for diode in self.clamping_diodes: - diode.forward_voltage.merge(F.Constant(1.1 * P.V)) - diode.max_current.merge(F.Constant(1 * P.A)) - diode.reverse_working_voltage.merge(F.Constant(1 * P.kV)) + diode.forward_voltage.merge(F.Range.from_center_rel(1.1 * P.V, 0.05)) + diode.max_current.merge(F.Range.from_center_rel(1 * P.A, 0.05)) + diode.reverse_working_voltage.merge(F.Range.from_center_rel(1 * P.kV, 0.05)) # connections # earth connections diff --git a/src/faebryk/library/SCD40.py b/src/faebryk/library/SCD40.py index 40f82456..a2ca5208 100644 --- a/src/faebryk/library/SCD40.py +++ b/src/faebryk/library/SCD40.py @@ -18,10 +18,9 @@ class _scd4x_esphome_config(F.has_esphome_config.impl()): def get_config(self) -> dict: val = self.update_interval.get_most_narrow() - assert isinstance(val, F.Constant), "No update interval set!" + assert isinstance(val, F.Constant) - obj = self.obj - assert isinstance(obj, SCD40) + obj = self.get_obj(SCD40) i2c = F.is_esphome_bus.find_connected_bus(obj.i2c) @@ -45,6 +44,12 @@ def get_config(self) -> dict: ] } + def is_implemented(self): + return ( + isinstance(self.update_interval.get_most_narrow(), F.Constant) + and super().is_implemented() + ) + esphome_config: _scd4x_esphome_config # interfaces @@ -66,7 +71,7 @@ def attach_to_footprint(self): ) def __preinit__(self): - self.power.voltage.merge(F.Constant(3.3 * P.V)) + self.power.voltage.merge(F.Range.from_center_rel(3.3 * P.V, 0.05)) self.i2c.terminate() self.power.decoupled.decouple() self.i2c.frequency.merge( diff --git a/src/faebryk/library/USB_C_5V_PSU.py b/src/faebryk/library/USB_C_5V_PSU.py index f4b91241..7340601a 100644 --- a/src/faebryk/library/USB_C_5V_PSU.py +++ b/src/faebryk/library/USB_C_5V_PSU.py @@ -16,7 +16,7 @@ class USB_C_5V_PSU(Module): configuration_resistors = L.list_field( 2, lambda: F.Resistor().builder( - lambda r: r.resistance.merge(F.Constant(5.1 * P.kohm)) + lambda r: r.resistance.merge(F.Range.from_center_rel(5.1 * P.kohm, 0.05)) ), ) diff --git a/src/faebryk/library/USB_C_PSU_Vertical.py b/src/faebryk/library/USB_C_PSU_Vertical.py index 9705ba48..c6d164bd 100644 --- a/src/faebryk/library/USB_C_PSU_Vertical.py +++ b/src/faebryk/library/USB_C_PSU_Vertical.py @@ -28,7 +28,7 @@ def __preinit__(self): for res in self.configuration_resistors: res.resistance.merge(5.1 * P.kohm) self.fuse.fuse_type.merge(F.Fuse.FuseType.RESETTABLE) - self.fuse.trip_current.merge(F.Constant(1 * P.A)) + self.fuse.trip_current.merge(F.Range.from_center_rel(1 * P.A, 0.05)) # alliases vcon = self.usb_connector.vbus diff --git a/src/faebryk/library/XL_3528RGBW_WS2812B.py b/src/faebryk/library/XL_3528RGBW_WS2812B.py index 4a0d4ad9..cc27988c 100644 --- a/src/faebryk/library/XL_3528RGBW_WS2812B.py +++ b/src/faebryk/library/XL_3528RGBW_WS2812B.py @@ -11,12 +11,9 @@ class _ws2812b_esphome_config(F.has_esphome_config.impl()): update_interval: F.TBD def get_config(self) -> dict: - assert isinstance( - self.update_interval, F.Constant - ), "No update interval set!" + assert isinstance(self.update_interval, F.Constant) - obj = self.obj - assert isinstance(obj, XL_3528RGBW_WS2812B), "This is not a WS2812B RGBW!" + obj = self.get_obj(XL_3528RGBW_WS2812B) data_pin = F.is_esphome_bus.find_connected_bus(obj.di.signal) @@ -35,6 +32,12 @@ def get_config(self) -> dict: ] } + def is_implemented(self): + return ( + isinstance(self.update_interval.get_most_narrow(), F.Constant) + and super().is_implemented() + ) + # interfaces power: F.ElectricPower