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Day_24.md

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Prev: Day 23$~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~$Next: Day 25

Day 24: Final steps for RTL2GDS using tritonRoute and openSTA

24.1 Routing and Design Rule Check (DRC)

24.1.1 Introduction to Maze Routing - Lee's Algorithm

  • Lee's algorithm is one possible solution for maze routing problems based on breadth-first search.
    • If a path exists between the source and target, this algorithm guarantees finding it.
    • It always finds the shortest path between the source and target.
  • Steps
    1. The layout area is divided into a Routing grid with keep-off areas for the pre-placed macros and logical blockages for the I/O pad ring.
    2. The next step is to identify the source pin (S) and target pin (T) of the cells in the grid
    3. Now, based on the distance from the grid box "S", adjacent grid boxes (only horizontal and vertical grid boxes are considered adjacent and not the diagonal ones) are labelled as 1. Next, the grid boxes adjacent to those labelled 1 are now labelled as 2. This iterative process progresses until we hit the target pin's, "T" grid box.
    • Note: The wave expansion marks only points in the routable area of the chip, not in the blocks or already wired parts.
  • Routes with lower number of bends are preferred.
Lee's Routing Algorithm
D24_Lees_Routing_Algorithm_resized
The blue route is preferred over the black one due to lower number of bends
  • This algorithm, however, has a high cost in term of both memory usage and run time.
  • To overcome these short-comings, there are other more advanced algorithms like Line Search algorithm & Steiner tree algorithm.

24.1.2 Design Rule Check during routing

  • While performing routing, the router tool needs to follow the DRC rules related to routing provided by the PDK.
  • Basically, the origin of these DRCs come from the manufacturing process used like photolithography or others, that for example, define the minimum wire width that can be manufactured, the minimum spacing between two wire in a metal layer etc.
Typical DRC rules for wires like width, spacing and pitch
D24_Routing_DRC_Typical_Rules_about_wire
  • Check out the DRC rules related to the local interconnect and the metal layers for sky130 PDK DRC.
A Signal short during route
Fixing it using other metal layers gives rise to new DRC checks related to VIAs
D24_Routing_DRC_Check_Examples_2

24.2 Power Distribution Network and Routing

24.2.1 Lab: Steps to build Power Distribution Network

  • Levels of Power distribution 
    > VDD, VSS pins/ balls
  |--> VDD, VSS pads
       |--> Core Power Rings
            |--> VDD, VSS Horizontal, Vertical Straps
                 |--> Standard Cell Rails
                 |
                 |--> Macro Power Ring
D24_Power_Distribution_Network_resized
Source: Power Distribution Network
  • Command to generate PDN in openLANE: run_power_grid_generation
Layout after PDN generation
D24_Layout_after_PDN_Generation
Layout zoomed
D24_Layout_after_PDN_Generation_Zoomed

24.2.2 Lab: Steps to perform routing

  • To run the routing in OpenLANE, execute: run_routing
No DRC violations after routing
D24_Detailed_Routing_No_DRC_Viols
No Timing violations at TYPICAL corner
D24_STA_for_typical_after_routing
Layout after routing (KLayout)
D24_Layout_after_routing_in_klayout
Layout after routing - Zoomed (Magic)
D24_Layout_after_Routing
  • Post-route STA 
    read_lef /openLANE_flow/designs/picorv32a/runs/latest_25-03/tmp/merged.lef
read_def /openLANE_flow/designs/picorv32a/runs/latest_25-03/results/routing/picorv32a.def
read_spef /openLANE_flow/designs/picorv32a/runs/latest_25-03/results/routing/picorv32a.spef

write_db picorv32a_routing.db

read_db picorv32a_routing.db
read_verilog /openLANE_flow/designs/picorv32a/runs/latest_25-03/results/synthesis/picorv32a.synthesis_preroute.v
read_liberty $::env(LIB_SYNTH_COMPLETE)
##read_liberty -max $::env(LIB_SLOWEST)
##read_liberty -min $::env(LIB_FASTEST)
link_design picorv32a
read_sdc /openLANE_flow/designs/picorv32a/src/my_base.sdc
set_propagated_clock [all_clocks]
report_checks -path_delay min_max -format full_clock_expanded -digits 4 -fields {net cap slew input_pins fanout}

24.2.3 Basics of global and detail routing

  • Global route using fast route and Detailed route using tritonRoute
  • Global route provides a routing guide.
  • In Detailed route, algorithms are used to find the best possible connectivity using the routing guides from global route.

24.2.4 TritonRoute Features

  • Performs initial detail route
  • Honors the preprocessed route guides (obtained after global route) - i.e., attempts as much as possible to route within route guides.
  • Assumes route guides for each net satisfy inter-guide connectivity.
  • Works on proposed MILP-based panel routing scheme with intra-layer parallel and inter-layer sequential routing framework.

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