Day8.md

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Day 8: Basic RISC-V CPU Microarchitecture

Our objective is to implement a basic RISC-V CPU core (RV32I Base Instruction set except the instructions - FENCE, ECALL & EBREAK).
The following diagrams show the general block diagram of the CPU and the initial implementation pipeline diagram using TL-Verilog:

CPU Block Diagram
TL-Verilog based implementation pipeline/ flow diagram

The implementation is done stage-by-stage verifying the functionality at each step in the Makerchip IDE. The following logic blocks are implemented and verified:

• Program Counter (PC)
• Instruction Fetch from Instruction Memory (IMEM Read)
• Instruction Decoder
  • Instruction Type Decode (I, R, S, B, U, J)
  • Instruction Immediate Value Decoding
  • Instruction Field Decoding
  • Complete Instruction Decoding
• Register File Read
• Arithmetic & Logic Unit (ALU)
• Register File Write
• Branch Instructions
  • (Modifying PC logic and adding additional logic to handle the Branch instructions)

8.1 Program Counter + Instruction Fetch

Program Counter + Intruction Fetch

8.2 Instruction Decoder

Instruction Decoder
RISC-V Opcode Map
RISC-V Instruction Format
RV32I ISA Encoding
Instruction Type Decoding
Immediate Value Decoding

8.3 Register File Read

Register File Read
Register File module interface

8.4 ALU

ALU (only ADD, ADDI implemented for now)

8.5 Register File Write

Register File Write

8.6 Branch Instruction Logic

Branch Instruction Logic added

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