README.md

VSD-HDP

This GitHub repository is created as part of attending the VLSI Hardware Development Program (VSD-HDP, Cohort: 21 October, 2023 – 29 December, 2023).

Progress Status

Day #	Topic(s) Covered	Status
Day 0	GitHub repo creation, System/ Tools Setup
Day 1	Introduction to Verilog RTL design and Synthesis
Day 2	Familiarization of .lib file structure and various timing models (QTMs/ETMs) Hierarchical vs. Flat synthesis Various Flip-Flop designs
Day 3	Logic Synthesis Optimizations Combinational Sequential
Day 4	Gate Level Simulation Synthesis-Simulation mismatch
Day 5	Introduction to RISC-V ISA and GNU Compiler Toolchain
Day 6	Introduction to ABI and basic verification flow
Day 7	Digital Logic with TL-Verilog and Makerchip
Day 8	Basic RISC-V CPU Microarchitecture
Day 9	Complete Pipelined RISC-V CPU Microarchitecture
Day 10	GLS of the implemented RISC-V CPU Core Conversion of TL-Verilog code to Verilog/ SystemVerilog GLS of the RISC-V CPU Core
Day 11	Advanced Synthesis and STA with DC
Day 12	Circuit Design using sky130