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pennamandreagilardoni
pennam
authored and
andreagilardoni
committed
rebuilding FSP for unor4wifi in order to set RTC_CFG_OPEN_SET_CLOCK_SOURCE to 0
1 parent ff836e4 commit 85db2ca

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10 files changed

+646
-60
lines changed

10 files changed

+646
-60
lines changed

‎extras/e2studioProjects/Santiago/configuration.xml

+1-1
Original file line numberDiff line numberDiff line change
@@ -1551,7 +1551,7 @@
15511551
</config>
15521552
<config id="config.driver.rtc">
15531553
<property id="config.driver.rtc.param_checking_enable" value="config.driver.rtc.param_checking_enable.bsp"/>
1554-
<property id="config.driver.rtc.open_set_source_clock" value="config.driver.rtc.open_set_source_clock.enabled"/>
1554+
<property id="config.driver.rtc.open_set_source_clock" value="config.driver.rtc.open_set_source_clock.disabled"/>
15551555
</config>
15561556
<config id="config.driver.spi">
15571557
<property id="config.driver.spi.param_checking_enable" value="config.driver.spi.param_checking_enable.bsp"/>

‎extras/e2studioProjects/Santiago/ra_cfg.txt

+1-1
Original file line numberDiff line numberDiff line change
@@ -198,7 +198,7 @@ FSP Configuration
198198

199199
Module "Realtime Clock (r_rtc)"
200200
Parameter Checking: Default (BSP)
201-
Set Source Clock in Open: Enabled
201+
Set Source Clock in Open: Disabled
202202

203203
Module "Timer, General PWM (r_gpt)"
204204
Parameter Checking: Default (BSP)

‎variants/UNOWIFIR4/includes/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h

+4-4
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,11 @@
11
/**************************************************************************//**
22
* @file cmsis_version.h
33
* @brief CMSIS Core(M) Version definitions
4-
* @version V5.0.4
5-
* @date 23. July 2019
4+
* @version V5.0.5
5+
* @date 02. February 2022
66
******************************************************************************/
77
/*
8-
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
8+
* Copyright (c) 2009-2022 ARM Limited. All rights reserved.
99
*
1010
* SPDX-License-Identifier: Apache-2.0
1111
*
@@ -33,7 +33,7 @@
3333

3434
/* CMSIS Version definitions */
3535
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
36-
#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */
36+
#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */
3737
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
3838
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
3939
#endif

‎variants/UNOWIFIR4/includes/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h

+20-9
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
/**************************************************************************//**
22
* @file core_armv81mml.h
33
* @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File
4-
* @version V1.4.1
5-
* @date 04. June 2021
4+
* @version V1.4.2
5+
* @date 13. October 2021
66
******************************************************************************/
77
/*
88
* Copyright (c) 2018-2021 Arm Limited. All rights reserved.
@@ -526,7 +526,7 @@ typedef struct
526526
__IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
527527
__IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
528528
__IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
529-
__IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
529+
__IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
530530
__IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
531531
__IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
532532
__IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
@@ -535,7 +535,10 @@ typedef struct
535535
__IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
536536
__IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
537537
__IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
538-
uint32_t RESERVED3[92U];
538+
uint32_t RESERVED7[21U];
539+
__IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */
540+
__IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */
541+
uint32_t RESERVED3[69U];
539542
__OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
540543
__IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */
541544
uint32_t RESERVED4[14U];
@@ -1490,15 +1493,14 @@ typedef struct
14901493
uint32_t RESERVED11[108];
14911494
__IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */
14921495
__IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */
1493-
uint32_t RESERVED12[4];
1496+
uint32_t RESERVED12[3];
14941497
__IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */
14951498
__IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */
14961499
uint32_t RESERVED13[3];
14971500
__IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */
1498-
__IOM uint32_t PIDR1; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 1 */
1499-
__IOM uint32_t PIDR2; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 2 */
1500-
__IOM uint32_t PIDR3; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 3 */
1501-
uint32_t RESERVED14[3];
1501+
__IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */
1502+
__IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */
1503+
__IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */
15021504
__IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */
15031505
__IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */
15041506
__IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */
@@ -3158,6 +3160,15 @@ typedef struct
31583160
/*@} */
31593161

31603162

3163+
/**
3164+
\ingroup CMSIS_core_register
3165+
\defgroup CMSIS_register_aliases Backwards Compatibility Aliases
3166+
\brief Register alias definitions for backwards compatibility.
3167+
@{
3168+
*/
3169+
#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */
3170+
/*@} */
3171+
31613172

31623173
/*******************************************************************************
31633174
* Hardware Abstraction Layer

‎variants/UNOWIFIR4/includes/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h

+16-4
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
/**************************************************************************//**
22
* @file core_armv8mml.h
33
* @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File
4-
* @version V5.2.2
5-
* @date 04. June 2021
4+
* @version V5.2.3
5+
* @date 13. October 2021
66
******************************************************************************/
77
/*
88
* Copyright (c) 2009-2021 Arm Limited. All rights reserved.
@@ -519,7 +519,7 @@ typedef struct
519519
__IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
520520
__IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
521521
__IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
522-
__IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
522+
__IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
523523
__IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
524524
__IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
525525
__IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
@@ -528,7 +528,10 @@ typedef struct
528528
__IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
529529
__IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
530530
__IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
531-
uint32_t RESERVED3[92U];
531+
uint32_t RESERVED7[21U];
532+
__IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */
533+
__IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */
534+
uint32_t RESERVED3[69U];
532535
__OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
533536
uint32_t RESERVED4[15U];
534537
__IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
@@ -2182,6 +2185,15 @@ typedef struct
21822185
/*@} */
21832186

21842187

2188+
/**
2189+
\ingroup CMSIS_core_register
2190+
\defgroup CMSIS_register_aliases Backwards Compatibility Aliases
2191+
\brief Register alias definitions for backwards compatibility.
2192+
@{
2193+
*/
2194+
#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */
2195+
/*@} */
2196+
21852197

21862198
/*******************************************************************************
21872199
* Hardware Abstraction Layer

‎variants/UNOWIFIR4/includes/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h

+16-4
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
/**************************************************************************//**
22
* @file core_cm33.h
33
* @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File
4-
* @version V5.2.2
5-
* @date 04. June 2021
4+
* @version V5.2.3
5+
* @date 13. October 2021
66
******************************************************************************/
77
/*
88
* Copyright (c) 2009-2021 Arm Limited. All rights reserved.
@@ -519,7 +519,7 @@ typedef struct
519519
__IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
520520
__IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
521521
__IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
522-
__IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
522+
__IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
523523
__IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
524524
__IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
525525
__IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
@@ -528,7 +528,10 @@ typedef struct
528528
__IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
529529
__IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
530530
__IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
531-
uint32_t RESERVED3[92U];
531+
uint32_t RESERVED7[21U];
532+
__IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */
533+
__IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */
534+
uint32_t RESERVED3[69U];
532535
__OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
533536
uint32_t RESERVED4[15U];
534537
__IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
@@ -2257,6 +2260,15 @@ typedef struct
22572260
/*@} */
22582261

22592262

2263+
/**
2264+
\ingroup CMSIS_core_register
2265+
\defgroup CMSIS_register_aliases Backwards Compatibility Aliases
2266+
\brief Register alias definitions for backwards compatibility.
2267+
@{
2268+
*/
2269+
#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */
2270+
/*@} */
2271+
22602272

22612273
/*******************************************************************************
22622274
* Hardware Abstraction Layer

‎variants/UNOWIFIR4/includes/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h

+16-4
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
/**************************************************************************//**
22
* @file core_cm35p.h
33
* @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File
4-
* @version V1.1.2
5-
* @date 04. June 2021
4+
* @version V1.1.3
5+
* @date 13. October 2021
66
******************************************************************************/
77
/*
88
* Copyright (c) 2018-2021 Arm Limited. All rights reserved.
@@ -519,7 +519,7 @@ typedef struct
519519
__IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
520520
__IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
521521
__IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
522-
__IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
522+
__IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
523523
__IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
524524
__IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
525525
__IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
@@ -528,7 +528,10 @@ typedef struct
528528
__IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
529529
__IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
530530
__IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
531-
uint32_t RESERVED3[92U];
531+
uint32_t RESERVED7[21U];
532+
__IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */
533+
__IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */
534+
uint32_t RESERVED3[69U];
532535
__OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
533536
uint32_t RESERVED4[15U];
534537
__IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
@@ -2257,6 +2260,15 @@ typedef struct
22572260
/*@} */
22582261

22592262

2263+
/**
2264+
\ingroup CMSIS_core_register
2265+
\defgroup CMSIS_register_aliases Backwards Compatibility Aliases
2266+
\brief Register alias definitions for backwards compatibility.
2267+
@{
2268+
*/
2269+
#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */
2270+
/*@} */
2271+
22602272

22612273
/*******************************************************************************
22622274
* Hardware Abstraction Layer

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