use core::ptr::NonNull;
+
+use crate::{TriggerMode, GIC_MAX_IRQ, SPI_RANGE};
+use tock_registers::interfaces::{Readable, Writeable};
+use tock_registers::register_structs;
+use tock_registers::registers::{ReadOnly, ReadWrite, WriteOnly};
+
+register_structs! {
+ #[allow(non_snake_case)]
+ GicDistributorRegs {
+ (0x0000 => CTLR: ReadWrite<u32>),
+ (0x0004 => TYPER: ReadOnly<u32>),
+ (0x0008 => IIDR: ReadOnly<u32>),
+ (0x000c => _reserved_0),
+ (0x0080 => IGROUPR: [ReadWrite<u32>; 0x20]),
+ (0x0100 => ISENABLER: [ReadWrite<u32>; 0x20]),
+ (0x0180 => ICENABLER: [ReadWrite<u32>; 0x20]),
+ (0x0200 => ISPENDR: [ReadWrite<u32>; 0x20]),
+ (0x0280 => ICPENDR: [ReadWrite<u32>; 0x20]),
+ (0x0300 => ISACTIVER: [ReadWrite<u32>; 0x20]),
+ (0x0380 => ICACTIVER: [ReadWrite<u32>; 0x20]),
+ (0x0400 => IPRIORITYR: [ReadWrite<u32>; 0x100]),
+ (0x0800 => ITARGETSR: [ReadWrite<u32>; 0x100]),
+ (0x0c00 => ICFGR: [ReadWrite<u32>; 0x40]),
+ (0x0d00 => _reserved_1),
+ (0x0f00 => SGIR: WriteOnly<u32>),
+ (0x0f04 => @END),
+ }
+}
+
+register_structs! {
+ #[allow(non_snake_case)]
+ GicCpuInterfaceRegs {
+ (0x0000 => CTLR: ReadWrite<u32>),
+ (0x0004 => PMR: ReadWrite<u32>),
+ (0x0008 => BPR: ReadWrite<u32>),
+ (0x000c => IAR: ReadOnly<u32>),
+ (0x0010 => EOIR: WriteOnly<u32>),
+ (0x0014 => RPR: ReadOnly<u32>),
+ (0x0018 => HPPIR: ReadOnly<u32>),
+ (0x001c => _reserved_1),
+ (0x00fc => IIDR: ReadOnly<u32>),
+ (0x0100 => _reserved_2),
+ (0x1000 => DIR: WriteOnly<u32>),
+ (0x1004 => @END),
+ }
+}
+
+pub struct GicDistributor {
+ base: NonNull<GicDistributorRegs>,
+ max_irqs: usize,
+}
+
+pub struct GicCpuInterface {
+ base: NonNull<GicCpuInterfaceRegs>,
+}
+
+unsafe impl Send for GicDistributor {}
+unsafe impl Sync for GicDistributor {}
+
+unsafe impl Send for GicCpuInterface {}
+unsafe impl Sync for GicCpuInterface {}
+
+impl GicDistributor {
+ pub const fn new(base: *mut u8) -> Self {
+ Self {
+ base: NonNull::new(base).unwrap().cast(),
+ max_irqs: GIC_MAX_IRQ,
+ }
+ }
+
+ const fn regs(&self) -> &GicDistributorRegs {
+ unsafe { self.base.as_ref() }
+ }
+
+ pub fn cpu_num(&self) -> usize {
+ ((self.regs().TYPER.get() as usize >> 5) & 0b111) + 1
+ }
+
+ pub fn max_irqs(&self) -> usize {
+ ((self.regs().TYPER.get() as usize & 0b11111) + 1) * 32
+ }
+
+ pub fn configure_interrupt(&mut self, vector: usize, tm: TriggerMode) {
+ if vector >= self.max_irqs || vector < SPI_RANGE.start {
+ return;
+ }
+
+ let reg_idx = vector >> 4;
+ let bit_shift = ((vector & 0xf) << 1) + 1;
+ let mut reg_val = self.regs().ICFGR[reg_idx].get();
+ match tm {
+ TriggerMode::Edge => reg_val |= 1 << bit_shift,
+ TriggerMode::Level => reg_val &= !(1 << bit_shift),
+ }
+ self.regs().ICFGR[reg_idx].set(reg_val);
+ }
+
+ pub fn set_enable(&mut self, vector: usize, enable: bool) {
+ if vector >= self.max_irqs {
+ return;
+ }
+ let reg = vector / 32;
+ let mask = 1 << (vector % 32);
+ if enable {
+ self.regs().ISENABLER[reg].set(mask);
+ } else {
+ self.regs().ICENABLER[reg].set(mask);
+ }
+ }
+
+ pub fn init(&mut self) {
+ let max_irqs = self.max_irqs();
+ assert!(max_irqs <= GIC_MAX_IRQ);
+ self.max_irqs = max_irqs;
+
+ for i in (0..max_irqs).step_by(32) {
+ self.regs().ICENABLER[i / 32].set(u32::MAX);
+ self.regs().ICPENDR[i / 32].set(u32::MAX);
+ }
+ if self.cpu_num() > 1 {
+ for i in (SPI_RANGE.start..max_irqs).step_by(4) {
+ self.regs().ITARGETSR[i / 4].set(0x01_01_01_01);
+ }
+ }
+ for i in SPI_RANGE.start..max_irqs {
+ self.configure_interrupt(i, TriggerMode::Edge);
+ }
+
+ self.regs().CTLR.set(1);
+ }
+}
+
+impl GicCpuInterface {
+ pub const fn new(base: *mut u8) -> Self {
+ Self {
+ base: NonNull::new(base).unwrap().cast(),
+ }
+ }
+
+ const fn regs(&self) -> &GicCpuInterfaceRegs {
+ unsafe { self.base.as_ref() }
+ }
+
+ pub fn iar(&self) -> u32 {
+ self.regs().IAR.get()
+ }
+
+ pub fn eoi(&self, iar: u32) {
+ self.regs().EOIR.set(iar);
+ }
+
+ pub fn handle_irq<F>(&self, handler: F)
+ where
+ F: FnOnce(u32),
+ {
+ let iar = self.iar();
+ let vector = iar & 0x3ff;
+ if vector < 1020 {
+ handler(vector);
+ self.eoi(iar);
+ } else {
+ }
+ }
+
+ pub fn init(&self) {
+ self.regs().CTLR.set(1);
+ self.regs().PMR.set(0xff);
+ }
+}
+
+