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[fix] Adjust init_array to the range of sdata-edata
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@Azure-stars
Azure-stars committed Feb 9, 2025
1 parent 1832ead commit 3cfc4ac
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Showing 13 changed files with 142 additions and 147 deletions.
1 change: 0 additions & 1 deletion api/arceos_posix_api/src/imp/fd_ops.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -22,7 +22,6 @@ pub trait FileLike: Send + Sync {
}

def_resource! {
#[allow(non_camel_case_types)]
pub(crate) static FD_TABLE: ResArc<RwLock<FlattenObjects<Arc<dyn FileLike>, AX_FILE_LIMIT>>> = ResArc::new();
}

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14 changes: 7 additions & 7 deletions modules/axhal/linker.lds.S
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Original file line number Diff line number Diff line change
Expand Up @@ -24,13 +24,6 @@ SECTIONS
. = ALIGN(4K);
_erodata = .;
}

.init_array : ALIGN(4K) {
__init_array_start = .;
*(.init_array .init_array.*)
__init_array_end = .;
. = ALIGN(4K);
}

.data : ALIGN(4K) {
_sdata = .;
Expand All @@ -47,6 +40,13 @@ SECTIONS
_etdata = .;
}

.init_array : ALIGN(4K) {
__init_array_start = .;
*(.init_array .init_array.*)
__init_array_end = .;
. = ALIGN(4K);
}

.tbss : ALIGN(0x10) {
_stbss = .;
*(.tbss .tbss.*)
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33 changes: 17 additions & 16 deletions modules/axhal/src/arch/riscv/context.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -150,7 +150,6 @@ impl UspaceContext {
/// # Safety
///
/// This function is unsafe because it changes processor mode and the stack.
#[inline(never)]
#[unsafe(no_mangle)]
pub unsafe fn enter_uspace(&self, kstack_top: VirtAddr) -> ! {
use riscv::register::{sepc, sscratch};
Expand All @@ -161,20 +160,22 @@ impl UspaceContext {
// Address of the top of the kernel stack after saving the trap frame.
let kernel_trap_addr = kstack_top.as_usize() - core::mem::size_of::<TrapFrame>();
unsafe {
core::arch::asm!("
mv sp, {tf}
STR gp, {kernel_trap_addr}, 2
LDR gp, sp, 2
STR tp, {kernel_trap_addr}, 3
LDR tp, sp, 3
LDR t0, sp, 32
csrw sstatus, t0
POP_GENERAL_REGS
LDR sp, sp, 1
sret",
core::arch::asm!(
include_asm_macros!(),
"
mv sp, {tf}
STR gp, {kernel_trap_addr}, 2
LDR gp, sp, 2
STR tp, {kernel_trap_addr}, 3
LDR tp, sp, 3
LDR t0, sp, 32
csrw sstatus, t0
POP_GENERAL_REGS
LDR sp, sp, 1
sret",
tf = in(reg) &(self.0),
kernel_trap_addr = in(reg) kernel_trap_addr,
options(noreturn),
Expand Down Expand Up @@ -283,7 +284,7 @@ impl TaskContext {
#[naked]
unsafe extern "C" fn context_switch(_current_task: &mut TaskContext, _next_task: &TaskContext) {
naked_asm!(
include_asm_marcos!(),
include_asm_macros!(),
"
// save old context (callee-saved registers)
STR ra, a0, 0
Expand Down
106 changes: 79 additions & 27 deletions modules/axhal/src/arch/riscv/macros.rs
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Original file line number Diff line number Diff line change
@@ -1,35 +1,87 @@
#[cfg(target_arch = "riscv32")]
macro_rules! include_asm_marcos {
() => {
r"
.ifndef XLENB
.equ XLENB, 4
.macro LDR rd, rs, off
lw \rd, \off*XLENB(\rs)
.endm
.macro STR rs2, rs1, off
sw \rs2, \off*XLENB(\rs1)
.endm
.endif"
};
}
macro_rules! __asm_macros {
() => {
r"
.ifndef XLENB
.equ XLENB, 4
.macro LDR rd, rs, off
lw \rd, \off*XLENB(\rs)
.endm
.macro STR rs2, rs1, off
sw \rs2, \off*XLENB(\rs1)
.endm
.endif"
};
}

#[cfg(target_arch = "riscv64")]
macro_rules! include_asm_marcos {
macro_rules! __asm_macros {
() => {
r"
.ifndef XLENB
.equ XLENB, 8
.macro LDR rd, rs, off
ld \rd, \off*XLENB(\rs)
.endm
.macro STR rs2, rs1, off
sd \rs2, \off*XLENB(\rs1)
.endm
.endif"
};
}

macro_rules! include_asm_macros {
() => {
r"
.ifndef XLENB
.equ XLENB, 8
concat!(
__asm_macros!(),
r"
.ifndef REGS_MACROS_FLAG
.equ REGS_MACROS_FLAG, 1
.macro PUSH_POP_GENERAL_REGS, op
\op ra, sp, 0
\op t0, sp, 4
\op t1, sp, 5
\op t2, sp, 6
\op s0, sp, 7
\op s1, sp, 8
\op a0, sp, 9
\op a1, sp, 10
\op a2, sp, 11
\op a3, sp, 12
\op a4, sp, 13
\op a5, sp, 14
\op a6, sp, 15
\op a7, sp, 16
\op s2, sp, 17
\op s3, sp, 18
\op s4, sp, 19
\op s5, sp, 20
\op s6, sp, 21
\op s7, sp, 22
\op s8, sp, 23
\op s9, sp, 24
\op s10, sp, 25
\op s11, sp, 26
\op t3, sp, 27
\op t4, sp, 28
\op t5, sp, 29
\op t6, sp, 30
.endm
.macro PUSH_GENERAL_REGS
PUSH_POP_GENERAL_REGS STR
.endm
.macro LDR rd, rs, off
ld \rd, \off*XLENB(\rs)
.endm
.macro STR rs2, rs1, off
sd \rs2, \off*XLENB(\rs1)
.endm
.macro POP_GENERAL_REGS
PUSH_POP_GENERAL_REGS LDR
.endm
.endif"
.endif"
)
};
}
39 changes: 0 additions & 39 deletions modules/axhal/src/arch/riscv/trap.S
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Original file line number Diff line number Diff line change
@@ -1,42 +1,3 @@
.macro PUSH_POP_GENERAL_REGS, op
\op ra, sp, 0
\op t0, sp, 4
\op t1, sp, 5
\op t2, sp, 6
\op s0, sp, 7
\op s1, sp, 8
\op a0, sp, 9
\op a1, sp, 10
\op a2, sp, 11
\op a3, sp, 12
\op a4, sp, 13
\op a5, sp, 14
\op a6, sp, 15
\op a7, sp, 16
\op s2, sp, 17
\op s3, sp, 18
\op s4, sp, 19
\op s5, sp, 20
\op s6, sp, 21
\op s7, sp, 22
\op s8, sp, 23
\op s9, sp, 24
\op s10, sp, 25
\op s11, sp, 26
\op t3, sp, 27
\op t4, sp, 28
\op t5, sp, 29
\op t6, sp, 30
.endm

.macro PUSH_GENERAL_REGS
PUSH_POP_GENERAL_REGS STR
.endm

.macro POP_GENERAL_REGS
PUSH_POP_GENERAL_REGS LDR
.endm

.macro SAVE_REGS, from_user
addi sp, sp, -{trapframe_size}
PUSH_GENERAL_REGS
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2 changes: 1 addition & 1 deletion modules/axhal/src/arch/riscv/trap.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@ use riscv::register::{scause, stval};
use super::TrapFrame;

core::arch::global_asm!(
include_asm_marcos!(),
include_asm_macros!(),
include_str!("trap.S"),
trapframe_size = const core::mem::size_of::<TrapFrame>(),
);
Expand Down
73 changes: 37 additions & 36 deletions modules/axhal/src/arch/x86_64/context.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -152,25 +152,25 @@ impl UspaceContext {
assert_eq!(super::tss_get_rsp0(), kstack_top);
unsafe {
core::arch::asm!("
mov rsp, {tf}
pop rax
pop rcx
pop rdx
pop rbx
pop rbp
pop rsi
pop rdi
pop r8
pop r9
pop r10
pop r11
pop r12
pop r13
pop r14
pop r15
add rsp, 16 // skip vector, error_code
swapgs
iretq",
mov rsp, {tf}
pop rax
pop rcx
pop rdx
pop rbx
pop rbp
pop rsi
pop rdi
pop r8
pop r9
pop r10
pop r11
pop r12
pop r13
pop r14
pop r15
add rsp, 16 // skip vector, error_code
swapgs
iretq",
tf = in(reg) &self.0,
options(noreturn),
)
Expand Down Expand Up @@ -371,23 +371,24 @@ impl TaskContext {
unsafe extern "C" fn context_switch(_current_stack: &mut u64, _next_stack: &u64) {
unsafe {
naked_asm!(
".code64
push rbp
push rbx
push r12
push r13
push r14
push r15
mov [rdi], rsp
mov rsp, [rsi]
pop r15
pop r14
pop r13
pop r12
pop rbx
pop rbp
ret",
"
.code64
push rbp
push rbx
push r12
push r13
push r14
push r15
mov [rdi], rsp
mov rsp, [rsi]
pop r15
pop r14
pop r13
pop r12
pop rbx
pop rbp
ret",
)
}
}
9 changes: 0 additions & 9 deletions modules/axhal/src/mem.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -88,13 +88,6 @@ fn kernel_image_regions() -> impl Iterator<Item = MemRegion> {
flags: MemRegionFlags::RESERVED | MemRegionFlags::READ,
name: ".rodata",
},
MemRegion {
paddr: virt_to_phys((__init_array_start as usize).into()).align_down_4k(),
size: VirtAddr::from_usize(__init_array_end as usize).align_up_4k()
- VirtAddr::from_usize(__init_array_start as usize).align_down_4k(),
flags: MemRegionFlags::RESERVED | MemRegionFlags::READ,
name: ".init_array",
},
MemRegion {
paddr: virt_to_phys((_sdata as usize).into()),
size: _edata as usize - _sdata as usize,
Expand Down Expand Up @@ -158,8 +151,6 @@ unsafe extern "C" {
fn _etext();
fn _srodata();
fn _erodata();
fn __init_array_start();
fn __init_array_end();
fn _sdata();
fn _edata();
fn _sbss();
Expand Down
1 change: 0 additions & 1 deletion modules/axhal/src/platform/aarch64_bsta1000b/mod.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -20,7 +20,6 @@ pub mod time {
}

unsafe extern "C" {
fn exception_vector_base();
fn rust_main(cpu_id: usize, dtb: usize);
#[cfg(feature = "smp")]
fn rust_main_secondary(cpu_id: usize);
Expand Down
3 changes: 0 additions & 3 deletions modules/axhal/src/platform/aarch64_phytium_pi/mod.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -26,7 +26,6 @@ pub mod misc {
}

unsafe extern "C" {
fn exception_vector_base();
fn rust_main(cpu_id: usize, dtb: usize);
#[cfg(feature = "smp")]
fn rust_main_secondary(cpu_id: usize);
Expand All @@ -35,7 +34,6 @@ unsafe extern "C" {
pub(crate) unsafe extern "C" fn rust_entry(cpu_id: usize, dtb: usize) {
crate::mem::clear_bss();
let cpu_id = cpu_hard_id_to_logic_id(cpu_id);
crate::arch::set_exception_vector_base(exception_vector_base as usize);
crate::arch::write_page_table_root0(0.into()); // disable low address access
crate::cpu::init_primary(cpu_id);
super::aarch64_common::pl011::init_early();
Expand All @@ -46,7 +44,6 @@ pub(crate) unsafe extern "C" fn rust_entry(cpu_id: usize, dtb: usize) {
#[cfg(feature = "smp")]
pub(crate) unsafe extern "C" fn rust_entry_secondary(cpu_id: usize) {
let cpu_id = cpu_hard_id_to_logic_id(cpu_id);
crate::arch::set_exception_vector_base(exception_vector_base as usize);
crate::arch::write_page_table_root0(0.into()); // disable low address access
crate::cpu::init_secondary(cpu_id);
rust_main_secondary(cpu_id);
Expand Down
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