diff --git a/library/axi_pwm_gen/axi_pwm_gen.v b/library/axi_pwm_gen/axi_pwm_gen.v index 14fc60b1429..9ef867882ae 100644 --- a/library/axi_pwm_gen/axi_pwm_gen.v +++ b/library/axi_pwm_gen/axi_pwm_gen.v @@ -45,14 +45,26 @@ module axi_pwm_gen #( parameter PULSE_1_WIDTH = 7, parameter PULSE_2_WIDTH = 7, parameter PULSE_3_WIDTH = 7, + parameter PULSE_4_WIDTH = 7, + parameter PULSE_5_WIDTH = 7, + parameter PULSE_6_WIDTH = 7, + parameter PULSE_7_WIDTH = 7, parameter PULSE_0_PERIOD = 10, parameter PULSE_1_PERIOD = 10, parameter PULSE_2_PERIOD = 10, parameter PULSE_3_PERIOD = 10, + parameter PULSE_4_PERIOD = 10, + parameter PULSE_5_PERIOD = 10, + parameter PULSE_6_PERIOD = 10, + parameter PULSE_7_PERIOD = 10, parameter PULSE_0_OFFSET = 0, parameter PULSE_1_OFFSET = 0, parameter PULSE_2_OFFSET = 0, - parameter PULSE_3_OFFSET = 0 + parameter PULSE_3_OFFSET = 0, + parameter PULSE_4_OFFSET = 0, + parameter PULSE_5_OFFSET = 0, + parameter PULSE_6_OFFSET = 0, + parameter PULSE_7_OFFSET = 0 ) ( // axi interface @@ -84,7 +96,11 @@ module axi_pwm_gen #( output pwm_0, output pwm_1, output pwm_2, - output pwm_3 + output pwm_3, + output pwm_4, + output pwm_5, + output pwm_6, + output pwm_7 ); // local parameters @@ -93,13 +109,26 @@ module axi_pwm_gen #( 8'h00, /* MINOR */ 8'h00}; /* PATCH */ localparam [31:0] CORE_MAGIC = 32'h601a3471; // PLSG + localparam [N_PWMS*32-1:0] PULSE_WIDTH = (N_PWMS == 1) ? PULSE_0_WIDTH : + (N_PWMS == 2 ? {PULSE_1_WIDTH,PULSE_0_WIDTH} : + (N_PWMS == 3 ? {PULSE_2_WIDTH,PULSE_1_WIDTH,PULSE_0_WIDTH} : + (N_PWMS == 4 ? {PULSE_3_WIDTH,PULSE_2_WIDTH,PULSE_1_WIDTH,PULSE_0_WIDTH} : + (N_PWMS == 5 ? {PULSE_4_WIDTH,PULSE_3_WIDTH,PULSE_2_WIDTH,PULSE_1_WIDTH,PULSE_0_WIDTH} : + (N_PWMS == 6 ? {PULSE_5_WIDTH,PULSE_4_WIDTH,PULSE_3_WIDTH,PULSE_2_WIDTH,PULSE_1_WIDTH,PULSE_0_WIDTH} : + (N_PWMS == 7 ? {PULSE_6_WIDTH,PULSE_5_WIDTH,PULSE_4_WIDTH,PULSE_3_WIDTH,PULSE_2_WIDTH,PULSE_1_WIDTH,PULSE_0_WIDTH} : + (N_PWMS == 8 ? {PULSE_7_WIDTH,PULSE_6_WIDTH,PULSE_5_WIDTH,PULSE_4_WIDTH,PULSE_3_WIDTH,PULSE_2_WIDTH,PULSE_1_WIDTH,PULSE_0_WIDTH} : 'b0))))))); + localparam [N_PWMS*32-1:0] PULSE_PERIOD = (N_PWMS == 1) ? PULSE_0_PERIOD : + (N_PWMS == 2 ? {PULSE_1_PERIOD,PULSE_0_PERIOD} : + (N_PWMS == 3 ? {PULSE_2_PERIOD,PULSE_1_PERIOD,PULSE_0_PERIOD} : + (N_PWMS == 4 ? {PULSE_3_PERIOD,PULSE_2_PERIOD,PULSE_1_PERIOD,PULSE_0_PERIOD} : + (N_PWMS == 5 ? {PULSE_4_PERIOD,PULSE_3_PERIOD,PULSE_2_PERIOD,PULSE_1_PERIOD,PULSE_0_PERIOD} : + (N_PWMS == 6 ? {PULSE_5_PERIOD,PULSE_4_PERIOD,PULSE_3_PERIOD,PULSE_2_PERIOD,PULSE_1_PERIOD,PULSE_0_PERIOD} : + (N_PWMS == 7 ? {PULSE_6_PERIOD,PULSE_5_PERIOD,PULSE_4_PERIOD,PULSE_3_PERIOD,PULSE_2_PERIOD,PULSE_1_PERIOD,PULSE_0_PERIOD} : + (N_PWMS == 8 ? {PULSE_7_PERIOD,PULSE_6_PERIOD,PULSE_5_PERIOD,PULSE_4_PERIOD,PULSE_3_PERIOD,PULSE_2_PERIOD,PULSE_1_PERIOD,PULSE_0_PERIOD} : 'b0))))))); // internal registers - reg sync_0 = 1'b0; - reg sync_1 = 1'b0; - reg sync_2 = 1'b0; - reg sync_3 = 1'b0; + reg sync [N_PWMS-1:0]; reg [31:0] offset_cnt = 32'd0; reg offset_alignment = 1'b0; reg pause_cnt_d = 1'b0; @@ -117,10 +146,11 @@ module axi_pwm_gen #( wire up_wreq_s; wire [ 13:0] up_waddr_s; wire [ 31:0] up_wdata_s; - wire [127:0] pwm_width_s; - wire [127:0] pwm_period_s; - wire [127:0] pwm_offset_s; - wire [ 31:0] pwm_counter[0:3]; + wire [N_PWMS-1:0] pwm; + wire [N_PWMS*32-1:0] pwm_width_s; + wire [N_PWMS*32-1:0] pwm_period_s; + wire [N_PWMS*32-1:0] pwm_offset_s; + wire [N_PWMS*32-1:0] pwm_counter[0:N_PWMS-1]; wire load_config_s; wire pwm_gen_resetn; wire ext_sync_s; @@ -140,14 +170,26 @@ module axi_pwm_gen #( .PULSE_1_WIDTH (PULSE_1_WIDTH), .PULSE_2_WIDTH (PULSE_2_WIDTH), .PULSE_3_WIDTH (PULSE_3_WIDTH), + .PULSE_4_WIDTH (PULSE_4_WIDTH), + .PULSE_5_WIDTH (PULSE_5_WIDTH), + .PULSE_6_WIDTH (PULSE_6_WIDTH), + .PULSE_7_WIDTH (PULSE_7_WIDTH), .PULSE_0_PERIOD (PULSE_0_PERIOD), .PULSE_1_PERIOD (PULSE_1_PERIOD), .PULSE_2_PERIOD (PULSE_2_PERIOD), .PULSE_3_PERIOD (PULSE_3_PERIOD), + .PULSE_4_PERIOD (PULSE_4_PERIOD), + .PULSE_5_PERIOD (PULSE_5_PERIOD), + .PULSE_6_PERIOD (PULSE_6_PERIOD), + .PULSE_7_PERIOD (PULSE_7_PERIOD), .PULSE_0_OFFSET (PULSE_0_OFFSET), .PULSE_1_OFFSET (PULSE_1_OFFSET), .PULSE_2_OFFSET (PULSE_2_OFFSET), - .PULSE_3_OFFSET (PULSE_3_OFFSET) + .PULSE_3_OFFSET (PULSE_3_OFFSET), + .PULSE_4_OFFSET (PULSE_4_OFFSET), + .PULSE_5_OFFSET (PULSE_5_OFFSET), + .PULSE_6_OFFSET (PULSE_6_OFFSET), + .PULSE_7_OFFSET (PULSE_7_OFFSET) ) i_regmap ( .ext_clk (ext_clk), .clk_out (clk), @@ -214,114 +256,51 @@ module axi_pwm_gen #( end end - assign pause_cnt = ((pwm_counter[0] == 32'd1 || - pwm_counter[1] == 32'd1 || - pwm_counter[2] == 32'd1 || - pwm_counter[3] == 32'd1) ? 1'b1 : 1'b0); + assign pause_cnt = (N_PWMS == 1) ? (pwm_counter[0] ? 1'b1 : 1'b0) : + (N_PWMS == 2 ? (pwm_counter[0] || pwm_counter[1] ? 1'b1 : 1'b0) : + (N_PWMS == 3 ? (pwm_counter[2] || pwm_counter[1] || pwm_counter[0] ? 1'b1 : 1'b0) : + (N_PWMS == 4 ? (pwm_counter[3] || pwm_counter[2] || pwm_counter[1] || pwm_counter[0] ? 1'b1 : 1'b0) : + (N_PWMS == 5 ? (pwm_counter[4] || pwm_counter[3] || pwm_counter[2] || pwm_counter[1] || pwm_counter[0] ? 1'b1 : 1'b0) : + (N_PWMS == 6 ? (pwm_counter[5] || pwm_counter[4] || pwm_counter[3] || pwm_counter[2] || pwm_counter[1] || pwm_counter[0] ? 1'b1 : 1'b0) : + (N_PWMS == 7 ? (pwm_counter[6] || pwm_counter[5] || pwm_counter[4] || pwm_counter[3] || pwm_counter[2] || pwm_counter[1] || pwm_counter[0] ? 1'b1 : 1'b0) : + (N_PWMS == 8 ? (pwm_counter[7] || pwm_counter[6] || pwm_counter[5] || pwm_counter[4] || pwm_counter[3] || pwm_counter[2] || pwm_counter[1] || pwm_counter[0] ? 1'b1 : 1'b0) : 1'b0))))))); + assign offset_alignment_ready = !pause_cnt_d & pause_cnt; - axi_pwm_gen_1 #( - .PULSE_WIDTH (PULSE_0_WIDTH), - .PULSE_PERIOD (PULSE_0_PERIOD) - ) i0_axi_pwm_gen_1( - .clk (clk), - .rstn (pwm_gen_resetn), - .pulse_width (pwm_width_s[31:0]), - .pulse_period (pwm_period_s[31:0]), - .load_config (load_config_s), - .sync (sync_0), - .pulse (pwm_0), - .pulse_counter (pwm_counter[0])); - - always @(posedge clk) begin - if (pwm_gen_resetn == 1'b0) begin - sync_0 <= 1'b1; - end else begin - sync_0 <= (offset_cnt == pwm_offset_s[31:0]) ? 1'b0 : 1'b1; - end - end - generate - - if (N_PWMS >= 2) begin - axi_pwm_gen_1 #( - .PULSE_WIDTH (PULSE_1_WIDTH), - .PULSE_PERIOD (PULSE_1_PERIOD) - ) i1_axi_pwm_gen_1( - .clk (clk), - .rstn (pwm_gen_resetn), - .pulse_width (pwm_width_s[63:32]), - .pulse_period (pwm_period_s[63:32]), - .load_config (load_config_s), - .sync (sync_1), - .pulse (pwm_1), - .pulse_counter (pwm_counter[1])); - - always @(posedge clk) begin - if (pwm_gen_resetn == 1'b0) begin - sync_1 <= 1'b1; - end else begin - sync_1 <= (offset_cnt == pwm_offset_s[63:32]) ? 1'b0 : 1'b1; - end - end - end else begin - assign pwm_1 = 1'b0; - assign pwm_counter[1] = 32'd1; - end - - if (N_PWMS >= 3) begin - axi_pwm_gen_1 #( - .PULSE_WIDTH (PULSE_2_WIDTH), - .PULSE_PERIOD (PULSE_2_PERIOD) - ) i2_axi_pwm_gen_1( - .clk (clk), - .rstn (pwm_gen_resetn), - .pulse_width (pwm_width_s[95:64]), - .pulse_period (pwm_period_s[95:64]), - .load_config (load_config_s), - .sync (sync_2), - .pulse (pwm_2), - .pulse_counter (pwm_counter[2])); - - always @(posedge clk) begin - if (pwm_gen_resetn == 1'b0) begin - sync_2 <= 1'b1; - end else begin - sync_2 <= (offset_cnt == pwm_offset_s[95:64]) ? 1'b0 : 1'b1; - end - end - end else begin - assign pwm_2 = 1'b0; - assign pwm_counter[2] = 32'd1; - end - - if (N_PWMS >= 4) begin - axi_pwm_gen_1 #( - .PULSE_WIDTH (PULSE_3_WIDTH), - .PULSE_PERIOD (PULSE_3_PERIOD) - ) i3_axi_pwm_gen_1( - .clk (clk), - .rstn (pwm_gen_resetn), - .pulse_width (pwm_width_s[127:96]), - .pulse_period (pwm_period_s[127:96]), - .load_config (load_config_s), - .sync (sync_3), - .pulse (pwm_3), - .pulse_counter (pwm_counter[3])); - - always @(posedge clk) begin - if (pwm_gen_resetn == 1'b0) begin - sync_3 <= 1'b1; - end else begin - sync_3 <= (offset_cnt == pwm_offset_s[127:96]) ? 1'b0 : 1'b1; - end - end - end else begin - assign pwm_3 = 1'b0; - assign pwm_counter[3] = 32'd1; + genvar i; + for (i = 0; i < N_PWMS; i = i + 1) begin + axi_pwm_gen_1 #( + .PULSE_WIDTH (PULSE_WIDTH[i*32+31:i*32]), + .PULSE_PERIOD (PULSE_PERIOD[i*32+1:i*32]) + ) i_axi_pwm_gen_1( + .clk (clk), + .rstn (pwm_gen_resetn), + .pulse_width (pwm_width_s[i*32+31:i*32]), + .pulse_period (pwm_period_s[i*32+31:i*32]), + .load_config (load_config_s), + .sync (sync[i]), + .pulse (pwm[i]), + .pulse_counter (pwm_counter[i])); + always @(posedge clk) begin + if (pwm_gen_resetn == 1'b0) begin + sync[i] <= 1'b1; + end else begin + sync[i] <= (offset_cnt == pwm_offset_s[i*32+31:i*32]) ? 1'b0 : 1'b1; + end + end end endgenerate + assign pwm_0 = (N_PWMS >= 1) ? pwm[0] : 1'b0; + assign pwm_1 = (N_PWMS >= 2) ? pwm[1] : 1'b0; + assign pwm_2 = (N_PWMS >= 3) ? pwm[2] : 1'b0; + assign pwm_3 = (N_PWMS >= 4) ? pwm[3] : 1'b0; + assign pwm_4 = (N_PWMS >= 5) ? pwm[4] : 1'b0; + assign pwm_5 = (N_PWMS >= 6) ? pwm[5] : 1'b0; + assign pwm_6 = (N_PWMS >= 7) ? pwm[6] : 1'b0; + assign pwm_7 = (N_PWMS >= 8) ? pwm[7] : 1'b0; + up_axi #( .AXI_ADDRESS_WIDTH(16) ) i_up_axi ( diff --git a/library/axi_pwm_gen/axi_pwm_gen_hw.tcl b/library/axi_pwm_gen/axi_pwm_gen_hw.tcl index 42f60146b21..40cb0cdc731 100644 --- a/library/axi_pwm_gen/axi_pwm_gen_hw.tcl +++ b/library/axi_pwm_gen/axi_pwm_gen_hw.tcl @@ -34,14 +34,26 @@ ad_ip_parameter PULSE_0_WIDTH INTEGER 7 ad_ip_parameter PULSE_1_WIDTH INTEGER 7 ad_ip_parameter PULSE_2_WIDTH INTEGER 7 ad_ip_parameter PULSE_3_WIDTH INTEGER 7 +ad_ip_parameter PULSE_4_WIDTH INTEGER 7 +ad_ip_parameter PULSE_5_WIDTH INTEGER 7 +ad_ip_parameter PULSE_6_WIDTH INTEGER 7 +ad_ip_parameter PULSE_7_WIDTH INTEGER 7 ad_ip_parameter PULSE_0_PERIOD INTEGER 10 ad_ip_parameter PULSE_1_PERIOD INTEGER 10 ad_ip_parameter PULSE_2_PERIOD INTEGER 10 ad_ip_parameter PULSE_3_PERIOD INTEGER 10 +ad_ip_parameter PULSE_4_PERIOD INTEGER 10 +ad_ip_parameter PULSE_5_PERIOD INTEGER 10 +ad_ip_parameter PULSE_6_PERIOD INTEGER 10 +ad_ip_parameter PULSE_7_PERIOD INTEGER 10 ad_ip_parameter PULSE_0_OFFSET INTEGER 0 ad_ip_parameter PULSE_1_OFFSET INTEGER 0 ad_ip_parameter PULSE_2_OFFSET INTEGER 0 ad_ip_parameter PULSE_3_OFFSET INTEGER 0 +ad_ip_parameter PULSE_4_OFFSET INTEGER 0 +ad_ip_parameter PULSE_5_OFFSET INTEGER 0 +ad_ip_parameter PULSE_6_OFFSET INTEGER 0 +ad_ip_parameter PULSE_7_OFFSET INTEGER 0 # interfaces @@ -53,6 +65,6 @@ ad_interface clock ext_clk input 1 ad_interface signal ext_sync input 1 # output signals -for {set i 0} {$i < 4} {incr i} { +for {set i 0} {$i < 8} {incr i} { ad_interface signal pwm_$i output 1 if_pwm } diff --git a/library/axi_pwm_gen/axi_pwm_gen_ip.tcl b/library/axi_pwm_gen/axi_pwm_gen_ip.tcl index 3a69c1d6926..074179631d6 100644 --- a/library/axi_pwm_gen/axi_pwm_gen_ip.tcl +++ b/library/axi_pwm_gen/axi_pwm_gen_ip.tcl @@ -101,7 +101,7 @@ set_property -dict [list \ ] [ipgui::get_guiparamspec -name "EXT_ASYNC_SYNC" -component $cc] # Maximum 4 pwms -for {set i 0} {$i < 4} {incr i} { +for {set i 0} {$i < 8} {incr i} { ipgui::add_param -name "PULSE_${i}_WIDTH" -component $cc -parent $page0 set_property -dict [list \ "display_name" "PULSE $i width" \ @@ -142,11 +142,6 @@ for {set i 0} {$i < 4} {incr i} { [ipx::get_user_parameters PULSE_${i}_OFFSET -of_objects $cc] } -for {set i 1} {$i < 4} {incr i} { - adi_set_ports_dependency "pwm_$i" \ - "(spirit:decode(id('MODELPARAM_VALUE.N_PWMS')) > $i)" -} - adi_set_ports_dependency "ext_sync" \ "(spirit:decode(id('MODELPARAM_VALUE.PWM_EXT_SYNC')) == 1)" diff --git a/library/axi_pwm_gen/axi_pwm_gen_regmap.v b/library/axi_pwm_gen/axi_pwm_gen_regmap.v index 0d81d0664cb..55149653169 100644 --- a/library/axi_pwm_gen/axi_pwm_gen_regmap.v +++ b/library/axi_pwm_gen/axi_pwm_gen_regmap.v @@ -45,15 +45,27 @@ module axi_pwm_gen_regmap #( parameter PULSE_1_WIDTH = 7, parameter PULSE_2_WIDTH = 7, parameter PULSE_3_WIDTH = 7, + parameter PULSE_4_WIDTH = 7, + parameter PULSE_5_WIDTH = 7, + parameter PULSE_6_WIDTH = 7, + parameter PULSE_7_WIDTH = 7, parameter PULSE_0_PERIOD = 10, parameter PULSE_1_PERIOD = 10, parameter PULSE_2_PERIOD = 10, parameter PULSE_3_PERIOD = 10, - parameter PULSE_0_EXT_SYNC = 0, + parameter PULSE_4_PERIOD = 10, + parameter PULSE_5_PERIOD = 10, + parameter PULSE_6_PERIOD = 10, + parameter PULSE_7_PERIOD = 10, parameter PULSE_0_OFFSET = 0, parameter PULSE_1_OFFSET = 0, parameter PULSE_2_OFFSET = 0, - parameter PULSE_3_OFFSET = 0 + parameter PULSE_3_OFFSET = 0, + parameter PULSE_4_OFFSET = 0, + parameter PULSE_5_OFFSET = 0, + parameter PULSE_6_OFFSET = 0, + parameter PULSE_7_OFFSET = 0 + ) ( // external clock @@ -64,9 +76,9 @@ module axi_pwm_gen_regmap #( output clk_out, output pwm_gen_resetn, - output [127:0] pwm_width, - output [127:0] pwm_period, - output [127:0] pwm_offset, + output [N_PWMS*32-1:0] pwm_width, + output [N_PWMS*32-1:0] pwm_period, + output [N_PWMS*32-1:0] pwm_offset, output load_config, // processor interface @@ -90,14 +102,54 @@ module axi_pwm_gen_regmap #( reg [31:0] up_pwm_width_1 = PULSE_1_WIDTH; reg [31:0] up_pwm_width_2 = PULSE_2_WIDTH; reg [31:0] up_pwm_width_3 = PULSE_3_WIDTH; + reg [31:0] up_pwm_width_4 = PULSE_4_WIDTH; + reg [31:0] up_pwm_width_5 = PULSE_5_WIDTH; + reg [31:0] up_pwm_width_6 = PULSE_6_WIDTH; + reg [31:0] up_pwm_width_7 = PULSE_7_WIDTH; reg [31:0] up_pwm_period_0 = PULSE_0_PERIOD; reg [31:0] up_pwm_period_1 = PULSE_1_PERIOD; reg [31:0] up_pwm_period_2 = PULSE_2_PERIOD; reg [31:0] up_pwm_period_3 = PULSE_3_PERIOD; + reg [31:0] up_pwm_period_4 = PULSE_4_PERIOD; + reg [31:0] up_pwm_period_5 = PULSE_5_PERIOD; + reg [31:0] up_pwm_period_6 = PULSE_6_PERIOD; + reg [31:0] up_pwm_period_7 = PULSE_7_PERIOD; reg [31:0] up_pwm_offset_0 = PULSE_0_OFFSET; reg [31:0] up_pwm_offset_1 = PULSE_1_OFFSET; reg [31:0] up_pwm_offset_2 = PULSE_2_OFFSET; reg [31:0] up_pwm_offset_3 = PULSE_3_OFFSET; + reg [31:0] up_pwm_offset_4 = PULSE_4_OFFSET; + reg [31:0] up_pwm_offset_5 = PULSE_5_OFFSET; + reg [31:0] up_pwm_offset_6 = PULSE_6_OFFSET; + reg [31:0] up_pwm_offset_7 = PULSE_7_OFFSET; + wire [N_PWMS*32-1:0] up_pwm_width; + wire [N_PWMS*32-1:0] up_pwm_period; + wire [N_PWMS*32-1:0] up_pwm_offset; + + assign up_pwm_width = (N_PWMS == 1) ? up_pwm_width_0 : (N_PWMS == 2 ? {up_pwm_width_1,up_pwm_width_0} : + (N_PWMS == 3 ? {up_pwm_width_2,up_pwm_width_1,up_pwm_width_0} : + (N_PWMS == 4 ? {up_pwm_width_3,up_pwm_width_2,up_pwm_width_1,up_pwm_width_0} : + (N_PWMS == 5 ? {up_pwm_width_4,up_pwm_width_3,up_pwm_width_2,up_pwm_width_1,up_pwm_width_0} : + (N_PWMS == 6 ? {up_pwm_width_5,up_pwm_width_4,up_pwm_width_3,up_pwm_width_2,up_pwm_width_1,up_pwm_width_0} : + (N_PWMS == 7 ? {up_pwm_width_6,up_pwm_width_5,up_pwm_width_4,up_pwm_width_3,up_pwm_width_2,up_pwm_width_1,up_pwm_width_0} : + (N_PWMS == 8 ? {up_pwm_width_7,up_pwm_width_6,up_pwm_width_5,up_pwm_width_4,up_pwm_width_3,up_pwm_width_2,up_pwm_width_1,up_pwm_width_0} : + 1'b0))))))); + assign up_pwm_period = (N_PWMS == 1) ? up_pwm_period_0 : (N_PWMS == 2 ? {up_pwm_period_1,up_pwm_period_0} : + (N_PWMS == 3 ? {up_pwm_period_2,up_pwm_period_1,up_pwm_period_0} : + (N_PWMS == 4 ? {up_pwm_period_3,up_pwm_period_2,up_pwm_period_1,up_pwm_period_0} : + (N_PWMS == 5 ? {up_pwm_period_4,up_pwm_period_3,up_pwm_period_2,up_pwm_period_1,up_pwm_period_0} : + (N_PWMS == 6 ? {up_pwm_period_5,up_pwm_period_4,up_pwm_period_3,up_pwm_period_2,up_pwm_period_1,up_pwm_period_0} : + (N_PWMS == 7 ? {up_pwm_period_6,up_pwm_period_5,up_pwm_period_4,up_pwm_period_3,up_pwm_period_2,up_pwm_period_1,up_pwm_period_0} : + (N_PWMS == 8 ? {up_pwm_period_7,up_pwm_period_6,up_pwm_period_5,up_pwm_period_4,up_pwm_period_3,up_pwm_period_2,up_pwm_period_1,up_pwm_period_0} : + 1'b0))))))); + assign up_pwm_offset = (N_PWMS == 1) ? up_pwm_offset_0 : (N_PWMS == 2 ? {up_pwm_offset_1,up_pwm_offset_0} : + (N_PWMS == 3 ? {up_pwm_offset_2,up_pwm_offset_1,up_pwm_offset_0} : + (N_PWMS == 4 ? {up_pwm_offset_3,up_pwm_offset_2,up_pwm_offset_1,up_pwm_offset_0} : + (N_PWMS == 5 ? {up_pwm_offset_4,up_pwm_offset_3,up_pwm_offset_2,up_pwm_offset_1,up_pwm_offset_0} : + (N_PWMS == 6 ? {up_pwm_offset_5,up_pwm_offset_4,up_pwm_offset_3,up_pwm_offset_2,up_pwm_offset_1,up_pwm_offset_0} : + (N_PWMS == 7 ? {up_pwm_offset_6,up_pwm_offset_5,up_pwm_offset_4,up_pwm_offset_3,up_pwm_offset_2,up_pwm_offset_1,up_pwm_offset_0} : + (N_PWMS == 8 ? {up_pwm_offset_7,up_pwm_offset_6,up_pwm_offset_5,up_pwm_offset_4,up_pwm_offset_3,up_pwm_offset_2,up_pwm_offset_1,up_pwm_offset_0} : + 1'b0))))))); reg up_load_config = 1'b0; reg up_reset = 1'b1; @@ -109,14 +161,26 @@ module axi_pwm_gen_regmap #( up_pwm_width_1 <= PULSE_1_WIDTH; up_pwm_width_2 <= PULSE_2_WIDTH; up_pwm_width_3 <= PULSE_3_WIDTH; + up_pwm_width_4 <= PULSE_4_WIDTH; + up_pwm_width_5 <= PULSE_5_WIDTH; + up_pwm_width_6 <= PULSE_6_WIDTH; + up_pwm_width_7 <= PULSE_7_WIDTH; up_pwm_period_0 <= PULSE_0_PERIOD; up_pwm_period_1 <= PULSE_1_PERIOD; up_pwm_period_2 <= PULSE_2_PERIOD; up_pwm_period_3 <= PULSE_3_PERIOD; + up_pwm_period_4 <= PULSE_4_PERIOD; + up_pwm_period_5 <= PULSE_5_PERIOD; + up_pwm_period_6 <= PULSE_6_PERIOD; + up_pwm_period_7 <= PULSE_7_PERIOD; up_pwm_offset_0 <= PULSE_0_OFFSET; up_pwm_offset_1 <= PULSE_1_OFFSET; up_pwm_offset_2 <= PULSE_2_OFFSET; up_pwm_offset_3 <= PULSE_3_OFFSET; + up_pwm_offset_4 <= PULSE_4_OFFSET; + up_pwm_offset_5 <= PULSE_5_OFFSET; + up_pwm_offset_6 <= PULSE_6_OFFSET; + up_pwm_offset_7 <= PULSE_7_OFFSET; up_load_config <= 1'b0; up_reset <= 1'b1; end else begin @@ -166,6 +230,42 @@ module axi_pwm_gen_regmap #( if ((up_wreq == 1'b1) && (up_waddr == 14'h1b)) begin up_pwm_offset_3 <= up_wdata; end + if ((up_wreq == 1'b1) && (up_waddr == 14'h1c)) begin + up_pwm_period_4 <= up_wdata; + end + if ((up_wreq == 1'b1) && (up_waddr == 14'h1d)) begin + up_pwm_width_4 <= up_wdata; + end + if ((up_wreq == 1'b1) && (up_waddr == 14'h1e)) begin + up_pwm_offset_4 <= up_wdata; + end + if ((up_wreq == 1'b1) && (up_waddr == 14'h20)) begin + up_pwm_period_5 <= up_wdata; + end + if ((up_wreq == 1'b1) && (up_waddr == 14'h21)) begin + up_pwm_width_5 <= up_wdata; + end + if ((up_wreq == 1'b1) && (up_waddr == 14'h22)) begin + up_pwm_offset_5 <= up_wdata; + end + if ((up_wreq == 1'b1) && (up_waddr == 14'h23)) begin + up_pwm_period_6 <= up_wdata; + end + if ((up_wreq == 1'b1) && (up_waddr == 14'h24)) begin + up_pwm_width_6 <= up_wdata; + end + if ((up_wreq == 1'b1) && (up_waddr == 14'h25)) begin + up_pwm_offset_6 <= up_wdata; + end + if ((up_wreq == 1'b1) && (up_waddr == 14'h26)) begin + up_pwm_period_7 <= up_wdata; + end + if ((up_wreq == 1'b1) && (up_waddr == 14'h27)) begin + up_pwm_width_7 <= up_wdata; + end + if ((up_wreq == 1'b1) && (up_waddr == 14'h28)) begin + up_pwm_offset_7 <= up_wdata; + end end end @@ -195,6 +295,18 @@ module axi_pwm_gen_regmap #( 14'h19: up_rdata <= up_pwm_period_3; 14'h1a: up_rdata <= up_pwm_width_3; 14'h1b: up_rdata <= up_pwm_offset_3; + 14'h1c: up_rdata <= up_pwm_period_4; + 14'h1d: up_rdata <= up_pwm_width_4; + 14'h1e: up_rdata <= up_pwm_offset_4; + 14'h20: up_rdata <= up_pwm_period_5; + 14'h21: up_rdata <= up_pwm_width_5; + 14'h22: up_rdata <= up_pwm_offset_5; + 14'h23: up_rdata <= up_pwm_period_6; + 14'h24: up_rdata <= up_pwm_width_6; + 14'h25: up_rdata <= up_pwm_offset_6; + 14'h26: up_rdata <= up_pwm_period_7; + 14'h27: up_rdata <= up_pwm_width_7; + 14'h28: up_rdata <= up_pwm_offset_7; default: up_rdata <= 0; endcase end else begin @@ -215,38 +327,29 @@ module axi_pwm_gen_regmap #( .rst ()); sync_data #( - .NUM_OF_BITS (128), + .NUM_BITS (N_PWMS*32), .ASYNC_CLK (1) ) i_pwm_period_sync ( .in_clk (up_clk), - .in_data ({up_pwm_period_3, - up_pwm_period_2, - up_pwm_period_1, - up_pwm_period_0}), + .in_data (up_pwm_period), .out_clk (clk_out), .out_data (pwm_period)); sync_data #( - .NUM_OF_BITS (128), + .NUM_OF_BITS (N_PWMS*32), .ASYNC_CLK (1) ) i_pwm_width_sync ( .in_clk (up_clk), - .in_data ({up_pwm_width_3, - up_pwm_width_2, - up_pwm_width_1, - up_pwm_width_0}), + .in_data (up_pwm_width), .out_clk (clk_out), .out_data (pwm_width)); sync_data #( - .NUM_OF_BITS (128), + .NUM_OF_BITS (N_PWMS*32), .ASYNC_CLK (1) ) i_pwm_offset_sync ( .in_clk (up_clk), - .in_data ({up_pwm_offset_3, - up_pwm_offset_2, - up_pwm_offset_1, - up_pwm_offset_0}), + .in_data (up_pwm_offset), .out_clk (clk_out), .out_data (pwm_offset)); @@ -263,9 +366,9 @@ module axi_pwm_gen_regmap #( assign clk_out = up_clk; assign pwm_gen_resetn = ~up_reset; - assign pwm_period = {up_pwm_period_3, up_pwm_period_2, up_pwm_period_1, up_pwm_period_0}; - assign pwm_width = {up_pwm_width_3, up_pwm_width_2, up_pwm_width_1, up_pwm_width_0}; - assign pwm_offset = {up_pwm_offset_3, up_pwm_offset_2, up_pwm_offset_1, up_pwm_offset_0}; + assign pwm_period = up_pwm_period; + assign pwm_width = up_pwm_width; + assign pwm_offset = up_pwm_offset; assign load_config = up_load_config; end