From 2a27a59188a7e8e043a5ceae1dcc93e98fee121f Mon Sep 17 00:00:00 2001 From: Pop Ioan Daniel Date: Fri, 13 Dec 2024 14:04:03 +0200 Subject: [PATCH] projects/ad7405: Set axi_clkgen to 40MHz/Add constraints Signed-off-by: Pop Ioan Daniel --- projects/ad7405_fmc/common/ad7405_bd.tcl | 4 ++-- projects/ad7405_fmc/zed/system_constr_cmos.xdc | 8 ++++++++ 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/projects/ad7405_fmc/common/ad7405_bd.tcl b/projects/ad7405_fmc/common/ad7405_bd.tcl index 1a34960d3f7..4ae006425ee 100644 --- a/projects/ad7405_fmc/common/ad7405_bd.tcl +++ b/projects/ad7405_fmc/common/ad7405_bd.tcl @@ -19,12 +19,12 @@ ad_ip_parameter axi_ad7405_dma CONFIG.DMA_2D_TRANSFER 0 ad_ip_parameter axi_ad7405_dma CONFIG.DMA_DATA_WIDTH_SRC 16 ad_ip_parameter axi_ad7405_dma CONFIG.DMA_DATA_WIDTH_DEST 64 -# MCLK generation 50 MHz +# MCLK generation 40 MHz ad_ip_instance axi_clkgen axi_adc_clkgen ad_ip_parameter axi_adc_clkgen CONFIG.VCO_DIV 1 ad_ip_parameter axi_adc_clkgen CONFIG.VCO_MUL 10 -ad_ip_parameter axi_adc_clkgen CONFIG.CLK0_DIV 20 +ad_ip_parameter axi_adc_clkgen CONFIG.CLK0_DIV 25 ad_ip_instance axi_ad7405 axi_ad7405 diff --git a/projects/ad7405_fmc/zed/system_constr_cmos.xdc b/projects/ad7405_fmc/zed/system_constr_cmos.xdc index 03546ee2f23..232032102b5 100644 --- a/projects/ad7405_fmc/zed/system_constr_cmos.xdc +++ b/projects/ad7405_fmc/zed/system_constr_cmos.xdc @@ -5,3 +5,11 @@ set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports adc_clk] ; ## G6 FMC_LA00_CC_P set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports adc_data] ; ## G7 FMC_LA00_CC_N + +set input_clock mmcm_clk_0_s +set input_clock_period 20.000; # Period of input clock +set dv_bre 10.000; # Data valid before the rising clock edge +set dv_are 3.000 +set input_ports adc_data +set_input_delay -clock $input_clock -max [expr $input_clock_period - $dv_bre] [get_ports $input_ports]; +set_input_delay -clock $input_clock -min $dv_are [get_ports $input_ports];