ad9081: vck190: Added support for JESD204B

ad9209: vck190: system_top: Changed serial connections

Signed-off-by: Bogdan Luncan <[email protected]>

Author: bluncan

library/jesd204/jesd204_versal_gt_adapter_rx/Makefile

@@ -7,6 +7,7 @@
 LIBRARY_NAME := jesd204_versal_gt_adapter_rx
 
 GENERIC_DEPS += jesd204_versal_gt_adapter_rx.v
+GENERIC_DEPS += lane_align.v
 
 XILINX_DEPS += ../jesd204_common/sync_header_align.v
 XILINX_DEPS += jesd204_versal_gt_adapter_rx_ip.tcl

library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx.v

@@ -7,20 +7,34 @@
 
 `timescale 1ns/100ps
 
-module  jesd204_versal_gt_adapter_rx (
+module  jesd204_versal_gt_adapter_rx #(
+    parameter LINK_MODE = 2 // 1 - 8B10B, 2 - 64B66B
+  )(
+  // Interface to Physical Layer
   input  [127 : 0] rxdata,
-  input    [5 : 0] rxheader,
+  input  [  5 : 0] rxheader,
+  input  [ 15 : 0] rxctrl0,
+  input  [ 15 : 0] rxctrl1,
+  input  [  7 : 0] rxctrl2,
+  input  [  7 : 0] rxctrl3,
   output           rxgearboxslip,
-  input    [1 : 0] rxheadervalid,
+  input  [  1 : 0] rxheadervalid,
+  output           rxslide,
 
   // Interface to Link layer core
-  output  [63:0]  rx_data,
-  output   [1:0]  rx_header,
-  output          rx_block_sync,
+  output [ 63 : 0]  rx_data,
+  output [  3 : 0]  rx_charisk,
+  output [  3 : 0]  rx_disperr,
+  output [  3 : 0]  rx_notintable,
+  output [  1 : 0]  rx_header,
+  output            rx_block_sync,
+  input             en_char_align,
 
-  input           usr_clk
+  input             resetn,
+  input             usr_clk
 );
 
+generate if (LINK_MODE == 2) begin
   // Sync header alignment
   wire rx_bitslip_req_s;
   reg [4:0] rx_bitslip_done_cnt = 'h0;
@@ -56,4 +70,29 @@ module  jesd204_versal_gt_adapter_rx (
     .o_header(rx_header),
     .o_block_sync(rx_block_sync));
 
+    assign rx_disperr    = 4'b0;
+    assign rx_charisk    = 4'b0;
+    assign rx_notintable = 4'b0;
+    assign rxslide       = 1'b0;
+  end else begin
+    assign rx_data       = {32'b0, rxdata[31:0]};
+    assign rx_header     = rxheader[1:0];
+
+    assign rx_charisk    = rxctrl0[3:0];
+    assign rx_disperr    = rxctrl1[3:0];
+    assign rx_notintable = rxctrl3[3:0];
+    assign rx_block_sync = 1'b0;
+    assign rxgearboxslip = 1'b0;
+
+    lane_align i_lane_align (
+      .usr_clk  (usr_clk),
+      .resetn   (resetn),
+      .rxdata   (rxdata[31:0]),
+      .rx_slide (rxslide),
+      .en_char_align (en_char_align)
+    );
+
+  end
+  endgenerate
+
 endmodule

library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx_ip.tcl

@@ -9,6 +9,7 @@ source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
 adi_ip_create jesd204_versal_gt_adapter_rx
 adi_ip_files jesd204_versal_gt_adapter_rx [list \
   jesd204_versal_gt_adapter_rx.v \
+  lane_align.v \
   ../jesd204_common/sync_header_align.v \
   ]
 
@@ -23,6 +24,9 @@ adi_add_bus "RX" "master" \
   { \
    { "rx_data" "rxdata" } \
    { "rx_header" "rxheader" } \
+   { "rx_charisk" "rxcharisk"} \
+   { "rx_disperr" "rxdisperr"} \
+   { "rx_notintable" "rxnotintable"} \
    { "rx_block_sync" "rxblock_sync" } \
   }
 
@@ -32,6 +36,11 @@ adi_add_bus "RX_GT_IP_Interface" "master" \
   { \
    { "rxdata" "ch_rxdata" } \
    { "rxheader" "ch_rxheader" } \
+   { "rxctrl0"  "ch_rxctrl0"  } \
+   { "rxctrl1"  "ch_rxctrl1"  } \
+   { "rxctrl2"  "ch_rxctrl2"  } \
+   { "rxctrl3"  "ch_rxctrl3"  } \
+   { "rxslide"   "ch_rxslide" } \
    { "rxheadervalid" "ch_rxheadervalid" } \
    { "rxgearboxslip" "ch_rxgearboxslip" } \
   }

library/jesd204/jesd204_versal_gt_adapter_rx/lane_align.v

@@ -0,0 +1,74 @@
+module lane_align (
+  input         usr_clk,
+  input         resetn,
+  input  [31:0] rxdata,
+  input         en_char_align,
+  output        rx_slide
+);
+
+  localparam K_CHARACTER = 32'hBCBCBCBC;
+
+  localparam WAIT_FOR_CHAR_ALIGN = 0;
+  localparam CHECK_ALIGNMENT = 1;
+  localparam PULSE_SLIDE = 2;
+  localparam WAIT_DELAY  = 3;
+
+  reg  [2:0] state;
+  reg  [2:0] next_state;
+  reg  [5:0] counter;
+  reg  [5:0] next_counter;
+  wire       rx_slide_s;
+
+  always @(negedge resetn or posedge usr_clk) begin
+    if (!resetn) begin
+      state <= WAIT_FOR_CHAR_ALIGN;
+      counter <= 'd0;
+    end else begin
+      state <= next_state;
+      counter <= next_counter;
+    end
+  end
+
+  always @(*) begin
+    next_counter <= counter;
+    case (state)
+      WAIT_FOR_CHAR_ALIGN: begin
+        if (en_char_align) begin
+          next_state <= CHECK_ALIGNMENT;
+        end else begin
+          next_state <= WAIT_FOR_CHAR_ALIGN;
+        end
+      end
+      CHECK_ALIGNMENT: begin
+        if (rxdata == K_CHARACTER) begin
+          next_state <= WAIT_FOR_CHAR_ALIGN;
+        end else begin
+          next_counter <= 'd0;
+          next_state <= PULSE_SLIDE;
+        end
+      end
+      PULSE_SLIDE: begin // a pulse is valid only if it takes 2 usr_clk cycles
+        if (counter == 'd1) begin
+          next_state <= WAIT_DELAY;
+          next_counter <= 'd0;
+        end else begin
+          next_state <= PULSE_SLIDE;
+          next_counter <= counter + 1'b1;
+        end
+      end
+      WAIT_DELAY: begin // wait 32 usr_clk cycles between each pulse
+        if (counter == 'd32) begin
+          next_state <= CHECK_ALIGNMENT;
+        end else begin
+          next_state <= WAIT_DELAY;
+          next_counter <= counter + 1'b1;
+        end
+      end
+    endcase
+  end
+
+  assign rx_slide_s = (state == PULSE_SLIDE)? 1'b1 : 1'b0;
+
+  assign rx_slide = rx_slide_s;
+
+endmodule

library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx.v

@@ -7,25 +7,41 @@
 
 `timescale 1ns/100ps
 
-module  jesd204_versal_gt_adapter_tx (
+module  jesd204_versal_gt_adapter_tx #(
+    parameter LINK_MODE = 2 // 1 - 8B10B, 2 - 64B66B
+  )(
   output  [127 : 0] txdata,
-  output    [5 : 0] txheader,
-
+  output  [  5 : 0] txheader,
+  output  [ 15 : 0] txctrl0,
+  output  [ 15 : 0] txctrl1,
+  output  [  7 : 0] txctrl2,
   // Interface to Link layer core
-  input      [63:0] tx_data,
-  input       [1:0] tx_header,
+  input   [ 63 : 0] tx_data,
+  input   [  1 : 0] tx_header,
+  input   [  3 : 0] tx_charisk,
 
   input             usr_clk
 );
 
-  wire [63:0] tx_data_flip;
-  genvar i;
-  for (i = 0; i < 64; i=i+1) begin
-    assign tx_data_flip[63-i] = tx_data[i];
-  end
+  generate if (LINK_MODE == 2) begin
+    wire [63:0] tx_data_flip;
+    genvar i;
+    for (i = 0; i < 64; i=i+1) begin
+      assign tx_data_flip[63-i] = tx_data[i];
+    end
 
-  assign txdata = {64'b0,tx_data_flip};
-  // Flip header bits and data
-  assign txheader = {4'b0,tx_header[0],tx_header[1]};
+    assign txdata   = {64'b0, tx_data_flip};
+    assign txheader = {4'b0, tx_header[0], tx_header[1]};
+    assign txctrl0  = 16'b0;
+    assign txctrl1  = 16'b0;
+    assign txctrl2  = 16'b0;
+  end else begin
+    assign txdata   = {96'b0, tx_data[31:0]};
+    assign txheader = {4'b0, tx_header};
+    assign txctrl0  = 16'b0;
+    assign txctrl1  = 16'b0;
+    assign txctrl2  = {4'b0, tx_charisk};
+  end
+  endgenerate
 
 endmodule

library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx_ip.tcl

@@ -22,6 +22,9 @@ adi_add_bus "TX_GT_IP_Interface" "master" \
   { \
    { "txdata" "ch_txdata" } \
    { "txheader" "ch_txheader" } \
+   { "txctrl0"  "ch_txctrl0"  } \
+   { "txctrl1"  "ch_txctrl1"  } \
+   { "txctrl2"  "ch_txctrl2"  } \
   }
 
 adi_add_bus "TX" "slave" \
@@ -30,6 +33,7 @@ adi_add_bus "TX" "slave" \
   { \
    { "tx_data" "txdata" } \
    { "tx_header" "txheader" } \
+   { "tx_charisk" "txcharisk" } \
   }
 
 ipx::save_core [ipx::current_core]