diff --git a/MAX/CMakeLists.txt b/MAX/CMakeLists.txt index eb6414c4..69499e2a 100644 --- a/MAX/CMakeLists.txt +++ b/MAX/CMakeLists.txt @@ -40,6 +40,7 @@ set(MSDK_PERIPH_INC_DIR ${MSDK_PERIPH_DIR}/Include/${TARGET_UC}) zephyr_include_directories( ./Include + ${MSDK_LIBRARY_DIR}/CMSIS/Include ${MSDK_CMSIS_DIR}/Include ${MSDK_PERIPH_INC_DIR} ) diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/max32665.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/max32665.h index 712a0c64..54d1e0cc 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/max32665.h +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/max32665.h @@ -21,6 +21,8 @@ #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_MAX32665_H_ #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_MAX32665_H_ +// clang-format off + #ifndef TARGET_NUM #define TARGET_NUM 32665 #endif @@ -178,15 +180,16 @@ typedef enum { /* ================================================================================ */ /* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */ -#define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ -#include /*!< Cortex-M4 processor and core peripherals */ +#include /*!< Cortex-M4 processor and core peripherals */ -#include "system_max32665.h" /*!< System Header */ +#include "system_max32665.h" /*!< System Header */ +#include "system_core1_max32665.h" /*!< System Header for Core 1 */ /* ================================================================================ */ /* ================== Device Specific Memory Section ================== */ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/system_core1_max32665.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/system_core1_max32665.h new file mode 100644 index 00000000..a206d719 --- /dev/null +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/system_core1_max32665.h @@ -0,0 +1,59 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_SYSTEM_CORE1_MAX32665_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_SYSTEM_CORE1_MAX32665_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @brief Start Core 1 code. + */ +void Start_Core1(void); + +/** + * @brief Stops Core 1 by disabling CPU1 clock. + */ +void Stop_Core1(void); + +/** + * @brief Main function for Core 1 Code. + * The user should override this function in their application code. + */ +int main_core1(void); + +/** + * @brief Equivalent to PreInit for Core 0, + * Can be used for preliminary initialization. + */ +void PreInit_Core1(void); + +/** + * @brief Initialize the system for Core 1. + */ +void SystemInit_Core1(void); + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_SYSTEM_CORE1_MAX32665_H_ diff --git a/MAX/Libraries/PeriphDrivers/Source/CORE1/system_core1.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Source/system_core1_max32665.c similarity index 54% rename from MAX/Libraries/PeriphDrivers/Source/CORE1/system_core1.c rename to MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Source/system_core1_max32665.c index f1cbd38b..74a277be 100644 --- a/MAX/Libraries/PeriphDrivers/Source/CORE1/system_core1.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Source/system_core1_max32665.c @@ -18,64 +18,66 @@ * ******************************************************************************/ -/** - * @file core1startup.c - * @brief Startup Code for MAX32665 Family CPU1 - * @details These functions are called at the startup of the second ARM core (CPU1/Core1) - */ #include #include #include -#include "max32665.h" +#include "mxc_device.h" #include "mxc_sys.h" #include "gcr_regs.h" -#include "icc_regs.h" -#include "pwrseq_regs.h" -extern uint32_t __isr_vector_core1; +extern void (*const __isr_vector_core1[])(void); -void Core1_Start(void) +void Start_Core1(void) { - MXC_GCR->gp0 = (uint32_t)(&__isr_vector_core1); + // Save Core 1 vector table location in GCR. + MXC_GCR->gp0 = (uint32_t)&__isr_vector_core1; MXC_GCR->perckcn1 &= ~MXC_F_GCR_PERCKCN1_CPU1D; } -void Core1_Stop(void) +void Stop_Core1(void) { MXC_GCR->perckcn1 |= MXC_F_GCR_PERCKCN1_CPU1D; } -__weak int Core1_Main(void) +/** + * The user declares this in application code. + */ +__weak int main_core1(void) { - // The user should declare this in application code, so we'll just spin while (1) {} } + +/** + * You may over-ride this function in your program by defining a custom + * PreInit_Core1(). + */ __weak void PreInit_Core1(void) { return; } +/** + * This function is called just before control is transferred to main() + * on Core 1. + * + * You may over-ride this function in your program by defining a custom + * SystemInit(), but care should be taken to reproduce the initialization + * steps or a non-functional system may result. + */ __weak void SystemInit_Core1(void) { - /* Configure the interrupt controller to use the application vector table in - * the application space */ + /** + * Configure the interrupt controller to use the application vector + * table in flash. Initially, VTOR points to the ROM's table. + */ SCB->VTOR = (uint32_t)&__isr_vector_core1; - /* Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11 - * Grant full access, per "Table B3-24 CPACR bit assignments". - * DDI0403D "ARMv7-M Architecture Reference Manual" */ + /** + * Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11 + * Grant full access, per "Table B3-24 CPACR bit assignments". + * DDI0403D "ARMv7-M Architecture Reference Manual" + */ SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk; __DSB(); __ISB(); - - // Enable ICache1 Clock - MXC_GCR->perckcn1 &= ~(1 << 22); - - // Invalidate cache and wait until ready - MXC_ICC1->invalidate = 1; - while (!(MXC_ICC1->cache_ctrl & MXC_F_ICC_CACHE_CTRL_RDY)) {} - - // Enable Cache - MXC_ICC1->cache_ctrl |= MXC_F_ICC_CACHE_CTRL_EN; - while (!(MXC_ICC1->cache_ctrl & MXC_F_ICC_CACHE_CTRL_RDY)) {} } diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32665/core1.h b/MAX/Libraries/PeriphDrivers/Include/MAX32665/core1.h index 6cf98e7c..eb8e86c6 100644 --- a/MAX/Libraries/PeriphDrivers/Include/MAX32665/core1.h +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32665/core1.h @@ -25,6 +25,12 @@ extern "C" { #endif +#include "mxc_device.h" + +#warning "core1.h is deprecated (05-24-2024)." +#warning "Use mxc_device.h instead, and set `ARM_DUALCORE=1` in project.mk" +#warning "Core 1 Startup/System code is located at Libraries/CMSIS/Device/Maxim/MAX32665/" + /** * @file core1.h * @brief Startup Code for MAX32665 Family CPU1 @@ -35,32 +41,36 @@ extern "C" { * @brief Starts the code on core 1 * Core1 code beings executing from Core1_Main() */ -void Core1_Start(void); +#if defined(__GNUC__) +inline __attribute__((deprecated("Use Start_Core1(); instead."))) void Core1_Start(void) +{ + Start_Core1(); +} +#endif /** * @brief Stops code executing in Core 1 */ -void Core1_Stop(void); +#if defined(__GNUC__) +inline __attribute__((deprecated("Use Stop_Core1(); instead."))) void Core1_Stop(void) +{ + Stop_Core1(); +} +#endif /** * @brief Main function for Core 1 Code * The user should override this function * in their application code */ -int Core1_Main(void); - -/** - * @brief Equivalent to PreInit for Core 0 - * Can be used for preliminary initialization - */ -void PreInit_Core1(void); +#if defined(__GNUC__) +inline __attribute__((deprecated( + "Use `int main_core1(void)` instead - main_core1 is Core 1's entry point where code starts, not Core1_Main."))) int +Core1_Main(void); +#endif -/** - * @brief Equivalent to PreInit for Core 1 - * Enables FPU, and ICache - * Sets interrupt vector - */ -void SystemInit_Core1(void); +// void PreInit_Core1(void) is now located in system_core_max32665.h +// void SystemInit_Core1(void) is now located in system_core_max32665.h #ifdef __cplusplus } diff --git a/MAX/Libraries/PeriphDrivers/Source/CORE1/startup_core1.S b/MAX/Libraries/PeriphDrivers/Source/CORE1/startup_core1.S deleted file mode 100644 index 328a4dde..00000000 --- a/MAX/Libraries/PeriphDrivers/Source/CORE1/startup_core1.S +++ /dev/null @@ -1,156 +0,0 @@ - .syntax unified - .arch armv7-m - - .section .stack_core1 - .align 3 - .globl Stack_Size_Core1 -#ifdef __STACK_SIZE_CORE1 - .equ Stack_Size_Core1, __STACK_SIZE -#else - .equ Stack_Size_Core1, 0x00001000 -#endif - .globl __StackTop_Core1 -__StackTop_Core1: - .size __StackTop_Core1, . - __StackTop_Core1 - - .section .text - .align 0x10 - .globl __isr_vector_core1 -__isr_vector_core1: - .long __StackTop_Core1 /* Top of Core 1 Stack */ - .long Reset_Handler_Core1 /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long MemManage_Handler /* MPU Fault Handler */ - .long BusFault_Handler /* Bus Fault Handler */ - .long UsageFault_Handler /* Usage Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* Device-specific Interrupts */ - .long PF_IRQHandler /* 0x10 0x0040 16: Power Fail */ - .long WDT0_IRQHandler /* 0x11 0x0044 17: Watchdog 0 */ - .long USB_IRQHandler /* 0x12 0x0048 18: USB */ - .long RTC_IRQHandler /* 0x13 0x004C 19: RTC */ - .long TRNG_IRQHandler /* 0x14 0x0050 20: True Random Number Generator */ - .long TMR0_IRQHandler /* 0x15 0x0054 21: Timer 0 */ - .long TMR1_IRQHandler /* 0x16 0x0058 22: Timer 1 */ - .long TMR2_IRQHandler /* 0x17 0x005C 23: Timer 2 */ - .long TMR3_IRQHandler /* 0x18 0x0060 24: Timer 3*/ - .long TMR4_IRQHandler /* 0x19 0x0064 25: Timer 4*/ - .long TMR5_IRQHandler /* 0x1A 0x0068 26: Timer 5 */ - .long RSV11_IRQHandler /* 0x1B 0x006C 27: Reserved */ - .long RSV12_IRQHandler /* 0x1C 0x0070 28: Reserved */ - .long I2C0_IRQHandler /* 0x1D 0x0074 29: I2C0 */ - .long UART0_IRQHandler /* 0x1E 0x0078 30: UART 0 */ - .long UART1_IRQHandler /* 0x1F 0x007C 31: UART 1 */ - .long SPI1_IRQHandler /* 0x20 0x0080 32: SPI1 */ - .long SPI2_IRQHandler /* 0x21 0x0084 33: SPI2 */ - .long RSV18_IRQHandler /* 0x22 0x0088 34: Reserved */ - .long RSV19_IRQHandler /* 0x23 0x008C 35: Reserved */ - .long ADC_IRQHandler /* 0x24 0x0090 36: ADC */ - .long RSV21_IRQHandler /* 0x25 0x0094 37: Reserved */ - .long RSV22_IRQHandler /* 0x26 0x0098 38: Reserved */ - .long FLC0_IRQHandler /* 0x27 0x009C 39: Flash Controller */ - .long GPIO0_IRQHandler /* 0x28 0x00A0 40: GPIO0 */ - .long GPIO1_IRQHandler /* 0x29 0x00A4 41: GPIO2 */ - .long RSV26_IRQHandler /* 0x2A 0x00A8 42: GPIO3 */ - .long TPU_IRQHandler /* 0x2B 0x00AC 43: Crypto */ - .long DMA0_IRQHandler /* 0x2C 0x00B0 44: DMA0 */ - .long DMA1_IRQHandler /* 0x2D 0x00B4 45: DMA1 */ - .long DMA2_IRQHandler /* 0x2E 0x00B8 46: DMA2 */ - .long DMA3_IRQHandler /* 0x2F 0x00BC 47: DMA3 */ - .long RSV32_IRQHandler /* 0x30 0x00C0 48: Reserved */ - .long RSV33_IRQHandler /* 0x31 0x00C4 49: Reserved */ - .long UART2_IRQHandler /* 0x32 0x00C8 50: UART 2 */ - .long RSV35_IRQHandler /* 0x33 0x00CC 51: Reserved */ - .long I2C1_IRQHandler /* 0x34 0x00D0 52: I2C1 */ - .long RSV37_IRQHandler /* 0x35 0x00D4 53: Reserved */ - .long SPIXFC_IRQHandler /* 0x36 0x00D8 54: SPI execute in place */ - .long BTLE_TX_DONE_IRQHandler /* 0x37 0x00DC 55: BTLE TX Done */ - .long BTLE_RX_RCVD_IRQHandler /* 0x38 0x00E0 56: BTLE RX Recived */ - .long BTLE_RX_ENG_DET_IRQHandler /* 0x39 0x00E4 57: BTLE RX Energy Dectected */ - .long BTLE_SFD_DET_IRQHandler /* 0x3A 0x00E8 58: BTLE SFD Detected */ - .long BTLE_SFD_TO_IRQHandler /* 0x3B 0x00EC 59: BTLE SFD Timeout*/ - .long BTLE_GP_EVENT_IRQHandler /* 0x3C 0x00F0 60: BTLE Timestamp*/ - .long BTLE_CFO_IRQHandler /* 0x3D 0x00F4 61: BTLE CFO Done */ - .long BTLE_SIG_DET_IRQHandler /* 0x3E 0x00F8 62: BTLE Signal Detected */ - .long BTLE_AGC_EVENT_IRQHandler /* 0x3F 0x00FC 63: BTLE AGC Event */ - .long BTLE_RFFE_SPIM_IRQHandler /* 0x40 0x0100 64: BTLE RFFE SPIM Done */ - .long BTLE_TX_AES_IRQHandler /* 0x41 0x0104 65: BTLE TX AES Done */ - .long BTLE_RX_AES_IRQHandler /* 0x42 0x0108 66: BTLE RX AES Done */ - .long BTLE_INV_APB_ADDR_IRQHandler /* 0x43 0x010C 67: BTLE Invalid APB Address*/ - .long BTLE_IQ_DATA_VALID_IRQHandler /* 0x44 0x0110 68: BTLE IQ Data Valid */ - .long WUT_IRQHandler /* 0x45 0x0114 69: WUT Wakeup */ - .long GPIOWAKE_IRQHandler /* 0x46 0x0118 70: GPIO Wakeup */ - .long RSV55_IRQHandler /* 0x47 0x011C 71: Reserved */ - .long SPI0_IRQHandler /* 0x48 0x0120 72: SPI AHB */ - .long WDT1_IRQHandler /* 0x49 0x0124 73: Watchdog 1 */ - .long RSV58_IRQHandler /* 0x4A 0x0128 74: Reserved */ - .long PT_IRQHandler /* 0x4B 0x012C 75: Pulse train */ - .long SDMA0_IRQHandler /* 0x4C 0x0130 76: Smart DMA 0 */ - .long RSV61_IRQHandler /* 0x4D 0x0134 77: Reserved */ - .long I2C2_IRQHandler /* 0x4E 0x0138 78: I2C 2 */ - .long RSV63_IRQHandler /* 0x4F 0x013C 79: Reserved */ - .long RSV64_IRQHandler /* 0x50 0x0140 80: Reserved */ - .long RSV65_IRQHandler /* 0x51 0x0144 81: Reserved */ - .long SDHC_IRQHandler /* 0x52 0x0148 82: SDIO/SDHC */ - .long OWM_IRQHandler /* 0x53 0x014C 83: One Wire Master */ - .long DMA4_IRQHandler /* 0x54 0x0150 84: DMA4 */ - .long DMA5_IRQHandler /* 0x55 0x0154 85: DMA5 */ - .long DMA6_IRQHandler /* 0x56 0x0158 86: DMA6 */ - .long DMA7_IRQHandler /* 0x57 0x015C 87: DMA7 */ - .long DMA8_IRQHandler /* 0x58 0x0160 88: DMA8 */ - .long DMA9_IRQHandler /* 0x59 0x0164 89: DMA9 */ - .long DMA10_IRQHandler /* 0x5A 0x0168 90: DMA10 */ - .long DMA11_IRQHandler /* 0x5B 0x016C 91: DMA11 */ - .long DMA12_IRQHandler /* 0x5C 0x0170 92: DMA12 */ - .long DMA13_IRQHandler /* 0x5D 0x0174 93: DMA13 */ - .long DMA14_IRQHandler /* 0x5E 0x0178 94: DMA14 */ - .long DMA15_IRQHandler /* 0x5F 0x017C 95: DMA15 */ - .long USBDMA_IRQHandler /* 0x60 0x0180 96: USB DMA */ - .long WDT2_IRQHandler /* 0x61 0x0184 97: Watchdog Timer 2 */ - .long ECC_IRQHandler /* 0x62 0x0188 98: Error Correction */ - .long DVS_IRQHandler /* 0x63 0x018C 99: DVS Controller */ - .long SIMO_IRQHandler /* 0x64 0x0190 100: SIMO Controller */ - .long SCA_IRQHandler /* 0x65 0x0194 101: SCA */ - .long AUDIO_IRQHandler /* 0x66 0x0198 102: Audio subsystem */ - .long FLC1_IRQHandler /* 0x67 0x019C 103: Flash Control 1 */ - .long RSV88_IRQHandler /* 0x68 0x01A0 104: UART 3 */ - .long RSV89_IRQHandler /* 0x69 0x01A4 105: UART 4 */ - .long RSV90_IRQHandler /* 0x6A 0x01A8 106: UART 5 */ - .long RSV91_IRQHandler /* 0x6B 0x01AC 107: Camera IF */ - .long RSV92_IRQHandler /* 0x6C 0x01B0 108: I3C */ - .long HTMR0_IRQHandler /* 0x6D 0x01B4 109: HTimer */ - .long HTMR1_IRQHandler /* 0x6E 0x01B8 109: HTimer */ - .thumb - .thumb_func - .align 2 - .globl Core1_Init - .type Core1_Init, %function -Reset_Handler_Core1: - ldr r0, =__StackTop_Core1 - mov sp, r0 - /* PreInit runs before any RAM initialization. Example usage: DDR setup, etc. */ - ldr r0, =PreInit_Core1 - blx r0 - - /* Perform system initialization after RAM initialization */ - - ldr r0, =SystemInit_Core1 - blx r0 - - /* Transfer control to users main program */ - ldr r0, =Core1_Main - blx r0 - -.SPINC1: - /* spin if main ever returns. */ - bl .SPINC1 diff --git a/MAX/Libraries/PeriphDrivers/Source/I2C/i2c_me18.c b/MAX/Libraries/PeriphDrivers/Source/I2C/i2c_me18.c index 315372c7..b038559e 100644 --- a/MAX/Libraries/PeriphDrivers/Source/I2C/i2c_me18.c +++ b/MAX/Libraries/PeriphDrivers/Source/I2C/i2c_me18.c @@ -54,18 +54,29 @@ int MXC_I2C_Init(mxc_i2c_regs_t *i2c, int masterMode, unsigned int slaveAddr) * * See MAX32690 Rev A2 Errata #16: * https://www.analog.com/media/en/technical-documentation/data-sheets/max32690_a2_errata_rev2.pdf + * + * Additionally, note that the TQFN package does not expose some of the duplicate pins. For this package, + * enabling the un-routed GPIOs has been shown to cause initialization issues with the I2C block. + * To work around this, "MAX32690GTK_PACKAGE_TQFN" can be defined by the build system. The recommend place + * to do it is in the "board.mk" file of the BSP. This will prevent the inaccessible pins from being configured. */ if (i2c == MXC_I2C0) { MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C0); MXC_GPIO_Config(&gpio_cfg_i2c0); +#ifndef MAX32690GTK_PACKAGE_TQFN MXC_GPIO_Config(&gpio_cfg_i2c0a); +#endif } else if (i2c == MXC_I2C1) { MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C1); MXC_GPIO_Config(&gpio_cfg_i2c1); +#ifndef MAX32690GTK_PACKAGE_TQFN MXC_GPIO_Config(&gpio_cfg_i2c1a); +#endif } else if (i2c == MXC_I2C2) { MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C2); +#ifndef MAX32690GTK_PACKAGE_TQFN MXC_GPIO_Config(&gpio_cfg_i2c2); +#endif MXC_GPIO_Config(&gpio_cfg_i2c2c); } else { return E_NO_DEVICE; diff --git a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_ai87.c b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_ai87.c index 9d1ce7b3..3105f9c7 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_ai87.c +++ b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_ai87.c @@ -403,34 +403,19 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; - - case 1: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; - - default: - return E_BAD_PARAM; - } - } - - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; - - case 1: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; - - default: - return E_BAD_PARAM; - } + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; + + case 1: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; + + default: + return E_BAD_PARAM; } return MXC_SPI_RevA1_MasterTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, @@ -457,36 +442,20 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; - - case 1: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; - default: - return E_BAD_PARAM; - break; - } - } + case 1: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; - - case 1: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; - - default: - return E_BAD_PARAM; - break; - } + default: + return E_BAD_PARAM; + break; } return MXC_SPI_RevA1_SlaveTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, diff --git a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_es17.c b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_es17.c index f4b82cc5..de0f94b9 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_es17.c +++ b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_es17.c @@ -252,35 +252,19 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; - - case 1: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; - - default: - return E_BAD_PARAM; - } - } - - //tx - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; - - case 1: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; - - default: - return E_BAD_PARAM; - } + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; + + case 1: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; + + default: + return E_BAD_PARAM; } return MXC_SPI_RevA1_MasterTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, @@ -307,34 +291,19 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; - case 1: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; + case 1: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; - default: - return E_BAD_PARAM; - } - } - - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; - - case 1: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; - - default: - return E_BAD_PARAM; - } + default: + return E_BAD_PARAM; } return MXC_SPI_RevA1_SlaveTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, diff --git a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me11.c b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me11.c index 6315e4bc..927f94c3 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me11.c +++ b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me11.c @@ -250,34 +250,19 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; - - case 1: - reqselTx = MXC_DMA_REQUEST_SPIMSSTX; - break; - - default: - return E_BAD_PARAM; - } - } - - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; - - case 1: - reqselTx = MXC_DMA_REQUEST_SPIMSSRX; - break; - - default: - return E_BAD_PARAM; - } + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; + + case 1: + reqselTx = MXC_DMA_REQUEST_SPIMSSTX; + reqselRx = MXC_DMA_REQUEST_SPIMSSRX; + break; + + default: + return E_BAD_PARAM; } return MXC_SPI_RevA1_MasterTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, @@ -304,34 +289,19 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; - case 1: - reqselTx = MXC_DMA_REQUEST_SPIMSSTX; - break; + case 1: + reqselTx = MXC_DMA_REQUEST_SPIMSSTX; + reqselRx = MXC_DMA_REQUEST_SPIMSSRX; + break; - default: - return E_BAD_PARAM; - } - } - - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; - - case 1: - reqselRx = MXC_DMA_REQUEST_SPIMSSRX; - break; - - default: - return E_BAD_PARAM; - } + default: + return E_BAD_PARAM; } return MXC_SPI_RevA1_SlaveTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, diff --git a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me12.c b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me12.c index ee08ebdc..be7dbc52 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me12.c +++ b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me12.c @@ -359,34 +359,19 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; - - case 1: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; - - default: - return E_BAD_PARAM; - } - } - - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; - - case 1: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; - - default: - return E_BAD_PARAM; - } + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; + + case 1: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; + + default: + return E_BAD_PARAM; } return MXC_SPI_RevA1_MasterTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, @@ -413,36 +398,20 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; - - case 1: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; - - default: - return E_BAD_PARAM; - break; - } - } - - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; - case 1: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; + case 1: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; - default: - return E_BAD_PARAM; - break; - } + default: + return E_BAD_PARAM; + break; } return MXC_SPI_RevA1_SlaveTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, diff --git a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me13.c b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me13.c index f5544910..76bcdc18 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me13.c +++ b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me13.c @@ -283,42 +283,24 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; - - case 1: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; - - case 2: - reqselTx = MXC_DMA_REQUEST_SPI2TX; - break; - - default: - return E_BAD_PARAM; - } - } - - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; - - case 1: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; - - case 2: - reqselRx = MXC_DMA_REQUEST_SPI2RX; - break; - - default: - return E_BAD_PARAM; - } + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; + + case 1: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; + + case 2: + reqselTx = MXC_DMA_REQUEST_SPI2TX; + reqselRx = MXC_DMA_REQUEST_SPI2RX; + break; + + default: + return E_BAD_PARAM; } return MXC_SPI_RevA1_MasterTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, @@ -344,42 +326,24 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; - - case 1: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; - - case 2: - reqselTx = MXC_DMA_REQUEST_SPI2TX; - break; + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; - default: - return E_BAD_PARAM; - } - } + case 1: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; + case 2: + reqselTx = MXC_DMA_REQUEST_SPI2TX; + reqselRx = MXC_DMA_REQUEST_SPI2RX; + break; - case 1: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; - - case 2: - reqselRx = MXC_DMA_REQUEST_SPI2RX; - break; - - default: - return E_BAD_PARAM; - } + default: + return E_BAD_PARAM; } return MXC_SPI_RevA1_SlaveTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, diff --git a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me14.c b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me14.c index a1f742e9..70eeb41e 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me14.c +++ b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me14.c @@ -348,42 +348,24 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req, mxc_dma_regs_t *dma) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; - - case 1: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; - - case 2: - reqselTx = MXC_DMA_REQUEST_SPI2TX; - break; - - default: - return E_BAD_PARAM; - } - } - - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; - - case 1: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; - - case 2: - reqselRx = MXC_DMA_REQUEST_SPI2RX; - break; - - default: - return E_BAD_PARAM; - } + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; + + case 1: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; + + case 2: + reqselTx = MXC_DMA_REQUEST_SPI2TX; + reqselRx = MXC_DMA_REQUEST_SPI2RX; + break; + + default: + return E_BAD_PARAM; } return MXC_SPI_RevA1_MasterTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, dma); @@ -413,42 +395,24 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req, mxc_dma_regs_t *dma) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; - - case 1: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; - case 2: - reqselTx = MXC_DMA_REQUEST_SPI2TX; - break; - - default: - return E_BAD_PARAM; - } - } + case 1: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; + case 2: + reqselTx = MXC_DMA_REQUEST_SPI2TX; + reqselRx = MXC_DMA_REQUEST_SPI2RX; + break; - case 1: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; - - case 2: - reqselRx = MXC_DMA_REQUEST_SPI2RX; - break; - - default: - return E_BAD_PARAM; - } + default: + return E_BAD_PARAM; } return MXC_SPI_RevA1_SlaveTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, dma); diff --git a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me15.c b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me15.c index 78edd791..f82cee59 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me15.c +++ b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me15.c @@ -264,42 +264,24 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; - - case 1: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; - - case 2: - reqselTx = MXC_DMA_REQUEST_SPI2TX; - break; - - default: - return E_BAD_PARAM; - } - } - - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; - - case 1: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; - - case 2: - reqselRx = MXC_DMA_REQUEST_SPI2RX; - break; - - default: - return E_BAD_PARAM; - } + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; + + case 1: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; + + case 2: + reqselTx = MXC_DMA_REQUEST_SPI2TX; + reqselRx = MXC_DMA_REQUEST_SPI2RX; + break; + + default: + return E_BAD_PARAM; } return MXC_SPI_RevA1_MasterTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, @@ -326,42 +308,24 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; - case 1: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; + case 1: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; - case 2: - reqselTx = MXC_DMA_REQUEST_SPI2TX; - break; + case 2: + reqselTx = MXC_DMA_REQUEST_SPI2TX; + reqselRx = MXC_DMA_REQUEST_SPI2RX; + break; - default: - return E_BAD_PARAM; - } - } - - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; - - case 1: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; - - case 2: - reqselRx = MXC_DMA_REQUEST_SPI2RX; - break; - - default: - return E_BAD_PARAM; - } + default: + return E_BAD_PARAM; } return MXC_SPI_RevA1_SlaveTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, MXC_DMA); diff --git a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me16.c b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me16.c index a2e09344..5be9927d 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me16.c +++ b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me16.c @@ -260,44 +260,26 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; - - case 1: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; - - case 2: - reqselTx = MXC_DMA_REQUEST_SPI2TX; - break; - - case 3: - reqselTx = MXC_DMA_REQUEST_SPI3TX; - break; - } - } - - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI0TX; - break; - - case 1: - reqselRx = MXC_DMA_REQUEST_SPI1TX; - break; - - case 2: - reqselRx = MXC_DMA_REQUEST_SPI2TX; - break; - - case 3: - reqselRx = MXC_DMA_REQUEST_SPI3TX; - break; - } + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0TX; + break; + + case 1: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1TX; + break; + + case 2: + reqselTx = MXC_DMA_REQUEST_SPI2TX; + reqselRx = MXC_DMA_REQUEST_SPI2TX; + break; + + case 3: + reqselTx = MXC_DMA_REQUEST_SPI3TX; + reqselRx = MXC_DMA_REQUEST_SPI3TX; + break; } return MXC_SPI_RevA1_MasterTransactionDMA(req, reqselTx, reqselRx); @@ -323,44 +305,26 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; - - case 1: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; - - case 2: - reqselTx = MXC_DMA_REQUEST_SPI2TX; - break; - - case 3: - reqselTx = MXC_DMA_REQUEST_SPI3TX; - break; - } - } - - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI0TX; - break; - - case 1: - reqselRx = MXC_DMA_REQUEST_SPI1TX; - break; - - case 2: - reqselRx = MXC_DMA_REQUEST_SPI2TX; - break; - - case 3: - reqselRx = MXC_DMA_REQUEST_SPI3TX; - break; - } + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0TX; + break; + + case 1: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1TX; + break; + + case 2: + reqselTx = MXC_DMA_REQUEST_SPI2TX; + reqselRx = MXC_DMA_REQUEST_SPI2TX; + break; + + case 3: + reqselTx = MXC_DMA_REQUEST_SPI3TX; + reqselRx = MXC_DMA_REQUEST_SPI3TX; + break; } return MXC_SPI_RevA1_SlaveTransactionDMA(req, reqselTx, reqselRx); diff --git a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me17.c b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me17.c index 21a546d6..a796c315 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me17.c +++ b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me17.c @@ -417,34 +417,19 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; - - case 1: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; - - default: - return E_BAD_PARAM; - } - } - - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; - - case 1: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; - - default: - return E_BAD_PARAM; - } + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; + + case 1: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; + + default: + return E_BAD_PARAM; } return MXC_SPI_RevA1_MasterTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, @@ -471,36 +456,20 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; - - case 1: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; - default: - return E_BAD_PARAM; - break; - } - } + case 1: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; - - case 1: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; - - default: - return E_BAD_PARAM; - break; - } + default: + return E_BAD_PARAM; + break; } return MXC_SPI_RevA1_SlaveTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, diff --git a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me18.c b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me18.c index 9fee2573..9d6c3b21 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me18.c +++ b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me18.c @@ -390,48 +390,29 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; - case 1: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; - case 2: - reqselTx = MXC_DMA_REQUEST_SPI2TX; - break; - case 3: - reqselTx = MXC_DMA_REQUEST_SPI3TX; - break; - case 4: - reqselTx = MXC_DMA_REQUEST_SPI4TX; - break; - default: - return E_BAD_PARAM; - } - } - - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; - case 1: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; - case 2: - reqselRx = MXC_DMA_REQUEST_SPI2RX; - break; - case 3: - reqselRx = MXC_DMA_REQUEST_SPI3RX; - break; - case 4: - reqselRx = MXC_DMA_REQUEST_SPI4RX; - break; - default: - return E_BAD_PARAM; - } + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; + case 1: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; + case 2: + reqselTx = MXC_DMA_REQUEST_SPI2TX; + reqselRx = MXC_DMA_REQUEST_SPI2RX; + break; + case 3: + reqselTx = MXC_DMA_REQUEST_SPI3TX; + reqselRx = MXC_DMA_REQUEST_SPI3RX; + break; + case 4: + reqselTx = MXC_DMA_REQUEST_SPI4TX; + reqselRx = MXC_DMA_REQUEST_SPI4RX; + break; + default: + return E_BAD_PARAM; } return MXC_SPI_RevA1_MasterTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, @@ -458,50 +439,30 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI0TX; - break; - case 1: - reqselRx = MXC_DMA_REQUEST_SPI1TX; - break; - case 2: - reqselTx = MXC_DMA_REQUEST_SPI2TX; - break; - case 3: - reqselTx = MXC_DMA_REQUEST_SPI3TX; - break; - case 4: - reqselTx = MXC_DMA_REQUEST_SPI4TX; - break; - default: - return E_BAD_PARAM; - break; - } - } - - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; - case 1: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; - case 2: - reqselTx = MXC_DMA_REQUEST_SPI2RX; - break; - case 3: - reqselTx = MXC_DMA_REQUEST_SPI3RX; - break; - case 4: - reqselTx = MXC_DMA_REQUEST_SPI4RX; - break; - default: - return E_BAD_PARAM; - break; - } + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; + case 1: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; + case 2: + reqselTx = MXC_DMA_REQUEST_SPI2TX; + reqselRx = MXC_DMA_REQUEST_SPI2RX; + break; + case 3: + reqselTx = MXC_DMA_REQUEST_SPI3TX; + reqselRx = MXC_DMA_REQUEST_SPI3RX; + break; + case 4: + reqselTx = MXC_DMA_REQUEST_SPI4TX; + reqselRx = MXC_DMA_REQUEST_SPI4RX; + break; + default: + return E_BAD_PARAM; + break; } return MXC_SPI_RevA1_SlaveTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, diff --git a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me21.c b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me21.c index 35aec655..738c0652 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me21.c +++ b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me21.c @@ -281,42 +281,24 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; - - case 1: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; - - case 2: - reqselTx = MXC_DMA_REQUEST_SPI2TX; - break; - - default: - return E_BAD_PARAM; - } - } - - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; - - case 1: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; - - case 2: - reqselRx = MXC_DMA_REQUEST_SPI2RX; - break; - - default: - return E_BAD_PARAM; - } + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; + + case 1: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; + + case 2: + reqselTx = MXC_DMA_REQUEST_SPI2TX; + reqselRx = MXC_DMA_REQUEST_SPI2RX; + break; + + default: + return E_BAD_PARAM; } return MXC_SPI_RevA1_MasterTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, @@ -343,43 +325,26 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; - case 1: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; + case 1: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; - case 2: - reqselTx = MXC_DMA_REQUEST_SPI2TX; - break; + case 2: + reqselTx = MXC_DMA_REQUEST_SPI2TX; + reqselRx = MXC_DMA_REQUEST_SPI2RX; + break; - default: - return E_BAD_PARAM; - } + default: + return E_BAD_PARAM; } - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; - - case 1: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; - - case 2: - reqselRx = MXC_DMA_REQUEST_SPI2RX; - break; - - default: - return E_BAD_PARAM; - } - } return MXC_SPI_RevA1_SlaveTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, MXC_DMA); } diff --git a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me30.c b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me30.c index ac48b4f2..a98afdde 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me30.c +++ b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me30.c @@ -347,26 +347,14 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req, mxc_dma_regs_t *dma) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPITX; - break; - - default: - return E_BAD_PARAM; - } - } - - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPIRX; - break; + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPITX; + reqselRx = MXC_DMA_REQUEST_SPIRX; + break; - default: - return E_BAD_PARAM; - } + default: + return E_BAD_PARAM; } return MXC_SPI_RevA1_MasterTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, dma); @@ -396,17 +384,6 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req, mxc_dma_regs_t *dma) switch (spi_num) { case 0: reqselTx = MXC_DMA_REQUEST_SPITX; - break; - - default: - return E_BAD_PARAM; - break; - } - } - - if (req->rxData != NULL) { - switch (spi_num) { - case 0: reqselRx = MXC_DMA_REQUEST_SPIRX; break; diff --git a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me55.c b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me55.c index 4254d262..338de200 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me55.c +++ b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me55.c @@ -279,42 +279,24 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; - - case 1: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; - - case 3: - reqselTx = MXC_DMA_REQUEST_SPI3TX; - break; - - default: - return E_BAD_PARAM; - } - } - - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; - - case 1: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; - - case 3: - reqselRx = MXC_DMA_REQUEST_SPI3RX; - break; - - default: - return E_BAD_PARAM; - } + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; + + case 1: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; + + case 3: + reqselTx = MXC_DMA_REQUEST_SPI3TX; + reqselRx = MXC_DMA_REQUEST_SPI3RX; + break; + + default: + return E_BAD_PARAM; } return MXC_SPI_RevA1_MasterTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, @@ -340,42 +322,24 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; - - case 1: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; - - case 3: - reqselTx = MXC_DMA_REQUEST_SPI3TX; - break; + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; - default: - return E_BAD_PARAM; - } - } + case 1: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; + case 3: + reqselTx = MXC_DMA_REQUEST_SPI3TX; + reqselRx = MXC_DMA_REQUEST_SPI3RX; + break; - case 1: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; - - case 3: - reqselRx = MXC_DMA_REQUEST_SPI3RX; - break; - - default: - return E_BAD_PARAM; - } + default: + return E_BAD_PARAM; } return MXC_SPI_RevA1_SlaveTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, diff --git a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_reva1.c b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_reva1.c index 74b8871e..fbe87887 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_reva1.c +++ b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_reva1.c @@ -1007,7 +1007,7 @@ int MXC_SPI_RevA1_MasterTransactionDMA(mxc_spi_reva_req_t *req, int reqselTx, in } //tx - if (req->txData != NULL && !tx_is_complete) { + if (req->txData != NULL && req->txLen && !tx_is_complete) { MXC_DMA_SetCallback(states[spi_num].channelTx, MXC_SPI_RevA1_DMACallback); #if (TARGET_NUM == 32657) @@ -1053,7 +1053,7 @@ int MXC_SPI_RevA1_MasterTransactionDMA(mxc_spi_reva_req_t *req, int reqselTx, in } // rx - if (req->rxData != NULL && !rx_is_complete) { + if (req->rxData != NULL && req->rxLen && !rx_is_complete) { MXC_DMA_SetCallback(states[spi_num].channelRx, MXC_SPI_RevA1_DMACallback); #if (TARGET_NUM == 32657) @@ -1107,11 +1107,11 @@ int MXC_SPI_RevA1_MasterTransactionDMA(mxc_spi_reva_req_t *req, int reqselTx, in } // Manually run TX/RX callbacks if the FIFO pre-load already completed that portion of the transaction - if (tx_is_complete) { + if (req->txData != NULL && req->txLen && tx_is_complete) { MXC_SPI_RevA1_DMACallback(states[spi_num].channelTx, E_NO_ERROR); } - if (rx_is_complete) { + if (req->rxData != NULL && req->rxLen && rx_is_complete) { MXC_SPI_RevA1_DMACallback(states[spi_num].channelRx, E_NO_ERROR); } diff --git a/MAX/Libraries/PeriphDrivers/Source/UART/uart_reva.c b/MAX/Libraries/PeriphDrivers/Source/UART/uart_reva.c index f7ce7d44..35f3b8c6 100644 --- a/MAX/Libraries/PeriphDrivers/Source/UART/uart_reva.c +++ b/MAX/Libraries/PeriphDrivers/Source/UART/uart_reva.c @@ -53,7 +53,17 @@ typedef struct { mxc_dma_regs_t *dma; } uart_reva_req_state_t; -uart_reva_req_state_t states[MXC_UART_INSTANCES]; +// clang-format off +uart_reva_req_state_t states[MXC_UART_INSTANCES] = { + [0 ... MXC_UART_INSTANCES - 1] = { + .tx_req = NULL, + .rx_req = NULL, + .channelTx = -1, + .channelRx = -1, + .auto_dma_handlers = false + } +}; +// clang-format on /* **** Function Prototypes **** */ diff --git a/MAX/Libraries/PeriphDrivers/Source/UART/uart_revb.c b/MAX/Libraries/PeriphDrivers/Source/UART/uart_revb.c index 5e2067eb..84b08201 100644 --- a/MAX/Libraries/PeriphDrivers/Source/UART/uart_revb.c +++ b/MAX/Libraries/PeriphDrivers/Source/UART/uart_revb.c @@ -51,7 +51,17 @@ typedef struct { mxc_dma_regs_t *dma; } uart_revb_req_state_t; -uart_revb_req_state_t states[MXC_UART_INSTANCES]; +// clang-format off +uart_revb_req_state_t states[MXC_UART_INSTANCES] = { + [0 ... MXC_UART_INSTANCES - 1] = { + .tx_req = NULL, + .rx_req = NULL, + .channelTx = -1, + .channelRx = -1, + .auto_dma_handlers = false + } +}; +// clang-format on /* **** Function Prototypes **** */ diff --git a/MAX/Source/MAX32655/CMakeLists.txt b/MAX/Source/MAX32655/CMakeLists.txt index cdc901c7..c78155ea 100644 --- a/MAX/Source/MAX32655/CMakeLists.txt +++ b/MAX/Source/MAX32655/CMakeLists.txt @@ -48,14 +48,18 @@ zephyr_include_directories( ${MSDK_PERIPH_SRC_DIR}/WUT ) +if(CONFIG_ARM) + zephyr_library_sources(${MSDK_CMSIS_DIR}/Source/system_max32655.c) + zephyr_library_sources(${MSDK_PERIPH_SRC_DIR}/SYS/mxc_lock.c) +elseif(CONFIG_RISCV) + zephyr_library_sources(${MSDK_CMSIS_DIR}/Source/system_riscv_max32655.c) +endif() + zephyr_library_sources( ./max32xxx_system.c - ${MSDK_CMSIS_DIR}/Source/system_max32655.c - ${MSDK_PERIPH_SRC_DIR}/SYS/mxc_assert.c ${MSDK_PERIPH_SRC_DIR}/SYS/mxc_delay.c - ${MSDK_PERIPH_SRC_DIR}/SYS/mxc_lock.c ${MSDK_PERIPH_SRC_DIR}/SYS/pins_me17.c ${MSDK_PERIPH_SRC_DIR}/SYS/sys_me17.c diff --git a/MAX/Source/MAX32680/CMakeLists.txt b/MAX/Source/MAX32680/CMakeLists.txt index bcdfad4f..03458b6a 100644 --- a/MAX/Source/MAX32680/CMakeLists.txt +++ b/MAX/Source/MAX32680/CMakeLists.txt @@ -48,14 +48,18 @@ zephyr_include_directories( ${MSDK_PERIPH_SRC_DIR}/WUT ) +if(CONFIG_ARM) + zephyr_library_sources(${MSDK_CMSIS_DIR}/Source/system_max32680.c) + zephyr_library_sources(${MSDK_PERIPH_SRC_DIR}/SYS/mxc_lock.c) +elseif(CONFIG_RISCV) + zephyr_library_sources(${MSDK_CMSIS_DIR}/Source/system_riscv_max32680.c) +endif() + zephyr_library_sources( ./max32xxx_system.c - ${MSDK_CMSIS_DIR}/Source/system_max32680.c - ${MSDK_PERIPH_SRC_DIR}/SYS/mxc_assert.c ${MSDK_PERIPH_SRC_DIR}/SYS/mxc_delay.c - ${MSDK_PERIPH_SRC_DIR}/SYS/mxc_lock.c ${MSDK_PERIPH_SRC_DIR}/SYS/pins_me20.c ${MSDK_PERIPH_SRC_DIR}/SYS/sys_me17.c diff --git a/MAX/Source/MAX32690/CMakeLists.txt b/MAX/Source/MAX32690/CMakeLists.txt index add3ddc5..53afa9fe 100644 --- a/MAX/Source/MAX32690/CMakeLists.txt +++ b/MAX/Source/MAX32690/CMakeLists.txt @@ -51,14 +51,18 @@ zephyr_include_directories( ${MSDK_PERIPH_SRC_DIR}/WUT ) +if(CONFIG_ARM) + zephyr_library_sources(${MSDK_CMSIS_DIR}/Source/system_max32690.c) + zephyr_library_sources(${MSDK_PERIPH_SRC_DIR}/SYS/mxc_lock.c) +elseif(CONFIG_RISCV) + zephyr_library_sources(${MSDK_CMSIS_DIR}/Source/system_riscv_max32690.c) +endif() + zephyr_library_sources( ./max32xxx_system.c - ${MSDK_CMSIS_DIR}/Source/system_max32690.c - ${MSDK_PERIPH_SRC_DIR}/SYS/mxc_assert.c ${MSDK_PERIPH_SRC_DIR}/SYS/mxc_delay.c - ${MSDK_PERIPH_SRC_DIR}/SYS/mxc_lock.c ${MSDK_PERIPH_SRC_DIR}/SYS/pins_me18.c ${MSDK_PERIPH_SRC_DIR}/SYS/sys_me18.c diff --git a/MAX/msdk_sha b/MAX/msdk_sha index da364cc5..dc2208a4 100644 --- a/MAX/msdk_sha +++ b/MAX/msdk_sha @@ -1 +1 @@ -4d53dd087b18b3d3bae5e17e6a5aef2f72077880 +f52582793257054276ab1eaa968662805a2fa003