From c7f3dec7ce8a426a992fa340ef0ec597c0f36601 Mon Sep 17 00:00:00 2001
From: Dirk Wischeropp <dirk.wischeropp@siemens.com>
Date: Wed, 9 Nov 2022 14:50:37 +0100
Subject: [PATCH] AD9371: Fix reset signaling for custom IP Core

---
 CI/scripts/matlab_processors.tcl                     | 3 ++-
 hdl/vendor/AnalogDevices/+AnalogDevices/add_clocks.m | 6 +++---
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/CI/scripts/matlab_processors.tcl b/CI/scripts/matlab_processors.tcl
index 9fa7a823..d2f64881 100644
--- a/CI/scripts/matlab_processors.tcl
+++ b/CI/scripts/matlab_processors.tcl
@@ -446,12 +446,13 @@ proc preprocess_bd {project carrier rxtx} {
                     # Add 1 extra AXI master ports to the interconnect
                     set_property -dict [list CONFIG.NUM_MI {22}] [get_bd_cells axi_cpu_interconnect]
                     #connect_bd_net -net [get_bd_nets axi_adrv9009_rx_clkgen] [get_bd_pins axi_cpu_interconnect/M13_ACLK] [get_bd_pins axi_adrv9009_rx_clkgen/clk_0]
-                    connect_bd_net [get_bd_pins sys_rstgen/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M21_ARESETN]
 
                     if {$rxtx == "rx" || $rxtx == "rxtx"} {
+                        connect_bd_net [get_bd_pins ad9371_rx_device_clk_rstgen/peripheral_aresetn] [get_bd_pins axi_cpu_interconnect/M21_ARESETN]
                         connect_bd_net -net [get_bd_nets axi_ad9371_rx_clkgen] [get_bd_pins axi_cpu_interconnect/M21_ACLK] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]
                     }
                     if {$rxtx == "tx"} {
+                        connect_bd_net [get_bd_pins ad9371_tx_device_clk_rstgen/peripheral_aresetn] [get_bd_pins axi_cpu_interconnect/M21_ARESETN]
                         connect_bd_net -net [get_bd_nets axi_ad9371_tx_clkgen] [get_bd_pins axi_cpu_interconnect/M21_ACLK] [get_bd_pins axi_ad9371_tx_clkgen/clk_0]
                     }
                 }
diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/add_clocks.m b/hdl/vendor/AnalogDevices/+AnalogDevices/add_clocks.m
index 3a039e50..71555943 100644
--- a/hdl/vendor/AnalogDevices/+AnalogDevices/add_clocks.m
+++ b/hdl/vendor/AnalogDevices/+AnalogDevices/add_clocks.m
@@ -66,15 +66,15 @@ function add_clocks(hRD,project,design)
             case 'RX'
                 hRD.addClockInterface( ...
                     'ClockConnection',   'axi_ad9371_rx_clkgen/clk_0', ...
-                    'ResetConnection',   'sys_rstgen/peripheral_aresetn');
+                    'ResetConnection',   'ad9371_rx_device_clk_rstgen/peripheral_aresetn');
             case 'TX'
                 hRD.addClockInterface( ...
                     'ClockConnection',   'axi_ad9371_tx_clkgen/clk_0', ...
-                    'ResetConnection',   'sys_rstgen/peripheral_aresetn');
+                    'ResetConnection',   'ad9371_tx_device_clk_rstgen/peripheral_aresetn');
             case 'RX & TX'
                 hRD.addClockInterface( ...
                     'ClockConnection',   'axi_ad9371_rx_clkgen/clk_0', ...
-                    'ResetConnection',   'sys_rstgen/peripheral_aresetn');
+                    'ResetConnection',   'ad9371_rx_device_clk_rstgen/peripheral_aresetn');
         %     case 'OBS'
         %         hRD.addClockInterface( ...
         %             'ClockConnection',   'axi_adrv9371_rx_os_clkgen/clk_0', ...